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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_ewm.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_EWM_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_EWM_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 EWM
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * External Watchdog Monitor
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_EWM_CTRL - Control Register
mbed_official 324:406fd2029f23 93 * - HW_EWM_SERV - Service Register
mbed_official 324:406fd2029f23 94 * - HW_EWM_CMPL - Compare Low Register
mbed_official 324:406fd2029f23 95 * - HW_EWM_CMPH - Compare High Register
mbed_official 324:406fd2029f23 96 *
mbed_official 324:406fd2029f23 97 * - hw_ewm_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 98 */
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
mbed_official 324:406fd2029f23 101
mbed_official 324:406fd2029f23 102 /*******************************************************************************
mbed_official 324:406fd2029f23 103 * HW_EWM_CTRL - Control Register
mbed_official 324:406fd2029f23 104 ******************************************************************************/
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 /*!
mbed_official 324:406fd2029f23 107 * @brief HW_EWM_CTRL - Control Register (RW)
mbed_official 324:406fd2029f23 108 *
mbed_official 324:406fd2029f23 109 * Reset value: 0x00U
mbed_official 324:406fd2029f23 110 *
mbed_official 324:406fd2029f23 111 * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
mbed_official 324:406fd2029f23 112 * written once after a CPU reset. Modifying these bits more than once, generates
mbed_official 324:406fd2029f23 113 * a bus transfer error.
mbed_official 324:406fd2029f23 114 */
mbed_official 324:406fd2029f23 115 typedef union _hw_ewm_ctrl
mbed_official 324:406fd2029f23 116 {
mbed_official 324:406fd2029f23 117 uint8_t U;
mbed_official 324:406fd2029f23 118 struct _hw_ewm_ctrl_bitfields
mbed_official 324:406fd2029f23 119 {
mbed_official 324:406fd2029f23 120 uint8_t EWMEN : 1; /*!< [0] EWM enable. */
mbed_official 324:406fd2029f23 121 uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */
mbed_official 324:406fd2029f23 122 uint8_t INEN : 1; /*!< [2] Input Enable. */
mbed_official 324:406fd2029f23 123 uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */
mbed_official 324:406fd2029f23 124 uint8_t RESERVED0 : 4; /*!< [7:4] */
mbed_official 324:406fd2029f23 125 } B;
mbed_official 324:406fd2029f23 126 } hw_ewm_ctrl_t;
mbed_official 324:406fd2029f23 127
mbed_official 324:406fd2029f23 128 /*!
mbed_official 324:406fd2029f23 129 * @name Constants and macros for entire EWM_CTRL register
mbed_official 324:406fd2029f23 130 */
mbed_official 324:406fd2029f23 131 /*@{*/
mbed_official 324:406fd2029f23 132 #define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 133
mbed_official 324:406fd2029f23 134 #define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
mbed_official 324:406fd2029f23 135 #define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U)
mbed_official 324:406fd2029f23 136 #define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v))
mbed_official 324:406fd2029f23 137 #define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 138 #define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 139 #define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 140 /*@}*/
mbed_official 324:406fd2029f23 141
mbed_official 324:406fd2029f23 142 /*
mbed_official 324:406fd2029f23 143 * Constants & macros for individual EWM_CTRL bitfields
mbed_official 324:406fd2029f23 144 */
mbed_official 324:406fd2029f23 145
mbed_official 324:406fd2029f23 146 /*!
mbed_official 324:406fd2029f23 147 * @name Register EWM_CTRL, field EWMEN[0] (RW)
mbed_official 324:406fd2029f23 148 *
mbed_official 324:406fd2029f23 149 * This bit when set, enables the EWM module. This resets the EWM counter to
mbed_official 324:406fd2029f23 150 * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
mbed_official 324:406fd2029f23 151 * therefore it cannot be enabled until a reset occurs, due to the write-once
mbed_official 324:406fd2029f23 152 * nature of this bit.
mbed_official 324:406fd2029f23 153 */
mbed_official 324:406fd2029f23 154 /*@{*/
mbed_official 324:406fd2029f23 155 #define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 156 #define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 157 #define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 158
mbed_official 324:406fd2029f23 159 /*! @brief Read current value of the EWM_CTRL_EWMEN field. */
mbed_official 324:406fd2029f23 160 #define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
mbed_official 324:406fd2029f23 161
mbed_official 324:406fd2029f23 162 /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 163 #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
mbed_official 324:406fd2029f23 164
mbed_official 324:406fd2029f23 165 /*! @brief Set the EWMEN field to a new value. */
mbed_official 324:406fd2029f23 166 #define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
mbed_official 324:406fd2029f23 167 /*@}*/
mbed_official 324:406fd2029f23 168
mbed_official 324:406fd2029f23 169 /*!
mbed_official 324:406fd2029f23 170 * @name Register EWM_CTRL, field ASSIN[1] (RW)
mbed_official 324:406fd2029f23 171 *
mbed_official 324:406fd2029f23 172 * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
mbed_official 324:406fd2029f23 173 * inverts the assert state to a logic one.
mbed_official 324:406fd2029f23 174 */
mbed_official 324:406fd2029f23 175 /*@{*/
mbed_official 324:406fd2029f23 176 #define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 177 #define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 178 #define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 179
mbed_official 324:406fd2029f23 180 /*! @brief Read current value of the EWM_CTRL_ASSIN field. */
mbed_official 324:406fd2029f23 181 #define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
mbed_official 324:406fd2029f23 182
mbed_official 324:406fd2029f23 183 /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 184 #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
mbed_official 324:406fd2029f23 185
mbed_official 324:406fd2029f23 186 /*! @brief Set the ASSIN field to a new value. */
mbed_official 324:406fd2029f23 187 #define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
mbed_official 324:406fd2029f23 188 /*@}*/
mbed_official 324:406fd2029f23 189
mbed_official 324:406fd2029f23 190 /*!
mbed_official 324:406fd2029f23 191 * @name Register EWM_CTRL, field INEN[2] (RW)
mbed_official 324:406fd2029f23 192 *
mbed_official 324:406fd2029f23 193 * This bit when set, enables the EWM_in port.
mbed_official 324:406fd2029f23 194 */
mbed_official 324:406fd2029f23 195 /*@{*/
mbed_official 324:406fd2029f23 196 #define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 197 #define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 198 #define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 199
mbed_official 324:406fd2029f23 200 /*! @brief Read current value of the EWM_CTRL_INEN field. */
mbed_official 324:406fd2029f23 201 #define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
mbed_official 324:406fd2029f23 202
mbed_official 324:406fd2029f23 203 /*! @brief Format value for bitfield EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 204 #define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
mbed_official 324:406fd2029f23 205
mbed_official 324:406fd2029f23 206 /*! @brief Set the INEN field to a new value. */
mbed_official 324:406fd2029f23 207 #define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
mbed_official 324:406fd2029f23 208 /*@}*/
mbed_official 324:406fd2029f23 209
mbed_official 324:406fd2029f23 210 /*!
mbed_official 324:406fd2029f23 211 * @name Register EWM_CTRL, field INTEN[3] (RW)
mbed_official 324:406fd2029f23 212 *
mbed_official 324:406fd2029f23 213 * This bit when set and EWM_out is asserted, an interrupt request is generated.
mbed_official 324:406fd2029f23 214 * To de-assert interrupt request, user should clear this bit by writing 0.
mbed_official 324:406fd2029f23 215 */
mbed_official 324:406fd2029f23 216 /*@{*/
mbed_official 324:406fd2029f23 217 #define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 218 #define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 219 #define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 220
mbed_official 324:406fd2029f23 221 /*! @brief Read current value of the EWM_CTRL_INTEN field. */
mbed_official 324:406fd2029f23 222 #define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
mbed_official 324:406fd2029f23 223
mbed_official 324:406fd2029f23 224 /*! @brief Format value for bitfield EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 225 #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
mbed_official 324:406fd2029f23 226
mbed_official 324:406fd2029f23 227 /*! @brief Set the INTEN field to a new value. */
mbed_official 324:406fd2029f23 228 #define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
mbed_official 324:406fd2029f23 229 /*@}*/
mbed_official 324:406fd2029f23 230
mbed_official 324:406fd2029f23 231 /*******************************************************************************
mbed_official 324:406fd2029f23 232 * HW_EWM_SERV - Service Register
mbed_official 324:406fd2029f23 233 ******************************************************************************/
mbed_official 324:406fd2029f23 234
mbed_official 324:406fd2029f23 235 /*!
mbed_official 324:406fd2029f23 236 * @brief HW_EWM_SERV - Service Register (WORZ)
mbed_official 324:406fd2029f23 237 *
mbed_official 324:406fd2029f23 238 * Reset value: 0x00U
mbed_official 324:406fd2029f23 239 *
mbed_official 324:406fd2029f23 240 * The SERV register provides the interface from the CPU to the EWM module. It
mbed_official 324:406fd2029f23 241 * is write-only and reads of this register return zero.
mbed_official 324:406fd2029f23 242 */
mbed_official 324:406fd2029f23 243 typedef union _hw_ewm_serv
mbed_official 324:406fd2029f23 244 {
mbed_official 324:406fd2029f23 245 uint8_t U;
mbed_official 324:406fd2029f23 246 struct _hw_ewm_serv_bitfields
mbed_official 324:406fd2029f23 247 {
mbed_official 324:406fd2029f23 248 uint8_t SERVICE : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 249 } B;
mbed_official 324:406fd2029f23 250 } hw_ewm_serv_t;
mbed_official 324:406fd2029f23 251
mbed_official 324:406fd2029f23 252 /*!
mbed_official 324:406fd2029f23 253 * @name Constants and macros for entire EWM_SERV register
mbed_official 324:406fd2029f23 254 */
mbed_official 324:406fd2029f23 255 /*@{*/
mbed_official 324:406fd2029f23 256 #define HW_EWM_SERV_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 #define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
mbed_official 324:406fd2029f23 259 #define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U)
mbed_official 324:406fd2029f23 260 #define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v))
mbed_official 324:406fd2029f23 261 /*@}*/
mbed_official 324:406fd2029f23 262
mbed_official 324:406fd2029f23 263 /*
mbed_official 324:406fd2029f23 264 * Constants & macros for individual EWM_SERV bitfields
mbed_official 324:406fd2029f23 265 */
mbed_official 324:406fd2029f23 266
mbed_official 324:406fd2029f23 267 /*!
mbed_official 324:406fd2029f23 268 * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
mbed_official 324:406fd2029f23 269 *
mbed_official 324:406fd2029f23 270 * The EWM service mechanism requires the CPU to write two values to the SERV
mbed_official 324:406fd2029f23 271 * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
mbed_official 324:406fd2029f23 272 * EWM service is illegal if either of the following conditions is true. The
mbed_official 324:406fd2029f23 273 * first or second data byte is not written correctly. The second data byte is not
mbed_official 324:406fd2029f23 274 * written within a fixed number of peripheral bus cycles of the first data byte.
mbed_official 324:406fd2029f23 275 * This fixed number of cycles is called EWM_service_time.
mbed_official 324:406fd2029f23 276 */
mbed_official 324:406fd2029f23 277 /*@{*/
mbed_official 324:406fd2029f23 278 #define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 279 #define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 280 #define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 281
mbed_official 324:406fd2029f23 282 /*! @brief Format value for bitfield EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 283 #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*! @brief Set the SERVICE field to a new value. */
mbed_official 324:406fd2029f23 286 #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
mbed_official 324:406fd2029f23 287 /*@}*/
mbed_official 324:406fd2029f23 288
mbed_official 324:406fd2029f23 289 /*******************************************************************************
mbed_official 324:406fd2029f23 290 * HW_EWM_CMPL - Compare Low Register
mbed_official 324:406fd2029f23 291 ******************************************************************************/
mbed_official 324:406fd2029f23 292
mbed_official 324:406fd2029f23 293 /*!
mbed_official 324:406fd2029f23 294 * @brief HW_EWM_CMPL - Compare Low Register (RW)
mbed_official 324:406fd2029f23 295 *
mbed_official 324:406fd2029f23 296 * Reset value: 0x00U
mbed_official 324:406fd2029f23 297 *
mbed_official 324:406fd2029f23 298 * The CMPL register is reset to zero after a CPU reset. This provides no
mbed_official 324:406fd2029f23 299 * minimum time for the CPU to service the EWM counter. This register can be written
mbed_official 324:406fd2029f23 300 * only once after a CPU reset. Writing this register more than once generates a
mbed_official 324:406fd2029f23 301 * bus transfer error.
mbed_official 324:406fd2029f23 302 */
mbed_official 324:406fd2029f23 303 typedef union _hw_ewm_cmpl
mbed_official 324:406fd2029f23 304 {
mbed_official 324:406fd2029f23 305 uint8_t U;
mbed_official 324:406fd2029f23 306 struct _hw_ewm_cmpl_bitfields
mbed_official 324:406fd2029f23 307 {
mbed_official 324:406fd2029f23 308 uint8_t COMPAREL : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 309 } B;
mbed_official 324:406fd2029f23 310 } hw_ewm_cmpl_t;
mbed_official 324:406fd2029f23 311
mbed_official 324:406fd2029f23 312 /*!
mbed_official 324:406fd2029f23 313 * @name Constants and macros for entire EWM_CMPL register
mbed_official 324:406fd2029f23 314 */
mbed_official 324:406fd2029f23 315 /*@{*/
mbed_official 324:406fd2029f23 316 #define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 317
mbed_official 324:406fd2029f23 318 #define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
mbed_official 324:406fd2029f23 319 #define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U)
mbed_official 324:406fd2029f23 320 #define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v))
mbed_official 324:406fd2029f23 321 #define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v)))
mbed_official 324:406fd2029f23 322 #define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 323 #define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 324 /*@}*/
mbed_official 324:406fd2029f23 325
mbed_official 324:406fd2029f23 326 /*
mbed_official 324:406fd2029f23 327 * Constants & macros for individual EWM_CMPL bitfields
mbed_official 324:406fd2029f23 328 */
mbed_official 324:406fd2029f23 329
mbed_official 324:406fd2029f23 330 /*!
mbed_official 324:406fd2029f23 331 * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
mbed_official 324:406fd2029f23 332 *
mbed_official 324:406fd2029f23 333 * To prevent runaway code from changing this field, software should write to
mbed_official 324:406fd2029f23 334 * this field after a CPU reset even if the (default) minimum service time is
mbed_official 324:406fd2029f23 335 * required.
mbed_official 324:406fd2029f23 336 */
mbed_official 324:406fd2029f23 337 /*@{*/
mbed_official 324:406fd2029f23 338 #define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 339 #define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 340 #define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 341
mbed_official 324:406fd2029f23 342 /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
mbed_official 324:406fd2029f23 343 #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
mbed_official 324:406fd2029f23 344
mbed_official 324:406fd2029f23 345 /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 346 #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
mbed_official 324:406fd2029f23 347
mbed_official 324:406fd2029f23 348 /*! @brief Set the COMPAREL field to a new value. */
mbed_official 324:406fd2029f23 349 #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
mbed_official 324:406fd2029f23 350 /*@}*/
mbed_official 324:406fd2029f23 351
mbed_official 324:406fd2029f23 352 /*******************************************************************************
mbed_official 324:406fd2029f23 353 * HW_EWM_CMPH - Compare High Register
mbed_official 324:406fd2029f23 354 ******************************************************************************/
mbed_official 324:406fd2029f23 355
mbed_official 324:406fd2029f23 356 /*!
mbed_official 324:406fd2029f23 357 * @brief HW_EWM_CMPH - Compare High Register (RW)
mbed_official 324:406fd2029f23 358 *
mbed_official 324:406fd2029f23 359 * Reset value: 0xFFU
mbed_official 324:406fd2029f23 360 *
mbed_official 324:406fd2029f23 361 * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
mbed_official 324:406fd2029f23 362 * of 256 clocks time, for the CPU to service the EWM counter. This register can
mbed_official 324:406fd2029f23 363 * be written only once after a CPU reset. Writing this register more than once
mbed_official 324:406fd2029f23 364 * generates a bus transfer error. The valid values for CMPH are up to 0xFE
mbed_official 324:406fd2029f23 365 * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
mbed_official 324:406fd2029f23 366 * if EWM counter is greater than CMPH.
mbed_official 324:406fd2029f23 367 */
mbed_official 324:406fd2029f23 368 typedef union _hw_ewm_cmph
mbed_official 324:406fd2029f23 369 {
mbed_official 324:406fd2029f23 370 uint8_t U;
mbed_official 324:406fd2029f23 371 struct _hw_ewm_cmph_bitfields
mbed_official 324:406fd2029f23 372 {
mbed_official 324:406fd2029f23 373 uint8_t COMPAREH : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 374 } B;
mbed_official 324:406fd2029f23 375 } hw_ewm_cmph_t;
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*!
mbed_official 324:406fd2029f23 378 * @name Constants and macros for entire EWM_CMPH register
mbed_official 324:406fd2029f23 379 */
mbed_official 324:406fd2029f23 380 /*@{*/
mbed_official 324:406fd2029f23 381 #define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 382
mbed_official 324:406fd2029f23 383 #define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
mbed_official 324:406fd2029f23 384 #define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U)
mbed_official 324:406fd2029f23 385 #define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v))
mbed_official 324:406fd2029f23 386 #define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v)))
mbed_official 324:406fd2029f23 387 #define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 388 #define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 389 /*@}*/
mbed_official 324:406fd2029f23 390
mbed_official 324:406fd2029f23 391 /*
mbed_official 324:406fd2029f23 392 * Constants & macros for individual EWM_CMPH bitfields
mbed_official 324:406fd2029f23 393 */
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395 /*!
mbed_official 324:406fd2029f23 396 * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
mbed_official 324:406fd2029f23 397 *
mbed_official 324:406fd2029f23 398 * To prevent runaway code from changing this field, software should write to
mbed_official 324:406fd2029f23 399 * this field after a CPU reset even if the (default) maximum service time is
mbed_official 324:406fd2029f23 400 * required.
mbed_official 324:406fd2029f23 401 */
mbed_official 324:406fd2029f23 402 /*@{*/
mbed_official 324:406fd2029f23 403 #define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 404 #define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 405 #define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 406
mbed_official 324:406fd2029f23 407 /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
mbed_official 324:406fd2029f23 408 #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
mbed_official 324:406fd2029f23 409
mbed_official 324:406fd2029f23 410 /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 411 #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
mbed_official 324:406fd2029f23 412
mbed_official 324:406fd2029f23 413 /*! @brief Set the COMPAREH field to a new value. */
mbed_official 324:406fd2029f23 414 #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
mbed_official 324:406fd2029f23 415 /*@}*/
mbed_official 324:406fd2029f23 416
mbed_official 324:406fd2029f23 417 /*******************************************************************************
mbed_official 324:406fd2029f23 418 * hw_ewm_t - module struct
mbed_official 324:406fd2029f23 419 ******************************************************************************/
mbed_official 324:406fd2029f23 420 /*!
mbed_official 324:406fd2029f23 421 * @brief All EWM module registers.
mbed_official 324:406fd2029f23 422 */
mbed_official 324:406fd2029f23 423 #pragma pack(1)
mbed_official 324:406fd2029f23 424 typedef struct _hw_ewm
mbed_official 324:406fd2029f23 425 {
mbed_official 324:406fd2029f23 426 __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */
mbed_official 324:406fd2029f23 427 __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */
mbed_official 324:406fd2029f23 428 __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */
mbed_official 324:406fd2029f23 429 __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */
mbed_official 324:406fd2029f23 430 } hw_ewm_t;
mbed_official 324:406fd2029f23 431 #pragma pack()
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Macro to access all EWM registers. */
mbed_official 324:406fd2029f23 434 /*! @param x EWM module instance base address. */
mbed_official 324:406fd2029f23 435 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 436 * use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
mbed_official 324:406fd2029f23 437 #define HW_EWM(x) (*(hw_ewm_t *)(x))
mbed_official 324:406fd2029f23 438
mbed_official 324:406fd2029f23 439 #endif /* __HW_EWM_REGISTERS_H__ */
mbed_official 324:406fd2029f23 440 /* EOF */