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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_crc.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_CRC_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_CRC_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 CRC
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Cyclic Redundancy Check
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_CRC_DATAL - CRC_DATAL register.
mbed_official	324:406fd2029f23	93	* - HW_CRC_DATAH - CRC_DATAH register.
mbed_official	324:406fd2029f23	94	* - HW_CRC_DATALL - CRC_DATALL register.
mbed_official	324:406fd2029f23	95	* - HW_CRC_DATALU - CRC_DATALU register.
mbed_official	324:406fd2029f23	96	* - HW_CRC_DATAHL - CRC_DATAHL register.
mbed_official	324:406fd2029f23	97	* - HW_CRC_DATAHU - CRC_DATAHU register.
mbed_official	324:406fd2029f23	98	* - HW_CRC_DATA - CRC Data register
mbed_official	324:406fd2029f23	99	* - HW_CRC_GPOLY - CRC Polynomial register
mbed_official	324:406fd2029f23	100	* - HW_CRC_GPOLYL - CRC_GPOLYL register.
mbed_official	324:406fd2029f23	101	* - HW_CRC_GPOLYH - CRC_GPOLYH register.
mbed_official	324:406fd2029f23	102	* - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
mbed_official	324:406fd2029f23	103	* - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
mbed_official	324:406fd2029f23	104	* - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
mbed_official	324:406fd2029f23	105	* - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
mbed_official	324:406fd2029f23	106	* - HW_CRC_CTRL - CRC Control register
mbed_official	324:406fd2029f23	107	* - HW_CRC_CTRLHU - CRC_CTRLHU register.
mbed_official	324:406fd2029f23	108	*
mbed_official	324:406fd2029f23	109	* - hw_crc_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	110	*/
mbed_official	324:406fd2029f23	111
mbed_official	324:406fd2029f23	112	#define HW_CRC_INSTANCE_COUNT (1U) /!< Number of instances of the CRC module. /
mbed_official	324:406fd2029f23	113
mbed_official	324:406fd2029f23	114	/*******************************************************************************
mbed_official	324:406fd2029f23	115	* HW_CRC_DATAL - CRC_DATAL register.
mbed_official	324:406fd2029f23	116	******************************************************************************/
mbed_official	324:406fd2029f23	117
mbed_official	324:406fd2029f23	118	/*!
mbed_official	324:406fd2029f23	119	* @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
mbed_official	324:406fd2029f23	120	*
mbed_official	324:406fd2029f23	121	* Reset value: 0xFFFFU
mbed_official	324:406fd2029f23	122	*/
mbed_official	324:406fd2029f23	123	typedef union _hw_crc_datal
mbed_official	324:406fd2029f23	124	{
mbed_official	324:406fd2029f23	125	uint16_t U;
mbed_official	324:406fd2029f23	126	struct _hw_crc_datal_bitfields
mbed_official	324:406fd2029f23	127	{
mbed_official	324:406fd2029f23	128	uint16_t DATAL : 16; /*!< [15:0] DATAL stores the lower 16 bits of
mbed_official	324:406fd2029f23	129	* the 16/32 bit CRC */
mbed_official	324:406fd2029f23	130	} B;
mbed_official	324:406fd2029f23	131	} hw_crc_datal_t;
mbed_official	324:406fd2029f23	132
mbed_official	324:406fd2029f23	133	/*!
mbed_official	324:406fd2029f23	134	* @name Constants and macros for entire CRC_DATAL register
mbed_official	324:406fd2029f23	135	*/
mbed_official	324:406fd2029f23	136	/@{/
mbed_official	324:406fd2029f23	137	#define HW_CRC_DATAL_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	138
mbed_official	324:406fd2029f23	139	#define HW_CRC_DATAL(x) ((__IO hw_crc_datal_t ) HW_CRC_DATAL_ADDR(x))
mbed_official	324:406fd2029f23	140	#define HW_CRC_DATAL_RD(x) (HW_CRC_DATAL(x).U)
mbed_official	324:406fd2029f23	141	#define HW_CRC_DATAL_WR(x, v) (HW_CRC_DATAL(x).U = (v))
mbed_official	324:406fd2029f23	142	#define HW_CRC_DATAL_SET(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	143	#define HW_CRC_DATAL_CLR(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	144	#define HW_CRC_DATAL_TOG(x, v) (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	145	/@}/
mbed_official	324:406fd2029f23	146
mbed_official	324:406fd2029f23	147	/*
mbed_official	324:406fd2029f23	148	* Constants & macros for individual CRC_DATAL bitfields
mbed_official	324:406fd2029f23	149	*/
mbed_official	324:406fd2029f23	150
mbed_official	324:406fd2029f23	151	/*!
mbed_official	324:406fd2029f23	152	* @name Register CRC_DATAL, field DATAL[15:0] (RW)
mbed_official	324:406fd2029f23	153	*/
mbed_official	324:406fd2029f23	154	/@{/
mbed_official	324:406fd2029f23	155	#define BP_CRC_DATAL_DATAL (0U) /!< Bit position for CRC_DATAL_DATAL. /
mbed_official	324:406fd2029f23	156	#define BM_CRC_DATAL_DATAL (0xFFFFU) /!< Bit mask for CRC_DATAL_DATAL. /
mbed_official	324:406fd2029f23	157	#define BS_CRC_DATAL_DATAL (16U) /!< Bit field size in bits for CRC_DATAL_DATAL. /
mbed_official	324:406fd2029f23	158
mbed_official	324:406fd2029f23	159	/! @brief Read current value of the CRC_DATAL_DATAL field. /
mbed_official	324:406fd2029f23	160	#define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U)
mbed_official	324:406fd2029f23	161
mbed_official	324:406fd2029f23	162	/! @brief Format value for bitfield CRC_DATAL_DATAL. /
mbed_official	324:406fd2029f23	163	#define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL)
mbed_official	324:406fd2029f23	164
mbed_official	324:406fd2029f23	165	/! @brief Set the DATAL field to a new value. /
mbed_official	324:406fd2029f23	166	#define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v))
mbed_official	324:406fd2029f23	167	/@}/
mbed_official	324:406fd2029f23	168	/*******************************************************************************
mbed_official	324:406fd2029f23	169	* HW_CRC_DATAH - CRC_DATAH register.
mbed_official	324:406fd2029f23	170	******************************************************************************/
mbed_official	324:406fd2029f23	171
mbed_official	324:406fd2029f23	172	/*!
mbed_official	324:406fd2029f23	173	* @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
mbed_official	324:406fd2029f23	174	*
mbed_official	324:406fd2029f23	175	* Reset value: 0xFFFFU
mbed_official	324:406fd2029f23	176	*/
mbed_official	324:406fd2029f23	177	typedef union _hw_crc_datah
mbed_official	324:406fd2029f23	178	{
mbed_official	324:406fd2029f23	179	uint16_t U;
mbed_official	324:406fd2029f23	180	struct _hw_crc_datah_bitfields
mbed_official	324:406fd2029f23	181	{
mbed_official	324:406fd2029f23	182	uint16_t DATAH : 16; /*!< [15:0] DATAH stores the high 16 bits of the
mbed_official	324:406fd2029f23	183	* 16/32 bit CRC */
mbed_official	324:406fd2029f23	184	} B;
mbed_official	324:406fd2029f23	185	} hw_crc_datah_t;
mbed_official	324:406fd2029f23	186
mbed_official	324:406fd2029f23	187	/*!
mbed_official	324:406fd2029f23	188	* @name Constants and macros for entire CRC_DATAH register
mbed_official	324:406fd2029f23	189	*/
mbed_official	324:406fd2029f23	190	/@{/
mbed_official	324:406fd2029f23	191	#define HW_CRC_DATAH_ADDR(x) ((x) + 0x2U)
mbed_official	324:406fd2029f23	192
mbed_official	324:406fd2029f23	193	#define HW_CRC_DATAH(x) ((__IO hw_crc_datah_t ) HW_CRC_DATAH_ADDR(x))
mbed_official	324:406fd2029f23	194	#define HW_CRC_DATAH_RD(x) (HW_CRC_DATAH(x).U)
mbed_official	324:406fd2029f23	195	#define HW_CRC_DATAH_WR(x, v) (HW_CRC_DATAH(x).U = (v))
mbed_official	324:406fd2029f23	196	#define HW_CRC_DATAH_SET(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	197	#define HW_CRC_DATAH_CLR(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	198	#define HW_CRC_DATAH_TOG(x, v) (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	199	/@}/
mbed_official	324:406fd2029f23	200
mbed_official	324:406fd2029f23	201	/*
mbed_official	324:406fd2029f23	202	* Constants & macros for individual CRC_DATAH bitfields
mbed_official	324:406fd2029f23	203	*/
mbed_official	324:406fd2029f23	204
mbed_official	324:406fd2029f23	205	/*!
mbed_official	324:406fd2029f23	206	* @name Register CRC_DATAH, field DATAH[15:0] (RW)
mbed_official	324:406fd2029f23	207	*/
mbed_official	324:406fd2029f23	208	/@{/
mbed_official	324:406fd2029f23	209	#define BP_CRC_DATAH_DATAH (0U) /!< Bit position for CRC_DATAH_DATAH. /
mbed_official	324:406fd2029f23	210	#define BM_CRC_DATAH_DATAH (0xFFFFU) /!< Bit mask for CRC_DATAH_DATAH. /
mbed_official	324:406fd2029f23	211	#define BS_CRC_DATAH_DATAH (16U) /!< Bit field size in bits for CRC_DATAH_DATAH. /
mbed_official	324:406fd2029f23	212
mbed_official	324:406fd2029f23	213	/! @brief Read current value of the CRC_DATAH_DATAH field. /
mbed_official	324:406fd2029f23	214	#define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U)
mbed_official	324:406fd2029f23	215
mbed_official	324:406fd2029f23	216	/! @brief Format value for bitfield CRC_DATAH_DATAH. /
mbed_official	324:406fd2029f23	217	#define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH)
mbed_official	324:406fd2029f23	218
mbed_official	324:406fd2029f23	219	/! @brief Set the DATAH field to a new value. /
mbed_official	324:406fd2029f23	220	#define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v))
mbed_official	324:406fd2029f23	221	/@}/
mbed_official	324:406fd2029f23	222	/*******************************************************************************
mbed_official	324:406fd2029f23	223	* HW_CRC_DATALL - CRC_DATALL register.
mbed_official	324:406fd2029f23	224	******************************************************************************/
mbed_official	324:406fd2029f23	225
mbed_official	324:406fd2029f23	226	/*!
mbed_official	324:406fd2029f23	227	* @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
mbed_official	324:406fd2029f23	228	*
mbed_official	324:406fd2029f23	229	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	230	*/
mbed_official	324:406fd2029f23	231	typedef union _hw_crc_datall
mbed_official	324:406fd2029f23	232	{
mbed_official	324:406fd2029f23	233	uint8_t U;
mbed_official	324:406fd2029f23	234	struct _hw_crc_datall_bitfields
mbed_official	324:406fd2029f23	235	{
mbed_official	324:406fd2029f23	236	uint8_t DATALL : 8; /*!< [7:0] CRCLL stores the first 8 bits of the
mbed_official	324:406fd2029f23	237	* 32 bit DATA */
mbed_official	324:406fd2029f23	238	} B;
mbed_official	324:406fd2029f23	239	} hw_crc_datall_t;
mbed_official	324:406fd2029f23	240
mbed_official	324:406fd2029f23	241	/*!
mbed_official	324:406fd2029f23	242	* @name Constants and macros for entire CRC_DATALL register
mbed_official	324:406fd2029f23	243	*/
mbed_official	324:406fd2029f23	244	/@{/
mbed_official	324:406fd2029f23	245	#define HW_CRC_DATALL_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	246
mbed_official	324:406fd2029f23	247	#define HW_CRC_DATALL(x) ((__IO hw_crc_datall_t ) HW_CRC_DATALL_ADDR(x))
mbed_official	324:406fd2029f23	248	#define HW_CRC_DATALL_RD(x) (HW_CRC_DATALL(x).U)
mbed_official	324:406fd2029f23	249	#define HW_CRC_DATALL_WR(x, v) (HW_CRC_DATALL(x).U = (v))
mbed_official	324:406fd2029f23	250	#define HW_CRC_DATALL_SET(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	251	#define HW_CRC_DATALL_CLR(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	252	#define HW_CRC_DATALL_TOG(x, v) (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	253	/@}/
mbed_official	324:406fd2029f23	254
mbed_official	324:406fd2029f23	255	/*
mbed_official	324:406fd2029f23	256	* Constants & macros for individual CRC_DATALL bitfields
mbed_official	324:406fd2029f23	257	*/
mbed_official	324:406fd2029f23	258
mbed_official	324:406fd2029f23	259	/*!
mbed_official	324:406fd2029f23	260	* @name Register CRC_DATALL, field DATALL[7:0] (RW)
mbed_official	324:406fd2029f23	261	*/
mbed_official	324:406fd2029f23	262	/@{/
mbed_official	324:406fd2029f23	263	#define BP_CRC_DATALL_DATALL (0U) /!< Bit position for CRC_DATALL_DATALL. /
mbed_official	324:406fd2029f23	264	#define BM_CRC_DATALL_DATALL (0xFFU) /!< Bit mask for CRC_DATALL_DATALL. /
mbed_official	324:406fd2029f23	265	#define BS_CRC_DATALL_DATALL (8U) /!< Bit field size in bits for CRC_DATALL_DATALL. /
mbed_official	324:406fd2029f23	266
mbed_official	324:406fd2029f23	267	/! @brief Read current value of the CRC_DATALL_DATALL field. /
mbed_official	324:406fd2029f23	268	#define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U)
mbed_official	324:406fd2029f23	269
mbed_official	324:406fd2029f23	270	/! @brief Format value for bitfield CRC_DATALL_DATALL. /
mbed_official	324:406fd2029f23	271	#define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL)
mbed_official	324:406fd2029f23	272
mbed_official	324:406fd2029f23	273	/! @brief Set the DATALL field to a new value. /
mbed_official	324:406fd2029f23	274	#define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v))
mbed_official	324:406fd2029f23	275	/@}/
mbed_official	324:406fd2029f23	276	/*******************************************************************************
mbed_official	324:406fd2029f23	277	* HW_CRC_DATALU - CRC_DATALU register.
mbed_official	324:406fd2029f23	278	******************************************************************************/
mbed_official	324:406fd2029f23	279
mbed_official	324:406fd2029f23	280	/*!
mbed_official	324:406fd2029f23	281	* @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
mbed_official	324:406fd2029f23	282	*
mbed_official	324:406fd2029f23	283	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	284	*/
mbed_official	324:406fd2029f23	285	typedef union _hw_crc_datalu
mbed_official	324:406fd2029f23	286	{
mbed_official	324:406fd2029f23	287	uint8_t U;
mbed_official	324:406fd2029f23	288	struct _hw_crc_datalu_bitfields
mbed_official	324:406fd2029f23	289	{
mbed_official	324:406fd2029f23	290	uint8_t DATALU : 8; /*!< [7:0] DATALL stores the second 8 bits of the
mbed_official	324:406fd2029f23	291	* 32 bit CRC */
mbed_official	324:406fd2029f23	292	} B;
mbed_official	324:406fd2029f23	293	} hw_crc_datalu_t;
mbed_official	324:406fd2029f23	294
mbed_official	324:406fd2029f23	295	/*!
mbed_official	324:406fd2029f23	296	* @name Constants and macros for entire CRC_DATALU register
mbed_official	324:406fd2029f23	297	*/
mbed_official	324:406fd2029f23	298	/@{/
mbed_official	324:406fd2029f23	299	#define HW_CRC_DATALU_ADDR(x) ((x) + 0x1U)
mbed_official	324:406fd2029f23	300
mbed_official	324:406fd2029f23	301	#define HW_CRC_DATALU(x) ((__IO hw_crc_datalu_t ) HW_CRC_DATALU_ADDR(x))
mbed_official	324:406fd2029f23	302	#define HW_CRC_DATALU_RD(x) (HW_CRC_DATALU(x).U)
mbed_official	324:406fd2029f23	303	#define HW_CRC_DATALU_WR(x, v) (HW_CRC_DATALU(x).U = (v))
mbed_official	324:406fd2029f23	304	#define HW_CRC_DATALU_SET(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) \| (v)))
mbed_official	324:406fd2029f23	305	#define HW_CRC_DATALU_CLR(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	306	#define HW_CRC_DATALU_TOG(x, v) (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	307	/@}/
mbed_official	324:406fd2029f23	308
mbed_official	324:406fd2029f23	309	/*
mbed_official	324:406fd2029f23	310	* Constants & macros for individual CRC_DATALU bitfields
mbed_official	324:406fd2029f23	311	*/
mbed_official	324:406fd2029f23	312
mbed_official	324:406fd2029f23	313	/*!
mbed_official	324:406fd2029f23	314	* @name Register CRC_DATALU, field DATALU[7:0] (RW)
mbed_official	324:406fd2029f23	315	*/
mbed_official	324:406fd2029f23	316	/@{/
mbed_official	324:406fd2029f23	317	#define BP_CRC_DATALU_DATALU (0U) /!< Bit position for CRC_DATALU_DATALU. /
mbed_official	324:406fd2029f23	318	#define BM_CRC_DATALU_DATALU (0xFFU) /!< Bit mask for CRC_DATALU_DATALU. /
mbed_official	324:406fd2029f23	319	#define BS_CRC_DATALU_DATALU (8U) /!< Bit field size in bits for CRC_DATALU_DATALU. /
mbed_official	324:406fd2029f23	320
mbed_official	324:406fd2029f23	321	/! @brief Read current value of the CRC_DATALU_DATALU field. /
mbed_official	324:406fd2029f23	322	#define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U)
mbed_official	324:406fd2029f23	323
mbed_official	324:406fd2029f23	324	/! @brief Format value for bitfield CRC_DATALU_DATALU. /
mbed_official	324:406fd2029f23	325	#define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU)
mbed_official	324:406fd2029f23	326
mbed_official	324:406fd2029f23	327	/! @brief Set the DATALU field to a new value. /
mbed_official	324:406fd2029f23	328	#define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v))
mbed_official	324:406fd2029f23	329	/@}/
mbed_official	324:406fd2029f23	330	/*******************************************************************************
mbed_official	324:406fd2029f23	331	* HW_CRC_DATAHL - CRC_DATAHL register.
mbed_official	324:406fd2029f23	332	******************************************************************************/
mbed_official	324:406fd2029f23	333
mbed_official	324:406fd2029f23	334	/*!
mbed_official	324:406fd2029f23	335	* @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
mbed_official	324:406fd2029f23	336	*
mbed_official	324:406fd2029f23	337	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	338	*/
mbed_official	324:406fd2029f23	339	typedef union _hw_crc_datahl
mbed_official	324:406fd2029f23	340	{
mbed_official	324:406fd2029f23	341	uint8_t U;
mbed_official	324:406fd2029f23	342	struct _hw_crc_datahl_bitfields
mbed_official	324:406fd2029f23	343	{
mbed_official	324:406fd2029f23	344	uint8_t DATAHL : 8; /*!< [7:0] DATAHL stores the third 8 bits of the
mbed_official	324:406fd2029f23	345	* 32 bit CRC */
mbed_official	324:406fd2029f23	346	} B;
mbed_official	324:406fd2029f23	347	} hw_crc_datahl_t;
mbed_official	324:406fd2029f23	348
mbed_official	324:406fd2029f23	349	/*!
mbed_official	324:406fd2029f23	350	* @name Constants and macros for entire CRC_DATAHL register
mbed_official	324:406fd2029f23	351	*/
mbed_official	324:406fd2029f23	352	/@{/
mbed_official	324:406fd2029f23	353	#define HW_CRC_DATAHL_ADDR(x) ((x) + 0x2U)
mbed_official	324:406fd2029f23	354
mbed_official	324:406fd2029f23	355	#define HW_CRC_DATAHL(x) ((__IO hw_crc_datahl_t ) HW_CRC_DATAHL_ADDR(x))
mbed_official	324:406fd2029f23	356	#define HW_CRC_DATAHL_RD(x) (HW_CRC_DATAHL(x).U)
mbed_official	324:406fd2029f23	357	#define HW_CRC_DATAHL_WR(x, v) (HW_CRC_DATAHL(x).U = (v))
mbed_official	324:406fd2029f23	358	#define HW_CRC_DATAHL_SET(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	359	#define HW_CRC_DATAHL_CLR(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	360	#define HW_CRC_DATAHL_TOG(x, v) (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	361	/@}/
mbed_official	324:406fd2029f23	362
mbed_official	324:406fd2029f23	363	/*
mbed_official	324:406fd2029f23	364	* Constants & macros for individual CRC_DATAHL bitfields
mbed_official	324:406fd2029f23	365	*/
mbed_official	324:406fd2029f23	366
mbed_official	324:406fd2029f23	367	/*!
mbed_official	324:406fd2029f23	368	* @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
mbed_official	324:406fd2029f23	369	*/
mbed_official	324:406fd2029f23	370	/@{/
mbed_official	324:406fd2029f23	371	#define BP_CRC_DATAHL_DATAHL (0U) /!< Bit position for CRC_DATAHL_DATAHL. /
mbed_official	324:406fd2029f23	372	#define BM_CRC_DATAHL_DATAHL (0xFFU) /!< Bit mask for CRC_DATAHL_DATAHL. /
mbed_official	324:406fd2029f23	373	#define BS_CRC_DATAHL_DATAHL (8U) /!< Bit field size in bits for CRC_DATAHL_DATAHL. /
mbed_official	324:406fd2029f23	374
mbed_official	324:406fd2029f23	375	/! @brief Read current value of the CRC_DATAHL_DATAHL field. /
mbed_official	324:406fd2029f23	376	#define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U)
mbed_official	324:406fd2029f23	377
mbed_official	324:406fd2029f23	378	/! @brief Format value for bitfield CRC_DATAHL_DATAHL. /
mbed_official	324:406fd2029f23	379	#define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL)
mbed_official	324:406fd2029f23	380
mbed_official	324:406fd2029f23	381	/! @brief Set the DATAHL field to a new value. /
mbed_official	324:406fd2029f23	382	#define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v))
mbed_official	324:406fd2029f23	383	/@}/
mbed_official	324:406fd2029f23	384	/*******************************************************************************
mbed_official	324:406fd2029f23	385	* HW_CRC_DATAHU - CRC_DATAHU register.
mbed_official	324:406fd2029f23	386	******************************************************************************/
mbed_official	324:406fd2029f23	387
mbed_official	324:406fd2029f23	388	/*!
mbed_official	324:406fd2029f23	389	* @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
mbed_official	324:406fd2029f23	390	*
mbed_official	324:406fd2029f23	391	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	392	*/
mbed_official	324:406fd2029f23	393	typedef union _hw_crc_datahu
mbed_official	324:406fd2029f23	394	{
mbed_official	324:406fd2029f23	395	uint8_t U;
mbed_official	324:406fd2029f23	396	struct _hw_crc_datahu_bitfields
mbed_official	324:406fd2029f23	397	{
mbed_official	324:406fd2029f23	398	uint8_t DATAHU : 8; /*!< [7:0] DATAHU stores the fourth 8 bits of the
mbed_official	324:406fd2029f23	399	* 32 bit CRC */
mbed_official	324:406fd2029f23	400	} B;
mbed_official	324:406fd2029f23	401	} hw_crc_datahu_t;
mbed_official	324:406fd2029f23	402
mbed_official	324:406fd2029f23	403	/*!
mbed_official	324:406fd2029f23	404	* @name Constants and macros for entire CRC_DATAHU register
mbed_official	324:406fd2029f23	405	*/
mbed_official	324:406fd2029f23	406	/@{/
mbed_official	324:406fd2029f23	407	#define HW_CRC_DATAHU_ADDR(x) ((x) + 0x3U)
mbed_official	324:406fd2029f23	408
mbed_official	324:406fd2029f23	409	#define HW_CRC_DATAHU(x) ((__IO hw_crc_datahu_t ) HW_CRC_DATAHU_ADDR(x))
mbed_official	324:406fd2029f23	410	#define HW_CRC_DATAHU_RD(x) (HW_CRC_DATAHU(x).U)
mbed_official	324:406fd2029f23	411	#define HW_CRC_DATAHU_WR(x, v) (HW_CRC_DATAHU(x).U = (v))
mbed_official	324:406fd2029f23	412	#define HW_CRC_DATAHU_SET(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) \| (v)))
mbed_official	324:406fd2029f23	413	#define HW_CRC_DATAHU_CLR(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	414	#define HW_CRC_DATAHU_TOG(x, v) (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	415	/@}/
mbed_official	324:406fd2029f23	416
mbed_official	324:406fd2029f23	417	/*
mbed_official	324:406fd2029f23	418	* Constants & macros for individual CRC_DATAHU bitfields
mbed_official	324:406fd2029f23	419	*/
mbed_official	324:406fd2029f23	420
mbed_official	324:406fd2029f23	421	/*!
mbed_official	324:406fd2029f23	422	* @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
mbed_official	324:406fd2029f23	423	*/
mbed_official	324:406fd2029f23	424	/@{/
mbed_official	324:406fd2029f23	425	#define BP_CRC_DATAHU_DATAHU (0U) /!< Bit position for CRC_DATAHU_DATAHU. /
mbed_official	324:406fd2029f23	426	#define BM_CRC_DATAHU_DATAHU (0xFFU) /!< Bit mask for CRC_DATAHU_DATAHU. /
mbed_official	324:406fd2029f23	427	#define BS_CRC_DATAHU_DATAHU (8U) /!< Bit field size in bits for CRC_DATAHU_DATAHU. /
mbed_official	324:406fd2029f23	428
mbed_official	324:406fd2029f23	429	/! @brief Read current value of the CRC_DATAHU_DATAHU field. /
mbed_official	324:406fd2029f23	430	#define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U)
mbed_official	324:406fd2029f23	431
mbed_official	324:406fd2029f23	432	/! @brief Format value for bitfield CRC_DATAHU_DATAHU. /
mbed_official	324:406fd2029f23	433	#define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU)
mbed_official	324:406fd2029f23	434
mbed_official	324:406fd2029f23	435	/! @brief Set the DATAHU field to a new value. /
mbed_official	324:406fd2029f23	436	#define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v))
mbed_official	324:406fd2029f23	437	/@}/
mbed_official	324:406fd2029f23	438	/*******************************************************************************
mbed_official	324:406fd2029f23	439	* HW_CRC_DATA - CRC Data register
mbed_official	324:406fd2029f23	440	******************************************************************************/
mbed_official	324:406fd2029f23	441
mbed_official	324:406fd2029f23	442	/*!
mbed_official	324:406fd2029f23	443	* @brief HW_CRC_DATA - CRC Data register (RW)
mbed_official	324:406fd2029f23	444	*
mbed_official	324:406fd2029f23	445	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	446	*
mbed_official	324:406fd2029f23	447	* The CRC Data register contains the value of the seed, data, and checksum.
mbed_official	324:406fd2029f23	448	* When CTRL[WAS] is set, any write to the data register is regarded as the seed
mbed_official	324:406fd2029f23	449	* value. When CTRL[WAS] is cleared, any write to the data register is regarded as
mbed_official	324:406fd2029f23	450	* data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
mbed_official	324:406fd2029f23	451	* not used for programming the seed value, and reads of these fields return an
mbed_official	324:406fd2029f23	452	* indeterminate value. In 32-bit CRC mode, all fields are used for programming
mbed_official	324:406fd2029f23	453	* the seed value. When programming data values, the values can be written 8 bits,
mbed_official	324:406fd2029f23	454	* 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
mbed_official	324:406fd2029f23	455	* data value written first. After all data values are written, the CRC result
mbed_official	324:406fd2029f23	456	* can be read from this data register. In 16-bit CRC mode, the CRC result is
mbed_official	324:406fd2029f23	457	* available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
mbed_official	324:406fd2029f23	458	* result. Reads of this register at any time return the intermediate CRC value,
mbed_official	324:406fd2029f23	459	* provided the CRC module is configured.
mbed_official	324:406fd2029f23	460	*/
mbed_official	324:406fd2029f23	461	typedef union _hw_crc_data
mbed_official	324:406fd2029f23	462	{
mbed_official	324:406fd2029f23	463	uint32_t U;
mbed_official	324:406fd2029f23	464	struct _hw_crc_data_bitfields
mbed_official	324:406fd2029f23	465	{
mbed_official	324:406fd2029f23	466	uint32_t LL : 8; /!< [7:0] CRC Low Lower Byte /
mbed_official	324:406fd2029f23	467	uint32_t LU : 8; /!< [15:8] CRC Low Upper Byte /
mbed_official	324:406fd2029f23	468	uint32_t HL : 8; /!< [23:16] CRC High Lower Byte /
mbed_official	324:406fd2029f23	469	uint32_t HU : 8; /!< [31:24] CRC High Upper Byte /
mbed_official	324:406fd2029f23	470	} B;
mbed_official	324:406fd2029f23	471	} hw_crc_data_t;
mbed_official	324:406fd2029f23	472
mbed_official	324:406fd2029f23	473	/*!
mbed_official	324:406fd2029f23	474	* @name Constants and macros for entire CRC_DATA register
mbed_official	324:406fd2029f23	475	*/
mbed_official	324:406fd2029f23	476	/@{/
mbed_official	324:406fd2029f23	477	#define HW_CRC_DATA_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	478
mbed_official	324:406fd2029f23	479	#define HW_CRC_DATA(x) ((__IO hw_crc_data_t ) HW_CRC_DATA_ADDR(x))
mbed_official	324:406fd2029f23	480	#define HW_CRC_DATA_RD(x) (HW_CRC_DATA(x).U)
mbed_official	324:406fd2029f23	481	#define HW_CRC_DATA_WR(x, v) (HW_CRC_DATA(x).U = (v))
mbed_official	324:406fd2029f23	482	#define HW_CRC_DATA_SET(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) \| (v)))
mbed_official	324:406fd2029f23	483	#define HW_CRC_DATA_CLR(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	484	#define HW_CRC_DATA_TOG(x, v) (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	485	/@}/
mbed_official	324:406fd2029f23	486
mbed_official	324:406fd2029f23	487	/*
mbed_official	324:406fd2029f23	488	* Constants & macros for individual CRC_DATA bitfields
mbed_official	324:406fd2029f23	489	*/
mbed_official	324:406fd2029f23	490
mbed_official	324:406fd2029f23	491	/*!
mbed_official	324:406fd2029f23	492	* @name Register CRC_DATA, field LL[7:0] (RW)
mbed_official	324:406fd2029f23	493	*
mbed_official	324:406fd2029f23	494	* When CTRL[WAS] is 1, values written to this field are part of the seed value.
mbed_official	324:406fd2029f23	495	* When CTRL[WAS] is 0, data written to this field is used for CRC checksum
mbed_official	324:406fd2029f23	496	* generation.
mbed_official	324:406fd2029f23	497	*/
mbed_official	324:406fd2029f23	498	/@{/
mbed_official	324:406fd2029f23	499	#define BP_CRC_DATA_LL (0U) /!< Bit position for CRC_DATA_LL. /
mbed_official	324:406fd2029f23	500	#define BM_CRC_DATA_LL (0x000000FFU) /!< Bit mask for CRC_DATA_LL. /
mbed_official	324:406fd2029f23	501	#define BS_CRC_DATA_LL (8U) /!< Bit field size in bits for CRC_DATA_LL. /
mbed_official	324:406fd2029f23	502
mbed_official	324:406fd2029f23	503	/! @brief Read current value of the CRC_DATA_LL field. /
mbed_official	324:406fd2029f23	504	#define BR_CRC_DATA_LL(x) (HW_CRC_DATA(x).B.LL)
mbed_official	324:406fd2029f23	505
mbed_official	324:406fd2029f23	506	/! @brief Format value for bitfield CRC_DATA_LL. /
mbed_official	324:406fd2029f23	507	#define BF_CRC_DATA_LL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL)
mbed_official	324:406fd2029f23	508
mbed_official	324:406fd2029f23	509	/! @brief Set the LL field to a new value. /
mbed_official	324:406fd2029f23	510	#define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) \| BF_CRC_DATA_LL(v)))
mbed_official	324:406fd2029f23	511	/@}/
mbed_official	324:406fd2029f23	512
mbed_official	324:406fd2029f23	513	/*!
mbed_official	324:406fd2029f23	514	* @name Register CRC_DATA, field LU[15:8] (RW)
mbed_official	324:406fd2029f23	515	*
mbed_official	324:406fd2029f23	516	* When CTRL[WAS] is 1, values written to this field are part of the seed value.
mbed_official	324:406fd2029f23	517	* When CTRL[WAS] is 0, data written to this field is used for CRC checksum
mbed_official	324:406fd2029f23	518	* generation.
mbed_official	324:406fd2029f23	519	*/
mbed_official	324:406fd2029f23	520	/@{/
mbed_official	324:406fd2029f23	521	#define BP_CRC_DATA_LU (8U) /!< Bit position for CRC_DATA_LU. /
mbed_official	324:406fd2029f23	522	#define BM_CRC_DATA_LU (0x0000FF00U) /!< Bit mask for CRC_DATA_LU. /
mbed_official	324:406fd2029f23	523	#define BS_CRC_DATA_LU (8U) /!< Bit field size in bits for CRC_DATA_LU. /
mbed_official	324:406fd2029f23	524
mbed_official	324:406fd2029f23	525	/! @brief Read current value of the CRC_DATA_LU field. /
mbed_official	324:406fd2029f23	526	#define BR_CRC_DATA_LU(x) (HW_CRC_DATA(x).B.LU)
mbed_official	324:406fd2029f23	527
mbed_official	324:406fd2029f23	528	/! @brief Format value for bitfield CRC_DATA_LU. /
mbed_official	324:406fd2029f23	529	#define BF_CRC_DATA_LU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU)
mbed_official	324:406fd2029f23	530
mbed_official	324:406fd2029f23	531	/! @brief Set the LU field to a new value. /
mbed_official	324:406fd2029f23	532	#define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) \| BF_CRC_DATA_LU(v)))
mbed_official	324:406fd2029f23	533	/@}/
mbed_official	324:406fd2029f23	534
mbed_official	324:406fd2029f23	535	/*!
mbed_official	324:406fd2029f23	536	* @name Register CRC_DATA, field HL[23:16] (RW)
mbed_official	324:406fd2029f23	537	*
mbed_official	324:406fd2029f23	538	* In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
mbed_official	324:406fd2029f23	539	* a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
mbed_official	324:406fd2029f23	540	* field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
mbed_official	324:406fd2029f23	541	* written to this field is used for CRC checksum generation in both 16-bit and
mbed_official	324:406fd2029f23	542	* 32-bit CRC modes.
mbed_official	324:406fd2029f23	543	*/
mbed_official	324:406fd2029f23	544	/@{/
mbed_official	324:406fd2029f23	545	#define BP_CRC_DATA_HL (16U) /!< Bit position for CRC_DATA_HL. /
mbed_official	324:406fd2029f23	546	#define BM_CRC_DATA_HL (0x00FF0000U) /!< Bit mask for CRC_DATA_HL. /
mbed_official	324:406fd2029f23	547	#define BS_CRC_DATA_HL (8U) /!< Bit field size in bits for CRC_DATA_HL. /
mbed_official	324:406fd2029f23	548
mbed_official	324:406fd2029f23	549	/! @brief Read current value of the CRC_DATA_HL field. /
mbed_official	324:406fd2029f23	550	#define BR_CRC_DATA_HL(x) (HW_CRC_DATA(x).B.HL)
mbed_official	324:406fd2029f23	551
mbed_official	324:406fd2029f23	552	/! @brief Format value for bitfield CRC_DATA_HL. /
mbed_official	324:406fd2029f23	553	#define BF_CRC_DATA_HL(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL)
mbed_official	324:406fd2029f23	554
mbed_official	324:406fd2029f23	555	/! @brief Set the HL field to a new value. /
mbed_official	324:406fd2029f23	556	#define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) \| BF_CRC_DATA_HL(v)))
mbed_official	324:406fd2029f23	557	/@}/
mbed_official	324:406fd2029f23	558
mbed_official	324:406fd2029f23	559	/*!
mbed_official	324:406fd2029f23	560	* @name Register CRC_DATA, field HU[31:24] (RW)
mbed_official	324:406fd2029f23	561	*
mbed_official	324:406fd2029f23	562	* In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
mbed_official	324:406fd2029f23	563	* a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
mbed_official	324:406fd2029f23	564	* field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
mbed_official	324:406fd2029f23	565	* written to this field is used for CRC checksum generation in both 16-bit and
mbed_official	324:406fd2029f23	566	* 32-bit CRC modes.
mbed_official	324:406fd2029f23	567	*/
mbed_official	324:406fd2029f23	568	/@{/
mbed_official	324:406fd2029f23	569	#define BP_CRC_DATA_HU (24U) /!< Bit position for CRC_DATA_HU. /
mbed_official	324:406fd2029f23	570	#define BM_CRC_DATA_HU (0xFF000000U) /!< Bit mask for CRC_DATA_HU. /
mbed_official	324:406fd2029f23	571	#define BS_CRC_DATA_HU (8U) /!< Bit field size in bits for CRC_DATA_HU. /
mbed_official	324:406fd2029f23	572
mbed_official	324:406fd2029f23	573	/! @brief Read current value of the CRC_DATA_HU field. /
mbed_official	324:406fd2029f23	574	#define BR_CRC_DATA_HU(x) (HW_CRC_DATA(x).B.HU)
mbed_official	324:406fd2029f23	575
mbed_official	324:406fd2029f23	576	/! @brief Format value for bitfield CRC_DATA_HU. /
mbed_official	324:406fd2029f23	577	#define BF_CRC_DATA_HU(v) ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU)
mbed_official	324:406fd2029f23	578
mbed_official	324:406fd2029f23	579	/! @brief Set the HU field to a new value. /
mbed_official	324:406fd2029f23	580	#define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) \| BF_CRC_DATA_HU(v)))
mbed_official	324:406fd2029f23	581	/@}/
mbed_official	324:406fd2029f23	582
mbed_official	324:406fd2029f23	583	/*******************************************************************************
mbed_official	324:406fd2029f23	584	* HW_CRC_GPOLY - CRC Polynomial register
mbed_official	324:406fd2029f23	585	******************************************************************************/
mbed_official	324:406fd2029f23	586
mbed_official	324:406fd2029f23	587	/*!
mbed_official	324:406fd2029f23	588	* @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
mbed_official	324:406fd2029f23	589	*
mbed_official	324:406fd2029f23	590	* Reset value: 0x00001021U
mbed_official	324:406fd2029f23	591	*
mbed_official	324:406fd2029f23	592	* This register contains the value of the polynomial for the CRC calculation.
mbed_official	324:406fd2029f23	593	* The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
mbed_official	324:406fd2029f23	594	* only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
mbed_official	324:406fd2029f23	595	* mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
mbed_official	324:406fd2029f23	596	* used in both 16- and 32-bit CRC modes.
mbed_official	324:406fd2029f23	597	*/
mbed_official	324:406fd2029f23	598	typedef union _hw_crc_gpoly
mbed_official	324:406fd2029f23	599	{
mbed_official	324:406fd2029f23	600	uint32_t U;
mbed_official	324:406fd2029f23	601	struct _hw_crc_gpoly_bitfields
mbed_official	324:406fd2029f23	602	{
mbed_official	324:406fd2029f23	603	uint32_t LOW : 16; /!< [15:0] Low Polynominal Half-word /
mbed_official	324:406fd2029f23	604	uint32_t HIGH : 16; /!< [31:16] High Polynominal Half-word /
mbed_official	324:406fd2029f23	605	} B;
mbed_official	324:406fd2029f23	606	} hw_crc_gpoly_t;
mbed_official	324:406fd2029f23	607
mbed_official	324:406fd2029f23	608	/*!
mbed_official	324:406fd2029f23	609	* @name Constants and macros for entire CRC_GPOLY register
mbed_official	324:406fd2029f23	610	*/
mbed_official	324:406fd2029f23	611	/@{/
mbed_official	324:406fd2029f23	612	#define HW_CRC_GPOLY_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	613
mbed_official	324:406fd2029f23	614	#define HW_CRC_GPOLY(x) ((__IO hw_crc_gpoly_t ) HW_CRC_GPOLY_ADDR(x))
mbed_official	324:406fd2029f23	615	#define HW_CRC_GPOLY_RD(x) (HW_CRC_GPOLY(x).U)
mbed_official	324:406fd2029f23	616	#define HW_CRC_GPOLY_WR(x, v) (HW_CRC_GPOLY(x).U = (v))
mbed_official	324:406fd2029f23	617	#define HW_CRC_GPOLY_SET(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) \| (v)))
mbed_official	324:406fd2029f23	618	#define HW_CRC_GPOLY_CLR(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	619	#define HW_CRC_GPOLY_TOG(x, v) (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	620	/@}/
mbed_official	324:406fd2029f23	621
mbed_official	324:406fd2029f23	622	/*
mbed_official	324:406fd2029f23	623	* Constants & macros for individual CRC_GPOLY bitfields
mbed_official	324:406fd2029f23	624	*/
mbed_official	324:406fd2029f23	625
mbed_official	324:406fd2029f23	626	/*!
mbed_official	324:406fd2029f23	627	* @name Register CRC_GPOLY, field LOW[15:0] (RW)
mbed_official	324:406fd2029f23	628	*
mbed_official	324:406fd2029f23	629	* Writable and readable in both 32-bit and 16-bit CRC modes.
mbed_official	324:406fd2029f23	630	*/
mbed_official	324:406fd2029f23	631	/@{/
mbed_official	324:406fd2029f23	632	#define BP_CRC_GPOLY_LOW (0U) /!< Bit position for CRC_GPOLY_LOW. /
mbed_official	324:406fd2029f23	633	#define BM_CRC_GPOLY_LOW (0x0000FFFFU) /!< Bit mask for CRC_GPOLY_LOW. /
mbed_official	324:406fd2029f23	634	#define BS_CRC_GPOLY_LOW (16U) /!< Bit field size in bits for CRC_GPOLY_LOW. /
mbed_official	324:406fd2029f23	635
mbed_official	324:406fd2029f23	636	/! @brief Read current value of the CRC_GPOLY_LOW field. /
mbed_official	324:406fd2029f23	637	#define BR_CRC_GPOLY_LOW(x) (HW_CRC_GPOLY(x).B.LOW)
mbed_official	324:406fd2029f23	638
mbed_official	324:406fd2029f23	639	/! @brief Format value for bitfield CRC_GPOLY_LOW. /
mbed_official	324:406fd2029f23	640	#define BF_CRC_GPOLY_LOW(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW)
mbed_official	324:406fd2029f23	641
mbed_official	324:406fd2029f23	642	/! @brief Set the LOW field to a new value. /
mbed_official	324:406fd2029f23	643	#define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) \| BF_CRC_GPOLY_LOW(v)))
mbed_official	324:406fd2029f23	644	/@}/
mbed_official	324:406fd2029f23	645
mbed_official	324:406fd2029f23	646	/*!
mbed_official	324:406fd2029f23	647	* @name Register CRC_GPOLY, field HIGH[31:16] (RW)
mbed_official	324:406fd2029f23	648	*
mbed_official	324:406fd2029f23	649	* Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
mbed_official	324:406fd2029f23	650	* writable in 16-bit CRC mode (CTRL[TCRC] is 0).
mbed_official	324:406fd2029f23	651	*/
mbed_official	324:406fd2029f23	652	/@{/
mbed_official	324:406fd2029f23	653	#define BP_CRC_GPOLY_HIGH (16U) /!< Bit position for CRC_GPOLY_HIGH. /
mbed_official	324:406fd2029f23	654	#define BM_CRC_GPOLY_HIGH (0xFFFF0000U) /!< Bit mask for CRC_GPOLY_HIGH. /
mbed_official	324:406fd2029f23	655	#define BS_CRC_GPOLY_HIGH (16U) /!< Bit field size in bits for CRC_GPOLY_HIGH. /
mbed_official	324:406fd2029f23	656
mbed_official	324:406fd2029f23	657	/! @brief Read current value of the CRC_GPOLY_HIGH field. /
mbed_official	324:406fd2029f23	658	#define BR_CRC_GPOLY_HIGH(x) (HW_CRC_GPOLY(x).B.HIGH)
mbed_official	324:406fd2029f23	659
mbed_official	324:406fd2029f23	660	/! @brief Format value for bitfield CRC_GPOLY_HIGH. /
mbed_official	324:406fd2029f23	661	#define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH)
mbed_official	324:406fd2029f23	662
mbed_official	324:406fd2029f23	663	/! @brief Set the HIGH field to a new value. /
mbed_official	324:406fd2029f23	664	#define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) \| BF_CRC_GPOLY_HIGH(v)))
mbed_official	324:406fd2029f23	665	/@}/
mbed_official	324:406fd2029f23	666	/*******************************************************************************
mbed_official	324:406fd2029f23	667	* HW_CRC_GPOLYL - CRC_GPOLYL register.
mbed_official	324:406fd2029f23	668	******************************************************************************/
mbed_official	324:406fd2029f23	669
mbed_official	324:406fd2029f23	670	/*!
mbed_official	324:406fd2029f23	671	* @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
mbed_official	324:406fd2029f23	672	*
mbed_official	324:406fd2029f23	673	* Reset value: 0xFFFFU
mbed_official	324:406fd2029f23	674	*/
mbed_official	324:406fd2029f23	675	typedef union _hw_crc_gpolyl
mbed_official	324:406fd2029f23	676	{
mbed_official	324:406fd2029f23	677	uint16_t U;
mbed_official	324:406fd2029f23	678	struct _hw_crc_gpolyl_bitfields
mbed_official	324:406fd2029f23	679	{
mbed_official	324:406fd2029f23	680	uint16_t GPOLYL : 16; /*!< [15:0] POLYL stores the lower 16 bits of
mbed_official	324:406fd2029f23	681	* the 16/32 bit CRC polynomial value */
mbed_official	324:406fd2029f23	682	} B;
mbed_official	324:406fd2029f23	683	} hw_crc_gpolyl_t;
mbed_official	324:406fd2029f23	684
mbed_official	324:406fd2029f23	685	/*!
mbed_official	324:406fd2029f23	686	* @name Constants and macros for entire CRC_GPOLYL register
mbed_official	324:406fd2029f23	687	*/
mbed_official	324:406fd2029f23	688	/@{/
mbed_official	324:406fd2029f23	689	#define HW_CRC_GPOLYL_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	690
mbed_official	324:406fd2029f23	691	#define HW_CRC_GPOLYL(x) ((__IO hw_crc_gpolyl_t ) HW_CRC_GPOLYL_ADDR(x))
mbed_official	324:406fd2029f23	692	#define HW_CRC_GPOLYL_RD(x) (HW_CRC_GPOLYL(x).U)
mbed_official	324:406fd2029f23	693	#define HW_CRC_GPOLYL_WR(x, v) (HW_CRC_GPOLYL(x).U = (v))
mbed_official	324:406fd2029f23	694	#define HW_CRC_GPOLYL_SET(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	695	#define HW_CRC_GPOLYL_CLR(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	696	#define HW_CRC_GPOLYL_TOG(x, v) (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	697	/@}/
mbed_official	324:406fd2029f23	698
mbed_official	324:406fd2029f23	699	/*
mbed_official	324:406fd2029f23	700	* Constants & macros for individual CRC_GPOLYL bitfields
mbed_official	324:406fd2029f23	701	*/
mbed_official	324:406fd2029f23	702
mbed_official	324:406fd2029f23	703	/*!
mbed_official	324:406fd2029f23	704	* @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
mbed_official	324:406fd2029f23	705	*/
mbed_official	324:406fd2029f23	706	/@{/
mbed_official	324:406fd2029f23	707	#define BP_CRC_GPOLYL_GPOLYL (0U) /!< Bit position for CRC_GPOLYL_GPOLYL. /
mbed_official	324:406fd2029f23	708	#define BM_CRC_GPOLYL_GPOLYL (0xFFFFU) /!< Bit mask for CRC_GPOLYL_GPOLYL. /
mbed_official	324:406fd2029f23	709	#define BS_CRC_GPOLYL_GPOLYL (16U) /!< Bit field size in bits for CRC_GPOLYL_GPOLYL. /
mbed_official	324:406fd2029f23	710
mbed_official	324:406fd2029f23	711	/! @brief Read current value of the CRC_GPOLYL_GPOLYL field. /
mbed_official	324:406fd2029f23	712	#define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U)
mbed_official	324:406fd2029f23	713
mbed_official	324:406fd2029f23	714	/! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. /
mbed_official	324:406fd2029f23	715	#define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL)
mbed_official	324:406fd2029f23	716
mbed_official	324:406fd2029f23	717	/! @brief Set the GPOLYL field to a new value. /
mbed_official	324:406fd2029f23	718	#define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v))
mbed_official	324:406fd2029f23	719	/@}/
mbed_official	324:406fd2029f23	720	/*******************************************************************************
mbed_official	324:406fd2029f23	721	* HW_CRC_GPOLYH - CRC_GPOLYH register.
mbed_official	324:406fd2029f23	722	******************************************************************************/
mbed_official	324:406fd2029f23	723
mbed_official	324:406fd2029f23	724	/*!
mbed_official	324:406fd2029f23	725	* @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
mbed_official	324:406fd2029f23	726	*
mbed_official	324:406fd2029f23	727	* Reset value: 0xFFFFU
mbed_official	324:406fd2029f23	728	*/
mbed_official	324:406fd2029f23	729	typedef union _hw_crc_gpolyh
mbed_official	324:406fd2029f23	730	{
mbed_official	324:406fd2029f23	731	uint16_t U;
mbed_official	324:406fd2029f23	732	struct _hw_crc_gpolyh_bitfields
mbed_official	324:406fd2029f23	733	{
mbed_official	324:406fd2029f23	734	uint16_t GPOLYH : 16; /*!< [15:0] POLYH stores the high 16 bits of
mbed_official	324:406fd2029f23	735	* the 16/32 bit CRC polynomial value */
mbed_official	324:406fd2029f23	736	} B;
mbed_official	324:406fd2029f23	737	} hw_crc_gpolyh_t;
mbed_official	324:406fd2029f23	738
mbed_official	324:406fd2029f23	739	/*!
mbed_official	324:406fd2029f23	740	* @name Constants and macros for entire CRC_GPOLYH register
mbed_official	324:406fd2029f23	741	*/
mbed_official	324:406fd2029f23	742	/@{/
mbed_official	324:406fd2029f23	743	#define HW_CRC_GPOLYH_ADDR(x) ((x) + 0x6U)
mbed_official	324:406fd2029f23	744
mbed_official	324:406fd2029f23	745	#define HW_CRC_GPOLYH(x) ((__IO hw_crc_gpolyh_t ) HW_CRC_GPOLYH_ADDR(x))
mbed_official	324:406fd2029f23	746	#define HW_CRC_GPOLYH_RD(x) (HW_CRC_GPOLYH(x).U)
mbed_official	324:406fd2029f23	747	#define HW_CRC_GPOLYH_WR(x, v) (HW_CRC_GPOLYH(x).U = (v))
mbed_official	324:406fd2029f23	748	#define HW_CRC_GPOLYH_SET(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	749	#define HW_CRC_GPOLYH_CLR(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	750	#define HW_CRC_GPOLYH_TOG(x, v) (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	751	/@}/
mbed_official	324:406fd2029f23	752
mbed_official	324:406fd2029f23	753	/*
mbed_official	324:406fd2029f23	754	* Constants & macros for individual CRC_GPOLYH bitfields
mbed_official	324:406fd2029f23	755	*/
mbed_official	324:406fd2029f23	756
mbed_official	324:406fd2029f23	757	/*!
mbed_official	324:406fd2029f23	758	* @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
mbed_official	324:406fd2029f23	759	*/
mbed_official	324:406fd2029f23	760	/@{/
mbed_official	324:406fd2029f23	761	#define BP_CRC_GPOLYH_GPOLYH (0U) /!< Bit position for CRC_GPOLYH_GPOLYH. /
mbed_official	324:406fd2029f23	762	#define BM_CRC_GPOLYH_GPOLYH (0xFFFFU) /!< Bit mask for CRC_GPOLYH_GPOLYH. /
mbed_official	324:406fd2029f23	763	#define BS_CRC_GPOLYH_GPOLYH (16U) /!< Bit field size in bits for CRC_GPOLYH_GPOLYH. /
mbed_official	324:406fd2029f23	764
mbed_official	324:406fd2029f23	765	/! @brief Read current value of the CRC_GPOLYH_GPOLYH field. /
mbed_official	324:406fd2029f23	766	#define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U)
mbed_official	324:406fd2029f23	767
mbed_official	324:406fd2029f23	768	/! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. /
mbed_official	324:406fd2029f23	769	#define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH)
mbed_official	324:406fd2029f23	770
mbed_official	324:406fd2029f23	771	/! @brief Set the GPOLYH field to a new value. /
mbed_official	324:406fd2029f23	772	#define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v))
mbed_official	324:406fd2029f23	773	/@}/
mbed_official	324:406fd2029f23	774	/*******************************************************************************
mbed_official	324:406fd2029f23	775	* HW_CRC_GPOLYLL - CRC_GPOLYLL register.
mbed_official	324:406fd2029f23	776	******************************************************************************/
mbed_official	324:406fd2029f23	777
mbed_official	324:406fd2029f23	778	/*!
mbed_official	324:406fd2029f23	779	* @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
mbed_official	324:406fd2029f23	780	*
mbed_official	324:406fd2029f23	781	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	782	*/
mbed_official	324:406fd2029f23	783	typedef union _hw_crc_gpolyll
mbed_official	324:406fd2029f23	784	{
mbed_official	324:406fd2029f23	785	uint8_t U;
mbed_official	324:406fd2029f23	786	struct _hw_crc_gpolyll_bitfields
mbed_official	324:406fd2029f23	787	{
mbed_official	324:406fd2029f23	788	uint8_t GPOLYLL : 8; /*!< [7:0] POLYLL stores the first 8 bits of the
mbed_official	324:406fd2029f23	789	* 32 bit CRC */
mbed_official	324:406fd2029f23	790	} B;
mbed_official	324:406fd2029f23	791	} hw_crc_gpolyll_t;
mbed_official	324:406fd2029f23	792
mbed_official	324:406fd2029f23	793	/*!
mbed_official	324:406fd2029f23	794	* @name Constants and macros for entire CRC_GPOLYLL register
mbed_official	324:406fd2029f23	795	*/
mbed_official	324:406fd2029f23	796	/@{/
mbed_official	324:406fd2029f23	797	#define HW_CRC_GPOLYLL_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	798
mbed_official	324:406fd2029f23	799	#define HW_CRC_GPOLYLL(x) ((__IO hw_crc_gpolyll_t ) HW_CRC_GPOLYLL_ADDR(x))
mbed_official	324:406fd2029f23	800	#define HW_CRC_GPOLYLL_RD(x) (HW_CRC_GPOLYLL(x).U)
mbed_official	324:406fd2029f23	801	#define HW_CRC_GPOLYLL_WR(x, v) (HW_CRC_GPOLYLL(x).U = (v))
mbed_official	324:406fd2029f23	802	#define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	803	#define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	804	#define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	805	/@}/
mbed_official	324:406fd2029f23	806
mbed_official	324:406fd2029f23	807	/*
mbed_official	324:406fd2029f23	808	* Constants & macros for individual CRC_GPOLYLL bitfields
mbed_official	324:406fd2029f23	809	*/
mbed_official	324:406fd2029f23	810
mbed_official	324:406fd2029f23	811	/*!
mbed_official	324:406fd2029f23	812	* @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
mbed_official	324:406fd2029f23	813	*/
mbed_official	324:406fd2029f23	814	/@{/
mbed_official	324:406fd2029f23	815	#define BP_CRC_GPOLYLL_GPOLYLL (0U) /!< Bit position for CRC_GPOLYLL_GPOLYLL. /
mbed_official	324:406fd2029f23	816	#define BM_CRC_GPOLYLL_GPOLYLL (0xFFU) /!< Bit mask for CRC_GPOLYLL_GPOLYLL. /
mbed_official	324:406fd2029f23	817	#define BS_CRC_GPOLYLL_GPOLYLL (8U) /!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. /
mbed_official	324:406fd2029f23	818
mbed_official	324:406fd2029f23	819	/! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. /
mbed_official	324:406fd2029f23	820	#define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U)
mbed_official	324:406fd2029f23	821
mbed_official	324:406fd2029f23	822	/! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. /
mbed_official	324:406fd2029f23	823	#define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL)
mbed_official	324:406fd2029f23	824
mbed_official	324:406fd2029f23	825	/! @brief Set the GPOLYLL field to a new value. /
mbed_official	324:406fd2029f23	826	#define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v))
mbed_official	324:406fd2029f23	827	/@}/
mbed_official	324:406fd2029f23	828	/*******************************************************************************
mbed_official	324:406fd2029f23	829	* HW_CRC_GPOLYLU - CRC_GPOLYLU register.
mbed_official	324:406fd2029f23	830	******************************************************************************/
mbed_official	324:406fd2029f23	831
mbed_official	324:406fd2029f23	832	/*!
mbed_official	324:406fd2029f23	833	* @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
mbed_official	324:406fd2029f23	834	*
mbed_official	324:406fd2029f23	835	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	836	*/
mbed_official	324:406fd2029f23	837	typedef union _hw_crc_gpolylu
mbed_official	324:406fd2029f23	838	{
mbed_official	324:406fd2029f23	839	uint8_t U;
mbed_official	324:406fd2029f23	840	struct _hw_crc_gpolylu_bitfields
mbed_official	324:406fd2029f23	841	{
mbed_official	324:406fd2029f23	842	uint8_t GPOLYLU : 8; /*!< [7:0] POLYLL stores the second 8 bits of
mbed_official	324:406fd2029f23	843	* the 32 bit CRC */
mbed_official	324:406fd2029f23	844	} B;
mbed_official	324:406fd2029f23	845	} hw_crc_gpolylu_t;
mbed_official	324:406fd2029f23	846
mbed_official	324:406fd2029f23	847	/*!
mbed_official	324:406fd2029f23	848	* @name Constants and macros for entire CRC_GPOLYLU register
mbed_official	324:406fd2029f23	849	*/
mbed_official	324:406fd2029f23	850	/@{/
mbed_official	324:406fd2029f23	851	#define HW_CRC_GPOLYLU_ADDR(x) ((x) + 0x5U)
mbed_official	324:406fd2029f23	852
mbed_official	324:406fd2029f23	853	#define HW_CRC_GPOLYLU(x) ((__IO hw_crc_gpolylu_t ) HW_CRC_GPOLYLU_ADDR(x))
mbed_official	324:406fd2029f23	854	#define HW_CRC_GPOLYLU_RD(x) (HW_CRC_GPOLYLU(x).U)
mbed_official	324:406fd2029f23	855	#define HW_CRC_GPOLYLU_WR(x, v) (HW_CRC_GPOLYLU(x).U = (v))
mbed_official	324:406fd2029f23	856	#define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) \| (v)))
mbed_official	324:406fd2029f23	857	#define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	858	#define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	859	/@}/
mbed_official	324:406fd2029f23	860
mbed_official	324:406fd2029f23	861	/*
mbed_official	324:406fd2029f23	862	* Constants & macros for individual CRC_GPOLYLU bitfields
mbed_official	324:406fd2029f23	863	*/
mbed_official	324:406fd2029f23	864
mbed_official	324:406fd2029f23	865	/*!
mbed_official	324:406fd2029f23	866	* @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
mbed_official	324:406fd2029f23	867	*/
mbed_official	324:406fd2029f23	868	/@{/
mbed_official	324:406fd2029f23	869	#define BP_CRC_GPOLYLU_GPOLYLU (0U) /!< Bit position for CRC_GPOLYLU_GPOLYLU. /
mbed_official	324:406fd2029f23	870	#define BM_CRC_GPOLYLU_GPOLYLU (0xFFU) /!< Bit mask for CRC_GPOLYLU_GPOLYLU. /
mbed_official	324:406fd2029f23	871	#define BS_CRC_GPOLYLU_GPOLYLU (8U) /!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. /
mbed_official	324:406fd2029f23	872
mbed_official	324:406fd2029f23	873	/! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. /
mbed_official	324:406fd2029f23	874	#define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U)
mbed_official	324:406fd2029f23	875
mbed_official	324:406fd2029f23	876	/! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. /
mbed_official	324:406fd2029f23	877	#define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU)
mbed_official	324:406fd2029f23	878
mbed_official	324:406fd2029f23	879	/! @brief Set the GPOLYLU field to a new value. /
mbed_official	324:406fd2029f23	880	#define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v))
mbed_official	324:406fd2029f23	881	/@}/
mbed_official	324:406fd2029f23	882	/*******************************************************************************
mbed_official	324:406fd2029f23	883	* HW_CRC_GPOLYHL - CRC_GPOLYHL register.
mbed_official	324:406fd2029f23	884	******************************************************************************/
mbed_official	324:406fd2029f23	885
mbed_official	324:406fd2029f23	886	/*!
mbed_official	324:406fd2029f23	887	* @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
mbed_official	324:406fd2029f23	888	*
mbed_official	324:406fd2029f23	889	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	890	*/
mbed_official	324:406fd2029f23	891	typedef union _hw_crc_gpolyhl
mbed_official	324:406fd2029f23	892	{
mbed_official	324:406fd2029f23	893	uint8_t U;
mbed_official	324:406fd2029f23	894	struct _hw_crc_gpolyhl_bitfields
mbed_official	324:406fd2029f23	895	{
mbed_official	324:406fd2029f23	896	uint8_t GPOLYHL : 8; /*!< [7:0] POLYHL stores the third 8 bits of the
mbed_official	324:406fd2029f23	897	* 32 bit CRC */
mbed_official	324:406fd2029f23	898	} B;
mbed_official	324:406fd2029f23	899	} hw_crc_gpolyhl_t;
mbed_official	324:406fd2029f23	900
mbed_official	324:406fd2029f23	901	/*!
mbed_official	324:406fd2029f23	902	* @name Constants and macros for entire CRC_GPOLYHL register
mbed_official	324:406fd2029f23	903	*/
mbed_official	324:406fd2029f23	904	/@{/
mbed_official	324:406fd2029f23	905	#define HW_CRC_GPOLYHL_ADDR(x) ((x) + 0x6U)
mbed_official	324:406fd2029f23	906
mbed_official	324:406fd2029f23	907	#define HW_CRC_GPOLYHL(x) ((__IO hw_crc_gpolyhl_t ) HW_CRC_GPOLYHL_ADDR(x))
mbed_official	324:406fd2029f23	908	#define HW_CRC_GPOLYHL_RD(x) (HW_CRC_GPOLYHL(x).U)
mbed_official	324:406fd2029f23	909	#define HW_CRC_GPOLYHL_WR(x, v) (HW_CRC_GPOLYHL(x).U = (v))
mbed_official	324:406fd2029f23	910	#define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	911	#define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	912	#define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	913	/@}/
mbed_official	324:406fd2029f23	914
mbed_official	324:406fd2029f23	915	/*
mbed_official	324:406fd2029f23	916	* Constants & macros for individual CRC_GPOLYHL bitfields
mbed_official	324:406fd2029f23	917	*/
mbed_official	324:406fd2029f23	918
mbed_official	324:406fd2029f23	919	/*!
mbed_official	324:406fd2029f23	920	* @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
mbed_official	324:406fd2029f23	921	*/
mbed_official	324:406fd2029f23	922	/@{/
mbed_official	324:406fd2029f23	923	#define BP_CRC_GPOLYHL_GPOLYHL (0U) /!< Bit position for CRC_GPOLYHL_GPOLYHL. /
mbed_official	324:406fd2029f23	924	#define BM_CRC_GPOLYHL_GPOLYHL (0xFFU) /!< Bit mask for CRC_GPOLYHL_GPOLYHL. /
mbed_official	324:406fd2029f23	925	#define BS_CRC_GPOLYHL_GPOLYHL (8U) /!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. /
mbed_official	324:406fd2029f23	926
mbed_official	324:406fd2029f23	927	/! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. /
mbed_official	324:406fd2029f23	928	#define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U)
mbed_official	324:406fd2029f23	929
mbed_official	324:406fd2029f23	930	/! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. /
mbed_official	324:406fd2029f23	931	#define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL)
mbed_official	324:406fd2029f23	932
mbed_official	324:406fd2029f23	933	/! @brief Set the GPOLYHL field to a new value. /
mbed_official	324:406fd2029f23	934	#define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v))
mbed_official	324:406fd2029f23	935	/@}/
mbed_official	324:406fd2029f23	936	/*******************************************************************************
mbed_official	324:406fd2029f23	937	* HW_CRC_GPOLYHU - CRC_GPOLYHU register.
mbed_official	324:406fd2029f23	938	******************************************************************************/
mbed_official	324:406fd2029f23	939
mbed_official	324:406fd2029f23	940	/*!
mbed_official	324:406fd2029f23	941	* @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
mbed_official	324:406fd2029f23	942	*
mbed_official	324:406fd2029f23	943	* Reset value: 0xFFU
mbed_official	324:406fd2029f23	944	*/
mbed_official	324:406fd2029f23	945	typedef union _hw_crc_gpolyhu
mbed_official	324:406fd2029f23	946	{
mbed_official	324:406fd2029f23	947	uint8_t U;
mbed_official	324:406fd2029f23	948	struct _hw_crc_gpolyhu_bitfields
mbed_official	324:406fd2029f23	949	{
mbed_official	324:406fd2029f23	950	uint8_t GPOLYHU : 8; /*!< [7:0] POLYHU stores the fourth 8 bits of
mbed_official	324:406fd2029f23	951	* the 32 bit CRC */
mbed_official	324:406fd2029f23	952	} B;
mbed_official	324:406fd2029f23	953	} hw_crc_gpolyhu_t;
mbed_official	324:406fd2029f23	954
mbed_official	324:406fd2029f23	955	/*!
mbed_official	324:406fd2029f23	956	* @name Constants and macros for entire CRC_GPOLYHU register
mbed_official	324:406fd2029f23	957	*/
mbed_official	324:406fd2029f23	958	/@{/
mbed_official	324:406fd2029f23	959	#define HW_CRC_GPOLYHU_ADDR(x) ((x) + 0x7U)
mbed_official	324:406fd2029f23	960
mbed_official	324:406fd2029f23	961	#define HW_CRC_GPOLYHU(x) ((__IO hw_crc_gpolyhu_t ) HW_CRC_GPOLYHU_ADDR(x))
mbed_official	324:406fd2029f23	962	#define HW_CRC_GPOLYHU_RD(x) (HW_CRC_GPOLYHU(x).U)
mbed_official	324:406fd2029f23	963	#define HW_CRC_GPOLYHU_WR(x, v) (HW_CRC_GPOLYHU(x).U = (v))
mbed_official	324:406fd2029f23	964	#define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) \| (v)))
mbed_official	324:406fd2029f23	965	#define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	966	#define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	967	/@}/
mbed_official	324:406fd2029f23	968
mbed_official	324:406fd2029f23	969	/*
mbed_official	324:406fd2029f23	970	* Constants & macros for individual CRC_GPOLYHU bitfields
mbed_official	324:406fd2029f23	971	*/
mbed_official	324:406fd2029f23	972
mbed_official	324:406fd2029f23	973	/*!
mbed_official	324:406fd2029f23	974	* @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
mbed_official	324:406fd2029f23	975	*/
mbed_official	324:406fd2029f23	976	/@{/
mbed_official	324:406fd2029f23	977	#define BP_CRC_GPOLYHU_GPOLYHU (0U) /!< Bit position for CRC_GPOLYHU_GPOLYHU. /
mbed_official	324:406fd2029f23	978	#define BM_CRC_GPOLYHU_GPOLYHU (0xFFU) /!< Bit mask for CRC_GPOLYHU_GPOLYHU. /
mbed_official	324:406fd2029f23	979	#define BS_CRC_GPOLYHU_GPOLYHU (8U) /!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. /
mbed_official	324:406fd2029f23	980
mbed_official	324:406fd2029f23	981	/! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. /
mbed_official	324:406fd2029f23	982	#define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U)
mbed_official	324:406fd2029f23	983
mbed_official	324:406fd2029f23	984	/! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. /
mbed_official	324:406fd2029f23	985	#define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU)
mbed_official	324:406fd2029f23	986
mbed_official	324:406fd2029f23	987	/! @brief Set the GPOLYHU field to a new value. /
mbed_official	324:406fd2029f23	988	#define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v))
mbed_official	324:406fd2029f23	989	/@}/
mbed_official	324:406fd2029f23	990
mbed_official	324:406fd2029f23	991	/*******************************************************************************
mbed_official	324:406fd2029f23	992	* HW_CRC_CTRL - CRC Control register
mbed_official	324:406fd2029f23	993	******************************************************************************/
mbed_official	324:406fd2029f23	994
mbed_official	324:406fd2029f23	995	/*!
mbed_official	324:406fd2029f23	996	* @brief HW_CRC_CTRL - CRC Control register (RW)
mbed_official	324:406fd2029f23	997	*
mbed_official	324:406fd2029f23	998	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	999	*
mbed_official	324:406fd2029f23	1000	* This register controls the configuration and working of the CRC module.
mbed_official	324:406fd2029f23	1001	* Appropriate bits must be set before starting a new CRC calculation. A new CRC
mbed_official	324:406fd2029f23	1002	* calculation is initialized by asserting CTRL[WAS] and then writing the seed into
mbed_official	324:406fd2029f23	1003	* the CRC data register.
mbed_official	324:406fd2029f23	1004	*/
mbed_official	324:406fd2029f23	1005	typedef union _hw_crc_ctrl
mbed_official	324:406fd2029f23	1006	{
mbed_official	324:406fd2029f23	1007	uint32_t U;
mbed_official	324:406fd2029f23	1008	struct _hw_crc_ctrl_bitfields
mbed_official	324:406fd2029f23	1009	{
mbed_official	324:406fd2029f23	1010	uint32_t RESERVED0 : 24; /!< [23:0] /
mbed_official	324:406fd2029f23	1011	uint32_t TCRC : 1; /!< [24] /
mbed_official	324:406fd2029f23	1012	uint32_t WAS : 1; /!< [25] Write CRC Data Register As Seed /
mbed_official	324:406fd2029f23	1013	uint32_t FXOR : 1; /!< [26] Complement Read Of CRC Data Register /
mbed_official	324:406fd2029f23	1014	uint32_t RESERVED1 : 1; /!< [27] /
mbed_official	324:406fd2029f23	1015	uint32_t TOTR : 2; /!< [29:28] Type Of Transpose For Read /
mbed_official	324:406fd2029f23	1016	uint32_t TOT : 2; /!< [31:30] Type Of Transpose For Writes /
mbed_official	324:406fd2029f23	1017	} B;
mbed_official	324:406fd2029f23	1018	} hw_crc_ctrl_t;
mbed_official	324:406fd2029f23	1019
mbed_official	324:406fd2029f23	1020	/*!
mbed_official	324:406fd2029f23	1021	* @name Constants and macros for entire CRC_CTRL register
mbed_official	324:406fd2029f23	1022	*/
mbed_official	324:406fd2029f23	1023	/@{/
mbed_official	324:406fd2029f23	1024	#define HW_CRC_CTRL_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	1025
mbed_official	324:406fd2029f23	1026	#define HW_CRC_CTRL(x) ((__IO hw_crc_ctrl_t ) HW_CRC_CTRL_ADDR(x))
mbed_official	324:406fd2029f23	1027	#define HW_CRC_CTRL_RD(x) (HW_CRC_CTRL(x).U)
mbed_official	324:406fd2029f23	1028	#define HW_CRC_CTRL_WR(x, v) (HW_CRC_CTRL(x).U = (v))
mbed_official	324:406fd2029f23	1029	#define HW_CRC_CTRL_SET(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1030	#define HW_CRC_CTRL_CLR(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1031	#define HW_CRC_CTRL_TOG(x, v) (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1032	/@}/
mbed_official	324:406fd2029f23	1033
mbed_official	324:406fd2029f23	1034	/*
mbed_official	324:406fd2029f23	1035	* Constants & macros for individual CRC_CTRL bitfields
mbed_official	324:406fd2029f23	1036	*/
mbed_official	324:406fd2029f23	1037
mbed_official	324:406fd2029f23	1038	/*!
mbed_official	324:406fd2029f23	1039	* @name Register CRC_CTRL, field TCRC[24] (RW)
mbed_official	324:406fd2029f23	1040	*
mbed_official	324:406fd2029f23	1041	* Width of CRC protocol.
mbed_official	324:406fd2029f23	1042	*
mbed_official	324:406fd2029f23	1043	* Values:
mbed_official	324:406fd2029f23	1044	* - 0 - 16-bit CRC protocol.
mbed_official	324:406fd2029f23	1045	* - 1 - 32-bit CRC protocol.
mbed_official	324:406fd2029f23	1046	*/
mbed_official	324:406fd2029f23	1047	/@{/
mbed_official	324:406fd2029f23	1048	#define BP_CRC_CTRL_TCRC (24U) /!< Bit position for CRC_CTRL_TCRC. /
mbed_official	324:406fd2029f23	1049	#define BM_CRC_CTRL_TCRC (0x01000000U) /!< Bit mask for CRC_CTRL_TCRC. /
mbed_official	324:406fd2029f23	1050	#define BS_CRC_CTRL_TCRC (1U) /!< Bit field size in bits for CRC_CTRL_TCRC. /
mbed_official	324:406fd2029f23	1051
mbed_official	324:406fd2029f23	1052	/! @brief Read current value of the CRC_CTRL_TCRC field. /
mbed_official	324:406fd2029f23	1053	#define BR_CRC_CTRL_TCRC(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC))
mbed_official	324:406fd2029f23	1054
mbed_official	324:406fd2029f23	1055	/! @brief Format value for bitfield CRC_CTRL_TCRC. /
mbed_official	324:406fd2029f23	1056	#define BF_CRC_CTRL_TCRC(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC)
mbed_official	324:406fd2029f23	1057
mbed_official	324:406fd2029f23	1058	/! @brief Set the TCRC field to a new value. /
mbed_official	324:406fd2029f23	1059	#define BW_CRC_CTRL_TCRC(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC) = (v))
mbed_official	324:406fd2029f23	1060	/@}/
mbed_official	324:406fd2029f23	1061
mbed_official	324:406fd2029f23	1062	/*!
mbed_official	324:406fd2029f23	1063	* @name Register CRC_CTRL, field WAS[25] (RW)
mbed_official	324:406fd2029f23	1064	*
mbed_official	324:406fd2029f23	1065	* When asserted, a value written to the CRC data register is considered a seed
mbed_official	324:406fd2029f23	1066	* value. When deasserted, a value written to the CRC data register is taken as
mbed_official	324:406fd2029f23	1067	* data for CRC computation.
mbed_official	324:406fd2029f23	1068	*
mbed_official	324:406fd2029f23	1069	* Values:
mbed_official	324:406fd2029f23	1070	* - 0 - Writes to the CRC data register are data values.
mbed_official	324:406fd2029f23	1071	* - 1 - Writes to the CRC data register are seed values.
mbed_official	324:406fd2029f23	1072	*/
mbed_official	324:406fd2029f23	1073	/@{/
mbed_official	324:406fd2029f23	1074	#define BP_CRC_CTRL_WAS (25U) /!< Bit position for CRC_CTRL_WAS. /
mbed_official	324:406fd2029f23	1075	#define BM_CRC_CTRL_WAS (0x02000000U) /!< Bit mask for CRC_CTRL_WAS. /
mbed_official	324:406fd2029f23	1076	#define BS_CRC_CTRL_WAS (1U) /!< Bit field size in bits for CRC_CTRL_WAS. /
mbed_official	324:406fd2029f23	1077
mbed_official	324:406fd2029f23	1078	/! @brief Read current value of the CRC_CTRL_WAS field. /
mbed_official	324:406fd2029f23	1079	#define BR_CRC_CTRL_WAS(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS))
mbed_official	324:406fd2029f23	1080
mbed_official	324:406fd2029f23	1081	/! @brief Format value for bitfield CRC_CTRL_WAS. /
mbed_official	324:406fd2029f23	1082	#define BF_CRC_CTRL_WAS(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS)
mbed_official	324:406fd2029f23	1083
mbed_official	324:406fd2029f23	1084	/! @brief Set the WAS field to a new value. /
mbed_official	324:406fd2029f23	1085	#define BW_CRC_CTRL_WAS(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS) = (v))
mbed_official	324:406fd2029f23	1086	/@}/
mbed_official	324:406fd2029f23	1087
mbed_official	324:406fd2029f23	1088	/*!
mbed_official	324:406fd2029f23	1089	* @name Register CRC_CTRL, field FXOR[26] (RW)
mbed_official	324:406fd2029f23	1090	*
mbed_official	324:406fd2029f23	1091	* Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
mbed_official	324:406fd2029f23	1092	* 0xFFFF. Asserting this bit enables on the fly complementing of read data.
mbed_official	324:406fd2029f23	1093	*
mbed_official	324:406fd2029f23	1094	* Values:
mbed_official	324:406fd2029f23	1095	* - 0 - No XOR on reading.
mbed_official	324:406fd2029f23	1096	* - 1 - Invert or complement the read value of the CRC Data register.
mbed_official	324:406fd2029f23	1097	*/
mbed_official	324:406fd2029f23	1098	/@{/
mbed_official	324:406fd2029f23	1099	#define BP_CRC_CTRL_FXOR (26U) /!< Bit position for CRC_CTRL_FXOR. /
mbed_official	324:406fd2029f23	1100	#define BM_CRC_CTRL_FXOR (0x04000000U) /!< Bit mask for CRC_CTRL_FXOR. /
mbed_official	324:406fd2029f23	1101	#define BS_CRC_CTRL_FXOR (1U) /!< Bit field size in bits for CRC_CTRL_FXOR. /
mbed_official	324:406fd2029f23	1102
mbed_official	324:406fd2029f23	1103	/! @brief Read current value of the CRC_CTRL_FXOR field. /
mbed_official	324:406fd2029f23	1104	#define BR_CRC_CTRL_FXOR(x) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR))
mbed_official	324:406fd2029f23	1105
mbed_official	324:406fd2029f23	1106	/! @brief Format value for bitfield CRC_CTRL_FXOR. /
mbed_official	324:406fd2029f23	1107	#define BF_CRC_CTRL_FXOR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR)
mbed_official	324:406fd2029f23	1108
mbed_official	324:406fd2029f23	1109	/! @brief Set the FXOR field to a new value. /
mbed_official	324:406fd2029f23	1110	#define BW_CRC_CTRL_FXOR(x, v) (BITBAND_ACCESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR) = (v))
mbed_official	324:406fd2029f23	1111	/@}/
mbed_official	324:406fd2029f23	1112
mbed_official	324:406fd2029f23	1113	/*!
mbed_official	324:406fd2029f23	1114	* @name Register CRC_CTRL, field TOTR[29:28] (RW)
mbed_official	324:406fd2029f23	1115	*
mbed_official	324:406fd2029f23	1116	* Identifies the transpose configuration of the value read from the CRC Data
mbed_official	324:406fd2029f23	1117	* register. See the description of the transpose feature for the available
mbed_official	324:406fd2029f23	1118	* transpose options.
mbed_official	324:406fd2029f23	1119	*
mbed_official	324:406fd2029f23	1120	* Values:
mbed_official	324:406fd2029f23	1121	* - 00 - No transposition.
mbed_official	324:406fd2029f23	1122	* - 01 - Bits in bytes are transposed; bytes are not transposed.
mbed_official	324:406fd2029f23	1123	* - 10 - Both bits in bytes and bytes are transposed.
mbed_official	324:406fd2029f23	1124	* - 11 - Only bytes are transposed; no bits in a byte are transposed.
mbed_official	324:406fd2029f23	1125	*/
mbed_official	324:406fd2029f23	1126	/@{/
mbed_official	324:406fd2029f23	1127	#define BP_CRC_CTRL_TOTR (28U) /!< Bit position for CRC_CTRL_TOTR. /
mbed_official	324:406fd2029f23	1128	#define BM_CRC_CTRL_TOTR (0x30000000U) /!< Bit mask for CRC_CTRL_TOTR. /
mbed_official	324:406fd2029f23	1129	#define BS_CRC_CTRL_TOTR (2U) /!< Bit field size in bits for CRC_CTRL_TOTR. /
mbed_official	324:406fd2029f23	1130
mbed_official	324:406fd2029f23	1131	/! @brief Read current value of the CRC_CTRL_TOTR field. /
mbed_official	324:406fd2029f23	1132	#define BR_CRC_CTRL_TOTR(x) (HW_CRC_CTRL(x).B.TOTR)
mbed_official	324:406fd2029f23	1133
mbed_official	324:406fd2029f23	1134	/! @brief Format value for bitfield CRC_CTRL_TOTR. /
mbed_official	324:406fd2029f23	1135	#define BF_CRC_CTRL_TOTR(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR)
mbed_official	324:406fd2029f23	1136
mbed_official	324:406fd2029f23	1137	/! @brief Set the TOTR field to a new value. /
mbed_official	324:406fd2029f23	1138	#define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) \| BF_CRC_CTRL_TOTR(v)))
mbed_official	324:406fd2029f23	1139	/@}/
mbed_official	324:406fd2029f23	1140
mbed_official	324:406fd2029f23	1141	/*!
mbed_official	324:406fd2029f23	1142	* @name Register CRC_CTRL, field TOT[31:30] (RW)
mbed_official	324:406fd2029f23	1143	*
mbed_official	324:406fd2029f23	1144	* Defines the transpose configuration of the data written to the CRC data
mbed_official	324:406fd2029f23	1145	* register. See the description of the transpose feature for the available transpose
mbed_official	324:406fd2029f23	1146	* options.
mbed_official	324:406fd2029f23	1147	*
mbed_official	324:406fd2029f23	1148	* Values:
mbed_official	324:406fd2029f23	1149	* - 00 - No transposition.
mbed_official	324:406fd2029f23	1150	* - 01 - Bits in bytes are transposed; bytes are not transposed.
mbed_official	324:406fd2029f23	1151	* - 10 - Both bits in bytes and bytes are transposed.
mbed_official	324:406fd2029f23	1152	* - 11 - Only bytes are transposed; no bits in a byte are transposed.
mbed_official	324:406fd2029f23	1153	*/
mbed_official	324:406fd2029f23	1154	/@{/
mbed_official	324:406fd2029f23	1155	#define BP_CRC_CTRL_TOT (30U) /!< Bit position for CRC_CTRL_TOT. /
mbed_official	324:406fd2029f23	1156	#define BM_CRC_CTRL_TOT (0xC0000000U) /!< Bit mask for CRC_CTRL_TOT. /
mbed_official	324:406fd2029f23	1157	#define BS_CRC_CTRL_TOT (2U) /!< Bit field size in bits for CRC_CTRL_TOT. /
mbed_official	324:406fd2029f23	1158
mbed_official	324:406fd2029f23	1159	/! @brief Read current value of the CRC_CTRL_TOT field. /
mbed_official	324:406fd2029f23	1160	#define BR_CRC_CTRL_TOT(x) (HW_CRC_CTRL(x).B.TOT)
mbed_official	324:406fd2029f23	1161
mbed_official	324:406fd2029f23	1162	/! @brief Format value for bitfield CRC_CTRL_TOT. /
mbed_official	324:406fd2029f23	1163	#define BF_CRC_CTRL_TOT(v) ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT)
mbed_official	324:406fd2029f23	1164
mbed_official	324:406fd2029f23	1165	/! @brief Set the TOT field to a new value. /
mbed_official	324:406fd2029f23	1166	#define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) \| BF_CRC_CTRL_TOT(v)))
mbed_official	324:406fd2029f23	1167	/@}/
mbed_official	324:406fd2029f23	1168	/*******************************************************************************
mbed_official	324:406fd2029f23	1169	* HW_CRC_CTRLHU - CRC_CTRLHU register.
mbed_official	324:406fd2029f23	1170	******************************************************************************/
mbed_official	324:406fd2029f23	1171
mbed_official	324:406fd2029f23	1172	/*!
mbed_official	324:406fd2029f23	1173	* @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
mbed_official	324:406fd2029f23	1174	*
mbed_official	324:406fd2029f23	1175	* Reset value: 0x00U
mbed_official	324:406fd2029f23	1176	*/
mbed_official	324:406fd2029f23	1177	typedef union _hw_crc_ctrlhu
mbed_official	324:406fd2029f23	1178	{
mbed_official	324:406fd2029f23	1179	uint8_t U;
mbed_official	324:406fd2029f23	1180	struct _hw_crc_ctrlhu_bitfields
mbed_official	324:406fd2029f23	1181	{
mbed_official	324:406fd2029f23	1182	uint8_t TCRC : 1; /!< [0] /
mbed_official	324:406fd2029f23	1183	uint8_t WAS : 1; /!< [1] /
mbed_official	324:406fd2029f23	1184	uint8_t FXOR : 1; /!< [2] /
mbed_official	324:406fd2029f23	1185	uint8_t RESERVED0 : 1; /!< [3] /
mbed_official	324:406fd2029f23	1186	uint8_t TOTR : 2; /!< [5:4] /
mbed_official	324:406fd2029f23	1187	uint8_t TOT : 2; /!< [7:6] /
mbed_official	324:406fd2029f23	1188	} B;
mbed_official	324:406fd2029f23	1189	} hw_crc_ctrlhu_t;
mbed_official	324:406fd2029f23	1190
mbed_official	324:406fd2029f23	1191	/*!
mbed_official	324:406fd2029f23	1192	* @name Constants and macros for entire CRC_CTRLHU register
mbed_official	324:406fd2029f23	1193	*/
mbed_official	324:406fd2029f23	1194	/@{/
mbed_official	324:406fd2029f23	1195	#define HW_CRC_CTRLHU_ADDR(x) ((x) + 0xBU)
mbed_official	324:406fd2029f23	1196
mbed_official	324:406fd2029f23	1197	#define HW_CRC_CTRLHU(x) ((__IO hw_crc_ctrlhu_t ) HW_CRC_CTRLHU_ADDR(x))
mbed_official	324:406fd2029f23	1198	#define HW_CRC_CTRLHU_RD(x) (HW_CRC_CTRLHU(x).U)
mbed_official	324:406fd2029f23	1199	#define HW_CRC_CTRLHU_WR(x, v) (HW_CRC_CTRLHU(x).U = (v))
mbed_official	324:406fd2029f23	1200	#define HW_CRC_CTRLHU_SET(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1201	#define HW_CRC_CTRLHU_CLR(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1202	#define HW_CRC_CTRLHU_TOG(x, v) (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1203	/@}/
mbed_official	324:406fd2029f23	1204
mbed_official	324:406fd2029f23	1205	/*
mbed_official	324:406fd2029f23	1206	* Constants & macros for individual CRC_CTRLHU bitfields
mbed_official	324:406fd2029f23	1207	*/
mbed_official	324:406fd2029f23	1208
mbed_official	324:406fd2029f23	1209	/*!
mbed_official	324:406fd2029f23	1210	* @name Register CRC_CTRLHU, field TCRC[0] (RW)
mbed_official	324:406fd2029f23	1211	*
mbed_official	324:406fd2029f23	1212	* Values:
mbed_official	324:406fd2029f23	1213	* - 0 - 16-bit CRC protocol.
mbed_official	324:406fd2029f23	1214	* - 1 - 32-bit CRC protocol.
mbed_official	324:406fd2029f23	1215	*/
mbed_official	324:406fd2029f23	1216	/@{/
mbed_official	324:406fd2029f23	1217	#define BP_CRC_CTRLHU_TCRC (0U) /!< Bit position for CRC_CTRLHU_TCRC. /
mbed_official	324:406fd2029f23	1218	#define BM_CRC_CTRLHU_TCRC (0x01U) /!< Bit mask for CRC_CTRLHU_TCRC. /
mbed_official	324:406fd2029f23	1219	#define BS_CRC_CTRLHU_TCRC (1U) /!< Bit field size in bits for CRC_CTRLHU_TCRC. /
mbed_official	324:406fd2029f23	1220
mbed_official	324:406fd2029f23	1221	/! @brief Read current value of the CRC_CTRLHU_TCRC field. /
mbed_official	324:406fd2029f23	1222	#define BR_CRC_CTRLHU_TCRC(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC))
mbed_official	324:406fd2029f23	1223
mbed_official	324:406fd2029f23	1224	/! @brief Format value for bitfield CRC_CTRLHU_TCRC. /
mbed_official	324:406fd2029f23	1225	#define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC)
mbed_official	324:406fd2029f23	1226
mbed_official	324:406fd2029f23	1227	/! @brief Set the TCRC field to a new value. /
mbed_official	324:406fd2029f23	1228	#define BW_CRC_CTRLHU_TCRC(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC) = (v))
mbed_official	324:406fd2029f23	1229	/@}/
mbed_official	324:406fd2029f23	1230
mbed_official	324:406fd2029f23	1231	/*!
mbed_official	324:406fd2029f23	1232	* @name Register CRC_CTRLHU, field WAS[1] (RW)
mbed_official	324:406fd2029f23	1233	*
mbed_official	324:406fd2029f23	1234	* Values:
mbed_official	324:406fd2029f23	1235	* - 0 - Writes to CRC data register are data values.
mbed_official	324:406fd2029f23	1236	* - 1 - Writes to CRC data reguster are seed values.
mbed_official	324:406fd2029f23	1237	*/
mbed_official	324:406fd2029f23	1238	/@{/
mbed_official	324:406fd2029f23	1239	#define BP_CRC_CTRLHU_WAS (1U) /!< Bit position for CRC_CTRLHU_WAS. /
mbed_official	324:406fd2029f23	1240	#define BM_CRC_CTRLHU_WAS (0x02U) /!< Bit mask for CRC_CTRLHU_WAS. /
mbed_official	324:406fd2029f23	1241	#define BS_CRC_CTRLHU_WAS (1U) /!< Bit field size in bits for CRC_CTRLHU_WAS. /
mbed_official	324:406fd2029f23	1242
mbed_official	324:406fd2029f23	1243	/! @brief Read current value of the CRC_CTRLHU_WAS field. /
mbed_official	324:406fd2029f23	1244	#define BR_CRC_CTRLHU_WAS(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS))
mbed_official	324:406fd2029f23	1245
mbed_official	324:406fd2029f23	1246	/! @brief Format value for bitfield CRC_CTRLHU_WAS. /
mbed_official	324:406fd2029f23	1247	#define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS)
mbed_official	324:406fd2029f23	1248
mbed_official	324:406fd2029f23	1249	/! @brief Set the WAS field to a new value. /
mbed_official	324:406fd2029f23	1250	#define BW_CRC_CTRLHU_WAS(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS) = (v))
mbed_official	324:406fd2029f23	1251	/@}/
mbed_official	324:406fd2029f23	1252
mbed_official	324:406fd2029f23	1253	/*!
mbed_official	324:406fd2029f23	1254	* @name Register CRC_CTRLHU, field FXOR[2] (RW)
mbed_official	324:406fd2029f23	1255	*
mbed_official	324:406fd2029f23	1256	* Values:
mbed_official	324:406fd2029f23	1257	* - 0 - No XOR on reading.
mbed_official	324:406fd2029f23	1258	* - 1 - Invert or complement the read value of CRC data register.
mbed_official	324:406fd2029f23	1259	*/
mbed_official	324:406fd2029f23	1260	/@{/
mbed_official	324:406fd2029f23	1261	#define BP_CRC_CTRLHU_FXOR (2U) /!< Bit position for CRC_CTRLHU_FXOR. /
mbed_official	324:406fd2029f23	1262	#define BM_CRC_CTRLHU_FXOR (0x04U) /!< Bit mask for CRC_CTRLHU_FXOR. /
mbed_official	324:406fd2029f23	1263	#define BS_CRC_CTRLHU_FXOR (1U) /!< Bit field size in bits for CRC_CTRLHU_FXOR. /
mbed_official	324:406fd2029f23	1264
mbed_official	324:406fd2029f23	1265	/! @brief Read current value of the CRC_CTRLHU_FXOR field. /
mbed_official	324:406fd2029f23	1266	#define BR_CRC_CTRLHU_FXOR(x) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR))
mbed_official	324:406fd2029f23	1267
mbed_official	324:406fd2029f23	1268	/! @brief Format value for bitfield CRC_CTRLHU_FXOR. /
mbed_official	324:406fd2029f23	1269	#define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR)
mbed_official	324:406fd2029f23	1270
mbed_official	324:406fd2029f23	1271	/! @brief Set the FXOR field to a new value. /
mbed_official	324:406fd2029f23	1272	#define BW_CRC_CTRLHU_FXOR(x, v) (BITBAND_ACCESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR) = (v))
mbed_official	324:406fd2029f23	1273	/@}/
mbed_official	324:406fd2029f23	1274
mbed_official	324:406fd2029f23	1275	/*!
mbed_official	324:406fd2029f23	1276	* @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
mbed_official	324:406fd2029f23	1277	*
mbed_official	324:406fd2029f23	1278	* Values:
mbed_official	324:406fd2029f23	1279	* - 00 - No Transposition.
mbed_official	324:406fd2029f23	1280	* - 01 - Bits in bytes are transposed, bytes are not transposed.
mbed_official	324:406fd2029f23	1281	* - 10 - Both bits in bytes and bytes are transposed.
mbed_official	324:406fd2029f23	1282	* - 11 - Only bytes are transposed; no bits in a byte are transposed.
mbed_official	324:406fd2029f23	1283	*/
mbed_official	324:406fd2029f23	1284	/@{/
mbed_official	324:406fd2029f23	1285	#define BP_CRC_CTRLHU_TOTR (4U) /!< Bit position for CRC_CTRLHU_TOTR. /
mbed_official	324:406fd2029f23	1286	#define BM_CRC_CTRLHU_TOTR (0x30U) /!< Bit mask for CRC_CTRLHU_TOTR. /
mbed_official	324:406fd2029f23	1287	#define BS_CRC_CTRLHU_TOTR (2U) /!< Bit field size in bits for CRC_CTRLHU_TOTR. /
mbed_official	324:406fd2029f23	1288
mbed_official	324:406fd2029f23	1289	/! @brief Read current value of the CRC_CTRLHU_TOTR field. /
mbed_official	324:406fd2029f23	1290	#define BR_CRC_CTRLHU_TOTR(x) (HW_CRC_CTRLHU(x).B.TOTR)
mbed_official	324:406fd2029f23	1291
mbed_official	324:406fd2029f23	1292	/! @brief Format value for bitfield CRC_CTRLHU_TOTR. /
mbed_official	324:406fd2029f23	1293	#define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR)
mbed_official	324:406fd2029f23	1294
mbed_official	324:406fd2029f23	1295	/! @brief Set the TOTR field to a new value. /
mbed_official	324:406fd2029f23	1296	#define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) \| BF_CRC_CTRLHU_TOTR(v)))
mbed_official	324:406fd2029f23	1297	/@}/
mbed_official	324:406fd2029f23	1298
mbed_official	324:406fd2029f23	1299	/*!
mbed_official	324:406fd2029f23	1300	* @name Register CRC_CTRLHU, field TOT[7:6] (RW)
mbed_official	324:406fd2029f23	1301	*
mbed_official	324:406fd2029f23	1302	* Values:
mbed_official	324:406fd2029f23	1303	* - 00 - No Transposition.
mbed_official	324:406fd2029f23	1304	* - 01 - Bits in bytes are transposed, bytes are not transposed.
mbed_official	324:406fd2029f23	1305	* - 10 - Both bits in bytes and bytes are transposed.
mbed_official	324:406fd2029f23	1306	* - 11 - Only bytes are transposed; no bits in a byte are transposed.
mbed_official	324:406fd2029f23	1307	*/
mbed_official	324:406fd2029f23	1308	/@{/
mbed_official	324:406fd2029f23	1309	#define BP_CRC_CTRLHU_TOT (6U) /!< Bit position for CRC_CTRLHU_TOT. /
mbed_official	324:406fd2029f23	1310	#define BM_CRC_CTRLHU_TOT (0xC0U) /!< Bit mask for CRC_CTRLHU_TOT. /
mbed_official	324:406fd2029f23	1311	#define BS_CRC_CTRLHU_TOT (2U) /!< Bit field size in bits for CRC_CTRLHU_TOT. /
mbed_official	324:406fd2029f23	1312
mbed_official	324:406fd2029f23	1313	/! @brief Read current value of the CRC_CTRLHU_TOT field. /
mbed_official	324:406fd2029f23	1314	#define BR_CRC_CTRLHU_TOT(x) (HW_CRC_CTRLHU(x).B.TOT)
mbed_official	324:406fd2029f23	1315
mbed_official	324:406fd2029f23	1316	/! @brief Format value for bitfield CRC_CTRLHU_TOT. /
mbed_official	324:406fd2029f23	1317	#define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT)
mbed_official	324:406fd2029f23	1318
mbed_official	324:406fd2029f23	1319	/! @brief Set the TOT field to a new value. /
mbed_official	324:406fd2029f23	1320	#define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) \| BF_CRC_CTRLHU_TOT(v)))
mbed_official	324:406fd2029f23	1321	/@}/
mbed_official	324:406fd2029f23	1322
mbed_official	324:406fd2029f23	1323	/*
mbed_official	324:406fd2029f23	1324	** Start of section using anonymous unions
mbed_official	324:406fd2029f23	1325	*/
mbed_official	324:406fd2029f23	1326
mbed_official	324:406fd2029f23	1327	#if defined(__ARMCC_VERSION)
mbed_official	324:406fd2029f23	1328	#pragma push
mbed_official	324:406fd2029f23	1329	#pragma anon_unions
mbed_official	324:406fd2029f23	1330	#elif defined(__CWCC__)
mbed_official	324:406fd2029f23	1331	#pragma push
mbed_official	324:406fd2029f23	1332	#pragma cpp_extensions on
mbed_official	324:406fd2029f23	1333	#elif defined(__GNUC__)
mbed_official	324:406fd2029f23	1334	/* anonymous unions are enabled by default */
mbed_official	324:406fd2029f23	1335	#elif defined(__IAR_SYSTEMS_ICC__)
mbed_official	324:406fd2029f23	1336	#pragma language=extended
mbed_official	324:406fd2029f23	1337	#else
mbed_official	324:406fd2029f23	1338	#error Not supported compiler type
mbed_official	324:406fd2029f23	1339	#endif
mbed_official	324:406fd2029f23	1340
mbed_official	324:406fd2029f23	1341	/*******************************************************************************
mbed_official	324:406fd2029f23	1342	* hw_crc_t - module struct
mbed_official	324:406fd2029f23	1343	******************************************************************************/
mbed_official	324:406fd2029f23	1344	/*!
mbed_official	324:406fd2029f23	1345	* @brief All CRC module registers.
mbed_official	324:406fd2029f23	1346	*/
mbed_official	324:406fd2029f23	1347	#pragma pack(1)
mbed_official	324:406fd2029f23	1348	typedef struct _hw_crc
mbed_official	324:406fd2029f23	1349	{
mbed_official	324:406fd2029f23	1350	union {
mbed_official	324:406fd2029f23	1351	struct {
mbed_official	324:406fd2029f23	1352	__IO hw_crc_datal_t DATAL; /!< [0x0] CRC_DATAL register. /
mbed_official	324:406fd2029f23	1353	__IO hw_crc_datah_t DATAH; /!< [0x2] CRC_DATAH register. /
mbed_official	324:406fd2029f23	1354	} ACCESS16BIT;
mbed_official	324:406fd2029f23	1355	struct {
mbed_official	324:406fd2029f23	1356	__IO hw_crc_datall_t DATALL; /!< [0x0] CRC_DATALL register. /
mbed_official	324:406fd2029f23	1357	__IO hw_crc_datalu_t DATALU; /!< [0x1] CRC_DATALU register. /
mbed_official	324:406fd2029f23	1358	__IO hw_crc_datahl_t DATAHL; /!< [0x2] CRC_DATAHL register. /
mbed_official	324:406fd2029f23	1359	__IO hw_crc_datahu_t DATAHU; /!< [0x3] CRC_DATAHU register. /
mbed_official	324:406fd2029f23	1360	} ACCESS8BIT;
mbed_official	324:406fd2029f23	1361	__IO hw_crc_data_t DATA; /!< [0x0] CRC Data register /
mbed_official	324:406fd2029f23	1362	};
mbed_official	324:406fd2029f23	1363	union {
mbed_official	324:406fd2029f23	1364	__IO hw_crc_gpoly_t GPOLY; /!< [0x4] CRC Polynomial register /
mbed_official	324:406fd2029f23	1365	struct {
mbed_official	324:406fd2029f23	1366	__IO hw_crc_gpolyl_t GPOLYL; /!< [0x4] CRC_GPOLYL register. /
mbed_official	324:406fd2029f23	1367	__IO hw_crc_gpolyh_t GPOLYH; /!< [0x6] CRC_GPOLYH register. /
mbed_official	324:406fd2029f23	1368	} GPOLY_ACCESS16BIT;
mbed_official	324:406fd2029f23	1369	struct {
mbed_official	324:406fd2029f23	1370	__IO hw_crc_gpolyll_t GPOLYLL; /!< [0x4] CRC_GPOLYLL register. /
mbed_official	324:406fd2029f23	1371	__IO hw_crc_gpolylu_t GPOLYLU; /!< [0x5] CRC_GPOLYLU register. /
mbed_official	324:406fd2029f23	1372	__IO hw_crc_gpolyhl_t GPOLYHL; /!< [0x6] CRC_GPOLYHL register. /
mbed_official	324:406fd2029f23	1373	__IO hw_crc_gpolyhu_t GPOLYHU; /!< [0x7] CRC_GPOLYHU register. /
mbed_official	324:406fd2029f23	1374	} GPOLY_ACCESS8BIT;
mbed_official	324:406fd2029f23	1375	};
mbed_official	324:406fd2029f23	1376	union {
mbed_official	324:406fd2029f23	1377	__IO hw_crc_ctrl_t CTRL; /!< [0x8] CRC Control register /
mbed_official	324:406fd2029f23	1378	struct {
mbed_official	324:406fd2029f23	1379	uint8_t _reserved0[3];
mbed_official	324:406fd2029f23	1380	__IO hw_crc_ctrlhu_t CTRLHU; /!< [0xB] CRC_CTRLHU register. /
mbed_official	324:406fd2029f23	1381	} CTRL_ACCESS8BIT;
mbed_official	324:406fd2029f23	1382	};
mbed_official	324:406fd2029f23	1383	} hw_crc_t;
mbed_official	324:406fd2029f23	1384	#pragma pack()
mbed_official	324:406fd2029f23	1385
mbed_official	324:406fd2029f23	1386	/! @brief Macro to access all CRC registers. /
mbed_official	324:406fd2029f23	1387	/! @param x CRC module instance base address. /
mbed_official	324:406fd2029f23	1388	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	1389	* use the '&' operator, like <code>&HW_CRC(CRC_BASE)</code>. */
mbed_official	324:406fd2029f23	1390	#define HW_CRC(x) ((hw_crc_t )(x))
mbed_official	324:406fd2029f23	1391
mbed_official	324:406fd2029f23	1392	/*
mbed_official	324:406fd2029f23	1393	** End of section using anonymous unions
mbed_official	324:406fd2029f23	1394	*/
mbed_official	324:406fd2029f23	1395
mbed_official	324:406fd2029f23	1396	#if defined(__ARMCC_VERSION)
mbed_official	324:406fd2029f23	1397	#pragma pop
mbed_official	324:406fd2029f23	1398	#elif defined(__CWCC__)
mbed_official	324:406fd2029f23	1399	#pragma pop
mbed_official	324:406fd2029f23	1400	#elif defined(__GNUC__)
mbed_official	324:406fd2029f23	1401	/* leave anonymous unions enabled */
mbed_official	324:406fd2029f23	1402	#elif defined(__IAR_SYSTEMS_ICC__)
mbed_official	324:406fd2029f23	1403	#pragma language=default
mbed_official	324:406fd2029f23	1404	#else
mbed_official	324:406fd2029f23	1405	#error Not supported compiler type
mbed_official	324:406fd2029f23	1406	#endif
mbed_official	324:406fd2029f23	1407
mbed_official	324:406fd2029f23	1408	#endif /* __HW_CRC_REGISTERS_H__ */
mbed_official	324:406fd2029f23	1409	/* EOF */