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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_cmt.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_CMT_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_CMT_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 CMT
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Carrier Modulator Transmitter
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
mbed_official 324:406fd2029f23 93 * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
mbed_official 324:406fd2029f23 94 * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
mbed_official 324:406fd2029f23 95 * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
mbed_official 324:406fd2029f23 96 * - HW_CMT_OC - CMT Output Control Register
mbed_official 324:406fd2029f23 97 * - HW_CMT_MSC - CMT Modulator Status and Control Register
mbed_official 324:406fd2029f23 98 * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
mbed_official 324:406fd2029f23 99 * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
mbed_official 324:406fd2029f23 100 * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
mbed_official 324:406fd2029f23 101 * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
mbed_official 324:406fd2029f23 102 * - HW_CMT_PPS - CMT Primary Prescaler Register
mbed_official 324:406fd2029f23 103 * - HW_CMT_DMA - CMT Direct Memory Access Register
mbed_official 324:406fd2029f23 104 *
mbed_official 324:406fd2029f23 105 * - hw_cmt_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 106 */
mbed_official 324:406fd2029f23 107
mbed_official 324:406fd2029f23 108 #define HW_CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
mbed_official 324:406fd2029f23 109
mbed_official 324:406fd2029f23 110 /*******************************************************************************
mbed_official 324:406fd2029f23 111 * HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
mbed_official 324:406fd2029f23 112 ******************************************************************************/
mbed_official 324:406fd2029f23 113
mbed_official 324:406fd2029f23 114 /*!
mbed_official 324:406fd2029f23 115 * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
mbed_official 324:406fd2029f23 116 *
mbed_official 324:406fd2029f23 117 * Reset value: 0x00U
mbed_official 324:406fd2029f23 118 *
mbed_official 324:406fd2029f23 119 * This data register contains the primary high value for generating the carrier
mbed_official 324:406fd2029f23 120 * output.
mbed_official 324:406fd2029f23 121 */
mbed_official 324:406fd2029f23 122 typedef union _hw_cmt_cgh1
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 uint8_t U;
mbed_official 324:406fd2029f23 125 struct _hw_cmt_cgh1_bitfields
mbed_official 324:406fd2029f23 126 {
mbed_official 324:406fd2029f23 127 uint8_t PH : 8; /*!< [7:0] Primary Carrier High Time Data Value */
mbed_official 324:406fd2029f23 128 } B;
mbed_official 324:406fd2029f23 129 } hw_cmt_cgh1_t;
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 /*!
mbed_official 324:406fd2029f23 132 * @name Constants and macros for entire CMT_CGH1 register
mbed_official 324:406fd2029f23 133 */
mbed_official 324:406fd2029f23 134 /*@{*/
mbed_official 324:406fd2029f23 135 #define HW_CMT_CGH1_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 136
mbed_official 324:406fd2029f23 137 #define HW_CMT_CGH1(x) (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR(x))
mbed_official 324:406fd2029f23 138 #define HW_CMT_CGH1_RD(x) (HW_CMT_CGH1(x).U)
mbed_official 324:406fd2029f23 139 #define HW_CMT_CGH1_WR(x, v) (HW_CMT_CGH1(x).U = (v))
mbed_official 324:406fd2029f23 140 #define HW_CMT_CGH1_SET(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) | (v)))
mbed_official 324:406fd2029f23 141 #define HW_CMT_CGH1_CLR(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 142 #define HW_CMT_CGH1_TOG(x, v) (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 143 /*@}*/
mbed_official 324:406fd2029f23 144
mbed_official 324:406fd2029f23 145 /*
mbed_official 324:406fd2029f23 146 * Constants & macros for individual CMT_CGH1 bitfields
mbed_official 324:406fd2029f23 147 */
mbed_official 324:406fd2029f23 148
mbed_official 324:406fd2029f23 149 /*!
mbed_official 324:406fd2029f23 150 * @name Register CMT_CGH1, field PH[7:0] (RW)
mbed_official 324:406fd2029f23 151 *
mbed_official 324:406fd2029f23 152 * Contains the number of input clocks required to generate the carrier high
mbed_official 324:406fd2029f23 153 * time period. When operating in Time mode, this register is always selected. When
mbed_official 324:406fd2029f23 154 * operating in FSK mode, this register and the secondary register pair are
mbed_official 324:406fd2029f23 155 * alternately selected under the control of the modulator. The primary carrier high
mbed_official 324:406fd2029f23 156 * time value is undefined out of reset. This register must be written to nonzero
mbed_official 324:406fd2029f23 157 * values before the carrier generator is enabled to avoid spurious results.
mbed_official 324:406fd2029f23 158 */
mbed_official 324:406fd2029f23 159 /*@{*/
mbed_official 324:406fd2029f23 160 #define BP_CMT_CGH1_PH (0U) /*!< Bit position for CMT_CGH1_PH. */
mbed_official 324:406fd2029f23 161 #define BM_CMT_CGH1_PH (0xFFU) /*!< Bit mask for CMT_CGH1_PH. */
mbed_official 324:406fd2029f23 162 #define BS_CMT_CGH1_PH (8U) /*!< Bit field size in bits for CMT_CGH1_PH. */
mbed_official 324:406fd2029f23 163
mbed_official 324:406fd2029f23 164 /*! @brief Read current value of the CMT_CGH1_PH field. */
mbed_official 324:406fd2029f23 165 #define BR_CMT_CGH1_PH(x) (HW_CMT_CGH1(x).U)
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 /*! @brief Format value for bitfield CMT_CGH1_PH. */
mbed_official 324:406fd2029f23 168 #define BF_CMT_CGH1_PH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH1_PH) & BM_CMT_CGH1_PH)
mbed_official 324:406fd2029f23 169
mbed_official 324:406fd2029f23 170 /*! @brief Set the PH field to a new value. */
mbed_official 324:406fd2029f23 171 #define BW_CMT_CGH1_PH(x, v) (HW_CMT_CGH1_WR(x, v))
mbed_official 324:406fd2029f23 172 /*@}*/
mbed_official 324:406fd2029f23 173
mbed_official 324:406fd2029f23 174 /*******************************************************************************
mbed_official 324:406fd2029f23 175 * HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
mbed_official 324:406fd2029f23 176 ******************************************************************************/
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*!
mbed_official 324:406fd2029f23 179 * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
mbed_official 324:406fd2029f23 180 *
mbed_official 324:406fd2029f23 181 * Reset value: 0x00U
mbed_official 324:406fd2029f23 182 *
mbed_official 324:406fd2029f23 183 * This data register contains the primary low value for generating the carrier
mbed_official 324:406fd2029f23 184 * output.
mbed_official 324:406fd2029f23 185 */
mbed_official 324:406fd2029f23 186 typedef union _hw_cmt_cgl1
mbed_official 324:406fd2029f23 187 {
mbed_official 324:406fd2029f23 188 uint8_t U;
mbed_official 324:406fd2029f23 189 struct _hw_cmt_cgl1_bitfields
mbed_official 324:406fd2029f23 190 {
mbed_official 324:406fd2029f23 191 uint8_t PL : 8; /*!< [7:0] Primary Carrier Low Time Data Value */
mbed_official 324:406fd2029f23 192 } B;
mbed_official 324:406fd2029f23 193 } hw_cmt_cgl1_t;
mbed_official 324:406fd2029f23 194
mbed_official 324:406fd2029f23 195 /*!
mbed_official 324:406fd2029f23 196 * @name Constants and macros for entire CMT_CGL1 register
mbed_official 324:406fd2029f23 197 */
mbed_official 324:406fd2029f23 198 /*@{*/
mbed_official 324:406fd2029f23 199 #define HW_CMT_CGL1_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 #define HW_CMT_CGL1(x) (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR(x))
mbed_official 324:406fd2029f23 202 #define HW_CMT_CGL1_RD(x) (HW_CMT_CGL1(x).U)
mbed_official 324:406fd2029f23 203 #define HW_CMT_CGL1_WR(x, v) (HW_CMT_CGL1(x).U = (v))
mbed_official 324:406fd2029f23 204 #define HW_CMT_CGL1_SET(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) | (v)))
mbed_official 324:406fd2029f23 205 #define HW_CMT_CGL1_CLR(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 206 #define HW_CMT_CGL1_TOG(x, v) (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 207 /*@}*/
mbed_official 324:406fd2029f23 208
mbed_official 324:406fd2029f23 209 /*
mbed_official 324:406fd2029f23 210 * Constants & macros for individual CMT_CGL1 bitfields
mbed_official 324:406fd2029f23 211 */
mbed_official 324:406fd2029f23 212
mbed_official 324:406fd2029f23 213 /*!
mbed_official 324:406fd2029f23 214 * @name Register CMT_CGL1, field PL[7:0] (RW)
mbed_official 324:406fd2029f23 215 *
mbed_official 324:406fd2029f23 216 * Contains the number of input clocks required to generate the carrier low time
mbed_official 324:406fd2029f23 217 * period. When operating in Time mode, this register is always selected. When
mbed_official 324:406fd2029f23 218 * operating in FSK mode, this register and the secondary register pair are
mbed_official 324:406fd2029f23 219 * alternately selected under the control of the modulator. The primary carrier low
mbed_official 324:406fd2029f23 220 * time value is undefined out of reset. This register must be written to nonzero
mbed_official 324:406fd2029f23 221 * values before the carrier generator is enabled to avoid spurious results.
mbed_official 324:406fd2029f23 222 */
mbed_official 324:406fd2029f23 223 /*@{*/
mbed_official 324:406fd2029f23 224 #define BP_CMT_CGL1_PL (0U) /*!< Bit position for CMT_CGL1_PL. */
mbed_official 324:406fd2029f23 225 #define BM_CMT_CGL1_PL (0xFFU) /*!< Bit mask for CMT_CGL1_PL. */
mbed_official 324:406fd2029f23 226 #define BS_CMT_CGL1_PL (8U) /*!< Bit field size in bits for CMT_CGL1_PL. */
mbed_official 324:406fd2029f23 227
mbed_official 324:406fd2029f23 228 /*! @brief Read current value of the CMT_CGL1_PL field. */
mbed_official 324:406fd2029f23 229 #define BR_CMT_CGL1_PL(x) (HW_CMT_CGL1(x).U)
mbed_official 324:406fd2029f23 230
mbed_official 324:406fd2029f23 231 /*! @brief Format value for bitfield CMT_CGL1_PL. */
mbed_official 324:406fd2029f23 232 #define BF_CMT_CGL1_PL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL1_PL) & BM_CMT_CGL1_PL)
mbed_official 324:406fd2029f23 233
mbed_official 324:406fd2029f23 234 /*! @brief Set the PL field to a new value. */
mbed_official 324:406fd2029f23 235 #define BW_CMT_CGL1_PL(x, v) (HW_CMT_CGL1_WR(x, v))
mbed_official 324:406fd2029f23 236 /*@}*/
mbed_official 324:406fd2029f23 237
mbed_official 324:406fd2029f23 238 /*******************************************************************************
mbed_official 324:406fd2029f23 239 * HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
mbed_official 324:406fd2029f23 240 ******************************************************************************/
mbed_official 324:406fd2029f23 241
mbed_official 324:406fd2029f23 242 /*!
mbed_official 324:406fd2029f23 243 * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
mbed_official 324:406fd2029f23 244 *
mbed_official 324:406fd2029f23 245 * Reset value: 0x00U
mbed_official 324:406fd2029f23 246 *
mbed_official 324:406fd2029f23 247 * This data register contains the secondary high value for generating the
mbed_official 324:406fd2029f23 248 * carrier output.
mbed_official 324:406fd2029f23 249 */
mbed_official 324:406fd2029f23 250 typedef union _hw_cmt_cgh2
mbed_official 324:406fd2029f23 251 {
mbed_official 324:406fd2029f23 252 uint8_t U;
mbed_official 324:406fd2029f23 253 struct _hw_cmt_cgh2_bitfields
mbed_official 324:406fd2029f23 254 {
mbed_official 324:406fd2029f23 255 uint8_t SH : 8; /*!< [7:0] Secondary Carrier High Time Data Value */
mbed_official 324:406fd2029f23 256 } B;
mbed_official 324:406fd2029f23 257 } hw_cmt_cgh2_t;
mbed_official 324:406fd2029f23 258
mbed_official 324:406fd2029f23 259 /*!
mbed_official 324:406fd2029f23 260 * @name Constants and macros for entire CMT_CGH2 register
mbed_official 324:406fd2029f23 261 */
mbed_official 324:406fd2029f23 262 /*@{*/
mbed_official 324:406fd2029f23 263 #define HW_CMT_CGH2_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 #define HW_CMT_CGH2(x) (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR(x))
mbed_official 324:406fd2029f23 266 #define HW_CMT_CGH2_RD(x) (HW_CMT_CGH2(x).U)
mbed_official 324:406fd2029f23 267 #define HW_CMT_CGH2_WR(x, v) (HW_CMT_CGH2(x).U = (v))
mbed_official 324:406fd2029f23 268 #define HW_CMT_CGH2_SET(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) | (v)))
mbed_official 324:406fd2029f23 269 #define HW_CMT_CGH2_CLR(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 270 #define HW_CMT_CGH2_TOG(x, v) (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 271 /*@}*/
mbed_official 324:406fd2029f23 272
mbed_official 324:406fd2029f23 273 /*
mbed_official 324:406fd2029f23 274 * Constants & macros for individual CMT_CGH2 bitfields
mbed_official 324:406fd2029f23 275 */
mbed_official 324:406fd2029f23 276
mbed_official 324:406fd2029f23 277 /*!
mbed_official 324:406fd2029f23 278 * @name Register CMT_CGH2, field SH[7:0] (RW)
mbed_official 324:406fd2029f23 279 *
mbed_official 324:406fd2029f23 280 * Contains the number of input clocks required to generate the carrier high
mbed_official 324:406fd2029f23 281 * time period. When operating in Time mode, this register is never selected. When
mbed_official 324:406fd2029f23 282 * operating in FSK mode, this register and the primary register pair are
mbed_official 324:406fd2029f23 283 * alternately selected under control of the modulator. The secondary carrier high time
mbed_official 324:406fd2029f23 284 * value is undefined out of reset. This register must be written to nonzero
mbed_official 324:406fd2029f23 285 * values before the carrier generator is enabled when operating in FSK mode.
mbed_official 324:406fd2029f23 286 */
mbed_official 324:406fd2029f23 287 /*@{*/
mbed_official 324:406fd2029f23 288 #define BP_CMT_CGH2_SH (0U) /*!< Bit position for CMT_CGH2_SH. */
mbed_official 324:406fd2029f23 289 #define BM_CMT_CGH2_SH (0xFFU) /*!< Bit mask for CMT_CGH2_SH. */
mbed_official 324:406fd2029f23 290 #define BS_CMT_CGH2_SH (8U) /*!< Bit field size in bits for CMT_CGH2_SH. */
mbed_official 324:406fd2029f23 291
mbed_official 324:406fd2029f23 292 /*! @brief Read current value of the CMT_CGH2_SH field. */
mbed_official 324:406fd2029f23 293 #define BR_CMT_CGH2_SH(x) (HW_CMT_CGH2(x).U)
mbed_official 324:406fd2029f23 294
mbed_official 324:406fd2029f23 295 /*! @brief Format value for bitfield CMT_CGH2_SH. */
mbed_official 324:406fd2029f23 296 #define BF_CMT_CGH2_SH(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGH2_SH) & BM_CMT_CGH2_SH)
mbed_official 324:406fd2029f23 297
mbed_official 324:406fd2029f23 298 /*! @brief Set the SH field to a new value. */
mbed_official 324:406fd2029f23 299 #define BW_CMT_CGH2_SH(x, v) (HW_CMT_CGH2_WR(x, v))
mbed_official 324:406fd2029f23 300 /*@}*/
mbed_official 324:406fd2029f23 301
mbed_official 324:406fd2029f23 302 /*******************************************************************************
mbed_official 324:406fd2029f23 303 * HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
mbed_official 324:406fd2029f23 304 ******************************************************************************/
mbed_official 324:406fd2029f23 305
mbed_official 324:406fd2029f23 306 /*!
mbed_official 324:406fd2029f23 307 * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
mbed_official 324:406fd2029f23 308 *
mbed_official 324:406fd2029f23 309 * Reset value: 0x00U
mbed_official 324:406fd2029f23 310 *
mbed_official 324:406fd2029f23 311 * This data register contains the secondary low value for generating the
mbed_official 324:406fd2029f23 312 * carrier output.
mbed_official 324:406fd2029f23 313 */
mbed_official 324:406fd2029f23 314 typedef union _hw_cmt_cgl2
mbed_official 324:406fd2029f23 315 {
mbed_official 324:406fd2029f23 316 uint8_t U;
mbed_official 324:406fd2029f23 317 struct _hw_cmt_cgl2_bitfields
mbed_official 324:406fd2029f23 318 {
mbed_official 324:406fd2029f23 319 uint8_t SL : 8; /*!< [7:0] Secondary Carrier Low Time Data Value */
mbed_official 324:406fd2029f23 320 } B;
mbed_official 324:406fd2029f23 321 } hw_cmt_cgl2_t;
mbed_official 324:406fd2029f23 322
mbed_official 324:406fd2029f23 323 /*!
mbed_official 324:406fd2029f23 324 * @name Constants and macros for entire CMT_CGL2 register
mbed_official 324:406fd2029f23 325 */
mbed_official 324:406fd2029f23 326 /*@{*/
mbed_official 324:406fd2029f23 327 #define HW_CMT_CGL2_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 328
mbed_official 324:406fd2029f23 329 #define HW_CMT_CGL2(x) (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR(x))
mbed_official 324:406fd2029f23 330 #define HW_CMT_CGL2_RD(x) (HW_CMT_CGL2(x).U)
mbed_official 324:406fd2029f23 331 #define HW_CMT_CGL2_WR(x, v) (HW_CMT_CGL2(x).U = (v))
mbed_official 324:406fd2029f23 332 #define HW_CMT_CGL2_SET(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) | (v)))
mbed_official 324:406fd2029f23 333 #define HW_CMT_CGL2_CLR(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 334 #define HW_CMT_CGL2_TOG(x, v) (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 335 /*@}*/
mbed_official 324:406fd2029f23 336
mbed_official 324:406fd2029f23 337 /*
mbed_official 324:406fd2029f23 338 * Constants & macros for individual CMT_CGL2 bitfields
mbed_official 324:406fd2029f23 339 */
mbed_official 324:406fd2029f23 340
mbed_official 324:406fd2029f23 341 /*!
mbed_official 324:406fd2029f23 342 * @name Register CMT_CGL2, field SL[7:0] (RW)
mbed_official 324:406fd2029f23 343 *
mbed_official 324:406fd2029f23 344 * Contains the number of input clocks required to generate the carrier low time
mbed_official 324:406fd2029f23 345 * period. When operating in Time mode, this register is never selected. When
mbed_official 324:406fd2029f23 346 * operating in FSK mode, this register and the primary register pair are
mbed_official 324:406fd2029f23 347 * alternately selected under the control of the modulator. The secondary carrier low time
mbed_official 324:406fd2029f23 348 * value is undefined out of reset. This register must be written to nonzero
mbed_official 324:406fd2029f23 349 * values before the carrier generator is enabled when operating in FSK mode.
mbed_official 324:406fd2029f23 350 */
mbed_official 324:406fd2029f23 351 /*@{*/
mbed_official 324:406fd2029f23 352 #define BP_CMT_CGL2_SL (0U) /*!< Bit position for CMT_CGL2_SL. */
mbed_official 324:406fd2029f23 353 #define BM_CMT_CGL2_SL (0xFFU) /*!< Bit mask for CMT_CGL2_SL. */
mbed_official 324:406fd2029f23 354 #define BS_CMT_CGL2_SL (8U) /*!< Bit field size in bits for CMT_CGL2_SL. */
mbed_official 324:406fd2029f23 355
mbed_official 324:406fd2029f23 356 /*! @brief Read current value of the CMT_CGL2_SL field. */
mbed_official 324:406fd2029f23 357 #define BR_CMT_CGL2_SL(x) (HW_CMT_CGL2(x).U)
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*! @brief Format value for bitfield CMT_CGL2_SL. */
mbed_official 324:406fd2029f23 360 #define BF_CMT_CGL2_SL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CGL2_SL) & BM_CMT_CGL2_SL)
mbed_official 324:406fd2029f23 361
mbed_official 324:406fd2029f23 362 /*! @brief Set the SL field to a new value. */
mbed_official 324:406fd2029f23 363 #define BW_CMT_CGL2_SL(x, v) (HW_CMT_CGL2_WR(x, v))
mbed_official 324:406fd2029f23 364 /*@}*/
mbed_official 324:406fd2029f23 365
mbed_official 324:406fd2029f23 366 /*******************************************************************************
mbed_official 324:406fd2029f23 367 * HW_CMT_OC - CMT Output Control Register
mbed_official 324:406fd2029f23 368 ******************************************************************************/
mbed_official 324:406fd2029f23 369
mbed_official 324:406fd2029f23 370 /*!
mbed_official 324:406fd2029f23 371 * @brief HW_CMT_OC - CMT Output Control Register (RW)
mbed_official 324:406fd2029f23 372 *
mbed_official 324:406fd2029f23 373 * Reset value: 0x00U
mbed_official 324:406fd2029f23 374 *
mbed_official 324:406fd2029f23 375 * This register is used to control the IRO signal of the CMT module.
mbed_official 324:406fd2029f23 376 */
mbed_official 324:406fd2029f23 377 typedef union _hw_cmt_oc
mbed_official 324:406fd2029f23 378 {
mbed_official 324:406fd2029f23 379 uint8_t U;
mbed_official 324:406fd2029f23 380 struct _hw_cmt_oc_bitfields
mbed_official 324:406fd2029f23 381 {
mbed_official 324:406fd2029f23 382 uint8_t RESERVED0 : 5; /*!< [4:0] */
mbed_official 324:406fd2029f23 383 uint8_t IROPEN : 1; /*!< [5] IRO Pin Enable */
mbed_official 324:406fd2029f23 384 uint8_t CMTPOL : 1; /*!< [6] CMT Output Polarity */
mbed_official 324:406fd2029f23 385 uint8_t IROL : 1; /*!< [7] IRO Latch Control */
mbed_official 324:406fd2029f23 386 } B;
mbed_official 324:406fd2029f23 387 } hw_cmt_oc_t;
mbed_official 324:406fd2029f23 388
mbed_official 324:406fd2029f23 389 /*!
mbed_official 324:406fd2029f23 390 * @name Constants and macros for entire CMT_OC register
mbed_official 324:406fd2029f23 391 */
mbed_official 324:406fd2029f23 392 /*@{*/
mbed_official 324:406fd2029f23 393 #define HW_CMT_OC_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395 #define HW_CMT_OC(x) (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR(x))
mbed_official 324:406fd2029f23 396 #define HW_CMT_OC_RD(x) (HW_CMT_OC(x).U)
mbed_official 324:406fd2029f23 397 #define HW_CMT_OC_WR(x, v) (HW_CMT_OC(x).U = (v))
mbed_official 324:406fd2029f23 398 #define HW_CMT_OC_SET(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) | (v)))
mbed_official 324:406fd2029f23 399 #define HW_CMT_OC_CLR(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 400 #define HW_CMT_OC_TOG(x, v) (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 401 /*@}*/
mbed_official 324:406fd2029f23 402
mbed_official 324:406fd2029f23 403 /*
mbed_official 324:406fd2029f23 404 * Constants & macros for individual CMT_OC bitfields
mbed_official 324:406fd2029f23 405 */
mbed_official 324:406fd2029f23 406
mbed_official 324:406fd2029f23 407 /*!
mbed_official 324:406fd2029f23 408 * @name Register CMT_OC, field IROPEN[5] (RW)
mbed_official 324:406fd2029f23 409 *
mbed_official 324:406fd2029f23 410 * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
mbed_official 324:406fd2029f23 411 * output that drives out either the CMT transmitter output or the state of IROL
mbed_official 324:406fd2029f23 412 * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
mbed_official 324:406fd2029f23 413 * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
mbed_official 324:406fd2029f23 414 * signal is disabled, it is in a high-impedance state and is unable to draw any
mbed_official 324:406fd2029f23 415 * current. This signal is disabled during reset.
mbed_official 324:406fd2029f23 416 *
mbed_official 324:406fd2029f23 417 * Values:
mbed_official 324:406fd2029f23 418 * - 0 - The IRO signal is disabled.
mbed_official 324:406fd2029f23 419 * - 1 - The IRO signal is enabled as output.
mbed_official 324:406fd2029f23 420 */
mbed_official 324:406fd2029f23 421 /*@{*/
mbed_official 324:406fd2029f23 422 #define BP_CMT_OC_IROPEN (5U) /*!< Bit position for CMT_OC_IROPEN. */
mbed_official 324:406fd2029f23 423 #define BM_CMT_OC_IROPEN (0x20U) /*!< Bit mask for CMT_OC_IROPEN. */
mbed_official 324:406fd2029f23 424 #define BS_CMT_OC_IROPEN (1U) /*!< Bit field size in bits for CMT_OC_IROPEN. */
mbed_official 324:406fd2029f23 425
mbed_official 324:406fd2029f23 426 /*! @brief Read current value of the CMT_OC_IROPEN field. */
mbed_official 324:406fd2029f23 427 #define BR_CMT_OC_IROPEN(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN))
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429 /*! @brief Format value for bitfield CMT_OC_IROPEN. */
mbed_official 324:406fd2029f23 430 #define BF_CMT_OC_IROPEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROPEN) & BM_CMT_OC_IROPEN)
mbed_official 324:406fd2029f23 431
mbed_official 324:406fd2029f23 432 /*! @brief Set the IROPEN field to a new value. */
mbed_official 324:406fd2029f23 433 #define BW_CMT_OC_IROPEN(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN) = (v))
mbed_official 324:406fd2029f23 434 /*@}*/
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*!
mbed_official 324:406fd2029f23 437 * @name Register CMT_OC, field CMTPOL[6] (RW)
mbed_official 324:406fd2029f23 438 *
mbed_official 324:406fd2029f23 439 * Controls the polarity of the IRO signal.
mbed_official 324:406fd2029f23 440 *
mbed_official 324:406fd2029f23 441 * Values:
mbed_official 324:406fd2029f23 442 * - 0 - The IRO signal is active-low.
mbed_official 324:406fd2029f23 443 * - 1 - The IRO signal is active-high.
mbed_official 324:406fd2029f23 444 */
mbed_official 324:406fd2029f23 445 /*@{*/
mbed_official 324:406fd2029f23 446 #define BP_CMT_OC_CMTPOL (6U) /*!< Bit position for CMT_OC_CMTPOL. */
mbed_official 324:406fd2029f23 447 #define BM_CMT_OC_CMTPOL (0x40U) /*!< Bit mask for CMT_OC_CMTPOL. */
mbed_official 324:406fd2029f23 448 #define BS_CMT_OC_CMTPOL (1U) /*!< Bit field size in bits for CMT_OC_CMTPOL. */
mbed_official 324:406fd2029f23 449
mbed_official 324:406fd2029f23 450 /*! @brief Read current value of the CMT_OC_CMTPOL field. */
mbed_official 324:406fd2029f23 451 #define BR_CMT_OC_CMTPOL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL))
mbed_official 324:406fd2029f23 452
mbed_official 324:406fd2029f23 453 /*! @brief Format value for bitfield CMT_OC_CMTPOL. */
mbed_official 324:406fd2029f23 454 #define BF_CMT_OC_CMTPOL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_CMTPOL) & BM_CMT_OC_CMTPOL)
mbed_official 324:406fd2029f23 455
mbed_official 324:406fd2029f23 456 /*! @brief Set the CMTPOL field to a new value. */
mbed_official 324:406fd2029f23 457 #define BW_CMT_OC_CMTPOL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL) = (v))
mbed_official 324:406fd2029f23 458 /*@}*/
mbed_official 324:406fd2029f23 459
mbed_official 324:406fd2029f23 460 /*!
mbed_official 324:406fd2029f23 461 * @name Register CMT_OC, field IROL[7] (RW)
mbed_official 324:406fd2029f23 462 *
mbed_official 324:406fd2029f23 463 * Reads the state of the IRO latch. Writing to IROL changes the state of the
mbed_official 324:406fd2029f23 464 * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
mbed_official 324:406fd2029f23 465 */
mbed_official 324:406fd2029f23 466 /*@{*/
mbed_official 324:406fd2029f23 467 #define BP_CMT_OC_IROL (7U) /*!< Bit position for CMT_OC_IROL. */
mbed_official 324:406fd2029f23 468 #define BM_CMT_OC_IROL (0x80U) /*!< Bit mask for CMT_OC_IROL. */
mbed_official 324:406fd2029f23 469 #define BS_CMT_OC_IROL (1U) /*!< Bit field size in bits for CMT_OC_IROL. */
mbed_official 324:406fd2029f23 470
mbed_official 324:406fd2029f23 471 /*! @brief Read current value of the CMT_OC_IROL field. */
mbed_official 324:406fd2029f23 472 #define BR_CMT_OC_IROL(x) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL))
mbed_official 324:406fd2029f23 473
mbed_official 324:406fd2029f23 474 /*! @brief Format value for bitfield CMT_OC_IROL. */
mbed_official 324:406fd2029f23 475 #define BF_CMT_OC_IROL(v) ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROL) & BM_CMT_OC_IROL)
mbed_official 324:406fd2029f23 476
mbed_official 324:406fd2029f23 477 /*! @brief Set the IROL field to a new value. */
mbed_official 324:406fd2029f23 478 #define BW_CMT_OC_IROL(x, v) (BITBAND_ACCESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL) = (v))
mbed_official 324:406fd2029f23 479 /*@}*/
mbed_official 324:406fd2029f23 480
mbed_official 324:406fd2029f23 481 /*******************************************************************************
mbed_official 324:406fd2029f23 482 * HW_CMT_MSC - CMT Modulator Status and Control Register
mbed_official 324:406fd2029f23 483 ******************************************************************************/
mbed_official 324:406fd2029f23 484
mbed_official 324:406fd2029f23 485 /*!
mbed_official 324:406fd2029f23 486 * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
mbed_official 324:406fd2029f23 487 *
mbed_official 324:406fd2029f23 488 * Reset value: 0x00U
mbed_official 324:406fd2029f23 489 *
mbed_official 324:406fd2029f23 490 * This register contains the modulator and carrier generator enable (MCGEN),
mbed_official 324:406fd2029f23 491 * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
mbed_official 324:406fd2029f23 492 * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
mbed_official 324:406fd2029f23 493 * (EOCF) status bit.
mbed_official 324:406fd2029f23 494 */
mbed_official 324:406fd2029f23 495 typedef union _hw_cmt_msc
mbed_official 324:406fd2029f23 496 {
mbed_official 324:406fd2029f23 497 uint8_t U;
mbed_official 324:406fd2029f23 498 struct _hw_cmt_msc_bitfields
mbed_official 324:406fd2029f23 499 {
mbed_official 324:406fd2029f23 500 uint8_t MCGEN : 1; /*!< [0] Modulator and Carrier Generator Enable */
mbed_official 324:406fd2029f23 501 uint8_t EOCIE : 1; /*!< [1] End of Cycle Interrupt Enable */
mbed_official 324:406fd2029f23 502 uint8_t FSK : 1; /*!< [2] FSK Mode Select */
mbed_official 324:406fd2029f23 503 uint8_t BASE : 1; /*!< [3] Baseband Enable */
mbed_official 324:406fd2029f23 504 uint8_t EXSPC : 1; /*!< [4] Extended Space Enable */
mbed_official 324:406fd2029f23 505 uint8_t CMTDIV : 2; /*!< [6:5] CMT Clock Divide Prescaler */
mbed_official 324:406fd2029f23 506 uint8_t EOCF : 1; /*!< [7] End Of Cycle Status Flag */
mbed_official 324:406fd2029f23 507 } B;
mbed_official 324:406fd2029f23 508 } hw_cmt_msc_t;
mbed_official 324:406fd2029f23 509
mbed_official 324:406fd2029f23 510 /*!
mbed_official 324:406fd2029f23 511 * @name Constants and macros for entire CMT_MSC register
mbed_official 324:406fd2029f23 512 */
mbed_official 324:406fd2029f23 513 /*@{*/
mbed_official 324:406fd2029f23 514 #define HW_CMT_MSC_ADDR(x) ((x) + 0x5U)
mbed_official 324:406fd2029f23 515
mbed_official 324:406fd2029f23 516 #define HW_CMT_MSC(x) (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR(x))
mbed_official 324:406fd2029f23 517 #define HW_CMT_MSC_RD(x) (HW_CMT_MSC(x).U)
mbed_official 324:406fd2029f23 518 #define HW_CMT_MSC_WR(x, v) (HW_CMT_MSC(x).U = (v))
mbed_official 324:406fd2029f23 519 #define HW_CMT_MSC_SET(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) | (v)))
mbed_official 324:406fd2029f23 520 #define HW_CMT_MSC_CLR(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 521 #define HW_CMT_MSC_TOG(x, v) (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 522 /*@}*/
mbed_official 324:406fd2029f23 523
mbed_official 324:406fd2029f23 524 /*
mbed_official 324:406fd2029f23 525 * Constants & macros for individual CMT_MSC bitfields
mbed_official 324:406fd2029f23 526 */
mbed_official 324:406fd2029f23 527
mbed_official 324:406fd2029f23 528 /*!
mbed_official 324:406fd2029f23 529 * @name Register CMT_MSC, field MCGEN[0] (RW)
mbed_official 324:406fd2029f23 530 *
mbed_official 324:406fd2029f23 531 * Setting MCGEN will initialize the carrier generator and modulator and will
mbed_official 324:406fd2029f23 532 * enable all clocks. When enabled, the carrier generator and modulator will
mbed_official 324:406fd2029f23 533 * function continuously. When MCGEN is cleared, the current modulator cycle will be
mbed_official 324:406fd2029f23 534 * allowed to expire before all carrier and modulator clocks are disabled to save
mbed_official 324:406fd2029f23 535 * power and the modulator output is forced low. To prevent spurious operation,
mbed_official 324:406fd2029f23 536 * the user should initialize all data and control registers before enabling the
mbed_official 324:406fd2029f23 537 * system.
mbed_official 324:406fd2029f23 538 *
mbed_official 324:406fd2029f23 539 * Values:
mbed_official 324:406fd2029f23 540 * - 0 - Modulator and carrier generator disabled
mbed_official 324:406fd2029f23 541 * - 1 - Modulator and carrier generator enabled
mbed_official 324:406fd2029f23 542 */
mbed_official 324:406fd2029f23 543 /*@{*/
mbed_official 324:406fd2029f23 544 #define BP_CMT_MSC_MCGEN (0U) /*!< Bit position for CMT_MSC_MCGEN. */
mbed_official 324:406fd2029f23 545 #define BM_CMT_MSC_MCGEN (0x01U) /*!< Bit mask for CMT_MSC_MCGEN. */
mbed_official 324:406fd2029f23 546 #define BS_CMT_MSC_MCGEN (1U) /*!< Bit field size in bits for CMT_MSC_MCGEN. */
mbed_official 324:406fd2029f23 547
mbed_official 324:406fd2029f23 548 /*! @brief Read current value of the CMT_MSC_MCGEN field. */
mbed_official 324:406fd2029f23 549 #define BR_CMT_MSC_MCGEN(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN))
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 /*! @brief Format value for bitfield CMT_MSC_MCGEN. */
mbed_official 324:406fd2029f23 552 #define BF_CMT_MSC_MCGEN(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_MCGEN) & BM_CMT_MSC_MCGEN)
mbed_official 324:406fd2029f23 553
mbed_official 324:406fd2029f23 554 /*! @brief Set the MCGEN field to a new value. */
mbed_official 324:406fd2029f23 555 #define BW_CMT_MSC_MCGEN(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN) = (v))
mbed_official 324:406fd2029f23 556 /*@}*/
mbed_official 324:406fd2029f23 557
mbed_official 324:406fd2029f23 558 /*!
mbed_official 324:406fd2029f23 559 * @name Register CMT_MSC, field EOCIE[1] (RW)
mbed_official 324:406fd2029f23 560 *
mbed_official 324:406fd2029f23 561 * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
mbed_official 324:406fd2029f23 562 *
mbed_official 324:406fd2029f23 563 * Values:
mbed_official 324:406fd2029f23 564 * - 0 - CPU interrupt is disabled.
mbed_official 324:406fd2029f23 565 * - 1 - CPU interrupt is enabled.
mbed_official 324:406fd2029f23 566 */
mbed_official 324:406fd2029f23 567 /*@{*/
mbed_official 324:406fd2029f23 568 #define BP_CMT_MSC_EOCIE (1U) /*!< Bit position for CMT_MSC_EOCIE. */
mbed_official 324:406fd2029f23 569 #define BM_CMT_MSC_EOCIE (0x02U) /*!< Bit mask for CMT_MSC_EOCIE. */
mbed_official 324:406fd2029f23 570 #define BS_CMT_MSC_EOCIE (1U) /*!< Bit field size in bits for CMT_MSC_EOCIE. */
mbed_official 324:406fd2029f23 571
mbed_official 324:406fd2029f23 572 /*! @brief Read current value of the CMT_MSC_EOCIE field. */
mbed_official 324:406fd2029f23 573 #define BR_CMT_MSC_EOCIE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE))
mbed_official 324:406fd2029f23 574
mbed_official 324:406fd2029f23 575 /*! @brief Format value for bitfield CMT_MSC_EOCIE. */
mbed_official 324:406fd2029f23 576 #define BF_CMT_MSC_EOCIE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EOCIE) & BM_CMT_MSC_EOCIE)
mbed_official 324:406fd2029f23 577
mbed_official 324:406fd2029f23 578 /*! @brief Set the EOCIE field to a new value. */
mbed_official 324:406fd2029f23 579 #define BW_CMT_MSC_EOCIE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE) = (v))
mbed_official 324:406fd2029f23 580 /*@}*/
mbed_official 324:406fd2029f23 581
mbed_official 324:406fd2029f23 582 /*!
mbed_official 324:406fd2029f23 583 * @name Register CMT_MSC, field FSK[2] (RW)
mbed_official 324:406fd2029f23 584 *
mbed_official 324:406fd2029f23 585 * Enables FSK operation.
mbed_official 324:406fd2029f23 586 *
mbed_official 324:406fd2029f23 587 * Values:
mbed_official 324:406fd2029f23 588 * - 0 - The CMT operates in Time or Baseband mode.
mbed_official 324:406fd2029f23 589 * - 1 - The CMT operates in FSK mode.
mbed_official 324:406fd2029f23 590 */
mbed_official 324:406fd2029f23 591 /*@{*/
mbed_official 324:406fd2029f23 592 #define BP_CMT_MSC_FSK (2U) /*!< Bit position for CMT_MSC_FSK. */
mbed_official 324:406fd2029f23 593 #define BM_CMT_MSC_FSK (0x04U) /*!< Bit mask for CMT_MSC_FSK. */
mbed_official 324:406fd2029f23 594 #define BS_CMT_MSC_FSK (1U) /*!< Bit field size in bits for CMT_MSC_FSK. */
mbed_official 324:406fd2029f23 595
mbed_official 324:406fd2029f23 596 /*! @brief Read current value of the CMT_MSC_FSK field. */
mbed_official 324:406fd2029f23 597 #define BR_CMT_MSC_FSK(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK))
mbed_official 324:406fd2029f23 598
mbed_official 324:406fd2029f23 599 /*! @brief Format value for bitfield CMT_MSC_FSK. */
mbed_official 324:406fd2029f23 600 #define BF_CMT_MSC_FSK(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_FSK) & BM_CMT_MSC_FSK)
mbed_official 324:406fd2029f23 601
mbed_official 324:406fd2029f23 602 /*! @brief Set the FSK field to a new value. */
mbed_official 324:406fd2029f23 603 #define BW_CMT_MSC_FSK(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK) = (v))
mbed_official 324:406fd2029f23 604 /*@}*/
mbed_official 324:406fd2029f23 605
mbed_official 324:406fd2029f23 606 /*!
mbed_official 324:406fd2029f23 607 * @name Register CMT_MSC, field BASE[3] (RW)
mbed_official 324:406fd2029f23 608 *
mbed_official 324:406fd2029f23 609 * When set, BASE disables the carrier generator and forces the carrier output
mbed_official 324:406fd2029f23 610 * high for generation of baseband protocols. When BASE is cleared, the carrier
mbed_official 324:406fd2029f23 611 * generator is enabled and the carrier output toggles at the frequency determined
mbed_official 324:406fd2029f23 612 * by values stored in the carrier data registers. This field is cleared by
mbed_official 324:406fd2029f23 613 * reset. This field is not double-buffered and must not be written to during a
mbed_official 324:406fd2029f23 614 * transmission.
mbed_official 324:406fd2029f23 615 *
mbed_official 324:406fd2029f23 616 * Values:
mbed_official 324:406fd2029f23 617 * - 0 - Baseband mode is disabled.
mbed_official 324:406fd2029f23 618 * - 1 - Baseband mode is enabled.
mbed_official 324:406fd2029f23 619 */
mbed_official 324:406fd2029f23 620 /*@{*/
mbed_official 324:406fd2029f23 621 #define BP_CMT_MSC_BASE (3U) /*!< Bit position for CMT_MSC_BASE. */
mbed_official 324:406fd2029f23 622 #define BM_CMT_MSC_BASE (0x08U) /*!< Bit mask for CMT_MSC_BASE. */
mbed_official 324:406fd2029f23 623 #define BS_CMT_MSC_BASE (1U) /*!< Bit field size in bits for CMT_MSC_BASE. */
mbed_official 324:406fd2029f23 624
mbed_official 324:406fd2029f23 625 /*! @brief Read current value of the CMT_MSC_BASE field. */
mbed_official 324:406fd2029f23 626 #define BR_CMT_MSC_BASE(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE))
mbed_official 324:406fd2029f23 627
mbed_official 324:406fd2029f23 628 /*! @brief Format value for bitfield CMT_MSC_BASE. */
mbed_official 324:406fd2029f23 629 #define BF_CMT_MSC_BASE(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_BASE) & BM_CMT_MSC_BASE)
mbed_official 324:406fd2029f23 630
mbed_official 324:406fd2029f23 631 /*! @brief Set the BASE field to a new value. */
mbed_official 324:406fd2029f23 632 #define BW_CMT_MSC_BASE(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE) = (v))
mbed_official 324:406fd2029f23 633 /*@}*/
mbed_official 324:406fd2029f23 634
mbed_official 324:406fd2029f23 635 /*!
mbed_official 324:406fd2029f23 636 * @name Register CMT_MSC, field EXSPC[4] (RW)
mbed_official 324:406fd2029f23 637 *
mbed_official 324:406fd2029f23 638 * Enables the extended space operation.
mbed_official 324:406fd2029f23 639 *
mbed_official 324:406fd2029f23 640 * Values:
mbed_official 324:406fd2029f23 641 * - 0 - Extended space is disabled.
mbed_official 324:406fd2029f23 642 * - 1 - Extended space is enabled.
mbed_official 324:406fd2029f23 643 */
mbed_official 324:406fd2029f23 644 /*@{*/
mbed_official 324:406fd2029f23 645 #define BP_CMT_MSC_EXSPC (4U) /*!< Bit position for CMT_MSC_EXSPC. */
mbed_official 324:406fd2029f23 646 #define BM_CMT_MSC_EXSPC (0x10U) /*!< Bit mask for CMT_MSC_EXSPC. */
mbed_official 324:406fd2029f23 647 #define BS_CMT_MSC_EXSPC (1U) /*!< Bit field size in bits for CMT_MSC_EXSPC. */
mbed_official 324:406fd2029f23 648
mbed_official 324:406fd2029f23 649 /*! @brief Read current value of the CMT_MSC_EXSPC field. */
mbed_official 324:406fd2029f23 650 #define BR_CMT_MSC_EXSPC(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC))
mbed_official 324:406fd2029f23 651
mbed_official 324:406fd2029f23 652 /*! @brief Format value for bitfield CMT_MSC_EXSPC. */
mbed_official 324:406fd2029f23 653 #define BF_CMT_MSC_EXSPC(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EXSPC) & BM_CMT_MSC_EXSPC)
mbed_official 324:406fd2029f23 654
mbed_official 324:406fd2029f23 655 /*! @brief Set the EXSPC field to a new value. */
mbed_official 324:406fd2029f23 656 #define BW_CMT_MSC_EXSPC(x, v) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC) = (v))
mbed_official 324:406fd2029f23 657 /*@}*/
mbed_official 324:406fd2029f23 658
mbed_official 324:406fd2029f23 659 /*!
mbed_official 324:406fd2029f23 660 * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
mbed_official 324:406fd2029f23 661 *
mbed_official 324:406fd2029f23 662 * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
mbed_official 324:406fd2029f23 663 * divided by 2 ,4, or 8 . This field must not be changed during a transmission
mbed_official 324:406fd2029f23 664 * because it is not double-buffered.
mbed_official 324:406fd2029f23 665 *
mbed_official 324:406fd2029f23 666 * Values:
mbed_official 324:406fd2029f23 667 * - 00 - IF * 1
mbed_official 324:406fd2029f23 668 * - 01 - IF * 2
mbed_official 324:406fd2029f23 669 * - 10 - IF * 4
mbed_official 324:406fd2029f23 670 * - 11 - IF * 8
mbed_official 324:406fd2029f23 671 */
mbed_official 324:406fd2029f23 672 /*@{*/
mbed_official 324:406fd2029f23 673 #define BP_CMT_MSC_CMTDIV (5U) /*!< Bit position for CMT_MSC_CMTDIV. */
mbed_official 324:406fd2029f23 674 #define BM_CMT_MSC_CMTDIV (0x60U) /*!< Bit mask for CMT_MSC_CMTDIV. */
mbed_official 324:406fd2029f23 675 #define BS_CMT_MSC_CMTDIV (2U) /*!< Bit field size in bits for CMT_MSC_CMTDIV. */
mbed_official 324:406fd2029f23 676
mbed_official 324:406fd2029f23 677 /*! @brief Read current value of the CMT_MSC_CMTDIV field. */
mbed_official 324:406fd2029f23 678 #define BR_CMT_MSC_CMTDIV(x) (HW_CMT_MSC(x).B.CMTDIV)
mbed_official 324:406fd2029f23 679
mbed_official 324:406fd2029f23 680 /*! @brief Format value for bitfield CMT_MSC_CMTDIV. */
mbed_official 324:406fd2029f23 681 #define BF_CMT_MSC_CMTDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_CMTDIV) & BM_CMT_MSC_CMTDIV)
mbed_official 324:406fd2029f23 682
mbed_official 324:406fd2029f23 683 /*! @brief Set the CMTDIV field to a new value. */
mbed_official 324:406fd2029f23 684 #define BW_CMT_MSC_CMTDIV(x, v) (HW_CMT_MSC_WR(x, (HW_CMT_MSC_RD(x) & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
mbed_official 324:406fd2029f23 685 /*@}*/
mbed_official 324:406fd2029f23 686
mbed_official 324:406fd2029f23 687 /*!
mbed_official 324:406fd2029f23 688 * @name Register CMT_MSC, field EOCF[7] (RO)
mbed_official 324:406fd2029f23 689 *
mbed_official 324:406fd2029f23 690 * Sets when: The modulator is not currently active and MCGEN is set to begin
mbed_official 324:406fd2029f23 691 * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
mbed_official 324:406fd2029f23 692 * set. This is recognized when a match occurs between the contents of the space
mbed_official 324:406fd2029f23 693 * period register and the down counter. At this time, the counter is
mbed_official 324:406fd2029f23 694 * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
mbed_official 324:406fd2029f23 695 * the space period register is loaded with, possibly new contents of the space
mbed_official 324:406fd2029f23 696 * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
mbed_official 324:406fd2029f23 697 * access of CMD2 or CMD4, or by the DMA transfer.
mbed_official 324:406fd2029f23 698 *
mbed_official 324:406fd2029f23 699 * Values:
mbed_official 324:406fd2029f23 700 * - 0 - End of modulation cycle has not occured since the flag last cleared.
mbed_official 324:406fd2029f23 701 * - 1 - End of modulator cycle has occurred.
mbed_official 324:406fd2029f23 702 */
mbed_official 324:406fd2029f23 703 /*@{*/
mbed_official 324:406fd2029f23 704 #define BP_CMT_MSC_EOCF (7U) /*!< Bit position for CMT_MSC_EOCF. */
mbed_official 324:406fd2029f23 705 #define BM_CMT_MSC_EOCF (0x80U) /*!< Bit mask for CMT_MSC_EOCF. */
mbed_official 324:406fd2029f23 706 #define BS_CMT_MSC_EOCF (1U) /*!< Bit field size in bits for CMT_MSC_EOCF. */
mbed_official 324:406fd2029f23 707
mbed_official 324:406fd2029f23 708 /*! @brief Read current value of the CMT_MSC_EOCF field. */
mbed_official 324:406fd2029f23 709 #define BR_CMT_MSC_EOCF(x) (BITBAND_ACCESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCF))
mbed_official 324:406fd2029f23 710 /*@}*/
mbed_official 324:406fd2029f23 711
mbed_official 324:406fd2029f23 712 /*******************************************************************************
mbed_official 324:406fd2029f23 713 * HW_CMT_CMD1 - CMT Modulator Data Register Mark High
mbed_official 324:406fd2029f23 714 ******************************************************************************/
mbed_official 324:406fd2029f23 715
mbed_official 324:406fd2029f23 716 /*!
mbed_official 324:406fd2029f23 717 * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
mbed_official 324:406fd2029f23 718 *
mbed_official 324:406fd2029f23 719 * Reset value: 0x00U
mbed_official 324:406fd2029f23 720 *
mbed_official 324:406fd2029f23 721 * The contents of this register are transferred to the modulator down counter
mbed_official 324:406fd2029f23 722 * upon the completion of a modulation period.
mbed_official 324:406fd2029f23 723 */
mbed_official 324:406fd2029f23 724 typedef union _hw_cmt_cmd1
mbed_official 324:406fd2029f23 725 {
mbed_official 324:406fd2029f23 726 uint8_t U;
mbed_official 324:406fd2029f23 727 struct _hw_cmt_cmd1_bitfields
mbed_official 324:406fd2029f23 728 {
mbed_official 324:406fd2029f23 729 uint8_t MB : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 730 } B;
mbed_official 324:406fd2029f23 731 } hw_cmt_cmd1_t;
mbed_official 324:406fd2029f23 732
mbed_official 324:406fd2029f23 733 /*!
mbed_official 324:406fd2029f23 734 * @name Constants and macros for entire CMT_CMD1 register
mbed_official 324:406fd2029f23 735 */
mbed_official 324:406fd2029f23 736 /*@{*/
mbed_official 324:406fd2029f23 737 #define HW_CMT_CMD1_ADDR(x) ((x) + 0x6U)
mbed_official 324:406fd2029f23 738
mbed_official 324:406fd2029f23 739 #define HW_CMT_CMD1(x) (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR(x))
mbed_official 324:406fd2029f23 740 #define HW_CMT_CMD1_RD(x) (HW_CMT_CMD1(x).U)
mbed_official 324:406fd2029f23 741 #define HW_CMT_CMD1_WR(x, v) (HW_CMT_CMD1(x).U = (v))
mbed_official 324:406fd2029f23 742 #define HW_CMT_CMD1_SET(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) | (v)))
mbed_official 324:406fd2029f23 743 #define HW_CMT_CMD1_CLR(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 744 #define HW_CMT_CMD1_TOG(x, v) (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 745 /*@}*/
mbed_official 324:406fd2029f23 746
mbed_official 324:406fd2029f23 747 /*
mbed_official 324:406fd2029f23 748 * Constants & macros for individual CMT_CMD1 bitfields
mbed_official 324:406fd2029f23 749 */
mbed_official 324:406fd2029f23 750
mbed_official 324:406fd2029f23 751 /*!
mbed_official 324:406fd2029f23 752 * @name Register CMT_CMD1, field MB[7:0] (RW)
mbed_official 324:406fd2029f23 753 *
mbed_official 324:406fd2029f23 754 * Controls the upper mark periods of the modulator for all modes.
mbed_official 324:406fd2029f23 755 */
mbed_official 324:406fd2029f23 756 /*@{*/
mbed_official 324:406fd2029f23 757 #define BP_CMT_CMD1_MB (0U) /*!< Bit position for CMT_CMD1_MB. */
mbed_official 324:406fd2029f23 758 #define BM_CMT_CMD1_MB (0xFFU) /*!< Bit mask for CMT_CMD1_MB. */
mbed_official 324:406fd2029f23 759 #define BS_CMT_CMD1_MB (8U) /*!< Bit field size in bits for CMT_CMD1_MB. */
mbed_official 324:406fd2029f23 760
mbed_official 324:406fd2029f23 761 /*! @brief Read current value of the CMT_CMD1_MB field. */
mbed_official 324:406fd2029f23 762 #define BR_CMT_CMD1_MB(x) (HW_CMT_CMD1(x).U)
mbed_official 324:406fd2029f23 763
mbed_official 324:406fd2029f23 764 /*! @brief Format value for bitfield CMT_CMD1_MB. */
mbed_official 324:406fd2029f23 765 #define BF_CMT_CMD1_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD1_MB) & BM_CMT_CMD1_MB)
mbed_official 324:406fd2029f23 766
mbed_official 324:406fd2029f23 767 /*! @brief Set the MB field to a new value. */
mbed_official 324:406fd2029f23 768 #define BW_CMT_CMD1_MB(x, v) (HW_CMT_CMD1_WR(x, v))
mbed_official 324:406fd2029f23 769 /*@}*/
mbed_official 324:406fd2029f23 770
mbed_official 324:406fd2029f23 771 /*******************************************************************************
mbed_official 324:406fd2029f23 772 * HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
mbed_official 324:406fd2029f23 773 ******************************************************************************/
mbed_official 324:406fd2029f23 774
mbed_official 324:406fd2029f23 775 /*!
mbed_official 324:406fd2029f23 776 * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
mbed_official 324:406fd2029f23 777 *
mbed_official 324:406fd2029f23 778 * Reset value: 0x00U
mbed_official 324:406fd2029f23 779 *
mbed_official 324:406fd2029f23 780 * The contents of this register are transferred to the modulator down counter
mbed_official 324:406fd2029f23 781 * upon the completion of a modulation period.
mbed_official 324:406fd2029f23 782 */
mbed_official 324:406fd2029f23 783 typedef union _hw_cmt_cmd2
mbed_official 324:406fd2029f23 784 {
mbed_official 324:406fd2029f23 785 uint8_t U;
mbed_official 324:406fd2029f23 786 struct _hw_cmt_cmd2_bitfields
mbed_official 324:406fd2029f23 787 {
mbed_official 324:406fd2029f23 788 uint8_t MB : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 789 } B;
mbed_official 324:406fd2029f23 790 } hw_cmt_cmd2_t;
mbed_official 324:406fd2029f23 791
mbed_official 324:406fd2029f23 792 /*!
mbed_official 324:406fd2029f23 793 * @name Constants and macros for entire CMT_CMD2 register
mbed_official 324:406fd2029f23 794 */
mbed_official 324:406fd2029f23 795 /*@{*/
mbed_official 324:406fd2029f23 796 #define HW_CMT_CMD2_ADDR(x) ((x) + 0x7U)
mbed_official 324:406fd2029f23 797
mbed_official 324:406fd2029f23 798 #define HW_CMT_CMD2(x) (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR(x))
mbed_official 324:406fd2029f23 799 #define HW_CMT_CMD2_RD(x) (HW_CMT_CMD2(x).U)
mbed_official 324:406fd2029f23 800 #define HW_CMT_CMD2_WR(x, v) (HW_CMT_CMD2(x).U = (v))
mbed_official 324:406fd2029f23 801 #define HW_CMT_CMD2_SET(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) | (v)))
mbed_official 324:406fd2029f23 802 #define HW_CMT_CMD2_CLR(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 803 #define HW_CMT_CMD2_TOG(x, v) (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 804 /*@}*/
mbed_official 324:406fd2029f23 805
mbed_official 324:406fd2029f23 806 /*
mbed_official 324:406fd2029f23 807 * Constants & macros for individual CMT_CMD2 bitfields
mbed_official 324:406fd2029f23 808 */
mbed_official 324:406fd2029f23 809
mbed_official 324:406fd2029f23 810 /*!
mbed_official 324:406fd2029f23 811 * @name Register CMT_CMD2, field MB[7:0] (RW)
mbed_official 324:406fd2029f23 812 *
mbed_official 324:406fd2029f23 813 * Controls the lower mark periods of the modulator for all modes.
mbed_official 324:406fd2029f23 814 */
mbed_official 324:406fd2029f23 815 /*@{*/
mbed_official 324:406fd2029f23 816 #define BP_CMT_CMD2_MB (0U) /*!< Bit position for CMT_CMD2_MB. */
mbed_official 324:406fd2029f23 817 #define BM_CMT_CMD2_MB (0xFFU) /*!< Bit mask for CMT_CMD2_MB. */
mbed_official 324:406fd2029f23 818 #define BS_CMT_CMD2_MB (8U) /*!< Bit field size in bits for CMT_CMD2_MB. */
mbed_official 324:406fd2029f23 819
mbed_official 324:406fd2029f23 820 /*! @brief Read current value of the CMT_CMD2_MB field. */
mbed_official 324:406fd2029f23 821 #define BR_CMT_CMD2_MB(x) (HW_CMT_CMD2(x).U)
mbed_official 324:406fd2029f23 822
mbed_official 324:406fd2029f23 823 /*! @brief Format value for bitfield CMT_CMD2_MB. */
mbed_official 324:406fd2029f23 824 #define BF_CMT_CMD2_MB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD2_MB) & BM_CMT_CMD2_MB)
mbed_official 324:406fd2029f23 825
mbed_official 324:406fd2029f23 826 /*! @brief Set the MB field to a new value. */
mbed_official 324:406fd2029f23 827 #define BW_CMT_CMD2_MB(x, v) (HW_CMT_CMD2_WR(x, v))
mbed_official 324:406fd2029f23 828 /*@}*/
mbed_official 324:406fd2029f23 829
mbed_official 324:406fd2029f23 830 /*******************************************************************************
mbed_official 324:406fd2029f23 831 * HW_CMT_CMD3 - CMT Modulator Data Register Space High
mbed_official 324:406fd2029f23 832 ******************************************************************************/
mbed_official 324:406fd2029f23 833
mbed_official 324:406fd2029f23 834 /*!
mbed_official 324:406fd2029f23 835 * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
mbed_official 324:406fd2029f23 836 *
mbed_official 324:406fd2029f23 837 * Reset value: 0x00U
mbed_official 324:406fd2029f23 838 *
mbed_official 324:406fd2029f23 839 * The contents of this register are transferred to the space period register
mbed_official 324:406fd2029f23 840 * upon the completion of a modulation period.
mbed_official 324:406fd2029f23 841 */
mbed_official 324:406fd2029f23 842 typedef union _hw_cmt_cmd3
mbed_official 324:406fd2029f23 843 {
mbed_official 324:406fd2029f23 844 uint8_t U;
mbed_official 324:406fd2029f23 845 struct _hw_cmt_cmd3_bitfields
mbed_official 324:406fd2029f23 846 {
mbed_official 324:406fd2029f23 847 uint8_t SB : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 848 } B;
mbed_official 324:406fd2029f23 849 } hw_cmt_cmd3_t;
mbed_official 324:406fd2029f23 850
mbed_official 324:406fd2029f23 851 /*!
mbed_official 324:406fd2029f23 852 * @name Constants and macros for entire CMT_CMD3 register
mbed_official 324:406fd2029f23 853 */
mbed_official 324:406fd2029f23 854 /*@{*/
mbed_official 324:406fd2029f23 855 #define HW_CMT_CMD3_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 856
mbed_official 324:406fd2029f23 857 #define HW_CMT_CMD3(x) (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR(x))
mbed_official 324:406fd2029f23 858 #define HW_CMT_CMD3_RD(x) (HW_CMT_CMD3(x).U)
mbed_official 324:406fd2029f23 859 #define HW_CMT_CMD3_WR(x, v) (HW_CMT_CMD3(x).U = (v))
mbed_official 324:406fd2029f23 860 #define HW_CMT_CMD3_SET(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) | (v)))
mbed_official 324:406fd2029f23 861 #define HW_CMT_CMD3_CLR(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 862 #define HW_CMT_CMD3_TOG(x, v) (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 863 /*@}*/
mbed_official 324:406fd2029f23 864
mbed_official 324:406fd2029f23 865 /*
mbed_official 324:406fd2029f23 866 * Constants & macros for individual CMT_CMD3 bitfields
mbed_official 324:406fd2029f23 867 */
mbed_official 324:406fd2029f23 868
mbed_official 324:406fd2029f23 869 /*!
mbed_official 324:406fd2029f23 870 * @name Register CMT_CMD3, field SB[7:0] (RW)
mbed_official 324:406fd2029f23 871 *
mbed_official 324:406fd2029f23 872 * Controls the upper space periods of the modulator for all modes.
mbed_official 324:406fd2029f23 873 */
mbed_official 324:406fd2029f23 874 /*@{*/
mbed_official 324:406fd2029f23 875 #define BP_CMT_CMD3_SB (0U) /*!< Bit position for CMT_CMD3_SB. */
mbed_official 324:406fd2029f23 876 #define BM_CMT_CMD3_SB (0xFFU) /*!< Bit mask for CMT_CMD3_SB. */
mbed_official 324:406fd2029f23 877 #define BS_CMT_CMD3_SB (8U) /*!< Bit field size in bits for CMT_CMD3_SB. */
mbed_official 324:406fd2029f23 878
mbed_official 324:406fd2029f23 879 /*! @brief Read current value of the CMT_CMD3_SB field. */
mbed_official 324:406fd2029f23 880 #define BR_CMT_CMD3_SB(x) (HW_CMT_CMD3(x).U)
mbed_official 324:406fd2029f23 881
mbed_official 324:406fd2029f23 882 /*! @brief Format value for bitfield CMT_CMD3_SB. */
mbed_official 324:406fd2029f23 883 #define BF_CMT_CMD3_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD3_SB) & BM_CMT_CMD3_SB)
mbed_official 324:406fd2029f23 884
mbed_official 324:406fd2029f23 885 /*! @brief Set the SB field to a new value. */
mbed_official 324:406fd2029f23 886 #define BW_CMT_CMD3_SB(x, v) (HW_CMT_CMD3_WR(x, v))
mbed_official 324:406fd2029f23 887 /*@}*/
mbed_official 324:406fd2029f23 888
mbed_official 324:406fd2029f23 889 /*******************************************************************************
mbed_official 324:406fd2029f23 890 * HW_CMT_CMD4 - CMT Modulator Data Register Space Low
mbed_official 324:406fd2029f23 891 ******************************************************************************/
mbed_official 324:406fd2029f23 892
mbed_official 324:406fd2029f23 893 /*!
mbed_official 324:406fd2029f23 894 * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
mbed_official 324:406fd2029f23 895 *
mbed_official 324:406fd2029f23 896 * Reset value: 0x00U
mbed_official 324:406fd2029f23 897 *
mbed_official 324:406fd2029f23 898 * The contents of this register are transferred to the space period register
mbed_official 324:406fd2029f23 899 * upon the completion of a modulation period.
mbed_official 324:406fd2029f23 900 */
mbed_official 324:406fd2029f23 901 typedef union _hw_cmt_cmd4
mbed_official 324:406fd2029f23 902 {
mbed_official 324:406fd2029f23 903 uint8_t U;
mbed_official 324:406fd2029f23 904 struct _hw_cmt_cmd4_bitfields
mbed_official 324:406fd2029f23 905 {
mbed_official 324:406fd2029f23 906 uint8_t SB : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 907 } B;
mbed_official 324:406fd2029f23 908 } hw_cmt_cmd4_t;
mbed_official 324:406fd2029f23 909
mbed_official 324:406fd2029f23 910 /*!
mbed_official 324:406fd2029f23 911 * @name Constants and macros for entire CMT_CMD4 register
mbed_official 324:406fd2029f23 912 */
mbed_official 324:406fd2029f23 913 /*@{*/
mbed_official 324:406fd2029f23 914 #define HW_CMT_CMD4_ADDR(x) ((x) + 0x9U)
mbed_official 324:406fd2029f23 915
mbed_official 324:406fd2029f23 916 #define HW_CMT_CMD4(x) (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR(x))
mbed_official 324:406fd2029f23 917 #define HW_CMT_CMD4_RD(x) (HW_CMT_CMD4(x).U)
mbed_official 324:406fd2029f23 918 #define HW_CMT_CMD4_WR(x, v) (HW_CMT_CMD4(x).U = (v))
mbed_official 324:406fd2029f23 919 #define HW_CMT_CMD4_SET(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) | (v)))
mbed_official 324:406fd2029f23 920 #define HW_CMT_CMD4_CLR(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 921 #define HW_CMT_CMD4_TOG(x, v) (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 922 /*@}*/
mbed_official 324:406fd2029f23 923
mbed_official 324:406fd2029f23 924 /*
mbed_official 324:406fd2029f23 925 * Constants & macros for individual CMT_CMD4 bitfields
mbed_official 324:406fd2029f23 926 */
mbed_official 324:406fd2029f23 927
mbed_official 324:406fd2029f23 928 /*!
mbed_official 324:406fd2029f23 929 * @name Register CMT_CMD4, field SB[7:0] (RW)
mbed_official 324:406fd2029f23 930 *
mbed_official 324:406fd2029f23 931 * Controls the lower space periods of the modulator for all modes.
mbed_official 324:406fd2029f23 932 */
mbed_official 324:406fd2029f23 933 /*@{*/
mbed_official 324:406fd2029f23 934 #define BP_CMT_CMD4_SB (0U) /*!< Bit position for CMT_CMD4_SB. */
mbed_official 324:406fd2029f23 935 #define BM_CMT_CMD4_SB (0xFFU) /*!< Bit mask for CMT_CMD4_SB. */
mbed_official 324:406fd2029f23 936 #define BS_CMT_CMD4_SB (8U) /*!< Bit field size in bits for CMT_CMD4_SB. */
mbed_official 324:406fd2029f23 937
mbed_official 324:406fd2029f23 938 /*! @brief Read current value of the CMT_CMD4_SB field. */
mbed_official 324:406fd2029f23 939 #define BR_CMT_CMD4_SB(x) (HW_CMT_CMD4(x).U)
mbed_official 324:406fd2029f23 940
mbed_official 324:406fd2029f23 941 /*! @brief Format value for bitfield CMT_CMD4_SB. */
mbed_official 324:406fd2029f23 942 #define BF_CMT_CMD4_SB(v) ((uint8_t)((uint8_t)(v) << BP_CMT_CMD4_SB) & BM_CMT_CMD4_SB)
mbed_official 324:406fd2029f23 943
mbed_official 324:406fd2029f23 944 /*! @brief Set the SB field to a new value. */
mbed_official 324:406fd2029f23 945 #define BW_CMT_CMD4_SB(x, v) (HW_CMT_CMD4_WR(x, v))
mbed_official 324:406fd2029f23 946 /*@}*/
mbed_official 324:406fd2029f23 947
mbed_official 324:406fd2029f23 948 /*******************************************************************************
mbed_official 324:406fd2029f23 949 * HW_CMT_PPS - CMT Primary Prescaler Register
mbed_official 324:406fd2029f23 950 ******************************************************************************/
mbed_official 324:406fd2029f23 951
mbed_official 324:406fd2029f23 952 /*!
mbed_official 324:406fd2029f23 953 * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
mbed_official 324:406fd2029f23 954 *
mbed_official 324:406fd2029f23 955 * Reset value: 0x00U
mbed_official 324:406fd2029f23 956 *
mbed_official 324:406fd2029f23 957 * This register is used to set the Primary Prescaler Divider field (PPSDIV).
mbed_official 324:406fd2029f23 958 */
mbed_official 324:406fd2029f23 959 typedef union _hw_cmt_pps
mbed_official 324:406fd2029f23 960 {
mbed_official 324:406fd2029f23 961 uint8_t U;
mbed_official 324:406fd2029f23 962 struct _hw_cmt_pps_bitfields
mbed_official 324:406fd2029f23 963 {
mbed_official 324:406fd2029f23 964 uint8_t PPSDIV : 4; /*!< [3:0] Primary Prescaler Divider */
mbed_official 324:406fd2029f23 965 uint8_t RESERVED0 : 4; /*!< [7:4] */
mbed_official 324:406fd2029f23 966 } B;
mbed_official 324:406fd2029f23 967 } hw_cmt_pps_t;
mbed_official 324:406fd2029f23 968
mbed_official 324:406fd2029f23 969 /*!
mbed_official 324:406fd2029f23 970 * @name Constants and macros for entire CMT_PPS register
mbed_official 324:406fd2029f23 971 */
mbed_official 324:406fd2029f23 972 /*@{*/
mbed_official 324:406fd2029f23 973 #define HW_CMT_PPS_ADDR(x) ((x) + 0xAU)
mbed_official 324:406fd2029f23 974
mbed_official 324:406fd2029f23 975 #define HW_CMT_PPS(x) (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR(x))
mbed_official 324:406fd2029f23 976 #define HW_CMT_PPS_RD(x) (HW_CMT_PPS(x).U)
mbed_official 324:406fd2029f23 977 #define HW_CMT_PPS_WR(x, v) (HW_CMT_PPS(x).U = (v))
mbed_official 324:406fd2029f23 978 #define HW_CMT_PPS_SET(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) | (v)))
mbed_official 324:406fd2029f23 979 #define HW_CMT_PPS_CLR(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 980 #define HW_CMT_PPS_TOG(x, v) (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 981 /*@}*/
mbed_official 324:406fd2029f23 982
mbed_official 324:406fd2029f23 983 /*
mbed_official 324:406fd2029f23 984 * Constants & macros for individual CMT_PPS bitfields
mbed_official 324:406fd2029f23 985 */
mbed_official 324:406fd2029f23 986
mbed_official 324:406fd2029f23 987 /*!
mbed_official 324:406fd2029f23 988 * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
mbed_official 324:406fd2029f23 989 *
mbed_official 324:406fd2029f23 990 * Divides the CMT clock to generate the Intermediate Frequency clock enable to
mbed_official 324:406fd2029f23 991 * the secondary prescaler.
mbed_official 324:406fd2029f23 992 *
mbed_official 324:406fd2029f23 993 * Values:
mbed_official 324:406fd2029f23 994 * - 0000 - Bus clock * 1
mbed_official 324:406fd2029f23 995 * - 0001 - Bus clock * 2
mbed_official 324:406fd2029f23 996 * - 0010 - Bus clock * 3
mbed_official 324:406fd2029f23 997 * - 0011 - Bus clock * 4
mbed_official 324:406fd2029f23 998 * - 0100 - Bus clock * 5
mbed_official 324:406fd2029f23 999 * - 0101 - Bus clock * 6
mbed_official 324:406fd2029f23 1000 * - 0110 - Bus clock * 7
mbed_official 324:406fd2029f23 1001 * - 0111 - Bus clock * 8
mbed_official 324:406fd2029f23 1002 * - 1000 - Bus clock * 9
mbed_official 324:406fd2029f23 1003 * - 1001 - Bus clock * 10
mbed_official 324:406fd2029f23 1004 * - 1010 - Bus clock * 11
mbed_official 324:406fd2029f23 1005 * - 1011 - Bus clock * 12
mbed_official 324:406fd2029f23 1006 * - 1100 - Bus clock * 13
mbed_official 324:406fd2029f23 1007 * - 1101 - Bus clock * 14
mbed_official 324:406fd2029f23 1008 * - 1110 - Bus clock * 15
mbed_official 324:406fd2029f23 1009 * - 1111 - Bus clock * 16
mbed_official 324:406fd2029f23 1010 */
mbed_official 324:406fd2029f23 1011 /*@{*/
mbed_official 324:406fd2029f23 1012 #define BP_CMT_PPS_PPSDIV (0U) /*!< Bit position for CMT_PPS_PPSDIV. */
mbed_official 324:406fd2029f23 1013 #define BM_CMT_PPS_PPSDIV (0x0FU) /*!< Bit mask for CMT_PPS_PPSDIV. */
mbed_official 324:406fd2029f23 1014 #define BS_CMT_PPS_PPSDIV (4U) /*!< Bit field size in bits for CMT_PPS_PPSDIV. */
mbed_official 324:406fd2029f23 1015
mbed_official 324:406fd2029f23 1016 /*! @brief Read current value of the CMT_PPS_PPSDIV field. */
mbed_official 324:406fd2029f23 1017 #define BR_CMT_PPS_PPSDIV(x) (HW_CMT_PPS(x).B.PPSDIV)
mbed_official 324:406fd2029f23 1018
mbed_official 324:406fd2029f23 1019 /*! @brief Format value for bitfield CMT_PPS_PPSDIV. */
mbed_official 324:406fd2029f23 1020 #define BF_CMT_PPS_PPSDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_PPS_PPSDIV) & BM_CMT_PPS_PPSDIV)
mbed_official 324:406fd2029f23 1021
mbed_official 324:406fd2029f23 1022 /*! @brief Set the PPSDIV field to a new value. */
mbed_official 324:406fd2029f23 1023 #define BW_CMT_PPS_PPSDIV(x, v) (HW_CMT_PPS_WR(x, (HW_CMT_PPS_RD(x) & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
mbed_official 324:406fd2029f23 1024 /*@}*/
mbed_official 324:406fd2029f23 1025
mbed_official 324:406fd2029f23 1026 /*******************************************************************************
mbed_official 324:406fd2029f23 1027 * HW_CMT_DMA - CMT Direct Memory Access Register
mbed_official 324:406fd2029f23 1028 ******************************************************************************/
mbed_official 324:406fd2029f23 1029
mbed_official 324:406fd2029f23 1030 /*!
mbed_official 324:406fd2029f23 1031 * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
mbed_official 324:406fd2029f23 1032 *
mbed_official 324:406fd2029f23 1033 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1034 *
mbed_official 324:406fd2029f23 1035 * This register is used to enable/disable direct memory access (DMA).
mbed_official 324:406fd2029f23 1036 */
mbed_official 324:406fd2029f23 1037 typedef union _hw_cmt_dma
mbed_official 324:406fd2029f23 1038 {
mbed_official 324:406fd2029f23 1039 uint8_t U;
mbed_official 324:406fd2029f23 1040 struct _hw_cmt_dma_bitfields
mbed_official 324:406fd2029f23 1041 {
mbed_official 324:406fd2029f23 1042 uint8_t DMA : 1; /*!< [0] DMA Enable */
mbed_official 324:406fd2029f23 1043 uint8_t RESERVED0 : 7; /*!< [7:1] */
mbed_official 324:406fd2029f23 1044 } B;
mbed_official 324:406fd2029f23 1045 } hw_cmt_dma_t;
mbed_official 324:406fd2029f23 1046
mbed_official 324:406fd2029f23 1047 /*!
mbed_official 324:406fd2029f23 1048 * @name Constants and macros for entire CMT_DMA register
mbed_official 324:406fd2029f23 1049 */
mbed_official 324:406fd2029f23 1050 /*@{*/
mbed_official 324:406fd2029f23 1051 #define HW_CMT_DMA_ADDR(x) ((x) + 0xBU)
mbed_official 324:406fd2029f23 1052
mbed_official 324:406fd2029f23 1053 #define HW_CMT_DMA(x) (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR(x))
mbed_official 324:406fd2029f23 1054 #define HW_CMT_DMA_RD(x) (HW_CMT_DMA(x).U)
mbed_official 324:406fd2029f23 1055 #define HW_CMT_DMA_WR(x, v) (HW_CMT_DMA(x).U = (v))
mbed_official 324:406fd2029f23 1056 #define HW_CMT_DMA_SET(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) | (v)))
mbed_official 324:406fd2029f23 1057 #define HW_CMT_DMA_CLR(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1058 #define HW_CMT_DMA_TOG(x, v) (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1059 /*@}*/
mbed_official 324:406fd2029f23 1060
mbed_official 324:406fd2029f23 1061 /*
mbed_official 324:406fd2029f23 1062 * Constants & macros for individual CMT_DMA bitfields
mbed_official 324:406fd2029f23 1063 */
mbed_official 324:406fd2029f23 1064
mbed_official 324:406fd2029f23 1065 /*!
mbed_official 324:406fd2029f23 1066 * @name Register CMT_DMA, field DMA[0] (RW)
mbed_official 324:406fd2029f23 1067 *
mbed_official 324:406fd2029f23 1068 * Enables the DMA protocol.
mbed_official 324:406fd2029f23 1069 *
mbed_official 324:406fd2029f23 1070 * Values:
mbed_official 324:406fd2029f23 1071 * - 0 - DMA transfer request and done are disabled.
mbed_official 324:406fd2029f23 1072 * - 1 - DMA transfer request and done are enabled.
mbed_official 324:406fd2029f23 1073 */
mbed_official 324:406fd2029f23 1074 /*@{*/
mbed_official 324:406fd2029f23 1075 #define BP_CMT_DMA_DMA (0U) /*!< Bit position for CMT_DMA_DMA. */
mbed_official 324:406fd2029f23 1076 #define BM_CMT_DMA_DMA (0x01U) /*!< Bit mask for CMT_DMA_DMA. */
mbed_official 324:406fd2029f23 1077 #define BS_CMT_DMA_DMA (1U) /*!< Bit field size in bits for CMT_DMA_DMA. */
mbed_official 324:406fd2029f23 1078
mbed_official 324:406fd2029f23 1079 /*! @brief Read current value of the CMT_DMA_DMA field. */
mbed_official 324:406fd2029f23 1080 #define BR_CMT_DMA_DMA(x) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA))
mbed_official 324:406fd2029f23 1081
mbed_official 324:406fd2029f23 1082 /*! @brief Format value for bitfield CMT_DMA_DMA. */
mbed_official 324:406fd2029f23 1083 #define BF_CMT_DMA_DMA(v) ((uint8_t)((uint8_t)(v) << BP_CMT_DMA_DMA) & BM_CMT_DMA_DMA)
mbed_official 324:406fd2029f23 1084
mbed_official 324:406fd2029f23 1085 /*! @brief Set the DMA field to a new value. */
mbed_official 324:406fd2029f23 1086 #define BW_CMT_DMA_DMA(x, v) (BITBAND_ACCESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA) = (v))
mbed_official 324:406fd2029f23 1087 /*@}*/
mbed_official 324:406fd2029f23 1088
mbed_official 324:406fd2029f23 1089 /*******************************************************************************
mbed_official 324:406fd2029f23 1090 * hw_cmt_t - module struct
mbed_official 324:406fd2029f23 1091 ******************************************************************************/
mbed_official 324:406fd2029f23 1092 /*!
mbed_official 324:406fd2029f23 1093 * @brief All CMT module registers.
mbed_official 324:406fd2029f23 1094 */
mbed_official 324:406fd2029f23 1095 #pragma pack(1)
mbed_official 324:406fd2029f23 1096 typedef struct _hw_cmt
mbed_official 324:406fd2029f23 1097 {
mbed_official 324:406fd2029f23 1098 __IO hw_cmt_cgh1_t CGH1; /*!< [0x0] CMT Carrier Generator High Data Register 1 */
mbed_official 324:406fd2029f23 1099 __IO hw_cmt_cgl1_t CGL1; /*!< [0x1] CMT Carrier Generator Low Data Register 1 */
mbed_official 324:406fd2029f23 1100 __IO hw_cmt_cgh2_t CGH2; /*!< [0x2] CMT Carrier Generator High Data Register 2 */
mbed_official 324:406fd2029f23 1101 __IO hw_cmt_cgl2_t CGL2; /*!< [0x3] CMT Carrier Generator Low Data Register 2 */
mbed_official 324:406fd2029f23 1102 __IO hw_cmt_oc_t OC; /*!< [0x4] CMT Output Control Register */
mbed_official 324:406fd2029f23 1103 __IO hw_cmt_msc_t MSC; /*!< [0x5] CMT Modulator Status and Control Register */
mbed_official 324:406fd2029f23 1104 __IO hw_cmt_cmd1_t CMD1; /*!< [0x6] CMT Modulator Data Register Mark High */
mbed_official 324:406fd2029f23 1105 __IO hw_cmt_cmd2_t CMD2; /*!< [0x7] CMT Modulator Data Register Mark Low */
mbed_official 324:406fd2029f23 1106 __IO hw_cmt_cmd3_t CMD3; /*!< [0x8] CMT Modulator Data Register Space High */
mbed_official 324:406fd2029f23 1107 __IO hw_cmt_cmd4_t CMD4; /*!< [0x9] CMT Modulator Data Register Space Low */
mbed_official 324:406fd2029f23 1108 __IO hw_cmt_pps_t PPS; /*!< [0xA] CMT Primary Prescaler Register */
mbed_official 324:406fd2029f23 1109 __IO hw_cmt_dma_t DMA; /*!< [0xB] CMT Direct Memory Access Register */
mbed_official 324:406fd2029f23 1110 } hw_cmt_t;
mbed_official 324:406fd2029f23 1111 #pragma pack()
mbed_official 324:406fd2029f23 1112
mbed_official 324:406fd2029f23 1113 /*! @brief Macro to access all CMT registers. */
mbed_official 324:406fd2029f23 1114 /*! @param x CMT module instance base address. */
mbed_official 324:406fd2029f23 1115 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 1116 * use the '&' operator, like <code>&HW_CMT(CMT_BASE)</code>. */
mbed_official 324:406fd2029f23 1117 #define HW_CMT(x) (*(hw_cmt_t *)(x))
mbed_official 324:406fd2029f23 1118
mbed_official 324:406fd2029f23 1119 #endif /* __HW_CMT_REGISTERS_H__ */
mbed_official 324:406fd2029f23 1120 /* EOF */