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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_can.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-02-10
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-08-12)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	50	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	51	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	52	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	53	** System initialization updated.
mbed_official	324:406fd2029f23	54	** MCG - registers updated.
mbed_official	324:406fd2029f23	55	** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-09)
mbed_official	324:406fd2029f23	59	** DMA - EARS register removed.
mbed_official	324:406fd2029f23	60	** AIPS0, AIPS1 - MPRA register updated.
mbed_official	324:406fd2029f23	61	** - rev. 2.3 (2014-01-24)
mbed_official	324:406fd2029f23	62	** Update according to reference manual rev. 2
mbed_official	324:406fd2029f23	63	** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official	324:406fd2029f23	64	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	65	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	66	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	67	** - rev. 2.5 (2014-02-10)
mbed_official	324:406fd2029f23	68	** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official	324:406fd2029f23	69	** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official	324:406fd2029f23	70	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	71	**
mbed_official	324:406fd2029f23	72	** ###################################################################
mbed_official	324:406fd2029f23	73	*/
mbed_official	324:406fd2029f23	74
mbed_official	324:406fd2029f23	75	/*
mbed_official	324:406fd2029f23	76	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	77	*
mbed_official	324:406fd2029f23	78	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	79	*/
mbed_official	324:406fd2029f23	80	#ifndef __HW_CAN_REGISTERS_H__
mbed_official	324:406fd2029f23	81	#define __HW_CAN_REGISTERS_H__
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	#include "MK64F12.h"
mbed_official	324:406fd2029f23	84	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	85
mbed_official	324:406fd2029f23	86	/*
mbed_official	324:406fd2029f23	87	* MK64F12 CAN
mbed_official	324:406fd2029f23	88	*
mbed_official	324:406fd2029f23	89	* Flex Controller Area Network module
mbed_official	324:406fd2029f23	90	*
mbed_official	324:406fd2029f23	91	* Registers defined in this header file:
mbed_official	324:406fd2029f23	92	* - HW_CAN_MCR - Module Configuration Register
mbed_official	324:406fd2029f23	93	* - HW_CAN_CTRL1 - Control 1 register
mbed_official	324:406fd2029f23	94	* - HW_CAN_TIMER - Free Running Timer
mbed_official	324:406fd2029f23	95	* - HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
mbed_official	324:406fd2029f23	96	* - HW_CAN_RX14MASK - Rx 14 Mask register
mbed_official	324:406fd2029f23	97	* - HW_CAN_RX15MASK - Rx 15 Mask register
mbed_official	324:406fd2029f23	98	* - HW_CAN_ECR - Error Counter
mbed_official	324:406fd2029f23	99	* - HW_CAN_ESR1 - Error and Status 1 register
mbed_official	324:406fd2029f23	100	* - HW_CAN_IMASK1 - Interrupt Masks 1 register
mbed_official	324:406fd2029f23	101	* - HW_CAN_IFLAG1 - Interrupt Flags 1 register
mbed_official	324:406fd2029f23	102	* - HW_CAN_CTRL2 - Control 2 register
mbed_official	324:406fd2029f23	103	* - HW_CAN_ESR2 - Error and Status 2 register
mbed_official	324:406fd2029f23	104	* - HW_CAN_CRCR - CRC Register
mbed_official	324:406fd2029f23	105	* - HW_CAN_RXFGMASK - Rx FIFO Global Mask register
mbed_official	324:406fd2029f23	106	* - HW_CAN_RXFIR - Rx FIFO Information Register
mbed_official	324:406fd2029f23	107	* - HW_CAN_CSn - Message Buffer 0 CS Register
mbed_official	324:406fd2029f23	108	* - HW_CAN_IDn - Message Buffer 0 ID Register
mbed_official	324:406fd2029f23	109	* - HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
mbed_official	324:406fd2029f23	110	* - HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
mbed_official	324:406fd2029f23	111	* - HW_CAN_RXIMRn - Rx Individual Mask Registers
mbed_official	324:406fd2029f23	112	*
mbed_official	324:406fd2029f23	113	* - hw_can_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	114	*/
mbed_official	324:406fd2029f23	115
mbed_official	324:406fd2029f23	116	#define HW_CAN_INSTANCE_COUNT (1U) /!< Number of instances of the CAN module. /
mbed_official	324:406fd2029f23	117
mbed_official	324:406fd2029f23	118	/*******************************************************************************
mbed_official	324:406fd2029f23	119	* HW_CAN_MCR - Module Configuration Register
mbed_official	324:406fd2029f23	120	******************************************************************************/
mbed_official	324:406fd2029f23	121
mbed_official	324:406fd2029f23	122	/*!
mbed_official	324:406fd2029f23	123	* @brief HW_CAN_MCR - Module Configuration Register (RW)
mbed_official	324:406fd2029f23	124	*
mbed_official	324:406fd2029f23	125	* Reset value: 0xD890000FU
mbed_official	324:406fd2029f23	126	*
mbed_official	324:406fd2029f23	127	* This register defines global system configurations, such as the module
mbed_official	324:406fd2029f23	128	* operation modes and the maximum message buffer configuration.
mbed_official	324:406fd2029f23	129	*/
mbed_official	324:406fd2029f23	130	typedef union _hw_can_mcr
mbed_official	324:406fd2029f23	131	{
mbed_official	324:406fd2029f23	132	uint32_t U;
mbed_official	324:406fd2029f23	133	struct _hw_can_mcr_bitfields
mbed_official	324:406fd2029f23	134	{
mbed_official	324:406fd2029f23	135	uint32_t MAXMB : 7; /!< [6:0] Number Of The Last Message Buffer /
mbed_official	324:406fd2029f23	136	uint32_t RESERVED0 : 1; /!< [7] /
mbed_official	324:406fd2029f23	137	uint32_t IDAM : 2; /!< [9:8] ID Acceptance Mode /
mbed_official	324:406fd2029f23	138	uint32_t RESERVED1 : 2; /!< [11:10] /
mbed_official	324:406fd2029f23	139	uint32_t AEN : 1; /!< [12] Abort Enable /
mbed_official	324:406fd2029f23	140	uint32_t LPRIOEN : 1; /!< [13] Local Priority Enable /
mbed_official	324:406fd2029f23	141	uint32_t RESERVED2 : 2; /!< [15:14] /
mbed_official	324:406fd2029f23	142	uint32_t IRMQ : 1; /!< [16] Individual Rx Masking And Queue Enable /
mbed_official	324:406fd2029f23	143	uint32_t SRXDIS : 1; /!< [17] Self Reception Disable /
mbed_official	324:406fd2029f23	144	uint32_t RESERVED3 : 1; /!< [18] /
mbed_official	324:406fd2029f23	145	uint32_t WAKSRC : 1; /!< [19] Wake Up Source /
mbed_official	324:406fd2029f23	146	uint32_t LPMACK : 1; /!< [20] Low-Power Mode Acknowledge /
mbed_official	324:406fd2029f23	147	uint32_t WRNEN : 1; /!< [21] Warning Interrupt Enable /
mbed_official	324:406fd2029f23	148	uint32_t SLFWAK : 1; /!< [22] Self Wake Up /
mbed_official	324:406fd2029f23	149	uint32_t SUPV : 1; /!< [23] Supervisor Mode /
mbed_official	324:406fd2029f23	150	uint32_t FRZACK : 1; /!< [24] Freeze Mode Acknowledge /
mbed_official	324:406fd2029f23	151	uint32_t SOFTRST : 1; /!< [25] Soft Reset /
mbed_official	324:406fd2029f23	152	uint32_t WAKMSK : 1; /!< [26] Wake Up Interrupt Mask /
mbed_official	324:406fd2029f23	153	uint32_t NOTRDY : 1; /!< [27] FlexCAN Not Ready /
mbed_official	324:406fd2029f23	154	uint32_t HALT : 1; /!< [28] Halt FlexCAN /
mbed_official	324:406fd2029f23	155	uint32_t RFEN : 1; /!< [29] Rx FIFO Enable /
mbed_official	324:406fd2029f23	156	uint32_t FRZ : 1; /!< [30] Freeze Enable /
mbed_official	324:406fd2029f23	157	uint32_t MDIS : 1; /!< [31] Module Disable /
mbed_official	324:406fd2029f23	158	} B;
mbed_official	324:406fd2029f23	159	} hw_can_mcr_t;
mbed_official	324:406fd2029f23	160
mbed_official	324:406fd2029f23	161	/*!
mbed_official	324:406fd2029f23	162	* @name Constants and macros for entire CAN_MCR register
mbed_official	324:406fd2029f23	163	*/
mbed_official	324:406fd2029f23	164	/@{/
mbed_official	324:406fd2029f23	165	#define HW_CAN_MCR_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	166
mbed_official	324:406fd2029f23	167	#define HW_CAN_MCR(x) ((__IO hw_can_mcr_t ) HW_CAN_MCR_ADDR(x))
mbed_official	324:406fd2029f23	168	#define HW_CAN_MCR_RD(x) (HW_CAN_MCR(x).U)
mbed_official	324:406fd2029f23	169	#define HW_CAN_MCR_WR(x, v) (HW_CAN_MCR(x).U = (v))
mbed_official	324:406fd2029f23	170	#define HW_CAN_MCR_SET(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) \| (v)))
mbed_official	324:406fd2029f23	171	#define HW_CAN_MCR_CLR(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	172	#define HW_CAN_MCR_TOG(x, v) (HW_CAN_MCR_WR(x, HW_CAN_MCR_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	173	/@}/
mbed_official	324:406fd2029f23	174
mbed_official	324:406fd2029f23	175	/*
mbed_official	324:406fd2029f23	176	* Constants & macros for individual CAN_MCR bitfields
mbed_official	324:406fd2029f23	177	*/
mbed_official	324:406fd2029f23	178
mbed_official	324:406fd2029f23	179	/*!
mbed_official	324:406fd2029f23	180	* @name Register CAN_MCR, field MAXMB[6:0] (RW)
mbed_official	324:406fd2029f23	181	*
mbed_official	324:406fd2029f23	182	* This 7-bit field defines the number of the last Message Buffers that will
mbed_official	324:406fd2029f23	183	* take part in the matching and arbitration processes. The reset value (0x0F) is
mbed_official	324:406fd2029f23	184	* equivalent to a 16 MB configuration. This field can be written only in Freeze
mbed_official	324:406fd2029f23	185	* mode because it is blocked by hardware in other modes. Number of the last MB =
mbed_official	324:406fd2029f23	186	* MAXMB MAXMB must be programmed with a value smaller than the parameter
mbed_official	324:406fd2029f23	187	* NUMBER_OF_MB, otherwise the number of the last effective Message Buffer will be:
mbed_official	324:406fd2029f23	188	* (NUMBER_OF_MB - 1) Additionally, the value of MAXMB must encompass the FIFO size
mbed_official	324:406fd2029f23	189	* defined by CTRL2[RFFN]. MAXMB also impacts the definition of the minimum number
mbed_official	324:406fd2029f23	190	* of peripheral clocks per CAN bit as described in Table "Minimum Ratio Between
mbed_official	324:406fd2029f23	191	* Peripheral Clock Frequency and CAN Bit Rate" (in Section "Arbitration and
mbed_official	324:406fd2029f23	192	* Matching Timing").
mbed_official	324:406fd2029f23	193	*/
mbed_official	324:406fd2029f23	194	/@{/
mbed_official	324:406fd2029f23	195	#define BP_CAN_MCR_MAXMB (0U) /!< Bit position for CAN_MCR_MAXMB. /
mbed_official	324:406fd2029f23	196	#define BM_CAN_MCR_MAXMB (0x0000007FU) /!< Bit mask for CAN_MCR_MAXMB. /
mbed_official	324:406fd2029f23	197	#define BS_CAN_MCR_MAXMB (7U) /!< Bit field size in bits for CAN_MCR_MAXMB. /
mbed_official	324:406fd2029f23	198
mbed_official	324:406fd2029f23	199	/! @brief Read current value of the CAN_MCR_MAXMB field. /
mbed_official	324:406fd2029f23	200	#define BR_CAN_MCR_MAXMB(x) (HW_CAN_MCR(x).B.MAXMB)
mbed_official	324:406fd2029f23	201
mbed_official	324:406fd2029f23	202	/! @brief Format value for bitfield CAN_MCR_MAXMB. /
mbed_official	324:406fd2029f23	203	#define BF_CAN_MCR_MAXMB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MAXMB) & BM_CAN_MCR_MAXMB)
mbed_official	324:406fd2029f23	204
mbed_official	324:406fd2029f23	205	/! @brief Set the MAXMB field to a new value. /
mbed_official	324:406fd2029f23	206	#define BW_CAN_MCR_MAXMB(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_MAXMB) \| BF_CAN_MCR_MAXMB(v)))
mbed_official	324:406fd2029f23	207	/@}/
mbed_official	324:406fd2029f23	208
mbed_official	324:406fd2029f23	209	/*!
mbed_official	324:406fd2029f23	210	* @name Register CAN_MCR, field IDAM[9:8] (RW)
mbed_official	324:406fd2029f23	211	*
mbed_official	324:406fd2029f23	212	* This 2-bit field identifies the format of the Rx FIFO ID Filter Table
mbed_official	324:406fd2029f23	213	* elements. Note that all elements of the table are configured at the same time by this
mbed_official	324:406fd2029f23	214	* field (they are all the same format). See Section "Rx FIFO Structure". This
mbed_official	324:406fd2029f23	215	* field can be written only in Freeze mode because it is blocked by hardware in
mbed_official	324:406fd2029f23	216	* other modes.
mbed_official	324:406fd2029f23	217	*
mbed_official	324:406fd2029f23	218	* Values:
mbed_official	324:406fd2029f23	219	* - 00 - Format A: One full ID (standard and extended) per ID Filter Table
mbed_official	324:406fd2029f23	220	* element.
mbed_official	324:406fd2029f23	221	* - 01 - Format B: Two full standard IDs or two partial 14-bit (standard and
mbed_official	324:406fd2029f23	222	* extended) IDs per ID Filter Table element.
mbed_official	324:406fd2029f23	223	* - 10 - Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
mbed_official	324:406fd2029f23	224	* - 11 - Format D: All frames rejected.
mbed_official	324:406fd2029f23	225	*/
mbed_official	324:406fd2029f23	226	/@{/
mbed_official	324:406fd2029f23	227	#define BP_CAN_MCR_IDAM (8U) /!< Bit position for CAN_MCR_IDAM. /
mbed_official	324:406fd2029f23	228	#define BM_CAN_MCR_IDAM (0x00000300U) /!< Bit mask for CAN_MCR_IDAM. /
mbed_official	324:406fd2029f23	229	#define BS_CAN_MCR_IDAM (2U) /!< Bit field size in bits for CAN_MCR_IDAM. /
mbed_official	324:406fd2029f23	230
mbed_official	324:406fd2029f23	231	/! @brief Read current value of the CAN_MCR_IDAM field. /
mbed_official	324:406fd2029f23	232	#define BR_CAN_MCR_IDAM(x) (HW_CAN_MCR(x).B.IDAM)
mbed_official	324:406fd2029f23	233
mbed_official	324:406fd2029f23	234	/! @brief Format value for bitfield CAN_MCR_IDAM. /
mbed_official	324:406fd2029f23	235	#define BF_CAN_MCR_IDAM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IDAM) & BM_CAN_MCR_IDAM)
mbed_official	324:406fd2029f23	236
mbed_official	324:406fd2029f23	237	/! @brief Set the IDAM field to a new value. /
mbed_official	324:406fd2029f23	238	#define BW_CAN_MCR_IDAM(x, v) (HW_CAN_MCR_WR(x, (HW_CAN_MCR_RD(x) & ~BM_CAN_MCR_IDAM) \| BF_CAN_MCR_IDAM(v)))
mbed_official	324:406fd2029f23	239	/@}/
mbed_official	324:406fd2029f23	240
mbed_official	324:406fd2029f23	241	/*!
mbed_official	324:406fd2029f23	242	* @name Register CAN_MCR, field AEN[12] (RW)
mbed_official	324:406fd2029f23	243	*
mbed_official	324:406fd2029f23	244	* This bit is supplied for backwards compatibility with legacy applications.
mbed_official	324:406fd2029f23	245	* When asserted, it enables the Tx abort mechanism. This mechanism guarantees a
mbed_official	324:406fd2029f23	246	* safe procedure for aborting a pending transmission, so that no frame is sent in
mbed_official	324:406fd2029f23	247	* the CAN bus without notification. This bit can be written only in Freeze mode
mbed_official	324:406fd2029f23	248	* because it is blocked by hardware in other modes. When MCR[AEN] is asserted,
mbed_official	324:406fd2029f23	249	* only the abort mechanism (see Section "Transmission Abort Mechanism") must be
mbed_official	324:406fd2029f23	250	* used for updating Mailboxes configured for transmission. Writing the Abort code
mbed_official	324:406fd2029f23	251	* into Rx Mailboxes can cause unpredictable results when the MCR[AEN] is
mbed_official	324:406fd2029f23	252	* asserted.
mbed_official	324:406fd2029f23	253	*
mbed_official	324:406fd2029f23	254	* Values:
mbed_official	324:406fd2029f23	255	* - 0 - Abort disabled.
mbed_official	324:406fd2029f23	256	* - 1 - Abort enabled.
mbed_official	324:406fd2029f23	257	*/
mbed_official	324:406fd2029f23	258	/@{/
mbed_official	324:406fd2029f23	259	#define BP_CAN_MCR_AEN (12U) /!< Bit position for CAN_MCR_AEN. /
mbed_official	324:406fd2029f23	260	#define BM_CAN_MCR_AEN (0x00001000U) /!< Bit mask for CAN_MCR_AEN. /
mbed_official	324:406fd2029f23	261	#define BS_CAN_MCR_AEN (1U) /!< Bit field size in bits for CAN_MCR_AEN. /
mbed_official	324:406fd2029f23	262
mbed_official	324:406fd2029f23	263	/! @brief Read current value of the CAN_MCR_AEN field. /
mbed_official	324:406fd2029f23	264	#define BR_CAN_MCR_AEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN))
mbed_official	324:406fd2029f23	265
mbed_official	324:406fd2029f23	266	/! @brief Format value for bitfield CAN_MCR_AEN. /
mbed_official	324:406fd2029f23	267	#define BF_CAN_MCR_AEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_AEN) & BM_CAN_MCR_AEN)
mbed_official	324:406fd2029f23	268
mbed_official	324:406fd2029f23	269	/! @brief Set the AEN field to a new value. /
mbed_official	324:406fd2029f23	270	#define BW_CAN_MCR_AEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_AEN) = (v))
mbed_official	324:406fd2029f23	271	/@}/
mbed_official	324:406fd2029f23	272
mbed_official	324:406fd2029f23	273	/*!
mbed_official	324:406fd2029f23	274	* @name Register CAN_MCR, field LPRIOEN[13] (RW)
mbed_official	324:406fd2029f23	275	*
mbed_official	324:406fd2029f23	276	* This bit is provided for backwards compatibility with legacy applications. It
mbed_official	324:406fd2029f23	277	* controls whether the local priority feature is enabled or not. It is used to
mbed_official	324:406fd2029f23	278	* expand the ID used during the arbitration process. With this expanded ID
mbed_official	324:406fd2029f23	279	* concept, the arbitration process is done based on the full 32-bit word, but the
mbed_official	324:406fd2029f23	280	* actual transmitted ID still has 11-bit for standard frames and 29-bit for
mbed_official	324:406fd2029f23	281	* extended frames. This bit can be written only in Freeze mode because it is blocked by
mbed_official	324:406fd2029f23	282	* hardware in other modes.
mbed_official	324:406fd2029f23	283	*
mbed_official	324:406fd2029f23	284	* Values:
mbed_official	324:406fd2029f23	285	* - 0 - Local Priority disabled.
mbed_official	324:406fd2029f23	286	* - 1 - Local Priority enabled.
mbed_official	324:406fd2029f23	287	*/
mbed_official	324:406fd2029f23	288	/@{/
mbed_official	324:406fd2029f23	289	#define BP_CAN_MCR_LPRIOEN (13U) /!< Bit position for CAN_MCR_LPRIOEN. /
mbed_official	324:406fd2029f23	290	#define BM_CAN_MCR_LPRIOEN (0x00002000U) /!< Bit mask for CAN_MCR_LPRIOEN. /
mbed_official	324:406fd2029f23	291	#define BS_CAN_MCR_LPRIOEN (1U) /!< Bit field size in bits for CAN_MCR_LPRIOEN. /
mbed_official	324:406fd2029f23	292
mbed_official	324:406fd2029f23	293	/! @brief Read current value of the CAN_MCR_LPRIOEN field. /
mbed_official	324:406fd2029f23	294	#define BR_CAN_MCR_LPRIOEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN))
mbed_official	324:406fd2029f23	295
mbed_official	324:406fd2029f23	296	/! @brief Format value for bitfield CAN_MCR_LPRIOEN. /
mbed_official	324:406fd2029f23	297	#define BF_CAN_MCR_LPRIOEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_LPRIOEN) & BM_CAN_MCR_LPRIOEN)
mbed_official	324:406fd2029f23	298
mbed_official	324:406fd2029f23	299	/! @brief Set the LPRIOEN field to a new value. /
mbed_official	324:406fd2029f23	300	#define BW_CAN_MCR_LPRIOEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPRIOEN) = (v))
mbed_official	324:406fd2029f23	301	/@}/
mbed_official	324:406fd2029f23	302
mbed_official	324:406fd2029f23	303	/*!
mbed_official	324:406fd2029f23	304	* @name Register CAN_MCR, field IRMQ[16] (RW)
mbed_official	324:406fd2029f23	305	*
mbed_official	324:406fd2029f23	306	* This bit indicates whether Rx matching process will be based either on
mbed_official	324:406fd2029f23	307	* individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and
mbed_official	324:406fd2029f23	308	* RX15MASK, RXFGMASK. This bit can be written only in Freeze mode because it is
mbed_official	324:406fd2029f23	309	* blocked by hardware in other modes.
mbed_official	324:406fd2029f23	310	*
mbed_official	324:406fd2029f23	311	* Values:
mbed_official	324:406fd2029f23	312	* - 0 - Individual Rx masking and queue feature are disabled. For backward
mbed_official	324:406fd2029f23	313	* compatibility with legacy applications, the reading of C/S word locks the MB
mbed_official	324:406fd2029f23	314	* even if it is EMPTY.
mbed_official	324:406fd2029f23	315	* - 1 - Individual Rx masking and queue feature are enabled.
mbed_official	324:406fd2029f23	316	*/
mbed_official	324:406fd2029f23	317	/@{/
mbed_official	324:406fd2029f23	318	#define BP_CAN_MCR_IRMQ (16U) /!< Bit position for CAN_MCR_IRMQ. /
mbed_official	324:406fd2029f23	319	#define BM_CAN_MCR_IRMQ (0x00010000U) /!< Bit mask for CAN_MCR_IRMQ. /
mbed_official	324:406fd2029f23	320	#define BS_CAN_MCR_IRMQ (1U) /!< Bit field size in bits for CAN_MCR_IRMQ. /
mbed_official	324:406fd2029f23	321
mbed_official	324:406fd2029f23	322	/! @brief Read current value of the CAN_MCR_IRMQ field. /
mbed_official	324:406fd2029f23	323	#define BR_CAN_MCR_IRMQ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ))
mbed_official	324:406fd2029f23	324
mbed_official	324:406fd2029f23	325	/! @brief Format value for bitfield CAN_MCR_IRMQ. /
mbed_official	324:406fd2029f23	326	#define BF_CAN_MCR_IRMQ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_IRMQ) & BM_CAN_MCR_IRMQ)
mbed_official	324:406fd2029f23	327
mbed_official	324:406fd2029f23	328	/! @brief Set the IRMQ field to a new value. /
mbed_official	324:406fd2029f23	329	#define BW_CAN_MCR_IRMQ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_IRMQ) = (v))
mbed_official	324:406fd2029f23	330	/@}/
mbed_official	324:406fd2029f23	331
mbed_official	324:406fd2029f23	332	/*!
mbed_official	324:406fd2029f23	333	* @name Register CAN_MCR, field SRXDIS[17] (RW)
mbed_official	324:406fd2029f23	334	*
mbed_official	324:406fd2029f23	335	* This bit defines whether FlexCAN is allowed to receive frames transmitted by
mbed_official	324:406fd2029f23	336	* itself. If this bit is asserted, frames transmitted by the module will not be
mbed_official	324:406fd2029f23	337	* stored in any MB, regardless if the MB is programmed with an ID that matches
mbed_official	324:406fd2029f23	338	* the transmitted frame, and no interrupt flag or interrupt signal will be
mbed_official	324:406fd2029f23	339	* generated due to the frame reception. This bit can be written only in Freeze mode
mbed_official	324:406fd2029f23	340	* because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	341	*
mbed_official	324:406fd2029f23	342	* Values:
mbed_official	324:406fd2029f23	343	* - 0 - Self reception enabled.
mbed_official	324:406fd2029f23	344	* - 1 - Self reception disabled.
mbed_official	324:406fd2029f23	345	*/
mbed_official	324:406fd2029f23	346	/@{/
mbed_official	324:406fd2029f23	347	#define BP_CAN_MCR_SRXDIS (17U) /!< Bit position for CAN_MCR_SRXDIS. /
mbed_official	324:406fd2029f23	348	#define BM_CAN_MCR_SRXDIS (0x00020000U) /!< Bit mask for CAN_MCR_SRXDIS. /
mbed_official	324:406fd2029f23	349	#define BS_CAN_MCR_SRXDIS (1U) /!< Bit field size in bits for CAN_MCR_SRXDIS. /
mbed_official	324:406fd2029f23	350
mbed_official	324:406fd2029f23	351	/! @brief Read current value of the CAN_MCR_SRXDIS field. /
mbed_official	324:406fd2029f23	352	#define BR_CAN_MCR_SRXDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS))
mbed_official	324:406fd2029f23	353
mbed_official	324:406fd2029f23	354	/! @brief Format value for bitfield CAN_MCR_SRXDIS. /
mbed_official	324:406fd2029f23	355	#define BF_CAN_MCR_SRXDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SRXDIS) & BM_CAN_MCR_SRXDIS)
mbed_official	324:406fd2029f23	356
mbed_official	324:406fd2029f23	357	/! @brief Set the SRXDIS field to a new value. /
mbed_official	324:406fd2029f23	358	#define BW_CAN_MCR_SRXDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SRXDIS) = (v))
mbed_official	324:406fd2029f23	359	/@}/
mbed_official	324:406fd2029f23	360
mbed_official	324:406fd2029f23	361	/*!
mbed_official	324:406fd2029f23	362	* @name Register CAN_MCR, field WAKSRC[19] (RW)
mbed_official	324:406fd2029f23	363	*
mbed_official	324:406fd2029f23	364	* This bit defines whether the integrated low-pass filter is applied to protect
mbed_official	324:406fd2029f23	365	* the Rx CAN input from spurious wake up. This bit can be written only in
mbed_official	324:406fd2029f23	366	* Freeze mode because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	367	*
mbed_official	324:406fd2029f23	368	* Values:
mbed_official	324:406fd2029f23	369	* - 0 - FlexCAN uses the unfiltered Rx input to detect recessive to dominant
mbed_official	324:406fd2029f23	370	* edges on the CAN bus.
mbed_official	324:406fd2029f23	371	* - 1 - FlexCAN uses the filtered Rx input to detect recessive to dominant
mbed_official	324:406fd2029f23	372	* edges on the CAN bus.
mbed_official	324:406fd2029f23	373	*/
mbed_official	324:406fd2029f23	374	/@{/
mbed_official	324:406fd2029f23	375	#define BP_CAN_MCR_WAKSRC (19U) /!< Bit position for CAN_MCR_WAKSRC. /
mbed_official	324:406fd2029f23	376	#define BM_CAN_MCR_WAKSRC (0x00080000U) /!< Bit mask for CAN_MCR_WAKSRC. /
mbed_official	324:406fd2029f23	377	#define BS_CAN_MCR_WAKSRC (1U) /!< Bit field size in bits for CAN_MCR_WAKSRC. /
mbed_official	324:406fd2029f23	378
mbed_official	324:406fd2029f23	379	/! @brief Read current value of the CAN_MCR_WAKSRC field. /
mbed_official	324:406fd2029f23	380	#define BR_CAN_MCR_WAKSRC(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC))
mbed_official	324:406fd2029f23	381
mbed_official	324:406fd2029f23	382	/! @brief Format value for bitfield CAN_MCR_WAKSRC. /
mbed_official	324:406fd2029f23	383	#define BF_CAN_MCR_WAKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKSRC) & BM_CAN_MCR_WAKSRC)
mbed_official	324:406fd2029f23	384
mbed_official	324:406fd2029f23	385	/! @brief Set the WAKSRC field to a new value. /
mbed_official	324:406fd2029f23	386	#define BW_CAN_MCR_WAKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKSRC) = (v))
mbed_official	324:406fd2029f23	387	/@}/
mbed_official	324:406fd2029f23	388
mbed_official	324:406fd2029f23	389	/*!
mbed_official	324:406fd2029f23	390	* @name Register CAN_MCR, field LPMACK[20] (RO)
mbed_official	324:406fd2029f23	391	*
mbed_official	324:406fd2029f23	392	* This read-only bit indicates that FlexCAN is in a low-power mode (Disable
mbed_official	324:406fd2029f23	393	* mode , Stop mode ). A low-power mode cannot be entered until all current
mbed_official	324:406fd2029f23	394	* transmission or reception processes have finished, so the CPU can poll the LPMACK bit
mbed_official	324:406fd2029f23	395	* to know when FlexCAN has actually entered low power mode. LPMACK will be
mbed_official	324:406fd2029f23	396	* asserted within 180 CAN bits from the low-power mode request by the CPU, and
mbed_official	324:406fd2029f23	397	* negated within 2 CAN bits after the low-power mode request removal (see Section
mbed_official	324:406fd2029f23	398	* "Protocol Timing").
mbed_official	324:406fd2029f23	399	*
mbed_official	324:406fd2029f23	400	* Values:
mbed_official	324:406fd2029f23	401	* - 0 - FlexCAN is not in a low-power mode.
mbed_official	324:406fd2029f23	402	* - 1 - FlexCAN is in a low-power mode.
mbed_official	324:406fd2029f23	403	*/
mbed_official	324:406fd2029f23	404	/@{/
mbed_official	324:406fd2029f23	405	#define BP_CAN_MCR_LPMACK (20U) /!< Bit position for CAN_MCR_LPMACK. /
mbed_official	324:406fd2029f23	406	#define BM_CAN_MCR_LPMACK (0x00100000U) /!< Bit mask for CAN_MCR_LPMACK. /
mbed_official	324:406fd2029f23	407	#define BS_CAN_MCR_LPMACK (1U) /!< Bit field size in bits for CAN_MCR_LPMACK. /
mbed_official	324:406fd2029f23	408
mbed_official	324:406fd2029f23	409	/! @brief Read current value of the CAN_MCR_LPMACK field. /
mbed_official	324:406fd2029f23	410	#define BR_CAN_MCR_LPMACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_LPMACK))
mbed_official	324:406fd2029f23	411	/@}/
mbed_official	324:406fd2029f23	412
mbed_official	324:406fd2029f23	413	/*!
mbed_official	324:406fd2029f23	414	* @name Register CAN_MCR, field WRNEN[21] (RW)
mbed_official	324:406fd2029f23	415	*
mbed_official	324:406fd2029f23	416	* When asserted, this bit enables the generation of the TWRNINT and RWRNINT
mbed_official	324:406fd2029f23	417	* flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and
mbed_official	324:406fd2029f23	418	* RWRNINT flags will always be zero, independent of the values of the error
mbed_official	324:406fd2029f23	419	* counters, and no warning interrupt will ever be generated. This bit can be written
mbed_official	324:406fd2029f23	420	* only in Freeze mode because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	421	*
mbed_official	324:406fd2029f23	422	* Values:
mbed_official	324:406fd2029f23	423	* - 0 - TWRNINT and RWRNINT bits are zero, independent of the values in the
mbed_official	324:406fd2029f23	424	* error counters.
mbed_official	324:406fd2029f23	425	* - 1 - TWRNINT and RWRNINT bits are set when the respective error counter
mbed_official	324:406fd2029f23	426	* transitions from less than 96 to greater than or equal to 96.
mbed_official	324:406fd2029f23	427	*/
mbed_official	324:406fd2029f23	428	/@{/
mbed_official	324:406fd2029f23	429	#define BP_CAN_MCR_WRNEN (21U) /!< Bit position for CAN_MCR_WRNEN. /
mbed_official	324:406fd2029f23	430	#define BM_CAN_MCR_WRNEN (0x00200000U) /!< Bit mask for CAN_MCR_WRNEN. /
mbed_official	324:406fd2029f23	431	#define BS_CAN_MCR_WRNEN (1U) /!< Bit field size in bits for CAN_MCR_WRNEN. /
mbed_official	324:406fd2029f23	432
mbed_official	324:406fd2029f23	433	/! @brief Read current value of the CAN_MCR_WRNEN field. /
mbed_official	324:406fd2029f23	434	#define BR_CAN_MCR_WRNEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN))
mbed_official	324:406fd2029f23	435
mbed_official	324:406fd2029f23	436	/! @brief Format value for bitfield CAN_MCR_WRNEN. /
mbed_official	324:406fd2029f23	437	#define BF_CAN_MCR_WRNEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WRNEN) & BM_CAN_MCR_WRNEN)
mbed_official	324:406fd2029f23	438
mbed_official	324:406fd2029f23	439	/! @brief Set the WRNEN field to a new value. /
mbed_official	324:406fd2029f23	440	#define BW_CAN_MCR_WRNEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WRNEN) = (v))
mbed_official	324:406fd2029f23	441	/@}/
mbed_official	324:406fd2029f23	442
mbed_official	324:406fd2029f23	443	/*!
mbed_official	324:406fd2029f23	444	* @name Register CAN_MCR, field SLFWAK[22] (RW)
mbed_official	324:406fd2029f23	445	*
mbed_official	324:406fd2029f23	446	* This bit enables the Self Wake Up feature when FlexCAN is in a low-power mode
mbed_official	324:406fd2029f23	447	* other than Disable mode. When this feature is enabled, the FlexCAN module
mbed_official	324:406fd2029f23	448	* monitors the bus for wake up event, that is, a recessive-to-dominant transition.
mbed_official	324:406fd2029f23	449	* If a wake up event is detected during Stop mode, then FlexCAN generates, if
mbed_official	324:406fd2029f23	450	* enabled to do so, a Wake Up interrupt to the CPU so that it can exit Stop mode
mbed_official	324:406fd2029f23	451	* globally and FlexCAN can request to resume the clocks. When FlexCAN is in a
mbed_official	324:406fd2029f23	452	* low-power mode other than Disable mode, this bit cannot be written as it is
mbed_official	324:406fd2029f23	453	* blocked by hardware.
mbed_official	324:406fd2029f23	454	*
mbed_official	324:406fd2029f23	455	* Values:
mbed_official	324:406fd2029f23	456	* - 0 - FlexCAN Self Wake Up feature is disabled.
mbed_official	324:406fd2029f23	457	* - 1 - FlexCAN Self Wake Up feature is enabled.
mbed_official	324:406fd2029f23	458	*/
mbed_official	324:406fd2029f23	459	/@{/
mbed_official	324:406fd2029f23	460	#define BP_CAN_MCR_SLFWAK (22U) /!< Bit position for CAN_MCR_SLFWAK. /
mbed_official	324:406fd2029f23	461	#define BM_CAN_MCR_SLFWAK (0x00400000U) /!< Bit mask for CAN_MCR_SLFWAK. /
mbed_official	324:406fd2029f23	462	#define BS_CAN_MCR_SLFWAK (1U) /!< Bit field size in bits for CAN_MCR_SLFWAK. /
mbed_official	324:406fd2029f23	463
mbed_official	324:406fd2029f23	464	/! @brief Read current value of the CAN_MCR_SLFWAK field. /
mbed_official	324:406fd2029f23	465	#define BR_CAN_MCR_SLFWAK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK))
mbed_official	324:406fd2029f23	466
mbed_official	324:406fd2029f23	467	/! @brief Format value for bitfield CAN_MCR_SLFWAK. /
mbed_official	324:406fd2029f23	468	#define BF_CAN_MCR_SLFWAK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SLFWAK) & BM_CAN_MCR_SLFWAK)
mbed_official	324:406fd2029f23	469
mbed_official	324:406fd2029f23	470	/! @brief Set the SLFWAK field to a new value. /
mbed_official	324:406fd2029f23	471	#define BW_CAN_MCR_SLFWAK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SLFWAK) = (v))
mbed_official	324:406fd2029f23	472	/@}/
mbed_official	324:406fd2029f23	473
mbed_official	324:406fd2029f23	474	/*!
mbed_official	324:406fd2029f23	475	* @name Register CAN_MCR, field SUPV[23] (RW)
mbed_official	324:406fd2029f23	476	*
mbed_official	324:406fd2029f23	477	* This bit configures the FlexCAN to be either in Supervisor or User mode. The
mbed_official	324:406fd2029f23	478	* registers affected by this bit are marked as S/U in the Access Type column of
mbed_official	324:406fd2029f23	479	* the module memory map. Reset value of this bit is 1, so the affected registers
mbed_official	324:406fd2029f23	480	* start with Supervisor access allowance only . This bit can be written only in
mbed_official	324:406fd2029f23	481	* Freeze mode because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	482	*
mbed_official	324:406fd2029f23	483	* Values:
mbed_official	324:406fd2029f23	484	* - 0 - FlexCAN is in User mode. Affected registers allow both Supervisor and
mbed_official	324:406fd2029f23	485	* Unrestricted accesses .
mbed_official	324:406fd2029f23	486	* - 1 - FlexCAN is in Supervisor mode. Affected registers allow only Supervisor
mbed_official	324:406fd2029f23	487	* access. Unrestricted access behaves as though the access was done to an
mbed_official	324:406fd2029f23	488	* unimplemented register location .
mbed_official	324:406fd2029f23	489	*/
mbed_official	324:406fd2029f23	490	/@{/
mbed_official	324:406fd2029f23	491	#define BP_CAN_MCR_SUPV (23U) /!< Bit position for CAN_MCR_SUPV. /
mbed_official	324:406fd2029f23	492	#define BM_CAN_MCR_SUPV (0x00800000U) /!< Bit mask for CAN_MCR_SUPV. /
mbed_official	324:406fd2029f23	493	#define BS_CAN_MCR_SUPV (1U) /!< Bit field size in bits for CAN_MCR_SUPV. /
mbed_official	324:406fd2029f23	494
mbed_official	324:406fd2029f23	495	/! @brief Read current value of the CAN_MCR_SUPV field. /
mbed_official	324:406fd2029f23	496	#define BR_CAN_MCR_SUPV(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV))
mbed_official	324:406fd2029f23	497
mbed_official	324:406fd2029f23	498	/! @brief Format value for bitfield CAN_MCR_SUPV. /
mbed_official	324:406fd2029f23	499	#define BF_CAN_MCR_SUPV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SUPV) & BM_CAN_MCR_SUPV)
mbed_official	324:406fd2029f23	500
mbed_official	324:406fd2029f23	501	/! @brief Set the SUPV field to a new value. /
mbed_official	324:406fd2029f23	502	#define BW_CAN_MCR_SUPV(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SUPV) = (v))
mbed_official	324:406fd2029f23	503	/@}/
mbed_official	324:406fd2029f23	504
mbed_official	324:406fd2029f23	505	/*!
mbed_official	324:406fd2029f23	506	* @name Register CAN_MCR, field FRZACK[24] (RO)
mbed_official	324:406fd2029f23	507	*
mbed_official	324:406fd2029f23	508	* This read-only bit indicates that FlexCAN is in Freeze mode and its prescaler
mbed_official	324:406fd2029f23	509	* is stopped. The Freeze mode request cannot be granted until current
mbed_official	324:406fd2029f23	510	* transmission or reception processes have finished. Therefore the software can poll the
mbed_official	324:406fd2029f23	511	* FRZACK bit to know when FlexCAN has actually entered Freeze mode. If Freeze
mbed_official	324:406fd2029f23	512	* Mode request is negated, then this bit is negated after the FlexCAN prescaler is
mbed_official	324:406fd2029f23	513	* running again. If Freeze mode is requested while FlexCAN is in a low power
mbed_official	324:406fd2029f23	514	* mode, then the FRZACK bit will be set only when the low-power mode is exited.
mbed_official	324:406fd2029f23	515	* See Section "Freeze Mode". FRZACK will be asserted within 178 CAN bits from the
mbed_official	324:406fd2029f23	516	* freeze mode request by the CPU, and negated within 2 CAN bits after the freeze
mbed_official	324:406fd2029f23	517	* mode request removal (see Section "Protocol Timing").
mbed_official	324:406fd2029f23	518	*
mbed_official	324:406fd2029f23	519	* Values:
mbed_official	324:406fd2029f23	520	* - 0 - FlexCAN not in Freeze mode, prescaler running.
mbed_official	324:406fd2029f23	521	* - 1 - FlexCAN in Freeze mode, prescaler stopped.
mbed_official	324:406fd2029f23	522	*/
mbed_official	324:406fd2029f23	523	/@{/
mbed_official	324:406fd2029f23	524	#define BP_CAN_MCR_FRZACK (24U) /!< Bit position for CAN_MCR_FRZACK. /
mbed_official	324:406fd2029f23	525	#define BM_CAN_MCR_FRZACK (0x01000000U) /!< Bit mask for CAN_MCR_FRZACK. /
mbed_official	324:406fd2029f23	526	#define BS_CAN_MCR_FRZACK (1U) /!< Bit field size in bits for CAN_MCR_FRZACK. /
mbed_official	324:406fd2029f23	527
mbed_official	324:406fd2029f23	528	/! @brief Read current value of the CAN_MCR_FRZACK field. /
mbed_official	324:406fd2029f23	529	#define BR_CAN_MCR_FRZACK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZACK))
mbed_official	324:406fd2029f23	530	/@}/
mbed_official	324:406fd2029f23	531
mbed_official	324:406fd2029f23	532	/*!
mbed_official	324:406fd2029f23	533	* @name Register CAN_MCR, field SOFTRST[25] (RW)
mbed_official	324:406fd2029f23	534	*
mbed_official	324:406fd2029f23	535	* When this bit is asserted, FlexCAN resets its internal state machines and
mbed_official	324:406fd2029f23	536	* some of the memory mapped registers. The following registers are reset: MCR
mbed_official	324:406fd2029f23	537	* (except the MDIS bit), TIMER , ECR, ESR1, ESR2, IMASK1, IMASK2, IFLAG1, IFLAG2 and
mbed_official	324:406fd2029f23	538	* CRCR. Configuration registers that control the interface to the CAN bus are
mbed_official	324:406fd2029f23	539	* not affected by soft reset. The following registers are unaffected: CTRL1,
mbed_official	324:406fd2029f23	540	* CTRL2, all RXIMR registers, RXMGMASK, RX14MASK, RX15MASK, RXFGMASK, RXFIR, all
mbed_official	324:406fd2029f23	541	* Message Buffers . The SOFTRST bit can be asserted directly by the CPU when it
mbed_official	324:406fd2029f23	542	* writes to the MCR Register, but it is also asserted when global soft reset is
mbed_official	324:406fd2029f23	543	* requested at MCU level . Because soft reset is synchronous and has to follow a
mbed_official	324:406fd2029f23	544	* request/acknowledge procedure across clock domains, it may take some time to
mbed_official	324:406fd2029f23	545	* fully propagate its effect. The SOFTRST bit remains asserted while reset is
mbed_official	324:406fd2029f23	546	* pending, and is automatically negated when reset completes. Therefore, software can
mbed_official	324:406fd2029f23	547	* poll this bit to know when the soft reset has completed. Soft reset cannot be
mbed_official	324:406fd2029f23	548	* applied while clocks are shut down in a low power mode. The module should be
mbed_official	324:406fd2029f23	549	* first removed from low power mode, and then soft reset can be applied.
mbed_official	324:406fd2029f23	550	*
mbed_official	324:406fd2029f23	551	* Values:
mbed_official	324:406fd2029f23	552	* - 0 - No reset request.
mbed_official	324:406fd2029f23	553	* - 1 - Resets the registers affected by soft reset.
mbed_official	324:406fd2029f23	554	*/
mbed_official	324:406fd2029f23	555	/@{/
mbed_official	324:406fd2029f23	556	#define BP_CAN_MCR_SOFTRST (25U) /!< Bit position for CAN_MCR_SOFTRST. /
mbed_official	324:406fd2029f23	557	#define BM_CAN_MCR_SOFTRST (0x02000000U) /!< Bit mask for CAN_MCR_SOFTRST. /
mbed_official	324:406fd2029f23	558	#define BS_CAN_MCR_SOFTRST (1U) /!< Bit field size in bits for CAN_MCR_SOFTRST. /
mbed_official	324:406fd2029f23	559
mbed_official	324:406fd2029f23	560	/! @brief Read current value of the CAN_MCR_SOFTRST field. /
mbed_official	324:406fd2029f23	561	#define BR_CAN_MCR_SOFTRST(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST))
mbed_official	324:406fd2029f23	562
mbed_official	324:406fd2029f23	563	/! @brief Format value for bitfield CAN_MCR_SOFTRST. /
mbed_official	324:406fd2029f23	564	#define BF_CAN_MCR_SOFTRST(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_SOFTRST) & BM_CAN_MCR_SOFTRST)
mbed_official	324:406fd2029f23	565
mbed_official	324:406fd2029f23	566	/! @brief Set the SOFTRST field to a new value. /
mbed_official	324:406fd2029f23	567	#define BW_CAN_MCR_SOFTRST(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_SOFTRST) = (v))
mbed_official	324:406fd2029f23	568	/@}/
mbed_official	324:406fd2029f23	569
mbed_official	324:406fd2029f23	570	/*!
mbed_official	324:406fd2029f23	571	* @name Register CAN_MCR, field WAKMSK[26] (RW)
mbed_official	324:406fd2029f23	572	*
mbed_official	324:406fd2029f23	573	* This bit enables the Wake Up Interrupt generation under Self Wake Up
mbed_official	324:406fd2029f23	574	* mechanism.
mbed_official	324:406fd2029f23	575	*
mbed_official	324:406fd2029f23	576	* Values:
mbed_official	324:406fd2029f23	577	* - 0 - Wake Up Interrupt is disabled.
mbed_official	324:406fd2029f23	578	* - 1 - Wake Up Interrupt is enabled.
mbed_official	324:406fd2029f23	579	*/
mbed_official	324:406fd2029f23	580	/@{/
mbed_official	324:406fd2029f23	581	#define BP_CAN_MCR_WAKMSK (26U) /!< Bit position for CAN_MCR_WAKMSK. /
mbed_official	324:406fd2029f23	582	#define BM_CAN_MCR_WAKMSK (0x04000000U) /!< Bit mask for CAN_MCR_WAKMSK. /
mbed_official	324:406fd2029f23	583	#define BS_CAN_MCR_WAKMSK (1U) /!< Bit field size in bits for CAN_MCR_WAKMSK. /
mbed_official	324:406fd2029f23	584
mbed_official	324:406fd2029f23	585	/! @brief Read current value of the CAN_MCR_WAKMSK field. /
mbed_official	324:406fd2029f23	586	#define BR_CAN_MCR_WAKMSK(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK))
mbed_official	324:406fd2029f23	587
mbed_official	324:406fd2029f23	588	/! @brief Format value for bitfield CAN_MCR_WAKMSK. /
mbed_official	324:406fd2029f23	589	#define BF_CAN_MCR_WAKMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_WAKMSK) & BM_CAN_MCR_WAKMSK)
mbed_official	324:406fd2029f23	590
mbed_official	324:406fd2029f23	591	/! @brief Set the WAKMSK field to a new value. /
mbed_official	324:406fd2029f23	592	#define BW_CAN_MCR_WAKMSK(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_WAKMSK) = (v))
mbed_official	324:406fd2029f23	593	/@}/
mbed_official	324:406fd2029f23	594
mbed_official	324:406fd2029f23	595	/*!
mbed_official	324:406fd2029f23	596	* @name Register CAN_MCR, field NOTRDY[27] (RO)
mbed_official	324:406fd2029f23	597	*
mbed_official	324:406fd2029f23	598	* This read-only bit indicates that FlexCAN is either in Disable mode , Stop
mbed_official	324:406fd2029f23	599	* mode or Freeze mode. It is negated once FlexCAN has exited these modes.
mbed_official	324:406fd2029f23	600	*
mbed_official	324:406fd2029f23	601	* Values:
mbed_official	324:406fd2029f23	602	* - 0 - FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back
mbed_official	324:406fd2029f23	603	* mode.
mbed_official	324:406fd2029f23	604	* - 1 - FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
mbed_official	324:406fd2029f23	605	*/
mbed_official	324:406fd2029f23	606	/@{/
mbed_official	324:406fd2029f23	607	#define BP_CAN_MCR_NOTRDY (27U) /!< Bit position for CAN_MCR_NOTRDY. /
mbed_official	324:406fd2029f23	608	#define BM_CAN_MCR_NOTRDY (0x08000000U) /!< Bit mask for CAN_MCR_NOTRDY. /
mbed_official	324:406fd2029f23	609	#define BS_CAN_MCR_NOTRDY (1U) /!< Bit field size in bits for CAN_MCR_NOTRDY. /
mbed_official	324:406fd2029f23	610
mbed_official	324:406fd2029f23	611	/! @brief Read current value of the CAN_MCR_NOTRDY field. /
mbed_official	324:406fd2029f23	612	#define BR_CAN_MCR_NOTRDY(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_NOTRDY))
mbed_official	324:406fd2029f23	613	/@}/
mbed_official	324:406fd2029f23	614
mbed_official	324:406fd2029f23	615	/*!
mbed_official	324:406fd2029f23	616	* @name Register CAN_MCR, field HALT[28] (RW)
mbed_official	324:406fd2029f23	617	*
mbed_official	324:406fd2029f23	618	* Assertion of this bit puts the FlexCAN module into Freeze mode. The CPU
mbed_official	324:406fd2029f23	619	* should clear it after initializing the Message Buffers and Control Register. No
mbed_official	324:406fd2029f23	620	* reception or transmission is performed by FlexCAN before this bit is cleared.
mbed_official	324:406fd2029f23	621	* Freeze mode cannot be entered while FlexCAN is in a low power mode.
mbed_official	324:406fd2029f23	622	*
mbed_official	324:406fd2029f23	623	* Values:
mbed_official	324:406fd2029f23	624	* - 0 - No Freeze mode request.
mbed_official	324:406fd2029f23	625	* - 1 - Enters Freeze mode if the FRZ bit is asserted.
mbed_official	324:406fd2029f23	626	*/
mbed_official	324:406fd2029f23	627	/@{/
mbed_official	324:406fd2029f23	628	#define BP_CAN_MCR_HALT (28U) /!< Bit position for CAN_MCR_HALT. /
mbed_official	324:406fd2029f23	629	#define BM_CAN_MCR_HALT (0x10000000U) /!< Bit mask for CAN_MCR_HALT. /
mbed_official	324:406fd2029f23	630	#define BS_CAN_MCR_HALT (1U) /!< Bit field size in bits for CAN_MCR_HALT. /
mbed_official	324:406fd2029f23	631
mbed_official	324:406fd2029f23	632	/! @brief Read current value of the CAN_MCR_HALT field. /
mbed_official	324:406fd2029f23	633	#define BR_CAN_MCR_HALT(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT))
mbed_official	324:406fd2029f23	634
mbed_official	324:406fd2029f23	635	/! @brief Format value for bitfield CAN_MCR_HALT. /
mbed_official	324:406fd2029f23	636	#define BF_CAN_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_HALT) & BM_CAN_MCR_HALT)
mbed_official	324:406fd2029f23	637
mbed_official	324:406fd2029f23	638	/! @brief Set the HALT field to a new value. /
mbed_official	324:406fd2029f23	639	#define BW_CAN_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_HALT) = (v))
mbed_official	324:406fd2029f23	640	/@}/
mbed_official	324:406fd2029f23	641
mbed_official	324:406fd2029f23	642	/*!
mbed_official	324:406fd2029f23	643	* @name Register CAN_MCR, field RFEN[29] (RW)
mbed_official	324:406fd2029f23	644	*
mbed_official	324:406fd2029f23	645	* This bit controls whether the Rx FIFO feature is enabled or not. When RFEN is
mbed_official	324:406fd2029f23	646	* set, MBs 0 to 5 cannot be used for normal reception and transmission because
mbed_official	324:406fd2029f23	647	* the corresponding memory region (0x80-0xDC) is used by the FIFO engine as well
mbed_official	324:406fd2029f23	648	* as additional MBs (up to 32, depending on CTRL2[RFFN] setting) which are used
mbed_official	324:406fd2029f23	649	* as Rx FIFO ID Filter Table elements. RFEN also impacts the definition of the
mbed_official	324:406fd2029f23	650	* minimum number of peripheral clocks per CAN bit as described in the table
mbed_official	324:406fd2029f23	651	* "Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate" (in section
mbed_official	324:406fd2029f23	652	* "Arbitration and Matching Timing"). This bit can be written only in Freeze mode
mbed_official	324:406fd2029f23	653	* because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	654	*
mbed_official	324:406fd2029f23	655	* Values:
mbed_official	324:406fd2029f23	656	* - 0 - Rx FIFO not enabled.
mbed_official	324:406fd2029f23	657	* - 1 - Rx FIFO enabled.
mbed_official	324:406fd2029f23	658	*/
mbed_official	324:406fd2029f23	659	/@{/
mbed_official	324:406fd2029f23	660	#define BP_CAN_MCR_RFEN (29U) /!< Bit position for CAN_MCR_RFEN. /
mbed_official	324:406fd2029f23	661	#define BM_CAN_MCR_RFEN (0x20000000U) /!< Bit mask for CAN_MCR_RFEN. /
mbed_official	324:406fd2029f23	662	#define BS_CAN_MCR_RFEN (1U) /!< Bit field size in bits for CAN_MCR_RFEN. /
mbed_official	324:406fd2029f23	663
mbed_official	324:406fd2029f23	664	/! @brief Read current value of the CAN_MCR_RFEN field. /
mbed_official	324:406fd2029f23	665	#define BR_CAN_MCR_RFEN(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN))
mbed_official	324:406fd2029f23	666
mbed_official	324:406fd2029f23	667	/! @brief Format value for bitfield CAN_MCR_RFEN. /
mbed_official	324:406fd2029f23	668	#define BF_CAN_MCR_RFEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_RFEN) & BM_CAN_MCR_RFEN)
mbed_official	324:406fd2029f23	669
mbed_official	324:406fd2029f23	670	/! @brief Set the RFEN field to a new value. /
mbed_official	324:406fd2029f23	671	#define BW_CAN_MCR_RFEN(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_RFEN) = (v))
mbed_official	324:406fd2029f23	672	/@}/
mbed_official	324:406fd2029f23	673
mbed_official	324:406fd2029f23	674	/*!
mbed_official	324:406fd2029f23	675	* @name Register CAN_MCR, field FRZ[30] (RW)
mbed_official	324:406fd2029f23	676	*
mbed_official	324:406fd2029f23	677	* The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR
mbed_official	324:406fd2029f23	678	* Register is set or when Debug mode is requested at MCU level . When FRZ is
mbed_official	324:406fd2029f23	679	* asserted, FlexCAN is enabled to enter Freeze mode. Negation of this bit field causes
mbed_official	324:406fd2029f23	680	* FlexCAN to exit from Freeze mode.
mbed_official	324:406fd2029f23	681	*
mbed_official	324:406fd2029f23	682	* Values:
mbed_official	324:406fd2029f23	683	* - 0 - Not enabled to enter Freeze mode.
mbed_official	324:406fd2029f23	684	* - 1 - Enabled to enter Freeze mode.
mbed_official	324:406fd2029f23	685	*/
mbed_official	324:406fd2029f23	686	/@{/
mbed_official	324:406fd2029f23	687	#define BP_CAN_MCR_FRZ (30U) /!< Bit position for CAN_MCR_FRZ. /
mbed_official	324:406fd2029f23	688	#define BM_CAN_MCR_FRZ (0x40000000U) /!< Bit mask for CAN_MCR_FRZ. /
mbed_official	324:406fd2029f23	689	#define BS_CAN_MCR_FRZ (1U) /!< Bit field size in bits for CAN_MCR_FRZ. /
mbed_official	324:406fd2029f23	690
mbed_official	324:406fd2029f23	691	/! @brief Read current value of the CAN_MCR_FRZ field. /
mbed_official	324:406fd2029f23	692	#define BR_CAN_MCR_FRZ(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ))
mbed_official	324:406fd2029f23	693
mbed_official	324:406fd2029f23	694	/! @brief Format value for bitfield CAN_MCR_FRZ. /
mbed_official	324:406fd2029f23	695	#define BF_CAN_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_FRZ) & BM_CAN_MCR_FRZ)
mbed_official	324:406fd2029f23	696
mbed_official	324:406fd2029f23	697	/! @brief Set the FRZ field to a new value. /
mbed_official	324:406fd2029f23	698	#define BW_CAN_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_FRZ) = (v))
mbed_official	324:406fd2029f23	699	/@}/
mbed_official	324:406fd2029f23	700
mbed_official	324:406fd2029f23	701	/*!
mbed_official	324:406fd2029f23	702	* @name Register CAN_MCR, field MDIS[31] (RW)
mbed_official	324:406fd2029f23	703	*
mbed_official	324:406fd2029f23	704	* This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN
mbed_official	324:406fd2029f23	705	* disables the clocks to the CAN Protocol Engine and Controller Host Interface
mbed_official	324:406fd2029f23	706	* sub-modules. This is the only bit within this register not affected by soft
mbed_official	324:406fd2029f23	707	* reset.
mbed_official	324:406fd2029f23	708	*
mbed_official	324:406fd2029f23	709	* Values:
mbed_official	324:406fd2029f23	710	* - 0 - Enable the FlexCAN module.
mbed_official	324:406fd2029f23	711	* - 1 - Disable the FlexCAN module.
mbed_official	324:406fd2029f23	712	*/
mbed_official	324:406fd2029f23	713	/@{/
mbed_official	324:406fd2029f23	714	#define BP_CAN_MCR_MDIS (31U) /!< Bit position for CAN_MCR_MDIS. /
mbed_official	324:406fd2029f23	715	#define BM_CAN_MCR_MDIS (0x80000000U) /!< Bit mask for CAN_MCR_MDIS. /
mbed_official	324:406fd2029f23	716	#define BS_CAN_MCR_MDIS (1U) /!< Bit field size in bits for CAN_MCR_MDIS. /
mbed_official	324:406fd2029f23	717
mbed_official	324:406fd2029f23	718	/! @brief Read current value of the CAN_MCR_MDIS field. /
mbed_official	324:406fd2029f23	719	#define BR_CAN_MCR_MDIS(x) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS))
mbed_official	324:406fd2029f23	720
mbed_official	324:406fd2029f23	721	/! @brief Format value for bitfield CAN_MCR_MDIS. /
mbed_official	324:406fd2029f23	722	#define BF_CAN_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_MCR_MDIS) & BM_CAN_MCR_MDIS)
mbed_official	324:406fd2029f23	723
mbed_official	324:406fd2029f23	724	/! @brief Set the MDIS field to a new value. /
mbed_official	324:406fd2029f23	725	#define BW_CAN_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_CAN_MCR_ADDR(x), BP_CAN_MCR_MDIS) = (v))
mbed_official	324:406fd2029f23	726	/@}/
mbed_official	324:406fd2029f23	727
mbed_official	324:406fd2029f23	728	/*******************************************************************************
mbed_official	324:406fd2029f23	729	* HW_CAN_CTRL1 - Control 1 register
mbed_official	324:406fd2029f23	730	******************************************************************************/
mbed_official	324:406fd2029f23	731
mbed_official	324:406fd2029f23	732	/*!
mbed_official	324:406fd2029f23	733	* @brief HW_CAN_CTRL1 - Control 1 register (RW)
mbed_official	324:406fd2029f23	734	*
mbed_official	324:406fd2029f23	735	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	736	*
mbed_official	324:406fd2029f23	737	* This register is defined for specific FlexCAN control features related to the
mbed_official	324:406fd2029f23	738	* CAN bus, such as bit-rate, programmable sampling point within an Rx bit, Loop
mbed_official	324:406fd2029f23	739	* Back mode, Listen-Only mode, Bus Off recovery behavior and interrupt enabling
mbed_official	324:406fd2029f23	740	* (Bus-Off, Error, Warning). It also determines the Division Factor for the
mbed_official	324:406fd2029f23	741	* clock prescaler.
mbed_official	324:406fd2029f23	742	*/
mbed_official	324:406fd2029f23	743	typedef union _hw_can_ctrl1
mbed_official	324:406fd2029f23	744	{
mbed_official	324:406fd2029f23	745	uint32_t U;
mbed_official	324:406fd2029f23	746	struct _hw_can_ctrl1_bitfields
mbed_official	324:406fd2029f23	747	{
mbed_official	324:406fd2029f23	748	uint32_t PROPSEG : 3; /!< [2:0] Propagation Segment /
mbed_official	324:406fd2029f23	749	uint32_t LOM : 1; /!< [3] Listen-Only Mode /
mbed_official	324:406fd2029f23	750	uint32_t LBUF : 1; /!< [4] Lowest Buffer Transmitted First /
mbed_official	324:406fd2029f23	751	uint32_t TSYN : 1; /!< [5] Timer Sync /
mbed_official	324:406fd2029f23	752	uint32_t BOFFREC : 1; /!< [6] Bus Off Recovery /
mbed_official	324:406fd2029f23	753	uint32_t SMP : 1; /!< [7] CAN Bit Sampling /
mbed_official	324:406fd2029f23	754	uint32_t RESERVED0 : 2; /!< [9:8] /
mbed_official	324:406fd2029f23	755	uint32_t RWRNMSK : 1; /!< [10] Rx Warning Interrupt Mask /
mbed_official	324:406fd2029f23	756	uint32_t TWRNMSK : 1; /!< [11] Tx Warning Interrupt Mask /
mbed_official	324:406fd2029f23	757	uint32_t LPB : 1; /!< [12] Loop Back Mode /
mbed_official	324:406fd2029f23	758	uint32_t CLKSRC : 1; /!< [13] CAN Engine Clock Source /
mbed_official	324:406fd2029f23	759	uint32_t ERRMSK : 1; /!< [14] Error Mask /
mbed_official	324:406fd2029f23	760	uint32_t BOFFMSK : 1; /!< [15] Bus Off Mask /
mbed_official	324:406fd2029f23	761	uint32_t PSEG2 : 3; /!< [18:16] Phase Segment 2 /
mbed_official	324:406fd2029f23	762	uint32_t PSEG1 : 3; /!< [21:19] Phase Segment 1 /
mbed_official	324:406fd2029f23	763	uint32_t RJW : 2; /!< [23:22] Resync Jump Width /
mbed_official	324:406fd2029f23	764	uint32_t PRESDIV : 8; /!< [31:24] Prescaler Division Factor /
mbed_official	324:406fd2029f23	765	} B;
mbed_official	324:406fd2029f23	766	} hw_can_ctrl1_t;
mbed_official	324:406fd2029f23	767
mbed_official	324:406fd2029f23	768	/*!
mbed_official	324:406fd2029f23	769	* @name Constants and macros for entire CAN_CTRL1 register
mbed_official	324:406fd2029f23	770	*/
mbed_official	324:406fd2029f23	771	/@{/
mbed_official	324:406fd2029f23	772	#define HW_CAN_CTRL1_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	773
mbed_official	324:406fd2029f23	774	#define HW_CAN_CTRL1(x) ((__IO hw_can_ctrl1_t ) HW_CAN_CTRL1_ADDR(x))
mbed_official	324:406fd2029f23	775	#define HW_CAN_CTRL1_RD(x) (HW_CAN_CTRL1(x).U)
mbed_official	324:406fd2029f23	776	#define HW_CAN_CTRL1_WR(x, v) (HW_CAN_CTRL1(x).U = (v))
mbed_official	324:406fd2029f23	777	#define HW_CAN_CTRL1_SET(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	778	#define HW_CAN_CTRL1_CLR(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	779	#define HW_CAN_CTRL1_TOG(x, v) (HW_CAN_CTRL1_WR(x, HW_CAN_CTRL1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	780	/@}/
mbed_official	324:406fd2029f23	781
mbed_official	324:406fd2029f23	782	/*
mbed_official	324:406fd2029f23	783	* Constants & macros for individual CAN_CTRL1 bitfields
mbed_official	324:406fd2029f23	784	*/
mbed_official	324:406fd2029f23	785
mbed_official	324:406fd2029f23	786	/*!
mbed_official	324:406fd2029f23	787	* @name Register CAN_CTRL1, field PROPSEG[2:0] (RW)
mbed_official	324:406fd2029f23	788	*
mbed_official	324:406fd2029f23	789	* This 3-bit field defines the length of the Propagation Segment in the bit
mbed_official	324:406fd2029f23	790	* time. The valid programmable values are 0-7. This field can be written only in
mbed_official	324:406fd2029f23	791	* Freeze mode because it is blocked by hardware in other modes. Propagation
mbed_official	324:406fd2029f23	792	* Segment Time = (PROPSEG + 1) * Time-Quanta. Time-Quantum = one Sclock period.
mbed_official	324:406fd2029f23	793	*/
mbed_official	324:406fd2029f23	794	/@{/
mbed_official	324:406fd2029f23	795	#define BP_CAN_CTRL1_PROPSEG (0U) /!< Bit position for CAN_CTRL1_PROPSEG. /
mbed_official	324:406fd2029f23	796	#define BM_CAN_CTRL1_PROPSEG (0x00000007U) /!< Bit mask for CAN_CTRL1_PROPSEG. /
mbed_official	324:406fd2029f23	797	#define BS_CAN_CTRL1_PROPSEG (3U) /!< Bit field size in bits for CAN_CTRL1_PROPSEG. /
mbed_official	324:406fd2029f23	798
mbed_official	324:406fd2029f23	799	/! @brief Read current value of the CAN_CTRL1_PROPSEG field. /
mbed_official	324:406fd2029f23	800	#define BR_CAN_CTRL1_PROPSEG(x) (HW_CAN_CTRL1(x).B.PROPSEG)
mbed_official	324:406fd2029f23	801
mbed_official	324:406fd2029f23	802	/! @brief Format value for bitfield CAN_CTRL1_PROPSEG. /
mbed_official	324:406fd2029f23	803	#define BF_CAN_CTRL1_PROPSEG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PROPSEG) & BM_CAN_CTRL1_PROPSEG)
mbed_official	324:406fd2029f23	804
mbed_official	324:406fd2029f23	805	/! @brief Set the PROPSEG field to a new value. /
mbed_official	324:406fd2029f23	806	#define BW_CAN_CTRL1_PROPSEG(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PROPSEG) \| BF_CAN_CTRL1_PROPSEG(v)))
mbed_official	324:406fd2029f23	807	/@}/
mbed_official	324:406fd2029f23	808
mbed_official	324:406fd2029f23	809	/*!
mbed_official	324:406fd2029f23	810	* @name Register CAN_CTRL1, field LOM[3] (RW)
mbed_official	324:406fd2029f23	811	*
mbed_official	324:406fd2029f23	812	* This bit configures FlexCAN to operate in Listen-Only mode. In this mode,
mbed_official	324:406fd2029f23	813	* transmission is disabled, all error counters are frozen and the module operates
mbed_official	324:406fd2029f23	814	* in a CAN Error Passive mode. Only messages acknowledged by another CAN station
mbed_official	324:406fd2029f23	815	* will be received. If FlexCAN detects a message that has not been acknowledged,
mbed_official	324:406fd2029f23	816	* it will flag a BIT0 error without changing the REC, as if it was trying to
mbed_official	324:406fd2029f23	817	* acknowledge the message. Listen-Only mode acknowledgement can be obtained by the
mbed_official	324:406fd2029f23	818	* state of ESR1[FLTCONF] field which is Passive Error when Listen-Only mode is
mbed_official	324:406fd2029f23	819	* entered. There can be some delay between the Listen-Only mode request and
mbed_official	324:406fd2029f23	820	* acknowledge. This bit can be written only in Freeze mode because it is blocked by
mbed_official	324:406fd2029f23	821	* hardware in other modes.
mbed_official	324:406fd2029f23	822	*
mbed_official	324:406fd2029f23	823	* Values:
mbed_official	324:406fd2029f23	824	* - 0 - Listen-Only mode is deactivated.
mbed_official	324:406fd2029f23	825	* - 1 - FlexCAN module operates in Listen-Only mode.
mbed_official	324:406fd2029f23	826	*/
mbed_official	324:406fd2029f23	827	/@{/
mbed_official	324:406fd2029f23	828	#define BP_CAN_CTRL1_LOM (3U) /!< Bit position for CAN_CTRL1_LOM. /
mbed_official	324:406fd2029f23	829	#define BM_CAN_CTRL1_LOM (0x00000008U) /!< Bit mask for CAN_CTRL1_LOM. /
mbed_official	324:406fd2029f23	830	#define BS_CAN_CTRL1_LOM (1U) /!< Bit field size in bits for CAN_CTRL1_LOM. /
mbed_official	324:406fd2029f23	831
mbed_official	324:406fd2029f23	832	/! @brief Read current value of the CAN_CTRL1_LOM field. /
mbed_official	324:406fd2029f23	833	#define BR_CAN_CTRL1_LOM(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM))
mbed_official	324:406fd2029f23	834
mbed_official	324:406fd2029f23	835	/! @brief Format value for bitfield CAN_CTRL1_LOM. /
mbed_official	324:406fd2029f23	836	#define BF_CAN_CTRL1_LOM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LOM) & BM_CAN_CTRL1_LOM)
mbed_official	324:406fd2029f23	837
mbed_official	324:406fd2029f23	838	/! @brief Set the LOM field to a new value. /
mbed_official	324:406fd2029f23	839	#define BW_CAN_CTRL1_LOM(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LOM) = (v))
mbed_official	324:406fd2029f23	840	/@}/
mbed_official	324:406fd2029f23	841
mbed_official	324:406fd2029f23	842	/*!
mbed_official	324:406fd2029f23	843	* @name Register CAN_CTRL1, field LBUF[4] (RW)
mbed_official	324:406fd2029f23	844	*
mbed_official	324:406fd2029f23	845	* This bit defines the ordering mechanism for Message Buffer transmission. When
mbed_official	324:406fd2029f23	846	* asserted, the LPRIOEN bit does not affect the priority arbitration. This bit
mbed_official	324:406fd2029f23	847	* can be written only in Freeze mode because it is blocked by hardware in other
mbed_official	324:406fd2029f23	848	* modes.
mbed_official	324:406fd2029f23	849	*
mbed_official	324:406fd2029f23	850	* Values:
mbed_official	324:406fd2029f23	851	* - 0 - Buffer with highest priority is transmitted first.
mbed_official	324:406fd2029f23	852	* - 1 - Lowest number buffer is transmitted first.
mbed_official	324:406fd2029f23	853	*/
mbed_official	324:406fd2029f23	854	/@{/
mbed_official	324:406fd2029f23	855	#define BP_CAN_CTRL1_LBUF (4U) /!< Bit position for CAN_CTRL1_LBUF. /
mbed_official	324:406fd2029f23	856	#define BM_CAN_CTRL1_LBUF (0x00000010U) /!< Bit mask for CAN_CTRL1_LBUF. /
mbed_official	324:406fd2029f23	857	#define BS_CAN_CTRL1_LBUF (1U) /!< Bit field size in bits for CAN_CTRL1_LBUF. /
mbed_official	324:406fd2029f23	858
mbed_official	324:406fd2029f23	859	/! @brief Read current value of the CAN_CTRL1_LBUF field. /
mbed_official	324:406fd2029f23	860	#define BR_CAN_CTRL1_LBUF(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF))
mbed_official	324:406fd2029f23	861
mbed_official	324:406fd2029f23	862	/! @brief Format value for bitfield CAN_CTRL1_LBUF. /
mbed_official	324:406fd2029f23	863	#define BF_CAN_CTRL1_LBUF(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LBUF) & BM_CAN_CTRL1_LBUF)
mbed_official	324:406fd2029f23	864
mbed_official	324:406fd2029f23	865	/! @brief Set the LBUF field to a new value. /
mbed_official	324:406fd2029f23	866	#define BW_CAN_CTRL1_LBUF(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LBUF) = (v))
mbed_official	324:406fd2029f23	867	/@}/
mbed_official	324:406fd2029f23	868
mbed_official	324:406fd2029f23	869	/*!
mbed_official	324:406fd2029f23	870	* @name Register CAN_CTRL1, field TSYN[5] (RW)
mbed_official	324:406fd2029f23	871	*
mbed_official	324:406fd2029f23	872	* This bit enables a mechanism that resets the free-running timer each time a
mbed_official	324:406fd2029f23	873	* message is received in Message Buffer 0. This feature provides means to
mbed_official	324:406fd2029f23	874	* synchronize multiple FlexCAN stations with a special "SYNC" message, that is, global
mbed_official	324:406fd2029f23	875	* network time. If the RFEN bit in MCR is set (Rx FIFO enabled), the first
mbed_official	324:406fd2029f23	876	* available Mailbox, according to CTRL2[RFFN] setting, is used for timer
mbed_official	324:406fd2029f23	877	* synchronization instead of MB0. This bit can be written only in Freeze mode because it is
mbed_official	324:406fd2029f23	878	* blocked by hardware in other modes.
mbed_official	324:406fd2029f23	879	*
mbed_official	324:406fd2029f23	880	* Values:
mbed_official	324:406fd2029f23	881	* - 0 - Timer Sync feature disabled
mbed_official	324:406fd2029f23	882	* - 1 - Timer Sync feature enabled
mbed_official	324:406fd2029f23	883	*/
mbed_official	324:406fd2029f23	884	/@{/
mbed_official	324:406fd2029f23	885	#define BP_CAN_CTRL1_TSYN (5U) /!< Bit position for CAN_CTRL1_TSYN. /
mbed_official	324:406fd2029f23	886	#define BM_CAN_CTRL1_TSYN (0x00000020U) /!< Bit mask for CAN_CTRL1_TSYN. /
mbed_official	324:406fd2029f23	887	#define BS_CAN_CTRL1_TSYN (1U) /!< Bit field size in bits for CAN_CTRL1_TSYN. /
mbed_official	324:406fd2029f23	888
mbed_official	324:406fd2029f23	889	/! @brief Read current value of the CAN_CTRL1_TSYN field. /
mbed_official	324:406fd2029f23	890	#define BR_CAN_CTRL1_TSYN(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN))
mbed_official	324:406fd2029f23	891
mbed_official	324:406fd2029f23	892	/! @brief Format value for bitfield CAN_CTRL1_TSYN. /
mbed_official	324:406fd2029f23	893	#define BF_CAN_CTRL1_TSYN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TSYN) & BM_CAN_CTRL1_TSYN)
mbed_official	324:406fd2029f23	894
mbed_official	324:406fd2029f23	895	/! @brief Set the TSYN field to a new value. /
mbed_official	324:406fd2029f23	896	#define BW_CAN_CTRL1_TSYN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TSYN) = (v))
mbed_official	324:406fd2029f23	897	/@}/
mbed_official	324:406fd2029f23	898
mbed_official	324:406fd2029f23	899	/*!
mbed_official	324:406fd2029f23	900	* @name Register CAN_CTRL1, field BOFFREC[6] (RW)
mbed_official	324:406fd2029f23	901	*
mbed_official	324:406fd2029f23	902	* This bit defines how FlexCAN recovers from Bus Off state. If this bit is
mbed_official	324:406fd2029f23	903	* negated, automatic recovering from Bus Off state occurs according to the CAN
mbed_official	324:406fd2029f23	904	* Specification 2.0B. If the bit is asserted, automatic recovering from Bus Off is
mbed_official	324:406fd2029f23	905	* disabled and the module remains in Bus Off state until the bit is negated by the
mbed_official	324:406fd2029f23	906	* user. If the negation occurs before 128 sequences of 11 recessive bits are
mbed_official	324:406fd2029f23	907	* detected on the CAN bus, then Bus Off recovery happens as if the BOFFREC bit had
mbed_official	324:406fd2029f23	908	* never been asserted. If the negation occurs after 128 sequences of 11
mbed_official	324:406fd2029f23	909	* recessive bits occurred, then FlexCAN will re-synchronize to the bus by waiting for
mbed_official	324:406fd2029f23	910	* 11 recessive bits before joining the bus. After negation, the BOFFREC bit can
mbed_official	324:406fd2029f23	911	* be re-asserted again during Bus Off, but it will be effective only the next
mbed_official	324:406fd2029f23	912	* time the module enters Bus Off. If BOFFREC was negated when the module entered
mbed_official	324:406fd2029f23	913	* Bus Off, asserting it during Bus Off will not be effective for the current Bus
mbed_official	324:406fd2029f23	914	* Off recovery.
mbed_official	324:406fd2029f23	915	*
mbed_official	324:406fd2029f23	916	* Values:
mbed_official	324:406fd2029f23	917	* - 0 - Automatic recovering from Bus Off state enabled, according to CAN Spec
mbed_official	324:406fd2029f23	918	* 2.0 part B.
mbed_official	324:406fd2029f23	919	* - 1 - Automatic recovering from Bus Off state disabled.
mbed_official	324:406fd2029f23	920	*/
mbed_official	324:406fd2029f23	921	/@{/
mbed_official	324:406fd2029f23	922	#define BP_CAN_CTRL1_BOFFREC (6U) /!< Bit position for CAN_CTRL1_BOFFREC. /
mbed_official	324:406fd2029f23	923	#define BM_CAN_CTRL1_BOFFREC (0x00000040U) /!< Bit mask for CAN_CTRL1_BOFFREC. /
mbed_official	324:406fd2029f23	924	#define BS_CAN_CTRL1_BOFFREC (1U) /!< Bit field size in bits for CAN_CTRL1_BOFFREC. /
mbed_official	324:406fd2029f23	925
mbed_official	324:406fd2029f23	926	/! @brief Read current value of the CAN_CTRL1_BOFFREC field. /
mbed_official	324:406fd2029f23	927	#define BR_CAN_CTRL1_BOFFREC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC))
mbed_official	324:406fd2029f23	928
mbed_official	324:406fd2029f23	929	/! @brief Format value for bitfield CAN_CTRL1_BOFFREC. /
mbed_official	324:406fd2029f23	930	#define BF_CAN_CTRL1_BOFFREC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFREC) & BM_CAN_CTRL1_BOFFREC)
mbed_official	324:406fd2029f23	931
mbed_official	324:406fd2029f23	932	/! @brief Set the BOFFREC field to a new value. /
mbed_official	324:406fd2029f23	933	#define BW_CAN_CTRL1_BOFFREC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFREC) = (v))
mbed_official	324:406fd2029f23	934	/@}/
mbed_official	324:406fd2029f23	935
mbed_official	324:406fd2029f23	936	/*!
mbed_official	324:406fd2029f23	937	* @name Register CAN_CTRL1, field SMP[7] (RW)
mbed_official	324:406fd2029f23	938	*
mbed_official	324:406fd2029f23	939	* This bit defines the sampling mode of CAN bits at the Rx input. This bit can
mbed_official	324:406fd2029f23	940	* be written only in Freeze mode because it is blocked by hardware in other
mbed_official	324:406fd2029f23	941	* modes.
mbed_official	324:406fd2029f23	942	*
mbed_official	324:406fd2029f23	943	* Values:
mbed_official	324:406fd2029f23	944	* - 0 - Just one sample is used to determine the bit value.
mbed_official	324:406fd2029f23	945	* - 1 - Three samples are used to determine the value of the received bit: the
mbed_official	324:406fd2029f23	946	* regular one (sample point) and 2 preceding samples; a majority rule is
mbed_official	324:406fd2029f23	947	* used.
mbed_official	324:406fd2029f23	948	*/
mbed_official	324:406fd2029f23	949	/@{/
mbed_official	324:406fd2029f23	950	#define BP_CAN_CTRL1_SMP (7U) /!< Bit position for CAN_CTRL1_SMP. /
mbed_official	324:406fd2029f23	951	#define BM_CAN_CTRL1_SMP (0x00000080U) /!< Bit mask for CAN_CTRL1_SMP. /
mbed_official	324:406fd2029f23	952	#define BS_CAN_CTRL1_SMP (1U) /!< Bit field size in bits for CAN_CTRL1_SMP. /
mbed_official	324:406fd2029f23	953
mbed_official	324:406fd2029f23	954	/! @brief Read current value of the CAN_CTRL1_SMP field. /
mbed_official	324:406fd2029f23	955	#define BR_CAN_CTRL1_SMP(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP))
mbed_official	324:406fd2029f23	956
mbed_official	324:406fd2029f23	957	/! @brief Format value for bitfield CAN_CTRL1_SMP. /
mbed_official	324:406fd2029f23	958	#define BF_CAN_CTRL1_SMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_SMP) & BM_CAN_CTRL1_SMP)
mbed_official	324:406fd2029f23	959
mbed_official	324:406fd2029f23	960	/! @brief Set the SMP field to a new value. /
mbed_official	324:406fd2029f23	961	#define BW_CAN_CTRL1_SMP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_SMP) = (v))
mbed_official	324:406fd2029f23	962	/@}/
mbed_official	324:406fd2029f23	963
mbed_official	324:406fd2029f23	964	/*!
mbed_official	324:406fd2029f23	965	* @name Register CAN_CTRL1, field RWRNMSK[10] (RW)
mbed_official	324:406fd2029f23	966	*
mbed_official	324:406fd2029f23	967	* This bit provides a mask for the Rx Warning Interrupt associated with the
mbed_official	324:406fd2029f23	968	* RWRNINT flag in the Error and Status Register. This bit is read as zero when
mbed_official	324:406fd2029f23	969	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
mbed_official	324:406fd2029f23	970	* asserted.
mbed_official	324:406fd2029f23	971	*
mbed_official	324:406fd2029f23	972	* Values:
mbed_official	324:406fd2029f23	973	* - 0 - Rx Warning Interrupt disabled.
mbed_official	324:406fd2029f23	974	* - 1 - Rx Warning Interrupt enabled.
mbed_official	324:406fd2029f23	975	*/
mbed_official	324:406fd2029f23	976	/@{/
mbed_official	324:406fd2029f23	977	#define BP_CAN_CTRL1_RWRNMSK (10U) /!< Bit position for CAN_CTRL1_RWRNMSK. /
mbed_official	324:406fd2029f23	978	#define BM_CAN_CTRL1_RWRNMSK (0x00000400U) /!< Bit mask for CAN_CTRL1_RWRNMSK. /
mbed_official	324:406fd2029f23	979	#define BS_CAN_CTRL1_RWRNMSK (1U) /!< Bit field size in bits for CAN_CTRL1_RWRNMSK. /
mbed_official	324:406fd2029f23	980
mbed_official	324:406fd2029f23	981	/! @brief Read current value of the CAN_CTRL1_RWRNMSK field. /
mbed_official	324:406fd2029f23	982	#define BR_CAN_CTRL1_RWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK))
mbed_official	324:406fd2029f23	983
mbed_official	324:406fd2029f23	984	/! @brief Format value for bitfield CAN_CTRL1_RWRNMSK. /
mbed_official	324:406fd2029f23	985	#define BF_CAN_CTRL1_RWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RWRNMSK) & BM_CAN_CTRL1_RWRNMSK)
mbed_official	324:406fd2029f23	986
mbed_official	324:406fd2029f23	987	/! @brief Set the RWRNMSK field to a new value. /
mbed_official	324:406fd2029f23	988	#define BW_CAN_CTRL1_RWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_RWRNMSK) = (v))
mbed_official	324:406fd2029f23	989	/@}/
mbed_official	324:406fd2029f23	990
mbed_official	324:406fd2029f23	991	/*!
mbed_official	324:406fd2029f23	992	* @name Register CAN_CTRL1, field TWRNMSK[11] (RW)
mbed_official	324:406fd2029f23	993	*
mbed_official	324:406fd2029f23	994	* This bit provides a mask for the Tx Warning Interrupt associated with the
mbed_official	324:406fd2029f23	995	* TWRNINT flag in the Error and Status Register. This bit is read as zero when
mbed_official	324:406fd2029f23	996	* MCR[WRNEN] bit is negated. This bit can be written only if MCR[WRNEN] bit is
mbed_official	324:406fd2029f23	997	* asserted.
mbed_official	324:406fd2029f23	998	*
mbed_official	324:406fd2029f23	999	* Values:
mbed_official	324:406fd2029f23	1000	* - 0 - Tx Warning Interrupt disabled.
mbed_official	324:406fd2029f23	1001	* - 1 - Tx Warning Interrupt enabled.
mbed_official	324:406fd2029f23	1002	*/
mbed_official	324:406fd2029f23	1003	/@{/
mbed_official	324:406fd2029f23	1004	#define BP_CAN_CTRL1_TWRNMSK (11U) /!< Bit position for CAN_CTRL1_TWRNMSK. /
mbed_official	324:406fd2029f23	1005	#define BM_CAN_CTRL1_TWRNMSK (0x00000800U) /!< Bit mask for CAN_CTRL1_TWRNMSK. /
mbed_official	324:406fd2029f23	1006	#define BS_CAN_CTRL1_TWRNMSK (1U) /!< Bit field size in bits for CAN_CTRL1_TWRNMSK. /
mbed_official	324:406fd2029f23	1007
mbed_official	324:406fd2029f23	1008	/! @brief Read current value of the CAN_CTRL1_TWRNMSK field. /
mbed_official	324:406fd2029f23	1009	#define BR_CAN_CTRL1_TWRNMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK))
mbed_official	324:406fd2029f23	1010
mbed_official	324:406fd2029f23	1011	/! @brief Format value for bitfield CAN_CTRL1_TWRNMSK. /
mbed_official	324:406fd2029f23	1012	#define BF_CAN_CTRL1_TWRNMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_TWRNMSK) & BM_CAN_CTRL1_TWRNMSK)
mbed_official	324:406fd2029f23	1013
mbed_official	324:406fd2029f23	1014	/! @brief Set the TWRNMSK field to a new value. /
mbed_official	324:406fd2029f23	1015	#define BW_CAN_CTRL1_TWRNMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_TWRNMSK) = (v))
mbed_official	324:406fd2029f23	1016	/@}/
mbed_official	324:406fd2029f23	1017
mbed_official	324:406fd2029f23	1018	/*!
mbed_official	324:406fd2029f23	1019	* @name Register CAN_CTRL1, field LPB[12] (RW)
mbed_official	324:406fd2029f23	1020	*
mbed_official	324:406fd2029f23	1021	* This bit configures FlexCAN to operate in Loop-Back mode. In this mode,
mbed_official	324:406fd2029f23	1022	* FlexCAN performs an internal loop back that can be used for self test operation.
mbed_official	324:406fd2029f23	1023	* The bit stream output of the transmitter is fed back internally to the receiver
mbed_official	324:406fd2029f23	1024	* input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
mbed_official	324:406fd2029f23	1025	* recessive state (logic 1). FlexCAN behaves as it normally does when transmitting,
mbed_official	324:406fd2029f23	1026	* and treats its own transmitted message as a message received from a remote
mbed_official	324:406fd2029f23	1027	* node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN
mbed_official	324:406fd2029f23	1028	* frame acknowledge field, generating an internal acknowledge bit to ensure proper
mbed_official	324:406fd2029f23	1029	* reception of its own message. Both transmit and receive interrupts are
mbed_official	324:406fd2029f23	1030	* generated. This bit can be written only in Freeze mode because it is blocked by
mbed_official	324:406fd2029f23	1031	* hardware in other modes. In this mode, the MCR[SRXDIS] cannot be asserted because
mbed_official	324:406fd2029f23	1032	* this will impede the self reception of a transmitted message.
mbed_official	324:406fd2029f23	1033	*
mbed_official	324:406fd2029f23	1034	* Values:
mbed_official	324:406fd2029f23	1035	* - 0 - Loop Back disabled.
mbed_official	324:406fd2029f23	1036	* - 1 - Loop Back enabled.
mbed_official	324:406fd2029f23	1037	*/
mbed_official	324:406fd2029f23	1038	/@{/
mbed_official	324:406fd2029f23	1039	#define BP_CAN_CTRL1_LPB (12U) /!< Bit position for CAN_CTRL1_LPB. /
mbed_official	324:406fd2029f23	1040	#define BM_CAN_CTRL1_LPB (0x00001000U) /!< Bit mask for CAN_CTRL1_LPB. /
mbed_official	324:406fd2029f23	1041	#define BS_CAN_CTRL1_LPB (1U) /!< Bit field size in bits for CAN_CTRL1_LPB. /
mbed_official	324:406fd2029f23	1042
mbed_official	324:406fd2029f23	1043	/! @brief Read current value of the CAN_CTRL1_LPB field. /
mbed_official	324:406fd2029f23	1044	#define BR_CAN_CTRL1_LPB(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB))
mbed_official	324:406fd2029f23	1045
mbed_official	324:406fd2029f23	1046	/! @brief Format value for bitfield CAN_CTRL1_LPB. /
mbed_official	324:406fd2029f23	1047	#define BF_CAN_CTRL1_LPB(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_LPB) & BM_CAN_CTRL1_LPB)
mbed_official	324:406fd2029f23	1048
mbed_official	324:406fd2029f23	1049	/! @brief Set the LPB field to a new value. /
mbed_official	324:406fd2029f23	1050	#define BW_CAN_CTRL1_LPB(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_LPB) = (v))
mbed_official	324:406fd2029f23	1051	/@}/
mbed_official	324:406fd2029f23	1052
mbed_official	324:406fd2029f23	1053	/*!
mbed_official	324:406fd2029f23	1054	* @name Register CAN_CTRL1, field CLKSRC[13] (RW)
mbed_official	324:406fd2029f23	1055	*
mbed_official	324:406fd2029f23	1056	* This bit selects the clock source to the CAN Protocol Engine (PE) to be
mbed_official	324:406fd2029f23	1057	* either the peripheral clock (driven by the PLL) or the crystal oscillator clock.
mbed_official	324:406fd2029f23	1058	* The selected clock is the one fed to the prescaler to generate the Serial Clock
mbed_official	324:406fd2029f23	1059	* (Sclock). In order to guarantee reliable operation, this bit can be written
mbed_official	324:406fd2029f23	1060	* only in Disable mode because it is blocked by hardware in other modes. See
mbed_official	324:406fd2029f23	1061	* Section "Protocol Timing".
mbed_official	324:406fd2029f23	1062	*
mbed_official	324:406fd2029f23	1063	* Values:
mbed_official	324:406fd2029f23	1064	* - 0 - The CAN engine clock source is the oscillator clock. Under this
mbed_official	324:406fd2029f23	1065	* condition, the oscillator clock frequency must be lower than the bus clock.
mbed_official	324:406fd2029f23	1066	* - 1 - The CAN engine clock source is the peripheral clock.
mbed_official	324:406fd2029f23	1067	*/
mbed_official	324:406fd2029f23	1068	/@{/
mbed_official	324:406fd2029f23	1069	#define BP_CAN_CTRL1_CLKSRC (13U) /!< Bit position for CAN_CTRL1_CLKSRC. /
mbed_official	324:406fd2029f23	1070	#define BM_CAN_CTRL1_CLKSRC (0x00002000U) /!< Bit mask for CAN_CTRL1_CLKSRC. /
mbed_official	324:406fd2029f23	1071	#define BS_CAN_CTRL1_CLKSRC (1U) /!< Bit field size in bits for CAN_CTRL1_CLKSRC. /
mbed_official	324:406fd2029f23	1072
mbed_official	324:406fd2029f23	1073	/! @brief Read current value of the CAN_CTRL1_CLKSRC field. /
mbed_official	324:406fd2029f23	1074	#define BR_CAN_CTRL1_CLKSRC(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC))
mbed_official	324:406fd2029f23	1075
mbed_official	324:406fd2029f23	1076	/! @brief Format value for bitfield CAN_CTRL1_CLKSRC. /
mbed_official	324:406fd2029f23	1077	#define BF_CAN_CTRL1_CLKSRC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_CLKSRC) & BM_CAN_CTRL1_CLKSRC)
mbed_official	324:406fd2029f23	1078
mbed_official	324:406fd2029f23	1079	/! @brief Set the CLKSRC field to a new value. /
mbed_official	324:406fd2029f23	1080	#define BW_CAN_CTRL1_CLKSRC(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_CLKSRC) = (v))
mbed_official	324:406fd2029f23	1081	/@}/
mbed_official	324:406fd2029f23	1082
mbed_official	324:406fd2029f23	1083	/*!
mbed_official	324:406fd2029f23	1084	* @name Register CAN_CTRL1, field ERRMSK[14] (RW)
mbed_official	324:406fd2029f23	1085	*
mbed_official	324:406fd2029f23	1086	* This bit provides a mask for the Error Interrupt.
mbed_official	324:406fd2029f23	1087	*
mbed_official	324:406fd2029f23	1088	* Values:
mbed_official	324:406fd2029f23	1089	* - 0 - Error interrupt disabled.
mbed_official	324:406fd2029f23	1090	* - 1 - Error interrupt enabled.
mbed_official	324:406fd2029f23	1091	*/
mbed_official	324:406fd2029f23	1092	/@{/
mbed_official	324:406fd2029f23	1093	#define BP_CAN_CTRL1_ERRMSK (14U) /!< Bit position for CAN_CTRL1_ERRMSK. /
mbed_official	324:406fd2029f23	1094	#define BM_CAN_CTRL1_ERRMSK (0x00004000U) /!< Bit mask for CAN_CTRL1_ERRMSK. /
mbed_official	324:406fd2029f23	1095	#define BS_CAN_CTRL1_ERRMSK (1U) /!< Bit field size in bits for CAN_CTRL1_ERRMSK. /
mbed_official	324:406fd2029f23	1096
mbed_official	324:406fd2029f23	1097	/! @brief Read current value of the CAN_CTRL1_ERRMSK field. /
mbed_official	324:406fd2029f23	1098	#define BR_CAN_CTRL1_ERRMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK))
mbed_official	324:406fd2029f23	1099
mbed_official	324:406fd2029f23	1100	/! @brief Format value for bitfield CAN_CTRL1_ERRMSK. /
mbed_official	324:406fd2029f23	1101	#define BF_CAN_CTRL1_ERRMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_ERRMSK) & BM_CAN_CTRL1_ERRMSK)
mbed_official	324:406fd2029f23	1102
mbed_official	324:406fd2029f23	1103	/! @brief Set the ERRMSK field to a new value. /
mbed_official	324:406fd2029f23	1104	#define BW_CAN_CTRL1_ERRMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_ERRMSK) = (v))
mbed_official	324:406fd2029f23	1105	/@}/
mbed_official	324:406fd2029f23	1106
mbed_official	324:406fd2029f23	1107	/*!
mbed_official	324:406fd2029f23	1108	* @name Register CAN_CTRL1, field BOFFMSK[15] (RW)
mbed_official	324:406fd2029f23	1109	*
mbed_official	324:406fd2029f23	1110	* This bit provides a mask for the Bus Off Interrupt.
mbed_official	324:406fd2029f23	1111	*
mbed_official	324:406fd2029f23	1112	* Values:
mbed_official	324:406fd2029f23	1113	* - 0 - Bus Off interrupt disabled.
mbed_official	324:406fd2029f23	1114	* - 1 - Bus Off interrupt enabled.
mbed_official	324:406fd2029f23	1115	*/
mbed_official	324:406fd2029f23	1116	/@{/
mbed_official	324:406fd2029f23	1117	#define BP_CAN_CTRL1_BOFFMSK (15U) /!< Bit position for CAN_CTRL1_BOFFMSK. /
mbed_official	324:406fd2029f23	1118	#define BM_CAN_CTRL1_BOFFMSK (0x00008000U) /!< Bit mask for CAN_CTRL1_BOFFMSK. /
mbed_official	324:406fd2029f23	1119	#define BS_CAN_CTRL1_BOFFMSK (1U) /!< Bit field size in bits for CAN_CTRL1_BOFFMSK. /
mbed_official	324:406fd2029f23	1120
mbed_official	324:406fd2029f23	1121	/! @brief Read current value of the CAN_CTRL1_BOFFMSK field. /
mbed_official	324:406fd2029f23	1122	#define BR_CAN_CTRL1_BOFFMSK(x) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK))
mbed_official	324:406fd2029f23	1123
mbed_official	324:406fd2029f23	1124	/! @brief Format value for bitfield CAN_CTRL1_BOFFMSK. /
mbed_official	324:406fd2029f23	1125	#define BF_CAN_CTRL1_BOFFMSK(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_BOFFMSK) & BM_CAN_CTRL1_BOFFMSK)
mbed_official	324:406fd2029f23	1126
mbed_official	324:406fd2029f23	1127	/! @brief Set the BOFFMSK field to a new value. /
mbed_official	324:406fd2029f23	1128	#define BW_CAN_CTRL1_BOFFMSK(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL1_ADDR(x), BP_CAN_CTRL1_BOFFMSK) = (v))
mbed_official	324:406fd2029f23	1129	/@}/
mbed_official	324:406fd2029f23	1130
mbed_official	324:406fd2029f23	1131	/*!
mbed_official	324:406fd2029f23	1132	* @name Register CAN_CTRL1, field PSEG2[18:16] (RW)
mbed_official	324:406fd2029f23	1133	*
mbed_official	324:406fd2029f23	1134	* This 3-bit field defines the length of Phase Buffer Segment 2 in the bit
mbed_official	324:406fd2029f23	1135	* time. The valid programmable values are 1-7. This field can be written only in
mbed_official	324:406fd2029f23	1136	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
mbed_official	324:406fd2029f23	1137	* Segment 2 = (PSEG2 + 1) * Time-Quanta.
mbed_official	324:406fd2029f23	1138	*/
mbed_official	324:406fd2029f23	1139	/@{/
mbed_official	324:406fd2029f23	1140	#define BP_CAN_CTRL1_PSEG2 (16U) /!< Bit position for CAN_CTRL1_PSEG2. /
mbed_official	324:406fd2029f23	1141	#define BM_CAN_CTRL1_PSEG2 (0x00070000U) /!< Bit mask for CAN_CTRL1_PSEG2. /
mbed_official	324:406fd2029f23	1142	#define BS_CAN_CTRL1_PSEG2 (3U) /!< Bit field size in bits for CAN_CTRL1_PSEG2. /
mbed_official	324:406fd2029f23	1143
mbed_official	324:406fd2029f23	1144	/! @brief Read current value of the CAN_CTRL1_PSEG2 field. /
mbed_official	324:406fd2029f23	1145	#define BR_CAN_CTRL1_PSEG2(x) (HW_CAN_CTRL1(x).B.PSEG2)
mbed_official	324:406fd2029f23	1146
mbed_official	324:406fd2029f23	1147	/! @brief Format value for bitfield CAN_CTRL1_PSEG2. /
mbed_official	324:406fd2029f23	1148	#define BF_CAN_CTRL1_PSEG2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG2) & BM_CAN_CTRL1_PSEG2)
mbed_official	324:406fd2029f23	1149
mbed_official	324:406fd2029f23	1150	/! @brief Set the PSEG2 field to a new value. /
mbed_official	324:406fd2029f23	1151	#define BW_CAN_CTRL1_PSEG2(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG2) \| BF_CAN_CTRL1_PSEG2(v)))
mbed_official	324:406fd2029f23	1152	/@}/
mbed_official	324:406fd2029f23	1153
mbed_official	324:406fd2029f23	1154	/*!
mbed_official	324:406fd2029f23	1155	* @name Register CAN_CTRL1, field PSEG1[21:19] (RW)
mbed_official	324:406fd2029f23	1156	*
mbed_official	324:406fd2029f23	1157	* This 3-bit field defines the length of Phase Buffer Segment 1 in the bit
mbed_official	324:406fd2029f23	1158	* time. The valid programmable values are 0-7. This field can be written only in
mbed_official	324:406fd2029f23	1159	* Freeze mode because it is blocked by hardware in other modes. Phase Buffer
mbed_official	324:406fd2029f23	1160	* Segment 1 = (PSEG1 + 1) * Time-Quanta.
mbed_official	324:406fd2029f23	1161	*/
mbed_official	324:406fd2029f23	1162	/@{/
mbed_official	324:406fd2029f23	1163	#define BP_CAN_CTRL1_PSEG1 (19U) /!< Bit position for CAN_CTRL1_PSEG1. /
mbed_official	324:406fd2029f23	1164	#define BM_CAN_CTRL1_PSEG1 (0x00380000U) /!< Bit mask for CAN_CTRL1_PSEG1. /
mbed_official	324:406fd2029f23	1165	#define BS_CAN_CTRL1_PSEG1 (3U) /!< Bit field size in bits for CAN_CTRL1_PSEG1. /
mbed_official	324:406fd2029f23	1166
mbed_official	324:406fd2029f23	1167	/! @brief Read current value of the CAN_CTRL1_PSEG1 field. /
mbed_official	324:406fd2029f23	1168	#define BR_CAN_CTRL1_PSEG1(x) (HW_CAN_CTRL1(x).B.PSEG1)
mbed_official	324:406fd2029f23	1169
mbed_official	324:406fd2029f23	1170	/! @brief Format value for bitfield CAN_CTRL1_PSEG1. /
mbed_official	324:406fd2029f23	1171	#define BF_CAN_CTRL1_PSEG1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PSEG1) & BM_CAN_CTRL1_PSEG1)
mbed_official	324:406fd2029f23	1172
mbed_official	324:406fd2029f23	1173	/! @brief Set the PSEG1 field to a new value. /
mbed_official	324:406fd2029f23	1174	#define BW_CAN_CTRL1_PSEG1(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PSEG1) \| BF_CAN_CTRL1_PSEG1(v)))
mbed_official	324:406fd2029f23	1175	/@}/
mbed_official	324:406fd2029f23	1176
mbed_official	324:406fd2029f23	1177	/*!
mbed_official	324:406fd2029f23	1178	* @name Register CAN_CTRL1, field RJW[23:22] (RW)
mbed_official	324:406fd2029f23	1179	*
mbed_official	324:406fd2029f23	1180	* This 2-bit field defines the maximum number of time quanta that a bit time
mbed_official	324:406fd2029f23	1181	* can be changed by one re-synchronization. One time quantum is equal to the
mbed_official	324:406fd2029f23	1182	* Sclock period. The valid programmable values are 0-3. This field can be written
mbed_official	324:406fd2029f23	1183	* only in Freeze mode because it is blocked by hardware in other modes. Resync Jump
mbed_official	324:406fd2029f23	1184	* Width = RJW + 1.
mbed_official	324:406fd2029f23	1185	*/
mbed_official	324:406fd2029f23	1186	/@{/
mbed_official	324:406fd2029f23	1187	#define BP_CAN_CTRL1_RJW (22U) /!< Bit position for CAN_CTRL1_RJW. /
mbed_official	324:406fd2029f23	1188	#define BM_CAN_CTRL1_RJW (0x00C00000U) /!< Bit mask for CAN_CTRL1_RJW. /
mbed_official	324:406fd2029f23	1189	#define BS_CAN_CTRL1_RJW (2U) /!< Bit field size in bits for CAN_CTRL1_RJW. /
mbed_official	324:406fd2029f23	1190
mbed_official	324:406fd2029f23	1191	/! @brief Read current value of the CAN_CTRL1_RJW field. /
mbed_official	324:406fd2029f23	1192	#define BR_CAN_CTRL1_RJW(x) (HW_CAN_CTRL1(x).B.RJW)
mbed_official	324:406fd2029f23	1193
mbed_official	324:406fd2029f23	1194	/! @brief Format value for bitfield CAN_CTRL1_RJW. /
mbed_official	324:406fd2029f23	1195	#define BF_CAN_CTRL1_RJW(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_RJW) & BM_CAN_CTRL1_RJW)
mbed_official	324:406fd2029f23	1196
mbed_official	324:406fd2029f23	1197	/! @brief Set the RJW field to a new value. /
mbed_official	324:406fd2029f23	1198	#define BW_CAN_CTRL1_RJW(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_RJW) \| BF_CAN_CTRL1_RJW(v)))
mbed_official	324:406fd2029f23	1199	/@}/
mbed_official	324:406fd2029f23	1200
mbed_official	324:406fd2029f23	1201	/*!
mbed_official	324:406fd2029f23	1202	* @name Register CAN_CTRL1, field PRESDIV[31:24] (RW)
mbed_official	324:406fd2029f23	1203	*
mbed_official	324:406fd2029f23	1204	* This 8-bit field defines the ratio between the PE clock frequency and the
mbed_official	324:406fd2029f23	1205	* Serial Clock (Sclock) frequency. The Sclock period defines the time quantum of
mbed_official	324:406fd2029f23	1206	* the CAN protocol. For the reset value, the Sclock frequency is equal to the PE
mbed_official	324:406fd2029f23	1207	* clock frequency. The Maximum value of this field is 0xFF, that gives a minimum
mbed_official	324:406fd2029f23	1208	* Sclock frequency equal to the PE clock frequency divided by 256. See Section
mbed_official	324:406fd2029f23	1209	* "Protocol Timing". This field can be written only in Freeze mode because it is
mbed_official	324:406fd2029f23	1210	* blocked by hardware in other modes. Sclock frequency = PE clock frequency /
mbed_official	324:406fd2029f23	1211	* (PRESDIV + 1)
mbed_official	324:406fd2029f23	1212	*/
mbed_official	324:406fd2029f23	1213	/@{/
mbed_official	324:406fd2029f23	1214	#define BP_CAN_CTRL1_PRESDIV (24U) /!< Bit position for CAN_CTRL1_PRESDIV. /
mbed_official	324:406fd2029f23	1215	#define BM_CAN_CTRL1_PRESDIV (0xFF000000U) /!< Bit mask for CAN_CTRL1_PRESDIV. /
mbed_official	324:406fd2029f23	1216	#define BS_CAN_CTRL1_PRESDIV (8U) /!< Bit field size in bits for CAN_CTRL1_PRESDIV. /
mbed_official	324:406fd2029f23	1217
mbed_official	324:406fd2029f23	1218	/! @brief Read current value of the CAN_CTRL1_PRESDIV field. /
mbed_official	324:406fd2029f23	1219	#define BR_CAN_CTRL1_PRESDIV(x) (HW_CAN_CTRL1(x).B.PRESDIV)
mbed_official	324:406fd2029f23	1220
mbed_official	324:406fd2029f23	1221	/! @brief Format value for bitfield CAN_CTRL1_PRESDIV. /
mbed_official	324:406fd2029f23	1222	#define BF_CAN_CTRL1_PRESDIV(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL1_PRESDIV) & BM_CAN_CTRL1_PRESDIV)
mbed_official	324:406fd2029f23	1223
mbed_official	324:406fd2029f23	1224	/! @brief Set the PRESDIV field to a new value. /
mbed_official	324:406fd2029f23	1225	#define BW_CAN_CTRL1_PRESDIV(x, v) (HW_CAN_CTRL1_WR(x, (HW_CAN_CTRL1_RD(x) & ~BM_CAN_CTRL1_PRESDIV) \| BF_CAN_CTRL1_PRESDIV(v)))
mbed_official	324:406fd2029f23	1226	/@}/
mbed_official	324:406fd2029f23	1227
mbed_official	324:406fd2029f23	1228	/*******************************************************************************
mbed_official	324:406fd2029f23	1229	* HW_CAN_TIMER - Free Running Timer
mbed_official	324:406fd2029f23	1230	******************************************************************************/
mbed_official	324:406fd2029f23	1231
mbed_official	324:406fd2029f23	1232	/*!
mbed_official	324:406fd2029f23	1233	* @brief HW_CAN_TIMER - Free Running Timer (RW)
mbed_official	324:406fd2029f23	1234	*
mbed_official	324:406fd2029f23	1235	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1236	*
mbed_official	324:406fd2029f23	1237	* This register represents a 16-bit free running counter that can be read and
mbed_official	324:406fd2029f23	1238	* written by the CPU. The timer starts from 0x0 after Reset, counts linearly to
mbed_official	324:406fd2029f23	1239	* 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock, which
mbed_official	324:406fd2029f23	1240	* defines the baud rate on the CAN bus. During a message transmission/reception,
mbed_official	324:406fd2029f23	1241	* it increments by one for each bit that is received or transmitted. When there
mbed_official	324:406fd2029f23	1242	* is no message on the bus, it counts using the previously programmed baud
mbed_official	324:406fd2029f23	1243	* rate. The timer is not incremented during Disable , Stop, and Freeze modes. The
mbed_official	324:406fd2029f23	1244	* timer value is captured when the second bit of the identifier field of any frame
mbed_official	324:406fd2029f23	1245	* is on the CAN bus. This captured value is written into the Time Stamp entry
mbed_official	324:406fd2029f23	1246	* in a message buffer after a successful reception or transmission of a message.
mbed_official	324:406fd2029f23	1247	* If bit CTRL1[TSYN] is asserted, the Timer is reset whenever a message is
mbed_official	324:406fd2029f23	1248	* received in the first available Mailbox, according to CTRL2[RFFN] setting. The CPU
mbed_official	324:406fd2029f23	1249	* can write to this register anytime. However, if the write occurs at the same
mbed_official	324:406fd2029f23	1250	* time that the Timer is being reset by a reception in the first Mailbox, then
mbed_official	324:406fd2029f23	1251	* the write value is discarded. Reading this register affects the Mailbox
mbed_official	324:406fd2029f23	1252	* Unlocking procedure; see Section "Mailbox Lock Mechanism".
mbed_official	324:406fd2029f23	1253	*/
mbed_official	324:406fd2029f23	1254	typedef union _hw_can_timer
mbed_official	324:406fd2029f23	1255	{
mbed_official	324:406fd2029f23	1256	uint32_t U;
mbed_official	324:406fd2029f23	1257	struct _hw_can_timer_bitfields
mbed_official	324:406fd2029f23	1258	{
mbed_official	324:406fd2029f23	1259	uint32_t TIMER : 16; /!< [15:0] Timer Value /
mbed_official	324:406fd2029f23	1260	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	1261	} B;
mbed_official	324:406fd2029f23	1262	} hw_can_timer_t;
mbed_official	324:406fd2029f23	1263
mbed_official	324:406fd2029f23	1264	/*!
mbed_official	324:406fd2029f23	1265	* @name Constants and macros for entire CAN_TIMER register
mbed_official	324:406fd2029f23	1266	*/
mbed_official	324:406fd2029f23	1267	/@{/
mbed_official	324:406fd2029f23	1268	#define HW_CAN_TIMER_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	1269
mbed_official	324:406fd2029f23	1270	#define HW_CAN_TIMER(x) ((__IO hw_can_timer_t ) HW_CAN_TIMER_ADDR(x))
mbed_official	324:406fd2029f23	1271	#define HW_CAN_TIMER_RD(x) (HW_CAN_TIMER(x).U)
mbed_official	324:406fd2029f23	1272	#define HW_CAN_TIMER_WR(x, v) (HW_CAN_TIMER(x).U = (v))
mbed_official	324:406fd2029f23	1273	#define HW_CAN_TIMER_SET(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1274	#define HW_CAN_TIMER_CLR(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1275	#define HW_CAN_TIMER_TOG(x, v) (HW_CAN_TIMER_WR(x, HW_CAN_TIMER_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1276	/@}/
mbed_official	324:406fd2029f23	1277
mbed_official	324:406fd2029f23	1278	/*
mbed_official	324:406fd2029f23	1279	* Constants & macros for individual CAN_TIMER bitfields
mbed_official	324:406fd2029f23	1280	*/
mbed_official	324:406fd2029f23	1281
mbed_official	324:406fd2029f23	1282	/*!
mbed_official	324:406fd2029f23	1283	* @name Register CAN_TIMER, field TIMER[15:0] (RW)
mbed_official	324:406fd2029f23	1284	*
mbed_official	324:406fd2029f23	1285	* Contains the free-running counter value.
mbed_official	324:406fd2029f23	1286	*/
mbed_official	324:406fd2029f23	1287	/@{/
mbed_official	324:406fd2029f23	1288	#define BP_CAN_TIMER_TIMER (0U) /!< Bit position for CAN_TIMER_TIMER. /
mbed_official	324:406fd2029f23	1289	#define BM_CAN_TIMER_TIMER (0x0000FFFFU) /!< Bit mask for CAN_TIMER_TIMER. /
mbed_official	324:406fd2029f23	1290	#define BS_CAN_TIMER_TIMER (16U) /!< Bit field size in bits for CAN_TIMER_TIMER. /
mbed_official	324:406fd2029f23	1291
mbed_official	324:406fd2029f23	1292	/! @brief Read current value of the CAN_TIMER_TIMER field. /
mbed_official	324:406fd2029f23	1293	#define BR_CAN_TIMER_TIMER(x) (HW_CAN_TIMER(x).B.TIMER)
mbed_official	324:406fd2029f23	1294
mbed_official	324:406fd2029f23	1295	/! @brief Format value for bitfield CAN_TIMER_TIMER. /
mbed_official	324:406fd2029f23	1296	#define BF_CAN_TIMER_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_CAN_TIMER_TIMER) & BM_CAN_TIMER_TIMER)
mbed_official	324:406fd2029f23	1297
mbed_official	324:406fd2029f23	1298	/! @brief Set the TIMER field to a new value. /
mbed_official	324:406fd2029f23	1299	#define BW_CAN_TIMER_TIMER(x, v) (HW_CAN_TIMER_WR(x, (HW_CAN_TIMER_RD(x) & ~BM_CAN_TIMER_TIMER) \| BF_CAN_TIMER_TIMER(v)))
mbed_official	324:406fd2029f23	1300	/@}/
mbed_official	324:406fd2029f23	1301
mbed_official	324:406fd2029f23	1302	/*******************************************************************************
mbed_official	324:406fd2029f23	1303	* HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register
mbed_official	324:406fd2029f23	1304	******************************************************************************/
mbed_official	324:406fd2029f23	1305
mbed_official	324:406fd2029f23	1306	/*!
mbed_official	324:406fd2029f23	1307	* @brief HW_CAN_RXMGMASK - Rx Mailboxes Global Mask Register (RW)
mbed_official	324:406fd2029f23	1308	*
mbed_official	324:406fd2029f23	1309	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	1310	*
mbed_official	324:406fd2029f23	1311	* This register is located in RAM. RXMGMASK is provided for legacy application
mbed_official	324:406fd2029f23	1312	* support. When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect. When
mbed_official	324:406fd2029f23	1313	* the MCR[IRMQ] bit is asserted, RXMGMASK has no effect. RXMGMASK is used to
mbed_official	324:406fd2029f23	1314	* mask the filter fields of all Rx MBs, excluding MBs 14-15, which have individual
mbed_official	324:406fd2029f23	1315	* mask registers. This register can only be written in Freeze mode as it is
mbed_official	324:406fd2029f23	1316	* blocked by hardware in other modes.
mbed_official	324:406fd2029f23	1317	*/
mbed_official	324:406fd2029f23	1318	typedef union _hw_can_rxmgmask
mbed_official	324:406fd2029f23	1319	{
mbed_official	324:406fd2029f23	1320	uint32_t U;
mbed_official	324:406fd2029f23	1321	struct _hw_can_rxmgmask_bitfields
mbed_official	324:406fd2029f23	1322	{
mbed_official	324:406fd2029f23	1323	uint32_t MG : 32; /!< [31:0] Rx Mailboxes Global Mask Bits /
mbed_official	324:406fd2029f23	1324	} B;
mbed_official	324:406fd2029f23	1325	} hw_can_rxmgmask_t;
mbed_official	324:406fd2029f23	1326
mbed_official	324:406fd2029f23	1327	/*!
mbed_official	324:406fd2029f23	1328	* @name Constants and macros for entire CAN_RXMGMASK register
mbed_official	324:406fd2029f23	1329	*/
mbed_official	324:406fd2029f23	1330	/@{/
mbed_official	324:406fd2029f23	1331	#define HW_CAN_RXMGMASK_ADDR(x) ((x) + 0x10U)
mbed_official	324:406fd2029f23	1332
mbed_official	324:406fd2029f23	1333	#define HW_CAN_RXMGMASK(x) ((__IO hw_can_rxmgmask_t ) HW_CAN_RXMGMASK_ADDR(x))
mbed_official	324:406fd2029f23	1334	#define HW_CAN_RXMGMASK_RD(x) (HW_CAN_RXMGMASK(x).U)
mbed_official	324:406fd2029f23	1335	#define HW_CAN_RXMGMASK_WR(x, v) (HW_CAN_RXMGMASK(x).U = (v))
mbed_official	324:406fd2029f23	1336	#define HW_CAN_RXMGMASK_SET(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1337	#define HW_CAN_RXMGMASK_CLR(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1338	#define HW_CAN_RXMGMASK_TOG(x, v) (HW_CAN_RXMGMASK_WR(x, HW_CAN_RXMGMASK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1339	/@}/
mbed_official	324:406fd2029f23	1340
mbed_official	324:406fd2029f23	1341	/*
mbed_official	324:406fd2029f23	1342	* Constants & macros for individual CAN_RXMGMASK bitfields
mbed_official	324:406fd2029f23	1343	*/
mbed_official	324:406fd2029f23	1344
mbed_official	324:406fd2029f23	1345	/*!
mbed_official	324:406fd2029f23	1346	* @name Register CAN_RXMGMASK, field MG[31:0] (RW)
mbed_official	324:406fd2029f23	1347	*
mbed_official	324:406fd2029f23	1348	* These bits mask the Mailbox filter bits. Note that the alignment with the ID
mbed_official	324:406fd2029f23	1349	* word of the Mailbox is not perfect as the two most significant MG bits affect
mbed_official	324:406fd2029f23	1350	* the fields RTR and IDE, which are located in the Control and Status word of
mbed_official	324:406fd2029f23	1351	* the Mailbox. The following table shows in detail which MG bits mask each Mailbox
mbed_official	324:406fd2029f23	1352	* filter field. SMB[RTR] RTR bit of the Incoming Frame. It is saved into an
mbed_official	324:406fd2029f23	1353	* auxiliary MB called Rx Serial Message Buffer (Rx SMB). CTRL2[RRS] CTRL2[EACEN]
mbed_official	324:406fd2029f23	1354	* Mailbox filter fields MB[RTR] MB[IDE] MB[ID] Reserved 0 - 0 note If the
mbed_official	324:406fd2029f23	1355	* CTRL2[EACEN] bit is negated, the RTR bit of Mailbox is never compared with the RTR bit
mbed_official	324:406fd2029f23	1356	* of the incoming frame. note If the CTRL2[EACEN] bit is negated, the IDE bit
mbed_official	324:406fd2029f23	1357	* of Mailbox is always compared with the IDE bit of the incoming frame. MG[28:0]
mbed_official	324:406fd2029f23	1358	* MG[31:29] 0 - 1 MG[31] MG[30] MG[28:0] MG[29] 1 0 - - - - MG[31:0] 1 1 0 - -
mbed_official	324:406fd2029f23	1359	* MG[28:0] MG[31:29] 1 1 1 MG[31] MG[30] MG[28:0] MG[29]
mbed_official	324:406fd2029f23	1360	*
mbed_official	324:406fd2029f23	1361	* Values:
mbed_official	324:406fd2029f23	1362	* - 0 - The corresponding bit in the filter is "don't care."
mbed_official	324:406fd2029f23	1363	* - 1 - The corresponding bit in the filter is checked.
mbed_official	324:406fd2029f23	1364	*/
mbed_official	324:406fd2029f23	1365	/@{/
mbed_official	324:406fd2029f23	1366	#define BP_CAN_RXMGMASK_MG (0U) /!< Bit position for CAN_RXMGMASK_MG. /
mbed_official	324:406fd2029f23	1367	#define BM_CAN_RXMGMASK_MG (0xFFFFFFFFU) /!< Bit mask for CAN_RXMGMASK_MG. /
mbed_official	324:406fd2029f23	1368	#define BS_CAN_RXMGMASK_MG (32U) /!< Bit field size in bits for CAN_RXMGMASK_MG. /
mbed_official	324:406fd2029f23	1369
mbed_official	324:406fd2029f23	1370	/! @brief Read current value of the CAN_RXMGMASK_MG field. /
mbed_official	324:406fd2029f23	1371	#define BR_CAN_RXMGMASK_MG(x) (HW_CAN_RXMGMASK(x).U)
mbed_official	324:406fd2029f23	1372
mbed_official	324:406fd2029f23	1373	/! @brief Format value for bitfield CAN_RXMGMASK_MG. /
mbed_official	324:406fd2029f23	1374	#define BF_CAN_RXMGMASK_MG(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXMGMASK_MG) & BM_CAN_RXMGMASK_MG)
mbed_official	324:406fd2029f23	1375
mbed_official	324:406fd2029f23	1376	/! @brief Set the MG field to a new value. /
mbed_official	324:406fd2029f23	1377	#define BW_CAN_RXMGMASK_MG(x, v) (HW_CAN_RXMGMASK_WR(x, v))
mbed_official	324:406fd2029f23	1378	/@}/
mbed_official	324:406fd2029f23	1379
mbed_official	324:406fd2029f23	1380	/*******************************************************************************
mbed_official	324:406fd2029f23	1381	* HW_CAN_RX14MASK - Rx 14 Mask register
mbed_official	324:406fd2029f23	1382	******************************************************************************/
mbed_official	324:406fd2029f23	1383
mbed_official	324:406fd2029f23	1384	/*!
mbed_official	324:406fd2029f23	1385	* @brief HW_CAN_RX14MASK - Rx 14 Mask register (RW)
mbed_official	324:406fd2029f23	1386	*
mbed_official	324:406fd2029f23	1387	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	1388	*
mbed_official	324:406fd2029f23	1389	* This register is located in RAM. RX14MASK is provided for legacy application
mbed_official	324:406fd2029f23	1390	* support. When the MCR[IRMQ] bit is asserted, RX14MASK has no effect. RX14MASK
mbed_official	324:406fd2029f23	1391	* is used to mask the filter fields of Message Buffer 14. This register can only
mbed_official	324:406fd2029f23	1392	* be programmed while the module is in Freeze mode as it is blocked by hardware
mbed_official	324:406fd2029f23	1393	* in other modes.
mbed_official	324:406fd2029f23	1394	*/
mbed_official	324:406fd2029f23	1395	typedef union _hw_can_rx14mask
mbed_official	324:406fd2029f23	1396	{
mbed_official	324:406fd2029f23	1397	uint32_t U;
mbed_official	324:406fd2029f23	1398	struct _hw_can_rx14mask_bitfields
mbed_official	324:406fd2029f23	1399	{
mbed_official	324:406fd2029f23	1400	uint32_t RX14M : 32; /!< [31:0] Rx Buffer 14 Mask Bits /
mbed_official	324:406fd2029f23	1401	} B;
mbed_official	324:406fd2029f23	1402	} hw_can_rx14mask_t;
mbed_official	324:406fd2029f23	1403
mbed_official	324:406fd2029f23	1404	/*!
mbed_official	324:406fd2029f23	1405	* @name Constants and macros for entire CAN_RX14MASK register
mbed_official	324:406fd2029f23	1406	*/
mbed_official	324:406fd2029f23	1407	/@{/
mbed_official	324:406fd2029f23	1408	#define HW_CAN_RX14MASK_ADDR(x) ((x) + 0x14U)
mbed_official	324:406fd2029f23	1409
mbed_official	324:406fd2029f23	1410	#define HW_CAN_RX14MASK(x) ((__IO hw_can_rx14mask_t ) HW_CAN_RX14MASK_ADDR(x))
mbed_official	324:406fd2029f23	1411	#define HW_CAN_RX14MASK_RD(x) (HW_CAN_RX14MASK(x).U)
mbed_official	324:406fd2029f23	1412	#define HW_CAN_RX14MASK_WR(x, v) (HW_CAN_RX14MASK(x).U = (v))
mbed_official	324:406fd2029f23	1413	#define HW_CAN_RX14MASK_SET(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1414	#define HW_CAN_RX14MASK_CLR(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1415	#define HW_CAN_RX14MASK_TOG(x, v) (HW_CAN_RX14MASK_WR(x, HW_CAN_RX14MASK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1416	/@}/
mbed_official	324:406fd2029f23	1417
mbed_official	324:406fd2029f23	1418	/*
mbed_official	324:406fd2029f23	1419	* Constants & macros for individual CAN_RX14MASK bitfields
mbed_official	324:406fd2029f23	1420	*/
mbed_official	324:406fd2029f23	1421
mbed_official	324:406fd2029f23	1422	/*!
mbed_official	324:406fd2029f23	1423	* @name Register CAN_RX14MASK, field RX14M[31:0] (RW)
mbed_official	324:406fd2029f23	1424	*
mbed_official	324:406fd2029f23	1425	* Each mask bit masks the corresponding Mailbox 14 filter field in the same way
mbed_official	324:406fd2029f23	1426	* that RXMGMASK masks other Mailboxes' filters. See the description of the
mbed_official	324:406fd2029f23	1427	* CAN_RXMGMASK register.
mbed_official	324:406fd2029f23	1428	*
mbed_official	324:406fd2029f23	1429	* Values:
mbed_official	324:406fd2029f23	1430	* - 0 - The corresponding bit in the filter is "don't care."
mbed_official	324:406fd2029f23	1431	* - 1 - The corresponding bit in the filter is checked.
mbed_official	324:406fd2029f23	1432	*/
mbed_official	324:406fd2029f23	1433	/@{/
mbed_official	324:406fd2029f23	1434	#define BP_CAN_RX14MASK_RX14M (0U) /!< Bit position for CAN_RX14MASK_RX14M. /
mbed_official	324:406fd2029f23	1435	#define BM_CAN_RX14MASK_RX14M (0xFFFFFFFFU) /!< Bit mask for CAN_RX14MASK_RX14M. /
mbed_official	324:406fd2029f23	1436	#define BS_CAN_RX14MASK_RX14M (32U) /!< Bit field size in bits for CAN_RX14MASK_RX14M. /
mbed_official	324:406fd2029f23	1437
mbed_official	324:406fd2029f23	1438	/! @brief Read current value of the CAN_RX14MASK_RX14M field. /
mbed_official	324:406fd2029f23	1439	#define BR_CAN_RX14MASK_RX14M(x) (HW_CAN_RX14MASK(x).U)
mbed_official	324:406fd2029f23	1440
mbed_official	324:406fd2029f23	1441	/! @brief Format value for bitfield CAN_RX14MASK_RX14M. /
mbed_official	324:406fd2029f23	1442	#define BF_CAN_RX14MASK_RX14M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX14MASK_RX14M) & BM_CAN_RX14MASK_RX14M)
mbed_official	324:406fd2029f23	1443
mbed_official	324:406fd2029f23	1444	/! @brief Set the RX14M field to a new value. /
mbed_official	324:406fd2029f23	1445	#define BW_CAN_RX14MASK_RX14M(x, v) (HW_CAN_RX14MASK_WR(x, v))
mbed_official	324:406fd2029f23	1446	/@}/
mbed_official	324:406fd2029f23	1447
mbed_official	324:406fd2029f23	1448	/*******************************************************************************
mbed_official	324:406fd2029f23	1449	* HW_CAN_RX15MASK - Rx 15 Mask register
mbed_official	324:406fd2029f23	1450	******************************************************************************/
mbed_official	324:406fd2029f23	1451
mbed_official	324:406fd2029f23	1452	/*!
mbed_official	324:406fd2029f23	1453	* @brief HW_CAN_RX15MASK - Rx 15 Mask register (RW)
mbed_official	324:406fd2029f23	1454	*
mbed_official	324:406fd2029f23	1455	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	1456	*
mbed_official	324:406fd2029f23	1457	* This register is located in RAM. RX15MASK is provided for legacy application
mbed_official	324:406fd2029f23	1458	* support. When the MCR[IRMQ] bit is asserted, RX15MASK has no effect. RX15MASK
mbed_official	324:406fd2029f23	1459	* is used to mask the filter fields of Message Buffer 15. This register can be
mbed_official	324:406fd2029f23	1460	* programmed only while the module is in Freeze mode because it is blocked by
mbed_official	324:406fd2029f23	1461	* hardware in other modes.
mbed_official	324:406fd2029f23	1462	*/
mbed_official	324:406fd2029f23	1463	typedef union _hw_can_rx15mask
mbed_official	324:406fd2029f23	1464	{
mbed_official	324:406fd2029f23	1465	uint32_t U;
mbed_official	324:406fd2029f23	1466	struct _hw_can_rx15mask_bitfields
mbed_official	324:406fd2029f23	1467	{
mbed_official	324:406fd2029f23	1468	uint32_t RX15M : 32; /!< [31:0] Rx Buffer 15 Mask Bits /
mbed_official	324:406fd2029f23	1469	} B;
mbed_official	324:406fd2029f23	1470	} hw_can_rx15mask_t;
mbed_official	324:406fd2029f23	1471
mbed_official	324:406fd2029f23	1472	/*!
mbed_official	324:406fd2029f23	1473	* @name Constants and macros for entire CAN_RX15MASK register
mbed_official	324:406fd2029f23	1474	*/
mbed_official	324:406fd2029f23	1475	/@{/
mbed_official	324:406fd2029f23	1476	#define HW_CAN_RX15MASK_ADDR(x) ((x) + 0x18U)
mbed_official	324:406fd2029f23	1477
mbed_official	324:406fd2029f23	1478	#define HW_CAN_RX15MASK(x) ((__IO hw_can_rx15mask_t ) HW_CAN_RX15MASK_ADDR(x))
mbed_official	324:406fd2029f23	1479	#define HW_CAN_RX15MASK_RD(x) (HW_CAN_RX15MASK(x).U)
mbed_official	324:406fd2029f23	1480	#define HW_CAN_RX15MASK_WR(x, v) (HW_CAN_RX15MASK(x).U = (v))
mbed_official	324:406fd2029f23	1481	#define HW_CAN_RX15MASK_SET(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1482	#define HW_CAN_RX15MASK_CLR(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1483	#define HW_CAN_RX15MASK_TOG(x, v) (HW_CAN_RX15MASK_WR(x, HW_CAN_RX15MASK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1484	/@}/
mbed_official	324:406fd2029f23	1485
mbed_official	324:406fd2029f23	1486	/*
mbed_official	324:406fd2029f23	1487	* Constants & macros for individual CAN_RX15MASK bitfields
mbed_official	324:406fd2029f23	1488	*/
mbed_official	324:406fd2029f23	1489
mbed_official	324:406fd2029f23	1490	/*!
mbed_official	324:406fd2029f23	1491	* @name Register CAN_RX15MASK, field RX15M[31:0] (RW)
mbed_official	324:406fd2029f23	1492	*
mbed_official	324:406fd2029f23	1493	* Each mask bit masks the corresponding Mailbox 15 filter field in the same way
mbed_official	324:406fd2029f23	1494	* that RXMGMASK masks other Mailboxes' filters. See the description of the
mbed_official	324:406fd2029f23	1495	* CAN_RXMGMASK register.
mbed_official	324:406fd2029f23	1496	*
mbed_official	324:406fd2029f23	1497	* Values:
mbed_official	324:406fd2029f23	1498	* - 0 - The corresponding bit in the filter is "don't care."
mbed_official	324:406fd2029f23	1499	* - 1 - The corresponding bit in the filter is checked.
mbed_official	324:406fd2029f23	1500	*/
mbed_official	324:406fd2029f23	1501	/@{/
mbed_official	324:406fd2029f23	1502	#define BP_CAN_RX15MASK_RX15M (0U) /!< Bit position for CAN_RX15MASK_RX15M. /
mbed_official	324:406fd2029f23	1503	#define BM_CAN_RX15MASK_RX15M (0xFFFFFFFFU) /!< Bit mask for CAN_RX15MASK_RX15M. /
mbed_official	324:406fd2029f23	1504	#define BS_CAN_RX15MASK_RX15M (32U) /!< Bit field size in bits for CAN_RX15MASK_RX15M. /
mbed_official	324:406fd2029f23	1505
mbed_official	324:406fd2029f23	1506	/! @brief Read current value of the CAN_RX15MASK_RX15M field. /
mbed_official	324:406fd2029f23	1507	#define BR_CAN_RX15MASK_RX15M(x) (HW_CAN_RX15MASK(x).U)
mbed_official	324:406fd2029f23	1508
mbed_official	324:406fd2029f23	1509	/! @brief Format value for bitfield CAN_RX15MASK_RX15M. /
mbed_official	324:406fd2029f23	1510	#define BF_CAN_RX15MASK_RX15M(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RX15MASK_RX15M) & BM_CAN_RX15MASK_RX15M)
mbed_official	324:406fd2029f23	1511
mbed_official	324:406fd2029f23	1512	/! @brief Set the RX15M field to a new value. /
mbed_official	324:406fd2029f23	1513	#define BW_CAN_RX15MASK_RX15M(x, v) (HW_CAN_RX15MASK_WR(x, v))
mbed_official	324:406fd2029f23	1514	/@}/
mbed_official	324:406fd2029f23	1515
mbed_official	324:406fd2029f23	1516	/*******************************************************************************
mbed_official	324:406fd2029f23	1517	* HW_CAN_ECR - Error Counter
mbed_official	324:406fd2029f23	1518	******************************************************************************/
mbed_official	324:406fd2029f23	1519
mbed_official	324:406fd2029f23	1520	/*!
mbed_official	324:406fd2029f23	1521	* @brief HW_CAN_ECR - Error Counter (RW)
mbed_official	324:406fd2029f23	1522	*
mbed_official	324:406fd2029f23	1523	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1524	*
mbed_official	324:406fd2029f23	1525	* This register has two 8-bit fields reflecting the value of two FlexCAN error
mbed_official	324:406fd2029f23	1526	* counters: Transmit Error Counter (TXERRCNT field) and Receive Error Counter
mbed_official	324:406fd2029f23	1527	* (RXERRCNT field). The rules for increasing and decreasing these counters are
mbed_official	324:406fd2029f23	1528	* described in the CAN protocol and are completely implemented in the FlexCAN
mbed_official	324:406fd2029f23	1529	* module. Both counters are read-only except in Freeze mode, where they can be
mbed_official	324:406fd2029f23	1530	* written by the CPU. FlexCAN responds to any bus state as described in the protocol,
mbed_official	324:406fd2029f23	1531	* for example, transmit Error Active or Error Passive flag, delay its
mbed_official	324:406fd2029f23	1532	* transmission start time (Error Passive) and avoid any influence on the bus when in Bus
mbed_official	324:406fd2029f23	1533	* Off state. The following are the basic rules for FlexCAN bus state transitions:
mbed_official	324:406fd2029f23	1534	* If the value of TXERRCNT or RXERRCNT increases to be greater than or equal to
mbed_official	324:406fd2029f23	1535	* 128, the FLTCONF field in the Error and Status Register is updated to reflect
mbed_official	324:406fd2029f23	1536	* 'Error Passive' state. If the FlexCAN state is 'Error Passive', and either
mbed_official	324:406fd2029f23	1537	* TXERRCNT or RXERRCNT decrements to a value less than or equal to 127 while the
mbed_official	324:406fd2029f23	1538	* other already satisfies this condition, the FLTCONF field in the Error and
mbed_official	324:406fd2029f23	1539	* Status Register is updated to reflect 'Error Active' state. If the value of
mbed_official	324:406fd2029f23	1540	* TXERRCNT increases to be greater than 255, the FLTCONF field in the Error and Status
mbed_official	324:406fd2029f23	1541	* Register is updated to reflect 'Bus Off' state, and an interrupt may be
mbed_official	324:406fd2029f23	1542	* issued. The value of TXERRCNT is then reset to zero. If FlexCAN is in 'Bus Off'
mbed_official	324:406fd2029f23	1543	* state, then TXERRCNT is cascaded together with another internal counter to count
mbed_official	324:406fd2029f23	1544	* the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
mbed_official	324:406fd2029f23	1545	* TXERRCNT is reset to zero and counts in a manner where the internal counter counts
mbed_official	324:406fd2029f23	1546	* 11 such bits and then wraps around while incrementing the TXERRCNT. When
mbed_official	324:406fd2029f23	1547	* TXERRCNT reaches the value of 128, the FLTCONF field in the Error and Status
mbed_official	324:406fd2029f23	1548	* Register is updated to be 'Error Active' and both error counters are reset to zero.
mbed_official	324:406fd2029f23	1549	* At any instance of dominant bit following a stream of less than 11
mbed_official	324:406fd2029f23	1550	* consecutive recessive bits, the internal counter resets itself to zero without affecting
mbed_official	324:406fd2029f23	1551	* the TXERRCNT value. If during system start-up, only one node is operating,
mbed_official	324:406fd2029f23	1552	* then its TXERRCNT increases in each message it is trying to transmit, as a
mbed_official	324:406fd2029f23	1553	* result of acknowledge errors (indicated by the ACKERR bit in the Error and Status
mbed_official	324:406fd2029f23	1554	* Register). After the transition to 'Error Passive' state, the TXERRCNT does not
mbed_official	324:406fd2029f23	1555	* increment anymore by acknowledge errors. Therefore the device never goes to
mbed_official	324:406fd2029f23	1556	* the 'Bus Off' state. If the RXERRCNT increases to a value greater than 127, it
mbed_official	324:406fd2029f23	1557	* is not incremented further, even if more errors are detected while being a
mbed_official	324:406fd2029f23	1558	* receiver. At the next successful message reception, the counter is set to a value
mbed_official	324:406fd2029f23	1559	* between 119 and 127 to resume to 'Error Active' state.
mbed_official	324:406fd2029f23	1560	*/
mbed_official	324:406fd2029f23	1561	typedef union _hw_can_ecr
mbed_official	324:406fd2029f23	1562	{
mbed_official	324:406fd2029f23	1563	uint32_t U;
mbed_official	324:406fd2029f23	1564	struct _hw_can_ecr_bitfields
mbed_official	324:406fd2029f23	1565	{
mbed_official	324:406fd2029f23	1566	uint32_t TXERRCNT : 8; /!< [7:0] Transmit Error Counter /
mbed_official	324:406fd2029f23	1567	uint32_t RXERRCNT : 8; /!< [15:8] Receive Error Counter /
mbed_official	324:406fd2029f23	1568	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	1569	} B;
mbed_official	324:406fd2029f23	1570	} hw_can_ecr_t;
mbed_official	324:406fd2029f23	1571
mbed_official	324:406fd2029f23	1572	/*!
mbed_official	324:406fd2029f23	1573	* @name Constants and macros for entire CAN_ECR register
mbed_official	324:406fd2029f23	1574	*/
mbed_official	324:406fd2029f23	1575	/@{/
mbed_official	324:406fd2029f23	1576	#define HW_CAN_ECR_ADDR(x) ((x) + 0x1CU)
mbed_official	324:406fd2029f23	1577
mbed_official	324:406fd2029f23	1578	#define HW_CAN_ECR(x) ((__IO hw_can_ecr_t ) HW_CAN_ECR_ADDR(x))
mbed_official	324:406fd2029f23	1579	#define HW_CAN_ECR_RD(x) (HW_CAN_ECR(x).U)
mbed_official	324:406fd2029f23	1580	#define HW_CAN_ECR_WR(x, v) (HW_CAN_ECR(x).U = (v))
mbed_official	324:406fd2029f23	1581	#define HW_CAN_ECR_SET(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1582	#define HW_CAN_ECR_CLR(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1583	#define HW_CAN_ECR_TOG(x, v) (HW_CAN_ECR_WR(x, HW_CAN_ECR_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1584	/@}/
mbed_official	324:406fd2029f23	1585
mbed_official	324:406fd2029f23	1586	/*
mbed_official	324:406fd2029f23	1587	* Constants & macros for individual CAN_ECR bitfields
mbed_official	324:406fd2029f23	1588	*/
mbed_official	324:406fd2029f23	1589
mbed_official	324:406fd2029f23	1590	/*!
mbed_official	324:406fd2029f23	1591	* @name Register CAN_ECR, field TXERRCNT[7:0] (RW)
mbed_official	324:406fd2029f23	1592	*/
mbed_official	324:406fd2029f23	1593	/@{/
mbed_official	324:406fd2029f23	1594	#define BP_CAN_ECR_TXERRCNT (0U) /!< Bit position for CAN_ECR_TXERRCNT. /
mbed_official	324:406fd2029f23	1595	#define BM_CAN_ECR_TXERRCNT (0x000000FFU) /!< Bit mask for CAN_ECR_TXERRCNT. /
mbed_official	324:406fd2029f23	1596	#define BS_CAN_ECR_TXERRCNT (8U) /!< Bit field size in bits for CAN_ECR_TXERRCNT. /
mbed_official	324:406fd2029f23	1597
mbed_official	324:406fd2029f23	1598	/! @brief Read current value of the CAN_ECR_TXERRCNT field. /
mbed_official	324:406fd2029f23	1599	#define BR_CAN_ECR_TXERRCNT(x) (HW_CAN_ECR(x).B.TXERRCNT)
mbed_official	324:406fd2029f23	1600
mbed_official	324:406fd2029f23	1601	/! @brief Format value for bitfield CAN_ECR_TXERRCNT. /
mbed_official	324:406fd2029f23	1602	#define BF_CAN_ECR_TXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_TXERRCNT) & BM_CAN_ECR_TXERRCNT)
mbed_official	324:406fd2029f23	1603
mbed_official	324:406fd2029f23	1604	/! @brief Set the TXERRCNT field to a new value. /
mbed_official	324:406fd2029f23	1605	#define BW_CAN_ECR_TXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_TXERRCNT) \| BF_CAN_ECR_TXERRCNT(v)))
mbed_official	324:406fd2029f23	1606	/@}/
mbed_official	324:406fd2029f23	1607
mbed_official	324:406fd2029f23	1608	/*!
mbed_official	324:406fd2029f23	1609	* @name Register CAN_ECR, field RXERRCNT[15:8] (RW)
mbed_official	324:406fd2029f23	1610	*/
mbed_official	324:406fd2029f23	1611	/@{/
mbed_official	324:406fd2029f23	1612	#define BP_CAN_ECR_RXERRCNT (8U) /!< Bit position for CAN_ECR_RXERRCNT. /
mbed_official	324:406fd2029f23	1613	#define BM_CAN_ECR_RXERRCNT (0x0000FF00U) /!< Bit mask for CAN_ECR_RXERRCNT. /
mbed_official	324:406fd2029f23	1614	#define BS_CAN_ECR_RXERRCNT (8U) /!< Bit field size in bits for CAN_ECR_RXERRCNT. /
mbed_official	324:406fd2029f23	1615
mbed_official	324:406fd2029f23	1616	/! @brief Read current value of the CAN_ECR_RXERRCNT field. /
mbed_official	324:406fd2029f23	1617	#define BR_CAN_ECR_RXERRCNT(x) (HW_CAN_ECR(x).B.RXERRCNT)
mbed_official	324:406fd2029f23	1618
mbed_official	324:406fd2029f23	1619	/! @brief Format value for bitfield CAN_ECR_RXERRCNT. /
mbed_official	324:406fd2029f23	1620	#define BF_CAN_ECR_RXERRCNT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ECR_RXERRCNT) & BM_CAN_ECR_RXERRCNT)
mbed_official	324:406fd2029f23	1621
mbed_official	324:406fd2029f23	1622	/! @brief Set the RXERRCNT field to a new value. /
mbed_official	324:406fd2029f23	1623	#define BW_CAN_ECR_RXERRCNT(x, v) (HW_CAN_ECR_WR(x, (HW_CAN_ECR_RD(x) & ~BM_CAN_ECR_RXERRCNT) \| BF_CAN_ECR_RXERRCNT(v)))
mbed_official	324:406fd2029f23	1624	/@}/
mbed_official	324:406fd2029f23	1625
mbed_official	324:406fd2029f23	1626	/*******************************************************************************
mbed_official	324:406fd2029f23	1627	* HW_CAN_ESR1 - Error and Status 1 register
mbed_official	324:406fd2029f23	1628	******************************************************************************/
mbed_official	324:406fd2029f23	1629
mbed_official	324:406fd2029f23	1630	/*!
mbed_official	324:406fd2029f23	1631	* @brief HW_CAN_ESR1 - Error and Status 1 register (RW)
mbed_official	324:406fd2029f23	1632	*
mbed_official	324:406fd2029f23	1633	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1634	*
mbed_official	324:406fd2029f23	1635	* This register reflects various error conditions, some general status of the
mbed_official	324:406fd2029f23	1636	* device and it is the source of interrupts to the CPU. The CPU read action
mbed_official	324:406fd2029f23	1637	* clears bits 15-10. Therefore the reported error conditions (bits 15-10) are those
mbed_official	324:406fd2029f23	1638	* that occurred since the last time the CPU read this register. Bits 9-3 are
mbed_official	324:406fd2029f23	1639	* status bits. The following table shows the FlexCAN state variables and their
mbed_official	324:406fd2029f23	1640	* meanings. Other combinations not shown in the table are reserved. SYNCH IDLE TX RX
mbed_official	324:406fd2029f23	1641	* FlexCAN State 0 0 0 0 Not synchronized to CAN bus 1 1 x x Idle 1 0 1 0
mbed_official	324:406fd2029f23	1642	* Transmitting 1 0 0 1 Receiving
mbed_official	324:406fd2029f23	1643	*/
mbed_official	324:406fd2029f23	1644	typedef union _hw_can_esr1
mbed_official	324:406fd2029f23	1645	{
mbed_official	324:406fd2029f23	1646	uint32_t U;
mbed_official	324:406fd2029f23	1647	struct _hw_can_esr1_bitfields
mbed_official	324:406fd2029f23	1648	{
mbed_official	324:406fd2029f23	1649	uint32_t WAKINT : 1; /!< [0] Wake-Up Interrupt /
mbed_official	324:406fd2029f23	1650	uint32_t ERRINT : 1; /!< [1] Error Interrupt /
mbed_official	324:406fd2029f23	1651	uint32_t BOFFINT : 1; /!< [2] Bus Off Interrupt /
mbed_official	324:406fd2029f23	1652	uint32_t RX : 1; /!< [3] FlexCAN In Reception /
mbed_official	324:406fd2029f23	1653	uint32_t FLTCONF : 2; /!< [5:4] Fault Confinement State /
mbed_official	324:406fd2029f23	1654	uint32_t TX : 1; /!< [6] FlexCAN In Transmission /
mbed_official	324:406fd2029f23	1655	uint32_t IDLE : 1; /!< [7] /
mbed_official	324:406fd2029f23	1656	uint32_t RXWRN : 1; /!< [8] Rx Error Warning /
mbed_official	324:406fd2029f23	1657	uint32_t TXWRN : 1; /!< [9] TX Error Warning /
mbed_official	324:406fd2029f23	1658	uint32_t STFERR : 1; /!< [10] Stuffing Error /
mbed_official	324:406fd2029f23	1659	uint32_t FRMERR : 1; /!< [11] Form Error /
mbed_official	324:406fd2029f23	1660	uint32_t CRCERR : 1; /!< [12] Cyclic Redundancy Check Error /
mbed_official	324:406fd2029f23	1661	uint32_t ACKERR : 1; /!< [13] Acknowledge Error /
mbed_official	324:406fd2029f23	1662	uint32_t BIT0ERR : 1; /!< [14] Bit0 Error /
mbed_official	324:406fd2029f23	1663	uint32_t BIT1ERR : 1; /!< [15] Bit1 Error /
mbed_official	324:406fd2029f23	1664	uint32_t RWRNINT : 1; /!< [16] Rx Warning Interrupt Flag /
mbed_official	324:406fd2029f23	1665	uint32_t TWRNINT : 1; /!< [17] Tx Warning Interrupt Flag /
mbed_official	324:406fd2029f23	1666	uint32_t SYNCH : 1; /!< [18] CAN Synchronization Status /
mbed_official	324:406fd2029f23	1667	uint32_t RESERVED0 : 13; /!< [31:19] /
mbed_official	324:406fd2029f23	1668	} B;
mbed_official	324:406fd2029f23	1669	} hw_can_esr1_t;
mbed_official	324:406fd2029f23	1670
mbed_official	324:406fd2029f23	1671	/*!
mbed_official	324:406fd2029f23	1672	* @name Constants and macros for entire CAN_ESR1 register
mbed_official	324:406fd2029f23	1673	*/
mbed_official	324:406fd2029f23	1674	/@{/
mbed_official	324:406fd2029f23	1675	#define HW_CAN_ESR1_ADDR(x) ((x) + 0x20U)
mbed_official	324:406fd2029f23	1676
mbed_official	324:406fd2029f23	1677	#define HW_CAN_ESR1(x) ((__IO hw_can_esr1_t ) HW_CAN_ESR1_ADDR(x))
mbed_official	324:406fd2029f23	1678	#define HW_CAN_ESR1_RD(x) (HW_CAN_ESR1(x).U)
mbed_official	324:406fd2029f23	1679	#define HW_CAN_ESR1_WR(x, v) (HW_CAN_ESR1(x).U = (v))
mbed_official	324:406fd2029f23	1680	#define HW_CAN_ESR1_SET(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1681	#define HW_CAN_ESR1_CLR(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1682	#define HW_CAN_ESR1_TOG(x, v) (HW_CAN_ESR1_WR(x, HW_CAN_ESR1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1683	/@}/
mbed_official	324:406fd2029f23	1684
mbed_official	324:406fd2029f23	1685	/*
mbed_official	324:406fd2029f23	1686	* Constants & macros for individual CAN_ESR1 bitfields
mbed_official	324:406fd2029f23	1687	*/
mbed_official	324:406fd2029f23	1688
mbed_official	324:406fd2029f23	1689	/*!
mbed_official	324:406fd2029f23	1690	* @name Register CAN_ESR1, field WAKINT[0] (W1C)
mbed_official	324:406fd2029f23	1691	*
mbed_official	324:406fd2029f23	1692	* This field applies when FlexCAN is in low-power mode under Self Wake Up
mbed_official	324:406fd2029f23	1693	* mechanism: Stop mode When a recessive-to-dominant transition is detected on the CAN
mbed_official	324:406fd2029f23	1694	* bus and if the MCR[WAKMSK] bit is set, an interrupt is generated to the CPU.
mbed_official	324:406fd2029f23	1695	* This bit is cleared by writing it to 1. When MCR[SLFWAK] is negated, this flag
mbed_official	324:406fd2029f23	1696	* is masked. The CPU must clear this flag before disabling the bit. Otherwise
mbed_official	324:406fd2029f23	1697	* it will be set when the SLFWAK is set again. Writing 0 has no effect.
mbed_official	324:406fd2029f23	1698	*
mbed_official	324:406fd2029f23	1699	* Values:
mbed_official	324:406fd2029f23	1700	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1701	* - 1 - Indicates a recessive to dominant transition was received on the CAN
mbed_official	324:406fd2029f23	1702	* bus.
mbed_official	324:406fd2029f23	1703	*/
mbed_official	324:406fd2029f23	1704	/@{/
mbed_official	324:406fd2029f23	1705	#define BP_CAN_ESR1_WAKINT (0U) /!< Bit position for CAN_ESR1_WAKINT. /
mbed_official	324:406fd2029f23	1706	#define BM_CAN_ESR1_WAKINT (0x00000001U) /!< Bit mask for CAN_ESR1_WAKINT. /
mbed_official	324:406fd2029f23	1707	#define BS_CAN_ESR1_WAKINT (1U) /!< Bit field size in bits for CAN_ESR1_WAKINT. /
mbed_official	324:406fd2029f23	1708
mbed_official	324:406fd2029f23	1709	/! @brief Read current value of the CAN_ESR1_WAKINT field. /
mbed_official	324:406fd2029f23	1710	#define BR_CAN_ESR1_WAKINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT))
mbed_official	324:406fd2029f23	1711
mbed_official	324:406fd2029f23	1712	/! @brief Format value for bitfield CAN_ESR1_WAKINT. /
mbed_official	324:406fd2029f23	1713	#define BF_CAN_ESR1_WAKINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_WAKINT) & BM_CAN_ESR1_WAKINT)
mbed_official	324:406fd2029f23	1714
mbed_official	324:406fd2029f23	1715	/! @brief Set the WAKINT field to a new value. /
mbed_official	324:406fd2029f23	1716	#define BW_CAN_ESR1_WAKINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_WAKINT) = (v))
mbed_official	324:406fd2029f23	1717	/@}/
mbed_official	324:406fd2029f23	1718
mbed_official	324:406fd2029f23	1719	/*!
mbed_official	324:406fd2029f23	1720	* @name Register CAN_ESR1, field ERRINT[1] (W1C)
mbed_official	324:406fd2029f23	1721	*
mbed_official	324:406fd2029f23	1722	* This bit indicates that at least one of the Error Bits (bits 15-10) is set.
mbed_official	324:406fd2029f23	1723	* If the corresponding mask bit CTRL1[ERRMSK] is set, an interrupt is generated
mbed_official	324:406fd2029f23	1724	* to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
mbed_official	324:406fd2029f23	1725	*
mbed_official	324:406fd2029f23	1726	* Values:
mbed_official	324:406fd2029f23	1727	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1728	* - 1 - Indicates setting of any Error Bit in the Error and Status Register.
mbed_official	324:406fd2029f23	1729	*/
mbed_official	324:406fd2029f23	1730	/@{/
mbed_official	324:406fd2029f23	1731	#define BP_CAN_ESR1_ERRINT (1U) /!< Bit position for CAN_ESR1_ERRINT. /
mbed_official	324:406fd2029f23	1732	#define BM_CAN_ESR1_ERRINT (0x00000002U) /!< Bit mask for CAN_ESR1_ERRINT. /
mbed_official	324:406fd2029f23	1733	#define BS_CAN_ESR1_ERRINT (1U) /!< Bit field size in bits for CAN_ESR1_ERRINT. /
mbed_official	324:406fd2029f23	1734
mbed_official	324:406fd2029f23	1735	/! @brief Read current value of the CAN_ESR1_ERRINT field. /
mbed_official	324:406fd2029f23	1736	#define BR_CAN_ESR1_ERRINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT))
mbed_official	324:406fd2029f23	1737
mbed_official	324:406fd2029f23	1738	/! @brief Format value for bitfield CAN_ESR1_ERRINT. /
mbed_official	324:406fd2029f23	1739	#define BF_CAN_ESR1_ERRINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_ERRINT) & BM_CAN_ESR1_ERRINT)
mbed_official	324:406fd2029f23	1740
mbed_official	324:406fd2029f23	1741	/! @brief Set the ERRINT field to a new value. /
mbed_official	324:406fd2029f23	1742	#define BW_CAN_ESR1_ERRINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ERRINT) = (v))
mbed_official	324:406fd2029f23	1743	/@}/
mbed_official	324:406fd2029f23	1744
mbed_official	324:406fd2029f23	1745	/*!
mbed_official	324:406fd2029f23	1746	* @name Register CAN_ESR1, field BOFFINT[2] (W1C)
mbed_official	324:406fd2029f23	1747	*
mbed_official	324:406fd2029f23	1748	* This bit is set when FlexCAN enters 'Bus Off' state. If the corresponding
mbed_official	324:406fd2029f23	1749	* mask bit in the Control Register (BOFFMSK) is set, an interrupt is generated to
mbed_official	324:406fd2029f23	1750	* the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
mbed_official	324:406fd2029f23	1751	*
mbed_official	324:406fd2029f23	1752	* Values:
mbed_official	324:406fd2029f23	1753	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1754	* - 1 - FlexCAN module entered Bus Off state.
mbed_official	324:406fd2029f23	1755	*/
mbed_official	324:406fd2029f23	1756	/@{/
mbed_official	324:406fd2029f23	1757	#define BP_CAN_ESR1_BOFFINT (2U) /!< Bit position for CAN_ESR1_BOFFINT. /
mbed_official	324:406fd2029f23	1758	#define BM_CAN_ESR1_BOFFINT (0x00000004U) /!< Bit mask for CAN_ESR1_BOFFINT. /
mbed_official	324:406fd2029f23	1759	#define BS_CAN_ESR1_BOFFINT (1U) /!< Bit field size in bits for CAN_ESR1_BOFFINT. /
mbed_official	324:406fd2029f23	1760
mbed_official	324:406fd2029f23	1761	/! @brief Read current value of the CAN_ESR1_BOFFINT field. /
mbed_official	324:406fd2029f23	1762	#define BR_CAN_ESR1_BOFFINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT))
mbed_official	324:406fd2029f23	1763
mbed_official	324:406fd2029f23	1764	/! @brief Format value for bitfield CAN_ESR1_BOFFINT. /
mbed_official	324:406fd2029f23	1765	#define BF_CAN_ESR1_BOFFINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_BOFFINT) & BM_CAN_ESR1_BOFFINT)
mbed_official	324:406fd2029f23	1766
mbed_official	324:406fd2029f23	1767	/! @brief Set the BOFFINT field to a new value. /
mbed_official	324:406fd2029f23	1768	#define BW_CAN_ESR1_BOFFINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BOFFINT) = (v))
mbed_official	324:406fd2029f23	1769	/@}/
mbed_official	324:406fd2029f23	1770
mbed_official	324:406fd2029f23	1771	/*!
mbed_official	324:406fd2029f23	1772	* @name Register CAN_ESR1, field RX[3] (RO)
mbed_official	324:406fd2029f23	1773	*
mbed_official	324:406fd2029f23	1774	* This bit indicates if FlexCAN is receiving a message. See the table in the
mbed_official	324:406fd2029f23	1775	* overall CAN_ESR1 register description.
mbed_official	324:406fd2029f23	1776	*
mbed_official	324:406fd2029f23	1777	* Values:
mbed_official	324:406fd2029f23	1778	* - 0 - FlexCAN is not receiving a message.
mbed_official	324:406fd2029f23	1779	* - 1 - FlexCAN is receiving a message.
mbed_official	324:406fd2029f23	1780	*/
mbed_official	324:406fd2029f23	1781	/@{/
mbed_official	324:406fd2029f23	1782	#define BP_CAN_ESR1_RX (3U) /!< Bit position for CAN_ESR1_RX. /
mbed_official	324:406fd2029f23	1783	#define BM_CAN_ESR1_RX (0x00000008U) /!< Bit mask for CAN_ESR1_RX. /
mbed_official	324:406fd2029f23	1784	#define BS_CAN_ESR1_RX (1U) /!< Bit field size in bits for CAN_ESR1_RX. /
mbed_official	324:406fd2029f23	1785
mbed_official	324:406fd2029f23	1786	/! @brief Read current value of the CAN_ESR1_RX field. /
mbed_official	324:406fd2029f23	1787	#define BR_CAN_ESR1_RX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RX))
mbed_official	324:406fd2029f23	1788	/@}/
mbed_official	324:406fd2029f23	1789
mbed_official	324:406fd2029f23	1790	/*!
mbed_official	324:406fd2029f23	1791	* @name Register CAN_ESR1, field FLTCONF[5:4] (RO)
mbed_official	324:406fd2029f23	1792	*
mbed_official	324:406fd2029f23	1793	* This 2-bit field indicates the Confinement State of the FlexCAN module. If
mbed_official	324:406fd2029f23	1794	* the LOM bit in the Control Register is asserted, after some delay that depends
mbed_official	324:406fd2029f23	1795	* on the CAN bit timing the FLTCONF field will indicate "Error Passive". The very
mbed_official	324:406fd2029f23	1796	* same delay affects the way how FLTCONF reflects an update to ECR register by
mbed_official	324:406fd2029f23	1797	* the CPU. It may be necessary up to one CAN bit time to get them coherent
mbed_official	324:406fd2029f23	1798	* again. Because the Control Register is not affected by soft reset, the FLTCONF
mbed_official	324:406fd2029f23	1799	* field will not be affected by soft reset if the LOM bit is asserted.
mbed_official	324:406fd2029f23	1800	*
mbed_official	324:406fd2029f23	1801	* Values:
mbed_official	324:406fd2029f23	1802	* - 00 - Error Active
mbed_official	324:406fd2029f23	1803	* - 01 - Error Passive
mbed_official	324:406fd2029f23	1804	* - 1x - Bus Off
mbed_official	324:406fd2029f23	1805	*/
mbed_official	324:406fd2029f23	1806	/@{/
mbed_official	324:406fd2029f23	1807	#define BP_CAN_ESR1_FLTCONF (4U) /!< Bit position for CAN_ESR1_FLTCONF. /
mbed_official	324:406fd2029f23	1808	#define BM_CAN_ESR1_FLTCONF (0x00000030U) /!< Bit mask for CAN_ESR1_FLTCONF. /
mbed_official	324:406fd2029f23	1809	#define BS_CAN_ESR1_FLTCONF (2U) /!< Bit field size in bits for CAN_ESR1_FLTCONF. /
mbed_official	324:406fd2029f23	1810
mbed_official	324:406fd2029f23	1811	/! @brief Read current value of the CAN_ESR1_FLTCONF field. /
mbed_official	324:406fd2029f23	1812	#define BR_CAN_ESR1_FLTCONF(x) (HW_CAN_ESR1(x).B.FLTCONF)
mbed_official	324:406fd2029f23	1813	/@}/
mbed_official	324:406fd2029f23	1814
mbed_official	324:406fd2029f23	1815	/*!
mbed_official	324:406fd2029f23	1816	* @name Register CAN_ESR1, field TX[6] (RO)
mbed_official	324:406fd2029f23	1817	*
mbed_official	324:406fd2029f23	1818	* This bit indicates if FlexCAN is transmitting a message. See the table in the
mbed_official	324:406fd2029f23	1819	* overall CAN_ESR1 register description.
mbed_official	324:406fd2029f23	1820	*
mbed_official	324:406fd2029f23	1821	* Values:
mbed_official	324:406fd2029f23	1822	* - 0 - FlexCAN is not transmitting a message.
mbed_official	324:406fd2029f23	1823	* - 1 - FlexCAN is transmitting a message.
mbed_official	324:406fd2029f23	1824	*/
mbed_official	324:406fd2029f23	1825	/@{/
mbed_official	324:406fd2029f23	1826	#define BP_CAN_ESR1_TX (6U) /!< Bit position for CAN_ESR1_TX. /
mbed_official	324:406fd2029f23	1827	#define BM_CAN_ESR1_TX (0x00000040U) /!< Bit mask for CAN_ESR1_TX. /
mbed_official	324:406fd2029f23	1828	#define BS_CAN_ESR1_TX (1U) /!< Bit field size in bits for CAN_ESR1_TX. /
mbed_official	324:406fd2029f23	1829
mbed_official	324:406fd2029f23	1830	/! @brief Read current value of the CAN_ESR1_TX field. /
mbed_official	324:406fd2029f23	1831	#define BR_CAN_ESR1_TX(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TX))
mbed_official	324:406fd2029f23	1832	/@}/
mbed_official	324:406fd2029f23	1833
mbed_official	324:406fd2029f23	1834	/*!
mbed_official	324:406fd2029f23	1835	* @name Register CAN_ESR1, field IDLE[7] (RO)
mbed_official	324:406fd2029f23	1836	*
mbed_official	324:406fd2029f23	1837	* This bit indicates when CAN bus is in IDLE state. See the table in the
mbed_official	324:406fd2029f23	1838	* overall CAN_ESR1 register description.
mbed_official	324:406fd2029f23	1839	*
mbed_official	324:406fd2029f23	1840	* Values:
mbed_official	324:406fd2029f23	1841	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1842	* - 1 - CAN bus is now IDLE.
mbed_official	324:406fd2029f23	1843	*/
mbed_official	324:406fd2029f23	1844	/@{/
mbed_official	324:406fd2029f23	1845	#define BP_CAN_ESR1_IDLE (7U) /!< Bit position for CAN_ESR1_IDLE. /
mbed_official	324:406fd2029f23	1846	#define BM_CAN_ESR1_IDLE (0x00000080U) /!< Bit mask for CAN_ESR1_IDLE. /
mbed_official	324:406fd2029f23	1847	#define BS_CAN_ESR1_IDLE (1U) /!< Bit field size in bits for CAN_ESR1_IDLE. /
mbed_official	324:406fd2029f23	1848
mbed_official	324:406fd2029f23	1849	/! @brief Read current value of the CAN_ESR1_IDLE field. /
mbed_official	324:406fd2029f23	1850	#define BR_CAN_ESR1_IDLE(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_IDLE))
mbed_official	324:406fd2029f23	1851	/@}/
mbed_official	324:406fd2029f23	1852
mbed_official	324:406fd2029f23	1853	/*!
mbed_official	324:406fd2029f23	1854	* @name Register CAN_ESR1, field RXWRN[8] (RO)
mbed_official	324:406fd2029f23	1855	*
mbed_official	324:406fd2029f23	1856	* This bit indicates when repetitive errors are occurring during message
mbed_official	324:406fd2029f23	1857	* reception. This bit is not updated during Freeze mode.
mbed_official	324:406fd2029f23	1858	*
mbed_official	324:406fd2029f23	1859	* Values:
mbed_official	324:406fd2029f23	1860	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1861	* - 1 - RXERRCNT is greater than or equal to 96.
mbed_official	324:406fd2029f23	1862	*/
mbed_official	324:406fd2029f23	1863	/@{/
mbed_official	324:406fd2029f23	1864	#define BP_CAN_ESR1_RXWRN (8U) /!< Bit position for CAN_ESR1_RXWRN. /
mbed_official	324:406fd2029f23	1865	#define BM_CAN_ESR1_RXWRN (0x00000100U) /!< Bit mask for CAN_ESR1_RXWRN. /
mbed_official	324:406fd2029f23	1866	#define BS_CAN_ESR1_RXWRN (1U) /!< Bit field size in bits for CAN_ESR1_RXWRN. /
mbed_official	324:406fd2029f23	1867
mbed_official	324:406fd2029f23	1868	/! @brief Read current value of the CAN_ESR1_RXWRN field. /
mbed_official	324:406fd2029f23	1869	#define BR_CAN_ESR1_RXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RXWRN))
mbed_official	324:406fd2029f23	1870	/@}/
mbed_official	324:406fd2029f23	1871
mbed_official	324:406fd2029f23	1872	/*!
mbed_official	324:406fd2029f23	1873	* @name Register CAN_ESR1, field TXWRN[9] (RO)
mbed_official	324:406fd2029f23	1874	*
mbed_official	324:406fd2029f23	1875	* This bit indicates when repetitive errors are occurring during message
mbed_official	324:406fd2029f23	1876	* transmission. This bit is not updated during Freeze mode.
mbed_official	324:406fd2029f23	1877	*
mbed_official	324:406fd2029f23	1878	* Values:
mbed_official	324:406fd2029f23	1879	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1880	* - 1 - TXERRCNT is greater than or equal to 96.
mbed_official	324:406fd2029f23	1881	*/
mbed_official	324:406fd2029f23	1882	/@{/
mbed_official	324:406fd2029f23	1883	#define BP_CAN_ESR1_TXWRN (9U) /!< Bit position for CAN_ESR1_TXWRN. /
mbed_official	324:406fd2029f23	1884	#define BM_CAN_ESR1_TXWRN (0x00000200U) /!< Bit mask for CAN_ESR1_TXWRN. /
mbed_official	324:406fd2029f23	1885	#define BS_CAN_ESR1_TXWRN (1U) /!< Bit field size in bits for CAN_ESR1_TXWRN. /
mbed_official	324:406fd2029f23	1886
mbed_official	324:406fd2029f23	1887	/! @brief Read current value of the CAN_ESR1_TXWRN field. /
mbed_official	324:406fd2029f23	1888	#define BR_CAN_ESR1_TXWRN(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TXWRN))
mbed_official	324:406fd2029f23	1889	/@}/
mbed_official	324:406fd2029f23	1890
mbed_official	324:406fd2029f23	1891	/*!
mbed_official	324:406fd2029f23	1892	* @name Register CAN_ESR1, field STFERR[10] (RO)
mbed_official	324:406fd2029f23	1893	*
mbed_official	324:406fd2029f23	1894	* This bit indicates that a Stuffing Error has been etected.
mbed_official	324:406fd2029f23	1895	*
mbed_official	324:406fd2029f23	1896	* Values:
mbed_official	324:406fd2029f23	1897	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1898	* - 1 - A Stuffing Error occurred since last read of this register.
mbed_official	324:406fd2029f23	1899	*/
mbed_official	324:406fd2029f23	1900	/@{/
mbed_official	324:406fd2029f23	1901	#define BP_CAN_ESR1_STFERR (10U) /!< Bit position for CAN_ESR1_STFERR. /
mbed_official	324:406fd2029f23	1902	#define BM_CAN_ESR1_STFERR (0x00000400U) /!< Bit mask for CAN_ESR1_STFERR. /
mbed_official	324:406fd2029f23	1903	#define BS_CAN_ESR1_STFERR (1U) /!< Bit field size in bits for CAN_ESR1_STFERR. /
mbed_official	324:406fd2029f23	1904
mbed_official	324:406fd2029f23	1905	/! @brief Read current value of the CAN_ESR1_STFERR field. /
mbed_official	324:406fd2029f23	1906	#define BR_CAN_ESR1_STFERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_STFERR))
mbed_official	324:406fd2029f23	1907	/@}/
mbed_official	324:406fd2029f23	1908
mbed_official	324:406fd2029f23	1909	/*!
mbed_official	324:406fd2029f23	1910	* @name Register CAN_ESR1, field FRMERR[11] (RO)
mbed_official	324:406fd2029f23	1911	*
mbed_official	324:406fd2029f23	1912	* This bit indicates that a Form Error has been detected by the receiver node,
mbed_official	324:406fd2029f23	1913	* that is, a fixed-form bit field contains at least one illegal bit.
mbed_official	324:406fd2029f23	1914	*
mbed_official	324:406fd2029f23	1915	* Values:
mbed_official	324:406fd2029f23	1916	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1917	* - 1 - A Form Error occurred since last read of this register.
mbed_official	324:406fd2029f23	1918	*/
mbed_official	324:406fd2029f23	1919	/@{/
mbed_official	324:406fd2029f23	1920	#define BP_CAN_ESR1_FRMERR (11U) /!< Bit position for CAN_ESR1_FRMERR. /
mbed_official	324:406fd2029f23	1921	#define BM_CAN_ESR1_FRMERR (0x00000800U) /!< Bit mask for CAN_ESR1_FRMERR. /
mbed_official	324:406fd2029f23	1922	#define BS_CAN_ESR1_FRMERR (1U) /!< Bit field size in bits for CAN_ESR1_FRMERR. /
mbed_official	324:406fd2029f23	1923
mbed_official	324:406fd2029f23	1924	/! @brief Read current value of the CAN_ESR1_FRMERR field. /
mbed_official	324:406fd2029f23	1925	#define BR_CAN_ESR1_FRMERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_FRMERR))
mbed_official	324:406fd2029f23	1926	/@}/
mbed_official	324:406fd2029f23	1927
mbed_official	324:406fd2029f23	1928	/*!
mbed_official	324:406fd2029f23	1929	* @name Register CAN_ESR1, field CRCERR[12] (RO)
mbed_official	324:406fd2029f23	1930	*
mbed_official	324:406fd2029f23	1931	* This bit indicates that a CRC Error has been detected by the receiver node,
mbed_official	324:406fd2029f23	1932	* that is, the calculated CRC is different from the received.
mbed_official	324:406fd2029f23	1933	*
mbed_official	324:406fd2029f23	1934	* Values:
mbed_official	324:406fd2029f23	1935	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1936	* - 1 - A CRC error occurred since last read of this register.
mbed_official	324:406fd2029f23	1937	*/
mbed_official	324:406fd2029f23	1938	/@{/
mbed_official	324:406fd2029f23	1939	#define BP_CAN_ESR1_CRCERR (12U) /!< Bit position for CAN_ESR1_CRCERR. /
mbed_official	324:406fd2029f23	1940	#define BM_CAN_ESR1_CRCERR (0x00001000U) /!< Bit mask for CAN_ESR1_CRCERR. /
mbed_official	324:406fd2029f23	1941	#define BS_CAN_ESR1_CRCERR (1U) /!< Bit field size in bits for CAN_ESR1_CRCERR. /
mbed_official	324:406fd2029f23	1942
mbed_official	324:406fd2029f23	1943	/! @brief Read current value of the CAN_ESR1_CRCERR field. /
mbed_official	324:406fd2029f23	1944	#define BR_CAN_ESR1_CRCERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_CRCERR))
mbed_official	324:406fd2029f23	1945	/@}/
mbed_official	324:406fd2029f23	1946
mbed_official	324:406fd2029f23	1947	/*!
mbed_official	324:406fd2029f23	1948	* @name Register CAN_ESR1, field ACKERR[13] (RO)
mbed_official	324:406fd2029f23	1949	*
mbed_official	324:406fd2029f23	1950	* This bit indicates that an Acknowledge Error has been detected by the
mbed_official	324:406fd2029f23	1951	* transmitter node, that is, a dominant bit has not been detected during the ACK SLOT.
mbed_official	324:406fd2029f23	1952	*
mbed_official	324:406fd2029f23	1953	* Values:
mbed_official	324:406fd2029f23	1954	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1955	* - 1 - An ACK error occurred since last read of this register.
mbed_official	324:406fd2029f23	1956	*/
mbed_official	324:406fd2029f23	1957	/@{/
mbed_official	324:406fd2029f23	1958	#define BP_CAN_ESR1_ACKERR (13U) /!< Bit position for CAN_ESR1_ACKERR. /
mbed_official	324:406fd2029f23	1959	#define BM_CAN_ESR1_ACKERR (0x00002000U) /!< Bit mask for CAN_ESR1_ACKERR. /
mbed_official	324:406fd2029f23	1960	#define BS_CAN_ESR1_ACKERR (1U) /!< Bit field size in bits for CAN_ESR1_ACKERR. /
mbed_official	324:406fd2029f23	1961
mbed_official	324:406fd2029f23	1962	/! @brief Read current value of the CAN_ESR1_ACKERR field. /
mbed_official	324:406fd2029f23	1963	#define BR_CAN_ESR1_ACKERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_ACKERR))
mbed_official	324:406fd2029f23	1964	/@}/
mbed_official	324:406fd2029f23	1965
mbed_official	324:406fd2029f23	1966	/*!
mbed_official	324:406fd2029f23	1967	* @name Register CAN_ESR1, field BIT0ERR[14] (RO)
mbed_official	324:406fd2029f23	1968	*
mbed_official	324:406fd2029f23	1969	* This bit indicates when an inconsistency occurs between the transmitted and
mbed_official	324:406fd2029f23	1970	* the received bit in a message.
mbed_official	324:406fd2029f23	1971	*
mbed_official	324:406fd2029f23	1972	* Values:
mbed_official	324:406fd2029f23	1973	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1974	* - 1 - At least one bit sent as dominant is received as recessive.
mbed_official	324:406fd2029f23	1975	*/
mbed_official	324:406fd2029f23	1976	/@{/
mbed_official	324:406fd2029f23	1977	#define BP_CAN_ESR1_BIT0ERR (14U) /!< Bit position for CAN_ESR1_BIT0ERR. /
mbed_official	324:406fd2029f23	1978	#define BM_CAN_ESR1_BIT0ERR (0x00004000U) /!< Bit mask for CAN_ESR1_BIT0ERR. /
mbed_official	324:406fd2029f23	1979	#define BS_CAN_ESR1_BIT0ERR (1U) /!< Bit field size in bits for CAN_ESR1_BIT0ERR. /
mbed_official	324:406fd2029f23	1980
mbed_official	324:406fd2029f23	1981	/! @brief Read current value of the CAN_ESR1_BIT0ERR field. /
mbed_official	324:406fd2029f23	1982	#define BR_CAN_ESR1_BIT0ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT0ERR))
mbed_official	324:406fd2029f23	1983	/@}/
mbed_official	324:406fd2029f23	1984
mbed_official	324:406fd2029f23	1985	/*!
mbed_official	324:406fd2029f23	1986	* @name Register CAN_ESR1, field BIT1ERR[15] (RO)
mbed_official	324:406fd2029f23	1987	*
mbed_official	324:406fd2029f23	1988	* This bit indicates when an inconsistency occurs between the transmitted and
mbed_official	324:406fd2029f23	1989	* the received bit in a message. This bit is not set by a transmitter in case of
mbed_official	324:406fd2029f23	1990	* arbitration field or ACK slot, or in case of a node sending a passive error
mbed_official	324:406fd2029f23	1991	* flag that detects dominant bits.
mbed_official	324:406fd2029f23	1992	*
mbed_official	324:406fd2029f23	1993	* Values:
mbed_official	324:406fd2029f23	1994	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	1995	* - 1 - At least one bit sent as recessive is received as dominant.
mbed_official	324:406fd2029f23	1996	*/
mbed_official	324:406fd2029f23	1997	/@{/
mbed_official	324:406fd2029f23	1998	#define BP_CAN_ESR1_BIT1ERR (15U) /!< Bit position for CAN_ESR1_BIT1ERR. /
mbed_official	324:406fd2029f23	1999	#define BM_CAN_ESR1_BIT1ERR (0x00008000U) /!< Bit mask for CAN_ESR1_BIT1ERR. /
mbed_official	324:406fd2029f23	2000	#define BS_CAN_ESR1_BIT1ERR (1U) /!< Bit field size in bits for CAN_ESR1_BIT1ERR. /
mbed_official	324:406fd2029f23	2001
mbed_official	324:406fd2029f23	2002	/! @brief Read current value of the CAN_ESR1_BIT1ERR field. /
mbed_official	324:406fd2029f23	2003	#define BR_CAN_ESR1_BIT1ERR(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_BIT1ERR))
mbed_official	324:406fd2029f23	2004	/@}/
mbed_official	324:406fd2029f23	2005
mbed_official	324:406fd2029f23	2006	/*!
mbed_official	324:406fd2029f23	2007	* @name Register CAN_ESR1, field RWRNINT[16] (W1C)
mbed_official	324:406fd2029f23	2008	*
mbed_official	324:406fd2029f23	2009	* If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN
mbed_official	324:406fd2029f23	2010	* flag transitions from 0 to 1, meaning that the Rx error counters reached 96. If
mbed_official	324:406fd2029f23	2011	* the corresponding mask bit in the Control Register (RWRNMSK) is set, an
mbed_official	324:406fd2029f23	2012	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When
mbed_official	324:406fd2029f23	2013	* WRNEN is negated, this flag is masked. CPU must clear this flag before disabling
mbed_official	324:406fd2029f23	2014	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
mbed_official	324:406fd2029f23	2015	* effect. This bit is not updated during Freeze mode.
mbed_official	324:406fd2029f23	2016	*
mbed_official	324:406fd2029f23	2017	* Values:
mbed_official	324:406fd2029f23	2018	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	2019	* - 1 - The Rx error counter transitioned from less than 96 to greater than or
mbed_official	324:406fd2029f23	2020	* equal to 96.
mbed_official	324:406fd2029f23	2021	*/
mbed_official	324:406fd2029f23	2022	/@{/
mbed_official	324:406fd2029f23	2023	#define BP_CAN_ESR1_RWRNINT (16U) /!< Bit position for CAN_ESR1_RWRNINT. /
mbed_official	324:406fd2029f23	2024	#define BM_CAN_ESR1_RWRNINT (0x00010000U) /!< Bit mask for CAN_ESR1_RWRNINT. /
mbed_official	324:406fd2029f23	2025	#define BS_CAN_ESR1_RWRNINT (1U) /!< Bit field size in bits for CAN_ESR1_RWRNINT. /
mbed_official	324:406fd2029f23	2026
mbed_official	324:406fd2029f23	2027	/! @brief Read current value of the CAN_ESR1_RWRNINT field. /
mbed_official	324:406fd2029f23	2028	#define BR_CAN_ESR1_RWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT))
mbed_official	324:406fd2029f23	2029
mbed_official	324:406fd2029f23	2030	/! @brief Format value for bitfield CAN_ESR1_RWRNINT. /
mbed_official	324:406fd2029f23	2031	#define BF_CAN_ESR1_RWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_RWRNINT) & BM_CAN_ESR1_RWRNINT)
mbed_official	324:406fd2029f23	2032
mbed_official	324:406fd2029f23	2033	/! @brief Set the RWRNINT field to a new value. /
mbed_official	324:406fd2029f23	2034	#define BW_CAN_ESR1_RWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_RWRNINT) = (v))
mbed_official	324:406fd2029f23	2035	/@}/
mbed_official	324:406fd2029f23	2036
mbed_official	324:406fd2029f23	2037	/*!
mbed_official	324:406fd2029f23	2038	* @name Register CAN_ESR1, field TWRNINT[17] (W1C)
mbed_official	324:406fd2029f23	2039	*
mbed_official	324:406fd2029f23	2040	* If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN
mbed_official	324:406fd2029f23	2041	* flag transitions from 0 to 1, meaning that the Tx error counter reached 96. If
mbed_official	324:406fd2029f23	2042	* the corresponding mask bit in the Control Register (TWRNMSK) is set, an
mbed_official	324:406fd2029f23	2043	* interrupt is generated to the CPU. This bit is cleared by writing it to 1. When WRNEN
mbed_official	324:406fd2029f23	2044	* is negated, this flag is masked. CPU must clear this flag before disabling
mbed_official	324:406fd2029f23	2045	* the bit. Otherwise it will be set when the WRNEN is set again. Writing 0 has no
mbed_official	324:406fd2029f23	2046	* effect. This flag is not generated during Bus Off state. This bit is not
mbed_official	324:406fd2029f23	2047	* updated during Freeze mode.
mbed_official	324:406fd2029f23	2048	*
mbed_official	324:406fd2029f23	2049	* Values:
mbed_official	324:406fd2029f23	2050	* - 0 - No such occurrence.
mbed_official	324:406fd2029f23	2051	* - 1 - The Tx error counter transitioned from less than 96 to greater than or
mbed_official	324:406fd2029f23	2052	* equal to 96.
mbed_official	324:406fd2029f23	2053	*/
mbed_official	324:406fd2029f23	2054	/@{/
mbed_official	324:406fd2029f23	2055	#define BP_CAN_ESR1_TWRNINT (17U) /!< Bit position for CAN_ESR1_TWRNINT. /
mbed_official	324:406fd2029f23	2056	#define BM_CAN_ESR1_TWRNINT (0x00020000U) /!< Bit mask for CAN_ESR1_TWRNINT. /
mbed_official	324:406fd2029f23	2057	#define BS_CAN_ESR1_TWRNINT (1U) /!< Bit field size in bits for CAN_ESR1_TWRNINT. /
mbed_official	324:406fd2029f23	2058
mbed_official	324:406fd2029f23	2059	/! @brief Read current value of the CAN_ESR1_TWRNINT field. /
mbed_official	324:406fd2029f23	2060	#define BR_CAN_ESR1_TWRNINT(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT))
mbed_official	324:406fd2029f23	2061
mbed_official	324:406fd2029f23	2062	/! @brief Format value for bitfield CAN_ESR1_TWRNINT. /
mbed_official	324:406fd2029f23	2063	#define BF_CAN_ESR1_TWRNINT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_ESR1_TWRNINT) & BM_CAN_ESR1_TWRNINT)
mbed_official	324:406fd2029f23	2064
mbed_official	324:406fd2029f23	2065	/! @brief Set the TWRNINT field to a new value. /
mbed_official	324:406fd2029f23	2066	#define BW_CAN_ESR1_TWRNINT(x, v) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_TWRNINT) = (v))
mbed_official	324:406fd2029f23	2067	/@}/
mbed_official	324:406fd2029f23	2068
mbed_official	324:406fd2029f23	2069	/*!
mbed_official	324:406fd2029f23	2070	* @name Register CAN_ESR1, field SYNCH[18] (RO)
mbed_official	324:406fd2029f23	2071	*
mbed_official	324:406fd2029f23	2072	* This read-only flag indicates whether the FlexCAN is synchronized to the CAN
mbed_official	324:406fd2029f23	2073	* bus and able to participate in the communication process. It is set and
mbed_official	324:406fd2029f23	2074	* cleared by the FlexCAN. See the table in the overall CAN_ESR1 register description.
mbed_official	324:406fd2029f23	2075	*
mbed_official	324:406fd2029f23	2076	* Values:
mbed_official	324:406fd2029f23	2077	* - 0 - FlexCAN is not synchronized to the CAN bus.
mbed_official	324:406fd2029f23	2078	* - 1 - FlexCAN is synchronized to the CAN bus.
mbed_official	324:406fd2029f23	2079	*/
mbed_official	324:406fd2029f23	2080	/@{/
mbed_official	324:406fd2029f23	2081	#define BP_CAN_ESR1_SYNCH (18U) /!< Bit position for CAN_ESR1_SYNCH. /
mbed_official	324:406fd2029f23	2082	#define BM_CAN_ESR1_SYNCH (0x00040000U) /!< Bit mask for CAN_ESR1_SYNCH. /
mbed_official	324:406fd2029f23	2083	#define BS_CAN_ESR1_SYNCH (1U) /!< Bit field size in bits for CAN_ESR1_SYNCH. /
mbed_official	324:406fd2029f23	2084
mbed_official	324:406fd2029f23	2085	/! @brief Read current value of the CAN_ESR1_SYNCH field. /
mbed_official	324:406fd2029f23	2086	#define BR_CAN_ESR1_SYNCH(x) (BITBAND_ACCESS32(HW_CAN_ESR1_ADDR(x), BP_CAN_ESR1_SYNCH))
mbed_official	324:406fd2029f23	2087	/@}/
mbed_official	324:406fd2029f23	2088
mbed_official	324:406fd2029f23	2089	/*******************************************************************************
mbed_official	324:406fd2029f23	2090	* HW_CAN_IMASK1 - Interrupt Masks 1 register
mbed_official	324:406fd2029f23	2091	******************************************************************************/
mbed_official	324:406fd2029f23	2092
mbed_official	324:406fd2029f23	2093	/*!
mbed_official	324:406fd2029f23	2094	* @brief HW_CAN_IMASK1 - Interrupt Masks 1 register (RW)
mbed_official	324:406fd2029f23	2095	*
mbed_official	324:406fd2029f23	2096	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2097	*
mbed_official	324:406fd2029f23	2098	* This register allows any number of a range of the 32 Message Buffer
mbed_official	324:406fd2029f23	2099	* Interrupts to be enabled or disabled for MB31 to MB0. It contains one interrupt mask
mbed_official	324:406fd2029f23	2100	* bit per buffer, enabling the CPU to determine which buffer generates an
mbed_official	324:406fd2029f23	2101	* interrupt after a successful transmission or reception, that is, when the
mbed_official	324:406fd2029f23	2102	* corresponding IFLAG1 bit is set.
mbed_official	324:406fd2029f23	2103	*/
mbed_official	324:406fd2029f23	2104	typedef union _hw_can_imask1
mbed_official	324:406fd2029f23	2105	{
mbed_official	324:406fd2029f23	2106	uint32_t U;
mbed_official	324:406fd2029f23	2107	struct _hw_can_imask1_bitfields
mbed_official	324:406fd2029f23	2108	{
mbed_official	324:406fd2029f23	2109	uint32_t BUFLM : 32; /!< [31:0] Buffer MB i Mask /
mbed_official	324:406fd2029f23	2110	} B;
mbed_official	324:406fd2029f23	2111	} hw_can_imask1_t;
mbed_official	324:406fd2029f23	2112
mbed_official	324:406fd2029f23	2113	/*!
mbed_official	324:406fd2029f23	2114	* @name Constants and macros for entire CAN_IMASK1 register
mbed_official	324:406fd2029f23	2115	*/
mbed_official	324:406fd2029f23	2116	/@{/
mbed_official	324:406fd2029f23	2117	#define HW_CAN_IMASK1_ADDR(x) ((x) + 0x28U)
mbed_official	324:406fd2029f23	2118
mbed_official	324:406fd2029f23	2119	#define HW_CAN_IMASK1(x) ((__IO hw_can_imask1_t ) HW_CAN_IMASK1_ADDR(x))
mbed_official	324:406fd2029f23	2120	#define HW_CAN_IMASK1_RD(x) (HW_CAN_IMASK1(x).U)
mbed_official	324:406fd2029f23	2121	#define HW_CAN_IMASK1_WR(x, v) (HW_CAN_IMASK1(x).U = (v))
mbed_official	324:406fd2029f23	2122	#define HW_CAN_IMASK1_SET(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2123	#define HW_CAN_IMASK1_CLR(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2124	#define HW_CAN_IMASK1_TOG(x, v) (HW_CAN_IMASK1_WR(x, HW_CAN_IMASK1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2125	/@}/
mbed_official	324:406fd2029f23	2126
mbed_official	324:406fd2029f23	2127	/*
mbed_official	324:406fd2029f23	2128	* Constants & macros for individual CAN_IMASK1 bitfields
mbed_official	324:406fd2029f23	2129	*/
mbed_official	324:406fd2029f23	2130
mbed_official	324:406fd2029f23	2131	/*!
mbed_official	324:406fd2029f23	2132	* @name Register CAN_IMASK1, field BUFLM[31:0] (RW)
mbed_official	324:406fd2029f23	2133	*
mbed_official	324:406fd2029f23	2134	* Each bit enables or disables the corresponding FlexCAN Message Buffer
mbed_official	324:406fd2029f23	2135	* Interrupt for MB31 to MB0. Setting or clearing a bit in the IMASK1 Register can
mbed_official	324:406fd2029f23	2136	* assert or negate an interrupt request, if the corresponding IFLAG1 bit is set.
mbed_official	324:406fd2029f23	2137	*
mbed_official	324:406fd2029f23	2138	* Values:
mbed_official	324:406fd2029f23	2139	* - 0 - The corresponding buffer Interrupt is disabled.
mbed_official	324:406fd2029f23	2140	* - 1 - The corresponding buffer Interrupt is enabled.
mbed_official	324:406fd2029f23	2141	*/
mbed_official	324:406fd2029f23	2142	/@{/
mbed_official	324:406fd2029f23	2143	#define BP_CAN_IMASK1_BUFLM (0U) /!< Bit position for CAN_IMASK1_BUFLM. /
mbed_official	324:406fd2029f23	2144	#define BM_CAN_IMASK1_BUFLM (0xFFFFFFFFU) /!< Bit mask for CAN_IMASK1_BUFLM. /
mbed_official	324:406fd2029f23	2145	#define BS_CAN_IMASK1_BUFLM (32U) /!< Bit field size in bits for CAN_IMASK1_BUFLM. /
mbed_official	324:406fd2029f23	2146
mbed_official	324:406fd2029f23	2147	/! @brief Read current value of the CAN_IMASK1_BUFLM field. /
mbed_official	324:406fd2029f23	2148	#define BR_CAN_IMASK1_BUFLM(x) (HW_CAN_IMASK1(x).U)
mbed_official	324:406fd2029f23	2149
mbed_official	324:406fd2029f23	2150	/! @brief Format value for bitfield CAN_IMASK1_BUFLM. /
mbed_official	324:406fd2029f23	2151	#define BF_CAN_IMASK1_BUFLM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IMASK1_BUFLM) & BM_CAN_IMASK1_BUFLM)
mbed_official	324:406fd2029f23	2152
mbed_official	324:406fd2029f23	2153	/! @brief Set the BUFLM field to a new value. /
mbed_official	324:406fd2029f23	2154	#define BW_CAN_IMASK1_BUFLM(x, v) (HW_CAN_IMASK1_WR(x, v))
mbed_official	324:406fd2029f23	2155	/@}/
mbed_official	324:406fd2029f23	2156
mbed_official	324:406fd2029f23	2157	/*******************************************************************************
mbed_official	324:406fd2029f23	2158	* HW_CAN_IFLAG1 - Interrupt Flags 1 register
mbed_official	324:406fd2029f23	2159	******************************************************************************/
mbed_official	324:406fd2029f23	2160
mbed_official	324:406fd2029f23	2161	/*!
mbed_official	324:406fd2029f23	2162	* @brief HW_CAN_IFLAG1 - Interrupt Flags 1 register (W1C)
mbed_official	324:406fd2029f23	2163	*
mbed_official	324:406fd2029f23	2164	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2165	*
mbed_official	324:406fd2029f23	2166	* This register defines the flags for the 32 Message Buffer interrupts for MB31
mbed_official	324:406fd2029f23	2167	* to MB0. It contains one interrupt flag bit per buffer. Each successful
mbed_official	324:406fd2029f23	2168	* transmission or reception sets the corresponding IFLAG1 bit. If the corresponding
mbed_official	324:406fd2029f23	2169	* IMASK1 bit is set, an interrupt will be generated. The interrupt flag must be
mbed_official	324:406fd2029f23	2170	* cleared by writing 1 to it. Writing 0 has no effect. The BUF7I to BUF5I flags
mbed_official	324:406fd2029f23	2171	* are also used to represent FIFO interrupts when the Rx FIFO is enabled. When the
mbed_official	324:406fd2029f23	2172	* bit MCR[RFEN] is set, the function of the 8 least significant interrupt flags
mbed_official	324:406fd2029f23	2173	* BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating conditions of
mbed_official	324:406fd2029f23	2174	* the FIFO, and the BUF4TO0I field is reserved. Before enabling the RFEN, the CPU
mbed_official	324:406fd2029f23	2175	* must service the IFLAG bits asserted in the Rx FIFO region; see Section "Rx
mbed_official	324:406fd2029f23	2176	* FIFO". Otherwise, these IFLAG bits will mistakenly show the related MBs now
mbed_official	324:406fd2029f23	2177	* belonging to FIFO as having contents to be serviced. When the RFEN bit is negated,
mbed_official	324:406fd2029f23	2178	* the FIFO flags must be cleared. The same care must be taken when an RFFN
mbed_official	324:406fd2029f23	2179	* value is selected extending Rx FIFO filters beyond MB7. For example, when RFFN is
mbed_official	324:406fd2029f23	2180	* 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
mbed_official	324:406fd2029f23	2181	* must be cleared. Before updating MCR[MAXMB] field, CPU must service the IFLAG1
mbed_official	324:406fd2029f23	2182	* bits whose MB value is greater than the MCR[MAXMB] to be updated; otherwise,
mbed_official	324:406fd2029f23	2183	* they will remain set and be inconsistent with the number of MBs available.
mbed_official	324:406fd2029f23	2184	*/
mbed_official	324:406fd2029f23	2185	typedef union _hw_can_iflag1
mbed_official	324:406fd2029f23	2186	{
mbed_official	324:406fd2029f23	2187	uint32_t U;
mbed_official	324:406fd2029f23	2188	struct _hw_can_iflag1_bitfields
mbed_official	324:406fd2029f23	2189	{
mbed_official	324:406fd2029f23	2190	uint32_t BUF0I : 1; /!< [0] Buffer MB0 Interrupt Or "reserved" /
mbed_official	324:406fd2029f23	2191	uint32_t BUF4TO1I : 4; /*!< [4:1] Buffer MB i Interrupt Or "reserved"
mbed_official	324:406fd2029f23	2192	* */
mbed_official	324:406fd2029f23	2193	uint32_t BUF5I : 1; /*!< [5] Buffer MB5 Interrupt Or "Frames
mbed_official	324:406fd2029f23	2194	* available in Rx FIFO" */
mbed_official	324:406fd2029f23	2195	uint32_t BUF6I : 1; /*!< [6] Buffer MB6 Interrupt Or "Rx FIFO
mbed_official	324:406fd2029f23	2196	* Warning" */
mbed_official	324:406fd2029f23	2197	uint32_t BUF7I : 1; /*!< [7] Buffer MB7 Interrupt Or "Rx FIFO
mbed_official	324:406fd2029f23	2198	* Overflow" */
mbed_official	324:406fd2029f23	2199	uint32_t BUF31TO8I : 24; /!< [31:8] Buffer MBi Interrupt /
mbed_official	324:406fd2029f23	2200	} B;
mbed_official	324:406fd2029f23	2201	} hw_can_iflag1_t;
mbed_official	324:406fd2029f23	2202
mbed_official	324:406fd2029f23	2203	/*!
mbed_official	324:406fd2029f23	2204	* @name Constants and macros for entire CAN_IFLAG1 register
mbed_official	324:406fd2029f23	2205	*/
mbed_official	324:406fd2029f23	2206	/@{/
mbed_official	324:406fd2029f23	2207	#define HW_CAN_IFLAG1_ADDR(x) ((x) + 0x30U)
mbed_official	324:406fd2029f23	2208
mbed_official	324:406fd2029f23	2209	#define HW_CAN_IFLAG1(x) ((__IO hw_can_iflag1_t ) HW_CAN_IFLAG1_ADDR(x))
mbed_official	324:406fd2029f23	2210	#define HW_CAN_IFLAG1_RD(x) (HW_CAN_IFLAG1(x).U)
mbed_official	324:406fd2029f23	2211	#define HW_CAN_IFLAG1_WR(x, v) (HW_CAN_IFLAG1(x).U = (v))
mbed_official	324:406fd2029f23	2212	#define HW_CAN_IFLAG1_SET(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2213	#define HW_CAN_IFLAG1_CLR(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2214	#define HW_CAN_IFLAG1_TOG(x, v) (HW_CAN_IFLAG1_WR(x, HW_CAN_IFLAG1_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2215	/@}/
mbed_official	324:406fd2029f23	2216
mbed_official	324:406fd2029f23	2217	/*
mbed_official	324:406fd2029f23	2218	* Constants & macros for individual CAN_IFLAG1 bitfields
mbed_official	324:406fd2029f23	2219	*/
mbed_official	324:406fd2029f23	2220
mbed_official	324:406fd2029f23	2221	/*!
mbed_official	324:406fd2029f23	2222	* @name Register CAN_IFLAG1, field BUF0I[0] (W1C)
mbed_official	324:406fd2029f23	2223	*
mbed_official	324:406fd2029f23	2224	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official	324:406fd2029f23	2225	* the interrupt for MB0. This flag is cleared by the FlexCAN whenever the bit
mbed_official	324:406fd2029f23	2226	* MCR[RFEN] is changed by CPU writes. The BUF0I flag is reserved when MCR[RFEN] is
mbed_official	324:406fd2029f23	2227	* set.
mbed_official	324:406fd2029f23	2228	*
mbed_official	324:406fd2029f23	2229	* Values:
mbed_official	324:406fd2029f23	2230	* - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official	324:406fd2029f23	2231	* transmission or reception when MCR[RFEN]=0.
mbed_official	324:406fd2029f23	2232	* - 1 - The corresponding buffer has successfully completed transmission or
mbed_official	324:406fd2029f23	2233	* reception when MCR[RFEN]=0.
mbed_official	324:406fd2029f23	2234	*/
mbed_official	324:406fd2029f23	2235	/@{/
mbed_official	324:406fd2029f23	2236	#define BP_CAN_IFLAG1_BUF0I (0U) /!< Bit position for CAN_IFLAG1_BUF0I. /
mbed_official	324:406fd2029f23	2237	#define BM_CAN_IFLAG1_BUF0I (0x00000001U) /!< Bit mask for CAN_IFLAG1_BUF0I. /
mbed_official	324:406fd2029f23	2238	#define BS_CAN_IFLAG1_BUF0I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF0I. /
mbed_official	324:406fd2029f23	2239
mbed_official	324:406fd2029f23	2240	/! @brief Read current value of the CAN_IFLAG1_BUF0I field. /
mbed_official	324:406fd2029f23	2241	#define BR_CAN_IFLAG1_BUF0I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I))
mbed_official	324:406fd2029f23	2242
mbed_official	324:406fd2029f23	2243	/! @brief Format value for bitfield CAN_IFLAG1_BUF0I. /
mbed_official	324:406fd2029f23	2244	#define BF_CAN_IFLAG1_BUF0I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF0I) & BM_CAN_IFLAG1_BUF0I)
mbed_official	324:406fd2029f23	2245
mbed_official	324:406fd2029f23	2246	/! @brief Set the BUF0I field to a new value. /
mbed_official	324:406fd2029f23	2247	#define BW_CAN_IFLAG1_BUF0I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF0I) = (v))
mbed_official	324:406fd2029f23	2248	/@}/
mbed_official	324:406fd2029f23	2249
mbed_official	324:406fd2029f23	2250	/*!
mbed_official	324:406fd2029f23	2251	* @name Register CAN_IFLAG1, field BUF4TO1I[4:1] (W1C)
mbed_official	324:406fd2029f23	2252	*
mbed_official	324:406fd2029f23	2253	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), these bits flag
mbed_official	324:406fd2029f23	2254	* the interrupts for MB4 to MB1. These flags are cleared by the FlexCAN whenever
mbed_official	324:406fd2029f23	2255	* the bit MCR[RFEN] is changed by CPU writes. The BUF4TO1I flags are reserved
mbed_official	324:406fd2029f23	2256	* when MCR[RFEN] is set.
mbed_official	324:406fd2029f23	2257	*
mbed_official	324:406fd2029f23	2258	* Values:
mbed_official	324:406fd2029f23	2259	* - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official	324:406fd2029f23	2260	* transmission or reception when MCR[RFEN]=0.
mbed_official	324:406fd2029f23	2261	* - 1 - The corresponding buffer has successfully completed transmission or
mbed_official	324:406fd2029f23	2262	* reception when MCR[RFEN]=0.
mbed_official	324:406fd2029f23	2263	*/
mbed_official	324:406fd2029f23	2264	/@{/
mbed_official	324:406fd2029f23	2265	#define BP_CAN_IFLAG1_BUF4TO1I (1U) /!< Bit position for CAN_IFLAG1_BUF4TO1I. /
mbed_official	324:406fd2029f23	2266	#define BM_CAN_IFLAG1_BUF4TO1I (0x0000001EU) /!< Bit mask for CAN_IFLAG1_BUF4TO1I. /
mbed_official	324:406fd2029f23	2267	#define BS_CAN_IFLAG1_BUF4TO1I (4U) /!< Bit field size in bits for CAN_IFLAG1_BUF4TO1I. /
mbed_official	324:406fd2029f23	2268
mbed_official	324:406fd2029f23	2269	/! @brief Read current value of the CAN_IFLAG1_BUF4TO1I field. /
mbed_official	324:406fd2029f23	2270	#define BR_CAN_IFLAG1_BUF4TO1I(x) (HW_CAN_IFLAG1(x).B.BUF4TO1I)
mbed_official	324:406fd2029f23	2271
mbed_official	324:406fd2029f23	2272	/! @brief Format value for bitfield CAN_IFLAG1_BUF4TO1I. /
mbed_official	324:406fd2029f23	2273	#define BF_CAN_IFLAG1_BUF4TO1I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF4TO1I) & BM_CAN_IFLAG1_BUF4TO1I)
mbed_official	324:406fd2029f23	2274
mbed_official	324:406fd2029f23	2275	/! @brief Set the BUF4TO1I field to a new value. /
mbed_official	324:406fd2029f23	2276	#define BW_CAN_IFLAG1_BUF4TO1I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF4TO1I) \| BF_CAN_IFLAG1_BUF4TO1I(v)))
mbed_official	324:406fd2029f23	2277	/@}/
mbed_official	324:406fd2029f23	2278
mbed_official	324:406fd2029f23	2279	/*!
mbed_official	324:406fd2029f23	2280	* @name Register CAN_IFLAG1, field BUF5I[5] (W1C)
mbed_official	324:406fd2029f23	2281	*
mbed_official	324:406fd2029f23	2282	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official	324:406fd2029f23	2283	* the interrupt for MB5. This flag is cleared by the FlexCAN whenever the bit
mbed_official	324:406fd2029f23	2284	* MCR[RFEN] is changed by CPU writes. The BUF5I flag represents "Frames available in
mbed_official	324:406fd2029f23	2285	* Rx FIFO" when MCR[RFEN] is set. In this case, the flag indicates that at
mbed_official	324:406fd2029f23	2286	* least one frame is available to be read from the Rx FIFO.
mbed_official	324:406fd2029f23	2287	*
mbed_official	324:406fd2029f23	2288	* Values:
mbed_official	324:406fd2029f23	2289	* - 0 - No occurrence of MB5 completing transmission/reception when
mbed_official	324:406fd2029f23	2290	* MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2291	* - 1 - MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s)
mbed_official	324:406fd2029f23	2292	* available in the Rx FIFO when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2293	*/
mbed_official	324:406fd2029f23	2294	/@{/
mbed_official	324:406fd2029f23	2295	#define BP_CAN_IFLAG1_BUF5I (5U) /!< Bit position for CAN_IFLAG1_BUF5I. /
mbed_official	324:406fd2029f23	2296	#define BM_CAN_IFLAG1_BUF5I (0x00000020U) /!< Bit mask for CAN_IFLAG1_BUF5I. /
mbed_official	324:406fd2029f23	2297	#define BS_CAN_IFLAG1_BUF5I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF5I. /
mbed_official	324:406fd2029f23	2298
mbed_official	324:406fd2029f23	2299	/! @brief Read current value of the CAN_IFLAG1_BUF5I field. /
mbed_official	324:406fd2029f23	2300	#define BR_CAN_IFLAG1_BUF5I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I))
mbed_official	324:406fd2029f23	2301
mbed_official	324:406fd2029f23	2302	/! @brief Format value for bitfield CAN_IFLAG1_BUF5I. /
mbed_official	324:406fd2029f23	2303	#define BF_CAN_IFLAG1_BUF5I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF5I) & BM_CAN_IFLAG1_BUF5I)
mbed_official	324:406fd2029f23	2304
mbed_official	324:406fd2029f23	2305	/! @brief Set the BUF5I field to a new value. /
mbed_official	324:406fd2029f23	2306	#define BW_CAN_IFLAG1_BUF5I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF5I) = (v))
mbed_official	324:406fd2029f23	2307	/@}/
mbed_official	324:406fd2029f23	2308
mbed_official	324:406fd2029f23	2309	/*!
mbed_official	324:406fd2029f23	2310	* @name Register CAN_IFLAG1, field BUF6I[6] (W1C)
mbed_official	324:406fd2029f23	2311	*
mbed_official	324:406fd2029f23	2312	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official	324:406fd2029f23	2313	* the interrupt for MB6. This flag is cleared by the FlexCAN whenever the bit
mbed_official	324:406fd2029f23	2314	* MCR[RFEN] is changed by CPU writes. The BUF6I flag represents "Rx FIFO Warning"
mbed_official	324:406fd2029f23	2315	* when MCR[RFEN] is set. In this case, the flag indicates when the number of
mbed_official	324:406fd2029f23	2316	* unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
mbed_official	324:406fd2029f23	2317	* a new one, meaning that the Rx FIFO is almost full. Note that if the flag is
mbed_official	324:406fd2029f23	2318	* cleared while the number of unread messages is greater than 4, it does not
mbed_official	324:406fd2029f23	2319	* assert again until the number of unread messages within the Rx FIFO is decreased
mbed_official	324:406fd2029f23	2320	* to be equal to or less than 4.
mbed_official	324:406fd2029f23	2321	*
mbed_official	324:406fd2029f23	2322	* Values:
mbed_official	324:406fd2029f23	2323	* - 0 - No occurrence of MB6 completing transmission/reception when
mbed_official	324:406fd2029f23	2324	* MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2325	* - 1 - MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
mbed_official	324:406fd2029f23	2326	* almost full when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2327	*/
mbed_official	324:406fd2029f23	2328	/@{/
mbed_official	324:406fd2029f23	2329	#define BP_CAN_IFLAG1_BUF6I (6U) /!< Bit position for CAN_IFLAG1_BUF6I. /
mbed_official	324:406fd2029f23	2330	#define BM_CAN_IFLAG1_BUF6I (0x00000040U) /!< Bit mask for CAN_IFLAG1_BUF6I. /
mbed_official	324:406fd2029f23	2331	#define BS_CAN_IFLAG1_BUF6I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF6I. /
mbed_official	324:406fd2029f23	2332
mbed_official	324:406fd2029f23	2333	/! @brief Read current value of the CAN_IFLAG1_BUF6I field. /
mbed_official	324:406fd2029f23	2334	#define BR_CAN_IFLAG1_BUF6I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I))
mbed_official	324:406fd2029f23	2335
mbed_official	324:406fd2029f23	2336	/! @brief Format value for bitfield CAN_IFLAG1_BUF6I. /
mbed_official	324:406fd2029f23	2337	#define BF_CAN_IFLAG1_BUF6I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF6I) & BM_CAN_IFLAG1_BUF6I)
mbed_official	324:406fd2029f23	2338
mbed_official	324:406fd2029f23	2339	/! @brief Set the BUF6I field to a new value. /
mbed_official	324:406fd2029f23	2340	#define BW_CAN_IFLAG1_BUF6I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF6I) = (v))
mbed_official	324:406fd2029f23	2341	/@}/
mbed_official	324:406fd2029f23	2342
mbed_official	324:406fd2029f23	2343	/*!
mbed_official	324:406fd2029f23	2344	* @name Register CAN_IFLAG1, field BUF7I[7] (W1C)
mbed_official	324:406fd2029f23	2345	*
mbed_official	324:406fd2029f23	2346	* When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags
mbed_official	324:406fd2029f23	2347	* the interrupt for MB7. This flag is cleared by the FlexCAN whenever the bit
mbed_official	324:406fd2029f23	2348	* MCR[RFEN] is changed by CPU writes. The BUF7I flag represents "Rx FIFO Overflow"
mbed_official	324:406fd2029f23	2349	* when MCR[RFEN] is set. In this case, the flag indicates that a message was lost
mbed_official	324:406fd2029f23	2350	* because the Rx FIFO is full. Note that the flag will not be asserted when the
mbed_official	324:406fd2029f23	2351	* Rx FIFO is full and the message was captured by a Mailbox.
mbed_official	324:406fd2029f23	2352	*
mbed_official	324:406fd2029f23	2353	* Values:
mbed_official	324:406fd2029f23	2354	* - 0 - No occurrence of MB7 completing transmission/reception when
mbed_official	324:406fd2029f23	2355	* MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2356	* - 1 - MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO
mbed_official	324:406fd2029f23	2357	* overflow when MCR[RFEN]=1
mbed_official	324:406fd2029f23	2358	*/
mbed_official	324:406fd2029f23	2359	/@{/
mbed_official	324:406fd2029f23	2360	#define BP_CAN_IFLAG1_BUF7I (7U) /!< Bit position for CAN_IFLAG1_BUF7I. /
mbed_official	324:406fd2029f23	2361	#define BM_CAN_IFLAG1_BUF7I (0x00000080U) /!< Bit mask for CAN_IFLAG1_BUF7I. /
mbed_official	324:406fd2029f23	2362	#define BS_CAN_IFLAG1_BUF7I (1U) /!< Bit field size in bits for CAN_IFLAG1_BUF7I. /
mbed_official	324:406fd2029f23	2363
mbed_official	324:406fd2029f23	2364	/! @brief Read current value of the CAN_IFLAG1_BUF7I field. /
mbed_official	324:406fd2029f23	2365	#define BR_CAN_IFLAG1_BUF7I(x) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I))
mbed_official	324:406fd2029f23	2366
mbed_official	324:406fd2029f23	2367	/! @brief Format value for bitfield CAN_IFLAG1_BUF7I. /
mbed_official	324:406fd2029f23	2368	#define BF_CAN_IFLAG1_BUF7I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF7I) & BM_CAN_IFLAG1_BUF7I)
mbed_official	324:406fd2029f23	2369
mbed_official	324:406fd2029f23	2370	/! @brief Set the BUF7I field to a new value. /
mbed_official	324:406fd2029f23	2371	#define BW_CAN_IFLAG1_BUF7I(x, v) (BITBAND_ACCESS32(HW_CAN_IFLAG1_ADDR(x), BP_CAN_IFLAG1_BUF7I) = (v))
mbed_official	324:406fd2029f23	2372	/@}/
mbed_official	324:406fd2029f23	2373
mbed_official	324:406fd2029f23	2374	/*!
mbed_official	324:406fd2029f23	2375	* @name Register CAN_IFLAG1, field BUF31TO8I[31:8] (W1C)
mbed_official	324:406fd2029f23	2376	*
mbed_official	324:406fd2029f23	2377	* Each bit flags the corresponding FlexCAN Message Buffer interrupt for MB31 to
mbed_official	324:406fd2029f23	2378	* MB8.
mbed_official	324:406fd2029f23	2379	*
mbed_official	324:406fd2029f23	2380	* Values:
mbed_official	324:406fd2029f23	2381	* - 0 - The corresponding buffer has no occurrence of successfully completed
mbed_official	324:406fd2029f23	2382	* transmission or reception.
mbed_official	324:406fd2029f23	2383	* - 1 - The corresponding buffer has successfully completed transmission or
mbed_official	324:406fd2029f23	2384	* reception.
mbed_official	324:406fd2029f23	2385	*/
mbed_official	324:406fd2029f23	2386	/@{/
mbed_official	324:406fd2029f23	2387	#define BP_CAN_IFLAG1_BUF31TO8I (8U) /!< Bit position for CAN_IFLAG1_BUF31TO8I. /
mbed_official	324:406fd2029f23	2388	#define BM_CAN_IFLAG1_BUF31TO8I (0xFFFFFF00U) /!< Bit mask for CAN_IFLAG1_BUF31TO8I. /
mbed_official	324:406fd2029f23	2389	#define BS_CAN_IFLAG1_BUF31TO8I (24U) /!< Bit field size in bits for CAN_IFLAG1_BUF31TO8I. /
mbed_official	324:406fd2029f23	2390
mbed_official	324:406fd2029f23	2391	/! @brief Read current value of the CAN_IFLAG1_BUF31TO8I field. /
mbed_official	324:406fd2029f23	2392	#define BR_CAN_IFLAG1_BUF31TO8I(x) (HW_CAN_IFLAG1(x).B.BUF31TO8I)
mbed_official	324:406fd2029f23	2393
mbed_official	324:406fd2029f23	2394	/! @brief Format value for bitfield CAN_IFLAG1_BUF31TO8I. /
mbed_official	324:406fd2029f23	2395	#define BF_CAN_IFLAG1_BUF31TO8I(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IFLAG1_BUF31TO8I) & BM_CAN_IFLAG1_BUF31TO8I)
mbed_official	324:406fd2029f23	2396
mbed_official	324:406fd2029f23	2397	/! @brief Set the BUF31TO8I field to a new value. /
mbed_official	324:406fd2029f23	2398	#define BW_CAN_IFLAG1_BUF31TO8I(x, v) (HW_CAN_IFLAG1_WR(x, (HW_CAN_IFLAG1_RD(x) & ~BM_CAN_IFLAG1_BUF31TO8I) \| BF_CAN_IFLAG1_BUF31TO8I(v)))
mbed_official	324:406fd2029f23	2399	/@}/
mbed_official	324:406fd2029f23	2400
mbed_official	324:406fd2029f23	2401	/*******************************************************************************
mbed_official	324:406fd2029f23	2402	* HW_CAN_CTRL2 - Control 2 register
mbed_official	324:406fd2029f23	2403	******************************************************************************/
mbed_official	324:406fd2029f23	2404
mbed_official	324:406fd2029f23	2405	/*!
mbed_official	324:406fd2029f23	2406	* @brief HW_CAN_CTRL2 - Control 2 register (RW)
mbed_official	324:406fd2029f23	2407	*
mbed_official	324:406fd2029f23	2408	* Reset value: 0x00B00000U
mbed_official	324:406fd2029f23	2409	*
mbed_official	324:406fd2029f23	2410	* This register contains control bits for CAN errors, FIFO features, and mode
mbed_official	324:406fd2029f23	2411	* selection.
mbed_official	324:406fd2029f23	2412	*/
mbed_official	324:406fd2029f23	2413	typedef union _hw_can_ctrl2
mbed_official	324:406fd2029f23	2414	{
mbed_official	324:406fd2029f23	2415	uint32_t U;
mbed_official	324:406fd2029f23	2416	struct _hw_can_ctrl2_bitfields
mbed_official	324:406fd2029f23	2417	{
mbed_official	324:406fd2029f23	2418	uint32_t RESERVED0 : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	2419	uint32_t EACEN : 1; /*!< [16] Entire Frame Arbitration Field
mbed_official	324:406fd2029f23	2420	* Comparison Enable For Rx Mailboxes */
mbed_official	324:406fd2029f23	2421	uint32_t RRS : 1; /!< [17] Remote Request Storing /
mbed_official	324:406fd2029f23	2422	uint32_t MRP : 1; /!< [18] Mailboxes Reception Priority /
mbed_official	324:406fd2029f23	2423	uint32_t TASD : 5; /!< [23:19] Tx Arbitration Start Delay /
mbed_official	324:406fd2029f23	2424	uint32_t RFFN : 4; /!< [27:24] Number Of Rx FIFO Filters /
mbed_official	324:406fd2029f23	2425	uint32_t WRMFRZ : 1; /*!< [28] Write-Access To Memory In Freeze Mode
mbed_official	324:406fd2029f23	2426	* */
mbed_official	324:406fd2029f23	2427	uint32_t RESERVED1 : 3; /!< [31:29] /
mbed_official	324:406fd2029f23	2428	} B;
mbed_official	324:406fd2029f23	2429	} hw_can_ctrl2_t;
mbed_official	324:406fd2029f23	2430
mbed_official	324:406fd2029f23	2431	/*!
mbed_official	324:406fd2029f23	2432	* @name Constants and macros for entire CAN_CTRL2 register
mbed_official	324:406fd2029f23	2433	*/
mbed_official	324:406fd2029f23	2434	/@{/
mbed_official	324:406fd2029f23	2435	#define HW_CAN_CTRL2_ADDR(x) ((x) + 0x34U)
mbed_official	324:406fd2029f23	2436
mbed_official	324:406fd2029f23	2437	#define HW_CAN_CTRL2(x) ((__IO hw_can_ctrl2_t ) HW_CAN_CTRL2_ADDR(x))
mbed_official	324:406fd2029f23	2438	#define HW_CAN_CTRL2_RD(x) (HW_CAN_CTRL2(x).U)
mbed_official	324:406fd2029f23	2439	#define HW_CAN_CTRL2_WR(x, v) (HW_CAN_CTRL2(x).U = (v))
mbed_official	324:406fd2029f23	2440	#define HW_CAN_CTRL2_SET(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2441	#define HW_CAN_CTRL2_CLR(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2442	#define HW_CAN_CTRL2_TOG(x, v) (HW_CAN_CTRL2_WR(x, HW_CAN_CTRL2_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2443	/@}/
mbed_official	324:406fd2029f23	2444
mbed_official	324:406fd2029f23	2445	/*
mbed_official	324:406fd2029f23	2446	* Constants & macros for individual CAN_CTRL2 bitfields
mbed_official	324:406fd2029f23	2447	*/
mbed_official	324:406fd2029f23	2448
mbed_official	324:406fd2029f23	2449	/*!
mbed_official	324:406fd2029f23	2450	* @name Register CAN_CTRL2, field EACEN[16] (RW)
mbed_official	324:406fd2029f23	2451	*
mbed_official	324:406fd2029f23	2452	* This bit controls the comparison of IDE and RTR bits whithin Rx Mailboxes
mbed_official	324:406fd2029f23	2453	* filters with their corresponding bits in the incoming frame by the matching
mbed_official	324:406fd2029f23	2454	* process. This bit does not affect matching for Rx FIFO. This bit can be written
mbed_official	324:406fd2029f23	2455	* only in Freeze mode because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	2456	*
mbed_official	324:406fd2029f23	2457	* Values:
mbed_official	324:406fd2029f23	2458	* - 0 - Rx Mailbox filter's IDE bit is always compared and RTR is never
mbed_official	324:406fd2029f23	2459	* compared despite mask bits.
mbed_official	324:406fd2029f23	2460	* - 1 - Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with
mbed_official	324:406fd2029f23	2461	* their corresponding bits within the incoming frame. Mask bits do apply.
mbed_official	324:406fd2029f23	2462	*/
mbed_official	324:406fd2029f23	2463	/@{/
mbed_official	324:406fd2029f23	2464	#define BP_CAN_CTRL2_EACEN (16U) /!< Bit position for CAN_CTRL2_EACEN. /
mbed_official	324:406fd2029f23	2465	#define BM_CAN_CTRL2_EACEN (0x00010000U) /!< Bit mask for CAN_CTRL2_EACEN. /
mbed_official	324:406fd2029f23	2466	#define BS_CAN_CTRL2_EACEN (1U) /!< Bit field size in bits for CAN_CTRL2_EACEN. /
mbed_official	324:406fd2029f23	2467
mbed_official	324:406fd2029f23	2468	/! @brief Read current value of the CAN_CTRL2_EACEN field. /
mbed_official	324:406fd2029f23	2469	#define BR_CAN_CTRL2_EACEN(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN))
mbed_official	324:406fd2029f23	2470
mbed_official	324:406fd2029f23	2471	/! @brief Format value for bitfield CAN_CTRL2_EACEN. /
mbed_official	324:406fd2029f23	2472	#define BF_CAN_CTRL2_EACEN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_EACEN) & BM_CAN_CTRL2_EACEN)
mbed_official	324:406fd2029f23	2473
mbed_official	324:406fd2029f23	2474	/! @brief Set the EACEN field to a new value. /
mbed_official	324:406fd2029f23	2475	#define BW_CAN_CTRL2_EACEN(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_EACEN) = (v))
mbed_official	324:406fd2029f23	2476	/@}/
mbed_official	324:406fd2029f23	2477
mbed_official	324:406fd2029f23	2478	/*!
mbed_official	324:406fd2029f23	2479	* @name Register CAN_CTRL2, field RRS[17] (RW)
mbed_official	324:406fd2029f23	2480	*
mbed_official	324:406fd2029f23	2481	* If this bit is asserted Remote Request Frame is submitted to a matching
mbed_official	324:406fd2029f23	2482	* process and stored in the corresponding Message Buffer in the same fashion of a
mbed_official	324:406fd2029f23	2483	* Data Frame. No automatic Remote Response Frame will be generated. If this bit is
mbed_official	324:406fd2029f23	2484	* negated the Remote Request Frame is submitted to a matching process and an
mbed_official	324:406fd2029f23	2485	* automatic Remote Response Frame is generated if a Message Buffer with CODE=0b1010
mbed_official	324:406fd2029f23	2486	* is found with the same ID. This bit can be written only in Freeze mode
mbed_official	324:406fd2029f23	2487	* because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	2488	*
mbed_official	324:406fd2029f23	2489	* Values:
mbed_official	324:406fd2029f23	2490	* - 0 - Remote Response Frame is generated.
mbed_official	324:406fd2029f23	2491	* - 1 - Remote Request Frame is stored.
mbed_official	324:406fd2029f23	2492	*/
mbed_official	324:406fd2029f23	2493	/@{/
mbed_official	324:406fd2029f23	2494	#define BP_CAN_CTRL2_RRS (17U) /!< Bit position for CAN_CTRL2_RRS. /
mbed_official	324:406fd2029f23	2495	#define BM_CAN_CTRL2_RRS (0x00020000U) /!< Bit mask for CAN_CTRL2_RRS. /
mbed_official	324:406fd2029f23	2496	#define BS_CAN_CTRL2_RRS (1U) /!< Bit field size in bits for CAN_CTRL2_RRS. /
mbed_official	324:406fd2029f23	2497
mbed_official	324:406fd2029f23	2498	/! @brief Read current value of the CAN_CTRL2_RRS field. /
mbed_official	324:406fd2029f23	2499	#define BR_CAN_CTRL2_RRS(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS))
mbed_official	324:406fd2029f23	2500
mbed_official	324:406fd2029f23	2501	/! @brief Format value for bitfield CAN_CTRL2_RRS. /
mbed_official	324:406fd2029f23	2502	#define BF_CAN_CTRL2_RRS(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RRS) & BM_CAN_CTRL2_RRS)
mbed_official	324:406fd2029f23	2503
mbed_official	324:406fd2029f23	2504	/! @brief Set the RRS field to a new value. /
mbed_official	324:406fd2029f23	2505	#define BW_CAN_CTRL2_RRS(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_RRS) = (v))
mbed_official	324:406fd2029f23	2506	/@}/
mbed_official	324:406fd2029f23	2507
mbed_official	324:406fd2029f23	2508	/*!
mbed_official	324:406fd2029f23	2509	* @name Register CAN_CTRL2, field MRP[18] (RW)
mbed_official	324:406fd2029f23	2510	*
mbed_official	324:406fd2029f23	2511	* If this bit is set the matching process starts from the Mailboxes and if no
mbed_official	324:406fd2029f23	2512	* match occurs the matching continues on the Rx FIFO. This bit can be written
mbed_official	324:406fd2029f23	2513	* only in Freeze mode because it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	2514	*
mbed_official	324:406fd2029f23	2515	* Values:
mbed_official	324:406fd2029f23	2516	* - 0 - Matching starts from Rx FIFO and continues on Mailboxes.
mbed_official	324:406fd2029f23	2517	* - 1 - Matching starts from Mailboxes and continues on Rx FIFO.
mbed_official	324:406fd2029f23	2518	*/
mbed_official	324:406fd2029f23	2519	/@{/
mbed_official	324:406fd2029f23	2520	#define BP_CAN_CTRL2_MRP (18U) /!< Bit position for CAN_CTRL2_MRP. /
mbed_official	324:406fd2029f23	2521	#define BM_CAN_CTRL2_MRP (0x00040000U) /!< Bit mask for CAN_CTRL2_MRP. /
mbed_official	324:406fd2029f23	2522	#define BS_CAN_CTRL2_MRP (1U) /!< Bit field size in bits for CAN_CTRL2_MRP. /
mbed_official	324:406fd2029f23	2523
mbed_official	324:406fd2029f23	2524	/! @brief Read current value of the CAN_CTRL2_MRP field. /
mbed_official	324:406fd2029f23	2525	#define BR_CAN_CTRL2_MRP(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP))
mbed_official	324:406fd2029f23	2526
mbed_official	324:406fd2029f23	2527	/! @brief Format value for bitfield CAN_CTRL2_MRP. /
mbed_official	324:406fd2029f23	2528	#define BF_CAN_CTRL2_MRP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_MRP) & BM_CAN_CTRL2_MRP)
mbed_official	324:406fd2029f23	2529
mbed_official	324:406fd2029f23	2530	/! @brief Set the MRP field to a new value. /
mbed_official	324:406fd2029f23	2531	#define BW_CAN_CTRL2_MRP(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_MRP) = (v))
mbed_official	324:406fd2029f23	2532	/@}/
mbed_official	324:406fd2029f23	2533
mbed_official	324:406fd2029f23	2534	/*!
mbed_official	324:406fd2029f23	2535	* @name Register CAN_CTRL2, field TASD[23:19] (RW)
mbed_official	324:406fd2029f23	2536	*
mbed_official	324:406fd2029f23	2537	* This 5-bit field indicates how many CAN bits the Tx arbitration process start
mbed_official	324:406fd2029f23	2538	* point can be delayed from the first bit of CRC field on CAN bus. This field
mbed_official	324:406fd2029f23	2539	* can be written only in Freeze mode because it is blocked by hardware in other
mbed_official	324:406fd2029f23	2540	* modes. This field is useful to optimize the transmit performance based on
mbed_official	324:406fd2029f23	2541	* factors such as: peripheral/serial clock ratio, CAN bit timing and number of MBs.
mbed_official	324:406fd2029f23	2542	* The duration of an arbitration process, in terms of CAN bits, is directly
mbed_official	324:406fd2029f23	2543	* proportional to the number of available MBs and CAN baud rate and inversely
mbed_official	324:406fd2029f23	2544	* proportional to the peripheral clock frequency. The optimal arbitration timing is
mbed_official	324:406fd2029f23	2545	* that in which the last MB is scanned right before the first bit of the
mbed_official	324:406fd2029f23	2546	* Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial
mbed_official	324:406fd2029f23	2547	* clock ratio is high and the CAN baud rate is low then the arbitration can be
mbed_official	324:406fd2029f23	2548	* delayed and vice-versa. If TASD is 0 then the arbitration start is not
mbed_official	324:406fd2029f23	2549	* delayed, thus the CPU has less time to configure a Tx MB for the next arbitration,
mbed_official	324:406fd2029f23	2550	* but more time is reserved for arbitration. On the other hand, if TASD is 24 then
mbed_official	324:406fd2029f23	2551	* the CPU can configure a Tx MB later and less time is reserved for
mbed_official	324:406fd2029f23	2552	* arbitration. If too little time is reserved for arbitration the FlexCAN may be not able
mbed_official	324:406fd2029f23	2553	* to find winner MBs in time to compete with other nodes for the CAN bus. If the
mbed_official	324:406fd2029f23	2554	* arbitration ends too much time before the first bit of Intermission field then
mbed_official	324:406fd2029f23	2555	* there is a chance that the CPU reconfigures some Tx MBs and the winner MB is
mbed_official	324:406fd2029f23	2556	* not the best to be transmitted. The optimal configuration for TASD can be
mbed_official	324:406fd2029f23	2557	* calculated as: TASD = 25 - {f CANCLK * [MAXMB + 3 - (RFEN * 8) - (RFEN * RFFN *
mbed_official	324:406fd2029f23	2558	* 2)] * 2} / {f SYS * [1+(PSEG1+1)+(PSEG2+1)+(PROPSEG+1)] * (PRESDIV+1)} where: f
mbed_official	324:406fd2029f23	2559	* CANCLK is the Protocol Engine (PE) Clock (see section "Protocol Timing"), in
mbed_official	324:406fd2029f23	2560	* Hz f SYS is the peripheral clock, in Hz MAXMB is the value in CTRL1[MAXMB]
mbed_official	324:406fd2029f23	2561	* field RFEN is the value in CTRL1[RFEN] bit RFFN is the value in CTRL2[RFFN] field
mbed_official	324:406fd2029f23	2562	* PSEG1 is the value in CTRL1[PSEG1] field PSEG2 is the value in CTRL1[PSEG2]
mbed_official	324:406fd2029f23	2563	* field PROPSEG is the value in CTRL1[PROPSEG] field PRESDIV is the value in
mbed_official	324:406fd2029f23	2564	* CTRL1[PRESDIV] field See Section "Arbitration process" and Section "Protocol
mbed_official	324:406fd2029f23	2565	* Timing" for more details.
mbed_official	324:406fd2029f23	2566	*/
mbed_official	324:406fd2029f23	2567	/@{/
mbed_official	324:406fd2029f23	2568	#define BP_CAN_CTRL2_TASD (19U) /!< Bit position for CAN_CTRL2_TASD. /
mbed_official	324:406fd2029f23	2569	#define BM_CAN_CTRL2_TASD (0x00F80000U) /!< Bit mask for CAN_CTRL2_TASD. /
mbed_official	324:406fd2029f23	2570	#define BS_CAN_CTRL2_TASD (5U) /!< Bit field size in bits for CAN_CTRL2_TASD. /
mbed_official	324:406fd2029f23	2571
mbed_official	324:406fd2029f23	2572	/! @brief Read current value of the CAN_CTRL2_TASD field. /
mbed_official	324:406fd2029f23	2573	#define BR_CAN_CTRL2_TASD(x) (HW_CAN_CTRL2(x).B.TASD)
mbed_official	324:406fd2029f23	2574
mbed_official	324:406fd2029f23	2575	/! @brief Format value for bitfield CAN_CTRL2_TASD. /
mbed_official	324:406fd2029f23	2576	#define BF_CAN_CTRL2_TASD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_TASD) & BM_CAN_CTRL2_TASD)
mbed_official	324:406fd2029f23	2577
mbed_official	324:406fd2029f23	2578	/! @brief Set the TASD field to a new value. /
mbed_official	324:406fd2029f23	2579	#define BW_CAN_CTRL2_TASD(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_TASD) \| BF_CAN_CTRL2_TASD(v)))
mbed_official	324:406fd2029f23	2580	/@}/
mbed_official	324:406fd2029f23	2581
mbed_official	324:406fd2029f23	2582	/*!
mbed_official	324:406fd2029f23	2583	* @name Register CAN_CTRL2, field RFFN[27:24] (RW)
mbed_official	324:406fd2029f23	2584	*
mbed_official	324:406fd2029f23	2585	* This 4-bit field defines the number of Rx FIFO filters, as shown in the
mbed_official	324:406fd2029f23	2586	* following table. The maximum selectable number of filters is determined by the MCU.
mbed_official	324:406fd2029f23	2587	* This field can only be written in Freeze mode as it is blocked by hardware in
mbed_official	324:406fd2029f23	2588	* other modes. This field must not be programmed with values that make the
mbed_official	324:406fd2029f23	2589	* number of Message Buffers occupied by Rx FIFO and ID Filter exceed the number of
mbed_official	324:406fd2029f23	2590	* Mailboxes present, defined by MCR[MAXMB]. Each group of eight filters occupies
mbed_official	324:406fd2029f23	2591	* a memory space equivalent to two Message Buffers which means that the more
mbed_official	324:406fd2029f23	2592	* filters are implemented the less Mailboxes will be available. Considering that
mbed_official	324:406fd2029f23	2593	* the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN should
mbed_official	324:406fd2029f23	2594	* be programmed with a value correponding to a number of filters not greater
mbed_official	324:406fd2029f23	2595	* than the number of available memory words which can be calculated as follows:
mbed_official	324:406fd2029f23	2596	* (SETUP_MB - 6) * 4 where SETUP_MB is the least between NUMBER_OF_MB and MAXMB.
mbed_official	324:406fd2029f23	2597	* The number of remaining Mailboxes available will be: (SETUP_MB - 8) - (RFFN *
mbed_official	324:406fd2029f23	2598	* 2) If the Number of Rx FIFO Filters programmed through RFFN exceeds the
mbed_official	324:406fd2029f23	2599	* SETUP_MB value (memory space available) the exceeding ones will not be functional.
mbed_official	324:406fd2029f23	2600	* RFFN[3:0] Number of Rx FIFO filters Message Buffers occupied by Rx FIFO and ID
mbed_official	324:406fd2029f23	2601	* Filter Table Remaining Available MailboxesThe number of the last remaining
mbed_official	324:406fd2029f23	2602	* available mailboxes is defined by the least value between the parameter
mbed_official	324:406fd2029f23	2603	* NUMBER_OF_MB minus 1 and the MCR[MAXMB] field. Rx FIFO ID Filter Table Elements Affected
mbed_official	324:406fd2029f23	2604	* by Rx Individual MasksIf Rx Individual Mask Registers are not enabled then
mbed_official	324:406fd2029f23	2605	* all Rx FIFO filters are affected by the Rx FIFO Global Mask. Rx FIFO ID Filter
mbed_official	324:406fd2029f23	2606	* Table Elements Affected by Rx FIFO Global Mask #rxfgmask-note 0x0 8 MB 0-7 MB
mbed_official	324:406fd2029f23	2607	* 8-63 Elements 0-7 none 0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15 0x2
mbed_official	324:406fd2029f23	2608	* 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23 0x3 32 MB 0-13 MB 14-63
mbed_official	324:406fd2029f23	2609	* Elements 0-13 Elements 14-31 0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
mbed_official	324:406fd2029f23	2610	* 0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47 0x6 56 MB 0-19 MB 20-63
mbed_official	324:406fd2029f23	2611	* Elements 0-19 Elements 20-55 0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
mbed_official	324:406fd2029f23	2612	* 0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71 0x9 80 MB 0-25 MB 26-63
mbed_official	324:406fd2029f23	2613	* Elements 0-25 Elements 26-79 0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements
mbed_official	324:406fd2029f23	2614	* 28-87 0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95 0xC 104 MB 0-31 MB
mbed_official	324:406fd2029f23	2615	* 32-63 Elements 0-31 Elements 32-103 0xD 112 MB 0-33 MB 34-63 Elements 0-31
mbed_official	324:406fd2029f23	2616	* Elements 32-111 0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119 0xF 128 MB
mbed_official	324:406fd2029f23	2617	* 0-37 MB 38-63 Elements 0-31 Elements 32-127
mbed_official	324:406fd2029f23	2618	*/
mbed_official	324:406fd2029f23	2619	/@{/
mbed_official	324:406fd2029f23	2620	#define BP_CAN_CTRL2_RFFN (24U) /!< Bit position for CAN_CTRL2_RFFN. /
mbed_official	324:406fd2029f23	2621	#define BM_CAN_CTRL2_RFFN (0x0F000000U) /!< Bit mask for CAN_CTRL2_RFFN. /
mbed_official	324:406fd2029f23	2622	#define BS_CAN_CTRL2_RFFN (4U) /!< Bit field size in bits for CAN_CTRL2_RFFN. /
mbed_official	324:406fd2029f23	2623
mbed_official	324:406fd2029f23	2624	/! @brief Read current value of the CAN_CTRL2_RFFN field. /
mbed_official	324:406fd2029f23	2625	#define BR_CAN_CTRL2_RFFN(x) (HW_CAN_CTRL2(x).B.RFFN)
mbed_official	324:406fd2029f23	2626
mbed_official	324:406fd2029f23	2627	/! @brief Format value for bitfield CAN_CTRL2_RFFN. /
mbed_official	324:406fd2029f23	2628	#define BF_CAN_CTRL2_RFFN(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_RFFN) & BM_CAN_CTRL2_RFFN)
mbed_official	324:406fd2029f23	2629
mbed_official	324:406fd2029f23	2630	/! @brief Set the RFFN field to a new value. /
mbed_official	324:406fd2029f23	2631	#define BW_CAN_CTRL2_RFFN(x, v) (HW_CAN_CTRL2_WR(x, (HW_CAN_CTRL2_RD(x) & ~BM_CAN_CTRL2_RFFN) \| BF_CAN_CTRL2_RFFN(v)))
mbed_official	324:406fd2029f23	2632	/@}/
mbed_official	324:406fd2029f23	2633
mbed_official	324:406fd2029f23	2634	/*!
mbed_official	324:406fd2029f23	2635	* @name Register CAN_CTRL2, field WRMFRZ[28] (RW)
mbed_official	324:406fd2029f23	2636	*
mbed_official	324:406fd2029f23	2637	* Enable unrestricted write access to FlexCAN memory in Freeze mode. This bit
mbed_official	324:406fd2029f23	2638	* can only be written in Freeze mode and has no effect out of Freeze mode.
mbed_official	324:406fd2029f23	2639	*
mbed_official	324:406fd2029f23	2640	* Values:
mbed_official	324:406fd2029f23	2641	* - 0 - Maintain the write access restrictions.
mbed_official	324:406fd2029f23	2642	* - 1 - Enable unrestricted write access to FlexCAN memory.
mbed_official	324:406fd2029f23	2643	*/
mbed_official	324:406fd2029f23	2644	/@{/
mbed_official	324:406fd2029f23	2645	#define BP_CAN_CTRL2_WRMFRZ (28U) /!< Bit position for CAN_CTRL2_WRMFRZ. /
mbed_official	324:406fd2029f23	2646	#define BM_CAN_CTRL2_WRMFRZ (0x10000000U) /!< Bit mask for CAN_CTRL2_WRMFRZ. /
mbed_official	324:406fd2029f23	2647	#define BS_CAN_CTRL2_WRMFRZ (1U) /!< Bit field size in bits for CAN_CTRL2_WRMFRZ. /
mbed_official	324:406fd2029f23	2648
mbed_official	324:406fd2029f23	2649	/! @brief Read current value of the CAN_CTRL2_WRMFRZ field. /
mbed_official	324:406fd2029f23	2650	#define BR_CAN_CTRL2_WRMFRZ(x) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ))
mbed_official	324:406fd2029f23	2651
mbed_official	324:406fd2029f23	2652	/! @brief Format value for bitfield CAN_CTRL2_WRMFRZ. /
mbed_official	324:406fd2029f23	2653	#define BF_CAN_CTRL2_WRMFRZ(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CTRL2_WRMFRZ) & BM_CAN_CTRL2_WRMFRZ)
mbed_official	324:406fd2029f23	2654
mbed_official	324:406fd2029f23	2655	/! @brief Set the WRMFRZ field to a new value. /
mbed_official	324:406fd2029f23	2656	#define BW_CAN_CTRL2_WRMFRZ(x, v) (BITBAND_ACCESS32(HW_CAN_CTRL2_ADDR(x), BP_CAN_CTRL2_WRMFRZ) = (v))
mbed_official	324:406fd2029f23	2657	/@}/
mbed_official	324:406fd2029f23	2658
mbed_official	324:406fd2029f23	2659	/*******************************************************************************
mbed_official	324:406fd2029f23	2660	* HW_CAN_ESR2 - Error and Status 2 register
mbed_official	324:406fd2029f23	2661	******************************************************************************/
mbed_official	324:406fd2029f23	2662
mbed_official	324:406fd2029f23	2663	/*!
mbed_official	324:406fd2029f23	2664	* @brief HW_CAN_ESR2 - Error and Status 2 register (RO)
mbed_official	324:406fd2029f23	2665	*
mbed_official	324:406fd2029f23	2666	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2667	*
mbed_official	324:406fd2029f23	2668	* This register reflects various interrupt flags and some general status.
mbed_official	324:406fd2029f23	2669	*/
mbed_official	324:406fd2029f23	2670	typedef union _hw_can_esr2
mbed_official	324:406fd2029f23	2671	{
mbed_official	324:406fd2029f23	2672	uint32_t U;
mbed_official	324:406fd2029f23	2673	struct _hw_can_esr2_bitfields
mbed_official	324:406fd2029f23	2674	{
mbed_official	324:406fd2029f23	2675	uint32_t RESERVED0 : 13; /!< [12:0] /
mbed_official	324:406fd2029f23	2676	uint32_t IMB : 1; /!< [13] Inactive Mailbox /
mbed_official	324:406fd2029f23	2677	uint32_t VPS : 1; /!< [14] Valid Priority Status /
mbed_official	324:406fd2029f23	2678	uint32_t RESERVED1 : 1; /!< [15] /
mbed_official	324:406fd2029f23	2679	uint32_t LPTM : 7; /!< [22:16] Lowest Priority Tx Mailbox /
mbed_official	324:406fd2029f23	2680	uint32_t RESERVED2 : 9; /!< [31:23] /
mbed_official	324:406fd2029f23	2681	} B;
mbed_official	324:406fd2029f23	2682	} hw_can_esr2_t;
mbed_official	324:406fd2029f23	2683
mbed_official	324:406fd2029f23	2684	/*!
mbed_official	324:406fd2029f23	2685	* @name Constants and macros for entire CAN_ESR2 register
mbed_official	324:406fd2029f23	2686	*/
mbed_official	324:406fd2029f23	2687	/@{/
mbed_official	324:406fd2029f23	2688	#define HW_CAN_ESR2_ADDR(x) ((x) + 0x38U)
mbed_official	324:406fd2029f23	2689
mbed_official	324:406fd2029f23	2690	#define HW_CAN_ESR2(x) ((__I hw_can_esr2_t ) HW_CAN_ESR2_ADDR(x))
mbed_official	324:406fd2029f23	2691	#define HW_CAN_ESR2_RD(x) (HW_CAN_ESR2(x).U)
mbed_official	324:406fd2029f23	2692	/@}/
mbed_official	324:406fd2029f23	2693
mbed_official	324:406fd2029f23	2694	/*
mbed_official	324:406fd2029f23	2695	* Constants & macros for individual CAN_ESR2 bitfields
mbed_official	324:406fd2029f23	2696	*/
mbed_official	324:406fd2029f23	2697
mbed_official	324:406fd2029f23	2698	/*!
mbed_official	324:406fd2029f23	2699	* @name Register CAN_ESR2, field IMB[13] (RO)
mbed_official	324:406fd2029f23	2700	*
mbed_official	324:406fd2029f23	2701	* If ESR2[VPS] is asserted, this bit indicates whether there is any inactive
mbed_official	324:406fd2029f23	2702	* Mailbox (CODE field is either 0b1000 or 0b0000). This bit is asserted in the
mbed_official	324:406fd2029f23	2703	* following cases: During arbitration, if an LPTM is found and it is inactive. If
mbed_official	324:406fd2029f23	2704	* IMB is not asserted and a frame is transmitted successfully. This bit is
mbed_official	324:406fd2029f23	2705	* cleared in all start of arbitration (see Section "Arbitration process"). LPTM
mbed_official	324:406fd2029f23	2706	* mechanism have the following behavior: if an MB is successfully transmitted and
mbed_official	324:406fd2029f23	2707	* ESR2[IMB]=0 (no inactive Mailbox), then ESR2[VPS] and ESR2[IMB] are asserted and
mbed_official	324:406fd2029f23	2708	* the index related to the MB just transmitted is loaded into ESR2[LPTM].
mbed_official	324:406fd2029f23	2709	*
mbed_official	324:406fd2029f23	2710	* Values:
mbed_official	324:406fd2029f23	2711	* - 0 - If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
mbed_official	324:406fd2029f23	2712	* - 1 - If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM
mbed_official	324:406fd2029f23	2713	* content is the number of the first one.
mbed_official	324:406fd2029f23	2714	*/
mbed_official	324:406fd2029f23	2715	/@{/
mbed_official	324:406fd2029f23	2716	#define BP_CAN_ESR2_IMB (13U) /!< Bit position for CAN_ESR2_IMB. /
mbed_official	324:406fd2029f23	2717	#define BM_CAN_ESR2_IMB (0x00002000U) /!< Bit mask for CAN_ESR2_IMB. /
mbed_official	324:406fd2029f23	2718	#define BS_CAN_ESR2_IMB (1U) /!< Bit field size in bits for CAN_ESR2_IMB. /
mbed_official	324:406fd2029f23	2719
mbed_official	324:406fd2029f23	2720	/! @brief Read current value of the CAN_ESR2_IMB field. /
mbed_official	324:406fd2029f23	2721	#define BR_CAN_ESR2_IMB(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_IMB))
mbed_official	324:406fd2029f23	2722	/@}/
mbed_official	324:406fd2029f23	2723
mbed_official	324:406fd2029f23	2724	/*!
mbed_official	324:406fd2029f23	2725	* @name Register CAN_ESR2, field VPS[14] (RO)
mbed_official	324:406fd2029f23	2726	*
mbed_official	324:406fd2029f23	2727	* This bit indicates whether IMB and LPTM contents are currently valid or not.
mbed_official	324:406fd2029f23	2728	* VPS is asserted upon every complete Tx arbitration process unless the CPU
mbed_official	324:406fd2029f23	2729	* writes to Control and Status word of a Mailbox that has already been scanned, that
mbed_official	324:406fd2029f23	2730	* is, it is behind Tx Arbitration Pointer, during the Tx arbitration process.
mbed_official	324:406fd2029f23	2731	* If there is no inactive Mailbox and only one Tx Mailbox that is being
mbed_official	324:406fd2029f23	2732	* transmitted then VPS is not asserted. VPS is negated upon the start of every Tx
mbed_official	324:406fd2029f23	2733	* arbitration process or upon a write to Control and Status word of any Mailbox.
mbed_official	324:406fd2029f23	2734	* ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
mbed_official	324:406fd2029f23	2735	* blocked by abort mechanism. When MCR[AEN] is asserted, the abort code write
mbed_official	324:406fd2029f23	2736	* in C/S of a MB that is being transmitted (pending abort), or any write attempt
mbed_official	324:406fd2029f23	2737	* into a Tx MB with IFLAG set is blocked.
mbed_official	324:406fd2029f23	2738	*
mbed_official	324:406fd2029f23	2739	* Values:
mbed_official	324:406fd2029f23	2740	* - 0 - Contents of IMB and LPTM are invalid.
mbed_official	324:406fd2029f23	2741	* - 1 - Contents of IMB and LPTM are valid.
mbed_official	324:406fd2029f23	2742	*/
mbed_official	324:406fd2029f23	2743	/@{/
mbed_official	324:406fd2029f23	2744	#define BP_CAN_ESR2_VPS (14U) /!< Bit position for CAN_ESR2_VPS. /
mbed_official	324:406fd2029f23	2745	#define BM_CAN_ESR2_VPS (0x00004000U) /!< Bit mask for CAN_ESR2_VPS. /
mbed_official	324:406fd2029f23	2746	#define BS_CAN_ESR2_VPS (1U) /!< Bit field size in bits for CAN_ESR2_VPS. /
mbed_official	324:406fd2029f23	2747
mbed_official	324:406fd2029f23	2748	/! @brief Read current value of the CAN_ESR2_VPS field. /
mbed_official	324:406fd2029f23	2749	#define BR_CAN_ESR2_VPS(x) (BITBAND_ACCESS32(HW_CAN_ESR2_ADDR(x), BP_CAN_ESR2_VPS))
mbed_official	324:406fd2029f23	2750	/@}/
mbed_official	324:406fd2029f23	2751
mbed_official	324:406fd2029f23	2752	/*!
mbed_official	324:406fd2029f23	2753	* @name Register CAN_ESR2, field LPTM[22:16] (RO)
mbed_official	324:406fd2029f23	2754	*
mbed_official	324:406fd2029f23	2755	* If ESR2[VPS] is asserted, this field indicates the lowest number inactive
mbed_official	324:406fd2029f23	2756	* Mailbox (see the IMB bit description). If there is no inactive Mailbox then the
mbed_official	324:406fd2029f23	2757	* Mailbox indicated depends on CTRL1[LBUF] bit value. If CTRL1[LBUF] bit is
mbed_official	324:406fd2029f23	2758	* negated then the Mailbox indicated is the one that has the greatest arbitration
mbed_official	324:406fd2029f23	2759	* value (see the "Highest priority Mailbox first" section). If CTRL1[LBUF] bit is
mbed_official	324:406fd2029f23	2760	* asserted then the Mailbox indicated is the highest number active Tx Mailbox. If
mbed_official	324:406fd2029f23	2761	* a Tx Mailbox is being transmitted it is not considered in LPTM calculation.
mbed_official	324:406fd2029f23	2762	* If ESR2[IMB] is not asserted and a frame is transmitted successfully, LPTM is
mbed_official	324:406fd2029f23	2763	* updated with its Mailbox number.
mbed_official	324:406fd2029f23	2764	*/
mbed_official	324:406fd2029f23	2765	/@{/
mbed_official	324:406fd2029f23	2766	#define BP_CAN_ESR2_LPTM (16U) /!< Bit position for CAN_ESR2_LPTM. /
mbed_official	324:406fd2029f23	2767	#define BM_CAN_ESR2_LPTM (0x007F0000U) /!< Bit mask for CAN_ESR2_LPTM. /
mbed_official	324:406fd2029f23	2768	#define BS_CAN_ESR2_LPTM (7U) /!< Bit field size in bits for CAN_ESR2_LPTM. /
mbed_official	324:406fd2029f23	2769
mbed_official	324:406fd2029f23	2770	/! @brief Read current value of the CAN_ESR2_LPTM field. /
mbed_official	324:406fd2029f23	2771	#define BR_CAN_ESR2_LPTM(x) (HW_CAN_ESR2(x).B.LPTM)
mbed_official	324:406fd2029f23	2772	/@}/
mbed_official	324:406fd2029f23	2773
mbed_official	324:406fd2029f23	2774	/*******************************************************************************
mbed_official	324:406fd2029f23	2775	* HW_CAN_CRCR - CRC Register
mbed_official	324:406fd2029f23	2776	******************************************************************************/
mbed_official	324:406fd2029f23	2777
mbed_official	324:406fd2029f23	2778	/*!
mbed_official	324:406fd2029f23	2779	* @brief HW_CAN_CRCR - CRC Register (RO)
mbed_official	324:406fd2029f23	2780	*
mbed_official	324:406fd2029f23	2781	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2782	*
mbed_official	324:406fd2029f23	2783	* This register provides information about the CRC of transmitted messages.
mbed_official	324:406fd2029f23	2784	*/
mbed_official	324:406fd2029f23	2785	typedef union _hw_can_crcr
mbed_official	324:406fd2029f23	2786	{
mbed_official	324:406fd2029f23	2787	uint32_t U;
mbed_official	324:406fd2029f23	2788	struct _hw_can_crcr_bitfields
mbed_official	324:406fd2029f23	2789	{
mbed_official	324:406fd2029f23	2790	uint32_t TXCRC : 15; /!< [14:0] CRC Transmitted /
mbed_official	324:406fd2029f23	2791	uint32_t RESERVED0 : 1; /!< [15] /
mbed_official	324:406fd2029f23	2792	uint32_t MBCRC : 7; /!< [22:16] CRC Mailbox /
mbed_official	324:406fd2029f23	2793	uint32_t RESERVED1 : 9; /!< [31:23] /
mbed_official	324:406fd2029f23	2794	} B;
mbed_official	324:406fd2029f23	2795	} hw_can_crcr_t;
mbed_official	324:406fd2029f23	2796
mbed_official	324:406fd2029f23	2797	/*!
mbed_official	324:406fd2029f23	2798	* @name Constants and macros for entire CAN_CRCR register
mbed_official	324:406fd2029f23	2799	*/
mbed_official	324:406fd2029f23	2800	/@{/
mbed_official	324:406fd2029f23	2801	#define HW_CAN_CRCR_ADDR(x) ((x) + 0x44U)
mbed_official	324:406fd2029f23	2802
mbed_official	324:406fd2029f23	2803	#define HW_CAN_CRCR(x) ((__I hw_can_crcr_t ) HW_CAN_CRCR_ADDR(x))
mbed_official	324:406fd2029f23	2804	#define HW_CAN_CRCR_RD(x) (HW_CAN_CRCR(x).U)
mbed_official	324:406fd2029f23	2805	/@}/
mbed_official	324:406fd2029f23	2806
mbed_official	324:406fd2029f23	2807	/*
mbed_official	324:406fd2029f23	2808	* Constants & macros for individual CAN_CRCR bitfields
mbed_official	324:406fd2029f23	2809	*/
mbed_official	324:406fd2029f23	2810
mbed_official	324:406fd2029f23	2811	/*!
mbed_official	324:406fd2029f23	2812	* @name Register CAN_CRCR, field TXCRC[14:0] (RO)
mbed_official	324:406fd2029f23	2813	*
mbed_official	324:406fd2029f23	2814	* This field indicates the CRC value of the last message transmitted. This
mbed_official	324:406fd2029f23	2815	* field is updated at the same time the Tx Interrupt Flag is asserted.
mbed_official	324:406fd2029f23	2816	*/
mbed_official	324:406fd2029f23	2817	/@{/
mbed_official	324:406fd2029f23	2818	#define BP_CAN_CRCR_TXCRC (0U) /!< Bit position for CAN_CRCR_TXCRC. /
mbed_official	324:406fd2029f23	2819	#define BM_CAN_CRCR_TXCRC (0x00007FFFU) /!< Bit mask for CAN_CRCR_TXCRC. /
mbed_official	324:406fd2029f23	2820	#define BS_CAN_CRCR_TXCRC (15U) /!< Bit field size in bits for CAN_CRCR_TXCRC. /
mbed_official	324:406fd2029f23	2821
mbed_official	324:406fd2029f23	2822	/! @brief Read current value of the CAN_CRCR_TXCRC field. /
mbed_official	324:406fd2029f23	2823	#define BR_CAN_CRCR_TXCRC(x) (HW_CAN_CRCR(x).B.TXCRC)
mbed_official	324:406fd2029f23	2824	/@}/
mbed_official	324:406fd2029f23	2825
mbed_official	324:406fd2029f23	2826	/*!
mbed_official	324:406fd2029f23	2827	* @name Register CAN_CRCR, field MBCRC[22:16] (RO)
mbed_official	324:406fd2029f23	2828	*
mbed_official	324:406fd2029f23	2829	* This field indicates the number of the Mailbox corresponding to the value in
mbed_official	324:406fd2029f23	2830	* TXCRC field.
mbed_official	324:406fd2029f23	2831	*/
mbed_official	324:406fd2029f23	2832	/@{/
mbed_official	324:406fd2029f23	2833	#define BP_CAN_CRCR_MBCRC (16U) /!< Bit position for CAN_CRCR_MBCRC. /
mbed_official	324:406fd2029f23	2834	#define BM_CAN_CRCR_MBCRC (0x007F0000U) /!< Bit mask for CAN_CRCR_MBCRC. /
mbed_official	324:406fd2029f23	2835	#define BS_CAN_CRCR_MBCRC (7U) /!< Bit field size in bits for CAN_CRCR_MBCRC. /
mbed_official	324:406fd2029f23	2836
mbed_official	324:406fd2029f23	2837	/! @brief Read current value of the CAN_CRCR_MBCRC field. /
mbed_official	324:406fd2029f23	2838	#define BR_CAN_CRCR_MBCRC(x) (HW_CAN_CRCR(x).B.MBCRC)
mbed_official	324:406fd2029f23	2839	/@}/
mbed_official	324:406fd2029f23	2840
mbed_official	324:406fd2029f23	2841	/*******************************************************************************
mbed_official	324:406fd2029f23	2842	* HW_CAN_RXFGMASK - Rx FIFO Global Mask register
mbed_official	324:406fd2029f23	2843	******************************************************************************/
mbed_official	324:406fd2029f23	2844
mbed_official	324:406fd2029f23	2845	/*!
mbed_official	324:406fd2029f23	2846	* @brief HW_CAN_RXFGMASK - Rx FIFO Global Mask register (RW)
mbed_official	324:406fd2029f23	2847	*
mbed_official	324:406fd2029f23	2848	* Reset value: 0xFFFFFFFFU
mbed_official	324:406fd2029f23	2849	*
mbed_official	324:406fd2029f23	2850	* This register is located in RAM. If Rx FIFO is enabled RXFGMASK is used to
mbed_official	324:406fd2029f23	2851	* mask the Rx FIFO ID Filter Table elements that do not have a corresponding RXIMR
mbed_official	324:406fd2029f23	2852	* according to CTRL2[RFFN] field setting. This register can only be written in
mbed_official	324:406fd2029f23	2853	* Freeze mode as it is blocked by hardware in other modes.
mbed_official	324:406fd2029f23	2854	*/
mbed_official	324:406fd2029f23	2855	typedef union _hw_can_rxfgmask
mbed_official	324:406fd2029f23	2856	{
mbed_official	324:406fd2029f23	2857	uint32_t U;
mbed_official	324:406fd2029f23	2858	struct _hw_can_rxfgmask_bitfields
mbed_official	324:406fd2029f23	2859	{
mbed_official	324:406fd2029f23	2860	uint32_t FGM : 32; /!< [31:0] Rx FIFO Global Mask Bits /
mbed_official	324:406fd2029f23	2861	} B;
mbed_official	324:406fd2029f23	2862	} hw_can_rxfgmask_t;
mbed_official	324:406fd2029f23	2863
mbed_official	324:406fd2029f23	2864	/*!
mbed_official	324:406fd2029f23	2865	* @name Constants and macros for entire CAN_RXFGMASK register
mbed_official	324:406fd2029f23	2866	*/
mbed_official	324:406fd2029f23	2867	/@{/
mbed_official	324:406fd2029f23	2868	#define HW_CAN_RXFGMASK_ADDR(x) ((x) + 0x48U)
mbed_official	324:406fd2029f23	2869
mbed_official	324:406fd2029f23	2870	#define HW_CAN_RXFGMASK(x) ((__IO hw_can_rxfgmask_t ) HW_CAN_RXFGMASK_ADDR(x))
mbed_official	324:406fd2029f23	2871	#define HW_CAN_RXFGMASK_RD(x) (HW_CAN_RXFGMASK(x).U)
mbed_official	324:406fd2029f23	2872	#define HW_CAN_RXFGMASK_WR(x, v) (HW_CAN_RXFGMASK(x).U = (v))
mbed_official	324:406fd2029f23	2873	#define HW_CAN_RXFGMASK_SET(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2874	#define HW_CAN_RXFGMASK_CLR(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2875	#define HW_CAN_RXFGMASK_TOG(x, v) (HW_CAN_RXFGMASK_WR(x, HW_CAN_RXFGMASK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2876	/@}/
mbed_official	324:406fd2029f23	2877
mbed_official	324:406fd2029f23	2878	/*
mbed_official	324:406fd2029f23	2879	* Constants & macros for individual CAN_RXFGMASK bitfields
mbed_official	324:406fd2029f23	2880	*/
mbed_official	324:406fd2029f23	2881
mbed_official	324:406fd2029f23	2882	/*!
mbed_official	324:406fd2029f23	2883	* @name Register CAN_RXFGMASK, field FGM[31:0] (RW)
mbed_official	324:406fd2029f23	2884	*
mbed_official	324:406fd2029f23	2885	* These bits mask the ID Filter Table elements bits in a perfect alignment. The
mbed_official	324:406fd2029f23	2886	* following table shows how the FGM bits correspond to each IDAF field. Rx FIFO
mbed_official	324:406fd2029f23	2887	* ID Filter Table Elements Format (MCR[IDAM]) Identifier Acceptance Filter
mbed_official	324:406fd2029f23	2888	* Fields RTR IDE RXIDA RXIDB If MCR[IDAM] field is equivalent to the format B only
mbed_official	324:406fd2029f23	2889	* the fourteen most significant bits of the Identifier of the incoming frame are
mbed_official	324:406fd2029f23	2890	* compared with the Rx FIFO filter. RXIDC If MCR[IDAM] field is equivalent to
mbed_official	324:406fd2029f23	2891	* the format C only the eight most significant bits of the Identifier of the
mbed_official	324:406fd2029f23	2892	* incoming frame are compared with the Rx FIFO filter. Reserved A FGM[31] FGM[30]
mbed_official	324:406fd2029f23	2893	* FGM[29:1] - - FGM[0] B FGM[31], FGM[15] FGM[30], FGM[14] - FGM[29:16], FGM[13:0]
mbed_official	324:406fd2029f23	2894	* - C - - - FGM[31:24], FGM[23:16], FGM[15:8], FGM[7:0]
mbed_official	324:406fd2029f23	2895	*
mbed_official	324:406fd2029f23	2896	* Values:
mbed_official	324:406fd2029f23	2897	* - 0 - The corresponding bit in the filter is "don't care."
mbed_official	324:406fd2029f23	2898	* - 1 - The corresponding bit in the filter is checked.
mbed_official	324:406fd2029f23	2899	*/
mbed_official	324:406fd2029f23	2900	/@{/
mbed_official	324:406fd2029f23	2901	#define BP_CAN_RXFGMASK_FGM (0U) /!< Bit position for CAN_RXFGMASK_FGM. /
mbed_official	324:406fd2029f23	2902	#define BM_CAN_RXFGMASK_FGM (0xFFFFFFFFU) /!< Bit mask for CAN_RXFGMASK_FGM. /
mbed_official	324:406fd2029f23	2903	#define BS_CAN_RXFGMASK_FGM (32U) /!< Bit field size in bits for CAN_RXFGMASK_FGM. /
mbed_official	324:406fd2029f23	2904
mbed_official	324:406fd2029f23	2905	/! @brief Read current value of the CAN_RXFGMASK_FGM field. /
mbed_official	324:406fd2029f23	2906	#define BR_CAN_RXFGMASK_FGM(x) (HW_CAN_RXFGMASK(x).U)
mbed_official	324:406fd2029f23	2907
mbed_official	324:406fd2029f23	2908	/! @brief Format value for bitfield CAN_RXFGMASK_FGM. /
mbed_official	324:406fd2029f23	2909	#define BF_CAN_RXFGMASK_FGM(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXFGMASK_FGM) & BM_CAN_RXFGMASK_FGM)
mbed_official	324:406fd2029f23	2910
mbed_official	324:406fd2029f23	2911	/! @brief Set the FGM field to a new value. /
mbed_official	324:406fd2029f23	2912	#define BW_CAN_RXFGMASK_FGM(x, v) (HW_CAN_RXFGMASK_WR(x, v))
mbed_official	324:406fd2029f23	2913	/@}/
mbed_official	324:406fd2029f23	2914
mbed_official	324:406fd2029f23	2915	/*******************************************************************************
mbed_official	324:406fd2029f23	2916	* HW_CAN_RXFIR - Rx FIFO Information Register
mbed_official	324:406fd2029f23	2917	******************************************************************************/
mbed_official	324:406fd2029f23	2918
mbed_official	324:406fd2029f23	2919	/*!
mbed_official	324:406fd2029f23	2920	* @brief HW_CAN_RXFIR - Rx FIFO Information Register (RO)
mbed_official	324:406fd2029f23	2921	*
mbed_official	324:406fd2029f23	2922	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2923	*
mbed_official	324:406fd2029f23	2924	* RXFIR provides information on Rx FIFO. This register is the port through
mbed_official	324:406fd2029f23	2925	* which the CPU accesses the output of the RXFIR FIFO located in RAM. The RXFIR FIFO
mbed_official	324:406fd2029f23	2926	* is written by the FlexCAN whenever a new message is moved into the Rx FIFO as
mbed_official	324:406fd2029f23	2927	* well as its output is updated whenever the output of the Rx FIFO is updated
mbed_official	324:406fd2029f23	2928	* with the next message. See Section "Rx FIFO" for instructions on reading this
mbed_official	324:406fd2029f23	2929	* register.
mbed_official	324:406fd2029f23	2930	*/
mbed_official	324:406fd2029f23	2931	typedef union _hw_can_rxfir
mbed_official	324:406fd2029f23	2932	{
mbed_official	324:406fd2029f23	2933	uint32_t U;
mbed_official	324:406fd2029f23	2934	struct _hw_can_rxfir_bitfields
mbed_official	324:406fd2029f23	2935	{
mbed_official	324:406fd2029f23	2936	uint32_t IDHIT : 9; /*!< [8:0] Identifier Acceptance Filter Hit
mbed_official	324:406fd2029f23	2937	* Indicator */
mbed_official	324:406fd2029f23	2938	uint32_t RESERVED0 : 23; /!< [31:9] /
mbed_official	324:406fd2029f23	2939	} B;
mbed_official	324:406fd2029f23	2940	} hw_can_rxfir_t;
mbed_official	324:406fd2029f23	2941
mbed_official	324:406fd2029f23	2942	/*!
mbed_official	324:406fd2029f23	2943	* @name Constants and macros for entire CAN_RXFIR register
mbed_official	324:406fd2029f23	2944	*/
mbed_official	324:406fd2029f23	2945	/@{/
mbed_official	324:406fd2029f23	2946	#define HW_CAN_RXFIR_ADDR(x) ((x) + 0x4CU)
mbed_official	324:406fd2029f23	2947
mbed_official	324:406fd2029f23	2948	#define HW_CAN_RXFIR(x) ((__I hw_can_rxfir_t ) HW_CAN_RXFIR_ADDR(x))
mbed_official	324:406fd2029f23	2949	#define HW_CAN_RXFIR_RD(x) (HW_CAN_RXFIR(x).U)
mbed_official	324:406fd2029f23	2950	/@}/
mbed_official	324:406fd2029f23	2951
mbed_official	324:406fd2029f23	2952	/*
mbed_official	324:406fd2029f23	2953	* Constants & macros for individual CAN_RXFIR bitfields
mbed_official	324:406fd2029f23	2954	*/
mbed_official	324:406fd2029f23	2955
mbed_official	324:406fd2029f23	2956	/*!
mbed_official	324:406fd2029f23	2957	* @name Register CAN_RXFIR, field IDHIT[8:0] (RO)
mbed_official	324:406fd2029f23	2958	*
mbed_official	324:406fd2029f23	2959	* This field indicates which Identifier Acceptance Filter was hit by the
mbed_official	324:406fd2029f23	2960	* received message that is in the output of the Rx FIFO. If multiple filters match the
mbed_official	324:406fd2029f23	2961	* incoming message ID then the first matching IDAF found (lowest number) by the
mbed_official	324:406fd2029f23	2962	* matching process is indicated. This field is valid only while the
mbed_official	324:406fd2029f23	2963	* IFLAG[BUF5I] is asserted.
mbed_official	324:406fd2029f23	2964	*/
mbed_official	324:406fd2029f23	2965	/@{/
mbed_official	324:406fd2029f23	2966	#define BP_CAN_RXFIR_IDHIT (0U) /!< Bit position for CAN_RXFIR_IDHIT. /
mbed_official	324:406fd2029f23	2967	#define BM_CAN_RXFIR_IDHIT (0x000001FFU) /!< Bit mask for CAN_RXFIR_IDHIT. /
mbed_official	324:406fd2029f23	2968	#define BS_CAN_RXFIR_IDHIT (9U) /!< Bit field size in bits for CAN_RXFIR_IDHIT. /
mbed_official	324:406fd2029f23	2969
mbed_official	324:406fd2029f23	2970	/! @brief Read current value of the CAN_RXFIR_IDHIT field. /
mbed_official	324:406fd2029f23	2971	#define BR_CAN_RXFIR_IDHIT(x) (HW_CAN_RXFIR(x).B.IDHIT)
mbed_official	324:406fd2029f23	2972	/@}/
mbed_official	324:406fd2029f23	2973
mbed_official	324:406fd2029f23	2974	/*******************************************************************************
mbed_official	324:406fd2029f23	2975	* HW_CAN_CSn - Message Buffer 0 CS Register
mbed_official	324:406fd2029f23	2976	******************************************************************************/
mbed_official	324:406fd2029f23	2977
mbed_official	324:406fd2029f23	2978	/*!
mbed_official	324:406fd2029f23	2979	* @brief HW_CAN_CSn - Message Buffer 0 CS Register (RW)
mbed_official	324:406fd2029f23	2980	*
mbed_official	324:406fd2029f23	2981	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2982	*/
mbed_official	324:406fd2029f23	2983	typedef union _hw_can_csn
mbed_official	324:406fd2029f23	2984	{
mbed_official	324:406fd2029f23	2985	uint32_t U;
mbed_official	324:406fd2029f23	2986	struct _hw_can_csn_bitfields
mbed_official	324:406fd2029f23	2987	{
mbed_official	324:406fd2029f23	2988	uint32_t TIME_STAMP : 16; /*!< [15:0] Free-Running Counter Time
mbed_official	324:406fd2029f23	2989	* stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx
mbed_official	324:406fd2029f23	2990	* and Rx frames at the time when the beginning of the Identifier field
mbed_official	324:406fd2029f23	2991	* appears on the CAN bus. */
mbed_official	324:406fd2029f23	2992	uint32_t DLC : 4; /*!< [19:16] Length of the data to be
mbed_official	324:406fd2029f23	2993	* stored/transmitted. */
mbed_official	324:406fd2029f23	2994	uint32_t RTR : 1; /*!< [20] Remote Transmission Request. One/zero for
mbed_official	324:406fd2029f23	2995	* remote/data frame. */
mbed_official	324:406fd2029f23	2996	uint32_t IDE : 1; /*!< [21] ID Extended. One/zero for
mbed_official	324:406fd2029f23	2997	* extended/standard format frame. */
mbed_official	324:406fd2029f23	2998	uint32_t SRR : 1; /*!< [22] Substitute Remote Request. Contains a
mbed_official	324:406fd2029f23	2999	* fixed recessive bit. */
mbed_official	324:406fd2029f23	3000	uint32_t RESERVED0 : 1; /!< [23] Reserved /
mbed_official	324:406fd2029f23	3001	uint32_t CODE : 4; /!< [27:24] Reserved /
mbed_official	324:406fd2029f23	3002	uint32_t RESERVED1 : 4; /!< [31:28] Reserved /
mbed_official	324:406fd2029f23	3003	} B;
mbed_official	324:406fd2029f23	3004	} hw_can_csn_t;
mbed_official	324:406fd2029f23	3005
mbed_official	324:406fd2029f23	3006	/*!
mbed_official	324:406fd2029f23	3007	* @name Constants and macros for entire CAN_CSn register
mbed_official	324:406fd2029f23	3008	*/
mbed_official	324:406fd2029f23	3009	/@{/
mbed_official	324:406fd2029f23	3010	#define HW_CAN_CSn_COUNT (16U)
mbed_official	324:406fd2029f23	3011
mbed_official	324:406fd2029f23	3012	#define HW_CAN_CSn_ADDR(x, n) ((x) + 0x80U + (0x10U * (n)))
mbed_official	324:406fd2029f23	3013
mbed_official	324:406fd2029f23	3014	#define HW_CAN_CSn(x, n) ((__IO hw_can_csn_t ) HW_CAN_CSn_ADDR(x, n))
mbed_official	324:406fd2029f23	3015	#define HW_CAN_CSn_RD(x, n) (HW_CAN_CSn(x, n).U)
mbed_official	324:406fd2029f23	3016	#define HW_CAN_CSn_WR(x, n, v) (HW_CAN_CSn(x, n).U = (v))
mbed_official	324:406fd2029f23	3017	#define HW_CAN_CSn_SET(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	3018	#define HW_CAN_CSn_CLR(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	3019	#define HW_CAN_CSn_TOG(x, n, v) (HW_CAN_CSn_WR(x, n, HW_CAN_CSn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	3020	/@}/
mbed_official	324:406fd2029f23	3021
mbed_official	324:406fd2029f23	3022	/*
mbed_official	324:406fd2029f23	3023	* Constants & macros for individual CAN_CSn bitfields
mbed_official	324:406fd2029f23	3024	*/
mbed_official	324:406fd2029f23	3025
mbed_official	324:406fd2029f23	3026	/*!
mbed_official	324:406fd2029f23	3027	* @name Register CAN_CSn, field TIME_STAMP[15:0] (RW)
mbed_official	324:406fd2029f23	3028	*/
mbed_official	324:406fd2029f23	3029	/@{/
mbed_official	324:406fd2029f23	3030	#define BP_CAN_CSn_TIME_STAMP (0U) /!< Bit position for CAN_CSn_TIME_STAMP. /
mbed_official	324:406fd2029f23	3031	#define BM_CAN_CSn_TIME_STAMP (0x0000FFFFU) /!< Bit mask for CAN_CSn_TIME_STAMP. /
mbed_official	324:406fd2029f23	3032	#define BS_CAN_CSn_TIME_STAMP (16U) /!< Bit field size in bits for CAN_CSn_TIME_STAMP. /
mbed_official	324:406fd2029f23	3033
mbed_official	324:406fd2029f23	3034	/! @brief Read current value of the CAN_CSn_TIME_STAMP field. /
mbed_official	324:406fd2029f23	3035	#define BR_CAN_CSn_TIME_STAMP(x, n) (HW_CAN_CSn(x, n).B.TIME_STAMP)
mbed_official	324:406fd2029f23	3036
mbed_official	324:406fd2029f23	3037	/! @brief Format value for bitfield CAN_CSn_TIME_STAMP. /
mbed_official	324:406fd2029f23	3038	#define BF_CAN_CSn_TIME_STAMP(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_TIME_STAMP) & BM_CAN_CSn_TIME_STAMP)
mbed_official	324:406fd2029f23	3039
mbed_official	324:406fd2029f23	3040	/! @brief Set the TIME_STAMP field to a new value. /
mbed_official	324:406fd2029f23	3041	#define BW_CAN_CSn_TIME_STAMP(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_TIME_STAMP) \| BF_CAN_CSn_TIME_STAMP(v)))
mbed_official	324:406fd2029f23	3042	/@}/
mbed_official	324:406fd2029f23	3043
mbed_official	324:406fd2029f23	3044	/*!
mbed_official	324:406fd2029f23	3045	* @name Register CAN_CSn, field DLC[19:16] (RW)
mbed_official	324:406fd2029f23	3046	*/
mbed_official	324:406fd2029f23	3047	/@{/
mbed_official	324:406fd2029f23	3048	#define BP_CAN_CSn_DLC (16U) /!< Bit position for CAN_CSn_DLC. /
mbed_official	324:406fd2029f23	3049	#define BM_CAN_CSn_DLC (0x000F0000U) /!< Bit mask for CAN_CSn_DLC. /
mbed_official	324:406fd2029f23	3050	#define BS_CAN_CSn_DLC (4U) /!< Bit field size in bits for CAN_CSn_DLC. /
mbed_official	324:406fd2029f23	3051
mbed_official	324:406fd2029f23	3052	/! @brief Read current value of the CAN_CSn_DLC field. /
mbed_official	324:406fd2029f23	3053	#define BR_CAN_CSn_DLC(x, n) (HW_CAN_CSn(x, n).B.DLC)
mbed_official	324:406fd2029f23	3054
mbed_official	324:406fd2029f23	3055	/! @brief Format value for bitfield CAN_CSn_DLC. /
mbed_official	324:406fd2029f23	3056	#define BF_CAN_CSn_DLC(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_DLC) & BM_CAN_CSn_DLC)
mbed_official	324:406fd2029f23	3057
mbed_official	324:406fd2029f23	3058	/! @brief Set the DLC field to a new value. /
mbed_official	324:406fd2029f23	3059	#define BW_CAN_CSn_DLC(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_DLC) \| BF_CAN_CSn_DLC(v)))
mbed_official	324:406fd2029f23	3060	/@}/
mbed_official	324:406fd2029f23	3061
mbed_official	324:406fd2029f23	3062	/*!
mbed_official	324:406fd2029f23	3063	* @name Register CAN_CSn, field RTR[20] (RW)
mbed_official	324:406fd2029f23	3064	*/
mbed_official	324:406fd2029f23	3065	/@{/
mbed_official	324:406fd2029f23	3066	#define BP_CAN_CSn_RTR (20U) /!< Bit position for CAN_CSn_RTR. /
mbed_official	324:406fd2029f23	3067	#define BM_CAN_CSn_RTR (0x00100000U) /!< Bit mask for CAN_CSn_RTR. /
mbed_official	324:406fd2029f23	3068	#define BS_CAN_CSn_RTR (1U) /!< Bit field size in bits for CAN_CSn_RTR. /
mbed_official	324:406fd2029f23	3069
mbed_official	324:406fd2029f23	3070	/! @brief Read current value of the CAN_CSn_RTR field. /
mbed_official	324:406fd2029f23	3071	#define BR_CAN_CSn_RTR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR))
mbed_official	324:406fd2029f23	3072
mbed_official	324:406fd2029f23	3073	/! @brief Format value for bitfield CAN_CSn_RTR. /
mbed_official	324:406fd2029f23	3074	#define BF_CAN_CSn_RTR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_RTR) & BM_CAN_CSn_RTR)
mbed_official	324:406fd2029f23	3075
mbed_official	324:406fd2029f23	3076	/! @brief Set the RTR field to a new value. /
mbed_official	324:406fd2029f23	3077	#define BW_CAN_CSn_RTR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_RTR) = (v))
mbed_official	324:406fd2029f23	3078	/@}/
mbed_official	324:406fd2029f23	3079
mbed_official	324:406fd2029f23	3080	/*!
mbed_official	324:406fd2029f23	3081	* @name Register CAN_CSn, field IDE[21] (RW)
mbed_official	324:406fd2029f23	3082	*/
mbed_official	324:406fd2029f23	3083	/@{/
mbed_official	324:406fd2029f23	3084	#define BP_CAN_CSn_IDE (21U) /!< Bit position for CAN_CSn_IDE. /
mbed_official	324:406fd2029f23	3085	#define BM_CAN_CSn_IDE (0x00200000U) /!< Bit mask for CAN_CSn_IDE. /
mbed_official	324:406fd2029f23	3086	#define BS_CAN_CSn_IDE (1U) /!< Bit field size in bits for CAN_CSn_IDE. /
mbed_official	324:406fd2029f23	3087
mbed_official	324:406fd2029f23	3088	/! @brief Read current value of the CAN_CSn_IDE field. /
mbed_official	324:406fd2029f23	3089	#define BR_CAN_CSn_IDE(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE))
mbed_official	324:406fd2029f23	3090
mbed_official	324:406fd2029f23	3091	/! @brief Format value for bitfield CAN_CSn_IDE. /
mbed_official	324:406fd2029f23	3092	#define BF_CAN_CSn_IDE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_IDE) & BM_CAN_CSn_IDE)
mbed_official	324:406fd2029f23	3093
mbed_official	324:406fd2029f23	3094	/! @brief Set the IDE field to a new value. /
mbed_official	324:406fd2029f23	3095	#define BW_CAN_CSn_IDE(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_IDE) = (v))
mbed_official	324:406fd2029f23	3096	/@}/
mbed_official	324:406fd2029f23	3097
mbed_official	324:406fd2029f23	3098	/*!
mbed_official	324:406fd2029f23	3099	* @name Register CAN_CSn, field SRR[22] (RW)
mbed_official	324:406fd2029f23	3100	*/
mbed_official	324:406fd2029f23	3101	/@{/
mbed_official	324:406fd2029f23	3102	#define BP_CAN_CSn_SRR (22U) /!< Bit position for CAN_CSn_SRR. /
mbed_official	324:406fd2029f23	3103	#define BM_CAN_CSn_SRR (0x00400000U) /!< Bit mask for CAN_CSn_SRR. /
mbed_official	324:406fd2029f23	3104	#define BS_CAN_CSn_SRR (1U) /!< Bit field size in bits for CAN_CSn_SRR. /
mbed_official	324:406fd2029f23	3105
mbed_official	324:406fd2029f23	3106	/! @brief Read current value of the CAN_CSn_SRR field. /
mbed_official	324:406fd2029f23	3107	#define BR_CAN_CSn_SRR(x, n) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR))
mbed_official	324:406fd2029f23	3108
mbed_official	324:406fd2029f23	3109	/! @brief Format value for bitfield CAN_CSn_SRR. /
mbed_official	324:406fd2029f23	3110	#define BF_CAN_CSn_SRR(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_SRR) & BM_CAN_CSn_SRR)
mbed_official	324:406fd2029f23	3111
mbed_official	324:406fd2029f23	3112	/! @brief Set the SRR field to a new value. /
mbed_official	324:406fd2029f23	3113	#define BW_CAN_CSn_SRR(x, n, v) (BITBAND_ACCESS32(HW_CAN_CSn_ADDR(x, n), BP_CAN_CSn_SRR) = (v))
mbed_official	324:406fd2029f23	3114	/@}/
mbed_official	324:406fd2029f23	3115
mbed_official	324:406fd2029f23	3116	/*!
mbed_official	324:406fd2029f23	3117	* @name Register CAN_CSn, field CODE[27:24] (RW)
mbed_official	324:406fd2029f23	3118	*/
mbed_official	324:406fd2029f23	3119	/@{/
mbed_official	324:406fd2029f23	3120	#define BP_CAN_CSn_CODE (24U) /!< Bit position for CAN_CSn_CODE. /
mbed_official	324:406fd2029f23	3121	#define BM_CAN_CSn_CODE (0x0F000000U) /!< Bit mask for CAN_CSn_CODE. /
mbed_official	324:406fd2029f23	3122	#define BS_CAN_CSn_CODE (4U) /!< Bit field size in bits for CAN_CSn_CODE. /
mbed_official	324:406fd2029f23	3123
mbed_official	324:406fd2029f23	3124	/! @brief Read current value of the CAN_CSn_CODE field. /
mbed_official	324:406fd2029f23	3125	#define BR_CAN_CSn_CODE(x, n) (HW_CAN_CSn(x, n).B.CODE)
mbed_official	324:406fd2029f23	3126
mbed_official	324:406fd2029f23	3127	/! @brief Format value for bitfield CAN_CSn_CODE. /
mbed_official	324:406fd2029f23	3128	#define BF_CAN_CSn_CODE(v) ((uint32_t)((uint32_t)(v) << BP_CAN_CSn_CODE) & BM_CAN_CSn_CODE)
mbed_official	324:406fd2029f23	3129
mbed_official	324:406fd2029f23	3130	/! @brief Set the CODE field to a new value. /
mbed_official	324:406fd2029f23	3131	#define BW_CAN_CSn_CODE(x, n, v) (HW_CAN_CSn_WR(x, n, (HW_CAN_CSn_RD(x, n) & ~BM_CAN_CSn_CODE) \| BF_CAN_CSn_CODE(v)))
mbed_official	324:406fd2029f23	3132	/@}/
mbed_official	324:406fd2029f23	3133	/*******************************************************************************
mbed_official	324:406fd2029f23	3134	* HW_CAN_IDn - Message Buffer 0 ID Register
mbed_official	324:406fd2029f23	3135	******************************************************************************/
mbed_official	324:406fd2029f23	3136
mbed_official	324:406fd2029f23	3137	/*!
mbed_official	324:406fd2029f23	3138	* @brief HW_CAN_IDn - Message Buffer 0 ID Register (RW)
mbed_official	324:406fd2029f23	3139	*
mbed_official	324:406fd2029f23	3140	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3141	*/
mbed_official	324:406fd2029f23	3142	typedef union _hw_can_idn
mbed_official	324:406fd2029f23	3143	{
mbed_official	324:406fd2029f23	3144	uint32_t U;
mbed_official	324:406fd2029f23	3145	struct _hw_can_idn_bitfields
mbed_official	324:406fd2029f23	3146	{
mbed_official	324:406fd2029f23	3147	uint32_t EXT : 18; /*!< [17:0] Contains extended (LOW word)
mbed_official	324:406fd2029f23	3148	* identifier of message buffer. */
mbed_official	324:406fd2029f23	3149	uint32_t STD : 11; /*!< [28:18] Contains standard/extended (HIGH
mbed_official	324:406fd2029f23	3150	* word) identifier of message buffer. */
mbed_official	324:406fd2029f23	3151	uint32_t PRIO : 3; /*!< [31:29] Local priority. This 3-bit fieldis
mbed_official	324:406fd2029f23	3152	* only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx
mbed_official	324:406fd2029f23	3153	* buffers. These bits are not transmitted. They are appended to the regular
mbed_official	324:406fd2029f23	3154	* ID to define the transmission priority. */
mbed_official	324:406fd2029f23	3155	} B;
mbed_official	324:406fd2029f23	3156	} hw_can_idn_t;
mbed_official	324:406fd2029f23	3157
mbed_official	324:406fd2029f23	3158	/*!
mbed_official	324:406fd2029f23	3159	* @name Constants and macros for entire CAN_IDn register
mbed_official	324:406fd2029f23	3160	*/
mbed_official	324:406fd2029f23	3161	/@{/
mbed_official	324:406fd2029f23	3162	#define HW_CAN_IDn_COUNT (16U)
mbed_official	324:406fd2029f23	3163
mbed_official	324:406fd2029f23	3164	#define HW_CAN_IDn_ADDR(x, n) ((x) + 0x84U + (0x10U * (n)))
mbed_official	324:406fd2029f23	3165
mbed_official	324:406fd2029f23	3166	#define HW_CAN_IDn(x, n) ((__IO hw_can_idn_t ) HW_CAN_IDn_ADDR(x, n))
mbed_official	324:406fd2029f23	3167	#define HW_CAN_IDn_RD(x, n) (HW_CAN_IDn(x, n).U)
mbed_official	324:406fd2029f23	3168	#define HW_CAN_IDn_WR(x, n, v) (HW_CAN_IDn(x, n).U = (v))
mbed_official	324:406fd2029f23	3169	#define HW_CAN_IDn_SET(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	3170	#define HW_CAN_IDn_CLR(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	3171	#define HW_CAN_IDn_TOG(x, n, v) (HW_CAN_IDn_WR(x, n, HW_CAN_IDn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	3172	/@}/
mbed_official	324:406fd2029f23	3173
mbed_official	324:406fd2029f23	3174	/*
mbed_official	324:406fd2029f23	3175	* Constants & macros for individual CAN_IDn bitfields
mbed_official	324:406fd2029f23	3176	*/
mbed_official	324:406fd2029f23	3177
mbed_official	324:406fd2029f23	3178	/*!
mbed_official	324:406fd2029f23	3179	* @name Register CAN_IDn, field EXT[17:0] (RW)
mbed_official	324:406fd2029f23	3180	*/
mbed_official	324:406fd2029f23	3181	/@{/
mbed_official	324:406fd2029f23	3182	#define BP_CAN_IDn_EXT (0U) /!< Bit position for CAN_IDn_EXT. /
mbed_official	324:406fd2029f23	3183	#define BM_CAN_IDn_EXT (0x0003FFFFU) /!< Bit mask for CAN_IDn_EXT. /
mbed_official	324:406fd2029f23	3184	#define BS_CAN_IDn_EXT (18U) /!< Bit field size in bits for CAN_IDn_EXT. /
mbed_official	324:406fd2029f23	3185
mbed_official	324:406fd2029f23	3186	/! @brief Read current value of the CAN_IDn_EXT field. /
mbed_official	324:406fd2029f23	3187	#define BR_CAN_IDn_EXT(x, n) (HW_CAN_IDn(x, n).B.EXT)
mbed_official	324:406fd2029f23	3188
mbed_official	324:406fd2029f23	3189	/! @brief Format value for bitfield CAN_IDn_EXT. /
mbed_official	324:406fd2029f23	3190	#define BF_CAN_IDn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_EXT) & BM_CAN_IDn_EXT)
mbed_official	324:406fd2029f23	3191
mbed_official	324:406fd2029f23	3192	/! @brief Set the EXT field to a new value. /
mbed_official	324:406fd2029f23	3193	#define BW_CAN_IDn_EXT(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_EXT) \| BF_CAN_IDn_EXT(v)))
mbed_official	324:406fd2029f23	3194	/@}/
mbed_official	324:406fd2029f23	3195
mbed_official	324:406fd2029f23	3196	/*!
mbed_official	324:406fd2029f23	3197	* @name Register CAN_IDn, field STD[28:18] (RW)
mbed_official	324:406fd2029f23	3198	*/
mbed_official	324:406fd2029f23	3199	/@{/
mbed_official	324:406fd2029f23	3200	#define BP_CAN_IDn_STD (18U) /!< Bit position for CAN_IDn_STD. /
mbed_official	324:406fd2029f23	3201	#define BM_CAN_IDn_STD (0x1FFC0000U) /!< Bit mask for CAN_IDn_STD. /
mbed_official	324:406fd2029f23	3202	#define BS_CAN_IDn_STD (11U) /!< Bit field size in bits for CAN_IDn_STD. /
mbed_official	324:406fd2029f23	3203
mbed_official	324:406fd2029f23	3204	/! @brief Read current value of the CAN_IDn_STD field. /
mbed_official	324:406fd2029f23	3205	#define BR_CAN_IDn_STD(x, n) (HW_CAN_IDn(x, n).B.STD)
mbed_official	324:406fd2029f23	3206
mbed_official	324:406fd2029f23	3207	/! @brief Format value for bitfield CAN_IDn_STD. /
mbed_official	324:406fd2029f23	3208	#define BF_CAN_IDn_STD(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_STD) & BM_CAN_IDn_STD)
mbed_official	324:406fd2029f23	3209
mbed_official	324:406fd2029f23	3210	/! @brief Set the STD field to a new value. /
mbed_official	324:406fd2029f23	3211	#define BW_CAN_IDn_STD(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_STD) \| BF_CAN_IDn_STD(v)))
mbed_official	324:406fd2029f23	3212	/@}/
mbed_official	324:406fd2029f23	3213
mbed_official	324:406fd2029f23	3214	/*!
mbed_official	324:406fd2029f23	3215	* @name Register CAN_IDn, field PRIO[31:29] (RW)
mbed_official	324:406fd2029f23	3216	*/
mbed_official	324:406fd2029f23	3217	/@{/
mbed_official	324:406fd2029f23	3218	#define BP_CAN_IDn_PRIO (29U) /!< Bit position for CAN_IDn_PRIO. /
mbed_official	324:406fd2029f23	3219	#define BM_CAN_IDn_PRIO (0xE0000000U) /!< Bit mask for CAN_IDn_PRIO. /
mbed_official	324:406fd2029f23	3220	#define BS_CAN_IDn_PRIO (3U) /!< Bit field size in bits for CAN_IDn_PRIO. /
mbed_official	324:406fd2029f23	3221
mbed_official	324:406fd2029f23	3222	/! @brief Read current value of the CAN_IDn_PRIO field. /
mbed_official	324:406fd2029f23	3223	#define BR_CAN_IDn_PRIO(x, n) (HW_CAN_IDn(x, n).B.PRIO)
mbed_official	324:406fd2029f23	3224
mbed_official	324:406fd2029f23	3225	/! @brief Format value for bitfield CAN_IDn_PRIO. /
mbed_official	324:406fd2029f23	3226	#define BF_CAN_IDn_PRIO(v) ((uint32_t)((uint32_t)(v) << BP_CAN_IDn_PRIO) & BM_CAN_IDn_PRIO)
mbed_official	324:406fd2029f23	3227
mbed_official	324:406fd2029f23	3228	/! @brief Set the PRIO field to a new value. /
mbed_official	324:406fd2029f23	3229	#define BW_CAN_IDn_PRIO(x, n, v) (HW_CAN_IDn_WR(x, n, (HW_CAN_IDn_RD(x, n) & ~BM_CAN_IDn_PRIO) \| BF_CAN_IDn_PRIO(v)))
mbed_official	324:406fd2029f23	3230	/@}/
mbed_official	324:406fd2029f23	3231	/*******************************************************************************
mbed_official	324:406fd2029f23	3232	* HW_CAN_WORD0n - Message Buffer 0 WORD0 Register
mbed_official	324:406fd2029f23	3233	******************************************************************************/
mbed_official	324:406fd2029f23	3234
mbed_official	324:406fd2029f23	3235	/*!
mbed_official	324:406fd2029f23	3236	* @brief HW_CAN_WORD0n - Message Buffer 0 WORD0 Register (RW)
mbed_official	324:406fd2029f23	3237	*
mbed_official	324:406fd2029f23	3238	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3239	*/
mbed_official	324:406fd2029f23	3240	typedef union _hw_can_word0n
mbed_official	324:406fd2029f23	3241	{
mbed_official	324:406fd2029f23	3242	uint32_t U;
mbed_official	324:406fd2029f23	3243	struct _hw_can_word0n_bitfields
mbed_official	324:406fd2029f23	3244	{
mbed_official	324:406fd2029f23	3245	uint32_t DATA_BYTE_3 : 8; /!< [7:0] Data byte 3 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3246	uint32_t DATA_BYTE_2 : 8; /!< [15:8] Data byte 2 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3247	uint32_t DATA_BYTE_1 : 8; /!< [23:16] Data byte 1 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3248	uint32_t DATA_BYTE_0 : 8; /!< [31:24] Data byte 0 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3249	} B;
mbed_official	324:406fd2029f23	3250	} hw_can_word0n_t;
mbed_official	324:406fd2029f23	3251
mbed_official	324:406fd2029f23	3252	/*!
mbed_official	324:406fd2029f23	3253	* @name Constants and macros for entire CAN_WORD0n register
mbed_official	324:406fd2029f23	3254	*/
mbed_official	324:406fd2029f23	3255	/@{/
mbed_official	324:406fd2029f23	3256	#define HW_CAN_WORD0n_COUNT (16U)
mbed_official	324:406fd2029f23	3257
mbed_official	324:406fd2029f23	3258	#define HW_CAN_WORD0n_ADDR(x, n) ((x) + 0x88U + (0x10U * (n)))
mbed_official	324:406fd2029f23	3259
mbed_official	324:406fd2029f23	3260	#define HW_CAN_WORD0n(x, n) ((__IO hw_can_word0n_t ) HW_CAN_WORD0n_ADDR(x, n))
mbed_official	324:406fd2029f23	3261	#define HW_CAN_WORD0n_RD(x, n) (HW_CAN_WORD0n(x, n).U)
mbed_official	324:406fd2029f23	3262	#define HW_CAN_WORD0n_WR(x, n, v) (HW_CAN_WORD0n(x, n).U = (v))
mbed_official	324:406fd2029f23	3263	#define HW_CAN_WORD0n_SET(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	3264	#define HW_CAN_WORD0n_CLR(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	3265	#define HW_CAN_WORD0n_TOG(x, n, v) (HW_CAN_WORD0n_WR(x, n, HW_CAN_WORD0n_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	3266	/@}/
mbed_official	324:406fd2029f23	3267
mbed_official	324:406fd2029f23	3268	/*
mbed_official	324:406fd2029f23	3269	* Constants & macros for individual CAN_WORD0n bitfields
mbed_official	324:406fd2029f23	3270	*/
mbed_official	324:406fd2029f23	3271
mbed_official	324:406fd2029f23	3272	/*!
mbed_official	324:406fd2029f23	3273	* @name Register CAN_WORD0n, field DATA_BYTE_3[7:0] (RW)
mbed_official	324:406fd2029f23	3274	*/
mbed_official	324:406fd2029f23	3275	/@{/
mbed_official	324:406fd2029f23	3276	#define BP_CAN_WORD0n_DATA_BYTE_3 (0U) /!< Bit position for CAN_WORD0n_DATA_BYTE_3. /
mbed_official	324:406fd2029f23	3277	#define BM_CAN_WORD0n_DATA_BYTE_3 (0x000000FFU) /!< Bit mask for CAN_WORD0n_DATA_BYTE_3. /
mbed_official	324:406fd2029f23	3278	#define BS_CAN_WORD0n_DATA_BYTE_3 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_3. /
mbed_official	324:406fd2029f23	3279
mbed_official	324:406fd2029f23	3280	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_3 field. /
mbed_official	324:406fd2029f23	3281	#define BR_CAN_WORD0n_DATA_BYTE_3(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_3)
mbed_official	324:406fd2029f23	3282
mbed_official	324:406fd2029f23	3283	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_3. /
mbed_official	324:406fd2029f23	3284	#define BF_CAN_WORD0n_DATA_BYTE_3(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_3) & BM_CAN_WORD0n_DATA_BYTE_3)
mbed_official	324:406fd2029f23	3285
mbed_official	324:406fd2029f23	3286	/! @brief Set the DATA_BYTE_3 field to a new value. /
mbed_official	324:406fd2029f23	3287	#define BW_CAN_WORD0n_DATA_BYTE_3(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_3) \| BF_CAN_WORD0n_DATA_BYTE_3(v)))
mbed_official	324:406fd2029f23	3288	/@}/
mbed_official	324:406fd2029f23	3289
mbed_official	324:406fd2029f23	3290	/*!
mbed_official	324:406fd2029f23	3291	* @name Register CAN_WORD0n, field DATA_BYTE_2[15:8] (RW)
mbed_official	324:406fd2029f23	3292	*/
mbed_official	324:406fd2029f23	3293	/@{/
mbed_official	324:406fd2029f23	3294	#define BP_CAN_WORD0n_DATA_BYTE_2 (8U) /!< Bit position for CAN_WORD0n_DATA_BYTE_2. /
mbed_official	324:406fd2029f23	3295	#define BM_CAN_WORD0n_DATA_BYTE_2 (0x0000FF00U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_2. /
mbed_official	324:406fd2029f23	3296	#define BS_CAN_WORD0n_DATA_BYTE_2 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_2. /
mbed_official	324:406fd2029f23	3297
mbed_official	324:406fd2029f23	3298	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_2 field. /
mbed_official	324:406fd2029f23	3299	#define BR_CAN_WORD0n_DATA_BYTE_2(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_2)
mbed_official	324:406fd2029f23	3300
mbed_official	324:406fd2029f23	3301	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_2. /
mbed_official	324:406fd2029f23	3302	#define BF_CAN_WORD0n_DATA_BYTE_2(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_2) & BM_CAN_WORD0n_DATA_BYTE_2)
mbed_official	324:406fd2029f23	3303
mbed_official	324:406fd2029f23	3304	/! @brief Set the DATA_BYTE_2 field to a new value. /
mbed_official	324:406fd2029f23	3305	#define BW_CAN_WORD0n_DATA_BYTE_2(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_2) \| BF_CAN_WORD0n_DATA_BYTE_2(v)))
mbed_official	324:406fd2029f23	3306	/@}/
mbed_official	324:406fd2029f23	3307
mbed_official	324:406fd2029f23	3308	/*!
mbed_official	324:406fd2029f23	3309	* @name Register CAN_WORD0n, field DATA_BYTE_1[23:16] (RW)
mbed_official	324:406fd2029f23	3310	*/
mbed_official	324:406fd2029f23	3311	/@{/
mbed_official	324:406fd2029f23	3312	#define BP_CAN_WORD0n_DATA_BYTE_1 (16U) /!< Bit position for CAN_WORD0n_DATA_BYTE_1. /
mbed_official	324:406fd2029f23	3313	#define BM_CAN_WORD0n_DATA_BYTE_1 (0x00FF0000U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_1. /
mbed_official	324:406fd2029f23	3314	#define BS_CAN_WORD0n_DATA_BYTE_1 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_1. /
mbed_official	324:406fd2029f23	3315
mbed_official	324:406fd2029f23	3316	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_1 field. /
mbed_official	324:406fd2029f23	3317	#define BR_CAN_WORD0n_DATA_BYTE_1(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_1)
mbed_official	324:406fd2029f23	3318
mbed_official	324:406fd2029f23	3319	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_1. /
mbed_official	324:406fd2029f23	3320	#define BF_CAN_WORD0n_DATA_BYTE_1(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_1) & BM_CAN_WORD0n_DATA_BYTE_1)
mbed_official	324:406fd2029f23	3321
mbed_official	324:406fd2029f23	3322	/! @brief Set the DATA_BYTE_1 field to a new value. /
mbed_official	324:406fd2029f23	3323	#define BW_CAN_WORD0n_DATA_BYTE_1(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_1) \| BF_CAN_WORD0n_DATA_BYTE_1(v)))
mbed_official	324:406fd2029f23	3324	/@}/
mbed_official	324:406fd2029f23	3325
mbed_official	324:406fd2029f23	3326	/*!
mbed_official	324:406fd2029f23	3327	* @name Register CAN_WORD0n, field DATA_BYTE_0[31:24] (RW)
mbed_official	324:406fd2029f23	3328	*/
mbed_official	324:406fd2029f23	3329	/@{/
mbed_official	324:406fd2029f23	3330	#define BP_CAN_WORD0n_DATA_BYTE_0 (24U) /!< Bit position for CAN_WORD0n_DATA_BYTE_0. /
mbed_official	324:406fd2029f23	3331	#define BM_CAN_WORD0n_DATA_BYTE_0 (0xFF000000U) /!< Bit mask for CAN_WORD0n_DATA_BYTE_0. /
mbed_official	324:406fd2029f23	3332	#define BS_CAN_WORD0n_DATA_BYTE_0 (8U) /!< Bit field size in bits for CAN_WORD0n_DATA_BYTE_0. /
mbed_official	324:406fd2029f23	3333
mbed_official	324:406fd2029f23	3334	/! @brief Read current value of the CAN_WORD0n_DATA_BYTE_0 field. /
mbed_official	324:406fd2029f23	3335	#define BR_CAN_WORD0n_DATA_BYTE_0(x, n) (HW_CAN_WORD0n(x, n).B.DATA_BYTE_0)
mbed_official	324:406fd2029f23	3336
mbed_official	324:406fd2029f23	3337	/! @brief Format value for bitfield CAN_WORD0n_DATA_BYTE_0. /
mbed_official	324:406fd2029f23	3338	#define BF_CAN_WORD0n_DATA_BYTE_0(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD0n_DATA_BYTE_0) & BM_CAN_WORD0n_DATA_BYTE_0)
mbed_official	324:406fd2029f23	3339
mbed_official	324:406fd2029f23	3340	/! @brief Set the DATA_BYTE_0 field to a new value. /
mbed_official	324:406fd2029f23	3341	#define BW_CAN_WORD0n_DATA_BYTE_0(x, n, v) (HW_CAN_WORD0n_WR(x, n, (HW_CAN_WORD0n_RD(x, n) & ~BM_CAN_WORD0n_DATA_BYTE_0) \| BF_CAN_WORD0n_DATA_BYTE_0(v)))
mbed_official	324:406fd2029f23	3342	/@}/
mbed_official	324:406fd2029f23	3343	/*******************************************************************************
mbed_official	324:406fd2029f23	3344	* HW_CAN_WORD1n - Message Buffer 0 WORD1 Register
mbed_official	324:406fd2029f23	3345	******************************************************************************/
mbed_official	324:406fd2029f23	3346
mbed_official	324:406fd2029f23	3347	/*!
mbed_official	324:406fd2029f23	3348	* @brief HW_CAN_WORD1n - Message Buffer 0 WORD1 Register (RW)
mbed_official	324:406fd2029f23	3349	*
mbed_official	324:406fd2029f23	3350	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3351	*/
mbed_official	324:406fd2029f23	3352	typedef union _hw_can_word1n
mbed_official	324:406fd2029f23	3353	{
mbed_official	324:406fd2029f23	3354	uint32_t U;
mbed_official	324:406fd2029f23	3355	struct _hw_can_word1n_bitfields
mbed_official	324:406fd2029f23	3356	{
mbed_official	324:406fd2029f23	3357	uint32_t DATA_BYTE_7 : 8; /!< [7:0] Data byte 7 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3358	uint32_t DATA_BYTE_6 : 8; /!< [15:8] Data byte 6 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3359	uint32_t DATA_BYTE_5 : 8; /!< [23:16] Data byte 5 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3360	uint32_t DATA_BYTE_4 : 8; /!< [31:24] Data byte 4 of Rx/Tx frame. /
mbed_official	324:406fd2029f23	3361	} B;
mbed_official	324:406fd2029f23	3362	} hw_can_word1n_t;
mbed_official	324:406fd2029f23	3363
mbed_official	324:406fd2029f23	3364	/*!
mbed_official	324:406fd2029f23	3365	* @name Constants and macros for entire CAN_WORD1n register
mbed_official	324:406fd2029f23	3366	*/
mbed_official	324:406fd2029f23	3367	/@{/
mbed_official	324:406fd2029f23	3368	#define HW_CAN_WORD1n_COUNT (16U)
mbed_official	324:406fd2029f23	3369
mbed_official	324:406fd2029f23	3370	#define HW_CAN_WORD1n_ADDR(x, n) ((x) + 0x8CU + (0x10U * (n)))
mbed_official	324:406fd2029f23	3371
mbed_official	324:406fd2029f23	3372	#define HW_CAN_WORD1n(x, n) ((__IO hw_can_word1n_t ) HW_CAN_WORD1n_ADDR(x, n))
mbed_official	324:406fd2029f23	3373	#define HW_CAN_WORD1n_RD(x, n) (HW_CAN_WORD1n(x, n).U)
mbed_official	324:406fd2029f23	3374	#define HW_CAN_WORD1n_WR(x, n, v) (HW_CAN_WORD1n(x, n).U = (v))
mbed_official	324:406fd2029f23	3375	#define HW_CAN_WORD1n_SET(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	3376	#define HW_CAN_WORD1n_CLR(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	3377	#define HW_CAN_WORD1n_TOG(x, n, v) (HW_CAN_WORD1n_WR(x, n, HW_CAN_WORD1n_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	3378	/@}/
mbed_official	324:406fd2029f23	3379
mbed_official	324:406fd2029f23	3380	/*
mbed_official	324:406fd2029f23	3381	* Constants & macros for individual CAN_WORD1n bitfields
mbed_official	324:406fd2029f23	3382	*/
mbed_official	324:406fd2029f23	3383
mbed_official	324:406fd2029f23	3384	/*!
mbed_official	324:406fd2029f23	3385	* @name Register CAN_WORD1n, field DATA_BYTE_7[7:0] (RW)
mbed_official	324:406fd2029f23	3386	*/
mbed_official	324:406fd2029f23	3387	/@{/
mbed_official	324:406fd2029f23	3388	#define BP_CAN_WORD1n_DATA_BYTE_7 (0U) /!< Bit position for CAN_WORD1n_DATA_BYTE_7. /
mbed_official	324:406fd2029f23	3389	#define BM_CAN_WORD1n_DATA_BYTE_7 (0x000000FFU) /!< Bit mask for CAN_WORD1n_DATA_BYTE_7. /
mbed_official	324:406fd2029f23	3390	#define BS_CAN_WORD1n_DATA_BYTE_7 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_7. /
mbed_official	324:406fd2029f23	3391
mbed_official	324:406fd2029f23	3392	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_7 field. /
mbed_official	324:406fd2029f23	3393	#define BR_CAN_WORD1n_DATA_BYTE_7(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_7)
mbed_official	324:406fd2029f23	3394
mbed_official	324:406fd2029f23	3395	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_7. /
mbed_official	324:406fd2029f23	3396	#define BF_CAN_WORD1n_DATA_BYTE_7(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_7) & BM_CAN_WORD1n_DATA_BYTE_7)
mbed_official	324:406fd2029f23	3397
mbed_official	324:406fd2029f23	3398	/! @brief Set the DATA_BYTE_7 field to a new value. /
mbed_official	324:406fd2029f23	3399	#define BW_CAN_WORD1n_DATA_BYTE_7(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_7) \| BF_CAN_WORD1n_DATA_BYTE_7(v)))
mbed_official	324:406fd2029f23	3400	/@}/
mbed_official	324:406fd2029f23	3401
mbed_official	324:406fd2029f23	3402	/*!
mbed_official	324:406fd2029f23	3403	* @name Register CAN_WORD1n, field DATA_BYTE_6[15:8] (RW)
mbed_official	324:406fd2029f23	3404	*/
mbed_official	324:406fd2029f23	3405	/@{/
mbed_official	324:406fd2029f23	3406	#define BP_CAN_WORD1n_DATA_BYTE_6 (8U) /!< Bit position for CAN_WORD1n_DATA_BYTE_6. /
mbed_official	324:406fd2029f23	3407	#define BM_CAN_WORD1n_DATA_BYTE_6 (0x0000FF00U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_6. /
mbed_official	324:406fd2029f23	3408	#define BS_CAN_WORD1n_DATA_BYTE_6 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_6. /
mbed_official	324:406fd2029f23	3409
mbed_official	324:406fd2029f23	3410	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_6 field. /
mbed_official	324:406fd2029f23	3411	#define BR_CAN_WORD1n_DATA_BYTE_6(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_6)
mbed_official	324:406fd2029f23	3412
mbed_official	324:406fd2029f23	3413	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_6. /
mbed_official	324:406fd2029f23	3414	#define BF_CAN_WORD1n_DATA_BYTE_6(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_6) & BM_CAN_WORD1n_DATA_BYTE_6)
mbed_official	324:406fd2029f23	3415
mbed_official	324:406fd2029f23	3416	/! @brief Set the DATA_BYTE_6 field to a new value. /
mbed_official	324:406fd2029f23	3417	#define BW_CAN_WORD1n_DATA_BYTE_6(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_6) \| BF_CAN_WORD1n_DATA_BYTE_6(v)))
mbed_official	324:406fd2029f23	3418	/@}/
mbed_official	324:406fd2029f23	3419
mbed_official	324:406fd2029f23	3420	/*!
mbed_official	324:406fd2029f23	3421	* @name Register CAN_WORD1n, field DATA_BYTE_5[23:16] (RW)
mbed_official	324:406fd2029f23	3422	*/
mbed_official	324:406fd2029f23	3423	/@{/
mbed_official	324:406fd2029f23	3424	#define BP_CAN_WORD1n_DATA_BYTE_5 (16U) /!< Bit position for CAN_WORD1n_DATA_BYTE_5. /
mbed_official	324:406fd2029f23	3425	#define BM_CAN_WORD1n_DATA_BYTE_5 (0x00FF0000U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_5. /
mbed_official	324:406fd2029f23	3426	#define BS_CAN_WORD1n_DATA_BYTE_5 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_5. /
mbed_official	324:406fd2029f23	3427
mbed_official	324:406fd2029f23	3428	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_5 field. /
mbed_official	324:406fd2029f23	3429	#define BR_CAN_WORD1n_DATA_BYTE_5(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_5)
mbed_official	324:406fd2029f23	3430
mbed_official	324:406fd2029f23	3431	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_5. /
mbed_official	324:406fd2029f23	3432	#define BF_CAN_WORD1n_DATA_BYTE_5(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_5) & BM_CAN_WORD1n_DATA_BYTE_5)
mbed_official	324:406fd2029f23	3433
mbed_official	324:406fd2029f23	3434	/! @brief Set the DATA_BYTE_5 field to a new value. /
mbed_official	324:406fd2029f23	3435	#define BW_CAN_WORD1n_DATA_BYTE_5(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_5) \| BF_CAN_WORD1n_DATA_BYTE_5(v)))
mbed_official	324:406fd2029f23	3436	/@}/
mbed_official	324:406fd2029f23	3437
mbed_official	324:406fd2029f23	3438	/*!
mbed_official	324:406fd2029f23	3439	* @name Register CAN_WORD1n, field DATA_BYTE_4[31:24] (RW)
mbed_official	324:406fd2029f23	3440	*/
mbed_official	324:406fd2029f23	3441	/@{/
mbed_official	324:406fd2029f23	3442	#define BP_CAN_WORD1n_DATA_BYTE_4 (24U) /!< Bit position for CAN_WORD1n_DATA_BYTE_4. /
mbed_official	324:406fd2029f23	3443	#define BM_CAN_WORD1n_DATA_BYTE_4 (0xFF000000U) /!< Bit mask for CAN_WORD1n_DATA_BYTE_4. /
mbed_official	324:406fd2029f23	3444	#define BS_CAN_WORD1n_DATA_BYTE_4 (8U) /!< Bit field size in bits for CAN_WORD1n_DATA_BYTE_4. /
mbed_official	324:406fd2029f23	3445
mbed_official	324:406fd2029f23	3446	/! @brief Read current value of the CAN_WORD1n_DATA_BYTE_4 field. /
mbed_official	324:406fd2029f23	3447	#define BR_CAN_WORD1n_DATA_BYTE_4(x, n) (HW_CAN_WORD1n(x, n).B.DATA_BYTE_4)
mbed_official	324:406fd2029f23	3448
mbed_official	324:406fd2029f23	3449	/! @brief Format value for bitfield CAN_WORD1n_DATA_BYTE_4. /
mbed_official	324:406fd2029f23	3450	#define BF_CAN_WORD1n_DATA_BYTE_4(v) ((uint32_t)((uint32_t)(v) << BP_CAN_WORD1n_DATA_BYTE_4) & BM_CAN_WORD1n_DATA_BYTE_4)
mbed_official	324:406fd2029f23	3451
mbed_official	324:406fd2029f23	3452	/! @brief Set the DATA_BYTE_4 field to a new value. /
mbed_official	324:406fd2029f23	3453	#define BW_CAN_WORD1n_DATA_BYTE_4(x, n, v) (HW_CAN_WORD1n_WR(x, n, (HW_CAN_WORD1n_RD(x, n) & ~BM_CAN_WORD1n_DATA_BYTE_4) \| BF_CAN_WORD1n_DATA_BYTE_4(v)))
mbed_official	324:406fd2029f23	3454	/@}/
mbed_official	324:406fd2029f23	3455
mbed_official	324:406fd2029f23	3456	/*******************************************************************************
mbed_official	324:406fd2029f23	3457	* HW_CAN_RXIMRn - Rx Individual Mask Registers
mbed_official	324:406fd2029f23	3458	******************************************************************************/
mbed_official	324:406fd2029f23	3459
mbed_official	324:406fd2029f23	3460	/*!
mbed_official	324:406fd2029f23	3461	* @brief HW_CAN_RXIMRn - Rx Individual Mask Registers (RW)
mbed_official	324:406fd2029f23	3462	*
mbed_official	324:406fd2029f23	3463	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3464	*
mbed_official	324:406fd2029f23	3465	* These registers are located in RAM. RXIMR are used as acceptance masks for ID
mbed_official	324:406fd2029f23	3466	* filtering in Rx MBs and the Rx FIFO. If the Rx FIFO is not enabled, one mask
mbed_official	324:406fd2029f23	3467	* register is provided for each available Mailbox, providing ID masking
mbed_official	324:406fd2029f23	3468	* capability on a per Mailbox basis. When the Rx FIFO is enabled (MCR[RFEN] bit is
mbed_official	324:406fd2029f23	3469	* asserted), up to 32 Rx Individual Mask Registers can apply to the Rx FIFO ID Filter
mbed_official	324:406fd2029f23	3470	* Table elements on a one-to-one correspondence depending on the setting of
mbed_official	324:406fd2029f23	3471	* CTRL2[RFFN]. RXIMR can only be written by the CPU while the module is in Freeze
mbed_official	324:406fd2029f23	3472	* mode; otherwise, they are blocked by hardware. The Individual Rx Mask Registers
mbed_official	324:406fd2029f23	3473	* are not affected by reset and must be explicitly initialized prior to any
mbed_official	324:406fd2029f23	3474	* reception.
mbed_official	324:406fd2029f23	3475	*/
mbed_official	324:406fd2029f23	3476	typedef union _hw_can_rximrn
mbed_official	324:406fd2029f23	3477	{
mbed_official	324:406fd2029f23	3478	uint32_t U;
mbed_official	324:406fd2029f23	3479	struct _hw_can_rximrn_bitfields
mbed_official	324:406fd2029f23	3480	{
mbed_official	324:406fd2029f23	3481	uint32_t MI : 32; /!< [31:0] Individual Mask Bits /
mbed_official	324:406fd2029f23	3482	} B;
mbed_official	324:406fd2029f23	3483	} hw_can_rximrn_t;
mbed_official	324:406fd2029f23	3484
mbed_official	324:406fd2029f23	3485	/*!
mbed_official	324:406fd2029f23	3486	* @name Constants and macros for entire CAN_RXIMRn register
mbed_official	324:406fd2029f23	3487	*/
mbed_official	324:406fd2029f23	3488	/@{/
mbed_official	324:406fd2029f23	3489	#define HW_CAN_RXIMRn_COUNT (16U)
mbed_official	324:406fd2029f23	3490
mbed_official	324:406fd2029f23	3491	#define HW_CAN_RXIMRn_ADDR(x, n) ((x) + 0x880U + (0x4U * (n)))
mbed_official	324:406fd2029f23	3492
mbed_official	324:406fd2029f23	3493	#define HW_CAN_RXIMRn(x, n) ((__IO hw_can_rximrn_t ) HW_CAN_RXIMRn_ADDR(x, n))
mbed_official	324:406fd2029f23	3494	#define HW_CAN_RXIMRn_RD(x, n) (HW_CAN_RXIMRn(x, n).U)
mbed_official	324:406fd2029f23	3495	#define HW_CAN_RXIMRn_WR(x, n, v) (HW_CAN_RXIMRn(x, n).U = (v))
mbed_official	324:406fd2029f23	3496	#define HW_CAN_RXIMRn_SET(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	3497	#define HW_CAN_RXIMRn_CLR(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	3498	#define HW_CAN_RXIMRn_TOG(x, n, v) (HW_CAN_RXIMRn_WR(x, n, HW_CAN_RXIMRn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	3499	/@}/
mbed_official	324:406fd2029f23	3500
mbed_official	324:406fd2029f23	3501	/*
mbed_official	324:406fd2029f23	3502	* Constants & macros for individual CAN_RXIMRn bitfields
mbed_official	324:406fd2029f23	3503	*/
mbed_official	324:406fd2029f23	3504
mbed_official	324:406fd2029f23	3505	/*!
mbed_official	324:406fd2029f23	3506	* @name Register CAN_RXIMRn, field MI[31:0] (RW)
mbed_official	324:406fd2029f23	3507	*
mbed_official	324:406fd2029f23	3508	* Each Individual Mask Bit masks the corresponding bit in both the Mailbox
mbed_official	324:406fd2029f23	3509	* filter and Rx FIFO ID Filter Table element in distinct ways. For Mailbox filters,
mbed_official	324:406fd2029f23	3510	* see the RXMGMASK register description. For Rx FIFO ID Filter Table elements,
mbed_official	324:406fd2029f23	3511	* see the RXFGMASK register description.
mbed_official	324:406fd2029f23	3512	*
mbed_official	324:406fd2029f23	3513	* Values:
mbed_official	324:406fd2029f23	3514	* - 0 - The corresponding bit in the filter is "don't care."
mbed_official	324:406fd2029f23	3515	* - 1 - The corresponding bit in the filter is checked.
mbed_official	324:406fd2029f23	3516	*/
mbed_official	324:406fd2029f23	3517	/@{/
mbed_official	324:406fd2029f23	3518	#define BP_CAN_RXIMRn_MI (0U) /!< Bit position for CAN_RXIMRn_MI. /
mbed_official	324:406fd2029f23	3519	#define BM_CAN_RXIMRn_MI (0xFFFFFFFFU) /!< Bit mask for CAN_RXIMRn_MI. /
mbed_official	324:406fd2029f23	3520	#define BS_CAN_RXIMRn_MI (32U) /!< Bit field size in bits for CAN_RXIMRn_MI. /
mbed_official	324:406fd2029f23	3521
mbed_official	324:406fd2029f23	3522	/! @brief Read current value of the CAN_RXIMRn_MI field. /
mbed_official	324:406fd2029f23	3523	#define BR_CAN_RXIMRn_MI(x, n) (HW_CAN_RXIMRn(x, n).U)
mbed_official	324:406fd2029f23	3524
mbed_official	324:406fd2029f23	3525	/! @brief Format value for bitfield CAN_RXIMRn_MI. /
mbed_official	324:406fd2029f23	3526	#define BF_CAN_RXIMRn_MI(v) ((uint32_t)((uint32_t)(v) << BP_CAN_RXIMRn_MI) & BM_CAN_RXIMRn_MI)
mbed_official	324:406fd2029f23	3527
mbed_official	324:406fd2029f23	3528	/! @brief Set the MI field to a new value. /
mbed_official	324:406fd2029f23	3529	#define BW_CAN_RXIMRn_MI(x, n, v) (HW_CAN_RXIMRn_WR(x, n, v))
mbed_official	324:406fd2029f23	3530	/@}/
mbed_official	324:406fd2029f23	3531
mbed_official	324:406fd2029f23	3532	/*******************************************************************************
mbed_official	324:406fd2029f23	3533	* hw_can_t - module struct
mbed_official	324:406fd2029f23	3534	******************************************************************************/
mbed_official	324:406fd2029f23	3535	/*!
mbed_official	324:406fd2029f23	3536	* @brief All CAN module registers.
mbed_official	324:406fd2029f23	3537	*/
mbed_official	324:406fd2029f23	3538	#pragma pack(1)
mbed_official	324:406fd2029f23	3539	typedef struct _hw_can
mbed_official	324:406fd2029f23	3540	{
mbed_official	324:406fd2029f23	3541	__IO hw_can_mcr_t MCR; /!< [0x0] Module Configuration Register /
mbed_official	324:406fd2029f23	3542	__IO hw_can_ctrl1_t CTRL1; /!< [0x4] Control 1 register /
mbed_official	324:406fd2029f23	3543	__IO hw_can_timer_t TIMER; /!< [0x8] Free Running Timer /
mbed_official	324:406fd2029f23	3544	uint8_t _reserved0[4];
mbed_official	324:406fd2029f23	3545	__IO hw_can_rxmgmask_t RXMGMASK; /!< [0x10] Rx Mailboxes Global Mask Register /
mbed_official	324:406fd2029f23	3546	__IO hw_can_rx14mask_t RX14MASK; /!< [0x14] Rx 14 Mask register /
mbed_official	324:406fd2029f23	3547	__IO hw_can_rx15mask_t RX15MASK; /!< [0x18] Rx 15 Mask register /
mbed_official	324:406fd2029f23	3548	__IO hw_can_ecr_t ECR; /!< [0x1C] Error Counter /
mbed_official	324:406fd2029f23	3549	__IO hw_can_esr1_t ESR1; /!< [0x20] Error and Status 1 register /
mbed_official	324:406fd2029f23	3550	uint8_t _reserved1[4];
mbed_official	324:406fd2029f23	3551	__IO hw_can_imask1_t IMASK1; /!< [0x28] Interrupt Masks 1 register /
mbed_official	324:406fd2029f23	3552	uint8_t _reserved2[4];
mbed_official	324:406fd2029f23	3553	__IO hw_can_iflag1_t IFLAG1; /!< [0x30] Interrupt Flags 1 register /
mbed_official	324:406fd2029f23	3554	__IO hw_can_ctrl2_t CTRL2; /!< [0x34] Control 2 register /
mbed_official	324:406fd2029f23	3555	__I hw_can_esr2_t ESR2; /!< [0x38] Error and Status 2 register /
mbed_official	324:406fd2029f23	3556	uint8_t _reserved3[8];
mbed_official	324:406fd2029f23	3557	__I hw_can_crcr_t CRCR; /!< [0x44] CRC Register /
mbed_official	324:406fd2029f23	3558	__IO hw_can_rxfgmask_t RXFGMASK; /!< [0x48] Rx FIFO Global Mask register /
mbed_official	324:406fd2029f23	3559	__I hw_can_rxfir_t RXFIR; /!< [0x4C] Rx FIFO Information Register /
mbed_official	324:406fd2029f23	3560	uint8_t _reserved4[48];
mbed_official	324:406fd2029f23	3561	struct {
mbed_official	324:406fd2029f23	3562	__IO hw_can_csn_t CSn; /!< [0x80] Message Buffer 0 CS Register /
mbed_official	324:406fd2029f23	3563	__IO hw_can_idn_t IDn; /!< [0x84] Message Buffer 0 ID Register /
mbed_official	324:406fd2029f23	3564	__IO hw_can_word0n_t WORD0n; /!< [0x88] Message Buffer 0 WORD0 Register /
mbed_official	324:406fd2029f23	3565	__IO hw_can_word1n_t WORD1n; /!< [0x8C] Message Buffer 0 WORD1 Register /
mbed_official	324:406fd2029f23	3566	} MB[16];
mbed_official	324:406fd2029f23	3567	uint8_t _reserved5[1792];
mbed_official	324:406fd2029f23	3568	__IO hw_can_rximrn_t RXIMRn[16]; /!< [0x880] Rx Individual Mask Registers /
mbed_official	324:406fd2029f23	3569	} hw_can_t;
mbed_official	324:406fd2029f23	3570	#pragma pack()
mbed_official	324:406fd2029f23	3571
mbed_official	324:406fd2029f23	3572	/! @brief Macro to access all CAN registers. /
mbed_official	324:406fd2029f23	3573	/! @param x CAN module instance base address. /
mbed_official	324:406fd2029f23	3574	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	3575	* use the '&' operator, like <code>&HW_CAN(CAN0_BASE)</code>. */
mbed_official	324:406fd2029f23	3576	#define HW_CAN(x) ((hw_can_t )(x))
mbed_official	324:406fd2029f23	3577
mbed_official	324:406fd2029f23	3578	#endif /* __HW_CAN_REGISTERS_H__ */
mbed_official	324:406fd2029f23	3579	/* EOF */