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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/device/MK64F12/MK64F12_axbs.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 50 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 51 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 52 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 53 ** System initialization updated.
mbed_official 324:406fd2029f23 54 ** MCG - registers updated.
mbed_official 324:406fd2029f23 55 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 59 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 60 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 63 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 64 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 65 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 66 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 68 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 69 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*
mbed_official 324:406fd2029f23 76 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 77 *
mbed_official 324:406fd2029f23 78 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 79 */
mbed_official 324:406fd2029f23 80 #ifndef __HW_AXBS_REGISTERS_H__
mbed_official 324:406fd2029f23 81 #define __HW_AXBS_REGISTERS_H__
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 #include "MK64F12.h"
mbed_official 324:406fd2029f23 84 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 /*
mbed_official 324:406fd2029f23 87 * MK64F12 AXBS
mbed_official 324:406fd2029f23 88 *
mbed_official 324:406fd2029f23 89 * Crossbar switch
mbed_official 324:406fd2029f23 90 *
mbed_official 324:406fd2029f23 91 * Registers defined in this header file:
mbed_official 324:406fd2029f23 92 * - HW_AXBS_PRSn - Priority Registers Slave
mbed_official 324:406fd2029f23 93 * - HW_AXBS_CRSn - Control Register
mbed_official 324:406fd2029f23 94 * - HW_AXBS_MGPCR0 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 95 * - HW_AXBS_MGPCR1 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 96 * - HW_AXBS_MGPCR2 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 97 * - HW_AXBS_MGPCR3 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 98 * - HW_AXBS_MGPCR4 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 99 * - HW_AXBS_MGPCR5 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 100 *
mbed_official 324:406fd2029f23 101 * - hw_axbs_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 102 */
mbed_official 324:406fd2029f23 103
mbed_official 324:406fd2029f23 104 #define HW_AXBS_INSTANCE_COUNT (1U) /*!< Number of instances of the AXBS module. */
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 /*******************************************************************************
mbed_official 324:406fd2029f23 107 * HW_AXBS_PRSn - Priority Registers Slave
mbed_official 324:406fd2029f23 108 ******************************************************************************/
mbed_official 324:406fd2029f23 109
mbed_official 324:406fd2029f23 110 /*!
mbed_official 324:406fd2029f23 111 * @brief HW_AXBS_PRSn - Priority Registers Slave (RW)
mbed_official 324:406fd2029f23 112 *
mbed_official 324:406fd2029f23 113 * Reset value: 0x00543210U
mbed_official 324:406fd2029f23 114 *
mbed_official 324:406fd2029f23 115 * The priority registers (PRSn) set the priority of each master port on a per
mbed_official 324:406fd2029f23 116 * slave port basis and reside in each slave port. The priority register can be
mbed_official 324:406fd2029f23 117 * accessed only with 32-bit accesses. After the CRSn[RO] bit is set, the PRSn
mbed_official 324:406fd2029f23 118 * register can only be read; attempts to write to it have no effect on PRSn and
mbed_official 324:406fd2029f23 119 * result in a bus-error response to the master initiating the write. Two available
mbed_official 324:406fd2029f23 120 * masters must not be programmed with the same priority level. Attempts to
mbed_official 324:406fd2029f23 121 * program two or more masters with the same priority level result in a bus-error
mbed_official 324:406fd2029f23 122 * response and the PRSn is not updated. Valid values for the Mn priority fields
mbed_official 324:406fd2029f23 123 * depend on which masters are available on the chip. This information can be found in
mbed_official 324:406fd2029f23 124 * the chip-specific information for the crossbar. If the chip contains less
mbed_official 324:406fd2029f23 125 * than five masters, values 0 to 3 are valid. Writing other values will result in
mbed_official 324:406fd2029f23 126 * an error. If the chip contains five or more masters, valid values are 0 to n-1,
mbed_official 324:406fd2029f23 127 * where n is the number of masters attached to the AXBS module. Other values
mbed_official 324:406fd2029f23 128 * will result in an error.
mbed_official 324:406fd2029f23 129 */
mbed_official 324:406fd2029f23 130 typedef union _hw_axbs_prsn
mbed_official 324:406fd2029f23 131 {
mbed_official 324:406fd2029f23 132 uint32_t U;
mbed_official 324:406fd2029f23 133 struct _hw_axbs_prsn_bitfields
mbed_official 324:406fd2029f23 134 {
mbed_official 324:406fd2029f23 135 uint32_t M0 : 3; /*!< [2:0] Master 0 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 136 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 137 uint32_t RESERVED0 : 1; /*!< [3] */
mbed_official 324:406fd2029f23 138 uint32_t M1 : 3; /*!< [6:4] Master 1 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 139 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 140 uint32_t RESERVED1 : 1; /*!< [7] */
mbed_official 324:406fd2029f23 141 uint32_t M2 : 3; /*!< [10:8] Master 2 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 142 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 143 uint32_t RESERVED2 : 1; /*!< [11] */
mbed_official 324:406fd2029f23 144 uint32_t M3 : 3; /*!< [14:12] Master 3 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 145 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 146 uint32_t RESERVED3 : 1; /*!< [15] */
mbed_official 324:406fd2029f23 147 uint32_t M4 : 3; /*!< [18:16] Master 4 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 148 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 149 uint32_t RESERVED4 : 1; /*!< [19] */
mbed_official 324:406fd2029f23 150 uint32_t M5 : 3; /*!< [22:20] Master 5 Priority. Sets the arbitration
mbed_official 324:406fd2029f23 151 * priority for this port on the associated slave port. */
mbed_official 324:406fd2029f23 152 uint32_t RESERVED5 : 9; /*!< [31:23] */
mbed_official 324:406fd2029f23 153 } B;
mbed_official 324:406fd2029f23 154 } hw_axbs_prsn_t;
mbed_official 324:406fd2029f23 155
mbed_official 324:406fd2029f23 156 /*!
mbed_official 324:406fd2029f23 157 * @name Constants and macros for entire AXBS_PRSn register
mbed_official 324:406fd2029f23 158 */
mbed_official 324:406fd2029f23 159 /*@{*/
mbed_official 324:406fd2029f23 160 #define HW_AXBS_PRSn_COUNT (5U)
mbed_official 324:406fd2029f23 161
mbed_official 324:406fd2029f23 162 #define HW_AXBS_PRSn_ADDR(x, n) ((x) + 0x0U + (0x100U * (n)))
mbed_official 324:406fd2029f23 163
mbed_official 324:406fd2029f23 164 #define HW_AXBS_PRSn(x, n) (*(__IO hw_axbs_prsn_t *) HW_AXBS_PRSn_ADDR(x, n))
mbed_official 324:406fd2029f23 165 #define HW_AXBS_PRSn_RD(x, n) (HW_AXBS_PRSn(x, n).U)
mbed_official 324:406fd2029f23 166 #define HW_AXBS_PRSn_WR(x, n, v) (HW_AXBS_PRSn(x, n).U = (v))
mbed_official 324:406fd2029f23 167 #define HW_AXBS_PRSn_SET(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 168 #define HW_AXBS_PRSn_CLR(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 169 #define HW_AXBS_PRSn_TOG(x, n, v) (HW_AXBS_PRSn_WR(x, n, HW_AXBS_PRSn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 170 /*@}*/
mbed_official 324:406fd2029f23 171
mbed_official 324:406fd2029f23 172 /*
mbed_official 324:406fd2029f23 173 * Constants & macros for individual AXBS_PRSn bitfields
mbed_official 324:406fd2029f23 174 */
mbed_official 324:406fd2029f23 175
mbed_official 324:406fd2029f23 176 /*!
mbed_official 324:406fd2029f23 177 * @name Register AXBS_PRSn, field M0[2:0] (RW)
mbed_official 324:406fd2029f23 178 *
mbed_official 324:406fd2029f23 179 * Values:
mbed_official 324:406fd2029f23 180 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 181 * slave port.
mbed_official 324:406fd2029f23 182 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 183 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 184 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 185 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 186 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 187 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 188 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 189 * port.
mbed_official 324:406fd2029f23 190 */
mbed_official 324:406fd2029f23 191 /*@{*/
mbed_official 324:406fd2029f23 192 #define BP_AXBS_PRSn_M0 (0U) /*!< Bit position for AXBS_PRSn_M0. */
mbed_official 324:406fd2029f23 193 #define BM_AXBS_PRSn_M0 (0x00000007U) /*!< Bit mask for AXBS_PRSn_M0. */
mbed_official 324:406fd2029f23 194 #define BS_AXBS_PRSn_M0 (3U) /*!< Bit field size in bits for AXBS_PRSn_M0. */
mbed_official 324:406fd2029f23 195
mbed_official 324:406fd2029f23 196 /*! @brief Read current value of the AXBS_PRSn_M0 field. */
mbed_official 324:406fd2029f23 197 #define BR_AXBS_PRSn_M0(x, n) (HW_AXBS_PRSn(x, n).B.M0)
mbed_official 324:406fd2029f23 198
mbed_official 324:406fd2029f23 199 /*! @brief Format value for bitfield AXBS_PRSn_M0. */
mbed_official 324:406fd2029f23 200 #define BF_AXBS_PRSn_M0(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M0) & BM_AXBS_PRSn_M0)
mbed_official 324:406fd2029f23 201
mbed_official 324:406fd2029f23 202 /*! @brief Set the M0 field to a new value. */
mbed_official 324:406fd2029f23 203 #define BW_AXBS_PRSn_M0(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M0) | BF_AXBS_PRSn_M0(v)))
mbed_official 324:406fd2029f23 204 /*@}*/
mbed_official 324:406fd2029f23 205
mbed_official 324:406fd2029f23 206 /*!
mbed_official 324:406fd2029f23 207 * @name Register AXBS_PRSn, field M1[6:4] (RW)
mbed_official 324:406fd2029f23 208 *
mbed_official 324:406fd2029f23 209 * Values:
mbed_official 324:406fd2029f23 210 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 211 * slave port.
mbed_official 324:406fd2029f23 212 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 213 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 214 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 215 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 216 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 217 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 218 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 219 * port.
mbed_official 324:406fd2029f23 220 */
mbed_official 324:406fd2029f23 221 /*@{*/
mbed_official 324:406fd2029f23 222 #define BP_AXBS_PRSn_M1 (4U) /*!< Bit position for AXBS_PRSn_M1. */
mbed_official 324:406fd2029f23 223 #define BM_AXBS_PRSn_M1 (0x00000070U) /*!< Bit mask for AXBS_PRSn_M1. */
mbed_official 324:406fd2029f23 224 #define BS_AXBS_PRSn_M1 (3U) /*!< Bit field size in bits for AXBS_PRSn_M1. */
mbed_official 324:406fd2029f23 225
mbed_official 324:406fd2029f23 226 /*! @brief Read current value of the AXBS_PRSn_M1 field. */
mbed_official 324:406fd2029f23 227 #define BR_AXBS_PRSn_M1(x, n) (HW_AXBS_PRSn(x, n).B.M1)
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*! @brief Format value for bitfield AXBS_PRSn_M1. */
mbed_official 324:406fd2029f23 230 #define BF_AXBS_PRSn_M1(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M1) & BM_AXBS_PRSn_M1)
mbed_official 324:406fd2029f23 231
mbed_official 324:406fd2029f23 232 /*! @brief Set the M1 field to a new value. */
mbed_official 324:406fd2029f23 233 #define BW_AXBS_PRSn_M1(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M1) | BF_AXBS_PRSn_M1(v)))
mbed_official 324:406fd2029f23 234 /*@}*/
mbed_official 324:406fd2029f23 235
mbed_official 324:406fd2029f23 236 /*!
mbed_official 324:406fd2029f23 237 * @name Register AXBS_PRSn, field M2[10:8] (RW)
mbed_official 324:406fd2029f23 238 *
mbed_official 324:406fd2029f23 239 * Values:
mbed_official 324:406fd2029f23 240 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 241 * slave port.
mbed_official 324:406fd2029f23 242 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 243 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 244 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 245 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 246 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 247 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 248 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 249 * port.
mbed_official 324:406fd2029f23 250 */
mbed_official 324:406fd2029f23 251 /*@{*/
mbed_official 324:406fd2029f23 252 #define BP_AXBS_PRSn_M2 (8U) /*!< Bit position for AXBS_PRSn_M2. */
mbed_official 324:406fd2029f23 253 #define BM_AXBS_PRSn_M2 (0x00000700U) /*!< Bit mask for AXBS_PRSn_M2. */
mbed_official 324:406fd2029f23 254 #define BS_AXBS_PRSn_M2 (3U) /*!< Bit field size in bits for AXBS_PRSn_M2. */
mbed_official 324:406fd2029f23 255
mbed_official 324:406fd2029f23 256 /*! @brief Read current value of the AXBS_PRSn_M2 field. */
mbed_official 324:406fd2029f23 257 #define BR_AXBS_PRSn_M2(x, n) (HW_AXBS_PRSn(x, n).B.M2)
mbed_official 324:406fd2029f23 258
mbed_official 324:406fd2029f23 259 /*! @brief Format value for bitfield AXBS_PRSn_M2. */
mbed_official 324:406fd2029f23 260 #define BF_AXBS_PRSn_M2(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M2) & BM_AXBS_PRSn_M2)
mbed_official 324:406fd2029f23 261
mbed_official 324:406fd2029f23 262 /*! @brief Set the M2 field to a new value. */
mbed_official 324:406fd2029f23 263 #define BW_AXBS_PRSn_M2(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M2) | BF_AXBS_PRSn_M2(v)))
mbed_official 324:406fd2029f23 264 /*@}*/
mbed_official 324:406fd2029f23 265
mbed_official 324:406fd2029f23 266 /*!
mbed_official 324:406fd2029f23 267 * @name Register AXBS_PRSn, field M3[14:12] (RW)
mbed_official 324:406fd2029f23 268 *
mbed_official 324:406fd2029f23 269 * Values:
mbed_official 324:406fd2029f23 270 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 271 * slave port.
mbed_official 324:406fd2029f23 272 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 273 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 274 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 275 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 276 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 277 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 278 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 279 * port.
mbed_official 324:406fd2029f23 280 */
mbed_official 324:406fd2029f23 281 /*@{*/
mbed_official 324:406fd2029f23 282 #define BP_AXBS_PRSn_M3 (12U) /*!< Bit position for AXBS_PRSn_M3. */
mbed_official 324:406fd2029f23 283 #define BM_AXBS_PRSn_M3 (0x00007000U) /*!< Bit mask for AXBS_PRSn_M3. */
mbed_official 324:406fd2029f23 284 #define BS_AXBS_PRSn_M3 (3U) /*!< Bit field size in bits for AXBS_PRSn_M3. */
mbed_official 324:406fd2029f23 285
mbed_official 324:406fd2029f23 286 /*! @brief Read current value of the AXBS_PRSn_M3 field. */
mbed_official 324:406fd2029f23 287 #define BR_AXBS_PRSn_M3(x, n) (HW_AXBS_PRSn(x, n).B.M3)
mbed_official 324:406fd2029f23 288
mbed_official 324:406fd2029f23 289 /*! @brief Format value for bitfield AXBS_PRSn_M3. */
mbed_official 324:406fd2029f23 290 #define BF_AXBS_PRSn_M3(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M3) & BM_AXBS_PRSn_M3)
mbed_official 324:406fd2029f23 291
mbed_official 324:406fd2029f23 292 /*! @brief Set the M3 field to a new value. */
mbed_official 324:406fd2029f23 293 #define BW_AXBS_PRSn_M3(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M3) | BF_AXBS_PRSn_M3(v)))
mbed_official 324:406fd2029f23 294 /*@}*/
mbed_official 324:406fd2029f23 295
mbed_official 324:406fd2029f23 296 /*!
mbed_official 324:406fd2029f23 297 * @name Register AXBS_PRSn, field M4[18:16] (RW)
mbed_official 324:406fd2029f23 298 *
mbed_official 324:406fd2029f23 299 * Values:
mbed_official 324:406fd2029f23 300 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 301 * slave port.
mbed_official 324:406fd2029f23 302 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 303 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 304 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 305 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 306 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 307 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 308 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 309 * port.
mbed_official 324:406fd2029f23 310 */
mbed_official 324:406fd2029f23 311 /*@{*/
mbed_official 324:406fd2029f23 312 #define BP_AXBS_PRSn_M4 (16U) /*!< Bit position for AXBS_PRSn_M4. */
mbed_official 324:406fd2029f23 313 #define BM_AXBS_PRSn_M4 (0x00070000U) /*!< Bit mask for AXBS_PRSn_M4. */
mbed_official 324:406fd2029f23 314 #define BS_AXBS_PRSn_M4 (3U) /*!< Bit field size in bits for AXBS_PRSn_M4. */
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 /*! @brief Read current value of the AXBS_PRSn_M4 field. */
mbed_official 324:406fd2029f23 317 #define BR_AXBS_PRSn_M4(x, n) (HW_AXBS_PRSn(x, n).B.M4)
mbed_official 324:406fd2029f23 318
mbed_official 324:406fd2029f23 319 /*! @brief Format value for bitfield AXBS_PRSn_M4. */
mbed_official 324:406fd2029f23 320 #define BF_AXBS_PRSn_M4(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M4) & BM_AXBS_PRSn_M4)
mbed_official 324:406fd2029f23 321
mbed_official 324:406fd2029f23 322 /*! @brief Set the M4 field to a new value. */
mbed_official 324:406fd2029f23 323 #define BW_AXBS_PRSn_M4(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M4) | BF_AXBS_PRSn_M4(v)))
mbed_official 324:406fd2029f23 324 /*@}*/
mbed_official 324:406fd2029f23 325
mbed_official 324:406fd2029f23 326 /*!
mbed_official 324:406fd2029f23 327 * @name Register AXBS_PRSn, field M5[22:20] (RW)
mbed_official 324:406fd2029f23 328 *
mbed_official 324:406fd2029f23 329 * Values:
mbed_official 324:406fd2029f23 330 * - 000 - This master has level 1, or highest, priority when accessing the
mbed_official 324:406fd2029f23 331 * slave port.
mbed_official 324:406fd2029f23 332 * - 001 - This master has level 2 priority when accessing the slave port.
mbed_official 324:406fd2029f23 333 * - 010 - This master has level 3 priority when accessing the slave port.
mbed_official 324:406fd2029f23 334 * - 011 - This master has level 4 priority when accessing the slave port.
mbed_official 324:406fd2029f23 335 * - 100 - This master has level 5 priority when accessing the slave port.
mbed_official 324:406fd2029f23 336 * - 101 - This master has level 6 priority when accessing the slave port.
mbed_official 324:406fd2029f23 337 * - 110 - This master has level 7 priority when accessing the slave port.
mbed_official 324:406fd2029f23 338 * - 111 - This master has level 8, or lowest, priority when accessing the slave
mbed_official 324:406fd2029f23 339 * port.
mbed_official 324:406fd2029f23 340 */
mbed_official 324:406fd2029f23 341 /*@{*/
mbed_official 324:406fd2029f23 342 #define BP_AXBS_PRSn_M5 (20U) /*!< Bit position for AXBS_PRSn_M5. */
mbed_official 324:406fd2029f23 343 #define BM_AXBS_PRSn_M5 (0x00700000U) /*!< Bit mask for AXBS_PRSn_M5. */
mbed_official 324:406fd2029f23 344 #define BS_AXBS_PRSn_M5 (3U) /*!< Bit field size in bits for AXBS_PRSn_M5. */
mbed_official 324:406fd2029f23 345
mbed_official 324:406fd2029f23 346 /*! @brief Read current value of the AXBS_PRSn_M5 field. */
mbed_official 324:406fd2029f23 347 #define BR_AXBS_PRSn_M5(x, n) (HW_AXBS_PRSn(x, n).B.M5)
mbed_official 324:406fd2029f23 348
mbed_official 324:406fd2029f23 349 /*! @brief Format value for bitfield AXBS_PRSn_M5. */
mbed_official 324:406fd2029f23 350 #define BF_AXBS_PRSn_M5(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_PRSn_M5) & BM_AXBS_PRSn_M5)
mbed_official 324:406fd2029f23 351
mbed_official 324:406fd2029f23 352 /*! @brief Set the M5 field to a new value. */
mbed_official 324:406fd2029f23 353 #define BW_AXBS_PRSn_M5(x, n, v) (HW_AXBS_PRSn_WR(x, n, (HW_AXBS_PRSn_RD(x, n) & ~BM_AXBS_PRSn_M5) | BF_AXBS_PRSn_M5(v)))
mbed_official 324:406fd2029f23 354 /*@}*/
mbed_official 324:406fd2029f23 355 /*******************************************************************************
mbed_official 324:406fd2029f23 356 * HW_AXBS_CRSn - Control Register
mbed_official 324:406fd2029f23 357 ******************************************************************************/
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*!
mbed_official 324:406fd2029f23 360 * @brief HW_AXBS_CRSn - Control Register (RW)
mbed_official 324:406fd2029f23 361 *
mbed_official 324:406fd2029f23 362 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 363 *
mbed_official 324:406fd2029f23 364 * These registers control several features of each slave port and must be
mbed_official 324:406fd2029f23 365 * accessed using 32-bit accesses. After CRSn[RO] is set, the PRSn can only be read;
mbed_official 324:406fd2029f23 366 * attempts to write to it have no effect and result in an error response.
mbed_official 324:406fd2029f23 367 */
mbed_official 324:406fd2029f23 368 typedef union _hw_axbs_crsn
mbed_official 324:406fd2029f23 369 {
mbed_official 324:406fd2029f23 370 uint32_t U;
mbed_official 324:406fd2029f23 371 struct _hw_axbs_crsn_bitfields
mbed_official 324:406fd2029f23 372 {
mbed_official 324:406fd2029f23 373 uint32_t PARK : 3; /*!< [2:0] Park */
mbed_official 324:406fd2029f23 374 uint32_t RESERVED0 : 1; /*!< [3] */
mbed_official 324:406fd2029f23 375 uint32_t PCTL : 2; /*!< [5:4] Parking Control */
mbed_official 324:406fd2029f23 376 uint32_t RESERVED1 : 2; /*!< [7:6] */
mbed_official 324:406fd2029f23 377 uint32_t ARB : 2; /*!< [9:8] Arbitration Mode */
mbed_official 324:406fd2029f23 378 uint32_t RESERVED2 : 20; /*!< [29:10] */
mbed_official 324:406fd2029f23 379 uint32_t HLP : 1; /*!< [30] Halt Low Priority */
mbed_official 324:406fd2029f23 380 uint32_t RO : 1; /*!< [31] Read Only */
mbed_official 324:406fd2029f23 381 } B;
mbed_official 324:406fd2029f23 382 } hw_axbs_crsn_t;
mbed_official 324:406fd2029f23 383
mbed_official 324:406fd2029f23 384 /*!
mbed_official 324:406fd2029f23 385 * @name Constants and macros for entire AXBS_CRSn register
mbed_official 324:406fd2029f23 386 */
mbed_official 324:406fd2029f23 387 /*@{*/
mbed_official 324:406fd2029f23 388 #define HW_AXBS_CRSn_COUNT (5U)
mbed_official 324:406fd2029f23 389
mbed_official 324:406fd2029f23 390 #define HW_AXBS_CRSn_ADDR(x, n) ((x) + 0x10U + (0x100U * (n)))
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392 #define HW_AXBS_CRSn(x, n) (*(__IO hw_axbs_crsn_t *) HW_AXBS_CRSn_ADDR(x, n))
mbed_official 324:406fd2029f23 393 #define HW_AXBS_CRSn_RD(x, n) (HW_AXBS_CRSn(x, n).U)
mbed_official 324:406fd2029f23 394 #define HW_AXBS_CRSn_WR(x, n, v) (HW_AXBS_CRSn(x, n).U = (v))
mbed_official 324:406fd2029f23 395 #define HW_AXBS_CRSn_SET(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 396 #define HW_AXBS_CRSn_CLR(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 397 #define HW_AXBS_CRSn_TOG(x, n, v) (HW_AXBS_CRSn_WR(x, n, HW_AXBS_CRSn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 398 /*@}*/
mbed_official 324:406fd2029f23 399
mbed_official 324:406fd2029f23 400 /*
mbed_official 324:406fd2029f23 401 * Constants & macros for individual AXBS_CRSn bitfields
mbed_official 324:406fd2029f23 402 */
mbed_official 324:406fd2029f23 403
mbed_official 324:406fd2029f23 404 /*!
mbed_official 324:406fd2029f23 405 * @name Register AXBS_CRSn, field PARK[2:0] (RW)
mbed_official 324:406fd2029f23 406 *
mbed_official 324:406fd2029f23 407 * Determines which master port the current slave port parks on when no masters
mbed_official 324:406fd2029f23 408 * are actively making requests and the PCTL bits are cleared. Select only master
mbed_official 324:406fd2029f23 409 * ports that are present on the chip. Otherwise, undefined behavior might occur.
mbed_official 324:406fd2029f23 410 *
mbed_official 324:406fd2029f23 411 * Values:
mbed_official 324:406fd2029f23 412 * - 000 - Park on master port M0
mbed_official 324:406fd2029f23 413 * - 001 - Park on master port M1
mbed_official 324:406fd2029f23 414 * - 010 - Park on master port M2
mbed_official 324:406fd2029f23 415 * - 011 - Park on master port M3
mbed_official 324:406fd2029f23 416 * - 100 - Park on master port M4
mbed_official 324:406fd2029f23 417 * - 101 - Park on master port M5
mbed_official 324:406fd2029f23 418 * - 110 - Park on master port M6
mbed_official 324:406fd2029f23 419 * - 111 - Park on master port M7
mbed_official 324:406fd2029f23 420 */
mbed_official 324:406fd2029f23 421 /*@{*/
mbed_official 324:406fd2029f23 422 #define BP_AXBS_CRSn_PARK (0U) /*!< Bit position for AXBS_CRSn_PARK. */
mbed_official 324:406fd2029f23 423 #define BM_AXBS_CRSn_PARK (0x00000007U) /*!< Bit mask for AXBS_CRSn_PARK. */
mbed_official 324:406fd2029f23 424 #define BS_AXBS_CRSn_PARK (3U) /*!< Bit field size in bits for AXBS_CRSn_PARK. */
mbed_official 324:406fd2029f23 425
mbed_official 324:406fd2029f23 426 /*! @brief Read current value of the AXBS_CRSn_PARK field. */
mbed_official 324:406fd2029f23 427 #define BR_AXBS_CRSn_PARK(x, n) (HW_AXBS_CRSn(x, n).B.PARK)
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429 /*! @brief Format value for bitfield AXBS_CRSn_PARK. */
mbed_official 324:406fd2029f23 430 #define BF_AXBS_CRSn_PARK(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PARK) & BM_AXBS_CRSn_PARK)
mbed_official 324:406fd2029f23 431
mbed_official 324:406fd2029f23 432 /*! @brief Set the PARK field to a new value. */
mbed_official 324:406fd2029f23 433 #define BW_AXBS_CRSn_PARK(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PARK) | BF_AXBS_CRSn_PARK(v)))
mbed_official 324:406fd2029f23 434 /*@}*/
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*!
mbed_official 324:406fd2029f23 437 * @name Register AXBS_CRSn, field PCTL[5:4] (RW)
mbed_official 324:406fd2029f23 438 *
mbed_official 324:406fd2029f23 439 * Determines the slave port's parking control. The low-power park feature
mbed_official 324:406fd2029f23 440 * results in an overall power savings if the slave port is not saturated. However,
mbed_official 324:406fd2029f23 441 * this forces an extra latency clock when any master tries to access the slave
mbed_official 324:406fd2029f23 442 * port while not in use because it is not parked on any master.
mbed_official 324:406fd2029f23 443 *
mbed_official 324:406fd2029f23 444 * Values:
mbed_official 324:406fd2029f23 445 * - 00 - When no master makes a request, the arbiter parks the slave port on
mbed_official 324:406fd2029f23 446 * the master port defined by the PARK field
mbed_official 324:406fd2029f23 447 * - 01 - When no master makes a request, the arbiter parks the slave port on
mbed_official 324:406fd2029f23 448 * the last master to be in control of the slave port
mbed_official 324:406fd2029f23 449 * - 10 - When no master makes a request, the slave port is not parked on a
mbed_official 324:406fd2029f23 450 * master and the arbiter drives all outputs to a constant safe state
mbed_official 324:406fd2029f23 451 * - 11 - Reserved
mbed_official 324:406fd2029f23 452 */
mbed_official 324:406fd2029f23 453 /*@{*/
mbed_official 324:406fd2029f23 454 #define BP_AXBS_CRSn_PCTL (4U) /*!< Bit position for AXBS_CRSn_PCTL. */
mbed_official 324:406fd2029f23 455 #define BM_AXBS_CRSn_PCTL (0x00000030U) /*!< Bit mask for AXBS_CRSn_PCTL. */
mbed_official 324:406fd2029f23 456 #define BS_AXBS_CRSn_PCTL (2U) /*!< Bit field size in bits for AXBS_CRSn_PCTL. */
mbed_official 324:406fd2029f23 457
mbed_official 324:406fd2029f23 458 /*! @brief Read current value of the AXBS_CRSn_PCTL field. */
mbed_official 324:406fd2029f23 459 #define BR_AXBS_CRSn_PCTL(x, n) (HW_AXBS_CRSn(x, n).B.PCTL)
mbed_official 324:406fd2029f23 460
mbed_official 324:406fd2029f23 461 /*! @brief Format value for bitfield AXBS_CRSn_PCTL. */
mbed_official 324:406fd2029f23 462 #define BF_AXBS_CRSn_PCTL(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_PCTL) & BM_AXBS_CRSn_PCTL)
mbed_official 324:406fd2029f23 463
mbed_official 324:406fd2029f23 464 /*! @brief Set the PCTL field to a new value. */
mbed_official 324:406fd2029f23 465 #define BW_AXBS_CRSn_PCTL(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_PCTL) | BF_AXBS_CRSn_PCTL(v)))
mbed_official 324:406fd2029f23 466 /*@}*/
mbed_official 324:406fd2029f23 467
mbed_official 324:406fd2029f23 468 /*!
mbed_official 324:406fd2029f23 469 * @name Register AXBS_CRSn, field ARB[9:8] (RW)
mbed_official 324:406fd2029f23 470 *
mbed_official 324:406fd2029f23 471 * Selects the arbitration policy for the slave port.
mbed_official 324:406fd2029f23 472 *
mbed_official 324:406fd2029f23 473 * Values:
mbed_official 324:406fd2029f23 474 * - 00 - Fixed priority
mbed_official 324:406fd2029f23 475 * - 01 - Round-robin, or rotating, priority
mbed_official 324:406fd2029f23 476 * - 10 - Reserved
mbed_official 324:406fd2029f23 477 * - 11 - Reserved
mbed_official 324:406fd2029f23 478 */
mbed_official 324:406fd2029f23 479 /*@{*/
mbed_official 324:406fd2029f23 480 #define BP_AXBS_CRSn_ARB (8U) /*!< Bit position for AXBS_CRSn_ARB. */
mbed_official 324:406fd2029f23 481 #define BM_AXBS_CRSn_ARB (0x00000300U) /*!< Bit mask for AXBS_CRSn_ARB. */
mbed_official 324:406fd2029f23 482 #define BS_AXBS_CRSn_ARB (2U) /*!< Bit field size in bits for AXBS_CRSn_ARB. */
mbed_official 324:406fd2029f23 483
mbed_official 324:406fd2029f23 484 /*! @brief Read current value of the AXBS_CRSn_ARB field. */
mbed_official 324:406fd2029f23 485 #define BR_AXBS_CRSn_ARB(x, n) (HW_AXBS_CRSn(x, n).B.ARB)
mbed_official 324:406fd2029f23 486
mbed_official 324:406fd2029f23 487 /*! @brief Format value for bitfield AXBS_CRSn_ARB. */
mbed_official 324:406fd2029f23 488 #define BF_AXBS_CRSn_ARB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_ARB) & BM_AXBS_CRSn_ARB)
mbed_official 324:406fd2029f23 489
mbed_official 324:406fd2029f23 490 /*! @brief Set the ARB field to a new value. */
mbed_official 324:406fd2029f23 491 #define BW_AXBS_CRSn_ARB(x, n, v) (HW_AXBS_CRSn_WR(x, n, (HW_AXBS_CRSn_RD(x, n) & ~BM_AXBS_CRSn_ARB) | BF_AXBS_CRSn_ARB(v)))
mbed_official 324:406fd2029f23 492 /*@}*/
mbed_official 324:406fd2029f23 493
mbed_official 324:406fd2029f23 494 /*!
mbed_official 324:406fd2029f23 495 * @name Register AXBS_CRSn, field HLP[30] (RW)
mbed_official 324:406fd2029f23 496 *
mbed_official 324:406fd2029f23 497 * Sets the initial arbitration priority for low power mode requests . Setting
mbed_official 324:406fd2029f23 498 * this bit will not affect the request for low power mode from attaining highest
mbed_official 324:406fd2029f23 499 * priority once it has control of the slave ports.
mbed_official 324:406fd2029f23 500 *
mbed_official 324:406fd2029f23 501 * Values:
mbed_official 324:406fd2029f23 502 * - 0 - The low power mode request has the highest priority for arbitration on
mbed_official 324:406fd2029f23 503 * this slave port
mbed_official 324:406fd2029f23 504 * - 1 - The low power mode request has the lowest initial priority for
mbed_official 324:406fd2029f23 505 * arbitration on this slave port
mbed_official 324:406fd2029f23 506 */
mbed_official 324:406fd2029f23 507 /*@{*/
mbed_official 324:406fd2029f23 508 #define BP_AXBS_CRSn_HLP (30U) /*!< Bit position for AXBS_CRSn_HLP. */
mbed_official 324:406fd2029f23 509 #define BM_AXBS_CRSn_HLP (0x40000000U) /*!< Bit mask for AXBS_CRSn_HLP. */
mbed_official 324:406fd2029f23 510 #define BS_AXBS_CRSn_HLP (1U) /*!< Bit field size in bits for AXBS_CRSn_HLP. */
mbed_official 324:406fd2029f23 511
mbed_official 324:406fd2029f23 512 /*! @brief Read current value of the AXBS_CRSn_HLP field. */
mbed_official 324:406fd2029f23 513 #define BR_AXBS_CRSn_HLP(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP))
mbed_official 324:406fd2029f23 514
mbed_official 324:406fd2029f23 515 /*! @brief Format value for bitfield AXBS_CRSn_HLP. */
mbed_official 324:406fd2029f23 516 #define BF_AXBS_CRSn_HLP(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_HLP) & BM_AXBS_CRSn_HLP)
mbed_official 324:406fd2029f23 517
mbed_official 324:406fd2029f23 518 /*! @brief Set the HLP field to a new value. */
mbed_official 324:406fd2029f23 519 #define BW_AXBS_CRSn_HLP(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_HLP) = (v))
mbed_official 324:406fd2029f23 520 /*@}*/
mbed_official 324:406fd2029f23 521
mbed_official 324:406fd2029f23 522 /*!
mbed_official 324:406fd2029f23 523 * @name Register AXBS_CRSn, field RO[31] (RW)
mbed_official 324:406fd2029f23 524 *
mbed_official 324:406fd2029f23 525 * Forces the slave port's CSRn and PRSn registers to be read-only. After set,
mbed_official 324:406fd2029f23 526 * only a hardware reset clears it.
mbed_official 324:406fd2029f23 527 *
mbed_official 324:406fd2029f23 528 * Values:
mbed_official 324:406fd2029f23 529 * - 0 - The slave port's registers are writeable
mbed_official 324:406fd2029f23 530 * - 1 - The slave port's registers are read-only and cannot be written.
mbed_official 324:406fd2029f23 531 * Attempted writes have no effect on the registers and result in a bus error
mbed_official 324:406fd2029f23 532 * response.
mbed_official 324:406fd2029f23 533 */
mbed_official 324:406fd2029f23 534 /*@{*/
mbed_official 324:406fd2029f23 535 #define BP_AXBS_CRSn_RO (31U) /*!< Bit position for AXBS_CRSn_RO. */
mbed_official 324:406fd2029f23 536 #define BM_AXBS_CRSn_RO (0x80000000U) /*!< Bit mask for AXBS_CRSn_RO. */
mbed_official 324:406fd2029f23 537 #define BS_AXBS_CRSn_RO (1U) /*!< Bit field size in bits for AXBS_CRSn_RO. */
mbed_official 324:406fd2029f23 538
mbed_official 324:406fd2029f23 539 /*! @brief Read current value of the AXBS_CRSn_RO field. */
mbed_official 324:406fd2029f23 540 #define BR_AXBS_CRSn_RO(x, n) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO))
mbed_official 324:406fd2029f23 541
mbed_official 324:406fd2029f23 542 /*! @brief Format value for bitfield AXBS_CRSn_RO. */
mbed_official 324:406fd2029f23 543 #define BF_AXBS_CRSn_RO(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_CRSn_RO) & BM_AXBS_CRSn_RO)
mbed_official 324:406fd2029f23 544
mbed_official 324:406fd2029f23 545 /*! @brief Set the RO field to a new value. */
mbed_official 324:406fd2029f23 546 #define BW_AXBS_CRSn_RO(x, n, v) (BITBAND_ACCESS32(HW_AXBS_CRSn_ADDR(x, n), BP_AXBS_CRSn_RO) = (v))
mbed_official 324:406fd2029f23 547 /*@}*/
mbed_official 324:406fd2029f23 548
mbed_official 324:406fd2029f23 549 /*******************************************************************************
mbed_official 324:406fd2029f23 550 * HW_AXBS_MGPCR0 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 551 ******************************************************************************/
mbed_official 324:406fd2029f23 552
mbed_official 324:406fd2029f23 553 /*!
mbed_official 324:406fd2029f23 554 * @brief HW_AXBS_MGPCR0 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 555 *
mbed_official 324:406fd2029f23 556 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 557 *
mbed_official 324:406fd2029f23 558 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 559 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 560 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 561 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 562 */
mbed_official 324:406fd2029f23 563 typedef union _hw_axbs_mgpcr0
mbed_official 324:406fd2029f23 564 {
mbed_official 324:406fd2029f23 565 uint32_t U;
mbed_official 324:406fd2029f23 566 struct _hw_axbs_mgpcr0_bitfields
mbed_official 324:406fd2029f23 567 {
mbed_official 324:406fd2029f23 568 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 569 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 570 } B;
mbed_official 324:406fd2029f23 571 } hw_axbs_mgpcr0_t;
mbed_official 324:406fd2029f23 572
mbed_official 324:406fd2029f23 573 /*!
mbed_official 324:406fd2029f23 574 * @name Constants and macros for entire AXBS_MGPCR0 register
mbed_official 324:406fd2029f23 575 */
mbed_official 324:406fd2029f23 576 /*@{*/
mbed_official 324:406fd2029f23 577 #define HW_AXBS_MGPCR0_ADDR(x) ((x) + 0x800U)
mbed_official 324:406fd2029f23 578
mbed_official 324:406fd2029f23 579 #define HW_AXBS_MGPCR0(x) (*(__IO hw_axbs_mgpcr0_t *) HW_AXBS_MGPCR0_ADDR(x))
mbed_official 324:406fd2029f23 580 #define HW_AXBS_MGPCR0_RD(x) (HW_AXBS_MGPCR0(x).U)
mbed_official 324:406fd2029f23 581 #define HW_AXBS_MGPCR0_WR(x, v) (HW_AXBS_MGPCR0(x).U = (v))
mbed_official 324:406fd2029f23 582 #define HW_AXBS_MGPCR0_SET(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) | (v)))
mbed_official 324:406fd2029f23 583 #define HW_AXBS_MGPCR0_CLR(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 584 #define HW_AXBS_MGPCR0_TOG(x, v) (HW_AXBS_MGPCR0_WR(x, HW_AXBS_MGPCR0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 585 /*@}*/
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /*
mbed_official 324:406fd2029f23 588 * Constants & macros for individual AXBS_MGPCR0 bitfields
mbed_official 324:406fd2029f23 589 */
mbed_official 324:406fd2029f23 590
mbed_official 324:406fd2029f23 591 /*!
mbed_official 324:406fd2029f23 592 * @name Register AXBS_MGPCR0, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 593 *
mbed_official 324:406fd2029f23 594 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 595 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 596 * accesses.
mbed_official 324:406fd2029f23 597 *
mbed_official 324:406fd2029f23 598 * Values:
mbed_official 324:406fd2029f23 599 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 600 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 601 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 602 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 603 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 604 * - 101 - Reserved
mbed_official 324:406fd2029f23 605 * - 110 - Reserved
mbed_official 324:406fd2029f23 606 * - 111 - Reserved
mbed_official 324:406fd2029f23 607 */
mbed_official 324:406fd2029f23 608 /*@{*/
mbed_official 324:406fd2029f23 609 #define BP_AXBS_MGPCR0_AULB (0U) /*!< Bit position for AXBS_MGPCR0_AULB. */
mbed_official 324:406fd2029f23 610 #define BM_AXBS_MGPCR0_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR0_AULB. */
mbed_official 324:406fd2029f23 611 #define BS_AXBS_MGPCR0_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR0_AULB. */
mbed_official 324:406fd2029f23 612
mbed_official 324:406fd2029f23 613 /*! @brief Read current value of the AXBS_MGPCR0_AULB field. */
mbed_official 324:406fd2029f23 614 #define BR_AXBS_MGPCR0_AULB(x) (HW_AXBS_MGPCR0(x).B.AULB)
mbed_official 324:406fd2029f23 615
mbed_official 324:406fd2029f23 616 /*! @brief Format value for bitfield AXBS_MGPCR0_AULB. */
mbed_official 324:406fd2029f23 617 #define BF_AXBS_MGPCR0_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR0_AULB) & BM_AXBS_MGPCR0_AULB)
mbed_official 324:406fd2029f23 618
mbed_official 324:406fd2029f23 619 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 620 #define BW_AXBS_MGPCR0_AULB(x, v) (HW_AXBS_MGPCR0_WR(x, (HW_AXBS_MGPCR0_RD(x) & ~BM_AXBS_MGPCR0_AULB) | BF_AXBS_MGPCR0_AULB(v)))
mbed_official 324:406fd2029f23 621 /*@}*/
mbed_official 324:406fd2029f23 622
mbed_official 324:406fd2029f23 623 /*******************************************************************************
mbed_official 324:406fd2029f23 624 * HW_AXBS_MGPCR1 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 625 ******************************************************************************/
mbed_official 324:406fd2029f23 626
mbed_official 324:406fd2029f23 627 /*!
mbed_official 324:406fd2029f23 628 * @brief HW_AXBS_MGPCR1 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 629 *
mbed_official 324:406fd2029f23 630 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 631 *
mbed_official 324:406fd2029f23 632 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 633 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 634 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 635 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 636 */
mbed_official 324:406fd2029f23 637 typedef union _hw_axbs_mgpcr1
mbed_official 324:406fd2029f23 638 {
mbed_official 324:406fd2029f23 639 uint32_t U;
mbed_official 324:406fd2029f23 640 struct _hw_axbs_mgpcr1_bitfields
mbed_official 324:406fd2029f23 641 {
mbed_official 324:406fd2029f23 642 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 643 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 644 } B;
mbed_official 324:406fd2029f23 645 } hw_axbs_mgpcr1_t;
mbed_official 324:406fd2029f23 646
mbed_official 324:406fd2029f23 647 /*!
mbed_official 324:406fd2029f23 648 * @name Constants and macros for entire AXBS_MGPCR1 register
mbed_official 324:406fd2029f23 649 */
mbed_official 324:406fd2029f23 650 /*@{*/
mbed_official 324:406fd2029f23 651 #define HW_AXBS_MGPCR1_ADDR(x) ((x) + 0x900U)
mbed_official 324:406fd2029f23 652
mbed_official 324:406fd2029f23 653 #define HW_AXBS_MGPCR1(x) (*(__IO hw_axbs_mgpcr1_t *) HW_AXBS_MGPCR1_ADDR(x))
mbed_official 324:406fd2029f23 654 #define HW_AXBS_MGPCR1_RD(x) (HW_AXBS_MGPCR1(x).U)
mbed_official 324:406fd2029f23 655 #define HW_AXBS_MGPCR1_WR(x, v) (HW_AXBS_MGPCR1(x).U = (v))
mbed_official 324:406fd2029f23 656 #define HW_AXBS_MGPCR1_SET(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) | (v)))
mbed_official 324:406fd2029f23 657 #define HW_AXBS_MGPCR1_CLR(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 658 #define HW_AXBS_MGPCR1_TOG(x, v) (HW_AXBS_MGPCR1_WR(x, HW_AXBS_MGPCR1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 659 /*@}*/
mbed_official 324:406fd2029f23 660
mbed_official 324:406fd2029f23 661 /*
mbed_official 324:406fd2029f23 662 * Constants & macros for individual AXBS_MGPCR1 bitfields
mbed_official 324:406fd2029f23 663 */
mbed_official 324:406fd2029f23 664
mbed_official 324:406fd2029f23 665 /*!
mbed_official 324:406fd2029f23 666 * @name Register AXBS_MGPCR1, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 667 *
mbed_official 324:406fd2029f23 668 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 669 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 670 * accesses.
mbed_official 324:406fd2029f23 671 *
mbed_official 324:406fd2029f23 672 * Values:
mbed_official 324:406fd2029f23 673 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 674 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 675 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 676 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 677 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 678 * - 101 - Reserved
mbed_official 324:406fd2029f23 679 * - 110 - Reserved
mbed_official 324:406fd2029f23 680 * - 111 - Reserved
mbed_official 324:406fd2029f23 681 */
mbed_official 324:406fd2029f23 682 /*@{*/
mbed_official 324:406fd2029f23 683 #define BP_AXBS_MGPCR1_AULB (0U) /*!< Bit position for AXBS_MGPCR1_AULB. */
mbed_official 324:406fd2029f23 684 #define BM_AXBS_MGPCR1_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR1_AULB. */
mbed_official 324:406fd2029f23 685 #define BS_AXBS_MGPCR1_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR1_AULB. */
mbed_official 324:406fd2029f23 686
mbed_official 324:406fd2029f23 687 /*! @brief Read current value of the AXBS_MGPCR1_AULB field. */
mbed_official 324:406fd2029f23 688 #define BR_AXBS_MGPCR1_AULB(x) (HW_AXBS_MGPCR1(x).B.AULB)
mbed_official 324:406fd2029f23 689
mbed_official 324:406fd2029f23 690 /*! @brief Format value for bitfield AXBS_MGPCR1_AULB. */
mbed_official 324:406fd2029f23 691 #define BF_AXBS_MGPCR1_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR1_AULB) & BM_AXBS_MGPCR1_AULB)
mbed_official 324:406fd2029f23 692
mbed_official 324:406fd2029f23 693 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 694 #define BW_AXBS_MGPCR1_AULB(x, v) (HW_AXBS_MGPCR1_WR(x, (HW_AXBS_MGPCR1_RD(x) & ~BM_AXBS_MGPCR1_AULB) | BF_AXBS_MGPCR1_AULB(v)))
mbed_official 324:406fd2029f23 695 /*@}*/
mbed_official 324:406fd2029f23 696
mbed_official 324:406fd2029f23 697 /*******************************************************************************
mbed_official 324:406fd2029f23 698 * HW_AXBS_MGPCR2 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 699 ******************************************************************************/
mbed_official 324:406fd2029f23 700
mbed_official 324:406fd2029f23 701 /*!
mbed_official 324:406fd2029f23 702 * @brief HW_AXBS_MGPCR2 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 703 *
mbed_official 324:406fd2029f23 704 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 705 *
mbed_official 324:406fd2029f23 706 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 707 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 708 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 709 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 710 */
mbed_official 324:406fd2029f23 711 typedef union _hw_axbs_mgpcr2
mbed_official 324:406fd2029f23 712 {
mbed_official 324:406fd2029f23 713 uint32_t U;
mbed_official 324:406fd2029f23 714 struct _hw_axbs_mgpcr2_bitfields
mbed_official 324:406fd2029f23 715 {
mbed_official 324:406fd2029f23 716 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 717 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 718 } B;
mbed_official 324:406fd2029f23 719 } hw_axbs_mgpcr2_t;
mbed_official 324:406fd2029f23 720
mbed_official 324:406fd2029f23 721 /*!
mbed_official 324:406fd2029f23 722 * @name Constants and macros for entire AXBS_MGPCR2 register
mbed_official 324:406fd2029f23 723 */
mbed_official 324:406fd2029f23 724 /*@{*/
mbed_official 324:406fd2029f23 725 #define HW_AXBS_MGPCR2_ADDR(x) ((x) + 0xA00U)
mbed_official 324:406fd2029f23 726
mbed_official 324:406fd2029f23 727 #define HW_AXBS_MGPCR2(x) (*(__IO hw_axbs_mgpcr2_t *) HW_AXBS_MGPCR2_ADDR(x))
mbed_official 324:406fd2029f23 728 #define HW_AXBS_MGPCR2_RD(x) (HW_AXBS_MGPCR2(x).U)
mbed_official 324:406fd2029f23 729 #define HW_AXBS_MGPCR2_WR(x, v) (HW_AXBS_MGPCR2(x).U = (v))
mbed_official 324:406fd2029f23 730 #define HW_AXBS_MGPCR2_SET(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) | (v)))
mbed_official 324:406fd2029f23 731 #define HW_AXBS_MGPCR2_CLR(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 732 #define HW_AXBS_MGPCR2_TOG(x, v) (HW_AXBS_MGPCR2_WR(x, HW_AXBS_MGPCR2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 733 /*@}*/
mbed_official 324:406fd2029f23 734
mbed_official 324:406fd2029f23 735 /*
mbed_official 324:406fd2029f23 736 * Constants & macros for individual AXBS_MGPCR2 bitfields
mbed_official 324:406fd2029f23 737 */
mbed_official 324:406fd2029f23 738
mbed_official 324:406fd2029f23 739 /*!
mbed_official 324:406fd2029f23 740 * @name Register AXBS_MGPCR2, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 741 *
mbed_official 324:406fd2029f23 742 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 743 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 744 * accesses.
mbed_official 324:406fd2029f23 745 *
mbed_official 324:406fd2029f23 746 * Values:
mbed_official 324:406fd2029f23 747 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 748 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 749 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 750 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 751 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 752 * - 101 - Reserved
mbed_official 324:406fd2029f23 753 * - 110 - Reserved
mbed_official 324:406fd2029f23 754 * - 111 - Reserved
mbed_official 324:406fd2029f23 755 */
mbed_official 324:406fd2029f23 756 /*@{*/
mbed_official 324:406fd2029f23 757 #define BP_AXBS_MGPCR2_AULB (0U) /*!< Bit position for AXBS_MGPCR2_AULB. */
mbed_official 324:406fd2029f23 758 #define BM_AXBS_MGPCR2_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR2_AULB. */
mbed_official 324:406fd2029f23 759 #define BS_AXBS_MGPCR2_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR2_AULB. */
mbed_official 324:406fd2029f23 760
mbed_official 324:406fd2029f23 761 /*! @brief Read current value of the AXBS_MGPCR2_AULB field. */
mbed_official 324:406fd2029f23 762 #define BR_AXBS_MGPCR2_AULB(x) (HW_AXBS_MGPCR2(x).B.AULB)
mbed_official 324:406fd2029f23 763
mbed_official 324:406fd2029f23 764 /*! @brief Format value for bitfield AXBS_MGPCR2_AULB. */
mbed_official 324:406fd2029f23 765 #define BF_AXBS_MGPCR2_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR2_AULB) & BM_AXBS_MGPCR2_AULB)
mbed_official 324:406fd2029f23 766
mbed_official 324:406fd2029f23 767 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 768 #define BW_AXBS_MGPCR2_AULB(x, v) (HW_AXBS_MGPCR2_WR(x, (HW_AXBS_MGPCR2_RD(x) & ~BM_AXBS_MGPCR2_AULB) | BF_AXBS_MGPCR2_AULB(v)))
mbed_official 324:406fd2029f23 769 /*@}*/
mbed_official 324:406fd2029f23 770
mbed_official 324:406fd2029f23 771 /*******************************************************************************
mbed_official 324:406fd2029f23 772 * HW_AXBS_MGPCR3 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 773 ******************************************************************************/
mbed_official 324:406fd2029f23 774
mbed_official 324:406fd2029f23 775 /*!
mbed_official 324:406fd2029f23 776 * @brief HW_AXBS_MGPCR3 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 777 *
mbed_official 324:406fd2029f23 778 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 779 *
mbed_official 324:406fd2029f23 780 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 781 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 782 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 783 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 784 */
mbed_official 324:406fd2029f23 785 typedef union _hw_axbs_mgpcr3
mbed_official 324:406fd2029f23 786 {
mbed_official 324:406fd2029f23 787 uint32_t U;
mbed_official 324:406fd2029f23 788 struct _hw_axbs_mgpcr3_bitfields
mbed_official 324:406fd2029f23 789 {
mbed_official 324:406fd2029f23 790 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 791 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 792 } B;
mbed_official 324:406fd2029f23 793 } hw_axbs_mgpcr3_t;
mbed_official 324:406fd2029f23 794
mbed_official 324:406fd2029f23 795 /*!
mbed_official 324:406fd2029f23 796 * @name Constants and macros for entire AXBS_MGPCR3 register
mbed_official 324:406fd2029f23 797 */
mbed_official 324:406fd2029f23 798 /*@{*/
mbed_official 324:406fd2029f23 799 #define HW_AXBS_MGPCR3_ADDR(x) ((x) + 0xB00U)
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 #define HW_AXBS_MGPCR3(x) (*(__IO hw_axbs_mgpcr3_t *) HW_AXBS_MGPCR3_ADDR(x))
mbed_official 324:406fd2029f23 802 #define HW_AXBS_MGPCR3_RD(x) (HW_AXBS_MGPCR3(x).U)
mbed_official 324:406fd2029f23 803 #define HW_AXBS_MGPCR3_WR(x, v) (HW_AXBS_MGPCR3(x).U = (v))
mbed_official 324:406fd2029f23 804 #define HW_AXBS_MGPCR3_SET(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) | (v)))
mbed_official 324:406fd2029f23 805 #define HW_AXBS_MGPCR3_CLR(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 806 #define HW_AXBS_MGPCR3_TOG(x, v) (HW_AXBS_MGPCR3_WR(x, HW_AXBS_MGPCR3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 807 /*@}*/
mbed_official 324:406fd2029f23 808
mbed_official 324:406fd2029f23 809 /*
mbed_official 324:406fd2029f23 810 * Constants & macros for individual AXBS_MGPCR3 bitfields
mbed_official 324:406fd2029f23 811 */
mbed_official 324:406fd2029f23 812
mbed_official 324:406fd2029f23 813 /*!
mbed_official 324:406fd2029f23 814 * @name Register AXBS_MGPCR3, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 815 *
mbed_official 324:406fd2029f23 816 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 817 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 818 * accesses.
mbed_official 324:406fd2029f23 819 *
mbed_official 324:406fd2029f23 820 * Values:
mbed_official 324:406fd2029f23 821 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 822 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 823 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 824 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 825 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 826 * - 101 - Reserved
mbed_official 324:406fd2029f23 827 * - 110 - Reserved
mbed_official 324:406fd2029f23 828 * - 111 - Reserved
mbed_official 324:406fd2029f23 829 */
mbed_official 324:406fd2029f23 830 /*@{*/
mbed_official 324:406fd2029f23 831 #define BP_AXBS_MGPCR3_AULB (0U) /*!< Bit position for AXBS_MGPCR3_AULB. */
mbed_official 324:406fd2029f23 832 #define BM_AXBS_MGPCR3_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR3_AULB. */
mbed_official 324:406fd2029f23 833 #define BS_AXBS_MGPCR3_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR3_AULB. */
mbed_official 324:406fd2029f23 834
mbed_official 324:406fd2029f23 835 /*! @brief Read current value of the AXBS_MGPCR3_AULB field. */
mbed_official 324:406fd2029f23 836 #define BR_AXBS_MGPCR3_AULB(x) (HW_AXBS_MGPCR3(x).B.AULB)
mbed_official 324:406fd2029f23 837
mbed_official 324:406fd2029f23 838 /*! @brief Format value for bitfield AXBS_MGPCR3_AULB. */
mbed_official 324:406fd2029f23 839 #define BF_AXBS_MGPCR3_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR3_AULB) & BM_AXBS_MGPCR3_AULB)
mbed_official 324:406fd2029f23 840
mbed_official 324:406fd2029f23 841 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 842 #define BW_AXBS_MGPCR3_AULB(x, v) (HW_AXBS_MGPCR3_WR(x, (HW_AXBS_MGPCR3_RD(x) & ~BM_AXBS_MGPCR3_AULB) | BF_AXBS_MGPCR3_AULB(v)))
mbed_official 324:406fd2029f23 843 /*@}*/
mbed_official 324:406fd2029f23 844
mbed_official 324:406fd2029f23 845 /*******************************************************************************
mbed_official 324:406fd2029f23 846 * HW_AXBS_MGPCR4 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 847 ******************************************************************************/
mbed_official 324:406fd2029f23 848
mbed_official 324:406fd2029f23 849 /*!
mbed_official 324:406fd2029f23 850 * @brief HW_AXBS_MGPCR4 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 851 *
mbed_official 324:406fd2029f23 852 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 853 *
mbed_official 324:406fd2029f23 854 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 855 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 856 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 857 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 858 */
mbed_official 324:406fd2029f23 859 typedef union _hw_axbs_mgpcr4
mbed_official 324:406fd2029f23 860 {
mbed_official 324:406fd2029f23 861 uint32_t U;
mbed_official 324:406fd2029f23 862 struct _hw_axbs_mgpcr4_bitfields
mbed_official 324:406fd2029f23 863 {
mbed_official 324:406fd2029f23 864 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 865 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 866 } B;
mbed_official 324:406fd2029f23 867 } hw_axbs_mgpcr4_t;
mbed_official 324:406fd2029f23 868
mbed_official 324:406fd2029f23 869 /*!
mbed_official 324:406fd2029f23 870 * @name Constants and macros for entire AXBS_MGPCR4 register
mbed_official 324:406fd2029f23 871 */
mbed_official 324:406fd2029f23 872 /*@{*/
mbed_official 324:406fd2029f23 873 #define HW_AXBS_MGPCR4_ADDR(x) ((x) + 0xC00U)
mbed_official 324:406fd2029f23 874
mbed_official 324:406fd2029f23 875 #define HW_AXBS_MGPCR4(x) (*(__IO hw_axbs_mgpcr4_t *) HW_AXBS_MGPCR4_ADDR(x))
mbed_official 324:406fd2029f23 876 #define HW_AXBS_MGPCR4_RD(x) (HW_AXBS_MGPCR4(x).U)
mbed_official 324:406fd2029f23 877 #define HW_AXBS_MGPCR4_WR(x, v) (HW_AXBS_MGPCR4(x).U = (v))
mbed_official 324:406fd2029f23 878 #define HW_AXBS_MGPCR4_SET(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) | (v)))
mbed_official 324:406fd2029f23 879 #define HW_AXBS_MGPCR4_CLR(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 880 #define HW_AXBS_MGPCR4_TOG(x, v) (HW_AXBS_MGPCR4_WR(x, HW_AXBS_MGPCR4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 881 /*@}*/
mbed_official 324:406fd2029f23 882
mbed_official 324:406fd2029f23 883 /*
mbed_official 324:406fd2029f23 884 * Constants & macros for individual AXBS_MGPCR4 bitfields
mbed_official 324:406fd2029f23 885 */
mbed_official 324:406fd2029f23 886
mbed_official 324:406fd2029f23 887 /*!
mbed_official 324:406fd2029f23 888 * @name Register AXBS_MGPCR4, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 889 *
mbed_official 324:406fd2029f23 890 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 891 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 892 * accesses.
mbed_official 324:406fd2029f23 893 *
mbed_official 324:406fd2029f23 894 * Values:
mbed_official 324:406fd2029f23 895 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 896 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 897 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 898 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 899 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 900 * - 101 - Reserved
mbed_official 324:406fd2029f23 901 * - 110 - Reserved
mbed_official 324:406fd2029f23 902 * - 111 - Reserved
mbed_official 324:406fd2029f23 903 */
mbed_official 324:406fd2029f23 904 /*@{*/
mbed_official 324:406fd2029f23 905 #define BP_AXBS_MGPCR4_AULB (0U) /*!< Bit position for AXBS_MGPCR4_AULB. */
mbed_official 324:406fd2029f23 906 #define BM_AXBS_MGPCR4_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR4_AULB. */
mbed_official 324:406fd2029f23 907 #define BS_AXBS_MGPCR4_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR4_AULB. */
mbed_official 324:406fd2029f23 908
mbed_official 324:406fd2029f23 909 /*! @brief Read current value of the AXBS_MGPCR4_AULB field. */
mbed_official 324:406fd2029f23 910 #define BR_AXBS_MGPCR4_AULB(x) (HW_AXBS_MGPCR4(x).B.AULB)
mbed_official 324:406fd2029f23 911
mbed_official 324:406fd2029f23 912 /*! @brief Format value for bitfield AXBS_MGPCR4_AULB. */
mbed_official 324:406fd2029f23 913 #define BF_AXBS_MGPCR4_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR4_AULB) & BM_AXBS_MGPCR4_AULB)
mbed_official 324:406fd2029f23 914
mbed_official 324:406fd2029f23 915 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 916 #define BW_AXBS_MGPCR4_AULB(x, v) (HW_AXBS_MGPCR4_WR(x, (HW_AXBS_MGPCR4_RD(x) & ~BM_AXBS_MGPCR4_AULB) | BF_AXBS_MGPCR4_AULB(v)))
mbed_official 324:406fd2029f23 917 /*@}*/
mbed_official 324:406fd2029f23 918
mbed_official 324:406fd2029f23 919 /*******************************************************************************
mbed_official 324:406fd2029f23 920 * HW_AXBS_MGPCR5 - Master General Purpose Control Register
mbed_official 324:406fd2029f23 921 ******************************************************************************/
mbed_official 324:406fd2029f23 922
mbed_official 324:406fd2029f23 923 /*!
mbed_official 324:406fd2029f23 924 * @brief HW_AXBS_MGPCR5 - Master General Purpose Control Register (RW)
mbed_official 324:406fd2029f23 925 *
mbed_official 324:406fd2029f23 926 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 927 *
mbed_official 324:406fd2029f23 928 * The MGPCR controls only whether the master's undefined length burst accesses
mbed_official 324:406fd2029f23 929 * are allowed to complete uninterrupted or whether they can be broken by
mbed_official 324:406fd2029f23 930 * requests from higher priority masters. The MGPCR can be accessed only in Supervisor
mbed_official 324:406fd2029f23 931 * mode with 32-bit accesses.
mbed_official 324:406fd2029f23 932 */
mbed_official 324:406fd2029f23 933 typedef union _hw_axbs_mgpcr5
mbed_official 324:406fd2029f23 934 {
mbed_official 324:406fd2029f23 935 uint32_t U;
mbed_official 324:406fd2029f23 936 struct _hw_axbs_mgpcr5_bitfields
mbed_official 324:406fd2029f23 937 {
mbed_official 324:406fd2029f23 938 uint32_t AULB : 3; /*!< [2:0] Arbitrates On Undefined Length Bursts */
mbed_official 324:406fd2029f23 939 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 940 } B;
mbed_official 324:406fd2029f23 941 } hw_axbs_mgpcr5_t;
mbed_official 324:406fd2029f23 942
mbed_official 324:406fd2029f23 943 /*!
mbed_official 324:406fd2029f23 944 * @name Constants and macros for entire AXBS_MGPCR5 register
mbed_official 324:406fd2029f23 945 */
mbed_official 324:406fd2029f23 946 /*@{*/
mbed_official 324:406fd2029f23 947 #define HW_AXBS_MGPCR5_ADDR(x) ((x) + 0xD00U)
mbed_official 324:406fd2029f23 948
mbed_official 324:406fd2029f23 949 #define HW_AXBS_MGPCR5(x) (*(__IO hw_axbs_mgpcr5_t *) HW_AXBS_MGPCR5_ADDR(x))
mbed_official 324:406fd2029f23 950 #define HW_AXBS_MGPCR5_RD(x) (HW_AXBS_MGPCR5(x).U)
mbed_official 324:406fd2029f23 951 #define HW_AXBS_MGPCR5_WR(x, v) (HW_AXBS_MGPCR5(x).U = (v))
mbed_official 324:406fd2029f23 952 #define HW_AXBS_MGPCR5_SET(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) | (v)))
mbed_official 324:406fd2029f23 953 #define HW_AXBS_MGPCR5_CLR(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 954 #define HW_AXBS_MGPCR5_TOG(x, v) (HW_AXBS_MGPCR5_WR(x, HW_AXBS_MGPCR5_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 955 /*@}*/
mbed_official 324:406fd2029f23 956
mbed_official 324:406fd2029f23 957 /*
mbed_official 324:406fd2029f23 958 * Constants & macros for individual AXBS_MGPCR5 bitfields
mbed_official 324:406fd2029f23 959 */
mbed_official 324:406fd2029f23 960
mbed_official 324:406fd2029f23 961 /*!
mbed_official 324:406fd2029f23 962 * @name Register AXBS_MGPCR5, field AULB[2:0] (RW)
mbed_official 324:406fd2029f23 963 *
mbed_official 324:406fd2029f23 964 * Determines whether, and when, the crossbar switch arbitrates away the slave
mbed_official 324:406fd2029f23 965 * port the master owns when the master is performing undefined length burst
mbed_official 324:406fd2029f23 966 * accesses.
mbed_official 324:406fd2029f23 967 *
mbed_official 324:406fd2029f23 968 * Values:
mbed_official 324:406fd2029f23 969 * - 000 - No arbitration is allowed during an undefined length burst
mbed_official 324:406fd2029f23 970 * - 001 - Arbitration is allowed at any time during an undefined length burst
mbed_official 324:406fd2029f23 971 * - 010 - Arbitration is allowed after four beats of an undefined length burst
mbed_official 324:406fd2029f23 972 * - 011 - Arbitration is allowed after eight beats of an undefined length burst
mbed_official 324:406fd2029f23 973 * - 100 - Arbitration is allowed after 16 beats of an undefined length burst
mbed_official 324:406fd2029f23 974 * - 101 - Reserved
mbed_official 324:406fd2029f23 975 * - 110 - Reserved
mbed_official 324:406fd2029f23 976 * - 111 - Reserved
mbed_official 324:406fd2029f23 977 */
mbed_official 324:406fd2029f23 978 /*@{*/
mbed_official 324:406fd2029f23 979 #define BP_AXBS_MGPCR5_AULB (0U) /*!< Bit position for AXBS_MGPCR5_AULB. */
mbed_official 324:406fd2029f23 980 #define BM_AXBS_MGPCR5_AULB (0x00000007U) /*!< Bit mask for AXBS_MGPCR5_AULB. */
mbed_official 324:406fd2029f23 981 #define BS_AXBS_MGPCR5_AULB (3U) /*!< Bit field size in bits for AXBS_MGPCR5_AULB. */
mbed_official 324:406fd2029f23 982
mbed_official 324:406fd2029f23 983 /*! @brief Read current value of the AXBS_MGPCR5_AULB field. */
mbed_official 324:406fd2029f23 984 #define BR_AXBS_MGPCR5_AULB(x) (HW_AXBS_MGPCR5(x).B.AULB)
mbed_official 324:406fd2029f23 985
mbed_official 324:406fd2029f23 986 /*! @brief Format value for bitfield AXBS_MGPCR5_AULB. */
mbed_official 324:406fd2029f23 987 #define BF_AXBS_MGPCR5_AULB(v) ((uint32_t)((uint32_t)(v) << BP_AXBS_MGPCR5_AULB) & BM_AXBS_MGPCR5_AULB)
mbed_official 324:406fd2029f23 988
mbed_official 324:406fd2029f23 989 /*! @brief Set the AULB field to a new value. */
mbed_official 324:406fd2029f23 990 #define BW_AXBS_MGPCR5_AULB(x, v) (HW_AXBS_MGPCR5_WR(x, (HW_AXBS_MGPCR5_RD(x) & ~BM_AXBS_MGPCR5_AULB) | BF_AXBS_MGPCR5_AULB(v)))
mbed_official 324:406fd2029f23 991 /*@}*/
mbed_official 324:406fd2029f23 992
mbed_official 324:406fd2029f23 993 /*******************************************************************************
mbed_official 324:406fd2029f23 994 * hw_axbs_t - module struct
mbed_official 324:406fd2029f23 995 ******************************************************************************/
mbed_official 324:406fd2029f23 996 /*!
mbed_official 324:406fd2029f23 997 * @brief All AXBS module registers.
mbed_official 324:406fd2029f23 998 */
mbed_official 324:406fd2029f23 999 #pragma pack(1)
mbed_official 324:406fd2029f23 1000 typedef struct _hw_axbs
mbed_official 324:406fd2029f23 1001 {
mbed_official 324:406fd2029f23 1002 struct {
mbed_official 324:406fd2029f23 1003 __IO hw_axbs_prsn_t PRSn; /*!< [0x0] Priority Registers Slave */
mbed_official 324:406fd2029f23 1004 uint8_t _reserved0[12];
mbed_official 324:406fd2029f23 1005 __IO hw_axbs_crsn_t CRSn; /*!< [0x10] Control Register */
mbed_official 324:406fd2029f23 1006 uint8_t _reserved1[236];
mbed_official 324:406fd2029f23 1007 } SLAVE[5];
mbed_official 324:406fd2029f23 1008 uint8_t _reserved0[768];
mbed_official 324:406fd2029f23 1009 __IO hw_axbs_mgpcr0_t MGPCR0; /*!< [0x800] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1010 uint8_t _reserved1[252];
mbed_official 324:406fd2029f23 1011 __IO hw_axbs_mgpcr1_t MGPCR1; /*!< [0x900] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1012 uint8_t _reserved2[252];
mbed_official 324:406fd2029f23 1013 __IO hw_axbs_mgpcr2_t MGPCR2; /*!< [0xA00] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1014 uint8_t _reserved3[252];
mbed_official 324:406fd2029f23 1015 __IO hw_axbs_mgpcr3_t MGPCR3; /*!< [0xB00] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1016 uint8_t _reserved4[252];
mbed_official 324:406fd2029f23 1017 __IO hw_axbs_mgpcr4_t MGPCR4; /*!< [0xC00] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1018 uint8_t _reserved5[252];
mbed_official 324:406fd2029f23 1019 __IO hw_axbs_mgpcr5_t MGPCR5; /*!< [0xD00] Master General Purpose Control Register */
mbed_official 324:406fd2029f23 1020 } hw_axbs_t;
mbed_official 324:406fd2029f23 1021 #pragma pack()
mbed_official 324:406fd2029f23 1022
mbed_official 324:406fd2029f23 1023 /*! @brief Macro to access all AXBS registers. */
mbed_official 324:406fd2029f23 1024 /*! @param x AXBS module instance base address. */
mbed_official 324:406fd2029f23 1025 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 1026 * use the '&' operator, like <code>&HW_AXBS(AXBS_BASE)</code>. */
mbed_official 324:406fd2029f23 1027 #define HW_AXBS(x) (*(hw_axbs_t *)(x))
mbed_official 324:406fd2029f23 1028
mbed_official 324:406fd2029f23 1029 #endif /* __HW_AXBS_REGISTERS_H__ */
mbed_official 324:406fd2029f23 1030 /* EOF */