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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/fsl_bitaccess.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 4 ** Build: b140604
mbed_official 324:406fd2029f23 5 **
mbed_official 324:406fd2029f23 6 ** Abstract:
mbed_official 324:406fd2029f23 7 ** Register bit field access macros.
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 10 ** All rights reserved.
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 13 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 16 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 19 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 20 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 23 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 24 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 25 **
mbed_official 324:406fd2029f23 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 36 **
mbed_official 324:406fd2029f23 37 ** http: www.freescale.com
mbed_official 324:406fd2029f23 38 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 39 **
mbed_official 324:406fd2029f23 40 ** Revisions:
mbed_official 324:406fd2029f23 41 ** - rev. 1.0 (2013-08-12)
mbed_official 324:406fd2029f23 42 ** Initial version.
mbed_official 324:406fd2029f23 43 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 44 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 45 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 46 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 47 ** System initialization updated.
mbed_official 324:406fd2029f23 48 ** MCG - registers updated.
mbed_official 324:406fd2029f23 49 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 50 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 51 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 52 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 53 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 54 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 55 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 56 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 57 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 58 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 59 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 60 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 61 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 62 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 63 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 64 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 65 **
mbed_official 324:406fd2029f23 66 ** ###################################################################
mbed_official 324:406fd2029f23 67 */
mbed_official 324:406fd2029f23 68
mbed_official 324:406fd2029f23 69
mbed_official 324:406fd2029f23 70 #ifndef _FSL_BITACCESS_H
mbed_official 324:406fd2029f23 71 #define _FSL_BITACCESS_H 1
mbed_official 324:406fd2029f23 72
mbed_official 324:406fd2029f23 73 #include <stdint.h>
mbed_official 324:406fd2029f23 74 #include <stdlib.h>
mbed_official 324:406fd2029f23 75
mbed_official 324:406fd2029f23 76 /**
mbed_official 324:406fd2029f23 77 * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region
mbed_official 324:406fd2029f23 78 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
mbed_official 324:406fd2029f23 79 * @param Reg Register to access.
mbed_official 324:406fd2029f23 80 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 81 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 82 */
mbed_official 324:406fd2029f23 83 #define BITBAND_ACCESS32(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
mbed_official 324:406fd2029f23 84
mbed_official 324:406fd2029f23 85 /**
mbed_official 324:406fd2029f23 86 * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region
mbed_official 324:406fd2029f23 87 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
mbed_official 324:406fd2029f23 88 * @param Reg Register to access.
mbed_official 324:406fd2029f23 89 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 90 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 91 */
mbed_official 324:406fd2029f23 92 #define BITBAND_ACCESS16(Reg,Bit) (*((uint16_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
mbed_official 324:406fd2029f23 93
mbed_official 324:406fd2029f23 94 /**
mbed_official 324:406fd2029f23 95 * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region
mbed_official 324:406fd2029f23 96 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
mbed_official 324:406fd2029f23 97 * @param Reg Register to access.
mbed_official 324:406fd2029f23 98 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 99 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 100 */
mbed_official 324:406fd2029f23 101 #define BITBAND_ACCESS8(Reg,Bit) (*((uint8_t volatile*)(0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
mbed_official 324:406fd2029f23 102
mbed_official 324:406fd2029f23 103 /*
mbed_official 324:406fd2029f23 104 * Macros for single instance registers
mbed_official 324:406fd2029f23 105 */
mbed_official 324:406fd2029f23 106
mbed_official 324:406fd2029f23 107 #define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field)
mbed_official 324:406fd2029f23 108 #define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field)
mbed_official 324:406fd2029f23 109 #define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field)
mbed_official 324:406fd2029f23 110
mbed_official 324:406fd2029f23 111 #define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 112 #define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 113 #define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 114
mbed_official 324:406fd2029f23 115 #define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
mbed_official 324:406fd2029f23 116 #define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym
mbed_official 324:406fd2029f23 117
mbed_official 324:406fd2029f23 118 #define BF_RD(reg, field) HW_##reg.B.field
mbed_official 324:406fd2029f23 119 #define BF_WR(reg, field, v) BW_##reg##_##field(v)
mbed_official 324:406fd2029f23 120
mbed_official 324:406fd2029f23 121 #define BF_CS1(reg, f1, v1) \
mbed_official 324:406fd2029f23 122 (HW_##reg##_CLR(BM_##reg##_##f1), \
mbed_official 324:406fd2029f23 123 HW_##reg##_SET(BF_##reg##_##f1(v1)))
mbed_official 324:406fd2029f23 124
mbed_official 324:406fd2029f23 125 #define BF_CS2(reg, f1, v1, f2, v2) \
mbed_official 324:406fd2029f23 126 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 127 BM_##reg##_##f2), \
mbed_official 324:406fd2029f23 128 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 129 BF_##reg##_##f2(v2)))
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
mbed_official 324:406fd2029f23 132 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 133 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 134 BM_##reg##_##f3), \
mbed_official 324:406fd2029f23 135 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 136 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 137 BF_##reg##_##f3(v3)))
mbed_official 324:406fd2029f23 138
mbed_official 324:406fd2029f23 139 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
mbed_official 324:406fd2029f23 140 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 141 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 142 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 143 BM_##reg##_##f4), \
mbed_official 324:406fd2029f23 144 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 145 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 146 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 147 BF_##reg##_##f4(v4)))
mbed_official 324:406fd2029f23 148
mbed_official 324:406fd2029f23 149 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
mbed_official 324:406fd2029f23 150 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 151 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 152 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 153 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 154 BM_##reg##_##f5), \
mbed_official 324:406fd2029f23 155 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 156 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 157 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 158 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 159 BF_##reg##_##f5(v5)))
mbed_official 324:406fd2029f23 160
mbed_official 324:406fd2029f23 161 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
mbed_official 324:406fd2029f23 162 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 163 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 164 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 165 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 166 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 167 BM_##reg##_##f6), \
mbed_official 324:406fd2029f23 168 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 169 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 170 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 171 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 172 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 173 BF_##reg##_##f6(v6)))
mbed_official 324:406fd2029f23 174
mbed_official 324:406fd2029f23 175 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
mbed_official 324:406fd2029f23 176 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 177 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 178 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 179 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 180 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 181 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 182 BM_##reg##_##f7), \
mbed_official 324:406fd2029f23 183 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 184 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 185 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 186 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 187 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 188 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 189 BF_##reg##_##f7(v7)))
mbed_official 324:406fd2029f23 190
mbed_official 324:406fd2029f23 191 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
mbed_official 324:406fd2029f23 192 (HW_##reg##_CLR(BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 193 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 194 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 195 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 196 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 197 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 198 BM_##reg##_##f7 | \
mbed_official 324:406fd2029f23 199 BM_##reg##_##f8), \
mbed_official 324:406fd2029f23 200 HW_##reg##_SET(BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 201 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 202 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 203 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 204 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 205 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 206 BF_##reg##_##f7(v7) | \
mbed_official 324:406fd2029f23 207 BF_##reg##_##f8(v8)))
mbed_official 324:406fd2029f23 208
mbed_official 324:406fd2029f23 209 /*
mbed_official 324:406fd2029f23 210 * Macros for multiple instance registers
mbed_official 324:406fd2029f23 211 */
mbed_official 324:406fd2029f23 212
mbed_official 324:406fd2029f23 213 #define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 214 #define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 215 #define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 216
mbed_official 324:406fd2029f23 217 #define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 218 #define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 219 #define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 220
mbed_official 324:406fd2029f23 221 #define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
mbed_official 324:406fd2029f23 222 #define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym
mbed_official 324:406fd2029f23 223
mbed_official 324:406fd2029f23 224 #define BF_RDn(reg, n, field) HW_##reg(n).B.field
mbed_official 324:406fd2029f23 225 #define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v)
mbed_official 324:406fd2029f23 226
mbed_official 324:406fd2029f23 227 #define BF_CS1n(reg, n, f1, v1) \
mbed_official 324:406fd2029f23 228 (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \
mbed_official 324:406fd2029f23 229 HW_##reg##_SET(n, (BF_##reg##_##f1(v1))))
mbed_official 324:406fd2029f23 230
mbed_official 324:406fd2029f23 231 #define BF_CS2n(reg, n, f1, v1, f2, v2) \
mbed_official 324:406fd2029f23 232 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 233 BM_##reg##_##f2)), \
mbed_official 324:406fd2029f23 234 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 235 BF_##reg##_##f2(v2))))
mbed_official 324:406fd2029f23 236
mbed_official 324:406fd2029f23 237 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
mbed_official 324:406fd2029f23 238 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 239 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 240 BM_##reg##_##f3)), \
mbed_official 324:406fd2029f23 241 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 242 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 243 BF_##reg##_##f3(v3))))
mbed_official 324:406fd2029f23 244
mbed_official 324:406fd2029f23 245 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
mbed_official 324:406fd2029f23 246 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 247 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 248 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 249 BM_##reg##_##f4)), \
mbed_official 324:406fd2029f23 250 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 251 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 252 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 253 BF_##reg##_##f4(v4))))
mbed_official 324:406fd2029f23 254
mbed_official 324:406fd2029f23 255 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
mbed_official 324:406fd2029f23 256 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 257 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 258 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 259 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 260 BM_##reg##_##f5)), \
mbed_official 324:406fd2029f23 261 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 262 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 263 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 264 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 265 BF_##reg##_##f5(v5))))
mbed_official 324:406fd2029f23 266
mbed_official 324:406fd2029f23 267 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
mbed_official 324:406fd2029f23 268 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 269 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 270 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 271 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 272 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 273 BM_##reg##_##f6)), \
mbed_official 324:406fd2029f23 274 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 275 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 276 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 277 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 278 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 279 BF_##reg##_##f6(v6))))
mbed_official 324:406fd2029f23 280
mbed_official 324:406fd2029f23 281 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
mbed_official 324:406fd2029f23 282 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 283 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 284 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 285 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 286 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 287 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 288 BM_##reg##_##f7)), \
mbed_official 324:406fd2029f23 289 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 290 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 291 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 292 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 293 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 294 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 295 BF_##reg##_##f7(v7))))
mbed_official 324:406fd2029f23 296
mbed_official 324:406fd2029f23 297 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
mbed_official 324:406fd2029f23 298 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 299 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 300 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 301 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 302 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 303 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 304 BM_##reg##_##f7 | \
mbed_official 324:406fd2029f23 305 BM_##reg##_##f8)), \
mbed_official 324:406fd2029f23 306 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 307 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 308 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 309 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 310 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 311 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 312 BF_##reg##_##f7(v7) | \
mbed_official 324:406fd2029f23 313 BF_##reg##_##f8(v8))))
mbed_official 324:406fd2029f23 314
mbed_official 324:406fd2029f23 315 /*
mbed_official 324:406fd2029f23 316 * Macros for single instance MULTI-BLOCK registers
mbed_official 324:406fd2029f23 317 */
mbed_official 324:406fd2029f23 318
mbed_official 324:406fd2029f23 319 #define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field)
mbed_official 324:406fd2029f23 320 #define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field)
mbed_official 324:406fd2029f23 321 #define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field)
mbed_official 324:406fd2029f23 322
mbed_official 324:406fd2029f23 323 #define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 324 #define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 325 #define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 326
mbed_official 324:406fd2029f23 327 #define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
mbed_official 324:406fd2029f23 328 #define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym
mbed_official 324:406fd2029f23 329
mbed_official 324:406fd2029f23 330 #define BFn_RD(reg, blk, field) HW_##reg(blk).B.field
mbed_official 324:406fd2029f23 331 #define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v)
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 #define BFn_CS1(reg, blk, f1, v1) \
mbed_official 324:406fd2029f23 334 (HW_##reg##_CLR(blk, BM_##reg##_##f1), \
mbed_official 324:406fd2029f23 335 HW_##reg##_SET(blk, BF_##reg##_##f1(v1)))
mbed_official 324:406fd2029f23 336
mbed_official 324:406fd2029f23 337 #define BFn_CS2(reg, blk, f1, v1, f2, v2) \
mbed_official 324:406fd2029f23 338 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 339 BM_##reg##_##f2), \
mbed_official 324:406fd2029f23 340 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 341 BF_##reg##_##f2(v2)))
mbed_official 324:406fd2029f23 342
mbed_official 324:406fd2029f23 343 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \
mbed_official 324:406fd2029f23 344 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 345 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 346 BM_##reg##_##f3), \
mbed_official 324:406fd2029f23 347 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 348 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 349 BF_##reg##_##f3(v3)))
mbed_official 324:406fd2029f23 350
mbed_official 324:406fd2029f23 351 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \
mbed_official 324:406fd2029f23 352 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 353 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 354 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 355 BM_##reg##_##f4), \
mbed_official 324:406fd2029f23 356 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 357 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 358 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 359 BF_##reg##_##f4(v4)))
mbed_official 324:406fd2029f23 360
mbed_official 324:406fd2029f23 361 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
mbed_official 324:406fd2029f23 362 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 363 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 364 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 365 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 366 BM_##reg##_##f5), \
mbed_official 324:406fd2029f23 367 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 368 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 369 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 370 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 371 BF_##reg##_##f5(v5)))
mbed_official 324:406fd2029f23 372
mbed_official 324:406fd2029f23 373 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
mbed_official 324:406fd2029f23 374 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 375 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 376 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 377 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 378 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 379 BM_##reg##_##f6), \
mbed_official 324:406fd2029f23 380 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 381 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 382 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 383 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 384 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 385 BF_##reg##_##f6(v6)))
mbed_official 324:406fd2029f23 386
mbed_official 324:406fd2029f23 387 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
mbed_official 324:406fd2029f23 388 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 389 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 390 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 391 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 392 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 393 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 394 BM_##reg##_##f7), \
mbed_official 324:406fd2029f23 395 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 396 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 397 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 398 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 399 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 400 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 401 BF_##reg##_##f7(v7)))
mbed_official 324:406fd2029f23 402
mbed_official 324:406fd2029f23 403 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
mbed_official 324:406fd2029f23 404 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 405 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 406 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 407 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 408 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 409 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 410 BM_##reg##_##f7 | \
mbed_official 324:406fd2029f23 411 BM_##reg##_##f8), \
mbed_official 324:406fd2029f23 412 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 413 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 414 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 415 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 416 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 417 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 418 BF_##reg##_##f7(v7) | \
mbed_official 324:406fd2029f23 419 BF_##reg##_##f8(v8)))
mbed_official 324:406fd2029f23 420
mbed_official 324:406fd2029f23 421 /*
mbed_official 324:406fd2029f23 422 * Macros for MULTI-BLOCK multiple instance registers
mbed_official 324:406fd2029f23 423 */
mbed_official 324:406fd2029f23 424
mbed_official 324:406fd2029f23 425 #define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 426 #define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 427 #define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field)
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429 #define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 430 #define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 431 #define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v))
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 #define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym)
mbed_official 324:406fd2029f23 434 #define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 #define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field
mbed_official 324:406fd2029f23 437 #define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v)
mbed_official 324:406fd2029f23 438
mbed_official 324:406fd2029f23 439 #define BFn_CS1n(reg, blk, n, f1, v1) \
mbed_official 324:406fd2029f23 440 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \
mbed_official 324:406fd2029f23 441 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1))))
mbed_official 324:406fd2029f23 442
mbed_official 324:406fd2029f23 443 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \
mbed_official 324:406fd2029f23 444 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 445 BM_##reg##_##f2)), \
mbed_official 324:406fd2029f23 446 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 447 BF_##reg##_##f2(v2))))
mbed_official 324:406fd2029f23 448
mbed_official 324:406fd2029f23 449 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \
mbed_official 324:406fd2029f23 450 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 451 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 452 BM_##reg##_##f3)), \
mbed_official 324:406fd2029f23 453 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 454 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 455 BF_##reg##_##f3(v3))))
mbed_official 324:406fd2029f23 456
mbed_official 324:406fd2029f23 457 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \
mbed_official 324:406fd2029f23 458 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 459 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 460 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 461 BM_##reg##_##f4)), \
mbed_official 324:406fd2029f23 462 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 463 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 464 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 465 BF_##reg##_##f4(v4))))
mbed_official 324:406fd2029f23 466
mbed_official 324:406fd2029f23 467 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
mbed_official 324:406fd2029f23 468 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 469 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 470 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 471 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 472 BM_##reg##_##f5)), \
mbed_official 324:406fd2029f23 473 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 474 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 475 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 476 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 477 BF_##reg##_##f5(v5))))
mbed_official 324:406fd2029f23 478
mbed_official 324:406fd2029f23 479 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
mbed_official 324:406fd2029f23 480 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 481 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 482 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 483 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 484 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 485 BM_##reg##_##f6)), \
mbed_official 324:406fd2029f23 486 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 487 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 488 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 489 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 490 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 491 BF_##reg##_##f6(v6))))
mbed_official 324:406fd2029f23 492
mbed_official 324:406fd2029f23 493 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
mbed_official 324:406fd2029f23 494 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 495 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 496 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 497 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 498 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 499 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 500 BM_##reg##_##f7)), \
mbed_official 324:406fd2029f23 501 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 502 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 503 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 504 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 505 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 506 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 507 BF_##reg##_##f7(v7))))
mbed_official 324:406fd2029f23 508
mbed_official 324:406fd2029f23 509 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
mbed_official 324:406fd2029f23 510 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \
mbed_official 324:406fd2029f23 511 BM_##reg##_##f2 | \
mbed_official 324:406fd2029f23 512 BM_##reg##_##f3 | \
mbed_official 324:406fd2029f23 513 BM_##reg##_##f4 | \
mbed_official 324:406fd2029f23 514 BM_##reg##_##f5 | \
mbed_official 324:406fd2029f23 515 BM_##reg##_##f6 | \
mbed_official 324:406fd2029f23 516 BM_##reg##_##f7 | \
mbed_official 324:406fd2029f23 517 BM_##reg##_##f8)), \
mbed_official 324:406fd2029f23 518 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \
mbed_official 324:406fd2029f23 519 BF_##reg##_##f2(v2) | \
mbed_official 324:406fd2029f23 520 BF_##reg##_##f3(v3) | \
mbed_official 324:406fd2029f23 521 BF_##reg##_##f4(v4) | \
mbed_official 324:406fd2029f23 522 BF_##reg##_##f5(v5) | \
mbed_official 324:406fd2029f23 523 BF_##reg##_##f6(v6) | \
mbed_official 324:406fd2029f23 524 BF_##reg##_##f7(v7) | \
mbed_official 324:406fd2029f23 525 BF_##reg##_##f8(v8))))
mbed_official 324:406fd2029f23 526
mbed_official 324:406fd2029f23 527 #endif /* _FSL_BITACCESS_H */
mbed_official 324:406fd2029f23 528
mbed_official 324:406fd2029f23 529 /******************************************************************************/