mbed official
mbed library sources
Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more
Superseded
This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/smc/fsl_smc_features.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
- Parent:
- 149:1fb5f62b92bd
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Version: rev. 1.0, 2014-05-14 |
| mbed_official | 324:406fd2029f23 | 4 | ** Build: b140515 |
| mbed_official | 324:406fd2029f23 | 5 | ** |
| mbed_official | 324:406fd2029f23 | 6 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 7 | ** Chip specific module features. |
| mbed_official | 324:406fd2029f23 | 8 | ** |
| mbed_official | 324:406fd2029f23 | 9 | ** Copyright: 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 10 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 13 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 16 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 20 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 21 | ** |
| mbed_official | 324:406fd2029f23 | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 23 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 24 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 25 | ** |
| mbed_official | 324:406fd2029f23 | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 36 | ** |
| mbed_official | 324:406fd2029f23 | 37 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 38 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 39 | ** |
| mbed_official | 324:406fd2029f23 | 40 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 41 | ** - rev. 1.0 (2014-05-14) |
| mbed_official | 324:406fd2029f23 | 42 | ** Customer release. |
| mbed_official | 324:406fd2029f23 | 43 | ** |
| mbed_official | 324:406fd2029f23 | 44 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 45 | */ |
| mbed_official | 324:406fd2029f23 | 46 | |
| mbed_official | 324:406fd2029f23 | 47 | #if !defined(__FSL_SMC_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 48 | #define __FSL_SMC_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 49 | |
| mbed_official | 324:406fd2029f23 | 50 | #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ |
| mbed_official | 324:406fd2029f23 | 51 | defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || \ |
| mbed_official | 324:406fd2029f23 | 52 | defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || \ |
| mbed_official | 324:406fd2029f23 | 53 | defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || \ |
| mbed_official | 324:406fd2029f23 | 54 | defined(CPU_MK22FN512VLL12) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || \ |
| mbed_official | 324:406fd2029f23 | 55 | defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || defined(CPU_MKV31F128VLH10) || \ |
| mbed_official | 324:406fd2029f23 | 56 | defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ |
| mbed_official | 324:406fd2029f23 | 57 | defined(CPU_MKV31F512VLL12) |
| mbed_official | 324:406fd2029f23 | 58 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 59 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
| mbed_official | 324:406fd2029f23 | 60 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 61 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
| mbed_official | 324:406fd2029f23 | 62 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 63 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 64 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 65 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
| mbed_official | 324:406fd2029f23 | 66 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 67 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) |
| mbed_official | 324:406fd2029f23 | 68 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 69 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
| mbed_official | 324:406fd2029f23 | 70 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 71 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) |
| mbed_official | 324:406fd2029f23 | 72 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 73 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 74 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 75 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) |
| mbed_official | 324:406fd2029f23 | 76 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 77 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
| mbed_official | 324:406fd2029f23 | 78 | #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ |
| mbed_official | 324:406fd2029f23 | 79 | defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ |
| mbed_official | 324:406fd2029f23 | 80 | defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ |
| mbed_official | 324:406fd2029f23 | 81 | defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ |
| mbed_official | 324:406fd2029f23 | 82 | defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ |
| mbed_official | 324:406fd2029f23 | 83 | defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ |
| mbed_official | 324:406fd2029f23 | 84 | defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ |
| mbed_official | 324:406fd2029f23 | 85 | defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ |
| mbed_official | 324:406fd2029f23 | 86 | defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ |
| mbed_official | 324:406fd2029f23 | 87 | defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ |
| mbed_official | 324:406fd2029f23 | 88 | defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) |
| mbed_official | 324:406fd2029f23 | 89 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 90 | #define FSL_FEATURE_SMC_HAS_PSTOPO (0) |
| mbed_official | 324:406fd2029f23 | 91 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 92 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
| mbed_official | 324:406fd2029f23 | 93 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 94 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 95 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 96 | #define FSL_FEATURE_SMC_HAS_LPWUI (1) |
| mbed_official | 324:406fd2029f23 | 97 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 98 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
| mbed_official | 324:406fd2029f23 | 99 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 100 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) |
| mbed_official | 324:406fd2029f23 | 101 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 102 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) |
| mbed_official | 324:406fd2029f23 | 103 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 104 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 105 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 106 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
| mbed_official | 324:406fd2029f23 | 107 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 108 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
| mbed_official | 324:406fd2029f23 | 109 | #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ |
| mbed_official | 324:406fd2029f23 | 110 | defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) |
| mbed_official | 324:406fd2029f23 | 111 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 112 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
| mbed_official | 324:406fd2029f23 | 113 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 114 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
| mbed_official | 324:406fd2029f23 | 115 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 116 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 117 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 118 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
| mbed_official | 324:406fd2029f23 | 119 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 120 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) |
| mbed_official | 324:406fd2029f23 | 121 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 122 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
| mbed_official | 324:406fd2029f23 | 123 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 124 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) |
| mbed_official | 324:406fd2029f23 | 125 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 126 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) |
| mbed_official | 324:406fd2029f23 | 127 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 128 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) |
| mbed_official | 324:406fd2029f23 | 129 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 130 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
| mbed_official | 324:406fd2029f23 | 131 | #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 324:406fd2029f23 | 132 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 324:406fd2029f23 | 133 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 134 | #define FSL_FEATURE_SMC_HAS_PSTOPO (0) |
| mbed_official | 324:406fd2029f23 | 135 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 136 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
| mbed_official | 324:406fd2029f23 | 137 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 138 | #define FSL_FEATURE_SMC_HAS_PORPO (0) |
| mbed_official | 324:406fd2029f23 | 139 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 140 | #define FSL_FEATURE_SMC_HAS_LPWUI (1) |
| mbed_official | 324:406fd2029f23 | 141 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 142 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
| mbed_official | 324:406fd2029f23 | 143 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 144 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) |
| mbed_official | 324:406fd2029f23 | 145 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 146 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) |
| mbed_official | 324:406fd2029f23 | 147 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 148 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 149 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 150 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
| mbed_official | 324:406fd2029f23 | 151 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 152 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
| mbed_official | 324:406fd2029f23 | 153 | #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ |
| mbed_official | 324:406fd2029f23 | 154 | defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) |
| mbed_official | 324:406fd2029f23 | 155 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 156 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
| mbed_official | 324:406fd2029f23 | 157 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 158 | #define FSL_FEATURE_SMC_HAS_LPOPO (1) |
| mbed_official | 324:406fd2029f23 | 159 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 160 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 161 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 162 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
| mbed_official | 324:406fd2029f23 | 163 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 164 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
| mbed_official | 324:406fd2029f23 | 165 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 166 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
| mbed_official | 324:406fd2029f23 | 167 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 168 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) |
| mbed_official | 324:406fd2029f23 | 169 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 170 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 171 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 172 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
| mbed_official | 324:406fd2029f23 | 173 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 174 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) |
| mbed_official | 324:406fd2029f23 | 175 | #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ |
| mbed_official | 324:406fd2029f23 | 176 | defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 177 | defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL13Z64VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 178 | defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || defined(CPU_MKL13Z128VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 179 | defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || defined(CPU_MKL13Z256VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 180 | defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || defined(CPU_MKL23Z64VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 181 | defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || defined(CPU_MKL23Z128VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 182 | defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || defined(CPU_MKL23Z256VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 183 | defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || defined(CPU_MKL25Z32VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 184 | defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 185 | defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 186 | defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL26Z256VLK4) || \ |
| mbed_official | 324:406fd2029f23 | 187 | defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || \ |
| mbed_official | 324:406fd2029f23 | 188 | defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 189 | defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 190 | defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 191 | defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
| mbed_official | 324:406fd2029f23 | 192 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 193 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
| mbed_official | 324:406fd2029f23 | 194 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 195 | #define FSL_FEATURE_SMC_HAS_LPOPO (0) |
| mbed_official | 324:406fd2029f23 | 196 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 197 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 198 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 199 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
| mbed_official | 324:406fd2029f23 | 200 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 201 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
| mbed_official | 324:406fd2029f23 | 202 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 203 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
| mbed_official | 324:406fd2029f23 | 204 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 205 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) |
| mbed_official | 324:406fd2029f23 | 206 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 207 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 208 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 209 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) |
| mbed_official | 324:406fd2029f23 | 210 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 211 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) |
| mbed_official | 324:406fd2029f23 | 212 | #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ |
| mbed_official | 324:406fd2029f23 | 213 | defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 214 | defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 215 | defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 216 | defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) |
| mbed_official | 324:406fd2029f23 | 217 | /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ |
| mbed_official | 324:406fd2029f23 | 218 | #define FSL_FEATURE_SMC_HAS_PSTOPO (1) |
| mbed_official | 324:406fd2029f23 | 219 | /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ |
| mbed_official | 324:406fd2029f23 | 220 | #define FSL_FEATURE_SMC_HAS_LPOPO (1) |
| mbed_official | 324:406fd2029f23 | 221 | /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ |
| mbed_official | 324:406fd2029f23 | 222 | #define FSL_FEATURE_SMC_HAS_PORPO (1) |
| mbed_official | 324:406fd2029f23 | 223 | /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ |
| mbed_official | 324:406fd2029f23 | 224 | #define FSL_FEATURE_SMC_HAS_LPWUI (0) |
| mbed_official | 324:406fd2029f23 | 225 | /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ |
| mbed_official | 324:406fd2029f23 | 226 | #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) |
| mbed_official | 324:406fd2029f23 | 227 | /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 228 | #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) |
| mbed_official | 324:406fd2029f23 | 229 | /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ |
| mbed_official | 324:406fd2029f23 | 230 | #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) |
| mbed_official | 324:406fd2029f23 | 231 | /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ |
| mbed_official | 324:406fd2029f23 | 232 | #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) |
| mbed_official | 324:406fd2029f23 | 233 | /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ |
| mbed_official | 324:406fd2029f23 | 234 | #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) |
| mbed_official | 324:406fd2029f23 | 235 | /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ |
| mbed_official | 324:406fd2029f23 | 236 | #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) |
| mbed_official | 146:f64d43ff0c18 | 237 | #else |
| mbed_official | 324:406fd2029f23 | 238 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 239 | #endif |
| mbed_official | 146:f64d43ff0c18 | 240 | |
| mbed_official | 324:406fd2029f23 | 241 | #endif /* __FSL_SMC_FEATURES_H__ */ |
| mbed_official | 324:406fd2029f23 | 242 | |
| mbed_official | 146:f64d43ff0c18 | 243 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 244 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 245 | ******************************************************************************/ |
