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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sim/fsl_sim_features.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
- Parent:
- 149:1fb5f62b92bd
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Version: rev. 1.0, 2014-05-14 |
| mbed_official | 324:406fd2029f23 | 4 | ** Build: b140515 |
| mbed_official | 324:406fd2029f23 | 5 | ** |
| mbed_official | 324:406fd2029f23 | 6 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 7 | ** Chip specific module features. |
| mbed_official | 324:406fd2029f23 | 8 | ** |
| mbed_official | 324:406fd2029f23 | 9 | ** Copyright: 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 10 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 13 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 16 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 20 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 21 | ** |
| mbed_official | 324:406fd2029f23 | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 23 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 24 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 25 | ** |
| mbed_official | 324:406fd2029f23 | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 36 | ** |
| mbed_official | 324:406fd2029f23 | 37 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 38 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 39 | ** |
| mbed_official | 324:406fd2029f23 | 40 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 41 | ** - rev. 1.0 (2014-05-14) |
| mbed_official | 324:406fd2029f23 | 42 | ** Customer release. |
| mbed_official | 324:406fd2029f23 | 43 | ** |
| mbed_official | 324:406fd2029f23 | 44 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 45 | */ |
| mbed_official | 324:406fd2029f23 | 46 | |
| mbed_official | 324:406fd2029f23 | 47 | #if !defined(__FSL_SIM_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 48 | #define __FSL_SIM_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 49 | |
| mbed_official | 324:406fd2029f23 | 50 | #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ |
| mbed_official | 324:406fd2029f23 | 51 | defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) |
| mbed_official | 324:406fd2029f23 | 52 | /* @brief Has USB FS divider. */ |
| mbed_official | 146:f64d43ff0c18 | 53 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 54 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 55 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 56 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 57 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 58 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 59 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 60 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 61 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 62 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 63 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 64 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 65 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 66 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 67 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 68 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 69 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 70 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 146:f64d43ff0c18 | 71 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 72 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 146:f64d43ff0c18 | 73 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 74 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 146:f64d43ff0c18 | 75 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 76 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 146:f64d43ff0c18 | 77 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 78 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 79 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 80 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 146:f64d43ff0c18 | 81 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 82 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 83 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 84 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 85 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 86 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 87 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 88 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 89 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 90 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 91 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 92 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 93 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 94 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 95 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 96 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 97 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 98 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 99 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 100 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 101 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 102 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 103 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 104 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 105 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 106 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 107 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 108 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 109 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 110 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 111 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 112 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 113 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 114 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 115 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 116 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 117 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 118 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 146:f64d43ff0c18 | 119 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 120 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 121 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 122 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 123 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 124 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 125 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 126 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 127 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 128 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 129 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 130 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 131 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 132 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 133 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 134 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 135 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 136 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 137 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 138 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 139 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 140 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 141 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 142 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 143 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 144 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 145 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 146 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 147 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 148 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 149 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 150 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 151 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 152 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 153 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 154 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 155 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 156 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 157 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 158 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 159 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 160 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 161 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 162 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 163 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 164 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 165 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 166 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 167 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 168 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 169 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 170 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 171 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 172 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 173 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 174 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 175 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 176 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 177 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 178 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 179 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 180 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 181 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 182 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 183 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 184 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 185 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 186 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 187 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 188 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 189 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 190 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 191 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 192 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 193 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 194 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 195 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 196 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 197 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 198 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 199 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 200 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 201 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 202 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 203 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 204 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 205 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 206 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 207 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 208 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 209 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 210 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 211 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 212 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 213 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 214 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 215 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 216 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 217 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 218 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 219 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 220 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 221 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 222 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 223 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 224 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 225 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 226 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 227 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 228 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 229 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 230 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 231 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 232 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 233 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 234 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 235 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 236 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 237 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 238 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 239 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 240 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 241 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 242 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 243 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 244 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 245 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 246 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 247 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 248 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 249 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 250 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 251 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 252 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 253 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 254 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 255 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 256 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 257 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 258 | #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) |
| mbed_official | 324:406fd2029f23 | 259 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 260 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 261 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 262 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 263 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 264 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 265 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 266 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 267 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 268 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 269 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 270 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 271 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 272 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 273 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 274 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 275 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 276 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 277 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 278 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 279 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 280 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 281 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 282 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 283 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 284 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 285 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 286 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 287 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 288 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 289 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 290 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 291 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 292 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 293 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 294 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 295 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 296 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 297 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 298 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 299 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 300 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 301 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 302 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 303 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 304 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 305 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 306 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 307 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 308 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 309 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 310 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 311 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 312 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 313 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 314 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 315 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 316 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 317 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 318 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 319 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 320 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 321 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 322 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 323 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 324 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 325 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 326 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 327 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 328 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 329 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 330 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 331 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 332 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 333 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 334 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 335 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 336 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 337 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 338 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 339 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 340 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 341 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 342 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 343 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 344 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 345 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 346 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 347 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 348 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 349 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 350 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 351 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 352 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 353 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 354 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 355 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 356 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 357 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 358 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 359 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 360 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 361 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 362 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 363 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 364 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 365 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 366 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 367 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 368 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 369 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 370 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 371 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 372 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 373 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 374 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 375 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 376 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 377 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 378 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 379 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 380 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 381 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 382 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 383 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 384 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 385 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 386 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 387 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 388 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 389 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 390 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 391 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 392 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 393 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 394 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 395 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 396 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 397 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 398 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 399 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 400 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 401 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 402 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 403 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 146:f64d43ff0c18 | 404 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 405 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 406 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 407 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 408 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 409 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 410 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 411 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 412 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 413 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 414 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 415 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 416 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 417 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 418 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 419 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 420 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 421 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 422 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 423 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 424 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 425 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 426 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 427 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 428 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 429 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 430 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 431 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 432 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 433 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 434 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 435 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 436 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 437 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 438 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 439 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 440 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 441 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 442 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 443 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 444 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 445 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 446 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 447 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 448 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 449 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 450 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 451 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 452 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 453 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 454 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 455 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 456 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 457 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 458 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 459 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 460 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 461 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 462 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 463 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 464 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 465 | #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) |
| mbed_official | 324:406fd2029f23 | 466 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 467 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 468 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 469 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 470 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 471 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 472 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 473 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 474 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 475 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 476 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 477 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 478 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 479 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 480 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 481 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 482 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 483 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 484 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 485 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 486 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 487 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 488 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 489 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 490 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 491 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 492 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 493 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 494 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 495 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 496 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 497 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 498 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 499 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 500 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 501 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 502 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 503 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 504 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 505 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 506 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 507 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 508 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 509 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 510 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 511 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 512 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 513 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 514 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 515 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 516 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 517 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 518 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 519 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 520 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 521 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 522 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 523 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 524 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 525 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 526 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 527 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 528 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 529 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 530 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 531 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 532 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 533 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 534 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 535 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 536 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 537 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 538 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 539 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 540 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 541 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 542 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 543 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 544 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 545 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 546 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 547 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 548 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 549 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 550 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 551 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 552 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 553 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 554 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 555 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 556 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 557 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 558 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 559 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 560 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 561 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 562 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 563 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 564 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 565 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 566 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 567 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 568 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 569 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 570 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 571 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 572 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 573 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 574 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 575 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 576 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 577 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 578 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 579 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 580 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 581 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 582 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 583 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 584 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 585 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 586 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 587 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 588 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 589 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 590 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 591 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 592 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 593 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 594 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 595 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 596 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 597 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 598 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 599 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 600 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 601 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 602 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 603 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 604 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 605 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 606 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 607 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 608 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 609 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 610 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 611 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 612 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 613 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 614 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 615 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 616 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 617 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 618 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 619 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 620 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 621 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 622 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 623 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 624 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 625 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 626 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 627 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 628 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 629 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 630 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 631 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 632 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 633 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 634 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 146:f64d43ff0c18 | 635 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 636 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 146:f64d43ff0c18 | 637 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 638 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 146:f64d43ff0c18 | 639 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 640 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 641 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 642 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 643 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 644 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 645 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 646 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 647 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 648 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 649 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 650 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 651 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 652 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 653 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 654 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 655 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 656 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 657 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 658 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 659 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 660 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 661 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 662 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 663 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 664 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 665 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 666 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 667 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 668 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 669 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 670 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 671 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 672 | #elif defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) |
| mbed_official | 324:406fd2029f23 | 673 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 674 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 675 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 676 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 677 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 678 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 679 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 680 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 681 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 682 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 683 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 684 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 685 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 686 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 687 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 688 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 689 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 690 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 691 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 692 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 693 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 694 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 695 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 696 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 697 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 698 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 699 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 700 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 701 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 702 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 703 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 704 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 705 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 706 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 707 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 708 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 709 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 710 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 711 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 712 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 713 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 714 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 715 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 716 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 717 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 718 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 719 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 720 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 721 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 722 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 723 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 724 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 725 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 726 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 727 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 728 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 729 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 730 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 731 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 732 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 733 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 734 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 735 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 736 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 737 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 738 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 739 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 740 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 741 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 742 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 743 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 744 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 745 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 746 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 747 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 748 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 749 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 750 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 751 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 752 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 753 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 754 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 755 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 756 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 757 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 758 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 759 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 760 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 761 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 762 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 763 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 764 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 765 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 766 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 767 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 768 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 769 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 770 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 771 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 772 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 773 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 774 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 775 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 776 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 777 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 778 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 779 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 780 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 781 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 782 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 783 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 784 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 785 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 786 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 787 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 788 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 789 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 790 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 791 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 792 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 793 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 794 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 795 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 796 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 797 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 798 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 799 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 800 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 801 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 802 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 803 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 804 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 805 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 806 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 807 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 808 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 809 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 810 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 811 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 812 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 813 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 814 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 815 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 816 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 817 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 818 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 819 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 820 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 821 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 822 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 823 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 824 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 825 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 826 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 827 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 828 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 829 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 830 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 831 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 832 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 833 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 834 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 835 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 836 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 837 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 838 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 839 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 840 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 841 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 842 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 843 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 844 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 845 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 846 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 847 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 848 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 849 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 850 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 851 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 852 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 853 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 854 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 855 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 856 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 857 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 858 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 859 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 146:f64d43ff0c18 | 860 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 861 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 146:f64d43ff0c18 | 862 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 863 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 864 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 865 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 146:f64d43ff0c18 | 866 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 867 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 868 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 869 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 870 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 871 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 872 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 873 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 874 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 875 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 876 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 877 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 878 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 879 | #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) |
| mbed_official | 324:406fd2029f23 | 880 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 881 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 882 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 883 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 884 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 885 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 886 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 887 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 888 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 889 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 890 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 891 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 892 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 893 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 894 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 895 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 896 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 897 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 898 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 899 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) |
| mbed_official | 324:406fd2029f23 | 900 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 901 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 902 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 903 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 904 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 905 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 906 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 907 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 908 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 909 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 910 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 911 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 912 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 913 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 914 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 915 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 916 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 917 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 918 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 919 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 920 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 921 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 922 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 923 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 924 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 925 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 926 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 927 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 928 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 929 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 930 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 931 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 932 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 933 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 934 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 935 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 936 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 937 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 938 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 939 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 940 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 941 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 942 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 943 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 944 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 945 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 946 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 947 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 948 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 949 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 950 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 951 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 952 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 953 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 954 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 955 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 956 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 957 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 958 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 959 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 960 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 961 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 962 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 963 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 964 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 965 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 966 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 967 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 968 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 969 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 970 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 971 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 972 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 973 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 974 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 975 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 976 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 977 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 978 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 979 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 980 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 981 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 982 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 983 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 984 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 985 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 986 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 987 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 988 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 989 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 990 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 991 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 992 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 993 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) |
| mbed_official | 324:406fd2029f23 | 994 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 995 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 996 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 997 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 998 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 999 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 1000 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1001 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 1002 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1003 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 1004 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1005 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 1006 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1007 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 1008 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1009 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1010 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1011 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 1012 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1013 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 1014 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1015 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1016 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1017 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 1018 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1019 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 1020 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1021 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1022 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 1023 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 1024 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 1025 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 1026 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1027 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 1028 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1029 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 1030 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1031 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 1032 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1033 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1034 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1035 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1036 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1037 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 1038 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1039 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1040 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1041 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 1042 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1043 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1044 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 1045 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 1046 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1047 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 1048 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1049 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 1050 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 1051 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 1052 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 1053 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 1054 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1055 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1056 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 1057 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 1058 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1059 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 1060 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1061 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 1062 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1063 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1064 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1065 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) |
| mbed_official | 324:406fd2029f23 | 1066 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 1067 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) |
| mbed_official | 324:406fd2029f23 | 1068 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 1069 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 1070 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 1071 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 1072 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 1073 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 1074 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 146:f64d43ff0c18 | 1075 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 1076 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1077 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) |
| mbed_official | 324:406fd2029f23 | 1078 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1079 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 1080 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 1081 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 1082 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 1083 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 1084 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1085 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 1086 | #elif defined(CPU_MK24FN256VDC12) |
| mbed_official | 324:406fd2029f23 | 1087 | /* @brief Has USB FS divider. */ |
| mbed_official | 146:f64d43ff0c18 | 1088 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1089 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 146:f64d43ff0c18 | 1090 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1091 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 1092 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1093 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 1094 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 1095 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1096 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1097 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1098 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1099 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1100 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1101 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 1102 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 1103 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 1104 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 1105 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 146:f64d43ff0c18 | 1106 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 1107 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 1108 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 1109 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 1110 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 1111 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 1112 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 1113 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 146:f64d43ff0c18 | 1114 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1115 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 1116 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1117 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1118 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1119 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1120 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1121 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 1122 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 1123 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1124 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1125 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1126 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1127 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1128 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1129 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1130 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1131 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1132 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1133 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1134 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1135 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1136 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1137 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1138 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1139 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1140 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1141 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1142 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1143 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1144 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1145 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 146:f64d43ff0c18 | 1146 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 1147 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 1148 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1149 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 146:f64d43ff0c18 | 1150 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1151 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 146:f64d43ff0c18 | 1152 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1153 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 146:f64d43ff0c18 | 1154 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1155 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1156 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1157 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1158 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1159 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1160 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1161 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1162 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 1163 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1164 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1165 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1166 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1167 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1168 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1169 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1170 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1171 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1172 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 1173 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 1174 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1175 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 146:f64d43ff0c18 | 1176 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 1177 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 1178 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 1179 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 1180 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 1181 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1182 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 1183 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1184 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1185 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1186 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1187 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1188 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1189 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1190 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 1191 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1192 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1193 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1194 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1195 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1196 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1197 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1198 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1199 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1200 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1201 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1202 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1203 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 1204 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 1205 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 1206 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 1207 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1208 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 1209 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1210 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 1211 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1212 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 1213 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1214 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 1215 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1216 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1217 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1218 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 1219 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1220 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 1221 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1222 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1223 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1224 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 1225 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1226 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 1227 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1228 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1229 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 1230 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 1231 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 1232 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 1233 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1234 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 1235 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1236 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 1237 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1238 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 1239 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1240 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1241 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1242 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1243 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1244 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 1245 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1246 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1247 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1248 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 1249 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1250 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1251 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 1252 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 1253 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1254 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 1255 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1256 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 1257 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 1258 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 1259 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 1260 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 1261 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1262 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1263 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 1264 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 1265 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1266 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 1267 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1268 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 1269 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1270 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1271 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1272 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 1273 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 1274 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 1275 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 1276 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 1277 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 1278 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 1279 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 1280 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 1281 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 1282 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 1283 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1284 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 1285 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1286 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 1287 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 1288 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 1289 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 1290 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 1291 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1292 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 1293 | #elif defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \ |
| mbed_official | 324:406fd2029f23 | 1294 | defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \ |
| mbed_official | 324:406fd2029f23 | 1295 | defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) |
| mbed_official | 324:406fd2029f23 | 1296 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 1297 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1298 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 1299 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1300 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1301 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1302 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 1303 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 1304 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1305 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1306 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1307 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1308 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1309 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1310 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 1311 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 1312 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 1313 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 1314 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 1315 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) |
| mbed_official | 324:406fd2029f23 | 1316 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 1317 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 1318 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 1319 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 1320 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 1321 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 1322 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 1323 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1324 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 1325 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1326 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1327 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1328 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1329 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1330 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 1331 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 1332 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1333 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1334 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1335 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1336 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1337 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1338 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1339 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1340 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1341 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1342 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1343 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1344 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1345 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1346 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1347 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1348 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1349 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1350 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1351 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1352 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1353 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1354 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1355 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 1356 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 1357 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1358 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 1359 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1360 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1361 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1362 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1363 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1364 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1365 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1366 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1367 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1368 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1369 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1370 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1371 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 1372 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1373 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 1374 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1375 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1376 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1377 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1378 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1379 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1380 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1381 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 1382 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 1383 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1384 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1385 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 1386 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 1387 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 1388 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 1389 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 1390 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1391 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 1392 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1393 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1394 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1395 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1396 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1397 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1398 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1399 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 1400 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1401 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1402 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1403 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1404 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1405 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1406 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1407 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1408 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1409 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) |
| mbed_official | 324:406fd2029f23 | 1410 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1411 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1412 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1413 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) |
| mbed_official | 324:406fd2029f23 | 1414 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 1415 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) |
| mbed_official | 324:406fd2029f23 | 1416 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1417 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 1418 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1419 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 1420 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1421 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 1422 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1423 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 1424 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1425 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1426 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1427 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 1428 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1429 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 1430 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1431 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1432 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1433 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 1434 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1435 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 1436 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1437 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1438 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 1439 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 1440 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 1441 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 1442 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1443 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 1444 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1445 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 1446 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1447 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 1448 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1449 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1450 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1451 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1452 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1453 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 1454 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1455 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1456 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1457 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 1458 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1459 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1460 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 1461 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 1462 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1463 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 1464 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1465 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 1466 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 1467 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 1468 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 1469 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 1470 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1471 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1472 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 1473 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 1474 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1475 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 1476 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1477 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 1478 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1479 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1480 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1481 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) |
| mbed_official | 324:406fd2029f23 | 1482 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 1483 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) |
| mbed_official | 324:406fd2029f23 | 1484 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 1485 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 1486 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 1487 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 1488 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 1489 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 1490 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 1491 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 1492 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1493 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) |
| mbed_official | 324:406fd2029f23 | 1494 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1495 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 1496 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 1497 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 1498 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 1499 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 1500 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1501 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 1502 | #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ |
| mbed_official | 324:406fd2029f23 | 1503 | defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) |
| mbed_official | 324:406fd2029f23 | 1504 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 1505 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1506 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 1507 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1508 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1509 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1510 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 1511 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 1512 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1513 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1514 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1515 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1516 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1517 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1518 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 1519 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 1520 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 1521 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) |
| mbed_official | 324:406fd2029f23 | 1522 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 1523 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 1524 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 1525 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 1526 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 1527 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 1528 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 1529 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 1530 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 1531 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1532 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 1533 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1534 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1535 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1536 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1537 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1538 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 1539 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 1540 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1541 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1542 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1543 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1544 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1545 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1546 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1547 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1548 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1549 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1550 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1551 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1552 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1553 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1554 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1555 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1556 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1557 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1558 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1559 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1560 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1561 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1562 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1563 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 1564 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 1565 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1566 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 1567 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1568 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1569 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1570 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1571 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1572 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1573 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1574 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1575 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1576 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1577 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1578 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1579 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 1580 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1581 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1582 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1583 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1584 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1585 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1586 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1587 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1588 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1589 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 1590 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 1591 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1592 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1593 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 1594 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 1595 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
| mbed_official | 324:406fd2029f23 | 1596 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 1597 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 1598 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1599 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 1600 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1601 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1602 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1603 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1604 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1605 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1606 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1607 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 1608 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1609 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1610 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1611 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1612 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1613 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1614 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1615 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1616 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1617 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) |
| mbed_official | 324:406fd2029f23 | 1618 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1619 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1620 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 1621 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) |
| mbed_official | 324:406fd2029f23 | 1622 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 1623 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) |
| mbed_official | 324:406fd2029f23 | 1624 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1625 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 1626 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1627 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 1628 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1629 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 1630 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1631 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 1632 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1633 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1634 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1635 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 1636 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1637 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 1638 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1639 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1640 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1641 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 1642 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 1643 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 1644 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1645 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1646 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 146:f64d43ff0c18 | 1647 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 1648 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 146:f64d43ff0c18 | 1649 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 1650 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1651 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 1652 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1653 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 1654 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1655 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) |
| mbed_official | 324:406fd2029f23 | 1656 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1657 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1658 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1659 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 1660 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1661 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) |
| mbed_official | 324:406fd2029f23 | 1662 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1663 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1664 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1665 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) |
| mbed_official | 324:406fd2029f23 | 1666 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1667 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 1668 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 1669 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 1670 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1671 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 1672 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1673 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 1674 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 1675 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 1676 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 1677 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 1678 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1679 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1680 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 1681 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 1682 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1683 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 1684 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 1685 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 1686 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1687 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1688 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1689 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) |
| mbed_official | 324:406fd2029f23 | 1690 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 1691 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) |
| mbed_official | 324:406fd2029f23 | 1692 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 1693 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 1694 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 1695 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 1696 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 1697 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 1698 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 1699 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 1700 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1701 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) |
| mbed_official | 324:406fd2029f23 | 1702 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1703 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) |
| mbed_official | 324:406fd2029f23 | 1704 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 1705 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 1706 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 1707 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 1708 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1709 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 1710 | #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 324:406fd2029f23 | 1711 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 324:406fd2029f23 | 1712 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 1713 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1714 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 1715 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1716 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1717 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1718 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 1719 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 1720 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1721 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1722 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1723 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1724 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1725 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1726 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 1727 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 1728 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 1729 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 1730 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 1731 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 1732 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 1733 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 1734 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 1735 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (1) |
| mbed_official | 324:406fd2029f23 | 1736 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 1737 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (1) |
| mbed_official | 324:406fd2029f23 | 1738 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 1739 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1740 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 1741 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1742 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1743 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1744 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1745 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1746 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 1747 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (1) |
| mbed_official | 324:406fd2029f23 | 1748 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1749 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1750 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1751 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1752 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1753 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1754 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1755 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1756 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1757 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1758 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1759 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1760 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1761 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1762 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1763 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1764 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1765 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1766 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1767 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1768 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1769 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1770 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1771 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 1772 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 1773 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1774 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 1775 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 1776 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1777 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1778 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1779 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 1780 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1781 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1782 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1783 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 1784 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1785 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1786 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1787 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 1788 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1789 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1790 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1791 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1792 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1793 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1794 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1795 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 1796 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1797 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 1798 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 1799 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1800 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1801 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 1802 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 1803 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 1804 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 1805 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 1806 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1807 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 1808 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1809 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1810 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1811 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1812 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1813 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 1814 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1815 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 1816 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1817 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1818 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1819 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 1820 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1821 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (1) |
| mbed_official | 324:406fd2029f23 | 1822 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1823 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (1) |
| mbed_official | 324:406fd2029f23 | 1824 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1825 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 1826 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1827 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (1) |
| mbed_official | 324:406fd2029f23 | 1828 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 1829 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) |
| mbed_official | 324:406fd2029f23 | 1830 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 1831 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 1832 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1833 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 1834 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1835 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (1) |
| mbed_official | 324:406fd2029f23 | 1836 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1837 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (1) |
| mbed_official | 324:406fd2029f23 | 1838 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1839 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 1840 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1841 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1842 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1843 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 1844 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1845 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 1846 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1847 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 1848 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1849 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 1850 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1851 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 1852 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 1853 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 1854 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 1855 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 1856 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 1857 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 1858 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1859 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 1860 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 1861 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 1862 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1863 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 1864 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1865 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (1) |
| mbed_official | 324:406fd2029f23 | 1866 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 1867 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (1) |
| mbed_official | 324:406fd2029f23 | 1868 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1869 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 1870 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1871 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (1) |
| mbed_official | 324:406fd2029f23 | 1872 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1873 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) |
| mbed_official | 324:406fd2029f23 | 1874 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 1875 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (1) |
| mbed_official | 324:406fd2029f23 | 1876 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 146:f64d43ff0c18 | 1877 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 1878 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 1879 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 1880 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 146:f64d43ff0c18 | 1881 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (0) |
| mbed_official | 324:406fd2029f23 | 1882 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 146:f64d43ff0c18 | 1883 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) |
| mbed_official | 324:406fd2029f23 | 1884 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 146:f64d43ff0c18 | 1885 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (0) |
| mbed_official | 324:406fd2029f23 | 1886 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 1887 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1888 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 1889 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (0) |
| mbed_official | 324:406fd2029f23 | 1890 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 1891 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (0) |
| mbed_official | 324:406fd2029f23 | 1892 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 1893 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (1) |
| mbed_official | 324:406fd2029f23 | 1894 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 1895 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 1896 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 1897 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) |
| mbed_official | 324:406fd2029f23 | 1898 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 146:f64d43ff0c18 | 1899 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) |
| mbed_official | 324:406fd2029f23 | 1900 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 146:f64d43ff0c18 | 1901 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) |
| mbed_official | 324:406fd2029f23 | 1902 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 146:f64d43ff0c18 | 1903 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 1904 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 146:f64d43ff0c18 | 1905 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (1) |
| mbed_official | 324:406fd2029f23 | 1906 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 146:f64d43ff0c18 | 1907 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (1) |
| mbed_official | 324:406fd2029f23 | 1908 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1909 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 1910 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 1911 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 1912 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 1913 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (1) |
| mbed_official | 324:406fd2029f23 | 1914 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 1915 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 1916 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1917 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 1918 | #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ |
| mbed_official | 324:406fd2029f23 | 1919 | defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) |
| mbed_official | 324:406fd2029f23 | 1920 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 1921 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1922 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 1923 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 1924 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 1925 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 1926 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 1927 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 1928 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1929 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1930 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1931 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 1932 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 1933 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 1934 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 1935 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 1936 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 1937 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 1938 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 1939 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 1940 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 1941 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 1942 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 1943 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 1944 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 1945 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 1946 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 1947 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1948 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 1949 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 1950 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1951 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) |
| mbed_official | 324:406fd2029f23 | 1952 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 1953 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 1954 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 1955 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 1956 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1957 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1958 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1959 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 1960 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1961 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1962 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1963 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1964 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1965 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1966 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1967 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1968 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1969 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1970 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1971 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1972 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1973 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1974 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1975 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 1976 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 1977 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 1978 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 1979 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
| mbed_official | 324:406fd2029f23 | 1980 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 1981 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 1982 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 1983 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 1984 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1985 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 1986 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 1987 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 1988 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1989 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1990 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1991 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1992 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1993 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 1994 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 1995 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 1996 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1997 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 1998 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 1999 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2000 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2001 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2002 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2003 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2004 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2005 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 2006 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 2007 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2008 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2009 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 2010 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 2011 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 2012 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 2013 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
| mbed_official | 324:406fd2029f23 | 2014 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2015 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 2016 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2017 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2018 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2019 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2020 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2021 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2022 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2023 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 2024 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2025 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2026 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2027 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2028 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2029 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2030 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2031 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2032 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2033 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2034 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2035 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2036 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 2037 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 2038 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 2039 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 2040 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2041 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 2042 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2043 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 2044 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2045 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 2046 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2047 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 2048 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2049 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) |
| mbed_official | 324:406fd2029f23 | 2050 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2051 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 2052 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2053 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 2054 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2055 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 2056 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2057 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 2058 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2059 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
| mbed_official | 324:406fd2029f23 | 2060 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2061 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2062 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 2063 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
| mbed_official | 324:406fd2029f23 | 2064 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 2065 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 2066 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2067 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 2068 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2069 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
| mbed_official | 324:406fd2029f23 | 2070 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2071 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 2072 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2073 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2074 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2075 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2076 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2077 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 2078 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2079 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2080 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2081 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 2082 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2083 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2084 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 2085 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 2086 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2087 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 2088 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2089 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 2090 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 2091 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 2092 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 2093 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 2094 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2095 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2096 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 2097 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 2098 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2099 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 2100 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2101 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 2102 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2103 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2104 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2105 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 2106 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 2107 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 2108 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 2109 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 2110 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 2111 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 2112 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 2113 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 2114 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 2115 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 2116 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 146:f64d43ff0c18 | 2117 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 2118 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2119 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 2120 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 2121 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 2122 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 2123 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
| mbed_official | 324:406fd2029f23 | 2124 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2125 | #define FSL_FEATURE_SIM_HAS_COP_STOP (1) |
| mbed_official | 324:406fd2029f23 | 2126 | #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ |
| mbed_official | 324:406fd2029f23 | 2127 | defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 2128 | defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) |
| mbed_official | 324:406fd2029f23 | 2129 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 2130 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2131 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 146:f64d43ff0c18 | 2132 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2133 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2134 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2135 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 2136 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 2137 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2138 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2139 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2140 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2141 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2142 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2143 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 2144 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 2145 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 2146 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 2147 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 2148 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 2149 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 2150 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 2151 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 146:f64d43ff0c18 | 2152 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 2153 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2154 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 2155 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 2156 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2157 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 2158 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2159 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2160 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2161 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2162 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2163 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 2164 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 2165 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2166 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2167 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2168 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2169 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2170 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2171 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2172 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2173 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2174 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2175 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2176 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2177 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2178 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2179 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2180 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2181 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2182 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2183 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2184 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2185 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2186 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2187 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2188 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
| mbed_official | 324:406fd2029f23 | 2189 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 2190 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2191 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 2192 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2193 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2194 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2195 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2196 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2197 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2198 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2199 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2200 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2201 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2202 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2203 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2204 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 2205 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2206 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2207 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2208 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2209 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2210 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2211 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2212 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2213 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2214 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 2215 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 2216 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2217 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2218 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 2219 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 2220 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 2221 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 2222 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
| mbed_official | 324:406fd2029f23 | 2223 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2224 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 2225 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2226 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2227 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2228 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2229 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2230 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2231 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2232 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 2233 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2234 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2235 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2236 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2237 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2238 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2239 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2240 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2241 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2242 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2243 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2244 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2245 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 2246 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 2247 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 2248 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 2249 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2250 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 2251 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2252 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 2253 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2254 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 2255 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2256 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 2257 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2258 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 2259 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2260 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 2261 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2262 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 2263 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2264 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) |
| mbed_official | 324:406fd2029f23 | 2265 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2266 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 2267 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2268 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
| mbed_official | 324:406fd2029f23 | 2269 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2270 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2271 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 2272 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
| mbed_official | 324:406fd2029f23 | 2273 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 2274 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 2275 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2276 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 2277 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2278 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
| mbed_official | 324:406fd2029f23 | 2279 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2280 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 2281 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2282 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2283 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2284 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2285 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2286 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 2287 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2288 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2289 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2290 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 2291 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2292 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2293 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 2294 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 2295 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2296 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 2297 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2298 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 2299 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 2300 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 2301 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 2302 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 2303 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2304 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2305 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 2306 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 2307 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2308 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 2309 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2310 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 2311 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2312 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2313 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2314 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 2315 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 2316 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 2317 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 2318 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 2319 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 2320 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 2321 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 2322 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 2323 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 2324 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 2325 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2326 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 2327 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2328 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 2329 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 2330 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 2331 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 2332 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
| mbed_official | 324:406fd2029f23 | 2333 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2334 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 2335 | #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 2336 | defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 2337 | defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 2338 | defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 2339 | defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 2340 | defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 2341 | defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 2342 | defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 2343 | defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) |
| mbed_official | 324:406fd2029f23 | 2344 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 2345 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2346 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 2347 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2348 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2349 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2350 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 2351 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 2352 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2353 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2354 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2355 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2356 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2357 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2358 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 2359 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 2360 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 2361 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 2362 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 2363 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 2364 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 2365 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 2366 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 2367 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 2368 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 2369 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 2370 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 2371 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2372 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 2373 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2374 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2375 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2376 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2377 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2378 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 2379 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 2380 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2381 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2382 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2383 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2384 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2385 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2386 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2387 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2388 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2389 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2390 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2391 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2392 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2393 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2394 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2395 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2396 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2397 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2398 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2399 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2400 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2401 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2402 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2403 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
| mbed_official | 324:406fd2029f23 | 2404 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 2405 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2406 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 2407 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2408 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2409 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2410 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2411 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2412 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2413 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2414 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2415 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2416 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2417 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2418 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2419 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 2420 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2421 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2422 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2423 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2424 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2425 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2426 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2427 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2428 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2429 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 2430 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 2431 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2432 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2433 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 2434 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 2435 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
| mbed_official | 324:406fd2029f23 | 2436 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 2437 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
| mbed_official | 324:406fd2029f23 | 2438 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2439 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 2440 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2441 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2442 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2443 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2444 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2445 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2446 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2447 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) |
| mbed_official | 324:406fd2029f23 | 2448 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2449 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2450 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2451 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 2452 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2453 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2454 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2455 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2456 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2457 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2458 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 2459 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2460 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 2461 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 2462 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 2463 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 2464 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2465 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 2466 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2467 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 2468 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2469 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 2470 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2471 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 2472 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2473 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) |
| mbed_official | 324:406fd2029f23 | 2474 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2475 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1) |
| mbed_official | 324:406fd2029f23 | 2476 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2477 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1) |
| mbed_official | 324:406fd2029f23 | 2478 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2479 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 2480 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2481 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 2482 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2483 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
| mbed_official | 324:406fd2029f23 | 2484 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2485 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2486 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 2487 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
| mbed_official | 324:406fd2029f23 | 2488 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 2489 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 2490 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2491 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 2492 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2493 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
| mbed_official | 324:406fd2029f23 | 2494 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2495 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 2496 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2497 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2498 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2499 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2500 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2501 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 2502 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2503 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2504 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2505 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 2506 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2507 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2508 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 2509 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 2510 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2511 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 2512 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2513 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 2514 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 2515 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 2516 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 2517 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 2518 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2519 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2520 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 2521 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 2522 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2523 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 2524 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2525 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 2526 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2527 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2528 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2529 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 2530 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 2531 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 2532 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 2533 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 2534 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 2535 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 2536 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 2537 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 2538 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 2539 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 2540 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2541 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 2542 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2543 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 2544 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 2545 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 2546 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 2547 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
| mbed_official | 324:406fd2029f23 | 2548 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2549 | #define FSL_FEATURE_SIM_HAS_COP_STOP (1) |
| mbed_official | 324:406fd2029f23 | 2550 | #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 2551 | defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 2552 | defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) |
| mbed_official | 324:406fd2029f23 | 2553 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 2554 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2555 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 2556 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) |
| mbed_official | 324:406fd2029f23 | 2557 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2558 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2559 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 2560 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 2561 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2562 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2563 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2564 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2565 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2566 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2567 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 2568 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 2569 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 2570 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 2571 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 2572 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 2573 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 2574 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 2575 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 2576 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 2577 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 2578 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 2579 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 2580 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2581 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 2582 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 2583 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2584 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2585 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2586 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2587 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 2588 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 2589 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2590 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2591 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2592 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2593 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2594 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2595 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2596 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2597 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2598 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2599 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2600 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2601 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2602 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2603 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2604 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2605 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2606 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2607 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2608 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2609 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2610 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2611 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2612 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
| mbed_official | 324:406fd2029f23 | 2613 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 2614 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2615 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 2616 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2617 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2618 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2619 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2620 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2621 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2622 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2623 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2624 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2625 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2626 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2627 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2628 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 2629 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2630 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2631 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2632 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2633 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2634 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2635 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2636 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2637 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2638 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 2639 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 2640 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2641 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2642 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 2643 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 2644 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
| mbed_official | 324:406fd2029f23 | 2645 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 2646 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
| mbed_official | 324:406fd2029f23 | 2647 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2648 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 2649 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2650 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2651 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2652 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2653 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2654 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2655 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2656 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) |
| mbed_official | 324:406fd2029f23 | 2657 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2658 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2659 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2660 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2661 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2662 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2663 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2664 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2665 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2666 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2667 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2668 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2669 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 2670 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 2671 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 2672 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 2673 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2674 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 2675 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2676 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 2677 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2678 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 2679 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2680 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 2681 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2682 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 2683 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2684 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 2685 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2686 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 2687 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2688 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) |
| mbed_official | 324:406fd2029f23 | 2689 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2690 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 2691 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2692 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
| mbed_official | 324:406fd2029f23 | 2693 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2694 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2695 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 2696 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
| mbed_official | 324:406fd2029f23 | 2697 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 2698 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 2699 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2700 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 2701 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2702 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
| mbed_official | 324:406fd2029f23 | 2703 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2704 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 2705 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2706 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2707 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 2708 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2709 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2710 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 2711 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2712 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2713 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2714 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 2715 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2716 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2717 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 2718 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 2719 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2720 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 2721 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 146:f64d43ff0c18 | 2722 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 2723 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 146:f64d43ff0c18 | 2724 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 2725 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 146:f64d43ff0c18 | 2726 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 2727 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2728 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2729 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 2730 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 2731 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 2732 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 2733 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2734 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 2735 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2736 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2737 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2738 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 2739 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 2740 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 2741 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 2742 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 2743 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 2744 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 2745 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 2746 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 2747 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 2748 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 2749 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2750 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 2751 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2752 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 2753 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 2754 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 2755 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 2756 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
| mbed_official | 324:406fd2029f23 | 2757 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2758 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 2759 | #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ |
| mbed_official | 324:406fd2029f23 | 2760 | defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ |
| mbed_official | 324:406fd2029f23 | 2761 | defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
| mbed_official | 324:406fd2029f23 | 2762 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 2763 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2764 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 2765 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (1) |
| mbed_official | 324:406fd2029f23 | 2766 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2767 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2768 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 2769 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 2770 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2771 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2772 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2773 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2774 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2775 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2776 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 2777 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) |
| mbed_official | 324:406fd2029f23 | 2778 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 2779 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 2780 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 2781 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 2782 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 2783 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 2784 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 2785 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 2786 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 2787 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 2788 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 2789 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) |
| mbed_official | 324:406fd2029f23 | 2790 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 2791 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 2792 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2793 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2794 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 2795 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2796 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 2797 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 2798 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2799 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2800 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2801 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2802 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2803 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2804 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2805 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2806 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2807 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2808 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2809 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2810 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2811 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2812 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2813 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2814 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2815 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2816 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2817 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 2818 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2819 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2820 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2821 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) |
| mbed_official | 324:406fd2029f23 | 2822 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 2823 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2824 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 2825 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2826 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2827 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2828 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 2829 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 2830 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2831 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2832 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2833 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2834 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2835 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 2836 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2837 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 2838 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2839 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2840 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2841 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2842 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2843 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2844 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 2845 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 2846 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2847 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) |
| mbed_official | 324:406fd2029f23 | 2848 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 2849 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) |
| mbed_official | 324:406fd2029f23 | 2850 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 2851 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) |
| mbed_official | 324:406fd2029f23 | 2852 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 2853 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) |
| mbed_official | 324:406fd2029f23 | 2854 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 2855 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) |
| mbed_official | 324:406fd2029f23 | 2856 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2857 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 2858 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2859 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2860 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2861 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2862 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2863 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2864 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2865 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) |
| mbed_official | 324:406fd2029f23 | 2866 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2867 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2868 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2869 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 2870 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2871 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2872 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2873 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2874 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2875 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2876 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2877 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 2878 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 2879 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 2880 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 2881 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 2882 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2883 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) |
| mbed_official | 324:406fd2029f23 | 2884 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2885 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 2886 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2887 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 2888 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2889 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 2890 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2891 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 2892 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2893 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 2894 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2895 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 2896 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 2897 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (1) |
| mbed_official | 324:406fd2029f23 | 2898 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 2899 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) |
| mbed_official | 324:406fd2029f23 | 2900 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2901 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) |
| mbed_official | 324:406fd2029f23 | 2902 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 2903 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 2904 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 2905 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) |
| mbed_official | 324:406fd2029f23 | 2906 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 2907 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 2908 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2909 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 2910 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 2911 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) |
| mbed_official | 324:406fd2029f23 | 2912 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2913 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 2914 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2915 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2916 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2917 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 2918 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2919 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 2920 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2921 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2922 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2923 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 2924 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 2925 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 2926 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 2927 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) |
| mbed_official | 324:406fd2029f23 | 2928 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2929 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) |
| mbed_official | 324:406fd2029f23 | 2930 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 2931 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 2932 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 2933 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 2934 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 2935 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 2936 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2937 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2938 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 2939 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 2940 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 2941 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 2942 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 2943 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 2944 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2945 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 2946 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2947 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 2948 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 2949 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 2950 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 146:f64d43ff0c18 | 2951 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 2952 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 146:f64d43ff0c18 | 2953 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 2954 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 146:f64d43ff0c18 | 2955 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 2956 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 2957 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 2958 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2959 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 2960 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 2961 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 2962 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 2963 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 2964 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 2965 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) |
| mbed_official | 324:406fd2029f23 | 2966 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2967 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 2968 | #elif defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || \ |
| mbed_official | 324:406fd2029f23 | 2969 | defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) |
| mbed_official | 324:406fd2029f23 | 2970 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 2971 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2972 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 2973 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 2974 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 2975 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 2976 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 2977 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 2978 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2979 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 2980 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2981 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 2982 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 2983 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 2984 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 2985 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 2986 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 2987 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 2988 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 2989 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 2990 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 2991 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 2992 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 2993 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 2994 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 2995 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 2996 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 2997 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 2998 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 2999 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3000 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3001 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3002 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3003 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3004 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 3005 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 3006 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3007 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3008 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3009 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3010 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3011 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3012 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3013 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3014 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3015 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3016 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3017 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3018 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3019 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3020 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3021 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3022 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3023 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3024 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3025 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3026 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3027 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3028 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3029 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 3030 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 3031 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 3032 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 3033 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3034 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3035 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3036 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3037 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 3038 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3039 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3040 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3041 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3042 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3043 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3044 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3045 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 3046 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3047 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3048 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3049 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3050 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3051 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3052 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3053 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 3054 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3055 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 3056 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 3057 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3058 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3059 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 3060 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 3061 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 3062 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 3063 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 3064 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3065 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 3066 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3067 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3068 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3069 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3070 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3071 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3072 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3073 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 3074 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3075 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3076 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3077 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 3078 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3079 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3080 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3081 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3082 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3083 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3084 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3085 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3086 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 3087 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 3088 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 3089 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 3090 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3091 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 3092 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3093 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 3094 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3095 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 3096 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3097 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 3098 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3099 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3100 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3101 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 3102 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3103 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 3104 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3105 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3106 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3107 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 3108 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3109 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 3110 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3111 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3112 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 3113 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 3114 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 3115 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 3116 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3117 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 3118 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3119 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 3120 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3121 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 3122 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3123 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3124 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3125 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3126 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3127 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 3128 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3129 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3130 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3131 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 3132 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3133 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3134 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 3135 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 3136 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3137 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 3138 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3139 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 3140 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 3141 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 3142 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 3143 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 3144 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3145 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3146 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 3147 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 3148 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3149 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 3150 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3151 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 3152 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3153 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3154 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3155 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 3156 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 3157 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 3158 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 3159 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 3160 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 3161 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 3162 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 3163 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 3164 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 146:f64d43ff0c18 | 3165 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 3166 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3167 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 3168 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3169 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 3170 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 3171 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 3172 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 3173 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 3174 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3175 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 3176 | #elif defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) |
| mbed_official | 324:406fd2029f23 | 3177 | /* @brief Has USB FS divider. */ |
| mbed_official | 146:f64d43ff0c18 | 3178 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3179 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 146:f64d43ff0c18 | 3180 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3181 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 3182 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 3183 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 3184 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 3185 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3186 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3187 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3188 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3189 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3190 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3191 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 3192 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 3193 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 3194 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 3195 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 3196 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 3197 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 3198 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 3199 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 3200 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 3201 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 3202 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 3203 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 3204 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3205 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 3206 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 3207 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3208 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3209 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3210 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3211 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 146:f64d43ff0c18 | 3212 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 3213 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3214 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3215 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3216 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3217 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3218 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3219 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3220 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3221 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3222 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3223 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3224 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3225 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3226 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3227 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3228 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3229 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3230 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3231 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3232 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3233 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3234 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3235 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 146:f64d43ff0c18 | 3236 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 3237 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 3238 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 3239 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 146:f64d43ff0c18 | 3240 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3241 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 146:f64d43ff0c18 | 3242 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3243 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3244 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) |
| mbed_official | 324:406fd2029f23 | 3245 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3246 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3247 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3248 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3249 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3250 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3251 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3252 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 3253 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 146:f64d43ff0c18 | 3254 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3255 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3256 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3257 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3258 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3259 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3260 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 3261 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3262 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 3263 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 3264 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3265 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 146:f64d43ff0c18 | 3266 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 3267 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 3268 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 3269 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 3270 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 3271 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3272 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 3273 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3274 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3275 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3276 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3277 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3278 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3279 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3280 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 3281 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3282 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3283 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3284 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 3285 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3286 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3287 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3288 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3289 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3290 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3291 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 3292 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3293 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3294 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 3295 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3296 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 3297 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3298 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 3299 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3300 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 3301 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3302 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 3303 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3304 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 3305 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3306 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3307 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3308 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 3309 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3310 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 3311 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3312 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3313 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3314 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 3315 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3316 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 3317 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3318 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3319 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 3320 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 3321 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 3322 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 3323 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3324 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 3325 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3326 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 3327 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3328 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 3329 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3330 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3331 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3332 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3333 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3334 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 3335 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3336 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3337 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3338 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 3339 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3340 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3341 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 3342 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 3343 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3344 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 3345 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3346 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 3347 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 3348 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 3349 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 3350 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 3351 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3352 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3353 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 3354 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 3355 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3356 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 3357 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3358 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 3359 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3360 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3361 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3362 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 3363 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 3364 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 3365 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 3366 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 3367 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 3368 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 3369 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 3370 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 3371 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 3372 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 3373 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3374 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 3375 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3376 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 3377 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 3378 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 3379 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 3380 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 3381 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3382 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 3383 | #elif defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) |
| mbed_official | 324:406fd2029f23 | 3384 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 3385 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3386 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 3387 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3388 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3389 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 3390 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 3391 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) |
| mbed_official | 324:406fd2029f23 | 3392 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3393 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3394 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3395 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3396 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3397 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3398 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 3399 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 3400 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 3401 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 3402 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 3403 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 3404 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 3405 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) |
| mbed_official | 324:406fd2029f23 | 3406 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 3407 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 3408 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 3409 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 3410 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 3411 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3412 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 3413 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 3414 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3415 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3416 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3417 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3418 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 3419 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 3420 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3421 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3422 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3423 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3424 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3425 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3426 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3427 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3428 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3429 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3430 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3431 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3432 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3433 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3434 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3435 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3436 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3437 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3438 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3439 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3440 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3441 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3442 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3443 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 3444 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 3445 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 3446 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 3447 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3448 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3449 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3450 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3451 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3452 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3453 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3454 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3455 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) |
| mbed_official | 324:406fd2029f23 | 3456 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3457 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3458 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3459 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) |
| mbed_official | 324:406fd2029f23 | 3460 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3461 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3462 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3463 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3464 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3465 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3466 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3467 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3468 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3469 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 3470 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 3471 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3472 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3473 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 3474 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 3475 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 3476 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 3477 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 3478 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3479 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 3480 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3481 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3482 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3483 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3484 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3485 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3486 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3487 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 3488 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3489 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3490 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3491 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 3492 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3493 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3494 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3495 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3496 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3497 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3498 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3499 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3500 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 3501 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 3502 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 3503 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 3504 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3505 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 3506 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3507 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 3508 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3509 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 3510 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3511 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) |
| mbed_official | 324:406fd2029f23 | 3512 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3513 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3514 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3515 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 3516 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3517 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 3518 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3519 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3520 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3521 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 3522 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 3523 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 3524 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3525 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3526 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 146:f64d43ff0c18 | 3527 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 3528 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 146:f64d43ff0c18 | 3529 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) |
| mbed_official | 324:406fd2029f23 | 3530 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3531 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 3532 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3533 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 3534 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3535 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 3536 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3537 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3538 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 146:f64d43ff0c18 | 3539 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3540 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3541 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 3542 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3543 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3544 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3545 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) |
| mbed_official | 324:406fd2029f23 | 3546 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3547 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3548 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 146:f64d43ff0c18 | 3549 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 3550 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3551 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 3552 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 146:f64d43ff0c18 | 3553 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 3554 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 146:f64d43ff0c18 | 3555 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 3556 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 146:f64d43ff0c18 | 3557 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 3558 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3559 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3560 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 3561 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 3562 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3563 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 3564 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3565 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 3566 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3567 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3568 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3569 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 3570 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 3571 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 3572 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 3573 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 3574 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 3575 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) |
| mbed_official | 324:406fd2029f23 | 3576 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 3577 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 3578 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 3579 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 3580 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3581 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 3582 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3583 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 3584 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 3585 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 3586 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 3587 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 3588 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3589 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 3590 | #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) || defined(CPU_MKV45F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 3591 | defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) |
| mbed_official | 324:406fd2029f23 | 3592 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 3593 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3594 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 3595 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3596 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3597 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 3598 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 3599 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 3600 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3601 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3602 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3603 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3604 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3605 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3606 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 3607 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 3608 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 3609 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 3610 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 3611 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 3612 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 3613 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 3614 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 3615 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 3616 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 3617 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 3618 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 3619 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3620 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 3621 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3622 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3623 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3624 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3625 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3626 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 3627 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 3628 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3629 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3630 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3631 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3632 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3633 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3634 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3635 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3636 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3637 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3638 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3639 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 3640 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3641 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3642 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3643 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3644 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3645 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3646 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3647 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3648 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3649 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3650 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3651 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 3652 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 3653 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3654 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 3655 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3656 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3657 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3658 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3659 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3660 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3661 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3662 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3663 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3664 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3665 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3666 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3667 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 3668 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3669 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 3670 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3671 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3672 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3673 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 3674 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3675 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3676 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3677 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 3678 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 3679 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3680 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3681 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 3682 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 3683 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 3684 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 3685 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 3686 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3687 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 3688 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3689 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3690 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3691 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3692 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3693 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3694 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3695 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 3696 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3697 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3698 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3699 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3700 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3701 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3702 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3703 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3704 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3705 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3706 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3707 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3708 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 3709 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 3710 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 3711 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 3712 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3713 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 3714 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3715 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 3716 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3717 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 3718 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3719 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 3720 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3721 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3722 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3723 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 3724 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3725 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 3726 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3727 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3728 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3729 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 3730 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3731 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 3732 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3733 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3734 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 3735 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 3736 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 3737 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 3738 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3739 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 3740 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3741 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 3742 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3743 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 3744 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3745 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3746 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3747 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3748 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3749 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 3750 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3751 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3752 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3753 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) |
| mbed_official | 324:406fd2029f23 | 3754 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3755 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3756 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 3757 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 3758 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3759 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 3760 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3761 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 3762 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 3763 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 3764 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 3765 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 3766 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 3767 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3768 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 3769 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 3770 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 3771 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 3772 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 146:f64d43ff0c18 | 3773 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 3774 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 3775 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3776 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 146:f64d43ff0c18 | 3777 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 3778 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 3779 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 3780 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 3781 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 3782 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 3783 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 3784 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 3785 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 3786 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 3787 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 3788 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3789 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 3790 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3791 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 3792 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 3793 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 3794 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 3795 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 3796 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3797 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 3798 | #elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) || defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || \ |
| mbed_official | 324:406fd2029f23 | 3799 | defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) |
| mbed_official | 324:406fd2029f23 | 3800 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 3801 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3802 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 3803 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 3804 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3805 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 3806 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 3807 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 3808 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3809 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 3810 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3811 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3812 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3813 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3814 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 3815 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 3816 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 3817 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 3818 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 3819 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 3820 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 3821 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 3822 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 3823 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 3824 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 3825 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 3826 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 3827 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3828 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 3829 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3830 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3831 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3832 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 3833 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 3834 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 3835 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 3836 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3837 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3838 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3839 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3840 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3841 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3842 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3843 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 3844 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3845 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3846 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3847 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 3848 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3849 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3850 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3851 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3852 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3853 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3854 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3855 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3856 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3857 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 3858 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3859 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 3860 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 3861 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (3) |
| mbed_official | 324:406fd2029f23 | 3862 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 3863 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 3864 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3865 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3866 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 3867 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 3868 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3869 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3870 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3871 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3872 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3873 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 3874 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3875 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 3876 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3877 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 3878 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3879 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3880 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3881 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 3882 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 3883 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3884 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3885 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 3886 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 3887 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 3888 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 3889 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 3890 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 3891 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 3892 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 3893 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 3894 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3895 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 3896 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3897 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3898 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3899 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3900 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3901 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3902 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3903 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 3904 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3905 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 3906 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3907 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 3908 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3909 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3910 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3911 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3912 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3913 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3914 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3915 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 3916 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 3917 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 3918 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 3919 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 3920 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3921 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 3922 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3923 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 3924 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3925 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 3926 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3927 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 3928 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3929 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3930 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3931 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 3932 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3933 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 3934 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 3935 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 3936 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 3937 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 3938 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 3939 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 3940 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 3941 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 3942 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 3943 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 3944 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 3945 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 3946 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3947 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 3948 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 3949 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 3950 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3951 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 3952 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3953 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3954 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3955 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 3956 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3957 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 3958 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3959 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3960 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3961 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) |
| mbed_official | 324:406fd2029f23 | 3962 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 3963 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 3964 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 3965 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 3966 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3967 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 3968 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 3969 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 3970 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 3971 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 3972 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 3973 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 3974 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3975 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3976 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 3977 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 3978 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3979 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 3980 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 3981 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 3982 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3983 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 3984 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 3985 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 3986 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 146:f64d43ff0c18 | 3987 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 3988 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 146:f64d43ff0c18 | 3989 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 3990 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 3991 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 3992 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 146:f64d43ff0c18 | 3993 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 3994 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 146:f64d43ff0c18 | 3995 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 3996 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 146:f64d43ff0c18 | 3997 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 3998 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 3999 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 4000 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 4001 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 4002 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 4003 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 4004 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4005 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 324:406fd2029f23 | 4006 | #elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 4007 | defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) |
| mbed_official | 324:406fd2029f23 | 4008 | /* @brief Has USB FS divider. */ |
| mbed_official | 324:406fd2029f23 | 4009 | #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 4010 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ |
| mbed_official | 324:406fd2029f23 | 4011 | #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) |
| mbed_official | 324:406fd2029f23 | 4012 | /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 4013 | #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) |
| mbed_official | 324:406fd2029f23 | 4014 | /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ |
| mbed_official | 324:406fd2029f23 | 4015 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) |
| mbed_official | 324:406fd2029f23 | 4016 | /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4017 | #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 4018 | /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4019 | #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 4020 | /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4021 | #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 4022 | /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ |
| mbed_official | 324:406fd2029f23 | 4023 | #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) |
| mbed_official | 324:406fd2029f23 | 4024 | /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ |
| mbed_official | 324:406fd2029f23 | 4025 | #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) |
| mbed_official | 324:406fd2029f23 | 4026 | /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ |
| mbed_official | 324:406fd2029f23 | 4027 | #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) |
| mbed_official | 324:406fd2029f23 | 4028 | /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ |
| mbed_official | 324:406fd2029f23 | 4029 | #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) |
| mbed_official | 324:406fd2029f23 | 4030 | /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ |
| mbed_official | 324:406fd2029f23 | 4031 | #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) |
| mbed_official | 324:406fd2029f23 | 4032 | /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ |
| mbed_official | 324:406fd2029f23 | 4033 | #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) |
| mbed_official | 324:406fd2029f23 | 4034 | /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ |
| mbed_official | 324:406fd2029f23 | 4035 | #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) |
| mbed_official | 324:406fd2029f23 | 4036 | /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ |
| mbed_official | 324:406fd2029f23 | 4037 | #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 4038 | /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ |
| mbed_official | 324:406fd2029f23 | 4039 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) |
| mbed_official | 324:406fd2029f23 | 4040 | /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ |
| mbed_official | 324:406fd2029f23 | 4041 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) |
| mbed_official | 324:406fd2029f23 | 4042 | /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ |
| mbed_official | 324:406fd2029f23 | 4043 | #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) |
| mbed_official | 324:406fd2029f23 | 4044 | /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4045 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 4046 | /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4047 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 4048 | /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4049 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 4050 | /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4051 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) |
| mbed_official | 324:406fd2029f23 | 4052 | /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4053 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 4054 | /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4055 | #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (1) |
| mbed_official | 324:406fd2029f23 | 4056 | /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4057 | #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 4058 | /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4059 | #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 4060 | /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4061 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 4062 | /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4063 | #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) |
| mbed_official | 324:406fd2029f23 | 4064 | /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4065 | #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) |
| mbed_official | 324:406fd2029f23 | 4066 | /* @brief Has FTM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 4067 | #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) |
| mbed_official | 324:406fd2029f23 | 4068 | /* @brief Number of FTM modules. */ |
| mbed_official | 324:406fd2029f23 | 4069 | #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 4070 | /* @brief Number of FTM triggers with selectable source. */ |
| mbed_official | 324:406fd2029f23 | 4071 | #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 4072 | /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 4073 | #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 4074 | /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ |
| mbed_official | 324:406fd2029f23 | 4075 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) |
| mbed_official | 324:406fd2029f23 | 4076 | /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4077 | #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 4078 | /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4079 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 4080 | /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4081 | #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) |
| mbed_official | 324:406fd2029f23 | 4082 | /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4083 | #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) |
| mbed_official | 324:406fd2029f23 | 4084 | /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 4085 | #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 4086 | /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 4087 | #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 4088 | /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 4089 | #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) |
| mbed_official | 324:406fd2029f23 | 4090 | /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ |
| mbed_official | 324:406fd2029f23 | 4091 | #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 4092 | /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 4093 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) |
| mbed_official | 324:406fd2029f23 | 4094 | /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ |
| mbed_official | 324:406fd2029f23 | 4095 | #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) |
| mbed_official | 324:406fd2029f23 | 4096 | /* @brief Has TPM module(s) configuration. */ |
| mbed_official | 324:406fd2029f23 | 4097 | #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) |
| mbed_official | 324:406fd2029f23 | 4098 | /* @brief The highest TPM module index. */ |
| mbed_official | 324:406fd2029f23 | 4099 | #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 4100 | /* @brief Has TPM module with index 0. */ |
| mbed_official | 324:406fd2029f23 | 4101 | #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) |
| mbed_official | 324:406fd2029f23 | 4102 | /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 4103 | #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) |
| mbed_official | 324:406fd2029f23 | 4104 | /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4105 | #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 4106 | /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4107 | #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 4108 | /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4109 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 4110 | /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4111 | #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) |
| mbed_official | 324:406fd2029f23 | 4112 | /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4113 | #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 4114 | /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4115 | #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) |
| mbed_official | 324:406fd2029f23 | 4116 | /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4117 | #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) |
| mbed_official | 324:406fd2029f23 | 4118 | /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4119 | #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 4120 | /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4121 | #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) |
| mbed_official | 324:406fd2029f23 | 4122 | /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4123 | #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) |
| mbed_official | 324:406fd2029f23 | 4124 | /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ |
| mbed_official | 324:406fd2029f23 | 4125 | #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) |
| mbed_official | 324:406fd2029f23 | 4126 | /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ |
| mbed_official | 324:406fd2029f23 | 4127 | #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) |
| mbed_official | 324:406fd2029f23 | 4128 | /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4129 | #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) |
| mbed_official | 324:406fd2029f23 | 4130 | /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4131 | #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) |
| mbed_official | 324:406fd2029f23 | 4132 | /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4133 | #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) |
| mbed_official | 324:406fd2029f23 | 4134 | /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4135 | #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) |
| mbed_official | 324:406fd2029f23 | 4136 | /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4137 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 4138 | /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4139 | #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) |
| mbed_official | 324:406fd2029f23 | 4140 | /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4141 | #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) |
| mbed_official | 324:406fd2029f23 | 4142 | /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ |
| mbed_official | 324:406fd2029f23 | 4143 | #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) |
| mbed_official | 324:406fd2029f23 | 4144 | /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ |
| mbed_official | 324:406fd2029f23 | 4145 | #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) |
| mbed_official | 324:406fd2029f23 | 4146 | /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4147 | #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) |
| mbed_official | 324:406fd2029f23 | 4148 | /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ |
| mbed_official | 324:406fd2029f23 | 4149 | #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 4150 | /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ |
| mbed_official | 324:406fd2029f23 | 4151 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) |
| mbed_official | 324:406fd2029f23 | 4152 | /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ |
| mbed_official | 324:406fd2029f23 | 4153 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) |
| mbed_official | 324:406fd2029f23 | 4154 | /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 4155 | #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) |
| mbed_official | 324:406fd2029f23 | 4156 | /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ |
| mbed_official | 324:406fd2029f23 | 4157 | #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) |
| mbed_official | 324:406fd2029f23 | 4158 | /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4159 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) |
| mbed_official | 324:406fd2029f23 | 4160 | /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4161 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) |
| mbed_official | 324:406fd2029f23 | 4162 | /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4163 | #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) |
| mbed_official | 324:406fd2029f23 | 4164 | /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4165 | #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) |
| mbed_official | 324:406fd2029f23 | 4166 | /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4167 | #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) |
| mbed_official | 324:406fd2029f23 | 4168 | /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4169 | #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) |
| mbed_official | 324:406fd2029f23 | 4170 | /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ |
| mbed_official | 324:406fd2029f23 | 4171 | #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) |
| mbed_official | 324:406fd2029f23 | 4172 | /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ |
| mbed_official | 324:406fd2029f23 | 4173 | #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) |
| mbed_official | 324:406fd2029f23 | 4174 | /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ |
| mbed_official | 324:406fd2029f23 | 4175 | #define FSL_FEATURE_SIM_SDID_HAS_FAMID (0) |
| mbed_official | 324:406fd2029f23 | 4176 | /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ |
| mbed_official | 324:406fd2029f23 | 4177 | #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) |
| mbed_official | 324:406fd2029f23 | 4178 | /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ |
| mbed_official | 324:406fd2029f23 | 4179 | #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) |
| mbed_official | 324:406fd2029f23 | 4180 | /* @brief Has device die ID (register bit field SDID[DIEID]). */ |
| mbed_official | 324:406fd2029f23 | 4181 | #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) |
| mbed_official | 324:406fd2029f23 | 4182 | /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 4183 | #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 4184 | /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ |
| mbed_official | 324:406fd2029f23 | 4185 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) |
| mbed_official | 324:406fd2029f23 | 4186 | /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ |
| mbed_official | 324:406fd2029f23 | 4187 | #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) |
| mbed_official | 324:406fd2029f23 | 4188 | /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ |
| mbed_official | 324:406fd2029f23 | 4189 | #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) |
| mbed_official | 324:406fd2029f23 | 4190 | /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ |
| mbed_official | 324:406fd2029f23 | 4191 | #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) |
| mbed_official | 324:406fd2029f23 | 4192 | /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ |
| mbed_official | 324:406fd2029f23 | 4193 | #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) |
| mbed_official | 324:406fd2029f23 | 4194 | /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ |
| mbed_official | 324:406fd2029f23 | 4195 | #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) |
| mbed_official | 324:406fd2029f23 | 4196 | /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ |
| mbed_official | 324:406fd2029f23 | 4197 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) |
| mbed_official | 324:406fd2029f23 | 4198 | /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ |
| mbed_official | 324:406fd2029f23 | 4199 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) |
| mbed_official | 324:406fd2029f23 | 4200 | /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ |
| mbed_official | 324:406fd2029f23 | 4201 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) |
| mbed_official | 324:406fd2029f23 | 4202 | /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ |
| mbed_official | 324:406fd2029f23 | 4203 | #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) |
| mbed_official | 324:406fd2029f23 | 4204 | /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 4205 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) |
| mbed_official | 324:406fd2029f23 | 4206 | /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ |
| mbed_official | 324:406fd2029f23 | 4207 | #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) |
| mbed_official | 324:406fd2029f23 | 4208 | /* @brief Has miscellanious control register (register MCR). */ |
| mbed_official | 324:406fd2029f23 | 4209 | #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) |
| mbed_official | 324:406fd2029f23 | 4210 | /* @brief Has COP watchdog (registers COPC and SRVCOP). */ |
| mbed_official | 324:406fd2029f23 | 4211 | #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) |
| mbed_official | 324:406fd2029f23 | 4212 | /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ |
| mbed_official | 324:406fd2029f23 | 4213 | #define FSL_FEATURE_SIM_HAS_COP_STOP (0) |
| mbed_official | 146:f64d43ff0c18 | 4214 | #else |
| mbed_official | 324:406fd2029f23 | 4215 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 4216 | #endif |
| mbed_official | 146:f64d43ff0c18 | 4217 | |
| mbed_official | 324:406fd2029f23 | 4218 | #endif /* __FSL_SIM_FEATURES_H__ */ |
| mbed_official | 324:406fd2029f23 | 4219 | |
| mbed_official | 146:f64d43ff0c18 | 4220 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 4221 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 4222 | ******************************************************************************/ |
