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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/sai/fsl_sai_features.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
- Parent:
- 149:1fb5f62b92bd
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Version: rev. 1.0, 2014-05-14 |
| mbed_official | 324:406fd2029f23 | 4 | ** Build: b140515 |
| mbed_official | 324:406fd2029f23 | 5 | ** |
| mbed_official | 324:406fd2029f23 | 6 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 7 | ** Chip specific module features. |
| mbed_official | 324:406fd2029f23 | 8 | ** |
| mbed_official | 324:406fd2029f23 | 9 | ** Copyright: 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 10 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 13 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 16 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 20 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 21 | ** |
| mbed_official | 324:406fd2029f23 | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 23 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 24 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 25 | ** |
| mbed_official | 324:406fd2029f23 | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 36 | ** |
| mbed_official | 324:406fd2029f23 | 37 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 38 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 39 | ** |
| mbed_official | 324:406fd2029f23 | 40 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 41 | ** - rev. 1.0 (2014-05-14) |
| mbed_official | 324:406fd2029f23 | 42 | ** Customer release. |
| mbed_official | 324:406fd2029f23 | 43 | ** |
| mbed_official | 324:406fd2029f23 | 44 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 45 | */ |
| mbed_official | 324:406fd2029f23 | 46 | |
| mbed_official | 324:406fd2029f23 | 47 | #if !defined(__FSL_SAI_FEATURES_H__) |
| mbed_official | 324:406fd2029f23 | 48 | #define __FSL_SAI_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 49 | |
| mbed_official | 146:f64d43ff0c18 | 50 | #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ |
| mbed_official | 146:f64d43ff0c18 | 51 | defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 52 | defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 53 | defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ |
| mbed_official | 146:f64d43ff0c18 | 54 | defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 55 | defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 56 | defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ |
| mbed_official | 324:406fd2029f23 | 57 | defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ |
| mbed_official | 324:406fd2029f23 | 58 | defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ |
| mbed_official | 324:406fd2029f23 | 59 | defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || \ |
| mbed_official | 324:406fd2029f23 | 60 | defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 61 | defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 146:f64d43ff0c18 | 62 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 324:406fd2029f23 | 63 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| mbed_official | 324:406fd2029f23 | 64 | #define FSL_FEATURE_SAI_FIFO_COUNT (8) |
| mbed_official | 324:406fd2029f23 | 65 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| mbed_official | 324:406fd2029f23 | 66 | #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 67 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| mbed_official | 324:406fd2029f23 | 68 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) |
| mbed_official | 324:406fd2029f23 | 69 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| mbed_official | 324:406fd2029f23 | 70 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) |
| mbed_official | 324:406fd2029f23 | 71 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| mbed_official | 324:406fd2029f23 | 72 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) |
| mbed_official | 324:406fd2029f23 | 73 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| mbed_official | 324:406fd2029f23 | 74 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) |
| mbed_official | 324:406fd2029f23 | 75 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| mbed_official | 324:406fd2029f23 | 76 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) |
| mbed_official | 324:406fd2029f23 | 77 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| mbed_official | 324:406fd2029f23 | 78 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) |
| mbed_official | 324:406fd2029f23 | 79 | #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ |
| mbed_official | 324:406fd2029f23 | 80 | defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ |
| mbed_official | 146:f64d43ff0c18 | 81 | defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) |
| mbed_official | 324:406fd2029f23 | 82 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| mbed_official | 324:406fd2029f23 | 83 | #define FSL_FEATURE_SAI_FIFO_COUNT (8) |
| mbed_official | 324:406fd2029f23 | 84 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| mbed_official | 324:406fd2029f23 | 85 | #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 86 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| mbed_official | 324:406fd2029f23 | 87 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (16) |
| mbed_official | 324:406fd2029f23 | 88 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| mbed_official | 324:406fd2029f23 | 89 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) |
| mbed_official | 324:406fd2029f23 | 90 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| mbed_official | 324:406fd2029f23 | 91 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) |
| mbed_official | 324:406fd2029f23 | 92 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| mbed_official | 324:406fd2029f23 | 93 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) |
| mbed_official | 324:406fd2029f23 | 94 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| mbed_official | 324:406fd2029f23 | 95 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) |
| mbed_official | 324:406fd2029f23 | 96 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| mbed_official | 324:406fd2029f23 | 97 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) |
| mbed_official | 324:406fd2029f23 | 98 | #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ |
| mbed_official | 324:406fd2029f23 | 99 | defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) |
| mbed_official | 324:406fd2029f23 | 100 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| mbed_official | 324:406fd2029f23 | 101 | #define FSL_FEATURE_SAI_FIFO_COUNT (8) |
| mbed_official | 324:406fd2029f23 | 102 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| mbed_official | 324:406fd2029f23 | 103 | #define FSL_FEATURE_SAI_CHANNEL_COUNT (2) |
| mbed_official | 324:406fd2029f23 | 104 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| mbed_official | 324:406fd2029f23 | 105 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) |
| mbed_official | 324:406fd2029f23 | 106 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| mbed_official | 324:406fd2029f23 | 107 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) |
| mbed_official | 324:406fd2029f23 | 108 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| mbed_official | 324:406fd2029f23 | 109 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) |
| mbed_official | 324:406fd2029f23 | 110 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| mbed_official | 324:406fd2029f23 | 111 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) |
| mbed_official | 324:406fd2029f23 | 112 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| mbed_official | 324:406fd2029f23 | 113 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) |
| mbed_official | 324:406fd2029f23 | 114 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| mbed_official | 324:406fd2029f23 | 115 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) |
| mbed_official | 324:406fd2029f23 | 116 | #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 117 | defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 118 | defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 119 | defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 120 | defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 121 | defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 122 | defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 123 | defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 124 | defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) |
| mbed_official | 324:406fd2029f23 | 125 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| mbed_official | 324:406fd2029f23 | 126 | #define FSL_FEATURE_SAI_FIFO_COUNT (4) |
| mbed_official | 324:406fd2029f23 | 127 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| mbed_official | 324:406fd2029f23 | 128 | #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 129 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| mbed_official | 324:406fd2029f23 | 130 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) |
| mbed_official | 324:406fd2029f23 | 131 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| mbed_official | 324:406fd2029f23 | 132 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) |
| mbed_official | 324:406fd2029f23 | 133 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| mbed_official | 324:406fd2029f23 | 134 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) |
| mbed_official | 324:406fd2029f23 | 135 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| mbed_official | 324:406fd2029f23 | 136 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) |
| mbed_official | 324:406fd2029f23 | 137 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| mbed_official | 324:406fd2029f23 | 138 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) |
| mbed_official | 324:406fd2029f23 | 139 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| mbed_official | 324:406fd2029f23 | 140 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (1) |
| mbed_official | 324:406fd2029f23 | 141 | #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ |
| mbed_official | 324:406fd2029f23 | 142 | defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ |
| mbed_official | 324:406fd2029f23 | 143 | defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
| mbed_official | 324:406fd2029f23 | 144 | /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ |
| mbed_official | 324:406fd2029f23 | 145 | #define FSL_FEATURE_SAI_FIFO_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 146 | /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ |
| mbed_official | 324:406fd2029f23 | 147 | #define FSL_FEATURE_SAI_CHANNEL_COUNT (1) |
| mbed_official | 324:406fd2029f23 | 148 | /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ |
| mbed_official | 324:406fd2029f23 | 149 | #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (2) |
| mbed_official | 324:406fd2029f23 | 150 | /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ |
| mbed_official | 324:406fd2029f23 | 151 | #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) |
| mbed_official | 324:406fd2029f23 | 152 | /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ |
| mbed_official | 324:406fd2029f23 | 153 | #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) |
| mbed_official | 324:406fd2029f23 | 154 | /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ |
| mbed_official | 324:406fd2029f23 | 155 | #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) |
| mbed_official | 324:406fd2029f23 | 156 | /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ |
| mbed_official | 324:406fd2029f23 | 157 | #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) |
| mbed_official | 324:406fd2029f23 | 158 | /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ |
| mbed_official | 324:406fd2029f23 | 159 | #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) |
| mbed_official | 146:f64d43ff0c18 | 160 | #else |
| mbed_official | 146:f64d43ff0c18 | 161 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 162 | #endif |
| mbed_official | 146:f64d43ff0c18 | 163 | |
| mbed_official | 324:406fd2029f23 | 164 | #endif /* __FSL_SAI_FEATURES_H__ */ |
| mbed_official | 324:406fd2029f23 | 165 | |
| mbed_official | 146:f64d43ff0c18 | 166 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 167 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 168 | ******************************************************************************/ |
