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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal_modes.c@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 324:406fd2029f23 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 3 | * All rights reserved. |
| mbed_official | 324:406fd2029f23 | 4 | * |
| mbed_official | 324:406fd2029f23 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 6 | * are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 7 | * |
| mbed_official | 324:406fd2029f23 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 9 | * of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 10 | * |
| mbed_official | 324:406fd2029f23 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 13 | * other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 14 | * |
| mbed_official | 324:406fd2029f23 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 16 | * contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 17 | * software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 18 | * |
| mbed_official | 324:406fd2029f23 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 29 | */ |
| mbed_official | 324:406fd2029f23 | 30 | |
| mbed_official | 324:406fd2029f23 | 31 | #include "fsl_mcg_hal_modes.h" |
| mbed_official | 324:406fd2029f23 | 32 | |
| mbed_official | 324:406fd2029f23 | 33 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 34 | * Definitions |
| mbed_official | 324:406fd2029f23 | 35 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 36 | |
| mbed_official | 324:406fd2029f23 | 37 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 38 | * Code |
| mbed_official | 324:406fd2029f23 | 39 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 40 | |
| mbed_official | 324:406fd2029f23 | 41 | /***************************************************************** |
| mbed_official | 324:406fd2029f23 | 42 | * MCG clock mode transition functions |
| mbed_official | 324:406fd2029f23 | 43 | * |
| mbed_official | 324:406fd2029f23 | 44 | * FEI -> FEE |
| mbed_official | 324:406fd2029f23 | 45 | * FEI -> FBI |
| mbed_official | 324:406fd2029f23 | 46 | * FEI -> FBE |
| mbed_official | 324:406fd2029f23 | 47 | * |
| mbed_official | 324:406fd2029f23 | 48 | * FEE -> FEI |
| mbed_official | 324:406fd2029f23 | 49 | * FEE -> FBI |
| mbed_official | 324:406fd2029f23 | 50 | * FEE -> FBE |
| mbed_official | 324:406fd2029f23 | 51 | * |
| mbed_official | 324:406fd2029f23 | 52 | * FBI -> FEI |
| mbed_official | 324:406fd2029f23 | 53 | * FBI -> FEE |
| mbed_official | 324:406fd2029f23 | 54 | * FBI -> FBE |
| mbed_official | 324:406fd2029f23 | 55 | * FBI -> BLPI |
| mbed_official | 324:406fd2029f23 | 56 | * |
| mbed_official | 324:406fd2029f23 | 57 | * BLPI -> FBI |
| mbed_official | 324:406fd2029f23 | 58 | * |
| mbed_official | 324:406fd2029f23 | 59 | * FBE -> FEE |
| mbed_official | 324:406fd2029f23 | 60 | * FBE -> FEI |
| mbed_official | 324:406fd2029f23 | 61 | * FBE -> FBI |
| mbed_official | 324:406fd2029f23 | 62 | * FBE -> PBE |
| mbed_official | 324:406fd2029f23 | 63 | * FBE -> BLPE |
| mbed_official | 324:406fd2029f23 | 64 | * |
| mbed_official | 324:406fd2029f23 | 65 | * PBE -> FBE |
| mbed_official | 324:406fd2029f23 | 66 | * PBE -> PEE |
| mbed_official | 324:406fd2029f23 | 67 | * PBE -> BLPE |
| mbed_official | 324:406fd2029f23 | 68 | * |
| mbed_official | 324:406fd2029f23 | 69 | * BLPE -> FBE |
| mbed_official | 324:406fd2029f23 | 70 | * BLPE -> PBE |
| mbed_official | 324:406fd2029f23 | 71 | * |
| mbed_official | 324:406fd2029f23 | 72 | * PEE -> PBE |
| mbed_official | 324:406fd2029f23 | 73 | * |
| mbed_official | 324:406fd2029f23 | 74 | *****************************************************************/ |
| mbed_official | 324:406fd2029f23 | 75 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 76 | * |
| mbed_official | 324:406fd2029f23 | 77 | * Functon name : CLOCK_HAL_GetMcgMode |
| mbed_official | 324:406fd2029f23 | 78 | * Description : internal function will check the mcg registers and determine |
| mbed_official | 324:406fd2029f23 | 79 | * the current mcg mode |
| mbed_official | 324:406fd2029f23 | 80 | * |
| mbed_official | 324:406fd2029f23 | 81 | * Return value : mcgMode or error code mcg_modes_t defined in fsl_mcg_hal_modes.h |
| mbed_official | 324:406fd2029f23 | 82 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 83 | mcg_modes_t CLOCK_HAL_GetMcgMode(uint32_t baseAddr) |
| mbed_official | 324:406fd2029f23 | 84 | { |
| mbed_official | 324:406fd2029f23 | 85 | /* Check MSG is in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 86 | if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */ |
| mbed_official | 324:406fd2029f23 | 87 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) /* FLL ref is internal ref clk (IREFST=1) */ |
| mbed_official | 324:406fd2029f23 | 88 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 89 | && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */ |
| mbed_official | 324:406fd2029f23 | 90 | #else |
| mbed_official | 324:406fd2029f23 | 91 | ) |
| mbed_official | 324:406fd2029f23 | 92 | #endif |
| mbed_official | 324:406fd2029f23 | 93 | { |
| mbed_official | 324:406fd2029f23 | 94 | return kMcgModeFEI; /* return FEI code */ |
| mbed_official | 324:406fd2029f23 | 95 | } |
| mbed_official | 324:406fd2029f23 | 96 | /* Check MCG is in PEE mode */ |
| mbed_official | 324:406fd2029f23 | 97 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll) && /* CLKS mux is PLL output (CLKST=3) */ |
| mbed_official | 324:406fd2029f23 | 98 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */ |
| mbed_official | 324:406fd2029f23 | 99 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 100 | && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel)) /* PLLS mux is PLL or PLLCS (PLLST=1) */ |
| mbed_official | 324:406fd2029f23 | 101 | #else |
| mbed_official | 324:406fd2029f23 | 102 | ) |
| mbed_official | 324:406fd2029f23 | 103 | #endif |
| mbed_official | 324:406fd2029f23 | 104 | { |
| mbed_official | 324:406fd2029f23 | 105 | return kMcgModePEE; /* return PEE code */ |
| mbed_official | 324:406fd2029f23 | 106 | } |
| mbed_official | 324:406fd2029f23 | 107 | /* Check MCG is in PBE mode */ |
| mbed_official | 324:406fd2029f23 | 108 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ |
| mbed_official | 324:406fd2029f23 | 109 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ |
| mbed_official | 324:406fd2029f23 | 110 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 111 | (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) && /* PLLS mux is PLL or PLLCS (PLLST=1) */ |
| mbed_official | 324:406fd2029f23 | 112 | #endif |
| mbed_official | 324:406fd2029f23 | 113 | (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ |
| mbed_official | 324:406fd2029f23 | 114 | { |
| mbed_official | 324:406fd2029f23 | 115 | return kMcgModePBE; /* return PBE code */ |
| mbed_official | 324:406fd2029f23 | 116 | } |
| mbed_official | 324:406fd2029f23 | 117 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 118 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ |
| mbed_official | 324:406fd2029f23 | 119 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ |
| mbed_official | 324:406fd2029f23 | 120 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 121 | (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ |
| mbed_official | 324:406fd2029f23 | 122 | #endif |
| mbed_official | 324:406fd2029f23 | 123 | (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ |
| mbed_official | 324:406fd2029f23 | 124 | { |
| mbed_official | 324:406fd2029f23 | 125 | return kMcgModeFBE; /* return FBE code */ |
| mbed_official | 324:406fd2029f23 | 126 | } |
| mbed_official | 324:406fd2029f23 | 127 | /* Check MCG is in BLPE mode */ |
| mbed_official | 324:406fd2029f23 | 128 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) && /* CLKS mux is external ref clk (CLKST=2) */ |
| mbed_official | 324:406fd2029f23 | 129 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) && /* FLL ref is external ref clk (IREFST=0) */ |
| mbed_official | 324:406fd2029f23 | 130 | (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */ |
| mbed_official | 324:406fd2029f23 | 131 | { |
| mbed_official | 324:406fd2029f23 | 132 | return kMcgModeBLPE; /* return BLPE code */ |
| mbed_official | 324:406fd2029f23 | 133 | } |
| mbed_official | 324:406fd2029f23 | 134 | /* Check if in BLPI mode */ |
| mbed_official | 324:406fd2029f23 | 135 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */ |
| mbed_official | 324:406fd2029f23 | 136 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */ |
| mbed_official | 324:406fd2029f23 | 137 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 138 | (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ |
| mbed_official | 324:406fd2029f23 | 139 | #endif |
| mbed_official | 324:406fd2029f23 | 140 | (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelLowPower))/* MCG_C2[LP] bit is set (LP=1) */ |
| mbed_official | 324:406fd2029f23 | 141 | { |
| mbed_official | 324:406fd2029f23 | 142 | return kMcgModeBLPI; /* return BLPI code */ |
| mbed_official | 324:406fd2029f23 | 143 | } |
| mbed_official | 324:406fd2029f23 | 144 | /* Check if in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 145 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) && /* CLKS mux in internal ref clk (CLKST=1) */ |
| mbed_official | 324:406fd2029f23 | 146 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) && /* FLL ref is internal ref clk (IREFST=1) */ |
| mbed_official | 324:406fd2029f23 | 147 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 148 | (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) && /* PLLS mux is FLL (PLLST=0) */ |
| mbed_official | 324:406fd2029f23 | 149 | #endif |
| mbed_official | 324:406fd2029f23 | 150 | (CLOCK_HAL_GetLowPowerMode(baseAddr) == kMcgLowPowerSelNormal)) /* MCG_C2[LP] bit is not set (LP=0) */ |
| mbed_official | 324:406fd2029f23 | 151 | { |
| mbed_official | 324:406fd2029f23 | 152 | return kMcgModeFBI; /* return FBI code */ |
| mbed_official | 324:406fd2029f23 | 153 | } |
| mbed_official | 324:406fd2029f23 | 154 | /* Check MCG is in FEE mode */ |
| mbed_official | 324:406fd2029f23 | 155 | else if ((CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) && /* CLKS mux is FLL output (CLKST=0) */ |
| mbed_official | 324:406fd2029f23 | 156 | (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatExternal) /* FLL ref is external ref clk (IREFST=0) */ |
| mbed_official | 324:406fd2029f23 | 157 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 158 | && (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll)) /* PLLS mux is FLL (PLLST=0) */ |
| mbed_official | 324:406fd2029f23 | 159 | #else |
| mbed_official | 324:406fd2029f23 | 160 | ) |
| mbed_official | 324:406fd2029f23 | 161 | #endif |
| mbed_official | 324:406fd2029f23 | 162 | { |
| mbed_official | 324:406fd2029f23 | 163 | return kMcgModeFEE; /* return FEE code */ |
| mbed_official | 324:406fd2029f23 | 164 | } |
| mbed_official | 324:406fd2029f23 | 165 | else |
| mbed_official | 324:406fd2029f23 | 166 | { |
| mbed_official | 324:406fd2029f23 | 167 | return kMcgModeError; /* error unknown mode */ |
| mbed_official | 324:406fd2029f23 | 168 | } |
| mbed_official | 324:406fd2029f23 | 169 | } /* CLOCK_HAL_GetMcgMode */ |
| mbed_official | 324:406fd2029f23 | 170 | |
| mbed_official | 324:406fd2029f23 | 171 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 172 | * |
| mbed_official | 324:406fd2029f23 | 173 | * Functon name : CLOCK_HAL_GetFllFrequency |
| mbed_official | 324:406fd2029f23 | 174 | * Description : internal function to check the fll frequency |
| mbed_official | 324:406fd2029f23 | 175 | * This function will calculate and check the fll frequency value based on input value. |
| mbed_official | 324:406fd2029f23 | 176 | * |
| mbed_official | 324:406fd2029f23 | 177 | * Parameters: fllRef - fll reference clock in Hz. |
| mbed_official | 324:406fd2029f23 | 178 | * |
| mbed_official | 324:406fd2029f23 | 179 | * Return value : fll output frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 180 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 181 | uint32_t CLOCK_HAL_GetFllFrequency(uint32_t baseAddr, int32_t fllRef) |
| mbed_official | 324:406fd2029f23 | 182 | { |
| mbed_official | 324:406fd2029f23 | 183 | int32_t fllFreqHz = 0; |
| mbed_official | 324:406fd2029f23 | 184 | |
| mbed_official | 324:406fd2029f23 | 185 | /* Check that only allowed ranges have been selected */ |
| mbed_official | 324:406fd2029f23 | 186 | if (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr) > kMcgDigitalControlledOscRangeSelMid) |
| mbed_official | 324:406fd2029f23 | 187 | { |
| mbed_official | 324:406fd2029f23 | 188 | return kMcgErrFllDrstDrsRange; /* return error code if DRS range 2 or 3 selected */ |
| mbed_official | 324:406fd2029f23 | 189 | } |
| mbed_official | 324:406fd2029f23 | 190 | |
| mbed_official | 324:406fd2029f23 | 191 | /* if DMX32 set */ |
| mbed_official | 324:406fd2029f23 | 192 | if (CLOCK_HAL_GetDmx32(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 193 | { |
| mbed_official | 324:406fd2029f23 | 194 | /* determine multiplier based on DRS */ |
| mbed_official | 324:406fd2029f23 | 195 | switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 196 | { |
| mbed_official | 324:406fd2029f23 | 197 | case 0: |
| mbed_official | 324:406fd2029f23 | 198 | fllFreqHz = (fllRef * kMcgConstant732); |
| mbed_official | 324:406fd2029f23 | 199 | if (fllFreqHz < kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 200 | { |
| mbed_official | 324:406fd2029f23 | 201 | return kMcgErrFllRange0Min; |
| mbed_official | 324:406fd2029f23 | 202 | } |
| mbed_official | 324:406fd2029f23 | 203 | else if (fllFreqHz > kMcgConstant25000000) |
| mbed_official | 324:406fd2029f23 | 204 | { |
| mbed_official | 324:406fd2029f23 | 205 | return kMcgErrFllRange0Max; |
| mbed_official | 324:406fd2029f23 | 206 | } |
| mbed_official | 324:406fd2029f23 | 207 | break; |
| mbed_official | 324:406fd2029f23 | 208 | case 1: |
| mbed_official | 324:406fd2029f23 | 209 | fllFreqHz = (fllRef * kMcgConstant1464); |
| mbed_official | 324:406fd2029f23 | 210 | if (fllFreqHz < kMcgConstant40000000) |
| mbed_official | 324:406fd2029f23 | 211 | { |
| mbed_official | 324:406fd2029f23 | 212 | return kMcgErrFllRange1Min; |
| mbed_official | 324:406fd2029f23 | 213 | } |
| mbed_official | 324:406fd2029f23 | 214 | else if (fllFreqHz > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 215 | { |
| mbed_official | 324:406fd2029f23 | 216 | return kMcgErrFllRange1Max; |
| mbed_official | 324:406fd2029f23 | 217 | } |
| mbed_official | 324:406fd2029f23 | 218 | break; |
| mbed_official | 324:406fd2029f23 | 219 | case 2: |
| mbed_official | 324:406fd2029f23 | 220 | fllFreqHz = (fllRef * kMcgConstant2197); |
| mbed_official | 324:406fd2029f23 | 221 | if (fllFreqHz < kMcgConstant60000000) |
| mbed_official | 324:406fd2029f23 | 222 | { |
| mbed_official | 324:406fd2029f23 | 223 | return kMcgErrFllRange2Min; |
| mbed_official | 324:406fd2029f23 | 224 | } |
| mbed_official | 324:406fd2029f23 | 225 | else if (fllFreqHz > kMcgConstant75000000) |
| mbed_official | 324:406fd2029f23 | 226 | { |
| mbed_official | 324:406fd2029f23 | 227 | return kMcgErrFllRange2Max; |
| mbed_official | 324:406fd2029f23 | 228 | } |
| mbed_official | 324:406fd2029f23 | 229 | break; |
| mbed_official | 324:406fd2029f23 | 230 | case 3: |
| mbed_official | 324:406fd2029f23 | 231 | fllFreqHz = (fllRef * kMcgConstant2929); |
| mbed_official | 324:406fd2029f23 | 232 | if (fllFreqHz < kMcgConstant80000000) |
| mbed_official | 324:406fd2029f23 | 233 | { |
| mbed_official | 324:406fd2029f23 | 234 | return kMcgErrFllRange3Min; |
| mbed_official | 324:406fd2029f23 | 235 | } |
| mbed_official | 324:406fd2029f23 | 236 | else if (fllFreqHz > kMcgConstant100000000) |
| mbed_official | 324:406fd2029f23 | 237 | { |
| mbed_official | 324:406fd2029f23 | 238 | return kMcgErrFllRange3Max; |
| mbed_official | 324:406fd2029f23 | 239 | } |
| mbed_official | 324:406fd2029f23 | 240 | break; |
| mbed_official | 324:406fd2029f23 | 241 | default: |
| mbed_official | 324:406fd2029f23 | 242 | break; |
| mbed_official | 324:406fd2029f23 | 243 | } |
| mbed_official | 324:406fd2029f23 | 244 | } |
| mbed_official | 324:406fd2029f23 | 245 | /* if DMX32 = 0 */ |
| mbed_official | 324:406fd2029f23 | 246 | else |
| mbed_official | 324:406fd2029f23 | 247 | { |
| mbed_official | 324:406fd2029f23 | 248 | /* determine multiplier based on DRS */ |
| mbed_official | 324:406fd2029f23 | 249 | switch (CLOCK_HAL_GetDigitalControlledOscRangeMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 250 | { |
| mbed_official | 324:406fd2029f23 | 251 | case 0: |
| mbed_official | 324:406fd2029f23 | 252 | fllFreqHz = (fllRef * kMcgConstant640); |
| mbed_official | 324:406fd2029f23 | 253 | if (fllFreqHz < kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 254 | { |
| mbed_official | 324:406fd2029f23 | 255 | return kMcgErrFllRange0Min; |
| mbed_official | 324:406fd2029f23 | 256 | } |
| mbed_official | 324:406fd2029f23 | 257 | else if (fllFreqHz > kMcgConstant25000000) |
| mbed_official | 324:406fd2029f23 | 258 | { |
| mbed_official | 324:406fd2029f23 | 259 | return kMcgErrFllRange0Max; |
| mbed_official | 324:406fd2029f23 | 260 | } |
| mbed_official | 324:406fd2029f23 | 261 | break; |
| mbed_official | 324:406fd2029f23 | 262 | case 1: |
| mbed_official | 324:406fd2029f23 | 263 | fllFreqHz = (fllRef * kMcgConstant1280); |
| mbed_official | 324:406fd2029f23 | 264 | if (fllFreqHz < kMcgConstant40000000) |
| mbed_official | 324:406fd2029f23 | 265 | { |
| mbed_official | 324:406fd2029f23 | 266 | return kMcgErrFllRange1Min; |
| mbed_official | 324:406fd2029f23 | 267 | } |
| mbed_official | 324:406fd2029f23 | 268 | else if (fllFreqHz > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 269 | { |
| mbed_official | 324:406fd2029f23 | 270 | return kMcgErrFllRange1Max; |
| mbed_official | 324:406fd2029f23 | 271 | } |
| mbed_official | 324:406fd2029f23 | 272 | break; |
| mbed_official | 324:406fd2029f23 | 273 | case 2: |
| mbed_official | 324:406fd2029f23 | 274 | fllFreqHz = (fllRef * kMcgConstant1920); |
| mbed_official | 324:406fd2029f23 | 275 | if (fllFreqHz < kMcgConstant60000000) |
| mbed_official | 324:406fd2029f23 | 276 | { |
| mbed_official | 324:406fd2029f23 | 277 | return kMcgErrFllRange2Min; |
| mbed_official | 324:406fd2029f23 | 278 | } |
| mbed_official | 324:406fd2029f23 | 279 | else if (fllFreqHz > kMcgConstant75000000) |
| mbed_official | 324:406fd2029f23 | 280 | { |
| mbed_official | 324:406fd2029f23 | 281 | return kMcgErrFllRange2Max; |
| mbed_official | 324:406fd2029f23 | 282 | } |
| mbed_official | 324:406fd2029f23 | 283 | break; |
| mbed_official | 324:406fd2029f23 | 284 | case 3: |
| mbed_official | 324:406fd2029f23 | 285 | fllFreqHz = (fllRef * kMcgConstant2560); |
| mbed_official | 324:406fd2029f23 | 286 | if (fllFreqHz < kMcgConstant80000000) |
| mbed_official | 324:406fd2029f23 | 287 | { |
| mbed_official | 324:406fd2029f23 | 288 | return kMcgErrFllRange3Min; |
| mbed_official | 324:406fd2029f23 | 289 | } |
| mbed_official | 324:406fd2029f23 | 290 | else if (fllFreqHz > kMcgConstant100000000) |
| mbed_official | 324:406fd2029f23 | 291 | { |
| mbed_official | 324:406fd2029f23 | 292 | return kMcgErrFllRange3Max; |
| mbed_official | 324:406fd2029f23 | 293 | } |
| mbed_official | 324:406fd2029f23 | 294 | break; |
| mbed_official | 324:406fd2029f23 | 295 | default: |
| mbed_official | 324:406fd2029f23 | 296 | break; |
| mbed_official | 324:406fd2029f23 | 297 | } |
| mbed_official | 324:406fd2029f23 | 298 | } |
| mbed_official | 324:406fd2029f23 | 299 | return fllFreqHz; |
| mbed_official | 324:406fd2029f23 | 300 | } /* CLOCK_HAL_GetFllFrequency */ |
| mbed_official | 324:406fd2029f23 | 301 | |
| mbed_official | 324:406fd2029f23 | 302 | |
| mbed_official | 324:406fd2029f23 | 303 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 304 | * |
| mbed_official | 324:406fd2029f23 | 305 | * Functon name : CLOCK_HAL_SetFeiToFeeMode |
| mbed_official | 324:406fd2029f23 | 306 | * Description : Mode transition FEI to FEE mode |
| mbed_official | 324:406fd2029f23 | 307 | * This function transitions the MCG from FEI mode to FEE mode. |
| mbed_official | 324:406fd2029f23 | 308 | * |
| mbed_official | 324:406fd2029f23 | 309 | * Parameters: oscselVal - oscillator selection value |
| mbed_official | 324:406fd2029f23 | 310 | * (eunm defined in mcg_oscsel_select_t) |
| mbed_official | 324:406fd2029f23 | 311 | * 0: kMcgOscselOsc, Selects System Oscillator (OSCCLK) |
| mbed_official | 324:406fd2029f23 | 312 | * 1: kMcgOscselRtc, Selects 32 kHz RTC Oscillator |
| mbed_official | 324:406fd2029f23 | 313 | * 2: kMcgOscselIrc, Selects 48 MHz IRC Oscillator (K70) |
| mbed_official | 324:406fd2029f23 | 314 | * crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 315 | * oscselVal - 0 |
| mbed_official | 324:406fd2029f23 | 316 | * erefsVal - 0: osc0 external clock frequency |
| mbed_official | 324:406fd2029f23 | 317 | * erefsVal - 1: osc0 crystal clock frequency |
| mbed_official | 324:406fd2029f23 | 318 | * oscselVal - 1: RTC 32Khz clock source frequency |
| mbed_official | 324:406fd2029f23 | 319 | * oscselVal - 2: IRC 48Mhz clock source frequency |
| mbed_official | 324:406fd2029f23 | 320 | * hgoVal - selects whether low power or high gain mode is selected |
| mbed_official | 324:406fd2029f23 | 321 | * for the crystal oscillator. This value is only valid when |
| mbed_official | 324:406fd2029f23 | 322 | * oscselVal is 0 and erefsVal is 1. |
| mbed_official | 324:406fd2029f23 | 323 | * (enum defined in mcg_high_gain_osc_select_t) |
| mbed_official | 324:406fd2029f23 | 324 | * 0: kMcgHgoSelectLow, Configure for low-power operation |
| mbed_official | 324:406fd2029f23 | 325 | * 1: kMcgHgoSelectHigh, Configure for high-gain operation |
| mbed_official | 324:406fd2029f23 | 326 | * erefsVal - selects external clock or crystal osc |
| mbed_official | 324:406fd2029f23 | 327 | * (enum defined in mcg_external_ref_clock_select_t) |
| mbed_official | 324:406fd2029f23 | 328 | * 0: kMcgErefClockSelectExt, External reference clock requested |
| mbed_official | 324:406fd2029f23 | 329 | * 1: kMcgErefClockSelectOsc, Oscillator requested |
| mbed_official | 324:406fd2029f23 | 330 | * |
| mbed_official | 324:406fd2029f23 | 331 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 332 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 333 | uint32_t CLOCK_HAL_SetFeiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) |
| mbed_official | 324:406fd2029f23 | 334 | { |
| mbed_official | 324:406fd2029f23 | 335 | uint8_t frDivVal; |
| mbed_official | 324:406fd2029f23 | 336 | uint32_t mcgOut, fllRefFreq, i; |
| mbed_official | 324:406fd2029f23 | 337 | |
| mbed_official | 324:406fd2029f23 | 338 | /* check if in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 339 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) |
| mbed_official | 324:406fd2029f23 | 340 | { |
| mbed_official | 324:406fd2029f23 | 341 | return kMcgErrNotInFeiMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 342 | } |
| mbed_official | 324:406fd2029f23 | 343 | |
| mbed_official | 324:406fd2029f23 | 344 | /* check external frequency is less than the maximum frequency */ |
| mbed_official | 324:406fd2029f23 | 345 | if (crystalVal > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 346 | { |
| mbed_official | 324:406fd2029f23 | 347 | return kMcgErrOscEtalRange; /* - external frequency is bigger than max frequency */ |
| mbed_official | 324:406fd2029f23 | 348 | } |
| mbed_official | 324:406fd2029f23 | 349 | |
| mbed_official | 324:406fd2029f23 | 350 | /* check crystal frequency is within spec. if crystal osc is being used */ |
| mbed_official | 324:406fd2029f23 | 351 | if (oscselVal == kMcgOscselOsc) |
| mbed_official | 324:406fd2029f23 | 352 | { |
| mbed_official | 324:406fd2029f23 | 353 | if (erefsVal) |
| mbed_official | 324:406fd2029f23 | 354 | { |
| mbed_official | 324:406fd2029f23 | 355 | /* return error if one of the available crystal options is not available */ |
| mbed_official | 324:406fd2029f23 | 356 | if ((crystalVal < kMcgConstant30000) || |
| mbed_official | 324:406fd2029f23 | 357 | ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || |
| mbed_official | 324:406fd2029f23 | 358 | (crystalVal > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 359 | { |
| mbed_official | 324:406fd2029f23 | 360 | return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ |
| mbed_official | 324:406fd2029f23 | 361 | } |
| mbed_official | 324:406fd2029f23 | 362 | |
| mbed_official | 324:406fd2029f23 | 363 | /* config the hgo settings */ |
| mbed_official | 324:406fd2029f23 | 364 | CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); |
| mbed_official | 324:406fd2029f23 | 365 | } |
| mbed_official | 324:406fd2029f23 | 366 | |
| mbed_official | 324:406fd2029f23 | 367 | /* config the erefs0 settings */ |
| mbed_official | 324:406fd2029f23 | 368 | CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); |
| mbed_official | 324:406fd2029f23 | 369 | } |
| mbed_official | 324:406fd2029f23 | 370 | |
| mbed_official | 324:406fd2029f23 | 371 | /* |
| mbed_official | 324:406fd2029f23 | 372 | * the RANGE value is determined by the external frequency. Since the RANGE parameter |
| mbed_official | 324:406fd2029f23 | 373 | * affects the FRDIV divide value it still needs to be set correctly even if the |
| mbed_official | 324:406fd2029f23 | 374 | * oscillator is not being used |
| mbed_official | 324:406fd2029f23 | 375 | */ |
| mbed_official | 324:406fd2029f23 | 376 | if (crystalVal <= kMcgConstant40000) |
| mbed_official | 324:406fd2029f23 | 377 | { |
| mbed_official | 324:406fd2029f23 | 378 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); |
| mbed_official | 324:406fd2029f23 | 379 | } |
| mbed_official | 324:406fd2029f23 | 380 | else if (crystalVal <= kMcgConstant8000000) |
| mbed_official | 324:406fd2029f23 | 381 | { |
| mbed_official | 324:406fd2029f23 | 382 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); |
| mbed_official | 324:406fd2029f23 | 383 | } |
| mbed_official | 324:406fd2029f23 | 384 | else |
| mbed_official | 324:406fd2029f23 | 385 | { |
| mbed_official | 324:406fd2029f23 | 386 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); |
| mbed_official | 324:406fd2029f23 | 387 | } |
| mbed_official | 324:406fd2029f23 | 388 | |
| mbed_official | 324:406fd2029f23 | 389 | /* determine FRDIV based on reference clock frequency */ |
| mbed_official | 324:406fd2029f23 | 390 | /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */ |
| mbed_official | 324:406fd2029f23 | 391 | if (crystalVal <= kMcgConstant1250000) |
| mbed_official | 324:406fd2029f23 | 392 | { |
| mbed_official | 324:406fd2029f23 | 393 | frDivVal = kMcgConstant0; |
| mbed_official | 324:406fd2029f23 | 394 | } |
| mbed_official | 324:406fd2029f23 | 395 | else if (crystalVal <= kMcgConstant2500000) |
| mbed_official | 324:406fd2029f23 | 396 | { |
| mbed_official | 324:406fd2029f23 | 397 | frDivVal = kMcgConstant1; |
| mbed_official | 324:406fd2029f23 | 398 | } |
| mbed_official | 324:406fd2029f23 | 399 | else if (crystalVal <= kMcgConstant5000000) |
| mbed_official | 324:406fd2029f23 | 400 | { |
| mbed_official | 324:406fd2029f23 | 401 | frDivVal = kMcgConstant2; |
| mbed_official | 324:406fd2029f23 | 402 | } |
| mbed_official | 324:406fd2029f23 | 403 | else if (crystalVal <= kMcgConstant10000000) |
| mbed_official | 324:406fd2029f23 | 404 | { |
| mbed_official | 324:406fd2029f23 | 405 | frDivVal = kMcgConstant3; |
| mbed_official | 324:406fd2029f23 | 406 | } |
| mbed_official | 324:406fd2029f23 | 407 | else if (crystalVal <= kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 408 | { |
| mbed_official | 324:406fd2029f23 | 409 | frDivVal = kMcgConstant4; |
| mbed_official | 324:406fd2029f23 | 410 | } |
| mbed_official | 324:406fd2029f23 | 411 | else |
| mbed_official | 324:406fd2029f23 | 412 | { |
| mbed_official | 324:406fd2029f23 | 413 | frDivVal = kMcgConstant5; |
| mbed_official | 324:406fd2029f23 | 414 | } |
| mbed_official | 324:406fd2029f23 | 415 | |
| mbed_official | 324:406fd2029f23 | 416 | /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ |
| mbed_official | 324:406fd2029f23 | 417 | if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) |
| mbed_official | 324:406fd2029f23 | 418 | { |
| mbed_official | 324:406fd2029f23 | 419 | fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 420 | } |
| mbed_official | 324:406fd2029f23 | 421 | else |
| mbed_official | 324:406fd2029f23 | 422 | { |
| mbed_official | 324:406fd2029f23 | 423 | fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 424 | } |
| mbed_official | 324:406fd2029f23 | 425 | |
| mbed_official | 324:406fd2029f23 | 426 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 427 | /* FLL reference frequency calculated from ext ref freq and FRDIV */ |
| mbed_official | 324:406fd2029f23 | 428 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); |
| mbed_official | 324:406fd2029f23 | 429 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 430 | { |
| mbed_official | 324:406fd2029f23 | 431 | return mcgOut; /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 432 | } |
| mbed_official | 324:406fd2029f23 | 433 | |
| mbed_official | 324:406fd2029f23 | 434 | /* |
| mbed_official | 324:406fd2029f23 | 435 | * Select external oscilator and Reference Divider and clear IREFS to start ext osc |
| mbed_official | 324:406fd2029f23 | 436 | * If IRCLK is required it must be enabled outside of this driver, existing state will |
| mbed_official | 324:406fd2029f23 | 437 | * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 |
| mbed_official | 324:406fd2029f23 | 438 | */ |
| mbed_official | 324:406fd2029f23 | 439 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal); |
| mbed_official | 324:406fd2029f23 | 440 | |
| mbed_official | 324:406fd2029f23 | 441 | /* if the external oscillator is used need to wait for OSCINIT to set */ |
| mbed_official | 324:406fd2029f23 | 442 | if ((oscselVal == kMcgOscselOsc) && (erefsVal)) |
| mbed_official | 324:406fd2029f23 | 443 | { |
| mbed_official | 324:406fd2029f23 | 444 | for (i = 0 ; i < kMcgConstant20000000 ; i++) |
| mbed_official | 324:406fd2029f23 | 445 | { |
| mbed_official | 324:406fd2029f23 | 446 | if (CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 447 | { |
| mbed_official | 324:406fd2029f23 | 448 | break; /* jump out early if OSCINIT sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 449 | } |
| mbed_official | 324:406fd2029f23 | 450 | } |
| mbed_official | 324:406fd2029f23 | 451 | |
| mbed_official | 324:406fd2029f23 | 452 | if (!CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 453 | { |
| mbed_official | 324:406fd2029f23 | 454 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 455 | return kMcgErrOscSetTimeout; |
| mbed_official | 324:406fd2029f23 | 456 | } |
| mbed_official | 324:406fd2029f23 | 457 | } |
| mbed_official | 324:406fd2029f23 | 458 | |
| mbed_official | 324:406fd2029f23 | 459 | /* Wait for clock status bits to show clock source is FLL */ |
| mbed_official | 324:406fd2029f23 | 460 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 461 | { |
| mbed_official | 324:406fd2029f23 | 462 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 463 | { |
| mbed_official | 324:406fd2029f23 | 464 | break; // jump out early if CLKST shows FLL selected before loop finishes |
| mbed_official | 324:406fd2029f23 | 465 | } |
| mbed_official | 324:406fd2029f23 | 466 | } |
| mbed_official | 324:406fd2029f23 | 467 | |
| mbed_official | 324:406fd2029f23 | 468 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 469 | { |
| mbed_official | 324:406fd2029f23 | 470 | return kMcgErrClkst0; // check FLL is really selected and return with error if not |
| mbed_official | 324:406fd2029f23 | 471 | } |
| mbed_official | 324:406fd2029f23 | 472 | |
| mbed_official | 324:406fd2029f23 | 473 | /* |
| mbed_official | 324:406fd2029f23 | 474 | * Now in FEE |
| mbed_official | 324:406fd2029f23 | 475 | * It is recommended that the clock monitor is enabled when using an external clock as the |
| mbed_official | 324:406fd2029f23 | 476 | * clock source/reference. |
| mbed_official | 324:406fd2029f23 | 477 | * It is enabled here but can be removed if this is not required. |
| mbed_official | 324:406fd2029f23 | 478 | */ |
| mbed_official | 324:406fd2029f23 | 479 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); |
| mbed_official | 324:406fd2029f23 | 480 | |
| mbed_official | 324:406fd2029f23 | 481 | return mcgOut; /* MCGOUT frequency equals FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 482 | } /* CLOCK_HAL_SetFeiToFeeMode */ |
| mbed_official | 324:406fd2029f23 | 483 | |
| mbed_official | 324:406fd2029f23 | 484 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 485 | * |
| mbed_official | 324:406fd2029f23 | 486 | * Functon name : CLOCK_HAL_SetFeiToFbiMode |
| mbed_official | 324:406fd2029f23 | 487 | * Description : Mode transition FEI to FBI mode |
| mbed_official | 324:406fd2029f23 | 488 | * This function transitions the MCG from FEI mode to FBI mode. |
| mbed_official | 324:406fd2029f23 | 489 | * |
| mbed_official | 324:406fd2029f23 | 490 | * Parameters: ircFreq - internal reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 491 | * ircSelect - slow or fast clock selection |
| mbed_official | 324:406fd2029f23 | 492 | * 0: slow, 1: fast |
| mbed_official | 324:406fd2029f23 | 493 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 494 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 495 | uint32_t CLOCK_HAL_SetFeiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) |
| mbed_official | 324:406fd2029f23 | 496 | { |
| mbed_official | 324:406fd2029f23 | 497 | uint8_t fcrDivVal; |
| mbed_official | 324:406fd2029f23 | 498 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 499 | |
| mbed_official | 324:406fd2029f23 | 500 | /* Check MCG is in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 501 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) |
| mbed_official | 324:406fd2029f23 | 502 | { |
| mbed_official | 324:406fd2029f23 | 503 | return kMcgErrNotInFeiMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 504 | } |
| mbed_official | 324:406fd2029f23 | 505 | |
| mbed_official | 324:406fd2029f23 | 506 | |
| mbed_official | 324:406fd2029f23 | 507 | /* Check that the irc frequency matches the selected IRC */ |
| mbed_official | 324:406fd2029f23 | 508 | if (!(ircSelect)) |
| mbed_official | 324:406fd2029f23 | 509 | { |
| mbed_official | 324:406fd2029f23 | 510 | if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) |
| mbed_official | 324:406fd2029f23 | 511 | { |
| mbed_official | 324:406fd2029f23 | 512 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 513 | } |
| mbed_official | 324:406fd2029f23 | 514 | } |
| mbed_official | 324:406fd2029f23 | 515 | else |
| mbed_official | 324:406fd2029f23 | 516 | { |
| mbed_official | 324:406fd2029f23 | 517 | if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) |
| mbed_official | 324:406fd2029f23 | 518 | { |
| mbed_official | 324:406fd2029f23 | 519 | return kMcgErrIrcFastRange; |
| mbed_official | 324:406fd2029f23 | 520 | } /* Fast IRC freq */ |
| mbed_official | 324:406fd2029f23 | 521 | } |
| mbed_official | 324:406fd2029f23 | 522 | |
| mbed_official | 324:406fd2029f23 | 523 | /* Select the desired IRC */ |
| mbed_official | 324:406fd2029f23 | 524 | CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); |
| mbed_official | 324:406fd2029f23 | 525 | |
| mbed_official | 324:406fd2029f23 | 526 | /* Change the CLKS mux to select the IRC as the MCGOUT */ |
| mbed_official | 324:406fd2029f23 | 527 | CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelInternal); |
| mbed_official | 324:406fd2029f23 | 528 | |
| mbed_official | 324:406fd2029f23 | 529 | /* Set LP bit to enable the FLL */ |
| mbed_official | 324:406fd2029f23 | 530 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 531 | |
| mbed_official | 324:406fd2029f23 | 532 | /* wait until internal reference switches to requested irc. */ |
| mbed_official | 324:406fd2029f23 | 533 | if (ircSelect == kMcgInternalRefClkSelSlow) |
| mbed_official | 324:406fd2029f23 | 534 | { |
| mbed_official | 324:406fd2029f23 | 535 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 536 | { |
| mbed_official | 324:406fd2029f23 | 537 | if (!(MCG_S & MCG_S_IRCST_MASK)) |
| mbed_official | 324:406fd2029f23 | 538 | { |
| mbed_official | 324:406fd2029f23 | 539 | break; /* jump out early if IRCST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 540 | } |
| mbed_official | 324:406fd2029f23 | 541 | } |
| mbed_official | 324:406fd2029f23 | 542 | if (MCG_S & MCG_S_IRCST_MASK) |
| mbed_official | 324:406fd2029f23 | 543 | { |
| mbed_official | 324:406fd2029f23 | 544 | /* check bit is really clear and return with error if set */ |
| mbed_official | 324:406fd2029f23 | 545 | return kMcgErrIrcstClearTimeout; |
| mbed_official | 324:406fd2029f23 | 546 | } |
| mbed_official | 324:406fd2029f23 | 547 | } |
| mbed_official | 324:406fd2029f23 | 548 | else |
| mbed_official | 324:406fd2029f23 | 549 | { |
| mbed_official | 324:406fd2029f23 | 550 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 551 | { |
| mbed_official | 324:406fd2029f23 | 552 | if (MCG_S & MCG_S_IRCST_MASK) |
| mbed_official | 324:406fd2029f23 | 553 | { |
| mbed_official | 324:406fd2029f23 | 554 | break; /* jump out early if IRCST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 555 | } |
| mbed_official | 324:406fd2029f23 | 556 | } |
| mbed_official | 324:406fd2029f23 | 557 | if (!(MCG_S & MCG_S_IRCST_MASK)) |
| mbed_official | 324:406fd2029f23 | 558 | { |
| mbed_official | 324:406fd2029f23 | 559 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 560 | return kMcgErrIrefstSetTimeout1; |
| mbed_official | 324:406fd2029f23 | 561 | } |
| mbed_official | 324:406fd2029f23 | 562 | } |
| mbed_official | 324:406fd2029f23 | 563 | |
| mbed_official | 324:406fd2029f23 | 564 | /* Wait for clock status bits to update */ |
| mbed_official | 324:406fd2029f23 | 565 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 566 | { |
| mbed_official | 324:406fd2029f23 | 567 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 568 | { |
| mbed_official | 324:406fd2029f23 | 569 | break; /* jump out early if CLKST shows IRC slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 570 | } |
| mbed_official | 324:406fd2029f23 | 571 | } |
| mbed_official | 324:406fd2029f23 | 572 | |
| mbed_official | 324:406fd2029f23 | 573 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 574 | { |
| mbed_official | 324:406fd2029f23 | 575 | /* check IRC is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 576 | return kMcgErrClkst1; |
| mbed_official | 324:406fd2029f23 | 577 | } |
| mbed_official | 324:406fd2029f23 | 578 | |
| mbed_official | 324:406fd2029f23 | 579 | /* Now in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 580 | if (ircSelect == kMcgInternalRefClkSelFast) |
| mbed_official | 324:406fd2029f23 | 581 | { |
| mbed_official | 324:406fd2029f23 | 582 | fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 583 | |
| mbed_official | 324:406fd2029f23 | 584 | /* MCGOUT frequency equals fast IRC frequency divided by 2 */ |
| mbed_official | 324:406fd2029f23 | 585 | return (ircFreq / fcrDivVal); |
| mbed_official | 324:406fd2029f23 | 586 | } |
| mbed_official | 324:406fd2029f23 | 587 | else |
| mbed_official | 324:406fd2029f23 | 588 | { |
| mbed_official | 324:406fd2029f23 | 589 | return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ |
| mbed_official | 324:406fd2029f23 | 590 | } |
| mbed_official | 324:406fd2029f23 | 591 | } /* CLOCK_HAL_SetFeiToFbiMode */ |
| mbed_official | 324:406fd2029f23 | 592 | |
| mbed_official | 324:406fd2029f23 | 593 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 594 | * |
| mbed_official | 324:406fd2029f23 | 595 | * Functon name : CLOCK_HAL_SetFeiToFbeMode |
| mbed_official | 324:406fd2029f23 | 596 | * Description : Mode transition FEI to FBE mode |
| mbed_official | 324:406fd2029f23 | 597 | * This function transitions the MCG from FEI mode to FBE mode. |
| mbed_official | 324:406fd2029f23 | 598 | * |
| mbed_official | 324:406fd2029f23 | 599 | * Parameters: oscselVal - oscillator selection value |
| mbed_official | 324:406fd2029f23 | 600 | * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M |
| mbed_official | 324:406fd2029f23 | 601 | * crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 602 | * oscselVal - 0 |
| mbed_official | 324:406fd2029f23 | 603 | * erefsVal - 0: osc0 external clock frequency |
| mbed_official | 324:406fd2029f23 | 604 | * erefsVal - 1: osc0 crystal clock frequency |
| mbed_official | 324:406fd2029f23 | 605 | * oscselVal - 1: RTC 32Khz clock source frequency |
| mbed_official | 324:406fd2029f23 | 606 | * oscselVal - 2: IRC 48Mhz clock source frequency |
| mbed_official | 324:406fd2029f23 | 607 | * hgoVal - selects whether low power or high gain mode is selected |
| mbed_official | 324:406fd2029f23 | 608 | * for the crystal oscillator. This value is only valid when |
| mbed_official | 324:406fd2029f23 | 609 | * oscselVal is 0 and erefsVal is 1. |
| mbed_official | 324:406fd2029f23 | 610 | * erefsVal - selects external clock (=0) or crystal osc (=1) |
| mbed_official | 324:406fd2029f23 | 611 | * |
| mbed_official | 324:406fd2029f23 | 612 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 613 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 614 | uint32_t CLOCK_HAL_SetFeiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) |
| mbed_official | 324:406fd2029f23 | 615 | { |
| mbed_official | 324:406fd2029f23 | 616 | uint8_t frDivVal; |
| mbed_official | 324:406fd2029f23 | 617 | int16_t i; |
| mbed_official | 324:406fd2029f23 | 618 | |
| mbed_official | 324:406fd2029f23 | 619 | /* check if in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 620 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEI) |
| mbed_official | 324:406fd2029f23 | 621 | { |
| mbed_official | 324:406fd2029f23 | 622 | return kMcgErrNotInFeiMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 623 | } |
| mbed_official | 324:406fd2029f23 | 624 | |
| mbed_official | 324:406fd2029f23 | 625 | /* check external frequency is less than the maximum frequency */ |
| mbed_official | 324:406fd2029f23 | 626 | if (crystalVal > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 627 | { |
| mbed_official | 324:406fd2029f23 | 628 | /* - external frequency is bigger than max frequency */ |
| mbed_official | 324:406fd2029f23 | 629 | return kMcgErrOscEtalRange; |
| mbed_official | 324:406fd2029f23 | 630 | } |
| mbed_official | 324:406fd2029f23 | 631 | |
| mbed_official | 324:406fd2029f23 | 632 | /* check crystal frequency is within spec. if crystal osc is being used */ |
| mbed_official | 324:406fd2029f23 | 633 | if (oscselVal == kMcgOscselOsc) |
| mbed_official | 324:406fd2029f23 | 634 | { |
| mbed_official | 324:406fd2029f23 | 635 | if (erefsVal) |
| mbed_official | 324:406fd2029f23 | 636 | { |
| mbed_official | 324:406fd2029f23 | 637 | /* return error if one of the available crystal options is not available */ |
| mbed_official | 324:406fd2029f23 | 638 | if ((crystalVal < kMcgConstant30000) || |
| mbed_official | 324:406fd2029f23 | 639 | ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || |
| mbed_official | 324:406fd2029f23 | 640 | (crystalVal > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 641 | { |
| mbed_official | 324:406fd2029f23 | 642 | /* - crystal frequency outside allowed range */ |
| mbed_official | 324:406fd2029f23 | 643 | return kMcgErrOscXtalRange; |
| mbed_official | 324:406fd2029f23 | 644 | } |
| mbed_official | 324:406fd2029f23 | 645 | |
| mbed_official | 324:406fd2029f23 | 646 | /* config the hgo settings */ |
| mbed_official | 324:406fd2029f23 | 647 | CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); |
| mbed_official | 324:406fd2029f23 | 648 | } |
| mbed_official | 324:406fd2029f23 | 649 | |
| mbed_official | 324:406fd2029f23 | 650 | /* config the erefs0 settings */ |
| mbed_official | 324:406fd2029f23 | 651 | CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); |
| mbed_official | 324:406fd2029f23 | 652 | } |
| mbed_official | 324:406fd2029f23 | 653 | |
| mbed_official | 324:406fd2029f23 | 654 | /* |
| mbed_official | 324:406fd2029f23 | 655 | * the RANGE value is determined by the external frequency. Since the RANGE parameter |
| mbed_official | 324:406fd2029f23 | 656 | * affects the FRDIV divide value it still needs to be set correctly even if the |
| mbed_official | 324:406fd2029f23 | 657 | * oscillator is not being used |
| mbed_official | 324:406fd2029f23 | 658 | */ |
| mbed_official | 324:406fd2029f23 | 659 | if (crystalVal <= kMcgConstant40000) |
| mbed_official | 324:406fd2029f23 | 660 | { |
| mbed_official | 324:406fd2029f23 | 661 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); |
| mbed_official | 324:406fd2029f23 | 662 | } |
| mbed_official | 324:406fd2029f23 | 663 | else if (crystalVal <= kMcgConstant8000000) |
| mbed_official | 324:406fd2029f23 | 664 | { |
| mbed_official | 324:406fd2029f23 | 665 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); |
| mbed_official | 324:406fd2029f23 | 666 | } |
| mbed_official | 324:406fd2029f23 | 667 | else |
| mbed_official | 324:406fd2029f23 | 668 | { |
| mbed_official | 324:406fd2029f23 | 669 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); |
| mbed_official | 324:406fd2029f23 | 670 | } |
| mbed_official | 324:406fd2029f23 | 671 | |
| mbed_official | 324:406fd2029f23 | 672 | /* determine FRDIV based on reference clock frequency */ |
| mbed_official | 324:406fd2029f23 | 673 | /* since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here. */ |
| mbed_official | 324:406fd2029f23 | 674 | if (crystalVal <= kMcgConstant1250000) |
| mbed_official | 324:406fd2029f23 | 675 | { |
| mbed_official | 324:406fd2029f23 | 676 | frDivVal = kMcgConstant0; |
| mbed_official | 324:406fd2029f23 | 677 | } |
| mbed_official | 324:406fd2029f23 | 678 | else if (crystalVal <= kMcgConstant2500000) |
| mbed_official | 324:406fd2029f23 | 679 | { |
| mbed_official | 324:406fd2029f23 | 680 | frDivVal = kMcgConstant1; |
| mbed_official | 324:406fd2029f23 | 681 | } |
| mbed_official | 324:406fd2029f23 | 682 | else if (crystalVal <= kMcgConstant5000000) |
| mbed_official | 324:406fd2029f23 | 683 | { |
| mbed_official | 324:406fd2029f23 | 684 | frDivVal = kMcgConstant2; |
| mbed_official | 324:406fd2029f23 | 685 | } |
| mbed_official | 324:406fd2029f23 | 686 | else if (crystalVal <= kMcgConstant10000000) |
| mbed_official | 324:406fd2029f23 | 687 | { |
| mbed_official | 324:406fd2029f23 | 688 | frDivVal = kMcgConstant3; |
| mbed_official | 324:406fd2029f23 | 689 | } |
| mbed_official | 324:406fd2029f23 | 690 | else if (crystalVal <= kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 691 | { |
| mbed_official | 324:406fd2029f23 | 692 | frDivVal = kMcgConstant4; |
| mbed_official | 324:406fd2029f23 | 693 | } |
| mbed_official | 324:406fd2029f23 | 694 | else |
| mbed_official | 324:406fd2029f23 | 695 | { |
| mbed_official | 324:406fd2029f23 | 696 | frDivVal = kMcgConstant5; |
| mbed_official | 324:406fd2029f23 | 697 | } |
| mbed_official | 324:406fd2029f23 | 698 | |
| mbed_official | 324:406fd2029f23 | 699 | /* Set LP bit to enable the FLL */ |
| mbed_official | 324:406fd2029f23 | 700 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 701 | |
| mbed_official | 324:406fd2029f23 | 702 | /* |
| mbed_official | 324:406fd2029f23 | 703 | * Select external oscilator and Reference Divider and clear IREFS to start ext osc |
| mbed_official | 324:406fd2029f23 | 704 | * If IRCLK is required it must be enabled outside of this driver, existing state will |
| mbed_official | 324:406fd2029f23 | 705 | * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 |
| mbed_official | 324:406fd2029f23 | 706 | */ |
| mbed_official | 324:406fd2029f23 | 707 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal); |
| mbed_official | 324:406fd2029f23 | 708 | |
| mbed_official | 324:406fd2029f23 | 709 | /* if the external oscillator is used need to wait for OSCINIT to set */ |
| mbed_official | 324:406fd2029f23 | 710 | if ((oscselVal == kMcgOscselOsc) && (erefsVal)) |
| mbed_official | 324:406fd2029f23 | 711 | { |
| mbed_official | 324:406fd2029f23 | 712 | for (i = 0 ; i < kMcgConstant10000 ; i++) |
| mbed_official | 324:406fd2029f23 | 713 | { |
| mbed_official | 324:406fd2029f23 | 714 | if (CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 715 | { |
| mbed_official | 324:406fd2029f23 | 716 | break; /* jump out early if OSCINIT sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 717 | } |
| mbed_official | 324:406fd2029f23 | 718 | } |
| mbed_official | 324:406fd2029f23 | 719 | |
| mbed_official | 324:406fd2029f23 | 720 | if (!CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 721 | { |
| mbed_official | 324:406fd2029f23 | 722 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 723 | return kMcgErrOscSetTimeout; |
| mbed_official | 324:406fd2029f23 | 724 | } |
| mbed_official | 324:406fd2029f23 | 725 | } |
| mbed_official | 324:406fd2029f23 | 726 | |
| mbed_official | 324:406fd2029f23 | 727 | /* wait for Reference clock Status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 728 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 729 | { |
| mbed_official | 324:406fd2029f23 | 730 | if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 731 | { |
| mbed_official | 324:406fd2029f23 | 732 | break; /* jump out early if IREFST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 733 | } |
| mbed_official | 324:406fd2029f23 | 734 | } |
| mbed_official | 324:406fd2029f23 | 735 | |
| mbed_official | 324:406fd2029f23 | 736 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 737 | { |
| mbed_official | 324:406fd2029f23 | 738 | /* check bit is really clear and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 739 | return kMcgErrIrefstClearTimeOut; |
| mbed_official | 324:406fd2029f23 | 740 | } |
| mbed_official | 324:406fd2029f23 | 741 | |
| mbed_official | 324:406fd2029f23 | 742 | /* Wait for clock status bits to show clock source is ext ref clk */ |
| mbed_official | 324:406fd2029f23 | 743 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 744 | { |
| mbed_official | 324:406fd2029f23 | 745 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 746 | { |
| mbed_official | 324:406fd2029f23 | 747 | break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 748 | } |
| mbed_official | 324:406fd2029f23 | 749 | } |
| mbed_official | 324:406fd2029f23 | 750 | |
| mbed_official | 324:406fd2029f23 | 751 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 752 | { |
| mbed_official | 324:406fd2029f23 | 753 | return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 754 | } |
| mbed_official | 324:406fd2029f23 | 755 | |
| mbed_official | 324:406fd2029f23 | 756 | /* |
| mbed_official | 324:406fd2029f23 | 757 | * Now in FBE |
| mbed_official | 324:406fd2029f23 | 758 | * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference. |
| mbed_official | 324:406fd2029f23 | 759 | * It is enabled here but can be removed if this is not required. |
| mbed_official | 324:406fd2029f23 | 760 | */ |
| mbed_official | 324:406fd2029f23 | 761 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); |
| mbed_official | 324:406fd2029f23 | 762 | |
| mbed_official | 324:406fd2029f23 | 763 | return crystalVal; /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 764 | } /* CLOCK_HAL_SetFeiToFbeMode */ |
| mbed_official | 324:406fd2029f23 | 765 | |
| mbed_official | 324:406fd2029f23 | 766 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 767 | * |
| mbed_official | 324:406fd2029f23 | 768 | * Functon name : CLOCK_HAL_SetFeeToFeiMode |
| mbed_official | 324:406fd2029f23 | 769 | * Description : Mode transition FEE to FEI mode |
| mbed_official | 324:406fd2029f23 | 770 | * This function transitions the MCG from FEE mode to FEI mode. |
| mbed_official | 324:406fd2029f23 | 771 | * |
| mbed_official | 324:406fd2029f23 | 772 | * Parameters: ircFreq - internal reference clock frequency value (slow) |
| mbed_official | 324:406fd2029f23 | 773 | * |
| mbed_official | 324:406fd2029f23 | 774 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 775 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 776 | uint32_t CLOCK_HAL_SetFeeToFeiMode(uint32_t baseAddr, uint32_t ircFreq) |
| mbed_official | 324:406fd2029f23 | 777 | { |
| mbed_official | 324:406fd2029f23 | 778 | int16_t i; |
| mbed_official | 324:406fd2029f23 | 779 | uint32_t mcgOut; |
| mbed_official | 324:406fd2029f23 | 780 | |
| mbed_official | 324:406fd2029f23 | 781 | /* Check MCG is in FEE mode */ |
| mbed_official | 324:406fd2029f23 | 782 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) |
| mbed_official | 324:406fd2029f23 | 783 | { |
| mbed_official | 324:406fd2029f23 | 784 | return kMcgErrNotInFeeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 785 | } |
| mbed_official | 324:406fd2029f23 | 786 | |
| mbed_official | 324:406fd2029f23 | 787 | /* Check IRC frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 788 | if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) |
| mbed_official | 324:406fd2029f23 | 789 | { |
| mbed_official | 324:406fd2029f23 | 790 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 791 | } |
| mbed_official | 324:406fd2029f23 | 792 | |
| mbed_official | 324:406fd2029f23 | 793 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 794 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); |
| mbed_official | 324:406fd2029f23 | 795 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 796 | { |
| mbed_official | 324:406fd2029f23 | 797 | /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 798 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 799 | } |
| mbed_official | 324:406fd2029f23 | 800 | |
| mbed_official | 324:406fd2029f23 | 801 | /* Ensure clock monitor is disabled before switching to FEI otherwise |
| mbed_official | 324:406fd2029f23 | 802 | * a loss of clock will trigger |
| mbed_official | 324:406fd2029f23 | 803 | */ |
| mbed_official | 324:406fd2029f23 | 804 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); |
| mbed_official | 324:406fd2029f23 | 805 | |
| mbed_official | 324:406fd2029f23 | 806 | /* Change FLL reference clock from external to internal by setting IREFS bit */ |
| mbed_official | 324:406fd2029f23 | 807 | CLOCK_HAL_SetInternalRefSelMode(baseAddr, kMcgInternalRefClkSrcSlow); |
| mbed_official | 324:406fd2029f23 | 808 | |
| mbed_official | 324:406fd2029f23 | 809 | /* wait for Reference clock to switch to internal reference */ |
| mbed_official | 324:406fd2029f23 | 810 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 811 | { |
| mbed_official | 324:406fd2029f23 | 812 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 813 | { |
| mbed_official | 324:406fd2029f23 | 814 | break; /* jump out early if IREFST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 815 | } |
| mbed_official | 324:406fd2029f23 | 816 | } |
| mbed_official | 324:406fd2029f23 | 817 | |
| mbed_official | 324:406fd2029f23 | 818 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 819 | { |
| mbed_official | 324:406fd2029f23 | 820 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 821 | return kMcgErrIrefstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 822 | } |
| mbed_official | 324:406fd2029f23 | 823 | |
| mbed_official | 324:406fd2029f23 | 824 | /* Now in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 825 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 826 | } /* CLOCK_HAL_SetFeeToFeiMode */ |
| mbed_official | 324:406fd2029f23 | 827 | |
| mbed_official | 324:406fd2029f23 | 828 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 829 | * |
| mbed_official | 324:406fd2029f23 | 830 | * Functon name : CLOCK_HAL_SetFeeToFbiMode |
| mbed_official | 324:406fd2029f23 | 831 | * Description : Mode transition FEE to FBI mode |
| mbed_official | 324:406fd2029f23 | 832 | * This function transitions the MCG from FEE mode to FBI mode. |
| mbed_official | 324:406fd2029f23 | 833 | * |
| mbed_official | 324:406fd2029f23 | 834 | * Parameters: ircFreq - internal reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 835 | * ircSelect - slow or fast clock selection |
| mbed_official | 324:406fd2029f23 | 836 | * 0: slow, 1: fast |
| mbed_official | 324:406fd2029f23 | 837 | * |
| mbed_official | 324:406fd2029f23 | 838 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 839 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 840 | uint32_t CLOCK_HAL_SetFeeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) |
| mbed_official | 324:406fd2029f23 | 841 | { |
| mbed_official | 324:406fd2029f23 | 842 | uint8_t fcrDivVal; |
| mbed_official | 324:406fd2029f23 | 843 | int16_t i; |
| mbed_official | 324:406fd2029f23 | 844 | |
| mbed_official | 324:406fd2029f23 | 845 | /* Check MCG is in FEE mode */ |
| mbed_official | 324:406fd2029f23 | 846 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) |
| mbed_official | 324:406fd2029f23 | 847 | { |
| mbed_official | 324:406fd2029f23 | 848 | return kMcgErrNotInFeeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 849 | } |
| mbed_official | 324:406fd2029f23 | 850 | |
| mbed_official | 324:406fd2029f23 | 851 | /* Check that the irc frequency matches the selected IRC */ |
| mbed_official | 324:406fd2029f23 | 852 | if (!(ircSelect)) |
| mbed_official | 324:406fd2029f23 | 853 | { |
| mbed_official | 324:406fd2029f23 | 854 | if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) |
| mbed_official | 324:406fd2029f23 | 855 | { |
| mbed_official | 324:406fd2029f23 | 856 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 857 | } |
| mbed_official | 324:406fd2029f23 | 858 | } |
| mbed_official | 324:406fd2029f23 | 859 | else |
| mbed_official | 324:406fd2029f23 | 860 | { |
| mbed_official | 324:406fd2029f23 | 861 | if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) |
| mbed_official | 324:406fd2029f23 | 862 | { |
| mbed_official | 324:406fd2029f23 | 863 | return kMcgErrIrcFastRange; |
| mbed_official | 324:406fd2029f23 | 864 | } /* Fast IRC freq */ |
| mbed_official | 324:406fd2029f23 | 865 | } |
| mbed_official | 324:406fd2029f23 | 866 | |
| mbed_official | 324:406fd2029f23 | 867 | /* Select the required IRC */ |
| mbed_official | 324:406fd2029f23 | 868 | CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); |
| mbed_official | 324:406fd2029f23 | 869 | |
| mbed_official | 324:406fd2029f23 | 870 | /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */ |
| mbed_official | 324:406fd2029f23 | 871 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); |
| mbed_official | 324:406fd2029f23 | 872 | |
| mbed_official | 324:406fd2029f23 | 873 | /* Select the IRC as the CLKS mux selection */ |
| mbed_official | 324:406fd2029f23 | 874 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); |
| mbed_official | 324:406fd2029f23 | 875 | |
| mbed_official | 324:406fd2029f23 | 876 | /* wait until internal reference switches to requested irc. */ |
| mbed_official | 324:406fd2029f23 | 877 | if (ircSelect == kMcgInternalRefClkSelSlow) |
| mbed_official | 324:406fd2029f23 | 878 | { |
| mbed_official | 324:406fd2029f23 | 879 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 880 | { |
| mbed_official | 324:406fd2029f23 | 881 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow) |
| mbed_official | 324:406fd2029f23 | 882 | { |
| mbed_official | 324:406fd2029f23 | 883 | break; /* jump out early if IRCST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 884 | } |
| mbed_official | 324:406fd2029f23 | 885 | } |
| mbed_official | 324:406fd2029f23 | 886 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow) |
| mbed_official | 324:406fd2029f23 | 887 | { |
| mbed_official | 324:406fd2029f23 | 888 | /* check bit is really clear and return with error if set */ |
| mbed_official | 324:406fd2029f23 | 889 | return kMcgErrIrcstClearTimeout; |
| mbed_official | 324:406fd2029f23 | 890 | } |
| mbed_official | 324:406fd2029f23 | 891 | } |
| mbed_official | 324:406fd2029f23 | 892 | else |
| mbed_official | 324:406fd2029f23 | 893 | { |
| mbed_official | 324:406fd2029f23 | 894 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 895 | { |
| mbed_official | 324:406fd2029f23 | 896 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast) |
| mbed_official | 324:406fd2029f23 | 897 | { |
| mbed_official | 324:406fd2029f23 | 898 | break; /* jump out early if IRCST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 899 | } |
| mbed_official | 324:406fd2029f23 | 900 | } |
| mbed_official | 324:406fd2029f23 | 901 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast) |
| mbed_official | 324:406fd2029f23 | 902 | { |
| mbed_official | 324:406fd2029f23 | 903 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 904 | return kMcgErrIrefstSetTimeout1; |
| mbed_official | 324:406fd2029f23 | 905 | } |
| mbed_official | 324:406fd2029f23 | 906 | } |
| mbed_official | 324:406fd2029f23 | 907 | |
| mbed_official | 324:406fd2029f23 | 908 | /* Wait for clock status bits to update */ |
| mbed_official | 324:406fd2029f23 | 909 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 910 | { |
| mbed_official | 324:406fd2029f23 | 911 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 912 | { |
| mbed_official | 324:406fd2029f23 | 913 | break; /* jump out early if CLKST shows IRC slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 914 | } |
| mbed_official | 324:406fd2029f23 | 915 | } |
| mbed_official | 324:406fd2029f23 | 916 | |
| mbed_official | 324:406fd2029f23 | 917 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 918 | { |
| mbed_official | 324:406fd2029f23 | 919 | return kMcgErrClkst1; /* check IRC is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 920 | } |
| mbed_official | 324:406fd2029f23 | 921 | |
| mbed_official | 324:406fd2029f23 | 922 | /* wait for Reference clock Status bit to set */ |
| mbed_official | 324:406fd2029f23 | 923 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 924 | { |
| mbed_official | 324:406fd2029f23 | 925 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 926 | { |
| mbed_official | 324:406fd2029f23 | 927 | break; /* jump out early if IREFST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 928 | } |
| mbed_official | 324:406fd2029f23 | 929 | } |
| mbed_official | 324:406fd2029f23 | 930 | |
| mbed_official | 324:406fd2029f23 | 931 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 932 | { |
| mbed_official | 324:406fd2029f23 | 933 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 934 | return kMcgErrIrefstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 935 | } |
| mbed_official | 324:406fd2029f23 | 936 | |
| mbed_official | 324:406fd2029f23 | 937 | /* Now in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 938 | if (ircSelect == kMcgInternalRefClkSelFast) |
| mbed_official | 324:406fd2029f23 | 939 | { |
| mbed_official | 324:406fd2029f23 | 940 | fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 941 | |
| mbed_official | 324:406fd2029f23 | 942 | return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ |
| mbed_official | 324:406fd2029f23 | 943 | } |
| mbed_official | 324:406fd2029f23 | 944 | else |
| mbed_official | 324:406fd2029f23 | 945 | { |
| mbed_official | 324:406fd2029f23 | 946 | return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ |
| mbed_official | 324:406fd2029f23 | 947 | } |
| mbed_official | 324:406fd2029f23 | 948 | } /* CLOCK_HAL_SetFeeToFbiMode */ |
| mbed_official | 324:406fd2029f23 | 949 | |
| mbed_official | 324:406fd2029f23 | 950 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 951 | * |
| mbed_official | 324:406fd2029f23 | 952 | * Functon name : CLOCK_HAL_SetFeeToFbeMode |
| mbed_official | 324:406fd2029f23 | 953 | * Description : Mode transition FEE to FBE mode |
| mbed_official | 324:406fd2029f23 | 954 | * This function transitions the MCG from FEE mode to FBE mode. |
| mbed_official | 324:406fd2029f23 | 955 | * |
| mbed_official | 324:406fd2029f23 | 956 | * Parameters: crystalVal - external reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 957 | * |
| mbed_official | 324:406fd2029f23 | 958 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 959 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 960 | uint32_t CLOCK_HAL_SetFeeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 961 | { |
| mbed_official | 324:406fd2029f23 | 962 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 963 | |
| mbed_official | 324:406fd2029f23 | 964 | /* Check MCG is in FEE mode */ |
| mbed_official | 324:406fd2029f23 | 965 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFEE) |
| mbed_official | 324:406fd2029f23 | 966 | { |
| mbed_official | 324:406fd2029f23 | 967 | return kMcgErrNotInFeeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 968 | } |
| mbed_official | 324:406fd2029f23 | 969 | |
| mbed_official | 324:406fd2029f23 | 970 | /* Set CLKS field to 2 to switch CLKS mux to select ext ref clock */ |
| mbed_official | 324:406fd2029f23 | 971 | CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal); |
| mbed_official | 324:406fd2029f23 | 972 | |
| mbed_official | 324:406fd2029f23 | 973 | /* Wait for clock status bits to show clock source is ext ref clk */ |
| mbed_official | 324:406fd2029f23 | 974 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 975 | { |
| mbed_official | 324:406fd2029f23 | 976 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 977 | { |
| mbed_official | 324:406fd2029f23 | 978 | break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 979 | } |
| mbed_official | 324:406fd2029f23 | 980 | } |
| mbed_official | 324:406fd2029f23 | 981 | |
| mbed_official | 324:406fd2029f23 | 982 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 983 | { |
| mbed_official | 324:406fd2029f23 | 984 | return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 985 | } |
| mbed_official | 324:406fd2029f23 | 986 | |
| mbed_official | 324:406fd2029f23 | 987 | /* Now in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 988 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 989 | } /* CLOCK_HAL_SetFeeToFbeMode */ |
| mbed_official | 324:406fd2029f23 | 990 | |
| mbed_official | 324:406fd2029f23 | 991 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 992 | * |
| mbed_official | 324:406fd2029f23 | 993 | * Functon name : CLOCK_HAL_SetFbiToFeiMode |
| mbed_official | 324:406fd2029f23 | 994 | * Description : Mode transition FBI to FEI mode |
| mbed_official | 324:406fd2029f23 | 995 | * This function transitions the MCG from FBI mode to FEI mode. |
| mbed_official | 324:406fd2029f23 | 996 | * |
| mbed_official | 324:406fd2029f23 | 997 | * Parameters: ircFreq - internal reference clock frequency value (slow) |
| mbed_official | 324:406fd2029f23 | 998 | * |
| mbed_official | 324:406fd2029f23 | 999 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1000 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1001 | uint32_t CLOCK_HAL_SetFbiToFeiMode(uint32_t baseAddr, uint32_t ircFreq) |
| mbed_official | 324:406fd2029f23 | 1002 | { |
| mbed_official | 324:406fd2029f23 | 1003 | int16_t i; |
| mbed_official | 324:406fd2029f23 | 1004 | int32_t mcgOut; |
| mbed_official | 324:406fd2029f23 | 1005 | |
| mbed_official | 324:406fd2029f23 | 1006 | /* check if in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1007 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) |
| mbed_official | 324:406fd2029f23 | 1008 | { |
| mbed_official | 324:406fd2029f23 | 1009 | return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ |
| mbed_official | 324:406fd2029f23 | 1010 | } |
| mbed_official | 324:406fd2029f23 | 1011 | |
| mbed_official | 324:406fd2029f23 | 1012 | /* Check IRC frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 1013 | if ((ircFreq < 31250) || (ircFreq > 39063)) |
| mbed_official | 324:406fd2029f23 | 1014 | { |
| mbed_official | 324:406fd2029f23 | 1015 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 1016 | } |
| mbed_official | 324:406fd2029f23 | 1017 | |
| mbed_official | 324:406fd2029f23 | 1018 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 1019 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); |
| mbed_official | 324:406fd2029f23 | 1020 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 1021 | { |
| mbed_official | 324:406fd2029f23 | 1022 | /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 1023 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 1024 | } |
| mbed_official | 324:406fd2029f23 | 1025 | |
| mbed_official | 324:406fd2029f23 | 1026 | /* Change the CLKS mux to select the FLL output as MCGOUT */ |
| mbed_official | 324:406fd2029f23 | 1027 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); |
| mbed_official | 324:406fd2029f23 | 1028 | |
| mbed_official | 324:406fd2029f23 | 1029 | /* wait for Reference clock Status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 1030 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1031 | { |
| mbed_official | 324:406fd2029f23 | 1032 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1033 | { |
| mbed_official | 324:406fd2029f23 | 1034 | break; /* jump out early if IREFST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1035 | } |
| mbed_official | 324:406fd2029f23 | 1036 | } |
| mbed_official | 324:406fd2029f23 | 1037 | |
| mbed_official | 324:406fd2029f23 | 1038 | if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1039 | { |
| mbed_official | 324:406fd2029f23 | 1040 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1041 | return kMcgErrIrefstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1042 | } |
| mbed_official | 324:406fd2029f23 | 1043 | |
| mbed_official | 324:406fd2029f23 | 1044 | /* Wait for clock status bits to show clock source is ext ref clk */ |
| mbed_official | 324:406fd2029f23 | 1045 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1046 | { |
| mbed_official | 324:406fd2029f23 | 1047 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1048 | { |
| mbed_official | 324:406fd2029f23 | 1049 | break; /* jump out early if CLKST shows FLL slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1050 | } |
| mbed_official | 324:406fd2029f23 | 1051 | } |
| mbed_official | 324:406fd2029f23 | 1052 | |
| mbed_official | 324:406fd2029f23 | 1053 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1054 | { |
| mbed_official | 324:406fd2029f23 | 1055 | return kMcgErrClkst0; /* check FLL is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 1056 | } |
| mbed_official | 324:406fd2029f23 | 1057 | |
| mbed_official | 324:406fd2029f23 | 1058 | /* Now in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 1059 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 1060 | } /* CLOCK_HAL_SetFbiToFeiMode */ |
| mbed_official | 324:406fd2029f23 | 1061 | |
| mbed_official | 324:406fd2029f23 | 1062 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1063 | * |
| mbed_official | 324:406fd2029f23 | 1064 | * Functon name : CLOCK_HAL_SetFbiToFeeMode |
| mbed_official | 324:406fd2029f23 | 1065 | * Description : Mode transition FBI to FEE mode |
| mbed_official | 324:406fd2029f23 | 1066 | * This function transitions the MCG from FBI mode to FEE mode. |
| mbed_official | 324:406fd2029f23 | 1067 | * |
| mbed_official | 324:406fd2029f23 | 1068 | * Parameters: oscselVal - oscillator selection value |
| mbed_official | 324:406fd2029f23 | 1069 | * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M |
| mbed_official | 324:406fd2029f23 | 1070 | * crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 1071 | * oscselVal - 0 |
| mbed_official | 324:406fd2029f23 | 1072 | * erefsVal - 0: osc0 external clock frequency |
| mbed_official | 324:406fd2029f23 | 1073 | * erefsVal - 1: osc0 crystal clock frequency |
| mbed_official | 324:406fd2029f23 | 1074 | * oscselVal - 1: RTC 32Khz clock source frequency |
| mbed_official | 324:406fd2029f23 | 1075 | * oscselVal - 2: IRC 48Mhz clock source frequency |
| mbed_official | 324:406fd2029f23 | 1076 | * hgoVal - selects whether low power or high gain mode is selected |
| mbed_official | 324:406fd2029f23 | 1077 | * for the crystal oscillator. This value is only valid when |
| mbed_official | 324:406fd2029f23 | 1078 | * oscselVal is 0 and erefsVal is 1. |
| mbed_official | 324:406fd2029f23 | 1079 | * erefsVal - selects external clock (=0) or crystal osc (=1) |
| mbed_official | 324:406fd2029f23 | 1080 | * |
| mbed_official | 324:406fd2029f23 | 1081 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1082 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1083 | uint32_t CLOCK_HAL_SetFbiToFeeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) |
| mbed_official | 324:406fd2029f23 | 1084 | { |
| mbed_official | 324:406fd2029f23 | 1085 | uint8_t frDivVal; |
| mbed_official | 324:406fd2029f23 | 1086 | uint32_t i; |
| mbed_official | 324:406fd2029f23 | 1087 | uint32_t mcgOut, fllRefFreq; |
| mbed_official | 324:406fd2029f23 | 1088 | |
| mbed_official | 324:406fd2029f23 | 1089 | /* check if in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1090 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) |
| mbed_official | 324:406fd2029f23 | 1091 | { |
| mbed_official | 324:406fd2029f23 | 1092 | return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ |
| mbed_official | 324:406fd2029f23 | 1093 | } |
| mbed_official | 324:406fd2029f23 | 1094 | |
| mbed_official | 324:406fd2029f23 | 1095 | /* check external frequency is less than the maximum frequency */ |
| mbed_official | 324:406fd2029f23 | 1096 | if (crystalVal > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 1097 | { |
| mbed_official | 324:406fd2029f23 | 1098 | return kMcgErrOscEtalRange; |
| mbed_official | 324:406fd2029f23 | 1099 | } |
| mbed_official | 324:406fd2029f23 | 1100 | |
| mbed_official | 324:406fd2029f23 | 1101 | /* check crystal frequency is within spec. if crystal osc is being used */ |
| mbed_official | 324:406fd2029f23 | 1102 | if (oscselVal == kMcgOscselOsc) |
| mbed_official | 324:406fd2029f23 | 1103 | { |
| mbed_official | 324:406fd2029f23 | 1104 | if (erefsVal) |
| mbed_official | 324:406fd2029f23 | 1105 | { |
| mbed_official | 324:406fd2029f23 | 1106 | /* return error if one of the available crystal options is not available */ |
| mbed_official | 324:406fd2029f23 | 1107 | if ((crystalVal < kMcgConstant30000) || |
| mbed_official | 324:406fd2029f23 | 1108 | ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || |
| mbed_official | 324:406fd2029f23 | 1109 | (crystalVal > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 1110 | { |
| mbed_official | 324:406fd2029f23 | 1111 | return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ |
| mbed_official | 324:406fd2029f23 | 1112 | } |
| mbed_official | 324:406fd2029f23 | 1113 | |
| mbed_official | 324:406fd2029f23 | 1114 | /* config the hgo settings */ |
| mbed_official | 324:406fd2029f23 | 1115 | CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); |
| mbed_official | 324:406fd2029f23 | 1116 | } |
| mbed_official | 324:406fd2029f23 | 1117 | |
| mbed_official | 324:406fd2029f23 | 1118 | /* config the erefs0 settings */ |
| mbed_official | 324:406fd2029f23 | 1119 | CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); |
| mbed_official | 324:406fd2029f23 | 1120 | } |
| mbed_official | 324:406fd2029f23 | 1121 | |
| mbed_official | 324:406fd2029f23 | 1122 | /* |
| mbed_official | 324:406fd2029f23 | 1123 | * the RANGE value is determined by the external frequency. Since the RANGE parameter |
| mbed_official | 324:406fd2029f23 | 1124 | * affects the FRDIV divide value it still needs to be set correctly even if the |
| mbed_official | 324:406fd2029f23 | 1125 | * oscillator is not being used |
| mbed_official | 324:406fd2029f23 | 1126 | */ |
| mbed_official | 324:406fd2029f23 | 1127 | if (crystalVal <= kMcgConstant40000) |
| mbed_official | 324:406fd2029f23 | 1128 | { |
| mbed_official | 324:406fd2029f23 | 1129 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); |
| mbed_official | 324:406fd2029f23 | 1130 | } |
| mbed_official | 324:406fd2029f23 | 1131 | else if (crystalVal <= kMcgConstant8000000) |
| mbed_official | 324:406fd2029f23 | 1132 | { |
| mbed_official | 324:406fd2029f23 | 1133 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); |
| mbed_official | 324:406fd2029f23 | 1134 | } |
| mbed_official | 324:406fd2029f23 | 1135 | else |
| mbed_official | 324:406fd2029f23 | 1136 | { |
| mbed_official | 324:406fd2029f23 | 1137 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); |
| mbed_official | 324:406fd2029f23 | 1138 | } |
| mbed_official | 324:406fd2029f23 | 1139 | |
| mbed_official | 324:406fd2029f23 | 1140 | /* determine FRDIV based on reference clock frequency */ |
| mbed_official | 324:406fd2029f23 | 1141 | /* since the external frequency has already been checked only the maximum frequency for each FRDIV |
| mbed_official | 324:406fd2029f23 | 1142 | * value needs to be compared here. |
| mbed_official | 324:406fd2029f23 | 1143 | */ |
| mbed_official | 324:406fd2029f23 | 1144 | if (crystalVal <= kMcgConstant1250000) |
| mbed_official | 324:406fd2029f23 | 1145 | { |
| mbed_official | 324:406fd2029f23 | 1146 | frDivVal = kMcgConstant0; |
| mbed_official | 324:406fd2029f23 | 1147 | } |
| mbed_official | 324:406fd2029f23 | 1148 | else if (crystalVal <= kMcgConstant2500000) |
| mbed_official | 324:406fd2029f23 | 1149 | { |
| mbed_official | 324:406fd2029f23 | 1150 | frDivVal = kMcgConstant1; |
| mbed_official | 324:406fd2029f23 | 1151 | } |
| mbed_official | 324:406fd2029f23 | 1152 | else if (crystalVal <= kMcgConstant5000000) |
| mbed_official | 324:406fd2029f23 | 1153 | { |
| mbed_official | 324:406fd2029f23 | 1154 | frDivVal = kMcgConstant2; |
| mbed_official | 324:406fd2029f23 | 1155 | } |
| mbed_official | 324:406fd2029f23 | 1156 | else if (crystalVal <= kMcgConstant10000000) |
| mbed_official | 324:406fd2029f23 | 1157 | { |
| mbed_official | 324:406fd2029f23 | 1158 | frDivVal = kMcgConstant3; |
| mbed_official | 324:406fd2029f23 | 1159 | } |
| mbed_official | 324:406fd2029f23 | 1160 | else if (crystalVal <= kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 1161 | { |
| mbed_official | 324:406fd2029f23 | 1162 | frDivVal = kMcgConstant4; |
| mbed_official | 324:406fd2029f23 | 1163 | } |
| mbed_official | 324:406fd2029f23 | 1164 | else |
| mbed_official | 324:406fd2029f23 | 1165 | { |
| mbed_official | 324:406fd2029f23 | 1166 | frDivVal = kMcgConstant5; |
| mbed_official | 324:406fd2029f23 | 1167 | } |
| mbed_official | 324:406fd2029f23 | 1168 | |
| mbed_official | 324:406fd2029f23 | 1169 | /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ |
| mbed_official | 324:406fd2029f23 | 1170 | if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) |
| mbed_official | 324:406fd2029f23 | 1171 | { |
| mbed_official | 324:406fd2029f23 | 1172 | fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 1173 | } |
| mbed_official | 324:406fd2029f23 | 1174 | else |
| mbed_official | 324:406fd2029f23 | 1175 | { |
| mbed_official | 324:406fd2029f23 | 1176 | fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 1177 | } |
| mbed_official | 324:406fd2029f23 | 1178 | |
| mbed_official | 324:406fd2029f23 | 1179 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 1180 | /* FLL reference frequency calculated from ext ref freq and FRDIV */ |
| mbed_official | 324:406fd2029f23 | 1181 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); |
| mbed_official | 324:406fd2029f23 | 1182 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 1183 | { |
| mbed_official | 324:406fd2029f23 | 1184 | return mcgOut; /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 1185 | } |
| mbed_official | 324:406fd2029f23 | 1186 | |
| mbed_official | 324:406fd2029f23 | 1187 | /* |
| mbed_official | 324:406fd2029f23 | 1188 | * Select external oscilator and Reference Divider and clear IREFS to start ext osc |
| mbed_official | 324:406fd2029f23 | 1189 | * If IRCLK is required it must be enabled outside of this driver, existing state will |
| mbed_official | 324:406fd2029f23 | 1190 | * be maintained CLKS=0, FRDIV=frdivVal, IREFS=0 |
| mbed_official | 324:406fd2029f23 | 1191 | */ |
| mbed_official | 324:406fd2029f23 | 1192 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, frDivVal, kMcgInternalRefClkSrcExternal); |
| mbed_official | 324:406fd2029f23 | 1193 | |
| mbed_official | 324:406fd2029f23 | 1194 | /* if the external oscillator is used need to wait for OSCINIT to set */ |
| mbed_official | 324:406fd2029f23 | 1195 | if ((oscselVal == kMcgOscselOsc) && (erefsVal)) |
| mbed_official | 324:406fd2029f23 | 1196 | { |
| mbed_official | 324:406fd2029f23 | 1197 | for (i = 0 ; i < kMcgConstant20000000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1198 | { |
| mbed_official | 324:406fd2029f23 | 1199 | if (CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1200 | { |
| mbed_official | 324:406fd2029f23 | 1201 | break; /* jump out early if OSCINIT sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1202 | } |
| mbed_official | 324:406fd2029f23 | 1203 | } |
| mbed_official | 324:406fd2029f23 | 1204 | |
| mbed_official | 324:406fd2029f23 | 1205 | if (!CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1206 | { |
| mbed_official | 324:406fd2029f23 | 1207 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1208 | return kMcgErrOscSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1209 | } |
| mbed_official | 324:406fd2029f23 | 1210 | } |
| mbed_official | 324:406fd2029f23 | 1211 | |
| mbed_official | 324:406fd2029f23 | 1212 | /* Wait for clock status bits to show clock source is FLL */ |
| mbed_official | 324:406fd2029f23 | 1213 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1214 | { |
| mbed_official | 324:406fd2029f23 | 1215 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1216 | { |
| mbed_official | 324:406fd2029f23 | 1217 | break; // jump out early if CLKST shows FLL selected before loop finishes |
| mbed_official | 324:406fd2029f23 | 1218 | } |
| mbed_official | 324:406fd2029f23 | 1219 | } |
| mbed_official | 324:406fd2029f23 | 1220 | |
| mbed_official | 324:406fd2029f23 | 1221 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1222 | { |
| mbed_official | 324:406fd2029f23 | 1223 | return kMcgErrClkst0; // check FLL is really selected and return with error if not |
| mbed_official | 324:406fd2029f23 | 1224 | } |
| mbed_official | 324:406fd2029f23 | 1225 | |
| mbed_official | 324:406fd2029f23 | 1226 | /* |
| mbed_official | 324:406fd2029f23 | 1227 | * Now in FEE |
| mbed_official | 324:406fd2029f23 | 1228 | * It is recommended that the clock monitor is enabled when using an external clock as the |
| mbed_official | 324:406fd2029f23 | 1229 | * clock source/reference. |
| mbed_official | 324:406fd2029f23 | 1230 | * It is enabled here but can be removed if this is not required. |
| mbed_official | 324:406fd2029f23 | 1231 | */ |
| mbed_official | 324:406fd2029f23 | 1232 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); |
| mbed_official | 324:406fd2029f23 | 1233 | |
| mbed_official | 324:406fd2029f23 | 1234 | return mcgOut; /* MCGOUT frequency equals FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 1235 | } /* CLOCK_HAL_SetFbiToFeeMode */ |
| mbed_official | 324:406fd2029f23 | 1236 | |
| mbed_official | 324:406fd2029f23 | 1237 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1238 | * |
| mbed_official | 324:406fd2029f23 | 1239 | * Functon name : CLOCK_HAL_SetFbiToFbeMode |
| mbed_official | 324:406fd2029f23 | 1240 | * Description : Mode transition FBI to FBE mode |
| mbed_official | 324:406fd2029f23 | 1241 | * This function transitions the MCG from FBI mode to FBE mode. |
| mbed_official | 324:406fd2029f23 | 1242 | * |
| mbed_official | 324:406fd2029f23 | 1243 | * Parameters: oscselVal - oscillator selection value |
| mbed_official | 324:406fd2029f23 | 1244 | * 0 - OSC 0, 1 - RTC 32k, 2 - IRC 48M |
| mbed_official | 324:406fd2029f23 | 1245 | * crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 1246 | * oscselVal - 0 |
| mbed_official | 324:406fd2029f23 | 1247 | * erefsVal - 0: osc0 external clock frequency |
| mbed_official | 324:406fd2029f23 | 1248 | * erefsVal - 1: osc0 crystal clock frequency |
| mbed_official | 324:406fd2029f23 | 1249 | * oscselVal - 1: RTC 32Khz clock source frequency |
| mbed_official | 324:406fd2029f23 | 1250 | * oscselVal - 2: IRC 48Mhz clock source frequency |
| mbed_official | 324:406fd2029f23 | 1251 | * hgoVal - selects whether low power or high gain mode is selected |
| mbed_official | 324:406fd2029f23 | 1252 | * for the crystal oscillator. This value is only valid when |
| mbed_official | 324:406fd2029f23 | 1253 | * oscselVal is 0 and erefsVal is 1. |
| mbed_official | 324:406fd2029f23 | 1254 | * erefsVal - selects external clock (=0) or crystal osc (=1) |
| mbed_official | 324:406fd2029f23 | 1255 | * |
| mbed_official | 324:406fd2029f23 | 1256 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1257 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1258 | uint32_t CLOCK_HAL_SetFbiToFbeMode(uint32_t baseAddr, mcg_oscsel_select_t oscselVal, uint32_t crystalVal, mcg_high_gain_osc_select_t hgoVal, mcg_external_ref_clock_select_t erefsVal) |
| mbed_official | 324:406fd2029f23 | 1259 | { |
| mbed_official | 324:406fd2029f23 | 1260 | uint8_t frDivVal; |
| mbed_official | 324:406fd2029f23 | 1261 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 1262 | |
| mbed_official | 324:406fd2029f23 | 1263 | /* check if in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1264 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) |
| mbed_official | 324:406fd2029f23 | 1265 | { |
| mbed_official | 324:406fd2029f23 | 1266 | return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ |
| mbed_official | 324:406fd2029f23 | 1267 | } |
| mbed_official | 324:406fd2029f23 | 1268 | |
| mbed_official | 324:406fd2029f23 | 1269 | /* check external frequency is less than the maximum frequency */ |
| mbed_official | 324:406fd2029f23 | 1270 | if (crystalVal > kMcgConstant50000000) |
| mbed_official | 324:406fd2029f23 | 1271 | { |
| mbed_official | 324:406fd2029f23 | 1272 | return kMcgErrOscEtalRange; |
| mbed_official | 324:406fd2029f23 | 1273 | } |
| mbed_official | 324:406fd2029f23 | 1274 | |
| mbed_official | 324:406fd2029f23 | 1275 | /* check crystal frequency is within spec. if crystal osc is being used */ |
| mbed_official | 324:406fd2029f23 | 1276 | if (oscselVal == kMcgOscselOsc) |
| mbed_official | 324:406fd2029f23 | 1277 | { |
| mbed_official | 324:406fd2029f23 | 1278 | if (erefsVal) |
| mbed_official | 324:406fd2029f23 | 1279 | { |
| mbed_official | 324:406fd2029f23 | 1280 | /* return error if one of the available crystal options is not available */ |
| mbed_official | 324:406fd2029f23 | 1281 | if ((crystalVal < kMcgConstant30000) || |
| mbed_official | 324:406fd2029f23 | 1282 | ((crystalVal > kMcgConstant40000) && (crystalVal < kMcgConstant3000000)) || |
| mbed_official | 324:406fd2029f23 | 1283 | (crystalVal > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 1284 | { |
| mbed_official | 324:406fd2029f23 | 1285 | return kMcgErrOscXtalRange; /* - crystal frequency outside allowed range */ |
| mbed_official | 324:406fd2029f23 | 1286 | } |
| mbed_official | 324:406fd2029f23 | 1287 | |
| mbed_official | 324:406fd2029f23 | 1288 | /* config the hgo settings */ |
| mbed_official | 324:406fd2029f23 | 1289 | CLOCK_HAL_SetHighGainOsc0Mode(baseAddr, hgoVal); |
| mbed_official | 324:406fd2029f23 | 1290 | } |
| mbed_official | 324:406fd2029f23 | 1291 | |
| mbed_official | 324:406fd2029f23 | 1292 | /* config the erefs0 settings */ |
| mbed_official | 324:406fd2029f23 | 1293 | CLOCK_HAL_SetExternalRefSel0Mode(baseAddr, erefsVal); |
| mbed_official | 324:406fd2029f23 | 1294 | } |
| mbed_official | 324:406fd2029f23 | 1295 | |
| mbed_official | 324:406fd2029f23 | 1296 | /* |
| mbed_official | 324:406fd2029f23 | 1297 | * the RANGE value is determined by the external frequency. Since the RANGE parameter |
| mbed_official | 324:406fd2029f23 | 1298 | * affects the FRDIV divide value it still needs to be set correctly even if the |
| mbed_official | 324:406fd2029f23 | 1299 | * oscillator is not being used |
| mbed_official | 324:406fd2029f23 | 1300 | */ |
| mbed_official | 324:406fd2029f23 | 1301 | if (crystalVal <= kMcgConstant40000) |
| mbed_official | 324:406fd2029f23 | 1302 | { |
| mbed_official | 324:406fd2029f23 | 1303 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelLow); |
| mbed_official | 324:406fd2029f23 | 1304 | } |
| mbed_official | 324:406fd2029f23 | 1305 | else if (crystalVal <= kMcgConstant8000000) |
| mbed_official | 324:406fd2029f23 | 1306 | { |
| mbed_official | 324:406fd2029f23 | 1307 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelHigh); |
| mbed_official | 324:406fd2029f23 | 1308 | } |
| mbed_official | 324:406fd2029f23 | 1309 | else |
| mbed_official | 324:406fd2029f23 | 1310 | { |
| mbed_official | 324:406fd2029f23 | 1311 | CLOCK_HAL_SetRange0Mode(baseAddr, kMcgFreqRangeSelVeryHigh); |
| mbed_official | 324:406fd2029f23 | 1312 | } |
| mbed_official | 324:406fd2029f23 | 1313 | |
| mbed_official | 324:406fd2029f23 | 1314 | /* determine FRDIV based on reference clock frequency */ |
| mbed_official | 324:406fd2029f23 | 1315 | /* since the external frequency has already been checked only the maximum frequency for each FRDIV |
| mbed_official | 324:406fd2029f23 | 1316 | * value needs to be compared here. |
| mbed_official | 324:406fd2029f23 | 1317 | */ |
| mbed_official | 324:406fd2029f23 | 1318 | if (crystalVal <= kMcgConstant1250000) |
| mbed_official | 324:406fd2029f23 | 1319 | { |
| mbed_official | 324:406fd2029f23 | 1320 | frDivVal = kMcgConstant0; |
| mbed_official | 324:406fd2029f23 | 1321 | } |
| mbed_official | 324:406fd2029f23 | 1322 | else if (crystalVal <= kMcgConstant2500000) |
| mbed_official | 324:406fd2029f23 | 1323 | { |
| mbed_official | 324:406fd2029f23 | 1324 | frDivVal = kMcgConstant1; |
| mbed_official | 324:406fd2029f23 | 1325 | } |
| mbed_official | 324:406fd2029f23 | 1326 | else if (crystalVal <= kMcgConstant5000000) |
| mbed_official | 324:406fd2029f23 | 1327 | { |
| mbed_official | 324:406fd2029f23 | 1328 | frDivVal = kMcgConstant2; |
| mbed_official | 324:406fd2029f23 | 1329 | } |
| mbed_official | 324:406fd2029f23 | 1330 | else if (crystalVal <= kMcgConstant10000000) |
| mbed_official | 324:406fd2029f23 | 1331 | { |
| mbed_official | 324:406fd2029f23 | 1332 | frDivVal = kMcgConstant3; |
| mbed_official | 324:406fd2029f23 | 1333 | } |
| mbed_official | 324:406fd2029f23 | 1334 | else if (crystalVal <= kMcgConstant20000000) |
| mbed_official | 324:406fd2029f23 | 1335 | { |
| mbed_official | 324:406fd2029f23 | 1336 | frDivVal = kMcgConstant4; |
| mbed_official | 324:406fd2029f23 | 1337 | } |
| mbed_official | 324:406fd2029f23 | 1338 | else |
| mbed_official | 324:406fd2029f23 | 1339 | { |
| mbed_official | 324:406fd2029f23 | 1340 | frDivVal = kMcgConstant5; |
| mbed_official | 324:406fd2029f23 | 1341 | } |
| mbed_official | 324:406fd2029f23 | 1342 | |
| mbed_official | 324:406fd2029f23 | 1343 | /* Set LP bit to enable the FLL */ |
| mbed_official | 324:406fd2029f23 | 1344 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 1345 | |
| mbed_official | 324:406fd2029f23 | 1346 | /* |
| mbed_official | 324:406fd2029f23 | 1347 | * Select external oscilator and Reference Divider and clear IREFS to start ext osc |
| mbed_official | 324:406fd2029f23 | 1348 | * If IRCLK is required it must be enabled outside of this driver, existing state will be maintained |
| mbed_official | 324:406fd2029f23 | 1349 | * CLKS=2, FRDIV=frdiv_val, IREFS=0 |
| mbed_official | 324:406fd2029f23 | 1350 | */ |
| mbed_official | 324:406fd2029f23 | 1351 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelExternal, frDivVal, kMcgInternalRefClkSrcExternal); |
| mbed_official | 324:406fd2029f23 | 1352 | |
| mbed_official | 324:406fd2029f23 | 1353 | /* if the external oscillator is used need to wait for OSCINIT to set */ |
| mbed_official | 324:406fd2029f23 | 1354 | if ((oscselVal == kMcgOscselOsc) && (erefsVal)) |
| mbed_official | 324:406fd2029f23 | 1355 | { |
| mbed_official | 324:406fd2029f23 | 1356 | for (i = 0 ; i < kMcgConstant10000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1357 | { |
| mbed_official | 324:406fd2029f23 | 1358 | if (CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1359 | { |
| mbed_official | 324:406fd2029f23 | 1360 | break; /* jump out early if OSCINIT sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1361 | } |
| mbed_official | 324:406fd2029f23 | 1362 | } |
| mbed_official | 324:406fd2029f23 | 1363 | |
| mbed_official | 324:406fd2029f23 | 1364 | if (!CLOCK_HAL_GetOscInit0(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1365 | { |
| mbed_official | 324:406fd2029f23 | 1366 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1367 | return kMcgErrOscSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1368 | } |
| mbed_official | 324:406fd2029f23 | 1369 | } |
| mbed_official | 324:406fd2029f23 | 1370 | |
| mbed_official | 324:406fd2029f23 | 1371 | /* wait for Reference clock Status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 1372 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1373 | { |
| mbed_official | 324:406fd2029f23 | 1374 | if (!CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1375 | { |
| mbed_official | 324:406fd2029f23 | 1376 | break; /* jump out early if IREFST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1377 | } |
| mbed_official | 324:406fd2029f23 | 1378 | } |
| mbed_official | 324:406fd2029f23 | 1379 | |
| mbed_official | 324:406fd2029f23 | 1380 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr)) |
| mbed_official | 324:406fd2029f23 | 1381 | { |
| mbed_official | 324:406fd2029f23 | 1382 | /* check bit is really clear and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1383 | return kMcgErrIrefstClearTimeOut; |
| mbed_official | 324:406fd2029f23 | 1384 | } |
| mbed_official | 324:406fd2029f23 | 1385 | |
| mbed_official | 324:406fd2029f23 | 1386 | /* Wait for clock status bits to show clock source is ext ref clk */ |
| mbed_official | 324:406fd2029f23 | 1387 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1388 | { |
| mbed_official | 324:406fd2029f23 | 1389 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 1390 | { |
| mbed_official | 324:406fd2029f23 | 1391 | break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1392 | } |
| mbed_official | 324:406fd2029f23 | 1393 | } |
| mbed_official | 324:406fd2029f23 | 1394 | |
| mbed_official | 324:406fd2029f23 | 1395 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 1396 | { |
| mbed_official | 324:406fd2029f23 | 1397 | return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 1398 | } |
| mbed_official | 324:406fd2029f23 | 1399 | |
| mbed_official | 324:406fd2029f23 | 1400 | /* |
| mbed_official | 324:406fd2029f23 | 1401 | * Now in FBE |
| mbed_official | 324:406fd2029f23 | 1402 | * It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference. |
| mbed_official | 324:406fd2029f23 | 1403 | * It is enabled here but can be removed if this is not required. |
| mbed_official | 324:406fd2029f23 | 1404 | */ |
| mbed_official | 324:406fd2029f23 | 1405 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, true); |
| mbed_official | 324:406fd2029f23 | 1406 | |
| mbed_official | 324:406fd2029f23 | 1407 | return crystalVal; /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 1408 | } /* CLOCK_HAL_SetFbiToFbeMode */ |
| mbed_official | 324:406fd2029f23 | 1409 | |
| mbed_official | 324:406fd2029f23 | 1410 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1411 | * |
| mbed_official | 324:406fd2029f23 | 1412 | * Functon name : CLOCK_HAL_SetFbiToBlpiMode |
| mbed_official | 324:406fd2029f23 | 1413 | * Description : Mode transition FBI to BLPI mode |
| mbed_official | 324:406fd2029f23 | 1414 | * This function transitions the MCG from FBI mode to BLPI mode.This is |
| mbed_official | 324:406fd2029f23 | 1415 | * achieved by setting the MCG_C2[LP] bit. |
| mbed_official | 324:406fd2029f23 | 1416 | * |
| mbed_official | 324:406fd2029f23 | 1417 | * Parameters: ircFreq - internal reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 1418 | * ircSelect - slow or fast clock selection |
| mbed_official | 324:406fd2029f23 | 1419 | * 0: slow, 1: fast |
| mbed_official | 324:406fd2029f23 | 1420 | * |
| mbed_official | 324:406fd2029f23 | 1421 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1422 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1423 | uint32_t CLOCK_HAL_SetFbiToBlpiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) |
| mbed_official | 324:406fd2029f23 | 1424 | { |
| mbed_official | 324:406fd2029f23 | 1425 | uint8_t fcrDivVal; |
| mbed_official | 324:406fd2029f23 | 1426 | |
| mbed_official | 324:406fd2029f23 | 1427 | /* check if in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1428 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBI) |
| mbed_official | 324:406fd2029f23 | 1429 | { |
| mbed_official | 324:406fd2029f23 | 1430 | return kMcgErrNotInFbiMode; /* MCG not in correct mode return fail code */ |
| mbed_official | 324:406fd2029f23 | 1431 | } |
| mbed_official | 324:406fd2029f23 | 1432 | |
| mbed_official | 324:406fd2029f23 | 1433 | /* Set LP bit to disable the FLL and enter BLPI */ |
| mbed_official | 324:406fd2029f23 | 1434 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); |
| mbed_official | 324:406fd2029f23 | 1435 | |
| mbed_official | 324:406fd2029f23 | 1436 | /* Now in BLPI */ |
| mbed_official | 324:406fd2029f23 | 1437 | if (ircSelect == kMcgInternalRefClkSelFast) |
| mbed_official | 324:406fd2029f23 | 1438 | { |
| mbed_official | 324:406fd2029f23 | 1439 | fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 1440 | return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ |
| mbed_official | 324:406fd2029f23 | 1441 | } |
| mbed_official | 324:406fd2029f23 | 1442 | else |
| mbed_official | 324:406fd2029f23 | 1443 | { |
| mbed_official | 324:406fd2029f23 | 1444 | return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ |
| mbed_official | 324:406fd2029f23 | 1445 | } |
| mbed_official | 324:406fd2029f23 | 1446 | } /* CLOCK_HAL_SetFbiToBlpiMode */ |
| mbed_official | 324:406fd2029f23 | 1447 | |
| mbed_official | 324:406fd2029f23 | 1448 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1449 | * |
| mbed_official | 324:406fd2029f23 | 1450 | * Functon name : CLOCK_HAL_SetBlpiToFbiMode |
| mbed_official | 324:406fd2029f23 | 1451 | * Description : Mode transition BLPI to FBI mode |
| mbed_official | 324:406fd2029f23 | 1452 | * This function transitions the MCG from BLPI mode to FBI mode.This is |
| mbed_official | 324:406fd2029f23 | 1453 | * achieved by clearing the MCG_C2[LP] bit. |
| mbed_official | 324:406fd2029f23 | 1454 | * |
| mbed_official | 324:406fd2029f23 | 1455 | * Parameters: ircFreq - internal reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 1456 | * ircSelect - slow or fast clock selection |
| mbed_official | 324:406fd2029f23 | 1457 | * 0: slow, 1: fast |
| mbed_official | 324:406fd2029f23 | 1458 | * |
| mbed_official | 324:406fd2029f23 | 1459 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1460 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1461 | uint32_t CLOCK_HAL_SetBlpiToFbiMode(uint32_t baseAddr, uint32_t ircFreq, uint8_t ircSelect) |
| mbed_official | 324:406fd2029f23 | 1462 | { |
| mbed_official | 324:406fd2029f23 | 1463 | uint8_t fcrDivVal; |
| mbed_official | 324:406fd2029f23 | 1464 | |
| mbed_official | 324:406fd2029f23 | 1465 | /* check if in BLPI mode */ |
| mbed_official | 324:406fd2029f23 | 1466 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPI) |
| mbed_official | 324:406fd2029f23 | 1467 | { |
| mbed_official | 324:406fd2029f23 | 1468 | return kMcgErrNotInBlpiMode; /* MCG not in correct mode return fail code */ |
| mbed_official | 324:406fd2029f23 | 1469 | } |
| mbed_official | 324:406fd2029f23 | 1470 | |
| mbed_official | 324:406fd2029f23 | 1471 | /* Clear LP bit to enable the FLL and enter FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1472 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 1473 | |
| mbed_official | 324:406fd2029f23 | 1474 | /* Now in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1475 | if (ircSelect) |
| mbed_official | 324:406fd2029f23 | 1476 | { |
| mbed_official | 324:406fd2029f23 | 1477 | fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 1478 | return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ |
| mbed_official | 324:406fd2029f23 | 1479 | } |
| mbed_official | 324:406fd2029f23 | 1480 | else |
| mbed_official | 324:406fd2029f23 | 1481 | { |
| mbed_official | 324:406fd2029f23 | 1482 | return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ |
| mbed_official | 324:406fd2029f23 | 1483 | } |
| mbed_official | 324:406fd2029f23 | 1484 | } /* CLOCK_HAL_SetBlpiToFbiMode */ |
| mbed_official | 324:406fd2029f23 | 1485 | |
| mbed_official | 324:406fd2029f23 | 1486 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1487 | * |
| mbed_official | 324:406fd2029f23 | 1488 | * Functon name : CLOCK_HAL_SetFbeToFeeMode |
| mbed_official | 324:406fd2029f23 | 1489 | * Description : Mode transition FBE to FEE mode |
| mbed_official | 324:406fd2029f23 | 1490 | * This function transitions the MCG from FBE mode to FEE mode. |
| mbed_official | 324:406fd2029f23 | 1491 | * |
| mbed_official | 324:406fd2029f23 | 1492 | * Parameters: crystalVal - external reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 1493 | * |
| mbed_official | 324:406fd2029f23 | 1494 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1495 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1496 | uint32_t CLOCK_HAL_SetFbeToFeeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 1497 | { |
| mbed_official | 324:406fd2029f23 | 1498 | uint16_t i, fllRefFreq, frDivVal; |
| mbed_official | 324:406fd2029f23 | 1499 | uint32_t mcgOut; |
| mbed_official | 324:406fd2029f23 | 1500 | |
| mbed_official | 324:406fd2029f23 | 1501 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1502 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) |
| mbed_official | 324:406fd2029f23 | 1503 | { |
| mbed_official | 324:406fd2029f23 | 1504 | return kMcgErrNotInFbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 1505 | } |
| mbed_official | 324:406fd2029f23 | 1506 | |
| mbed_official | 324:406fd2029f23 | 1507 | /* get curretn frdiv value */ |
| mbed_official | 324:406fd2029f23 | 1508 | frDivVal = CLOCK_HAL_GetFllExternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 1509 | |
| mbed_official | 324:406fd2029f23 | 1510 | /* The FLL ref clk divide value depends on FRDIV and the RANGE value */ |
| mbed_official | 324:406fd2029f23 | 1511 | if (CLOCK_HAL_GetRange0Mode(baseAddr) > kMcgFreqRangeSelLow) |
| mbed_official | 324:406fd2029f23 | 1512 | { |
| mbed_official | 324:406fd2029f23 | 1513 | fllRefFreq = ((crystalVal) / (kMcgConstant32 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 1514 | } |
| mbed_official | 324:406fd2029f23 | 1515 | else |
| mbed_official | 324:406fd2029f23 | 1516 | { |
| mbed_official | 324:406fd2029f23 | 1517 | fllRefFreq = ((crystalVal) / (kMcgConstant1 << frDivVal)); |
| mbed_official | 324:406fd2029f23 | 1518 | } |
| mbed_official | 324:406fd2029f23 | 1519 | |
| mbed_official | 324:406fd2029f23 | 1520 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 1521 | /* FLL reference frequency calculated from ext ref freq and FRDIV */ |
| mbed_official | 324:406fd2029f23 | 1522 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, fllRefFreq); |
| mbed_official | 324:406fd2029f23 | 1523 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 1524 | { |
| mbed_official | 324:406fd2029f23 | 1525 | return mcgOut; /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 1526 | } |
| mbed_official | 324:406fd2029f23 | 1527 | |
| mbed_official | 324:406fd2029f23 | 1528 | /* Clear CLKS field to switch CLKS mux to select FLL output */ |
| mbed_official | 324:406fd2029f23 | 1529 | CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut); |
| mbed_official | 324:406fd2029f23 | 1530 | |
| mbed_official | 324:406fd2029f23 | 1531 | /* Wait for clock status bits to show clock source is FLL */ |
| mbed_official | 324:406fd2029f23 | 1532 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1533 | { |
| mbed_official | 324:406fd2029f23 | 1534 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1535 | { |
| mbed_official | 324:406fd2029f23 | 1536 | break; // jump out early if CLKST shows FLL selected before loop finishes |
| mbed_official | 324:406fd2029f23 | 1537 | } |
| mbed_official | 324:406fd2029f23 | 1538 | } |
| mbed_official | 324:406fd2029f23 | 1539 | |
| mbed_official | 324:406fd2029f23 | 1540 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1541 | { |
| mbed_official | 324:406fd2029f23 | 1542 | return kMcgErrClkst0; // check FLL is really selected and return with error if not |
| mbed_official | 324:406fd2029f23 | 1543 | } |
| mbed_official | 324:406fd2029f23 | 1544 | |
| mbed_official | 324:406fd2029f23 | 1545 | /* Now in FEE mode */ |
| mbed_official | 324:406fd2029f23 | 1546 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 1547 | } /* CLOCK_HAL_SetFbeToFeeMode */ |
| mbed_official | 324:406fd2029f23 | 1548 | |
| mbed_official | 324:406fd2029f23 | 1549 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1550 | * |
| mbed_official | 324:406fd2029f23 | 1551 | * Functon name : CLOCK_HAL_SetFbeToFeiMode |
| mbed_official | 324:406fd2029f23 | 1552 | * Description : Mode transition FBE to FEI mode |
| mbed_official | 324:406fd2029f23 | 1553 | * This function transitions the MCG from FBE mode to FEI mode. |
| mbed_official | 324:406fd2029f23 | 1554 | * |
| mbed_official | 324:406fd2029f23 | 1555 | * Parameters: ircFreq - internal reference clock frequency value (slow) |
| mbed_official | 324:406fd2029f23 | 1556 | * |
| mbed_official | 324:406fd2029f23 | 1557 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1558 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1559 | uint32_t CLOCK_HAL_SetFbeToFeiMode(uint32_t baseAddr, uint32_t ircFreq) |
| mbed_official | 324:406fd2029f23 | 1560 | { |
| mbed_official | 324:406fd2029f23 | 1561 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 1562 | uint32_t mcgOut; |
| mbed_official | 324:406fd2029f23 | 1563 | |
| mbed_official | 324:406fd2029f23 | 1564 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1565 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) |
| mbed_official | 324:406fd2029f23 | 1566 | { |
| mbed_official | 324:406fd2029f23 | 1567 | return kMcgErrNotInFbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 1568 | } |
| mbed_official | 324:406fd2029f23 | 1569 | |
| mbed_official | 324:406fd2029f23 | 1570 | /* Check IRC frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 1571 | if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) |
| mbed_official | 324:406fd2029f23 | 1572 | { |
| mbed_official | 324:406fd2029f23 | 1573 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 1574 | } |
| mbed_official | 324:406fd2029f23 | 1575 | |
| mbed_official | 324:406fd2029f23 | 1576 | /* Check resulting FLL frequency */ |
| mbed_official | 324:406fd2029f23 | 1577 | mcgOut = CLOCK_HAL_GetFllFrequency(baseAddr, ircFreq); |
| mbed_official | 324:406fd2029f23 | 1578 | if (mcgOut < kMcgErrMax) |
| mbed_official | 324:406fd2029f23 | 1579 | { |
| mbed_official | 324:406fd2029f23 | 1580 | /* If error code returned, return the code to calling function */ |
| mbed_official | 324:406fd2029f23 | 1581 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 1582 | } |
| mbed_official | 324:406fd2029f23 | 1583 | |
| mbed_official | 324:406fd2029f23 | 1584 | /* |
| mbed_official | 324:406fd2029f23 | 1585 | * Ensure clock monitor is disabled before switching to FEI otherwise |
| mbed_official | 324:406fd2029f23 | 1586 | * a loss of clock will trigger. This assumes OSC0 is used as the external clock source. |
| mbed_official | 324:406fd2029f23 | 1587 | */ |
| mbed_official | 324:406fd2029f23 | 1588 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); |
| mbed_official | 324:406fd2029f23 | 1589 | |
| mbed_official | 324:406fd2029f23 | 1590 | // Move to FEI by setting CLKS to 0 and enabling the slow IRC as the FLL reference clock |
| mbed_official | 324:406fd2029f23 | 1591 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelOut, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); |
| mbed_official | 324:406fd2029f23 | 1592 | |
| mbed_official | 324:406fd2029f23 | 1593 | /* wait for Reference clock to switch to internal reference */ |
| mbed_official | 324:406fd2029f23 | 1594 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1595 | { |
| mbed_official | 324:406fd2029f23 | 1596 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 1597 | { |
| mbed_official | 324:406fd2029f23 | 1598 | break; /* jump out early if IREFST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1599 | } |
| mbed_official | 324:406fd2029f23 | 1600 | } |
| mbed_official | 324:406fd2029f23 | 1601 | |
| mbed_official | 324:406fd2029f23 | 1602 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 1603 | { |
| mbed_official | 324:406fd2029f23 | 1604 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1605 | return kMcgErrIrefstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1606 | } |
| mbed_official | 324:406fd2029f23 | 1607 | |
| mbed_official | 324:406fd2029f23 | 1608 | /* Wait for clock status bits to show clock source is FLL output */ |
| mbed_official | 324:406fd2029f23 | 1609 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1610 | { |
| mbed_official | 324:406fd2029f23 | 1611 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1612 | { |
| mbed_official | 324:406fd2029f23 | 1613 | /* jump out early if CLKST shows FLL output slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1614 | break; |
| mbed_official | 324:406fd2029f23 | 1615 | } |
| mbed_official | 324:406fd2029f23 | 1616 | } |
| mbed_official | 324:406fd2029f23 | 1617 | |
| mbed_official | 324:406fd2029f23 | 1618 | /* check FLL output is really selected */ |
| mbed_official | 324:406fd2029f23 | 1619 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatFll) |
| mbed_official | 324:406fd2029f23 | 1620 | { |
| mbed_official | 324:406fd2029f23 | 1621 | /* return with error if not */ |
| mbed_official | 324:406fd2029f23 | 1622 | return kMcgErrClkst0; |
| mbed_official | 324:406fd2029f23 | 1623 | } |
| mbed_official | 324:406fd2029f23 | 1624 | |
| mbed_official | 324:406fd2029f23 | 1625 | /* Now in FEI mode */ |
| mbed_official | 324:406fd2029f23 | 1626 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 1627 | } /* CLOCK_HAL_SetFbeToFeiMode */ |
| mbed_official | 324:406fd2029f23 | 1628 | |
| mbed_official | 324:406fd2029f23 | 1629 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1630 | * |
| mbed_official | 324:406fd2029f23 | 1631 | * Functon name : CLOCK_HAL_SetFbeToFbiMode |
| mbed_official | 324:406fd2029f23 | 1632 | * Description : Mode transition FBE to FBI mode |
| mbed_official | 324:406fd2029f23 | 1633 | * This function transitions the MCG from FBE mode to FBI mode. |
| mbed_official | 324:406fd2029f23 | 1634 | * |
| mbed_official | 324:406fd2029f23 | 1635 | * Parameters: ircFreq - internal reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 1636 | * ircSelect - slow or fast clock selection |
| mbed_official | 324:406fd2029f23 | 1637 | * 0: slow, 1: fast |
| mbed_official | 324:406fd2029f23 | 1638 | * |
| mbed_official | 324:406fd2029f23 | 1639 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1640 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1641 | uint32_t CLOCK_HAL_SetFbeToFbiMode(uint32_t baseAddr, uint32_t ircFreq, mcg_internal_ref_clock_select_t ircSelect) |
| mbed_official | 324:406fd2029f23 | 1642 | { |
| mbed_official | 324:406fd2029f23 | 1643 | uint8_t fcrDivVal; |
| mbed_official | 324:406fd2029f23 | 1644 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 1645 | |
| mbed_official | 324:406fd2029f23 | 1646 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1647 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) |
| mbed_official | 324:406fd2029f23 | 1648 | { |
| mbed_official | 324:406fd2029f23 | 1649 | return kMcgErrNotInFbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 1650 | } |
| mbed_official | 324:406fd2029f23 | 1651 | |
| mbed_official | 324:406fd2029f23 | 1652 | /* Check that the irc frequency matches the selected IRC */ |
| mbed_official | 324:406fd2029f23 | 1653 | if (!(ircSelect)) |
| mbed_official | 324:406fd2029f23 | 1654 | { |
| mbed_official | 324:406fd2029f23 | 1655 | if ((ircFreq < kMcgConstant31250) || (ircFreq > kMcgConstant39063)) |
| mbed_official | 324:406fd2029f23 | 1656 | { |
| mbed_official | 324:406fd2029f23 | 1657 | return kMcgErrIrcSlowRange; |
| mbed_official | 324:406fd2029f23 | 1658 | } |
| mbed_official | 324:406fd2029f23 | 1659 | } |
| mbed_official | 324:406fd2029f23 | 1660 | else |
| mbed_official | 324:406fd2029f23 | 1661 | { |
| mbed_official | 324:406fd2029f23 | 1662 | if ((ircFreq < kMcgConstant3000000) || (ircFreq > kMcgConstant5000000)) |
| mbed_official | 324:406fd2029f23 | 1663 | { |
| mbed_official | 324:406fd2029f23 | 1664 | return kMcgErrIrcFastRange; |
| mbed_official | 324:406fd2029f23 | 1665 | } /* Fast IRC freq */ |
| mbed_official | 324:406fd2029f23 | 1666 | } |
| mbed_official | 324:406fd2029f23 | 1667 | |
| mbed_official | 324:406fd2029f23 | 1668 | /* Select the required IRC */ |
| mbed_official | 324:406fd2029f23 | 1669 | CLOCK_HAL_SetInternalRefClkSelMode(baseAddr, ircSelect); |
| mbed_official | 324:406fd2029f23 | 1670 | |
| mbed_official | 324:406fd2029f23 | 1671 | /* Make sure the clock monitor is disabled before switching modes otherwise it will trigger */ |
| mbed_official | 324:406fd2029f23 | 1672 | CLOCK_HAL_SetClkMonitor0Cmd(baseAddr, false); |
| mbed_official | 324:406fd2029f23 | 1673 | |
| mbed_official | 324:406fd2029f23 | 1674 | /* Select the IRC as the CLKS mux selection */ |
| mbed_official | 324:406fd2029f23 | 1675 | CLOCK_HAL_SetClksFrdivInternalRefSelect(baseAddr, kMcgClkSelInternal, CLOCK_HAL_GetFllExternalRefDivider(baseAddr), kMcgInternalRefClkSrcSlow); |
| mbed_official | 324:406fd2029f23 | 1676 | |
| mbed_official | 324:406fd2029f23 | 1677 | /* wait until internal reference switches to requested irc. */ |
| mbed_official | 324:406fd2029f23 | 1678 | if (ircSelect == kMcgInternalRefClkSelSlow) |
| mbed_official | 324:406fd2029f23 | 1679 | { |
| mbed_official | 324:406fd2029f23 | 1680 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1681 | { |
| mbed_official | 324:406fd2029f23 | 1682 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatSlow) |
| mbed_official | 324:406fd2029f23 | 1683 | { |
| mbed_official | 324:406fd2029f23 | 1684 | break; /* jump out early if IRCST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1685 | } |
| mbed_official | 324:406fd2029f23 | 1686 | } |
| mbed_official | 324:406fd2029f23 | 1687 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatSlow) |
| mbed_official | 324:406fd2029f23 | 1688 | { |
| mbed_official | 324:406fd2029f23 | 1689 | /* check bit is really clear and return with error if set */ |
| mbed_official | 324:406fd2029f23 | 1690 | return kMcgErrIrcstClearTimeout; |
| mbed_official | 324:406fd2029f23 | 1691 | } |
| mbed_official | 324:406fd2029f23 | 1692 | } |
| mbed_official | 324:406fd2029f23 | 1693 | else |
| mbed_official | 324:406fd2029f23 | 1694 | { |
| mbed_official | 324:406fd2029f23 | 1695 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1696 | { |
| mbed_official | 324:406fd2029f23 | 1697 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) == kMcgInternalRefClkStatFast) |
| mbed_official | 324:406fd2029f23 | 1698 | { |
| mbed_official | 324:406fd2029f23 | 1699 | break; /* jump out early if IRCST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1700 | } |
| mbed_official | 324:406fd2029f23 | 1701 | } |
| mbed_official | 324:406fd2029f23 | 1702 | if (CLOCK_HAL_GetInternalRefClkStatMode(baseAddr) != kMcgInternalRefClkStatFast) |
| mbed_official | 324:406fd2029f23 | 1703 | { |
| mbed_official | 324:406fd2029f23 | 1704 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1705 | return kMcgErrIrefstSetTimeout1; |
| mbed_official | 324:406fd2029f23 | 1706 | } |
| mbed_official | 324:406fd2029f23 | 1707 | } |
| mbed_official | 324:406fd2029f23 | 1708 | |
| mbed_official | 324:406fd2029f23 | 1709 | /* Wait for clock status bits to update */ |
| mbed_official | 324:406fd2029f23 | 1710 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1711 | { |
| mbed_official | 324:406fd2029f23 | 1712 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 1713 | { |
| mbed_official | 324:406fd2029f23 | 1714 | break; /* jump out early if CLKST shows IRC slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1715 | } |
| mbed_official | 324:406fd2029f23 | 1716 | } |
| mbed_official | 324:406fd2029f23 | 1717 | |
| mbed_official | 324:406fd2029f23 | 1718 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatInternalRef) |
| mbed_official | 324:406fd2029f23 | 1719 | { |
| mbed_official | 324:406fd2029f23 | 1720 | return kMcgErrClkst1; /* check IRC is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 1721 | } |
| mbed_official | 324:406fd2029f23 | 1722 | |
| mbed_official | 324:406fd2029f23 | 1723 | /* wait for Reference clock Status bit to set */ |
| mbed_official | 324:406fd2029f23 | 1724 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1725 | { |
| mbed_official | 324:406fd2029f23 | 1726 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) == kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 1727 | { |
| mbed_official | 324:406fd2029f23 | 1728 | break; /* jump out early if IREFST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1729 | } |
| mbed_official | 324:406fd2029f23 | 1730 | } |
| mbed_official | 324:406fd2029f23 | 1731 | |
| mbed_official | 324:406fd2029f23 | 1732 | if (CLOCK_HAL_GetInternalRefStatMode(baseAddr) != kMcgInternalRefStatInternal) |
| mbed_official | 324:406fd2029f23 | 1733 | { |
| mbed_official | 324:406fd2029f23 | 1734 | /* check bit is really set and return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1735 | return kMcgErrIrefstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1736 | } |
| mbed_official | 324:406fd2029f23 | 1737 | |
| mbed_official | 324:406fd2029f23 | 1738 | /* Now in FBI mode */ |
| mbed_official | 324:406fd2029f23 | 1739 | if (ircSelect == kMcgInternalRefClkSelFast) |
| mbed_official | 324:406fd2029f23 | 1740 | { |
| mbed_official | 324:406fd2029f23 | 1741 | fcrDivVal = CLOCK_HAL_GetFastClkInternalRefDivider(baseAddr); |
| mbed_official | 324:406fd2029f23 | 1742 | |
| mbed_official | 324:406fd2029f23 | 1743 | return (ircFreq / fcrDivVal); /* MCGOUT frequency equals fast IRC frequency divided by 2 */ |
| mbed_official | 324:406fd2029f23 | 1744 | } |
| mbed_official | 324:406fd2029f23 | 1745 | else |
| mbed_official | 324:406fd2029f23 | 1746 | { |
| mbed_official | 324:406fd2029f23 | 1747 | return ircFreq; /* MCGOUT frequency equals slow IRC frequency */ |
| mbed_official | 324:406fd2029f23 | 1748 | } |
| mbed_official | 324:406fd2029f23 | 1749 | } /* CLOCK_HAL_SetFbeToFbiMode */ |
| mbed_official | 324:406fd2029f23 | 1750 | |
| mbed_official | 324:406fd2029f23 | 1751 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 1752 | |
| mbed_official | 324:406fd2029f23 | 1753 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1754 | * |
| mbed_official | 324:406fd2029f23 | 1755 | * Functon name : CLOCK_HAL_SetFbeToPbeMode |
| mbed_official | 324:406fd2029f23 | 1756 | * Description : Mode transition FBE to PBE mode |
| mbed_official | 324:406fd2029f23 | 1757 | * This function transitions the MCG from FBE mode to PBE mode. |
| mbed_official | 324:406fd2029f23 | 1758 | * The function requires the desired OSC and PLL be passed in to it for compatibility |
| mbed_official | 324:406fd2029f23 | 1759 | * with the future support of OSC/PLL selection |
| mbed_official | 324:406fd2029f23 | 1760 | * (This function presently only supports OSC0 as PLL source) |
| mbed_official | 324:406fd2029f23 | 1761 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 1762 | * pllcsSelect - 0 to select PLL0, non-zero to select PLL1. |
| mbed_official | 324:406fd2029f23 | 1763 | * prdivVal - value to divide the external clock source by to create |
| mbed_official | 324:406fd2029f23 | 1764 | * the desired PLL reference clock frequency |
| mbed_official | 324:406fd2029f23 | 1765 | * vdivVal - value to multiply the PLL reference clock frequency by |
| mbed_official | 324:406fd2029f23 | 1766 | * |
| mbed_official | 324:406fd2029f23 | 1767 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1768 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1769 | uint32_t CLOCK_HAL_SetFbeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect, |
| mbed_official | 324:406fd2029f23 | 1770 | uint8_t prdivVal, uint8_t vdivVal) |
| mbed_official | 324:406fd2029f23 | 1771 | { |
| mbed_official | 324:406fd2029f23 | 1772 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 1773 | uint32_t pllFreq; |
| mbed_official | 324:406fd2029f23 | 1774 | |
| mbed_official | 324:406fd2029f23 | 1775 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1776 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) |
| mbed_official | 324:406fd2029f23 | 1777 | { |
| mbed_official | 324:406fd2029f23 | 1778 | return kMcgErrNotInFbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 1779 | } |
| mbed_official | 324:406fd2029f23 | 1780 | |
| mbed_official | 324:406fd2029f23 | 1781 | /* |
| mbed_official | 324:406fd2029f23 | 1782 | * As the external frequency (osc0) has already been checked when FBE mode was enterred |
| mbed_official | 324:406fd2029f23 | 1783 | * it is not checked here. |
| mbed_official | 324:406fd2029f23 | 1784 | */ |
| mbed_official | 324:406fd2029f23 | 1785 | |
| mbed_official | 324:406fd2029f23 | 1786 | /* Check PLL divider settings are within spec.*/ |
| mbed_official | 324:406fd2029f23 | 1787 | if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX)) |
| mbed_official | 324:406fd2029f23 | 1788 | { |
| mbed_official | 324:406fd2029f23 | 1789 | return kMcgErrPllPrdidRange; |
| mbed_official | 324:406fd2029f23 | 1790 | } |
| mbed_official | 324:406fd2029f23 | 1791 | |
| mbed_official | 324:406fd2029f23 | 1792 | if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31))) |
| mbed_official | 324:406fd2029f23 | 1793 | { |
| mbed_official | 324:406fd2029f23 | 1794 | return kMcgErrPllVdivRange; |
| mbed_official | 324:406fd2029f23 | 1795 | } |
| mbed_official | 324:406fd2029f23 | 1796 | |
| mbed_official | 324:406fd2029f23 | 1797 | /* Check PLL reference clock frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 1798 | if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 1799 | { |
| mbed_official | 324:406fd2029f23 | 1800 | return kMcgErrPllRefClkRange; |
| mbed_official | 324:406fd2029f23 | 1801 | } |
| mbed_official | 324:406fd2029f23 | 1802 | |
| mbed_official | 324:406fd2029f23 | 1803 | /* Check PLL output frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 1804 | pllFreq = (crystalVal / prdivVal) * vdivVal; |
| mbed_official | 324:406fd2029f23 | 1805 | if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000)) |
| mbed_official | 324:406fd2029f23 | 1806 | { |
| mbed_official | 324:406fd2029f23 | 1807 | return kMcgErrPllOutClkRange; |
| mbed_official | 324:406fd2029f23 | 1808 | } |
| mbed_official | 324:406fd2029f23 | 1809 | |
| mbed_official | 324:406fd2029f23 | 1810 | #if FSL_FEATURE_MCG_HAS_PLL1 |
| mbed_official | 324:406fd2029f23 | 1811 | /* set pllcsSelect */ |
| mbed_official | 324:406fd2029f23 | 1812 | CLOCK_HAL_SetPllcs(pllcsSelect); |
| mbed_official | 324:406fd2029f23 | 1813 | |
| mbed_official | 324:406fd2029f23 | 1814 | if (pllcsSelect == kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 1815 | #endif |
| mbed_official | 324:406fd2029f23 | 1816 | { |
| mbed_official | 324:406fd2029f23 | 1817 | /* |
| mbed_official | 324:406fd2029f23 | 1818 | * Configure MCG_C5 |
| mbed_official | 324:406fd2029f23 | 1819 | * If the PLL is to run in STOP mode then the PLLSTEN bit needs |
| mbed_official | 324:406fd2029f23 | 1820 | * to be OR'ed in here or in user code. |
| mbed_official | 324:406fd2029f23 | 1821 | */ |
| mbed_official | 324:406fd2029f23 | 1822 | |
| mbed_official | 324:406fd2029f23 | 1823 | CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1); |
| mbed_official | 324:406fd2029f23 | 1824 | |
| mbed_official | 324:406fd2029f23 | 1825 | /* |
| mbed_official | 324:406fd2029f23 | 1826 | * Configure MCG_C6 |
| mbed_official | 324:406fd2029f23 | 1827 | * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk |
| mbed_official | 324:406fd2029f23 | 1828 | * The clock monitor is not enabled here as it has likely been enabled previously and |
| mbed_official | 324:406fd2029f23 | 1829 | * so the value of CME is not altered here. |
| mbed_official | 324:406fd2029f23 | 1830 | * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6 |
| mbed_official | 324:406fd2029f23 | 1831 | */ |
| mbed_official | 324:406fd2029f23 | 1832 | |
| mbed_official | 324:406fd2029f23 | 1833 | CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 1834 | CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel); |
| mbed_official | 324:406fd2029f23 | 1835 | |
| mbed_official | 324:406fd2029f23 | 1836 | // wait for PLLST status bit to set |
| mbed_official | 324:406fd2029f23 | 1837 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1838 | { |
| mbed_official | 324:406fd2029f23 | 1839 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) |
| mbed_official | 324:406fd2029f23 | 1840 | { |
| mbed_official | 324:406fd2029f23 | 1841 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1842 | break; |
| mbed_official | 324:406fd2029f23 | 1843 | } |
| mbed_official | 324:406fd2029f23 | 1844 | } |
| mbed_official | 324:406fd2029f23 | 1845 | |
| mbed_official | 324:406fd2029f23 | 1846 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1847 | if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) |
| mbed_official | 324:406fd2029f23 | 1848 | { |
| mbed_official | 324:406fd2029f23 | 1849 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1850 | return kMcgErrPllstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1851 | } |
| mbed_official | 324:406fd2029f23 | 1852 | |
| mbed_official | 324:406fd2029f23 | 1853 | /* Wait for LOCK bit to set */ |
| mbed_official | 324:406fd2029f23 | 1854 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1855 | { |
| mbed_official | 324:406fd2029f23 | 1856 | if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 1857 | { |
| mbed_official | 324:406fd2029f23 | 1858 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1859 | break; |
| mbed_official | 324:406fd2029f23 | 1860 | } |
| mbed_official | 324:406fd2029f23 | 1861 | } |
| mbed_official | 324:406fd2029f23 | 1862 | |
| mbed_official | 324:406fd2029f23 | 1863 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1864 | if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 1865 | { |
| mbed_official | 324:406fd2029f23 | 1866 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1867 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 1868 | } |
| mbed_official | 324:406fd2029f23 | 1869 | |
| mbed_official | 324:406fd2029f23 | 1870 | #if FSL_FEATURE_MCG_USE_PLLREFSEL |
| mbed_official | 324:406fd2029f23 | 1871 | /* wait for PLLCST status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 1872 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1873 | { |
| mbed_official | 324:406fd2029f23 | 1874 | if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 1875 | { |
| mbed_official | 324:406fd2029f23 | 1876 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1877 | break; |
| mbed_official | 324:406fd2029f23 | 1878 | } |
| mbed_official | 324:406fd2029f23 | 1879 | } |
| mbed_official | 324:406fd2029f23 | 1880 | |
| mbed_official | 324:406fd2029f23 | 1881 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1882 | if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 1883 | { |
| mbed_official | 324:406fd2029f23 | 1884 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1885 | return kMcgErrPllcst; |
| mbed_official | 324:406fd2029f23 | 1886 | } |
| mbed_official | 324:406fd2029f23 | 1887 | #endif |
| mbed_official | 324:406fd2029f23 | 1888 | } |
| mbed_official | 324:406fd2029f23 | 1889 | #if FSL_FEATURE_MCG_HAS_PLL1 |
| mbed_official | 324:406fd2029f23 | 1890 | else |
| mbed_official | 324:406fd2029f23 | 1891 | { |
| mbed_official | 324:406fd2029f23 | 1892 | /* |
| mbed_official | 324:406fd2029f23 | 1893 | * Configure MCG_C11 |
| mbed_official | 324:406fd2029f23 | 1894 | * If the PLL is to run in STOP mode |
| mbed_official | 324:406fd2029f23 | 1895 | * then the PLLSTEN bit needs to be OR'ed in here or in user code. |
| mbed_official | 324:406fd2029f23 | 1896 | */ |
| mbed_official | 324:406fd2029f23 | 1897 | CLOCK_HAL_SetPrdiv1(prdivVal - 1); |
| mbed_official | 324:406fd2029f23 | 1898 | |
| mbed_official | 324:406fd2029f23 | 1899 | /* |
| mbed_official | 324:406fd2029f23 | 1900 | * Configure MCG_C12 |
| mbed_official | 324:406fd2029f23 | 1901 | * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk |
| mbed_official | 324:406fd2029f23 | 1902 | * The clock monitor is not enabled here as it has likely been enabled previously |
| mbed_official | 324:406fd2029f23 | 1903 | * and so the value of CME is not altered here. |
| mbed_official | 324:406fd2029f23 | 1904 | * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit |
| mbed_official | 324:406fd2029f23 | 1905 | * in MCG_C12 |
| mbed_official | 324:406fd2029f23 | 1906 | */ |
| mbed_official | 324:406fd2029f23 | 1907 | |
| mbed_official | 324:406fd2029f23 | 1908 | CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 1909 | CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel); |
| mbed_official | 324:406fd2029f23 | 1910 | |
| mbed_official | 324:406fd2029f23 | 1911 | // wait for PLLST status bit to set |
| mbed_official | 324:406fd2029f23 | 1912 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1913 | { |
| mbed_official | 324:406fd2029f23 | 1914 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) |
| mbed_official | 324:406fd2029f23 | 1915 | { |
| mbed_official | 324:406fd2029f23 | 1916 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1917 | break; |
| mbed_official | 324:406fd2029f23 | 1918 | } |
| mbed_official | 324:406fd2029f23 | 1919 | } |
| mbed_official | 324:406fd2029f23 | 1920 | |
| mbed_official | 324:406fd2029f23 | 1921 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1922 | if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) |
| mbed_official | 324:406fd2029f23 | 1923 | { |
| mbed_official | 324:406fd2029f23 | 1924 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1925 | return kMcgErrPllstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 1926 | } |
| mbed_official | 324:406fd2029f23 | 1927 | |
| mbed_official | 324:406fd2029f23 | 1928 | /* Wait for LOCK bit to set */ |
| mbed_official | 324:406fd2029f23 | 1929 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1930 | { |
| mbed_official | 324:406fd2029f23 | 1931 | if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 1932 | { |
| mbed_official | 324:406fd2029f23 | 1933 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1934 | break; |
| mbed_official | 324:406fd2029f23 | 1935 | } |
| mbed_official | 324:406fd2029f23 | 1936 | } |
| mbed_official | 324:406fd2029f23 | 1937 | |
| mbed_official | 324:406fd2029f23 | 1938 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1939 | if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 1940 | { |
| mbed_official | 324:406fd2029f23 | 1941 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1942 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 1943 | } |
| mbed_official | 324:406fd2029f23 | 1944 | |
| mbed_official | 324:406fd2029f23 | 1945 | /* wait for PLLCST status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 1946 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 1947 | { |
| mbed_official | 324:406fd2029f23 | 1948 | if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1) |
| mbed_official | 324:406fd2029f23 | 1949 | { |
| mbed_official | 324:406fd2029f23 | 1950 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 1951 | break; |
| mbed_official | 324:406fd2029f23 | 1952 | } |
| mbed_official | 324:406fd2029f23 | 1953 | } |
| mbed_official | 324:406fd2029f23 | 1954 | |
| mbed_official | 324:406fd2029f23 | 1955 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 1956 | if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1) |
| mbed_official | 324:406fd2029f23 | 1957 | { |
| mbed_official | 324:406fd2029f23 | 1958 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 1959 | return kMcgErrPllcst; |
| mbed_official | 324:406fd2029f23 | 1960 | } |
| mbed_official | 324:406fd2029f23 | 1961 | } |
| mbed_official | 324:406fd2029f23 | 1962 | #endif /* PLL1 is selected */ |
| mbed_official | 324:406fd2029f23 | 1963 | |
| mbed_official | 324:406fd2029f23 | 1964 | /* now in PBE */ |
| mbed_official | 324:406fd2029f23 | 1965 | |
| mbed_official | 324:406fd2029f23 | 1966 | /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 1967 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 1968 | } /* CLOCK_HAL_SetFbeToPbeMode */ |
| mbed_official | 324:406fd2029f23 | 1969 | #endif |
| mbed_official | 324:406fd2029f23 | 1970 | |
| mbed_official | 324:406fd2029f23 | 1971 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 1972 | * |
| mbed_official | 324:406fd2029f23 | 1973 | * Functon name : CLOCK_HAL_SetFbeToBlpeMode |
| mbed_official | 324:406fd2029f23 | 1974 | * Description : Mode transition FBE to BLPE mode |
| mbed_official | 324:406fd2029f23 | 1975 | * This function transitions the MCG from FBE mode to BLPE mode. |
| mbed_official | 324:406fd2029f23 | 1976 | * |
| mbed_official | 324:406fd2029f23 | 1977 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 1978 | * |
| mbed_official | 324:406fd2029f23 | 1979 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 1980 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 1981 | uint32_t CLOCK_HAL_SetFbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 1982 | { |
| mbed_official | 324:406fd2029f23 | 1983 | /* Check MCG is in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1984 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeFBE) |
| mbed_official | 324:406fd2029f23 | 1985 | { |
| mbed_official | 324:406fd2029f23 | 1986 | return kMcgErrNotInFbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 1987 | } |
| mbed_official | 324:406fd2029f23 | 1988 | |
| mbed_official | 324:406fd2029f23 | 1989 | /* To move from FBE to BLPE the LP bit must be set */ |
| mbed_official | 324:406fd2029f23 | 1990 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); |
| mbed_official | 324:406fd2029f23 | 1991 | |
| mbed_official | 324:406fd2029f23 | 1992 | /* now in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 1993 | |
| mbed_official | 324:406fd2029f23 | 1994 | /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 1995 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 1996 | } /* CLOCK_HAL_SetFbeToBlpeMode */ |
| mbed_official | 324:406fd2029f23 | 1997 | |
| mbed_official | 324:406fd2029f23 | 1998 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 1999 | |
| mbed_official | 324:406fd2029f23 | 2000 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2001 | * |
| mbed_official | 324:406fd2029f23 | 2002 | * Functon name : CLOCK_HAL_SetPbeToFbeMode |
| mbed_official | 324:406fd2029f23 | 2003 | * Description : Mode transition PBE to FBE mode |
| mbed_official | 324:406fd2029f23 | 2004 | * This function transitions the MCG from PBE mode to FBE mode. |
| mbed_official | 324:406fd2029f23 | 2005 | * |
| mbed_official | 324:406fd2029f23 | 2006 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 2007 | * |
| mbed_official | 324:406fd2029f23 | 2008 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2009 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2010 | uint32_t CLOCK_HAL_SetPbeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 2011 | { |
| mbed_official | 324:406fd2029f23 | 2012 | int16_t i; |
| mbed_official | 324:406fd2029f23 | 2013 | |
| mbed_official | 324:406fd2029f23 | 2014 | /* Check MCG is in PBE mode */ |
| mbed_official | 324:406fd2029f23 | 2015 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) |
| mbed_official | 324:406fd2029f23 | 2016 | { |
| mbed_official | 324:406fd2029f23 | 2017 | return kMcgErrNotInPbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2018 | } |
| mbed_official | 324:406fd2029f23 | 2019 | |
| mbed_official | 324:406fd2029f23 | 2020 | /* |
| mbed_official | 324:406fd2029f23 | 2021 | * As we are running from the ext clock, by default the external clock settings are valid |
| mbed_official | 324:406fd2029f23 | 2022 | * To move to FBE from PBE simply requires the switching of the PLLS mux to disable the PLL |
| mbed_official | 324:406fd2029f23 | 2023 | */ |
| mbed_official | 324:406fd2029f23 | 2024 | |
| mbed_official | 324:406fd2029f23 | 2025 | CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll); |
| mbed_official | 324:406fd2029f23 | 2026 | |
| mbed_official | 324:406fd2029f23 | 2027 | /* wait for PLLST status bit to set */ |
| mbed_official | 324:406fd2029f23 | 2028 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2029 | { |
| mbed_official | 324:406fd2029f23 | 2030 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) |
| mbed_official | 324:406fd2029f23 | 2031 | { |
| mbed_official | 324:406fd2029f23 | 2032 | /* jump out early if PLLST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2033 | break; |
| mbed_official | 324:406fd2029f23 | 2034 | } |
| mbed_official | 324:406fd2029f23 | 2035 | } |
| mbed_official | 324:406fd2029f23 | 2036 | |
| mbed_official | 324:406fd2029f23 | 2037 | /* check bit is really clear */ |
| mbed_official | 324:406fd2029f23 | 2038 | if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll) |
| mbed_official | 324:406fd2029f23 | 2039 | { |
| mbed_official | 324:406fd2029f23 | 2040 | /* return with error if not clear */ |
| mbed_official | 324:406fd2029f23 | 2041 | return kMcgErrPllstClearTimeout; |
| mbed_official | 324:406fd2029f23 | 2042 | } |
| mbed_official | 324:406fd2029f23 | 2043 | |
| mbed_official | 324:406fd2029f23 | 2044 | /* Now in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 2045 | |
| mbed_official | 324:406fd2029f23 | 2046 | /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 2047 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 2048 | } /* CLOCK_HAL_SetPbeToFbeMode */ |
| mbed_official | 324:406fd2029f23 | 2049 | |
| mbed_official | 324:406fd2029f23 | 2050 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2051 | * |
| mbed_official | 324:406fd2029f23 | 2052 | * Functon name : CLOCK_HAL_SetPbeToPeeMode |
| mbed_official | 324:406fd2029f23 | 2053 | * Description : Mode transition PBE to PEE mode |
| mbed_official | 324:406fd2029f23 | 2054 | * This function transitions the MCG from PBE mode to PEE mode. |
| mbed_official | 324:406fd2029f23 | 2055 | * |
| mbed_official | 324:406fd2029f23 | 2056 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 2057 | * pllcsSelect - PLLCS select setting |
| mbed_official | 324:406fd2029f23 | 2058 | * mcg_pll_clk_select_t is defined in fsl_mcg_hal.h |
| mbed_official | 324:406fd2029f23 | 2059 | * 0: kMcgPllcsSelectPll0 PLL0 output clock is selected |
| mbed_official | 324:406fd2029f23 | 2060 | * 1: kMcgPllcsSelectPll1 PLL1 output clock is selected |
| mbed_official | 324:406fd2029f23 | 2061 | * |
| mbed_official | 324:406fd2029f23 | 2062 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2063 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2064 | uint32_t CLOCK_HAL_SetPbeToPeeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect) |
| mbed_official | 324:406fd2029f23 | 2065 | { |
| mbed_official | 324:406fd2029f23 | 2066 | uint8_t prDiv, vDiv; |
| mbed_official | 324:406fd2029f23 | 2067 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 2068 | uint32_t mcgOut; |
| mbed_official | 324:406fd2029f23 | 2069 | |
| mbed_official | 324:406fd2029f23 | 2070 | /* Check MCG is in PBE mode */ |
| mbed_official | 324:406fd2029f23 | 2071 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) |
| mbed_official | 324:406fd2029f23 | 2072 | { |
| mbed_official | 324:406fd2029f23 | 2073 | return kMcgErrNotInPbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2074 | } |
| mbed_official | 324:406fd2029f23 | 2075 | |
| mbed_official | 324:406fd2029f23 | 2076 | /* As the PLL settings have already been checked when PBE mode was enterred they are not checked here */ |
| mbed_official | 324:406fd2029f23 | 2077 | |
| mbed_official | 324:406fd2029f23 | 2078 | /* Check the PLL state before transitioning to PEE mode */ |
| mbed_official | 324:406fd2029f23 | 2079 | |
| mbed_official | 324:406fd2029f23 | 2080 | #if FSL_FEATURE_MCG_HAS_PLL1 |
| mbed_official | 324:406fd2029f23 | 2081 | /* Check the selected PLL state before transitioning to PEE mode */ |
| mbed_official | 324:406fd2029f23 | 2082 | if (pllcsSelect == kMcgPllcsSelectPll1) |
| mbed_official | 324:406fd2029f23 | 2083 | { |
| mbed_official | 324:406fd2029f23 | 2084 | /* Check LOCK bit is set before transitioning MCG to PLL output */ |
| mbed_official | 324:406fd2029f23 | 2085 | /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */ |
| mbed_official | 324:406fd2029f23 | 2086 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2087 | { |
| mbed_official | 324:406fd2029f23 | 2088 | if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 2089 | { |
| mbed_official | 324:406fd2029f23 | 2090 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2091 | break; |
| mbed_official | 324:406fd2029f23 | 2092 | } |
| mbed_official | 324:406fd2029f23 | 2093 | } |
| mbed_official | 324:406fd2029f23 | 2094 | |
| mbed_official | 324:406fd2029f23 | 2095 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2096 | if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 2097 | { |
| mbed_official | 324:406fd2029f23 | 2098 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2099 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 2100 | } |
| mbed_official | 324:406fd2029f23 | 2101 | |
| mbed_official | 324:406fd2029f23 | 2102 | /* Use actual PLL settings to calculate PLL frequency */ |
| mbed_official | 324:406fd2029f23 | 2103 | prDiv = (CLOCK_HAL_GetPrdiv1(baseAddr) + 1); |
| mbed_official | 324:406fd2029f23 | 2104 | vDiv = (CLOCK_HAL_GetVdiv1(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 2105 | } |
| mbed_official | 324:406fd2029f23 | 2106 | else |
| mbed_official | 324:406fd2029f23 | 2107 | #endif |
| mbed_official | 324:406fd2029f23 | 2108 | { |
| mbed_official | 324:406fd2029f23 | 2109 | /* Check LOCK bit is set before transitioning MCG to PLL output */ |
| mbed_official | 324:406fd2029f23 | 2110 | /* already checked in fbe_pbe but good practice to re-check before switch to use PLL */ |
| mbed_official | 324:406fd2029f23 | 2111 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2112 | { |
| mbed_official | 324:406fd2029f23 | 2113 | if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 2114 | { |
| mbed_official | 324:406fd2029f23 | 2115 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2116 | break; |
| mbed_official | 324:406fd2029f23 | 2117 | } |
| mbed_official | 324:406fd2029f23 | 2118 | } |
| mbed_official | 324:406fd2029f23 | 2119 | |
| mbed_official | 324:406fd2029f23 | 2120 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2121 | if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 2122 | { |
| mbed_official | 324:406fd2029f23 | 2123 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2124 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 2125 | } |
| mbed_official | 324:406fd2029f23 | 2126 | |
| mbed_official | 324:406fd2029f23 | 2127 | /* Use actual PLL settings to calculate PLL frequency */ |
| mbed_official | 324:406fd2029f23 | 2128 | prDiv = (CLOCK_HAL_GetPllExternalRefDivider0(baseAddr) + 1); |
| mbed_official | 324:406fd2029f23 | 2129 | vDiv = (CLOCK_HAL_GetVoltCtrlOscDivider0(baseAddr) + FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 2130 | } |
| mbed_official | 324:406fd2029f23 | 2131 | |
| mbed_official | 324:406fd2029f23 | 2132 | /* clear CLKS to switch CLKS mux to select PLL as MCG_OUT */ |
| mbed_official | 324:406fd2029f23 | 2133 | CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelOut); |
| mbed_official | 324:406fd2029f23 | 2134 | |
| mbed_official | 324:406fd2029f23 | 2135 | /* Wait for clock status bits to update */ |
| mbed_official | 324:406fd2029f23 | 2136 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2137 | { |
| mbed_official | 324:406fd2029f23 | 2138 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatPll) |
| mbed_official | 324:406fd2029f23 | 2139 | { |
| mbed_official | 324:406fd2029f23 | 2140 | break; /* jump out early if CLKST = 3 before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2141 | } |
| mbed_official | 324:406fd2029f23 | 2142 | } |
| mbed_official | 324:406fd2029f23 | 2143 | |
| mbed_official | 324:406fd2029f23 | 2144 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatPll) |
| mbed_official | 324:406fd2029f23 | 2145 | { |
| mbed_official | 324:406fd2029f23 | 2146 | return kMcgErrClkst3; /* check CLKST is set correctly and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 2147 | } |
| mbed_official | 324:406fd2029f23 | 2148 | |
| mbed_official | 324:406fd2029f23 | 2149 | /* Now in PEE */ |
| mbed_official | 324:406fd2029f23 | 2150 | |
| mbed_official | 324:406fd2029f23 | 2151 | /* MCGOUT equals PLL output frequency with any special divider */ |
| mbed_official | 324:406fd2029f23 | 2152 | mcgOut = (crystalVal / prDiv) * vDiv; |
| mbed_official | 324:406fd2029f23 | 2153 | |
| mbed_official | 324:406fd2029f23 | 2154 | return mcgOut; |
| mbed_official | 324:406fd2029f23 | 2155 | } /* CLOCK_HAL_SetPbeToPeeMode */ |
| mbed_official | 324:406fd2029f23 | 2156 | |
| mbed_official | 324:406fd2029f23 | 2157 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2158 | * |
| mbed_official | 324:406fd2029f23 | 2159 | * Functon name : CLOCK_HAL_SetPbeToBlpeMode |
| mbed_official | 324:406fd2029f23 | 2160 | * Description : Mode transition PBE to BLPE mode |
| mbed_official | 324:406fd2029f23 | 2161 | * This function transitions the MCG from PBE mode to BLPE mode. |
| mbed_official | 324:406fd2029f23 | 2162 | * |
| mbed_official | 324:406fd2029f23 | 2163 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 2164 | * |
| mbed_official | 324:406fd2029f23 | 2165 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2166 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2167 | uint32_t CLOCK_HAL_SetPbeToBlpeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 2168 | { |
| mbed_official | 324:406fd2029f23 | 2169 | /* Check MCG is in PBE mode */ |
| mbed_official | 324:406fd2029f23 | 2170 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePBE) |
| mbed_official | 324:406fd2029f23 | 2171 | { |
| mbed_official | 324:406fd2029f23 | 2172 | return kMcgErrNotInPbeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2173 | } |
| mbed_official | 324:406fd2029f23 | 2174 | |
| mbed_official | 324:406fd2029f23 | 2175 | /* To enter BLPE mode the LP bit must be set, disabling the PLL */ |
| mbed_official | 324:406fd2029f23 | 2176 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelLowPower); |
| mbed_official | 324:406fd2029f23 | 2177 | |
| mbed_official | 324:406fd2029f23 | 2178 | /* Now in BLPE mode */ |
| mbed_official | 324:406fd2029f23 | 2179 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 2180 | } /* CLOCK_HAL_SetPbeToBlpeMode */ |
| mbed_official | 324:406fd2029f23 | 2181 | |
| mbed_official | 324:406fd2029f23 | 2182 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2183 | * |
| mbed_official | 324:406fd2029f23 | 2184 | * Functon name : CLOCK_HAL_SetPeeToPbeMode |
| mbed_official | 324:406fd2029f23 | 2185 | * Description : Mode transition PEE to PBE mode |
| mbed_official | 324:406fd2029f23 | 2186 | * This function transitions the MCG from PEE mode to PBE mode. |
| mbed_official | 324:406fd2029f23 | 2187 | * |
| mbed_official | 324:406fd2029f23 | 2188 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 2189 | * |
| mbed_official | 324:406fd2029f23 | 2190 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2191 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2192 | uint32_t CLOCK_HAL_SetPeeToPbeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 2193 | { |
| mbed_official | 324:406fd2029f23 | 2194 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 2195 | |
| mbed_official | 324:406fd2029f23 | 2196 | /* Check MCG is in PEE mode */ |
| mbed_official | 324:406fd2029f23 | 2197 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModePEE) |
| mbed_official | 324:406fd2029f23 | 2198 | { |
| mbed_official | 324:406fd2029f23 | 2199 | return kMcgErrNotInPeeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2200 | } |
| mbed_official | 324:406fd2029f23 | 2201 | |
| mbed_official | 324:406fd2029f23 | 2202 | /* |
| mbed_official | 324:406fd2029f23 | 2203 | * As we are running from the PLL by default the PLL and external clock settings are valid |
| mbed_official | 324:406fd2029f23 | 2204 | * To move to PBE from PEE simply requires the switching of the CLKS mux to select the ext clock |
| mbed_official | 324:406fd2029f23 | 2205 | */ |
| mbed_official | 324:406fd2029f23 | 2206 | /* As CLKS is already 0 the CLKS value can simply be OR'ed into the register */ |
| mbed_official | 324:406fd2029f23 | 2207 | CLOCK_HAL_SetClkSrcMode(baseAddr, kMcgClkSelExternal); |
| mbed_official | 324:406fd2029f23 | 2208 | |
| mbed_official | 324:406fd2029f23 | 2209 | /* Wait for clock status bits to update */ |
| mbed_official | 324:406fd2029f23 | 2210 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2211 | { |
| mbed_official | 324:406fd2029f23 | 2212 | if (CLOCK_HAL_GetClkStatMode(baseAddr) == kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 2213 | { |
| mbed_official | 324:406fd2029f23 | 2214 | break; /* jump out early if CLKST shows EXT CLK slected before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2215 | } |
| mbed_official | 324:406fd2029f23 | 2216 | } |
| mbed_official | 324:406fd2029f23 | 2217 | |
| mbed_official | 324:406fd2029f23 | 2218 | if (CLOCK_HAL_GetClkStatMode(baseAddr) != kMcgClkStatExternalRef) |
| mbed_official | 324:406fd2029f23 | 2219 | { |
| mbed_official | 324:406fd2029f23 | 2220 | return kMcgErrClkst2; /* check EXT CLK is really selected and return with error if not */ |
| mbed_official | 324:406fd2029f23 | 2221 | } |
| mbed_official | 324:406fd2029f23 | 2222 | |
| mbed_official | 324:406fd2029f23 | 2223 | /* Now in PBE mode */ |
| mbed_official | 324:406fd2029f23 | 2224 | return crystalVal; /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 2225 | } /* CLOCK_HAL_SetPeeToPbeMode */ |
| mbed_official | 324:406fd2029f23 | 2226 | |
| mbed_official | 324:406fd2029f23 | 2227 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2228 | * |
| mbed_official | 324:406fd2029f23 | 2229 | * Functon name : CLOCK_HAL_SetBlpeToPbeMode |
| mbed_official | 324:406fd2029f23 | 2230 | * Description : Mode transition BLPE to PBE mode |
| mbed_official | 324:406fd2029f23 | 2231 | * This function transitions the MCG from BLPE mode to PBE mode. |
| mbed_official | 324:406fd2029f23 | 2232 | * The function requires the desired OSC and PLL be passed in to it for compatibility |
| mbed_official | 324:406fd2029f23 | 2233 | * with the future support of OSC/PLL selection |
| mbed_official | 324:406fd2029f23 | 2234 | * (This function presently only supports OSC0 as PLL source) |
| mbed_official | 324:406fd2029f23 | 2235 | * Parameters: crystalVal - external clock frequency in Hz |
| mbed_official | 324:406fd2029f23 | 2236 | * pllcsSelect - 0 to select PLL0, non-zero to select PLL1. |
| mbed_official | 324:406fd2029f23 | 2237 | * prdivVal - value to divide the external clock source by to create |
| mbed_official | 324:406fd2029f23 | 2238 | * the desired PLL reference clock frequency |
| mbed_official | 324:406fd2029f23 | 2239 | * vdivVal - value to multiply the PLL reference clock frequency by |
| mbed_official | 324:406fd2029f23 | 2240 | * |
| mbed_official | 324:406fd2029f23 | 2241 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2242 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2243 | uint32_t CLOCK_HAL_SetBlpeToPbeMode(uint32_t baseAddr, uint32_t crystalVal, mcg_pll_clk_select_t pllcsSelect, uint8_t prdivVal, uint8_t vdivVal) |
| mbed_official | 324:406fd2029f23 | 2244 | { |
| mbed_official | 324:406fd2029f23 | 2245 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 2246 | uint32_t pllFreq; |
| mbed_official | 324:406fd2029f23 | 2247 | |
| mbed_official | 324:406fd2029f23 | 2248 | /* Check MCG is in BLPE mode */ |
| mbed_official | 324:406fd2029f23 | 2249 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE) |
| mbed_official | 324:406fd2029f23 | 2250 | { |
| mbed_official | 324:406fd2029f23 | 2251 | return kMcgErrNotInBlpeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2252 | } |
| mbed_official | 324:406fd2029f23 | 2253 | |
| mbed_official | 324:406fd2029f23 | 2254 | /* |
| mbed_official | 324:406fd2029f23 | 2255 | * As the external frequency (osc0) has already been checked when FBE mode was enterred |
| mbed_official | 324:406fd2029f23 | 2256 | * it is not checked here. |
| mbed_official | 324:406fd2029f23 | 2257 | */ |
| mbed_official | 324:406fd2029f23 | 2258 | |
| mbed_official | 324:406fd2029f23 | 2259 | /* Check PLL divider settings are within spec.*/ |
| mbed_official | 324:406fd2029f23 | 2260 | if ((prdivVal < 1) || (prdivVal > FSL_FEATURE_MCG_PLL_PRDIV_MAX)) |
| mbed_official | 324:406fd2029f23 | 2261 | { |
| mbed_official | 324:406fd2029f23 | 2262 | return kMcgErrPllPrdidRange; |
| mbed_official | 324:406fd2029f23 | 2263 | } |
| mbed_official | 324:406fd2029f23 | 2264 | |
| mbed_official | 324:406fd2029f23 | 2265 | if ((vdivVal < FSL_FEATURE_MCG_PLL_VDIV_BASE) || (vdivVal > (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31))) |
| mbed_official | 324:406fd2029f23 | 2266 | { |
| mbed_official | 324:406fd2029f23 | 2267 | return kMcgErrPllVdivRange; |
| mbed_official | 324:406fd2029f23 | 2268 | } |
| mbed_official | 324:406fd2029f23 | 2269 | |
| mbed_official | 324:406fd2029f23 | 2270 | /* Check PLL reference clock frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 2271 | if (((crystalVal / prdivVal) < kMcgConstant8000000) || ((crystalVal / prdivVal) > kMcgConstant32000000)) |
| mbed_official | 324:406fd2029f23 | 2272 | { |
| mbed_official | 324:406fd2029f23 | 2273 | return kMcgErrPllRefClkRange; |
| mbed_official | 324:406fd2029f23 | 2274 | } |
| mbed_official | 324:406fd2029f23 | 2275 | |
| mbed_official | 324:406fd2029f23 | 2276 | /* Check PLL output frequency is within spec. */ |
| mbed_official | 324:406fd2029f23 | 2277 | pllFreq = (crystalVal / prdivVal) * vdivVal; |
| mbed_official | 324:406fd2029f23 | 2278 | if ((pllFreq < kMcgConstant180000000) || (pllFreq > kMcgConstant360000000)) |
| mbed_official | 324:406fd2029f23 | 2279 | { |
| mbed_official | 324:406fd2029f23 | 2280 | return kMcgErrPllOutClkRange; |
| mbed_official | 324:406fd2029f23 | 2281 | } |
| mbed_official | 324:406fd2029f23 | 2282 | |
| mbed_official | 324:406fd2029f23 | 2283 | #if FSL_FEATURE_MCG_HAS_PLL1 |
| mbed_official | 324:406fd2029f23 | 2284 | /* set pllcsSelect */ |
| mbed_official | 324:406fd2029f23 | 2285 | CLOCK_HAL_SetPllcs(pllcsSelect); |
| mbed_official | 324:406fd2029f23 | 2286 | |
| mbed_official | 324:406fd2029f23 | 2287 | if (pllcsSelect == kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 2288 | #endif |
| mbed_official | 324:406fd2029f23 | 2289 | { |
| mbed_official | 324:406fd2029f23 | 2290 | /* |
| mbed_official | 324:406fd2029f23 | 2291 | * Configure MCG_C5 |
| mbed_official | 324:406fd2029f23 | 2292 | * If the PLL is to run in STOP mode then the PLLSTEN bit needs |
| mbed_official | 324:406fd2029f23 | 2293 | * to be OR'ed in here or in user code. |
| mbed_official | 324:406fd2029f23 | 2294 | */ |
| mbed_official | 324:406fd2029f23 | 2295 | |
| mbed_official | 324:406fd2029f23 | 2296 | CLOCK_HAL_SetPllExternalRefDivider0(baseAddr, prdivVal - 1); |
| mbed_official | 324:406fd2029f23 | 2297 | |
| mbed_official | 324:406fd2029f23 | 2298 | /* |
| mbed_official | 324:406fd2029f23 | 2299 | * Configure MCG_C6 |
| mbed_official | 324:406fd2029f23 | 2300 | * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk |
| mbed_official | 324:406fd2029f23 | 2301 | * The clock monitor is not enabled here as it has likely been enabled previously and |
| mbed_official | 324:406fd2029f23 | 2302 | * so the value of CME is not altered here. |
| mbed_official | 324:406fd2029f23 | 2303 | * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit in MCG_C6 |
| mbed_official | 324:406fd2029f23 | 2304 | */ |
| mbed_official | 324:406fd2029f23 | 2305 | |
| mbed_official | 324:406fd2029f23 | 2306 | CLOCK_HAL_SetVoltCtrlOscDivider0(baseAddr, vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 2307 | CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelPllClkSel); |
| mbed_official | 324:406fd2029f23 | 2308 | |
| mbed_official | 324:406fd2029f23 | 2309 | /* Set LP bit to enable the PLL */ |
| mbed_official | 324:406fd2029f23 | 2310 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 2311 | |
| mbed_official | 324:406fd2029f23 | 2312 | // wait for PLLST status bit to set |
| mbed_official | 324:406fd2029f23 | 2313 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2314 | { |
| mbed_official | 324:406fd2029f23 | 2315 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) |
| mbed_official | 324:406fd2029f23 | 2316 | { |
| mbed_official | 324:406fd2029f23 | 2317 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2318 | break; |
| mbed_official | 324:406fd2029f23 | 2319 | } |
| mbed_official | 324:406fd2029f23 | 2320 | } |
| mbed_official | 324:406fd2029f23 | 2321 | |
| mbed_official | 324:406fd2029f23 | 2322 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2323 | if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) |
| mbed_official | 324:406fd2029f23 | 2324 | { |
| mbed_official | 324:406fd2029f23 | 2325 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2326 | return kMcgErrPllstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 2327 | } |
| mbed_official | 324:406fd2029f23 | 2328 | |
| mbed_official | 324:406fd2029f23 | 2329 | /* Wait for LOCK bit to set */ |
| mbed_official | 324:406fd2029f23 | 2330 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2331 | { |
| mbed_official | 324:406fd2029f23 | 2332 | if (CLOCK_HAL_GetLock0Mode(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 2333 | { |
| mbed_official | 324:406fd2029f23 | 2334 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2335 | break; |
| mbed_official | 324:406fd2029f23 | 2336 | } |
| mbed_official | 324:406fd2029f23 | 2337 | } |
| mbed_official | 324:406fd2029f23 | 2338 | |
| mbed_official | 324:406fd2029f23 | 2339 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2340 | if ((CLOCK_HAL_GetLock0Mode(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 2341 | { |
| mbed_official | 324:406fd2029f23 | 2342 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2343 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 2344 | } |
| mbed_official | 324:406fd2029f23 | 2345 | |
| mbed_official | 324:406fd2029f23 | 2346 | #if FSL_FEATURE_MCG_USE_PLLREFSEL |
| mbed_official | 324:406fd2029f23 | 2347 | /* wait for PLLCST status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 2348 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2349 | { |
| mbed_official | 324:406fd2029f23 | 2350 | if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 2351 | { |
| mbed_official | 324:406fd2029f23 | 2352 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2353 | break; |
| mbed_official | 324:406fd2029f23 | 2354 | } |
| mbed_official | 324:406fd2029f23 | 2355 | } |
| mbed_official | 324:406fd2029f23 | 2356 | |
| mbed_official | 324:406fd2029f23 | 2357 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2358 | if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll0) |
| mbed_official | 324:406fd2029f23 | 2359 | { |
| mbed_official | 324:406fd2029f23 | 2360 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2361 | return kMcgErrPllcst; |
| mbed_official | 324:406fd2029f23 | 2362 | } |
| mbed_official | 324:406fd2029f23 | 2363 | #endif |
| mbed_official | 324:406fd2029f23 | 2364 | } |
| mbed_official | 324:406fd2029f23 | 2365 | #if FSL_FEATURE_MCG_HAS_PLL1 |
| mbed_official | 324:406fd2029f23 | 2366 | else |
| mbed_official | 324:406fd2029f23 | 2367 | { |
| mbed_official | 324:406fd2029f23 | 2368 | /* |
| mbed_official | 324:406fd2029f23 | 2369 | * Configure MCG_C11 |
| mbed_official | 324:406fd2029f23 | 2370 | * If the PLL is to run in STOP mode |
| mbed_official | 324:406fd2029f23 | 2371 | * then the PLLSTEN bit needs to be OR'ed in here or in user code. |
| mbed_official | 324:406fd2029f23 | 2372 | */ |
| mbed_official | 324:406fd2029f23 | 2373 | CLOCK_HAL_SetPrdiv1(prdivVal - 1); |
| mbed_official | 324:406fd2029f23 | 2374 | |
| mbed_official | 324:406fd2029f23 | 2375 | /* |
| mbed_official | 324:406fd2029f23 | 2376 | * Configure MCG_C12 |
| mbed_official | 324:406fd2029f23 | 2377 | * The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk |
| mbed_official | 324:406fd2029f23 | 2378 | * The clock monitor is not enabled here as it has likely been enabled previously |
| mbed_official | 324:406fd2029f23 | 2379 | * and so the value of CME is not altered here. |
| mbed_official | 324:406fd2029f23 | 2380 | * The loss of lock interrupt can be enabled by seperate OR'ing in the LOLIE bit |
| mbed_official | 324:406fd2029f23 | 2381 | * in MCG_C12 |
| mbed_official | 324:406fd2029f23 | 2382 | */ |
| mbed_official | 324:406fd2029f23 | 2383 | |
| mbed_official | 324:406fd2029f23 | 2384 | CLOCK_HAL_SetVdiv1(vdivVal - FSL_FEATURE_MCG_PLL_VDIV_BASE); |
| mbed_official | 324:406fd2029f23 | 2385 | CLOCK_HAL_SetPllSelMode(kMcgPllSelPllClkSel); |
| mbed_official | 324:406fd2029f23 | 2386 | |
| mbed_official | 324:406fd2029f23 | 2387 | /* Set LP bit to enable the PLL */ |
| mbed_official | 324:406fd2029f23 | 2388 | CLOCK_HAL_SetLowPowerMode(kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 2389 | |
| mbed_official | 324:406fd2029f23 | 2390 | // wait for PLLST status bit to set |
| mbed_official | 324:406fd2029f23 | 2391 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2392 | { |
| mbed_official | 324:406fd2029f23 | 2393 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatPllClkSel) |
| mbed_official | 324:406fd2029f23 | 2394 | { |
| mbed_official | 324:406fd2029f23 | 2395 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2396 | break; |
| mbed_official | 324:406fd2029f23 | 2397 | } |
| mbed_official | 324:406fd2029f23 | 2398 | } |
| mbed_official | 324:406fd2029f23 | 2399 | |
| mbed_official | 324:406fd2029f23 | 2400 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2401 | if ((CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatPllClkSel)) |
| mbed_official | 324:406fd2029f23 | 2402 | { |
| mbed_official | 324:406fd2029f23 | 2403 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2404 | return kMcgErrPllstSetTimeout; |
| mbed_official | 324:406fd2029f23 | 2405 | } |
| mbed_official | 324:406fd2029f23 | 2406 | |
| mbed_official | 324:406fd2029f23 | 2407 | /* Wait for LOCK bit to set */ |
| mbed_official | 324:406fd2029f23 | 2408 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2409 | { |
| mbed_official | 324:406fd2029f23 | 2410 | if (CLOCK_HAL_GetLock1(baseAddr) == kMcgLockLocked) |
| mbed_official | 324:406fd2029f23 | 2411 | { |
| mbed_official | 324:406fd2029f23 | 2412 | /* jump out early if LOCK sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2413 | break; |
| mbed_official | 324:406fd2029f23 | 2414 | } |
| mbed_official | 324:406fd2029f23 | 2415 | } |
| mbed_official | 324:406fd2029f23 | 2416 | |
| mbed_official | 324:406fd2029f23 | 2417 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2418 | if ((CLOCK_HAL_GetLock1(baseAddr) != kMcgLockLocked)) |
| mbed_official | 324:406fd2029f23 | 2419 | { |
| mbed_official | 324:406fd2029f23 | 2420 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2421 | return kMcgErrPllLockBit; |
| mbed_official | 324:406fd2029f23 | 2422 | } |
| mbed_official | 324:406fd2029f23 | 2423 | |
| mbed_official | 324:406fd2029f23 | 2424 | /* wait for PLLCST status bit to clear */ |
| mbed_official | 324:406fd2029f23 | 2425 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2426 | { |
| mbed_official | 324:406fd2029f23 | 2427 | if (CLOCK_HAL_GetPllcst(baseAddr) == kMcgPllcsSelectPll1) |
| mbed_official | 324:406fd2029f23 | 2428 | { |
| mbed_official | 324:406fd2029f23 | 2429 | /* jump out early if PLLST sets before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2430 | break; |
| mbed_official | 324:406fd2029f23 | 2431 | } |
| mbed_official | 324:406fd2029f23 | 2432 | } |
| mbed_official | 324:406fd2029f23 | 2433 | |
| mbed_official | 324:406fd2029f23 | 2434 | /* check bit is really set */ |
| mbed_official | 324:406fd2029f23 | 2435 | if (CLOCK_HAL_GetPllcst(baseAddr) != kMcgPllcsSelectPll1) |
| mbed_official | 324:406fd2029f23 | 2436 | { |
| mbed_official | 324:406fd2029f23 | 2437 | /* return with error if not set */ |
| mbed_official | 324:406fd2029f23 | 2438 | return kMcgErrPllcst; |
| mbed_official | 324:406fd2029f23 | 2439 | } |
| mbed_official | 324:406fd2029f23 | 2440 | } |
| mbed_official | 324:406fd2029f23 | 2441 | #endif /* PLL1 is selected */ |
| mbed_official | 324:406fd2029f23 | 2442 | |
| mbed_official | 324:406fd2029f23 | 2443 | /* now in PBE */ |
| mbed_official | 324:406fd2029f23 | 2444 | |
| mbed_official | 324:406fd2029f23 | 2445 | /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 2446 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 2447 | } /* CLOCK_HAL_SetBlpeToPbeMode */ |
| mbed_official | 324:406fd2029f23 | 2448 | #endif |
| mbed_official | 324:406fd2029f23 | 2449 | |
| mbed_official | 324:406fd2029f23 | 2450 | /*FUNCTION****************************************************************************** |
| mbed_official | 324:406fd2029f23 | 2451 | * |
| mbed_official | 324:406fd2029f23 | 2452 | * Functon name : CLOCK_HAL_SetBlpeToFbeMode |
| mbed_official | 324:406fd2029f23 | 2453 | * Description : Mode transition BLPE to FBE mode |
| mbed_official | 324:406fd2029f23 | 2454 | * This function transitions the MCG from BLPE mode to FBE mode. |
| mbed_official | 324:406fd2029f23 | 2455 | * |
| mbed_official | 324:406fd2029f23 | 2456 | * Parameters: crystalVal - external reference clock frequency value |
| mbed_official | 324:406fd2029f23 | 2457 | * |
| mbed_official | 324:406fd2029f23 | 2458 | * Return value : MCGCLKOUT frequency (Hz) or error code |
| mbed_official | 324:406fd2029f23 | 2459 | *END***********************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 2460 | uint32_t CLOCK_HAL_SetBlpeToFbeMode(uint32_t baseAddr, uint32_t crystalVal) |
| mbed_official | 324:406fd2029f23 | 2461 | { |
| mbed_official | 324:406fd2029f23 | 2462 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 2463 | uint16_t i; |
| mbed_official | 324:406fd2029f23 | 2464 | #endif |
| mbed_official | 324:406fd2029f23 | 2465 | |
| mbed_official | 324:406fd2029f23 | 2466 | /* Check MCG is in BLPE mode */ |
| mbed_official | 324:406fd2029f23 | 2467 | if (CLOCK_HAL_GetMcgMode(baseAddr) != kMcgModeBLPE) |
| mbed_official | 324:406fd2029f23 | 2468 | { |
| mbed_official | 324:406fd2029f23 | 2469 | return kMcgErrNotInBlpeMode; /* return error code */ |
| mbed_official | 324:406fd2029f23 | 2470 | } |
| mbed_official | 324:406fd2029f23 | 2471 | |
| mbed_official | 324:406fd2029f23 | 2472 | /* To move from BLPE to FBE the PLLS mux be set to select the FLL output*/ |
| mbed_official | 324:406fd2029f23 | 2473 | /* and the LP bit must be cleared */ |
| mbed_official | 324:406fd2029f23 | 2474 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 2475 | CLOCK_HAL_SetPllSelMode(baseAddr, kMcgPllSelFll); |
| mbed_official | 324:406fd2029f23 | 2476 | #endif |
| mbed_official | 324:406fd2029f23 | 2477 | CLOCK_HAL_SetLowPowerMode(baseAddr, kMcgLowPowerSelNormal); |
| mbed_official | 324:406fd2029f23 | 2478 | |
| mbed_official | 324:406fd2029f23 | 2479 | #if FSL_FEATURE_MCG_HAS_PLL |
| mbed_official | 324:406fd2029f23 | 2480 | /* wait for PLLST status bit to set */ |
| mbed_official | 324:406fd2029f23 | 2481 | for (i = 0 ; i < kMcgConstant2000 ; i++) |
| mbed_official | 324:406fd2029f23 | 2482 | { |
| mbed_official | 324:406fd2029f23 | 2483 | if (CLOCK_HAL_GetPllStatMode(baseAddr) == kMcgPllStatFll) |
| mbed_official | 324:406fd2029f23 | 2484 | { |
| mbed_official | 324:406fd2029f23 | 2485 | /* jump out early if PLLST clears before loop finishes */ |
| mbed_official | 324:406fd2029f23 | 2486 | break; |
| mbed_official | 324:406fd2029f23 | 2487 | } |
| mbed_official | 324:406fd2029f23 | 2488 | } |
| mbed_official | 324:406fd2029f23 | 2489 | |
| mbed_official | 324:406fd2029f23 | 2490 | /* check bit is really clear */ |
| mbed_official | 324:406fd2029f23 | 2491 | if (CLOCK_HAL_GetPllStatMode(baseAddr) != kMcgPllStatFll) |
| mbed_official | 324:406fd2029f23 | 2492 | { |
| mbed_official | 324:406fd2029f23 | 2493 | /* return with error if not clear */ |
| mbed_official | 324:406fd2029f23 | 2494 | return kMcgErrPllstClearTimeout; |
| mbed_official | 324:406fd2029f23 | 2495 | } |
| mbed_official | 324:406fd2029f23 | 2496 | #endif |
| mbed_official | 324:406fd2029f23 | 2497 | /* now in FBE mode */ |
| mbed_official | 324:406fd2029f23 | 2498 | |
| mbed_official | 324:406fd2029f23 | 2499 | /* MCGOUT frequency equals external clock frequency */ |
| mbed_official | 324:406fd2029f23 | 2500 | return crystalVal; |
| mbed_official | 324:406fd2029f23 | 2501 | } /* CLOCK_HAL_SetBlpeToFbeMode */ |
