mbed official
mbed library sources
Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more
Superseded
This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_features.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
- Parent:
- 149:1fb5f62b92bd
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Version: rev. 1.0, 2014-05-14 |
| mbed_official | 324:406fd2029f23 | 4 | ** Build: b140515 |
| mbed_official | 324:406fd2029f23 | 5 | ** |
| mbed_official | 324:406fd2029f23 | 6 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 7 | ** Chip specific module features. |
| mbed_official | 324:406fd2029f23 | 8 | ** |
| mbed_official | 324:406fd2029f23 | 9 | ** Copyright: 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 10 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 13 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 16 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 20 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 21 | ** |
| mbed_official | 324:406fd2029f23 | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 23 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 24 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 25 | ** |
| mbed_official | 324:406fd2029f23 | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 36 | ** |
| mbed_official | 324:406fd2029f23 | 37 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 38 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 39 | ** |
| mbed_official | 324:406fd2029f23 | 40 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 41 | ** - rev. 1.0 (2014-05-14) |
| mbed_official | 324:406fd2029f23 | 42 | ** Customer release. |
| mbed_official | 324:406fd2029f23 | 43 | ** |
| mbed_official | 324:406fd2029f23 | 44 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 45 | */ |
| mbed_official | 324:406fd2029f23 | 46 | |
| mbed_official | 324:406fd2029f23 | 47 | #if !defined(__FSL_MCG_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 48 | #define __FSL_MCG_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 49 | |
| mbed_official | 324:406fd2029f23 | 50 | #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \ |
| mbed_official | 324:406fd2029f23 | 51 | defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \ |
| mbed_official | 324:406fd2029f23 | 52 | defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10) || \ |
| mbed_official | 324:406fd2029f23 | 53 | defined(CPU_MKV31F128VLH10) || defined(CPU_MKV31F128VLL10) |
| mbed_official | 324:406fd2029f23 | 54 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 55 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
| mbed_official | 324:406fd2029f23 | 56 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 57 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
| mbed_official | 324:406fd2029f23 | 58 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 146:f64d43ff0c18 | 59 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 60 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 146:f64d43ff0c18 | 61 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 62 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 63 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 64 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 65 | #define FSL_FEATURE_MCG_HAS_IRC_48M (1) |
| mbed_official | 324:406fd2029f23 | 66 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 67 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 68 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 69 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 70 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 71 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 72 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 73 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 74 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 75 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 76 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 77 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 78 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 79 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
| mbed_official | 324:406fd2029f23 | 80 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 81 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 82 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 83 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 84 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 85 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 86 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 87 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 88 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 89 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 90 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 91 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 92 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 93 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 94 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 95 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 96 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 97 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 98 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 99 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 100 | #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ |
| mbed_official | 324:406fd2029f23 | 101 | defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ |
| mbed_official | 324:406fd2029f23 | 102 | defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ |
| mbed_official | 324:406fd2029f23 | 103 | defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ |
| mbed_official | 324:406fd2029f23 | 104 | defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ |
| mbed_official | 324:406fd2029f23 | 105 | defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ |
| mbed_official | 324:406fd2029f23 | 106 | defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ |
| mbed_official | 324:406fd2029f23 | 107 | defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) |
| mbed_official | 324:406fd2029f23 | 108 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 109 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) |
| mbed_official | 324:406fd2029f23 | 110 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 111 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 112 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 113 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 114 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 115 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
| mbed_official | 324:406fd2029f23 | 116 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 117 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 118 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 146:f64d43ff0c18 | 119 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 120 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 121 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 122 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 123 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 124 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 125 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 126 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 127 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 128 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 129 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 130 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 131 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 132 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 133 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 134 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 135 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 136 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 137 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 138 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 139 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 140 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 141 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 142 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 143 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 144 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 145 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 146 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 147 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 148 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 149 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 150 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 151 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 152 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 153 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 154 | #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) |
| mbed_official | 324:406fd2029f23 | 155 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 156 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
| mbed_official | 324:406fd2029f23 | 157 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 158 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
| mbed_official | 324:406fd2029f23 | 159 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 160 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 161 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 162 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
| mbed_official | 324:406fd2029f23 | 163 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 164 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 165 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 166 | #define FSL_FEATURE_MCG_HAS_IRC_48M (1) |
| mbed_official | 324:406fd2029f23 | 167 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 168 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 169 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 170 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 171 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 172 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 173 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 174 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 175 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 176 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 177 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 178 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 179 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 180 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
| mbed_official | 324:406fd2029f23 | 181 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 182 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 183 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 184 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 185 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 186 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 187 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 188 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 189 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 190 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 191 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 192 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 193 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 194 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 195 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 196 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 197 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 198 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 199 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 200 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 201 | #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ |
| mbed_official | 324:406fd2029f23 | 202 | defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \ |
| mbed_official | 324:406fd2029f23 | 203 | defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || defined(CPU_MK63FN1M0VLQ12) || \ |
| mbed_official | 324:406fd2029f23 | 204 | defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FX512VLL12) || \ |
| mbed_official | 324:406fd2029f23 | 205 | defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VMD12) || \ |
| mbed_official | 324:406fd2029f23 | 206 | defined(CPU_MK64FN1M0VMD12) |
| mbed_official | 324:406fd2029f23 | 207 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 208 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) |
| mbed_official | 324:406fd2029f23 | 209 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 210 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 211 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 212 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 213 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 214 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
| mbed_official | 324:406fd2029f23 | 215 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 216 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 217 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 218 | #define FSL_FEATURE_MCG_HAS_IRC_48M (1) |
| mbed_official | 324:406fd2029f23 | 219 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 220 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 221 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 222 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 223 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 146:f64d43ff0c18 | 224 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 225 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 226 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 227 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 146:f64d43ff0c18 | 228 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 229 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 230 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 231 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 232 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 233 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 234 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 235 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 236 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 237 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 238 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 239 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 240 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 241 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 242 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 243 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 244 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 245 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 246 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 247 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 248 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 249 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 250 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 251 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 252 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 253 | #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \ |
| mbed_official | 324:406fd2029f23 | 254 | defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) |
| mbed_official | 324:406fd2029f23 | 255 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 256 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) |
| mbed_official | 324:406fd2029f23 | 257 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 258 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 259 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 260 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 261 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 146:f64d43ff0c18 | 262 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
| mbed_official | 324:406fd2029f23 | 263 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 264 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 265 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 266 | #define FSL_FEATURE_MCG_HAS_IRC_48M (1) |
| mbed_official | 324:406fd2029f23 | 267 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 268 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 269 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 270 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 271 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 272 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 273 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 274 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 275 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 276 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 277 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 278 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 279 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 280 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 281 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 282 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 283 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 284 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 285 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 286 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) |
| mbed_official | 324:406fd2029f23 | 287 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 288 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 289 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 290 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 291 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 292 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 293 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 294 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 295 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 296 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 297 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 298 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 299 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 300 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 301 | #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 324:406fd2029f23 | 302 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 324:406fd2029f23 | 303 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 304 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) |
| mbed_official | 324:406fd2029f23 | 305 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 306 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) |
| mbed_official | 324:406fd2029f23 | 307 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 308 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 309 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 310 | #define FSL_FEATURE_MCG_HAS_RTC_32K (1) |
| mbed_official | 324:406fd2029f23 | 311 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 312 | #define FSL_FEATURE_MCG_HAS_PLL1 (1) |
| mbed_official | 324:406fd2029f23 | 313 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 146:f64d43ff0c18 | 314 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 315 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 316 | #define FSL_FEATURE_MCG_HAS_OSC1 (1) |
| mbed_official | 324:406fd2029f23 | 317 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 146:f64d43ff0c18 | 318 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 319 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 146:f64d43ff0c18 | 320 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 321 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 322 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 323 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 146:f64d43ff0c18 | 324 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (1) |
| mbed_official | 324:406fd2029f23 | 325 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 326 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 327 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 328 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 329 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 330 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 331 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 332 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 333 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 334 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 335 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 336 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 337 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 338 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 339 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 340 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 341 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 342 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 343 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 344 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 345 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 346 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 347 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 348 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 349 | #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ |
| mbed_official | 324:406fd2029f23 | 350 | defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) |
| mbed_official | 324:406fd2029f23 | 351 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 352 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
| mbed_official | 324:406fd2029f23 | 353 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 354 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
| mbed_official | 324:406fd2029f23 | 355 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 356 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 357 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 358 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 359 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 360 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 361 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 362 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 363 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 364 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 365 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 366 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 367 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 368 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 369 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 370 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 371 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 372 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 373 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 374 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 375 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 376 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
| mbed_official | 324:406fd2029f23 | 377 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 378 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 379 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 380 | #define FSL_FEATURE_MCG_HAS_FLL (0) |
| mbed_official | 324:406fd2029f23 | 381 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 382 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 383 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 384 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (0) |
| mbed_official | 324:406fd2029f23 | 385 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 386 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 387 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 388 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 389 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 390 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) |
| mbed_official | 324:406fd2029f23 | 391 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 392 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) |
| mbed_official | 324:406fd2029f23 | 393 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 394 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) |
| mbed_official | 324:406fd2029f23 | 395 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 396 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) |
| mbed_official | 324:406fd2029f23 | 397 | #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ |
| mbed_official | 324:406fd2029f23 | 398 | defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ |
| mbed_official | 324:406fd2029f23 | 399 | defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) |
| mbed_official | 324:406fd2029f23 | 400 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 401 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
| mbed_official | 324:406fd2029f23 | 402 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 403 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
| mbed_official | 324:406fd2029f23 | 404 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 405 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 406 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 407 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 408 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 409 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 410 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 411 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 412 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 413 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 414 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 415 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 416 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 417 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 418 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 419 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 420 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 421 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 422 | /* @brief TBD */ |
| mbed_official | 146:f64d43ff0c18 | 423 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 424 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 425 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
| mbed_official | 324:406fd2029f23 | 426 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 427 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 428 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 429 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 430 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 431 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 432 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 433 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 434 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 435 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 436 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 437 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 438 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 439 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 440 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 441 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 442 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 443 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 444 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 445 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 446 | #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 447 | defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 448 | defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 449 | defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 450 | defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 451 | defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 452 | defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 453 | defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 454 | defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) |
| mbed_official | 324:406fd2029f23 | 455 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 456 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) |
| mbed_official | 324:406fd2029f23 | 457 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 458 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) |
| mbed_official | 324:406fd2029f23 | 459 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 460 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 461 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 462 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 463 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 464 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 465 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 466 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 467 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 468 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 469 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 470 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 471 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 472 | #define FSL_FEATURE_MCG_HAS_LOLRE (0) |
| mbed_official | 324:406fd2029f23 | 473 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 474 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 475 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 476 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 477 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 478 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 479 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 480 | #define FSL_FEATURE_MCG_HAS_PLL (0) |
| mbed_official | 324:406fd2029f23 | 481 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 482 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 483 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 484 | #define FSL_FEATURE_MCG_HAS_FLL (0) |
| mbed_official | 324:406fd2029f23 | 485 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 486 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 487 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 488 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 489 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 490 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 491 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 492 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 493 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 494 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (0) |
| mbed_official | 324:406fd2029f23 | 495 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 496 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (0) |
| mbed_official | 324:406fd2029f23 | 497 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 498 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (1) |
| mbed_official | 324:406fd2029f23 | 499 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 500 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (1) |
| mbed_official | 324:406fd2029f23 | 501 | #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 502 | defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 503 | defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) |
| mbed_official | 324:406fd2029f23 | 504 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 505 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) |
| mbed_official | 324:406fd2029f23 | 506 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 507 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 508 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 509 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 510 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 511 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 512 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 513 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 514 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 515 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 516 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 517 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 518 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 519 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (0) |
| mbed_official | 324:406fd2029f23 | 520 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 521 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 522 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 523 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 524 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 525 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 526 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 527 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 528 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 529 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 530 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 531 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 532 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 533 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 534 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 535 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) |
| mbed_official | 324:406fd2029f23 | 536 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 537 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 538 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 539 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 540 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 541 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 542 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 543 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 544 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 545 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 546 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 547 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 548 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 549 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 550 | #elif defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \ |
| mbed_official | 324:406fd2029f23 | 551 | defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ |
| mbed_official | 324:406fd2029f23 | 552 | defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
| mbed_official | 324:406fd2029f23 | 553 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 554 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) |
| mbed_official | 324:406fd2029f23 | 555 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 556 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 557 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 558 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 559 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 560 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 561 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 562 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 563 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 564 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 565 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 566 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 567 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 568 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 569 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 570 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 571 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 572 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 573 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 574 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 575 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 576 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 577 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 578 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 579 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 580 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) |
| mbed_official | 324:406fd2029f23 | 581 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 582 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 583 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 584 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) |
| mbed_official | 324:406fd2029f23 | 585 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 586 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 587 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 588 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 589 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 590 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 591 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 592 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 593 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 594 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 595 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 596 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 597 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 598 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 599 | #elif defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || defined(CPU_MKV31F512VLL12) |
| mbed_official | 324:406fd2029f23 | 600 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 601 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (25) |
| mbed_official | 324:406fd2029f23 | 602 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 603 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) |
| mbed_official | 324:406fd2029f23 | 604 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 146:f64d43ff0c18 | 605 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) |
| mbed_official | 324:406fd2029f23 | 606 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 607 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 608 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 609 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 610 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 146:f64d43ff0c18 | 611 | #define FSL_FEATURE_MCG_HAS_IRC_48M (1) |
| mbed_official | 324:406fd2029f23 | 612 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 146:f64d43ff0c18 | 613 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 614 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 146:f64d43ff0c18 | 615 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 616 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 146:f64d43ff0c18 | 617 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 618 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 146:f64d43ff0c18 | 619 | #define FSL_FEATURE_MCG_USE_OSCSEL (1) |
| mbed_official | 324:406fd2029f23 | 620 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 146:f64d43ff0c18 | 621 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 622 | /* @brief TBD */ |
| mbed_official | 146:f64d43ff0c18 | 623 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 624 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 625 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 626 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 627 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 628 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 629 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 630 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 631 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 632 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 633 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 634 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 635 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 636 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 637 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 638 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 639 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 640 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 641 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 642 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 643 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 644 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 645 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 646 | #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \ |
| mbed_official | 324:406fd2029f23 | 647 | defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 648 | defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 649 | defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \ |
| mbed_official | 324:406fd2029f23 | 650 | defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15) |
| mbed_official | 324:406fd2029f23 | 651 | /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV] increased by one). */ |
| mbed_official | 324:406fd2029f23 | 652 | #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (8) |
| mbed_official | 324:406fd2029f23 | 653 | /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ |
| mbed_official | 324:406fd2029f23 | 654 | #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) |
| mbed_official | 324:406fd2029f23 | 655 | /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ |
| mbed_official | 324:406fd2029f23 | 656 | #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) |
| mbed_official | 324:406fd2029f23 | 657 | /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1] and C8[LOCRE1]). */ |
| mbed_official | 324:406fd2029f23 | 658 | #define FSL_FEATURE_MCG_HAS_RTC_32K (0) |
| mbed_official | 324:406fd2029f23 | 659 | /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 660 | #define FSL_FEATURE_MCG_HAS_PLL1 (0) |
| mbed_official | 324:406fd2029f23 | 661 | /* @brief Has 48MHz internal oscillator. */ |
| mbed_official | 324:406fd2029f23 | 662 | #define FSL_FEATURE_MCG_HAS_IRC_48M (0) |
| mbed_official | 324:406fd2029f23 | 663 | /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ |
| mbed_official | 324:406fd2029f23 | 664 | #define FSL_FEATURE_MCG_HAS_OSC1 (0) |
| mbed_official | 324:406fd2029f23 | 665 | /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ |
| mbed_official | 324:406fd2029f23 | 666 | #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) |
| mbed_official | 324:406fd2029f23 | 667 | /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ |
| mbed_official | 324:406fd2029f23 | 668 | #define FSL_FEATURE_MCG_HAS_LOLRE (1) |
| mbed_official | 324:406fd2029f23 | 669 | /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ |
| mbed_official | 324:406fd2029f23 | 670 | #define FSL_FEATURE_MCG_USE_OSCSEL (0) |
| mbed_official | 324:406fd2029f23 | 671 | /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ |
| mbed_official | 324:406fd2029f23 | 672 | #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) |
| mbed_official | 324:406fd2029f23 | 673 | /* @brief TBD */ |
| mbed_official | 324:406fd2029f23 | 674 | #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) |
| mbed_official | 324:406fd2029f23 | 675 | /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ |
| mbed_official | 324:406fd2029f23 | 676 | #define FSL_FEATURE_MCG_HAS_PLL (1) |
| mbed_official | 324:406fd2029f23 | 677 | /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ |
| mbed_official | 324:406fd2029f23 | 678 | #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) |
| mbed_official | 324:406fd2029f23 | 679 | /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ |
| mbed_official | 324:406fd2029f23 | 680 | #define FSL_FEATURE_MCG_HAS_FLL (1) |
| mbed_official | 324:406fd2029f23 | 681 | /* @brief Has PLL external to MCG (register C9). */ |
| mbed_official | 324:406fd2029f23 | 682 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) |
| mbed_official | 324:406fd2029f23 | 683 | /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ |
| mbed_official | 324:406fd2029f23 | 684 | #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) |
| mbed_official | 324:406fd2029f23 | 685 | /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ |
| mbed_official | 324:406fd2029f23 | 686 | #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) |
| mbed_official | 324:406fd2029f23 | 687 | /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ |
| mbed_official | 324:406fd2029f23 | 688 | #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) |
| mbed_official | 324:406fd2029f23 | 689 | /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ |
| mbed_official | 324:406fd2029f23 | 690 | #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) |
| mbed_official | 324:406fd2029f23 | 691 | /* @brief Has external clock monitor (register bit C6[CME]). */ |
| mbed_official | 324:406fd2029f23 | 692 | #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) |
| mbed_official | 324:406fd2029f23 | 693 | /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ |
| mbed_official | 324:406fd2029f23 | 694 | #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) |
| mbed_official | 324:406fd2029f23 | 695 | /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ |
| mbed_official | 324:406fd2029f23 | 696 | #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) |
| mbed_official | 146:f64d43ff0c18 | 697 | #else |
| mbed_official | 324:406fd2029f23 | 698 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 699 | #endif |
| mbed_official | 146:f64d43ff0c18 | 700 | |
| mbed_official | 324:406fd2029f23 | 701 | #endif /* __FSL_MCG_FEATURES_H__ */ |
| mbed_official | 324:406fd2029f23 | 702 | |
| mbed_official | 146:f64d43ff0c18 | 703 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 704 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 705 | ******************************************************************************/ |
