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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/lpuart/fsl_lpuart_features.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 324:406fd2029f23 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Version: rev. 1.0, 2014-05-14 |
| mbed_official | 324:406fd2029f23 | 4 | ** Build: b140515 |
| mbed_official | 324:406fd2029f23 | 5 | ** |
| mbed_official | 324:406fd2029f23 | 6 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 7 | ** Chip specific module features. |
| mbed_official | 324:406fd2029f23 | 8 | ** |
| mbed_official | 324:406fd2029f23 | 9 | ** Copyright: 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 10 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 13 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 16 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 19 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 20 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 21 | ** |
| mbed_official | 324:406fd2029f23 | 22 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 23 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 24 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 25 | ** |
| mbed_official | 324:406fd2029f23 | 26 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 27 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 28 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 29 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 30 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 31 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 32 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 34 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 35 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 36 | ** |
| mbed_official | 324:406fd2029f23 | 37 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 38 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 39 | ** |
| mbed_official | 324:406fd2029f23 | 40 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 41 | ** - rev. 1.0 (2014-05-14) |
| mbed_official | 324:406fd2029f23 | 42 | ** Customer release. |
| mbed_official | 324:406fd2029f23 | 43 | ** |
| mbed_official | 324:406fd2029f23 | 44 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 45 | */ |
| mbed_official | 324:406fd2029f23 | 46 | |
| mbed_official | 324:406fd2029f23 | 47 | #if !defined(__FSL_LPUART_FEATURES_H__) |
| mbed_official | 324:406fd2029f23 | 48 | #define __FSL_LPUART_FEATURES_H__ |
| mbed_official | 324:406fd2029f23 | 49 | |
| mbed_official | 324:406fd2029f23 | 50 | #if defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \ |
| mbed_official | 324:406fd2029f23 | 51 | defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ |
| mbed_official | 324:406fd2029f23 | 52 | defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK65FN2M0CAC18) || \ |
| mbed_official | 324:406fd2029f23 | 53 | defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || \ |
| mbed_official | 324:406fd2029f23 | 54 | defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F128VLH10) || \ |
| mbed_official | 324:406fd2029f23 | 55 | defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \ |
| mbed_official | 324:406fd2029f23 | 56 | defined(CPU_MKV31F512VLL12) |
| mbed_official | 324:406fd2029f23 | 57 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
| mbed_official | 324:406fd2029f23 | 58 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 324:406fd2029f23 | 59 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 60 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 61 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 62 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 324:406fd2029f23 | 63 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 64 | #define FSL_FEATURE_LPUART_HAS_FIFO (0) |
| mbed_official | 324:406fd2029f23 | 65 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
| mbed_official | 324:406fd2029f23 | 66 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 67 | /* @brief Infrared (modulation) is supported. */ |
| mbed_official | 324:406fd2029f23 | 68 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 69 | /* @brief 2 bits long stop bit is available. */ |
| mbed_official | 324:406fd2029f23 | 70 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 71 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 72 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 73 | /* @brief Baud rate fine adjustment is available. */ |
| mbed_official | 324:406fd2029f23 | 74 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 75 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 76 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 77 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 78 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 79 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 80 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 81 | /* @brief Peripheral type. */ |
| mbed_official | 324:406fd2029f23 | 82 | #define FSL_FEATURE_LPUART_IS_SCI (1) |
| mbed_official | 324:406fd2029f23 | 83 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 84 | #define FSL_FEATURE_LPUART_FIFO_SIZE (0) |
| mbed_official | 324:406fd2029f23 | 85 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 86 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) |
| mbed_official | 324:406fd2029f23 | 87 | /* @brief Maximal data width with parity bit. */ |
| mbed_official | 324:406fd2029f23 | 88 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 324:406fd2029f23 | 89 | /* @brief Supports two match addresses to filter incoming frames. */ |
| mbed_official | 324:406fd2029f23 | 90 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 324:406fd2029f23 | 91 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 92 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) |
| mbed_official | 324:406fd2029f23 | 93 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
| mbed_official | 324:406fd2029f23 | 94 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) |
| mbed_official | 324:406fd2029f23 | 95 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 96 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 324:406fd2029f23 | 97 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
| mbed_official | 324:406fd2029f23 | 98 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 99 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 100 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 101 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 102 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 103 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
| mbed_official | 324:406fd2029f23 | 104 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) |
| mbed_official | 324:406fd2029f23 | 105 | #elif defined(CPU_MKL03Z32CAF4) || defined(CPU_MKL03Z8VFG4) || defined(CPU_MKL03Z16VFG4) || defined(CPU_MKL03Z32VFG4) || \ |
| mbed_official | 324:406fd2029f23 | 106 | defined(CPU_MKL03Z8VFK4) || defined(CPU_MKL03Z16VFK4) || defined(CPU_MKL03Z32VFK4) |
| mbed_official | 324:406fd2029f23 | 107 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
| mbed_official | 324:406fd2029f23 | 108 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 324:406fd2029f23 | 109 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 110 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 111 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 112 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 324:406fd2029f23 | 113 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 114 | #define FSL_FEATURE_LPUART_HAS_FIFO (0) |
| mbed_official | 324:406fd2029f23 | 115 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
| mbed_official | 324:406fd2029f23 | 116 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 117 | /* @brief Infrared (modulation) is supported. */ |
| mbed_official | 324:406fd2029f23 | 118 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 119 | /* @brief 2 bits long stop bit is available. */ |
| mbed_official | 324:406fd2029f23 | 120 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 121 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 122 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 123 | /* @brief Baud rate fine adjustment is available. */ |
| mbed_official | 324:406fd2029f23 | 124 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 125 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 126 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 127 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 128 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 129 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 130 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 131 | /* @brief Peripheral type. */ |
| mbed_official | 324:406fd2029f23 | 132 | #define FSL_FEATURE_LPUART_IS_SCI (1) |
| mbed_official | 324:406fd2029f23 | 133 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 134 | #define FSL_FEATURE_LPUART_FIFO_SIZE (0) |
| mbed_official | 324:406fd2029f23 | 135 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 136 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) |
| mbed_official | 324:406fd2029f23 | 137 | /* @brief Maximal data width with parity bit. */ |
| mbed_official | 324:406fd2029f23 | 138 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 324:406fd2029f23 | 139 | /* @brief Supports two match addresses to filter incoming frames. */ |
| mbed_official | 324:406fd2029f23 | 140 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 324:406fd2029f23 | 141 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 142 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0) |
| mbed_official | 324:406fd2029f23 | 143 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
| mbed_official | 324:406fd2029f23 | 144 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) |
| mbed_official | 324:406fd2029f23 | 145 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 146 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 324:406fd2029f23 | 147 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
| mbed_official | 324:406fd2029f23 | 148 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 149 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 150 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 151 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 152 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 153 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
| mbed_official | 324:406fd2029f23 | 154 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) |
| mbed_official | 324:406fd2029f23 | 155 | #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 156 | defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 157 | defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 158 | defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \ |
| mbed_official | 324:406fd2029f23 | 159 | defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \ |
| mbed_official | 324:406fd2029f23 | 160 | defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 161 | defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 162 | defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \ |
| mbed_official | 324:406fd2029f23 | 163 | defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4) |
| mbed_official | 324:406fd2029f23 | 164 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ |
| mbed_official | 324:406fd2029f23 | 165 | #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 324:406fd2029f23 | 166 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 167 | #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 168 | /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 169 | #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 324:406fd2029f23 | 170 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 171 | #define FSL_FEATURE_LPUART_HAS_FIFO (0) |
| mbed_official | 324:406fd2029f23 | 172 | /* @brief Hardware flow control (RTS, CTS) is supported. */ |
| mbed_official | 324:406fd2029f23 | 173 | #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 174 | /* @brief Infrared (modulation) is supported. */ |
| mbed_official | 324:406fd2029f23 | 175 | #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 176 | /* @brief 2 bits long stop bit is available. */ |
| mbed_official | 324:406fd2029f23 | 177 | #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 178 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 179 | #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 180 | /* @brief Baud rate fine adjustment is available. */ |
| mbed_official | 324:406fd2029f23 | 181 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 182 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 183 | #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 184 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 185 | #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 186 | /* @brief Baud rate oversampling is available. */ |
| mbed_official | 324:406fd2029f23 | 187 | #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
| mbed_official | 324:406fd2029f23 | 188 | /* @brief Peripheral type. */ |
| mbed_official | 324:406fd2029f23 | 189 | #define FSL_FEATURE_LPUART_IS_SCI (1) |
| mbed_official | 324:406fd2029f23 | 190 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ |
| mbed_official | 324:406fd2029f23 | 191 | #define FSL_FEATURE_LPUART_FIFO_SIZE (0) |
| mbed_official | 324:406fd2029f23 | 192 | /* @brief Maximal data width without parity bit. */ |
| mbed_official | 324:406fd2029f23 | 193 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) |
| mbed_official | 324:406fd2029f23 | 194 | /* @brief Maximal data width with parity bit. */ |
| mbed_official | 324:406fd2029f23 | 195 | #define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 324:406fd2029f23 | 196 | /* @brief Supports two match addresses to filter incoming frames. */ |
| mbed_official | 324:406fd2029f23 | 197 | #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 324:406fd2029f23 | 198 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 199 | #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) |
| mbed_official | 324:406fd2029f23 | 200 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ |
| mbed_official | 324:406fd2029f23 | 201 | #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) |
| mbed_official | 324:406fd2029f23 | 202 | /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ |
| mbed_official | 324:406fd2029f23 | 203 | #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 324:406fd2029f23 | 204 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ |
| mbed_official | 324:406fd2029f23 | 205 | #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 206 | /* @brief Has improved smart card (ISO7816 protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 207 | #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 208 | /* @brief Has local operation network (CEA709.1-B protocol) support. */ |
| mbed_official | 324:406fd2029f23 | 209 | #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 324:406fd2029f23 | 210 | /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ |
| mbed_official | 324:406fd2029f23 | 211 | #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) |
| mbed_official | 324:406fd2029f23 | 212 | #else |
| mbed_official | 324:406fd2029f23 | 213 | #define MBED_NO_LPUART |
| mbed_official | 324:406fd2029f23 | 214 | #endif |
| mbed_official | 324:406fd2029f23 | 215 | |
| mbed_official | 324:406fd2029f23 | 216 | #endif /* __FSL_LPUART_FEATURES_H__ */ |
| mbed_official | 324:406fd2029f23 | 217 | |
| mbed_official | 324:406fd2029f23 | 218 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 219 | * EOF |
| mbed_official | 324:406fd2029f23 | 220 | ******************************************************************************/ |
