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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_FTM_HAL_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_FTM_HAL_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #include "fsl_device_registers.h"
mbed_official 146:f64d43ff0c18 34 #include "fsl_ftm_features.h"
mbed_official 146:f64d43ff0c18 35 #include <stdbool.h>
mbed_official 146:f64d43ff0c18 36 #include <assert.h>
mbed_official 146:f64d43ff0c18 37
mbed_official 146:f64d43ff0c18 38 /*!
mbed_official 146:f64d43ff0c18 39 * @addtogroup ftm_hal
mbed_official 146:f64d43ff0c18 40 * @{
mbed_official 146:f64d43ff0c18 41 */
mbed_official 146:f64d43ff0c18 42
mbed_official 146:f64d43ff0c18 43 /*******************************************************************************
mbed_official 146:f64d43ff0c18 44 * Definitions
mbed_official 146:f64d43ff0c18 45 ******************************************************************************/
mbed_official 146:f64d43ff0c18 46 #define HW_CHAN0 (0U) /*!< Channel number for CHAN0.*/
mbed_official 146:f64d43ff0c18 47 #define HW_CHAN1 (1U) /*!< Channel number for CHAN1.*/
mbed_official 146:f64d43ff0c18 48 #define HW_CHAN2 (2U) /*!< Channel number for CHAN2.*/
mbed_official 146:f64d43ff0c18 49 #define HW_CHAN3 (3U) /*!< Channel number for CHAN3.*/
mbed_official 146:f64d43ff0c18 50 #define HW_CHAN4 (4U) /*!< Channel number for CHAN4.*/
mbed_official 146:f64d43ff0c18 51 #define HW_CHAN5 (5U) /*!< Channel number for CHAN5.*/
mbed_official 146:f64d43ff0c18 52 #define HW_CHAN6 (6U) /*!< Channel number for CHAN6.*/
mbed_official 146:f64d43ff0c18 53 #define HW_CHAN7 (7U) /*!< Channel number for CHAN7.*/
mbed_official 146:f64d43ff0c18 54
mbed_official 146:f64d43ff0c18 55 #define FTM_COMBINE_CHAN_CTRL_WIDTH (8U)
mbed_official 324:406fd2029f23 56
mbed_official 146:f64d43ff0c18 57 /*! @brief FlexTimer clock source selection*/
mbed_official 146:f64d43ff0c18 58 typedef enum _ftm_clock_source
mbed_official 146:f64d43ff0c18 59 {
mbed_official 324:406fd2029f23 60 kClock_source_FTM_None = 0,
mbed_official 324:406fd2029f23 61 kClock_source_FTM_SystemClk,
mbed_official 324:406fd2029f23 62 kClock_source_FTM_FixedClk,
mbed_official 324:406fd2029f23 63 kClock_source_FTM_ExternalClk
mbed_official 146:f64d43ff0c18 64 }ftm_clock_source_t;
mbed_official 146:f64d43ff0c18 65
mbed_official 324:406fd2029f23 66 /*! @brief FlexTimer counting mode selection */
mbed_official 146:f64d43ff0c18 67 typedef enum _ftm_counting_mode
mbed_official 146:f64d43ff0c18 68 {
mbed_official 324:406fd2029f23 69 kCounting_FTM_UP = 0,
mbed_official 324:406fd2029f23 70 kCounting_FTM_UpDown
mbed_official 146:f64d43ff0c18 71 }ftm_counting_mode_t;
mbed_official 146:f64d43ff0c18 72
mbed_official 146:f64d43ff0c18 73 /*! @brief FlexTimer pre-scaler factor selection for the clock source*/
mbed_official 146:f64d43ff0c18 74 typedef enum _ftm_clock_ps
mbed_official 146:f64d43ff0c18 75 {
mbed_official 324:406fd2029f23 76 kFtmDividedBy1 = 0,
mbed_official 324:406fd2029f23 77 kFtmDividedBy2 ,
mbed_official 324:406fd2029f23 78 kFtmDividedBy4 ,
mbed_official 324:406fd2029f23 79 kFtmDividedBy8,
mbed_official 324:406fd2029f23 80 kFtmDividedBy16,
mbed_official 324:406fd2029f23 81 kFtmDividedBy32,
mbed_official 324:406fd2029f23 82 kFtmDividedBy64,
mbed_official 324:406fd2029f23 83 kFtmDividedBy128
mbed_official 146:f64d43ff0c18 84 }ftm_clock_ps_t;
mbed_official 146:f64d43ff0c18 85
mbed_official 146:f64d43ff0c18 86 /*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/
mbed_official 146:f64d43ff0c18 87 typedef enum _ftm_deadtime_ps
mbed_official 146:f64d43ff0c18 88 {
mbed_official 324:406fd2029f23 89 kFtmDivided1 = 1,
mbed_official 324:406fd2029f23 90 kFtmDivided4 = 2,
mbed_official 324:406fd2029f23 91 kFtmDivided16 = 3,
mbed_official 146:f64d43ff0c18 92 }ftm_deadtime_ps_t;
mbed_official 146:f64d43ff0c18 93
mbed_official 324:406fd2029f23 94 /*! @brief FlexTimer operation mode, capture, output, dual */
mbed_official 324:406fd2029f23 95 typedef enum _ftm_config_mode_t
mbed_official 324:406fd2029f23 96 {
mbed_official 146:f64d43ff0c18 97 kFtmInputCapture,
mbed_official 146:f64d43ff0c18 98 kFtmOutputCompare,
mbed_official 146:f64d43ff0c18 99 kFtmEdgeAlignedPWM,
mbed_official 146:f64d43ff0c18 100 kFtmCenterAlignedPWM,
mbed_official 146:f64d43ff0c18 101 kFtmCombinedPWM,
mbed_official 324:406fd2029f23 102 kFtmDualEdgeCapture
mbed_official 324:406fd2029f23 103 }ftm_config_mode_t;
mbed_official 146:f64d43ff0c18 104
mbed_official 146:f64d43ff0c18 105 /*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */
mbed_official 324:406fd2029f23 106 typedef enum _ftm_input_capture_edge_mode_t
mbed_official 324:406fd2029f23 107 {
mbed_official 146:f64d43ff0c18 108 kFtmRisingEdge = 0,
mbed_official 146:f64d43ff0c18 109 kFtmFallingEdge,
mbed_official 146:f64d43ff0c18 110 kFtmRisingAndFalling
mbed_official 324:406fd2029f23 111 }ftm_input_capture_edge_mode_t;
mbed_official 146:f64d43ff0c18 112
mbed_official 146:f64d43ff0c18 113 /*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/
mbed_official 324:406fd2029f23 114 typedef enum _ftm_output_compare_edge_mode_t
mbed_official 324:406fd2029f23 115 {
mbed_official 146:f64d43ff0c18 116 kFtmToggleOnMatch = 0,
mbed_official 146:f64d43ff0c18 117 kFtmClearOnMatch,
mbed_official 146:f64d43ff0c18 118 kFtmSetOnMatch
mbed_official 324:406fd2029f23 119 }ftm_output_compare_edge_mode_t;
mbed_official 146:f64d43ff0c18 120
mbed_official 146:f64d43ff0c18 121 /*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */
mbed_official 324:406fd2029f23 122 typedef enum _ftm_pwm_edge_mode_t
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 kFtmHighTrue = 0,
mbed_official 324:406fd2029f23 125 kFtmLowTrue
mbed_official 324:406fd2029f23 126 }ftm_pwm_edge_mode_t;
mbed_official 324:406fd2029f23 127
mbed_official 324:406fd2029f23 128 /*! @brief FlexTimer dual capture edge mode, one shot or continuous */
mbed_official 324:406fd2029f23 129 typedef enum _ftm_dual_capture_edge_mode_t
mbed_official 324:406fd2029f23 130 {
mbed_official 324:406fd2029f23 131 kFtmOneShout = 0,
mbed_official 324:406fd2029f23 132 kFtmContinuous
mbed_official 324:406fd2029f23 133 }ftm_dual_capture_edge_mode_t;
mbed_official 146:f64d43ff0c18 134
mbed_official 324:406fd2029f23 135 /*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */
mbed_official 324:406fd2029f23 136 typedef enum _ftm_quad_decode_mode_t
mbed_official 324:406fd2029f23 137 {
mbed_official 324:406fd2029f23 138 kFtmQuadPhaseEncode = 0,
mbed_official 324:406fd2029f23 139 kFtmQuadCountAndDir
mbed_official 324:406fd2029f23 140 }ftm_quad_decode_mode_t;
mbed_official 324:406fd2029f23 141
mbed_official 324:406fd2029f23 142 /*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */
mbed_official 324:406fd2029f23 143 typedef enum _ftm_quad_phase_polarity_t
mbed_official 324:406fd2029f23 144 {
mbed_official 324:406fd2029f23 145 kFtmQuadPhaseNormal = 0,
mbed_official 324:406fd2029f23 146 kFtmQuadPhaseInvert
mbed_official 324:406fd2029f23 147 }ftm_quad_phase_polarity_t;
mbed_official 146:f64d43ff0c18 148
mbed_official 146:f64d43ff0c18 149 /*! @brief FlexTimer edge mode*/
mbed_official 324:406fd2029f23 150 typedef union _ftm_edge_mode_t
mbed_official 324:406fd2029f23 151 {
mbed_official 146:f64d43ff0c18 152 ftm_input_capture_edge_mode_t input_capture_edge_mode;
mbed_official 146:f64d43ff0c18 153 ftm_output_compare_edge_mode_t output_compare_edge_mode;
mbed_official 146:f64d43ff0c18 154 ftm_pwm_edge_mode_t ftm_pwm_edge_mode;
mbed_official 146:f64d43ff0c18 155 ftm_dual_capture_edge_mode_t ftm_dual_capture_edge_mode;
mbed_official 324:406fd2029f23 156 }ftm_edge_mode_t;
mbed_official 146:f64d43ff0c18 157
mbed_official 324:406fd2029f23 158 /*!
mbed_official 324:406fd2029f23 159 * @brief FlexTimer driver PWM parameter
mbed_official 324:406fd2029f23 160 *
mbed_official 324:406fd2029f23 161 */
mbed_official 324:406fd2029f23 162 typedef struct FtmPwmParam
mbed_official 324:406fd2029f23 163 {
mbed_official 324:406fd2029f23 164 ftm_config_mode_t mode; /*!< FlexTimer PWM operation mode */
mbed_official 324:406fd2029f23 165 ftm_pwm_edge_mode_t edgeMode; /*!< PWM output mode */
mbed_official 324:406fd2029f23 166 uint32_t uFrequencyHZ; /*!< PWM period in Hz */
mbed_official 324:406fd2029f23 167 uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100
mbed_official 324:406fd2029f23 168 0=inactive signal(0% duty cycle)...
mbed_official 324:406fd2029f23 169 100=active signal (100% duty cycle). */
mbed_official 324:406fd2029f23 170 uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM.
mbed_official 324:406fd2029f23 171 Specifies the delay to the first edge in a PWM period.
mbed_official 324:406fd2029f23 172 If unsure please leave as 0, should be specified as
mbed_official 324:406fd2029f23 173 percentage of the PWM period*/
mbed_official 324:406fd2029f23 174 }ftm_pwm_param_t;
mbed_official 324:406fd2029f23 175
mbed_official 324:406fd2029f23 176 /*! @brief FlexTimer quadrature decode phase parameters */
mbed_official 324:406fd2029f23 177 typedef struct FtmPhaseParam
mbed_official 324:406fd2029f23 178 {
mbed_official 324:406fd2029f23 179 bool kFtmPhaseInputFilter; /*!< false: disable phase filter, true: enable phase filter */
mbed_official 324:406fd2029f23 180 uint32_t kFtmPhaseFilterVal; /*!< Filter value, used only if phase input filter is enabled */
mbed_official 324:406fd2029f23 181 ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert */
mbed_official 324:406fd2029f23 182 }ftm_phase_params_t;
mbed_official 324:406fd2029f23 183
mbed_official 146:f64d43ff0c18 184 /*FTM timer control*/
mbed_official 146:f64d43ff0c18 185 /*!
mbed_official 146:f64d43ff0c18 186 * @brief Sets the FTM clock source.
mbed_official 324:406fd2029f23 187 *
mbed_official 324:406fd2029f23 188 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 189 * @param clock The FTM peripheral clock selection\n
mbed_official 324:406fd2029f23 190 * bits - 00: No clock 01: system clock 10: fixed clock 11: External clock
mbed_official 146:f64d43ff0c18 191 */
mbed_official 324:406fd2029f23 192 static inline void FTM_HAL_SetClockSource(uint32_t ftmBaseAddr, ftm_clock_source_t clock)
mbed_official 146:f64d43ff0c18 193 {
mbed_official 324:406fd2029f23 194 BW_FTM_SC_CLKS(ftmBaseAddr, clock);
mbed_official 324:406fd2029f23 195 }
mbed_official 324:406fd2029f23 196
mbed_official 324:406fd2029f23 197 /*!
mbed_official 324:406fd2029f23 198 * @brief Reads the FTM clock source.
mbed_official 324:406fd2029f23 199 *
mbed_official 324:406fd2029f23 200 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 201 *
mbed_official 324:406fd2029f23 202 * @return The FTM clock source selection\n
mbed_official 324:406fd2029f23 203 * bits - 00: No clock 01: system clock 10: fixed clock 11:External clock
mbed_official 324:406fd2029f23 204 */
mbed_official 324:406fd2029f23 205 static inline uint8_t FTM_HAL_GetClockSource(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 206 {
mbed_official 324:406fd2029f23 207 return BR_FTM_SC_CLKS(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 208 }
mbed_official 146:f64d43ff0c18 209
mbed_official 146:f64d43ff0c18 210 /*!
mbed_official 146:f64d43ff0c18 211 * @brief Sets the FTM clock divider.
mbed_official 324:406fd2029f23 212 *
mbed_official 324:406fd2029f23 213 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 214 * @param ps The FTM peripheral clock pre-scale divider
mbed_official 146:f64d43ff0c18 215 */
mbed_official 324:406fd2029f23 216 static inline void FTM_HAL_SetClockPs(uint32_t ftmBaseAddr, ftm_clock_ps_t ps)
mbed_official 146:f64d43ff0c18 217 {
mbed_official 324:406fd2029f23 218 BW_FTM_SC_PS(ftmBaseAddr, ps);
mbed_official 324:406fd2029f23 219 }
mbed_official 324:406fd2029f23 220
mbed_official 324:406fd2029f23 221 /*!
mbed_official 324:406fd2029f23 222 * @brief Reads the FTM clock divider.
mbed_official 324:406fd2029f23 223 *
mbed_official 324:406fd2029f23 224 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 225 *
mbed_official 324:406fd2029f23 226 * @return The FTM clock pre-scale divider
mbed_official 324:406fd2029f23 227 */
mbed_official 324:406fd2029f23 228 static inline uint8_t FTM_HAL_GetClockPs(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 229 {
mbed_official 324:406fd2029f23 230 return BR_FTM_SC_PS(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 231 }
mbed_official 146:f64d43ff0c18 232
mbed_official 146:f64d43ff0c18 233 /*!
mbed_official 146:f64d43ff0c18 234 * @brief Enables the FTM peripheral timer overflow interrupt.
mbed_official 324:406fd2029f23 235 *
mbed_official 324:406fd2029f23 236 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 237 */
mbed_official 324:406fd2029f23 238 static inline void FTM_HAL_EnableTimerOverflowInt(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 239 {
mbed_official 324:406fd2029f23 240 HW_FTM_SC_SET(ftmBaseAddr, BM_FTM_SC_TOIE);
mbed_official 146:f64d43ff0c18 241 }
mbed_official 146:f64d43ff0c18 242
mbed_official 146:f64d43ff0c18 243 /*!
mbed_official 146:f64d43ff0c18 244 * @brief Disables the FTM peripheral timer overflow interrupt.
mbed_official 324:406fd2029f23 245 *
mbed_official 324:406fd2029f23 246 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 247 */
mbed_official 324:406fd2029f23 248 static inline void FTM_HAL_DisableTimerOverflowInt(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 249 {
mbed_official 324:406fd2029f23 250 HW_FTM_SC_CLR(ftmBaseAddr, BM_FTM_SC_TOIE);
mbed_official 324:406fd2029f23 251 }
mbed_official 324:406fd2029f23 252
mbed_official 324:406fd2029f23 253 /*!
mbed_official 324:406fd2029f23 254 * @brief Reads the bit that controls enabling the FTM timer overflow interrupt.
mbed_official 324:406fd2029f23 255 *
mbed_official 324:406fd2029f23 256 * @param baseAddr FTM module base address.
mbed_official 324:406fd2029f23 257 * @retval true if overflow interrupt is enabled, false if not
mbed_official 146:f64d43ff0c18 258 */
mbed_official 324:406fd2029f23 259 static inline bool FTM_HAL_IsOverflowIntEnabled(uint32_t baseAddr)
mbed_official 146:f64d43ff0c18 260 {
mbed_official 324:406fd2029f23 261 return (bool)(BR_FTM_SC_TOIE(baseAddr));
mbed_official 324:406fd2029f23 262 }
mbed_official 324:406fd2029f23 263
mbed_official 324:406fd2029f23 264 /*!
mbed_official 324:406fd2029f23 265 * @brief Clears the timer overflow interrupt flag.
mbed_official 324:406fd2029f23 266 *
mbed_official 324:406fd2029f23 267 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 268 */
mbed_official 324:406fd2029f23 269 static inline void FTM_HAL_ClearTimerOverflow(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 270 {
mbed_official 324:406fd2029f23 271 BW_FTM_SC_TOF(ftmBaseAddr, 0);
mbed_official 146:f64d43ff0c18 272 }
mbed_official 146:f64d43ff0c18 273
mbed_official 146:f64d43ff0c18 274 /*!
mbed_official 146:f64d43ff0c18 275 * @brief Returns the FTM peripheral timer overflow interrupt flag.
mbed_official 324:406fd2029f23 276 *
mbed_official 324:406fd2029f23 277 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 278 * @retval true if overflow, false if not
mbed_official 146:f64d43ff0c18 279 */
mbed_official 324:406fd2029f23 280 static inline bool FTM_HAL_HasTimerOverflowed(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 281 {
mbed_official 324:406fd2029f23 282 return BR_FTM_SC_TOF(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 283 }
mbed_official 146:f64d43ff0c18 284
mbed_official 146:f64d43ff0c18 285 /*!
mbed_official 146:f64d43ff0c18 286 * @brief Sets the FTM center-aligned PWM select.
mbed_official 324:406fd2029f23 287 *
mbed_official 324:406fd2029f23 288 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 289 * @param mode 1:upcounting mode 0:up_down counting mode
mbed_official 146:f64d43ff0c18 290 */
mbed_official 324:406fd2029f23 291 static inline void FTM_HAL_SetCpwms(uint32_t ftmBaseAddr, uint8_t mode)
mbed_official 146:f64d43ff0c18 292 {
mbed_official 324:406fd2029f23 293 assert(mode < 2);
mbed_official 324:406fd2029f23 294 BW_FTM_SC_CPWMS(ftmBaseAddr, mode);
mbed_official 146:f64d43ff0c18 295 }
mbed_official 146:f64d43ff0c18 296
mbed_official 146:f64d43ff0c18 297 /*!
mbed_official 146:f64d43ff0c18 298 * @brief Sets the FTM peripheral current counter value.
mbed_official 324:406fd2029f23 299 *
mbed_official 324:406fd2029f23 300 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 301 * @param val FTM timer counter value to be set
mbed_official 146:f64d43ff0c18 302 */
mbed_official 324:406fd2029f23 303 static inline void FTM_HAL_SetCounter(uint32_t ftmBaseAddr,uint16_t val)
mbed_official 146:f64d43ff0c18 304 {
mbed_official 324:406fd2029f23 305 BW_FTM_CNT_COUNT(ftmBaseAddr, val);
mbed_official 146:f64d43ff0c18 306 }
mbed_official 146:f64d43ff0c18 307
mbed_official 146:f64d43ff0c18 308 /*!
mbed_official 146:f64d43ff0c18 309 * @brief Returns the FTM peripheral current counter value.
mbed_official 324:406fd2029f23 310 *
mbed_official 324:406fd2029f23 311 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 312 * @retval current FTM timer counter value
mbed_official 146:f64d43ff0c18 313 */
mbed_official 324:406fd2029f23 314 static inline uint16_t FTM_HAL_GetCounter(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 315 {
mbed_official 324:406fd2029f23 316 return BR_FTM_CNT_COUNT(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 317 }
mbed_official 146:f64d43ff0c18 318
mbed_official 146:f64d43ff0c18 319 /*!
mbed_official 146:f64d43ff0c18 320 * @brief Sets the FTM peripheral timer modulo value.
mbed_official 324:406fd2029f23 321 *
mbed_official 324:406fd2029f23 322 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 323 * @param val The value to be set to the timer modulo
mbed_official 146:f64d43ff0c18 324 */
mbed_official 324:406fd2029f23 325 static inline void FTM_HAL_SetMod(uint32_t ftmBaseAddr, uint16_t val)
mbed_official 146:f64d43ff0c18 326 {
mbed_official 324:406fd2029f23 327 BW_FTM_MOD_MOD(ftmBaseAddr, val);
mbed_official 146:f64d43ff0c18 328 }
mbed_official 146:f64d43ff0c18 329
mbed_official 146:f64d43ff0c18 330 /*!
mbed_official 146:f64d43ff0c18 331 * @brief Returns the FTM peripheral counter modulo value.
mbed_official 324:406fd2029f23 332 *
mbed_official 324:406fd2029f23 333 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 334 * @retval FTM timer modulo value
mbed_official 146:f64d43ff0c18 335 */
mbed_official 324:406fd2029f23 336 static inline uint16_t FTM_HAL_GetMod(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 337 {
mbed_official 324:406fd2029f23 338 return BR_FTM_MOD_MOD(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 339 }
mbed_official 146:f64d43ff0c18 340
mbed_official 146:f64d43ff0c18 341 /*!
mbed_official 146:f64d43ff0c18 342 * @brief Sets the FTM peripheral timer counter initial value.
mbed_official 324:406fd2029f23 343 *
mbed_official 324:406fd2029f23 344 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 345 * @param val initial value to be set
mbed_official 146:f64d43ff0c18 346 */
mbed_official 324:406fd2029f23 347 static inline void FTM_HAL_SetCounterInitVal(uint32_t ftmBaseAddr, uint16_t val)
mbed_official 146:f64d43ff0c18 348 {
mbed_official 324:406fd2029f23 349 BW_FTM_CNTIN_INIT(ftmBaseAddr, val & BM_FTM_CNTIN_INIT);
mbed_official 146:f64d43ff0c18 350 }
mbed_official 146:f64d43ff0c18 351
mbed_official 146:f64d43ff0c18 352 /*!
mbed_official 146:f64d43ff0c18 353 * @brief Returns the FTM peripheral counter initial value.
mbed_official 324:406fd2029f23 354 *
mbed_official 324:406fd2029f23 355 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 356 * @retval FTM timer counter initial value
mbed_official 146:f64d43ff0c18 357 */
mbed_official 324:406fd2029f23 358 static inline uint16_t FTM_HAL_GetCounterInitVal(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 359 {
mbed_official 324:406fd2029f23 360 return BR_FTM_CNTIN_INIT(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 361 }
mbed_official 146:f64d43ff0c18 362
mbed_official 324:406fd2029f23 363 /*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */
mbed_official 146:f64d43ff0c18 364 /*!
mbed_official 146:f64d43ff0c18 365 * @brief Sets the FTM peripheral timer channel mode.
mbed_official 324:406fd2029f23 366 *
mbed_official 324:406fd2029f23 367 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 368 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 369 * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11
mbed_official 146:f64d43ff0c18 370 */
mbed_official 324:406fd2029f23 371 static inline void FTM_HAL_SetChnMSnBAMode(uint32_t ftmBaseAddr, uint8_t channel, uint8_t selection)
mbed_official 146:f64d43ff0c18 372 {
mbed_official 324:406fd2029f23 373 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 374 BW_FTM_CnSC_MSA(ftmBaseAddr, channel, selection & 1);
mbed_official 324:406fd2029f23 375 BW_FTM_CnSC_MSB(ftmBaseAddr, channel, selection & 2 ? 1 : 0);
mbed_official 146:f64d43ff0c18 376 }
mbed_official 146:f64d43ff0c18 377
mbed_official 146:f64d43ff0c18 378 /*!
mbed_official 146:f64d43ff0c18 379 * @brief Sets the FTM peripheral timer channel edge level.
mbed_official 324:406fd2029f23 380 *
mbed_official 324:406fd2029f23 381 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 382 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 383 * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11
mbed_official 146:f64d43ff0c18 384 */
mbed_official 324:406fd2029f23 385 static inline void FTM_HAL_SetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel, uint8_t level)
mbed_official 146:f64d43ff0c18 386 {
mbed_official 324:406fd2029f23 387 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 388 BW_FTM_CnSC_ELSA(ftmBaseAddr, channel, level & 1 ? 1 : 0);
mbed_official 324:406fd2029f23 389 BW_FTM_CnSC_ELSB(ftmBaseAddr, channel, level & 2 ? 1 : 0);
mbed_official 146:f64d43ff0c18 390 }
mbed_official 146:f64d43ff0c18 391
mbed_official 146:f64d43ff0c18 392 /*!
mbed_official 146:f64d43ff0c18 393 * @brief Gets the FTM peripheral timer channel mode.
mbed_official 324:406fd2029f23 394 *
mbed_official 324:406fd2029f23 395 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 396 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 397 * @retval The MSnB:MSnA mode value, will be 00,01, 10, 11
mbed_official 146:f64d43ff0c18 398 */
mbed_official 324:406fd2029f23 399 static inline uint8_t FTM_HAL_GetChnMode(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 400 {
mbed_official 324:406fd2029f23 401 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 402 return (BR_FTM_CnSC_MSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_MSB(ftmBaseAddr, channel) << 1));
mbed_official 146:f64d43ff0c18 403 }
mbed_official 146:f64d43ff0c18 404
mbed_official 146:f64d43ff0c18 405 /*!
mbed_official 146:f64d43ff0c18 406 * @brief Gets the FTM peripheral timer channel edge level.
mbed_official 324:406fd2029f23 407 *
mbed_official 324:406fd2029f23 408 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 409 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 410 * @retval The ELSnB:ELSnA mode value, will be 00,01, 10, 11
mbed_official 146:f64d43ff0c18 411 */
mbed_official 324:406fd2029f23 412 static inline uint8_t FTM_HAL_GetChnEdgeLevel(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 413 {
mbed_official 324:406fd2029f23 414 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 415 return (BR_FTM_CnSC_ELSA(ftmBaseAddr, channel)|| (BR_FTM_CnSC_ELSB(ftmBaseAddr, channel) << 1));
mbed_official 146:f64d43ff0c18 416 }
mbed_official 146:f64d43ff0c18 417
mbed_official 146:f64d43ff0c18 418 /*!
mbed_official 146:f64d43ff0c18 419 * @brief Enables or disables the FTM peripheral timer channel DMA.
mbed_official 324:406fd2029f23 420 *
mbed_official 324:406fd2029f23 421 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 422 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 423 * @param val enable or disable
mbed_official 146:f64d43ff0c18 424 */
mbed_official 324:406fd2029f23 425 static inline void FTM_HAL_SetChnDmaCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
mbed_official 146:f64d43ff0c18 426 {
mbed_official 324:406fd2029f23 427 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 428 BW_FTM_CnSC_DMA(ftmBaseAddr, channel,(val? 1 : 0));
mbed_official 146:f64d43ff0c18 429 }
mbed_official 146:f64d43ff0c18 430
mbed_official 146:f64d43ff0c18 431 /*!
mbed_official 146:f64d43ff0c18 432 * @brief Returns whether the FTM peripheral timer channel DMA is enabled.
mbed_official 324:406fd2029f23 433 *
mbed_official 324:406fd2029f23 434 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 435 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 436 * @retval true if enabled, false if disabled
mbed_official 146:f64d43ff0c18 437 */
mbed_official 324:406fd2029f23 438 static inline bool FTM_HAL_IsChnDma(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 439 {
mbed_official 324:406fd2029f23 440 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 441 return (BR_FTM_CnSC_DMA(ftmBaseAddr, channel) ? true : false);
mbed_official 146:f64d43ff0c18 442 }
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 /*!
mbed_official 146:f64d43ff0c18 445 * @brief Enables the FTM peripheral timer channel(n) interrupt.
mbed_official 324:406fd2029f23 446 *
mbed_official 324:406fd2029f23 447 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 448 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 449 */
mbed_official 324:406fd2029f23 450 static inline void FTM_HAL_EnableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 451 {
mbed_official 324:406fd2029f23 452 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 453 BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 1);
mbed_official 146:f64d43ff0c18 454 }
mbed_official 146:f64d43ff0c18 455 /*!
mbed_official 146:f64d43ff0c18 456 * @brief Disables the FTM peripheral timer channel(n) interrupt.
mbed_official 324:406fd2029f23 457 *
mbed_official 324:406fd2029f23 458 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 459 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 460 */
mbed_official 324:406fd2029f23 461 static inline void FTM_HAL_DisableChnInt(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 462 {
mbed_official 324:406fd2029f23 463 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 464 BW_FTM_CnSC_CHIE(ftmBaseAddr, channel, 0);
mbed_official 146:f64d43ff0c18 465 }
mbed_official 146:f64d43ff0c18 466
mbed_official 146:f64d43ff0c18 467 /*!
mbed_official 146:f64d43ff0c18 468 * @brief Returns whether any event for the FTM peripheral timer channel has occurred.
mbed_official 324:406fd2029f23 469 *
mbed_official 324:406fd2029f23 470 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 471 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 472 * @retval true if event occurred, false otherwise.
mbed_official 146:f64d43ff0c18 473 */
mbed_official 324:406fd2029f23 474 static inline bool FTM_HAL_HasChnEventOccurred(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 475 {
mbed_official 324:406fd2029f23 476 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 477 return (BR_FTM_CnSC_CHF(ftmBaseAddr, channel)) ? true : false;
mbed_official 146:f64d43ff0c18 478 }
mbed_official 146:f64d43ff0c18 479
mbed_official 146:f64d43ff0c18 480 /*FTM channel control*/
mbed_official 146:f64d43ff0c18 481 /*!
mbed_official 146:f64d43ff0c18 482 * @brief Sets the FTM peripheral timer channel counter value.
mbed_official 324:406fd2029f23 483 *
mbed_official 324:406fd2029f23 484 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 485 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 486 * @param val counter value to be set
mbed_official 146:f64d43ff0c18 487 */
mbed_official 324:406fd2029f23 488 static inline void FTM_HAL_SetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
mbed_official 146:f64d43ff0c18 489 {
mbed_official 324:406fd2029f23 490 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 491 HW_FTM_CnV_WR(ftmBaseAddr, channel, val);
mbed_official 146:f64d43ff0c18 492 }
mbed_official 146:f64d43ff0c18 493
mbed_official 146:f64d43ff0c18 494 /*!
mbed_official 146:f64d43ff0c18 495 * @brief Gets the FTM peripheral timer channel counter value.
mbed_official 324:406fd2029f23 496 *
mbed_official 324:406fd2029f23 497 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 498 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 499 * @retval val return current channel counter value
mbed_official 146:f64d43ff0c18 500 */
mbed_official 324:406fd2029f23 501 static inline uint16_t FTM_HAL_GetChnCountVal(uint32_t ftmBaseAddr, uint8_t channel, uint16_t val)
mbed_official 146:f64d43ff0c18 502 {
mbed_official 324:406fd2029f23 503 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 504 return BR_FTM_CnV_VAL(ftmBaseAddr, channel);
mbed_official 146:f64d43ff0c18 505 }
mbed_official 146:f64d43ff0c18 506
mbed_official 146:f64d43ff0c18 507 /*!
mbed_official 146:f64d43ff0c18 508 * @brief Gets the FTM peripheral timer channel event status.
mbed_official 324:406fd2029f23 509 *
mbed_official 324:406fd2029f23 510 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 511 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 512 * @retval val return current channel event status value
mbed_official 146:f64d43ff0c18 513 */
mbed_official 324:406fd2029f23 514 static inline uint32_t FTM_HAL_GetChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 515 {
mbed_official 324:406fd2029f23 516 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 517 return (HW_FTM_STATUS_RD(ftmBaseAddr)&(1U << channel)) ? true : false;
mbed_official 324:406fd2029f23 518 /*return BR_FTM_STATUS(ftmBaseAddr, channel);*/
mbed_official 146:f64d43ff0c18 519 }
mbed_official 146:f64d43ff0c18 520
mbed_official 146:f64d43ff0c18 521 /*!
mbed_official 146:f64d43ff0c18 522 * @brief Clears the FTM peripheral timer all channel event status.
mbed_official 324:406fd2029f23 523 *
mbed_official 324:406fd2029f23 524 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 525 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 526 * @retval val return current channel counter value
mbed_official 146:f64d43ff0c18 527 */
mbed_official 324:406fd2029f23 528 static inline void FTM_HAL_ClearChnEventStatus(uint32_t ftmBaseAddr, uint8_t channel)
mbed_official 146:f64d43ff0c18 529 {
mbed_official 324:406fd2029f23 530 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 531 HW_FTM_STATUS_CLR(ftmBaseAddr, 1U << channel);
mbed_official 146:f64d43ff0c18 532 }
mbed_official 146:f64d43ff0c18 533
mbed_official 146:f64d43ff0c18 534 /*!
mbed_official 146:f64d43ff0c18 535 * @brief Sets the FTM peripheral timer channel output mask.
mbed_official 324:406fd2029f23 536 *
mbed_official 324:406fd2029f23 537 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 538 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 539 * @param mask mask to be set 0 or 1, unmasked or masked
mbed_official 146:f64d43ff0c18 540 */
mbed_official 324:406fd2029f23 541 static inline void FTM_HAL_SetChnOutputMask(uint32_t ftmBaseAddr, uint8_t channel, bool mask)
mbed_official 146:f64d43ff0c18 542 {
mbed_official 324:406fd2029f23 543 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 544 mask? HW_FTM_OUTMASK_SET(ftmBaseAddr, 1U << channel) : HW_FTM_OUTMASK_CLR(ftmBaseAddr, 1U << channel);
mbed_official 324:406fd2029f23 545 /* BW_FTM_OUTMASK_CHnOM(ftmBaseAddr, channel,mask); */
mbed_official 146:f64d43ff0c18 546 }
mbed_official 146:f64d43ff0c18 547
mbed_official 146:f64d43ff0c18 548 /*!
mbed_official 146:f64d43ff0c18 549 * @brief Sets the FTM peripheral timer channel output initial state 0 or 1.
mbed_official 324:406fd2029f23 550 *
mbed_official 324:406fd2029f23 551 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 552 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 553 * @param state counter value to be set 0 or 1
mbed_official 146:f64d43ff0c18 554 */
mbed_official 324:406fd2029f23 555 static inline void FTM_HAL_SetChnOutputInitState(uint32_t ftmBaseAddr, uint8_t channel, uint8_t state)
mbed_official 146:f64d43ff0c18 556 {
mbed_official 324:406fd2029f23 557 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 558 HW_FTM_OUTINIT_CLR(ftmBaseAddr, 1U << channel);
mbed_official 324:406fd2029f23 559 HW_FTM_OUTINIT_SET(ftmBaseAddr, (uint8_t)(state << channel));
mbed_official 146:f64d43ff0c18 560 }
mbed_official 146:f64d43ff0c18 561
mbed_official 146:f64d43ff0c18 562 /*!
mbed_official 146:f64d43ff0c18 563 * @brief Sets the FTM peripheral timer channel output polarity.
mbed_official 324:406fd2029f23 564 *
mbed_official 324:406fd2029f23 565 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 566 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 567 * @param pol polarity to be set 0 or 1
mbed_official 146:f64d43ff0c18 568 */
mbed_official 324:406fd2029f23 569 static inline void FTM_HAL_SetChnOutputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
mbed_official 146:f64d43ff0c18 570 {
mbed_official 324:406fd2029f23 571 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 572 HW_FTM_POL_CLR(ftmBaseAddr, 1U << channel);
mbed_official 324:406fd2029f23 573 HW_FTM_POL_SET(ftmBaseAddr, (uint8_t)(pol << channel));
mbed_official 146:f64d43ff0c18 574 }
mbed_official 146:f64d43ff0c18 575 /*!
mbed_official 146:f64d43ff0c18 576 * @brief Sets the FTM peripheral timer channel input polarity.
mbed_official 324:406fd2029f23 577 *
mbed_official 324:406fd2029f23 578 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 579 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 580 * @param pol polarity to be set, 0: active high, 1:active low
mbed_official 146:f64d43ff0c18 581 */
mbed_official 324:406fd2029f23 582 static inline void FTM_HAL_SetChnFaultInputPolarity(uint32_t ftmBaseAddr, uint8_t channel, uint8_t pol)
mbed_official 146:f64d43ff0c18 583 {
mbed_official 324:406fd2029f23 584 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 585 HW_FTM_FLTPOL_CLR(ftmBaseAddr, 1U << channel);
mbed_official 324:406fd2029f23 586 HW_FTM_FLTPOL_SET(ftmBaseAddr, (uint8_t)(pol<<channel));
mbed_official 146:f64d43ff0c18 587 }
mbed_official 146:f64d43ff0c18 588
mbed_official 146:f64d43ff0c18 589
mbed_official 146:f64d43ff0c18 590 /*Feature mode selection HAL*/
mbed_official 146:f64d43ff0c18 591 /*FTM fault control*/
mbed_official 146:f64d43ff0c18 592 /*!
mbed_official 146:f64d43ff0c18 593 * @brief Enables the FTM peripheral timer fault interrupt.
mbed_official 324:406fd2029f23 594 *
mbed_official 324:406fd2029f23 595 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 596 */
mbed_official 324:406fd2029f23 597 static inline void FTM_HAL_EnableFaultInt(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 598 {
mbed_official 324:406fd2029f23 599 BW_FTM_MODE_FAULTIE(ftmBaseAddr, 1);
mbed_official 146:f64d43ff0c18 600 }
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 /*!
mbed_official 146:f64d43ff0c18 603 * @brief Disables the FTM peripheral timer fault interrupt.
mbed_official 324:406fd2029f23 604 *
mbed_official 324:406fd2029f23 605 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 606 */
mbed_official 324:406fd2029f23 607 static inline void FTM_HAL_DisableFaultInt(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 608 {
mbed_official 324:406fd2029f23 609 BW_FTM_MODE_FAULTIE(ftmBaseAddr, 0);
mbed_official 146:f64d43ff0c18 610 }
mbed_official 146:f64d43ff0c18 611
mbed_official 146:f64d43ff0c18 612 /*!
mbed_official 324:406fd2029f23 613 * @brief Defines the FTM fault control mode.
mbed_official 324:406fd2029f23 614 *
mbed_official 324:406fd2029f23 615 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 616 * @param mode, valid options are 1, 2, 3, 4
mbed_official 146:f64d43ff0c18 617 */
mbed_official 324:406fd2029f23 618 static inline void FTM_HAL_SetFaultControlMode(uint32_t ftmBaseAddr, uint8_t mode)
mbed_official 146:f64d43ff0c18 619 {
mbed_official 324:406fd2029f23 620 BW_FTM_MODE_FAULTM(ftmBaseAddr, mode);
mbed_official 146:f64d43ff0c18 621 }
mbed_official 146:f64d43ff0c18 622
mbed_official 146:f64d43ff0c18 623 /*!
mbed_official 324:406fd2029f23 624 * @brief Enables or disables the FTM peripheral timer capture test mode.
mbed_official 324:406fd2029f23 625 *
mbed_official 324:406fd2029f23 626 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 627 * @param enable true to enable capture test mode, false to disable
mbed_official 146:f64d43ff0c18 628 */
mbed_official 324:406fd2029f23 629 static inline void FTM_HAL_SetCaptureTestCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 630 {
mbed_official 324:406fd2029f23 631 BW_FTM_MODE_CAPTEST(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 632 }
mbed_official 146:f64d43ff0c18 633
mbed_official 146:f64d43ff0c18 634 /*!
mbed_official 324:406fd2029f23 635 * @brief Enables or disables the FTM write protection.
mbed_official 324:406fd2029f23 636 *
mbed_official 324:406fd2029f23 637 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 638 * @param enable true: Write-protection is enabled, false: Write-protection is disabled
mbed_official 146:f64d43ff0c18 639 */
mbed_official 324:406fd2029f23 640 static inline void FTM_HAL_SetWriteProtectionCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 641 {
mbed_official 324:406fd2029f23 642 enable ? BW_FTM_FMS_WPEN(ftmBaseAddr, 1) : BW_FTM_MODE_WPDIS(ftmBaseAddr, 1);
mbed_official 146:f64d43ff0c18 643 }
mbed_official 146:f64d43ff0c18 644
mbed_official 146:f64d43ff0c18 645 /*!
mbed_official 146:f64d43ff0c18 646 * @brief Enables the FTM peripheral timer group.
mbed_official 324:406fd2029f23 647 *
mbed_official 324:406fd2029f23 648 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 649 * @param enable true: all registers including FTM-specific registers are available
mbed_official 324:406fd2029f23 650 * false: only the TPM-compatible registers are available
mbed_official 146:f64d43ff0c18 651 */
mbed_official 324:406fd2029f23 652 static inline void FTM_HAL_Enable(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 653 {
mbed_official 324:406fd2029f23 654 assert(BR_FTM_MODE_WPDIS(ftmBaseAddr));
mbed_official 324:406fd2029f23 655 BW_FTM_MODE_FTMEN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 656 }
mbed_official 146:f64d43ff0c18 657
mbed_official 146:f64d43ff0c18 658 /*!
mbed_official 324:406fd2029f23 659 * @brief Initializes the channels output.
mbed_official 324:406fd2029f23 660 *
mbed_official 324:406fd2029f23 661 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 662 * @param enable true: the channels output is initialized according to the state of OUTINIT reg
mbed_official 324:406fd2029f23 663 * false: has no effect
mbed_official 146:f64d43ff0c18 664 */
mbed_official 324:406fd2029f23 665 static inline void FTM_HAL_SetInitChnOutputCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 666 {
mbed_official 324:406fd2029f23 667 BW_FTM_MODE_INIT(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 668 }
mbed_official 146:f64d43ff0c18 669
mbed_official 146:f64d43ff0c18 670 /*!
mbed_official 146:f64d43ff0c18 671 * @brief Sets the FTM peripheral timer sync mode.
mbed_official 324:406fd2029f23 672 *
mbed_official 324:406fd2029f23 673 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 674 * @param enable true: no restriction both software and hardware triggers can be used\n
mbed_official 324:406fd2029f23 675 * false: software trigger can only be used for MOD and CnV synch, hardware trigger
mbed_official 324:406fd2029f23 676 * only for OUTMASK and FTM counter synch.
mbed_official 146:f64d43ff0c18 677 */
mbed_official 324:406fd2029f23 678 static inline void FTM_HAL_SetPwmSyncMode(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 679 {
mbed_official 324:406fd2029f23 680 BW_FTM_MODE_PWMSYNC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 681 }
mbed_official 146:f64d43ff0c18 682
mbed_official 146:f64d43ff0c18 683 /*FTM synchronization control*/
mbed_official 146:f64d43ff0c18 684 /*!
mbed_official 324:406fd2029f23 685 * @brief Enables or disables the FTM peripheral timer software trigger.
mbed_official 324:406fd2029f23 686 *
mbed_official 324:406fd2029f23 687 * @param ftmBaseAddr The FTM base address.
mbed_official 324:406fd2029f23 688 * @param enable true: software trigger is selected, false: software trigger is not selected
mbed_official 146:f64d43ff0c18 689 */
mbed_official 324:406fd2029f23 690 static inline void FTM_HAL_SetSoftwareTriggerCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 691 {
mbed_official 324:406fd2029f23 692 BW_FTM_SYNC_SWSYNC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 693 }
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 /*!
mbed_official 146:f64d43ff0c18 696 * @brief Sets the FTM peripheral timer hardware trigger.
mbed_official 324:406fd2029f23 697 *
mbed_official 324:406fd2029f23 698 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 699 * @param trigger_num 0, 1, 2 for trigger0, trigger1 and trigger3
mbed_official 324:406fd2029f23 700 * @param enable true: enable hardware trigger from field trigger_num for PWM synch
mbed_official 324:406fd2029f23 701 * false: disable hardware trigger from field trigger_num for PWM synch
mbed_official 146:f64d43ff0c18 702 */
mbed_official 324:406fd2029f23 703 void FTM_HAL_SetHardwareTrigger(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable);
mbed_official 146:f64d43ff0c18 704
mbed_official 146:f64d43ff0c18 705 /*!
mbed_official 324:406fd2029f23 706 * @brief Determines when the OUTMASK register is updated with the value of its buffer.
mbed_official 324:406fd2029f23 707 *
mbed_official 324:406fd2029f23 708 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 709 * @param enable true if OUTMASK register is updated only by PWM sync\n
mbed_official 324:406fd2029f23 710 * false if OUTMASK register is updated in all rising edges of the system clock
mbed_official 146:f64d43ff0c18 711 */
mbed_official 324:406fd2029f23 712 static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 713 {
mbed_official 324:406fd2029f23 714 BW_FTM_SYNC_SYNCHOM(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 715 }
mbed_official 146:f64d43ff0c18 716
mbed_official 146:f64d43ff0c18 717 /*!
mbed_official 324:406fd2029f23 718 * @brief Determines if the FTM counter is re-initialized when the selected trigger for
mbed_official 324:406fd2029f23 719 * synchronization is detected.
mbed_official 324:406fd2029f23 720 *
mbed_official 324:406fd2029f23 721 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 722 * @param enable True to update FTM counter when triggered , false to count normally
mbed_official 146:f64d43ff0c18 723 */
mbed_official 324:406fd2029f23 724 static inline void FTM_HAL_SetCountReinitSyncCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 725 {
mbed_official 324:406fd2029f23 726 BW_FTM_SYNC_REINIT(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 727 }
mbed_official 324:406fd2029f23 728
mbed_official 324:406fd2029f23 729 /*!
mbed_official 324:406fd2029f23 730 * @brief Enables or disables the FTM peripheral timer maximum loading points.
mbed_official 324:406fd2029f23 731 *
mbed_official 324:406fd2029f23 732 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 733 * @param enable True to enable maximum loading point, false to disable
mbed_official 324:406fd2029f23 734 */
mbed_official 324:406fd2029f23 735 static inline void FTM_HAL_SetMaxLoadingCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 736 {
mbed_official 324:406fd2029f23 737 BW_FTM_SYNC_CNTMAX(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 738 }
mbed_official 146:f64d43ff0c18 739 /*!
mbed_official 324:406fd2029f23 740 * @brief Enables or disables the FTM peripheral timer minimum loading points.
mbed_official 324:406fd2029f23 741 *
mbed_official 324:406fd2029f23 742 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 743 * @param enable True to enable minimum loading point, false to disable
mbed_official 146:f64d43ff0c18 744 */
mbed_official 324:406fd2029f23 745 static inline void FTM_HAL_SetMinLoadingCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 746 {
mbed_official 324:406fd2029f23 747 BW_FTM_SYNC_CNTMIN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 748 }
mbed_official 146:f64d43ff0c18 749
mbed_official 146:f64d43ff0c18 750 /*!
mbed_official 146:f64d43ff0c18 751 * @brief Combines the channel control.
mbed_official 146:f64d43ff0c18 752 *
mbed_official 146:f64d43ff0c18 753 * Returns an index for each channel pair.
mbed_official 146:f64d43ff0c18 754 *
mbed_official 146:f64d43ff0c18 755 * @param channel The FTM peripheral channel number.
mbed_official 146:f64d43ff0c18 756 * @return 0 for channel pair 0 & 1\n
mbed_official 146:f64d43ff0c18 757 * 1 for channel pair 2 & 3\n
mbed_official 146:f64d43ff0c18 758 * 2 for channel pair 4 & 5\n
mbed_official 146:f64d43ff0c18 759 * 3 for channel pair 6 & 7
mbed_official 146:f64d43ff0c18 760 */
mbed_official 324:406fd2029f23 761 uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel);
mbed_official 324:406fd2029f23 762
mbed_official 324:406fd2029f23 763 /*!
mbed_official 324:406fd2029f23 764 * @brief Enables the FTM peripheral timer channel pair fault control.
mbed_official 324:406fd2029f23 765 *
mbed_official 324:406fd2029f23 766 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 767 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 768 * @param enable True to enable fault control, false to disable
mbed_official 324:406fd2029f23 769 */
mbed_official 324:406fd2029f23 770 static inline void FTM_HAL_SetDualChnFaultCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 771 {
mbed_official 324:406fd2029f23 772 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 773
mbed_official 324:406fd2029f23 774 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 775 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_FAULTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 776 }
mbed_official 146:f64d43ff0c18 777
mbed_official 146:f64d43ff0c18 778 /*!
mbed_official 324:406fd2029f23 779 * @brief Enables or disables the FTM peripheral timer channel pair counter PWM sync.
mbed_official 324:406fd2029f23 780 *
mbed_official 324:406fd2029f23 781 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 782 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 783 * @param enable True to enable PWM synchronization, false to disable
mbed_official 146:f64d43ff0c18 784 */
mbed_official 324:406fd2029f23 785 static inline void FTM_HAL_SetDualChnPwmSyncCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 786 {
mbed_official 324:406fd2029f23 787 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 788
mbed_official 324:406fd2029f23 789 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 790 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_SYNCEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 791 }
mbed_official 146:f64d43ff0c18 792
mbed_official 146:f64d43ff0c18 793 /*!
mbed_official 324:406fd2029f23 794 * @brief Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
mbed_official 324:406fd2029f23 795 *
mbed_official 324:406fd2029f23 796 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 797 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 798 * @param enable True to enable deadtime insertion, false to disable
mbed_official 146:f64d43ff0c18 799 */
mbed_official 324:406fd2029f23 800 static inline void FTM_HAL_SetDualChnDeadtimeCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 801 {
mbed_official 324:406fd2029f23 802 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 803
mbed_official 324:406fd2029f23 804 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 805 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DTEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 806 }
mbed_official 146:f64d43ff0c18 807
mbed_official 146:f64d43ff0c18 808 /*!
mbed_official 324:406fd2029f23 809 * @brief Enables or disables the FTM peripheral timer channel dual edge capture decap.
mbed_official 324:406fd2029f23 810 *
mbed_official 324:406fd2029f23 811 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 812 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 813 * @param enable True to enable dual edge capture mode, false to disable
mbed_official 146:f64d43ff0c18 814 */
mbed_official 324:406fd2029f23 815 static inline void FTM_HAL_SetDualChnDecapCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 816 {
mbed_official 324:406fd2029f23 817 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 818
mbed_official 324:406fd2029f23 819 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 820 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 821 }
mbed_official 146:f64d43ff0c18 822
mbed_official 146:f64d43ff0c18 823 /*!
mbed_official 324:406fd2029f23 824 * @brief Enables the FTM peripheral timer dual edge capture mode.
mbed_official 324:406fd2029f23 825 *
mbed_official 324:406fd2029f23 826 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 827 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 828 * @param enable True to enable dual edge capture, false to disable
mbed_official 146:f64d43ff0c18 829 */
mbed_official 324:406fd2029f23 830 static inline void FTM_HAL_SetDualEdgeCaptureCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 831 {
mbed_official 324:406fd2029f23 832 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 833
mbed_official 324:406fd2029f23 834 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 835 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_DECAPEN0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 836 }
mbed_official 146:f64d43ff0c18 837
mbed_official 146:f64d43ff0c18 838 /*!
mbed_official 324:406fd2029f23 839 * @brief Enables or disables the FTM peripheral timer channel pair output complement mode.
mbed_official 324:406fd2029f23 840 *
mbed_official 324:406fd2029f23 841 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 842 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 843 * @param enable True to enable complementary mode, false to disable
mbed_official 146:f64d43ff0c18 844 */
mbed_official 324:406fd2029f23 845 static inline void FTM_HAL_SetDualChnCompCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 846 {
mbed_official 324:406fd2029f23 847 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 848
mbed_official 324:406fd2029f23 849 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 850 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMP0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 851
mbed_official 146:f64d43ff0c18 852 }
mbed_official 146:f64d43ff0c18 853
mbed_official 146:f64d43ff0c18 854 /*!
mbed_official 324:406fd2029f23 855 * @brief Enables or disables the FTM peripheral timer channel pair output combine mode.
mbed_official 324:406fd2029f23 856 *
mbed_official 324:406fd2029f23 857 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 858 * @param channel The FTM peripheral channel number
mbed_official 146:f64d43ff0c18 859 * @param enable True to enable channel pair to combine, false to disable
mbed_official 146:f64d43ff0c18 860 */
mbed_official 324:406fd2029f23 861 static inline void FTM_HAL_SetDualChnCombineCmd(uint32_t ftmBaseAddr, uint8_t channel, bool enable)
mbed_official 146:f64d43ff0c18 862 {
mbed_official 324:406fd2029f23 863 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 146:f64d43ff0c18 864
mbed_official 324:406fd2029f23 865 enable ? HW_FTM_COMBINE_SET(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH)):
mbed_official 324:406fd2029f23 866 HW_FTM_COMBINE_CLR(ftmBaseAddr, BM_FTM_COMBINE_COMBINE0 << (FTM_HAL_GetChnPairIndex(channel) * FTM_COMBINE_CHAN_CTRL_WIDTH));
mbed_official 146:f64d43ff0c18 867 }
mbed_official 146:f64d43ff0c18 868
mbed_official 146:f64d43ff0c18 869 /*FTM dead time insertion control*/
mbed_official 146:f64d43ff0c18 870 /*!
mbed_official 324:406fd2029f23 871 * @brief Sets the FTM deadtime divider.
mbed_official 324:406fd2029f23 872 *
mbed_official 324:406fd2029f23 873 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 874 * @param divider The FTM peripheral prescale divider\n
mbed_official 324:406fd2029f23 875 * 0x :divided by 1, 10: divided by 4, 11:divided by 16
mbed_official 146:f64d43ff0c18 876 */
mbed_official 324:406fd2029f23 877 static inline void FTM_HAL_SetDeadtimePrescale(uint32_t ftmBaseAddr, ftm_deadtime_ps_t divider)
mbed_official 146:f64d43ff0c18 878 {
mbed_official 324:406fd2029f23 879 BW_FTM_DEADTIME_DTPS(ftmBaseAddr, divider);
mbed_official 146:f64d43ff0c18 880 }
mbed_official 146:f64d43ff0c18 881
mbed_official 146:f64d43ff0c18 882 /*!
mbed_official 146:f64d43ff0c18 883 * @brief Sets the FTM deadtime value.
mbed_official 324:406fd2029f23 884 *
mbed_official 324:406fd2029f23 885 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 886 * @param count The FTM peripheral prescale divider\n
mbed_official 324:406fd2029f23 887 * 0: no counts inserted, 1: 1 count is inserted, 2: 2 count is inserted....
mbed_official 146:f64d43ff0c18 888 */
mbed_official 324:406fd2029f23 889 static inline void FTM_HAL_SetDeadtimeCount(uint32_t ftmBaseAddr, uint8_t count)
mbed_official 146:f64d43ff0c18 890 {
mbed_official 324:406fd2029f23 891 BW_FTM_DEADTIME_DTVAL(ftmBaseAddr, count);
mbed_official 146:f64d43ff0c18 892 }
mbed_official 324:406fd2029f23 893
mbed_official 324:406fd2029f23 894 /*!
mbed_official 324:406fd2029f23 895 * @brief Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register.
mbed_official 324:406fd2029f23 896 *
mbed_official 324:406fd2029f23 897 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 898 * @param enable True to enable, false to disable
mbed_official 324:406fd2029f23 899 */
mbed_official 324:406fd2029f23 900 static inline void FTM_HAL_SetInitTriggerCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 901 {
mbed_official 324:406fd2029f23 902 BW_FTM_EXTTRIG_INITTRIGEN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 903 }
mbed_official 324:406fd2029f23 904
mbed_official 146:f64d43ff0c18 905 /*FTM external trigger */
mbed_official 146:f64d43ff0c18 906 /*!
mbed_official 324:406fd2029f23 907 * @brief Enables or disables the generation of the FTM peripheral timer channel trigger.
mbed_official 324:406fd2029f23 908 *
mbed_official 324:406fd2029f23 909 * Enables or disables the when the generation of the FTM peripheral timer channel trigger when the
mbed_official 324:406fd2029f23 910 * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers.
mbed_official 324:406fd2029f23 911 *
mbed_official 324:406fd2029f23 912 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 913 * @param channel Channel to be enabled, valid value 0, 1, 2, 3, 4, 5
mbed_official 324:406fd2029f23 914 * @param val True to enable, false to disable
mbed_official 146:f64d43ff0c18 915 */
mbed_official 324:406fd2029f23 916 void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val);
mbed_official 324:406fd2029f23 917
mbed_official 146:f64d43ff0c18 918 /*!
mbed_official 146:f64d43ff0c18 919 * @brief Checks whether any channel trigger event has occurred.
mbed_official 324:406fd2029f23 920 *
mbed_official 324:406fd2029f23 921 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 922 * @retval true if there is a channel trigger event, false if not.
mbed_official 146:f64d43ff0c18 923 */
mbed_official 324:406fd2029f23 924 static inline bool FTM_HAL_IsChnTriggerGenerated(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 925 {
mbed_official 324:406fd2029f23 926 return BR_FTM_EXTTRIG_TRIGF(ftmBaseAddr);
mbed_official 146:f64d43ff0c18 927 }
mbed_official 146:f64d43ff0c18 928
mbed_official 146:f64d43ff0c18 929
mbed_official 146:f64d43ff0c18 930 /*Fault mode status*/
mbed_official 146:f64d43ff0c18 931 /*!
mbed_official 146:f64d43ff0c18 932 * @brief Gets the FTM detected fault input.
mbed_official 324:406fd2029f23 933 *
mbed_official 324:406fd2029f23 934 * This function reads the status for all fault inputs
mbed_official 324:406fd2029f23 935 *
mbed_official 324:406fd2029f23 936 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 937 * @retval Return fault byte
mbed_official 146:f64d43ff0c18 938 */
mbed_official 324:406fd2029f23 939 static inline uint8_t FTM_HAL_GetDetectedFaultInput(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 940 {
mbed_official 324:406fd2029f23 941 return (HW_FTM_FMS(ftmBaseAddr).U & 0x0f);
mbed_official 146:f64d43ff0c18 942 }
mbed_official 146:f64d43ff0c18 943 /*!
mbed_official 146:f64d43ff0c18 944 * @brief Checks whether the write protection is enabled.
mbed_official 324:406fd2029f23 945 *
mbed_official 324:406fd2029f23 946 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 947 * @retval True if enabled, false if not
mbed_official 146:f64d43ff0c18 948 */
mbed_official 324:406fd2029f23 949 static inline bool FTM_HAL_IsWriteProtectionEnabled(uint32_t ftmBaseAddr)
mbed_official 146:f64d43ff0c18 950 {
mbed_official 324:406fd2029f23 951 return BR_FTM_FMS_WPEN(ftmBaseAddr) ? true : false;
mbed_official 146:f64d43ff0c18 952 }
mbed_official 146:f64d43ff0c18 953
mbed_official 146:f64d43ff0c18 954 /*Quadrature decoder control*/
mbed_official 324:406fd2029f23 955
mbed_official 146:f64d43ff0c18 956 /*!
mbed_official 146:f64d43ff0c18 957 * @brief Enables the channel quadrature decoder.
mbed_official 324:406fd2029f23 958 *
mbed_official 324:406fd2029f23 959 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 960 * @param enable True to enable, false to disable
mbed_official 146:f64d43ff0c18 961 */
mbed_official 324:406fd2029f23 962 static inline void FTM_HAL_SetQuadDecoderCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 963 {
mbed_official 324:406fd2029f23 964 BW_FTM_QDCTRL_QUADEN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 965 }
mbed_official 324:406fd2029f23 966
mbed_official 324:406fd2029f23 967 /*!
mbed_official 324:406fd2029f23 968 * @brief Enables or disables the phase A input filter.
mbed_official 324:406fd2029f23 969 *
mbed_official 324:406fd2029f23 970 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 971 * @param enable true enables the phase input filter, false disables the filter
mbed_official 324:406fd2029f23 972 */
mbed_official 324:406fd2029f23 973 static inline void FTM_HAL_SetQuadPhaseAFilterCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 974 {
mbed_official 324:406fd2029f23 975 BW_FTM_QDCTRL_PHAFLTREN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 976 }
mbed_official 324:406fd2029f23 977
mbed_official 324:406fd2029f23 978 /*!
mbed_official 324:406fd2029f23 979 * @brief Enables or disables the phase B input filter.
mbed_official 324:406fd2029f23 980 *
mbed_official 324:406fd2029f23 981 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 982 * @param enable true enables the phase input filter, false disables the filter
mbed_official 324:406fd2029f23 983 */
mbed_official 324:406fd2029f23 984 static inline void FTM_HAL_SetQuadPhaseBFilterCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 985 {
mbed_official 324:406fd2029f23 986 BW_FTM_QDCTRL_PHBFLTREN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 987 }
mbed_official 324:406fd2029f23 988
mbed_official 324:406fd2029f23 989 /*!
mbed_official 324:406fd2029f23 990 * @brief Selects polarity for the quadrature decode phase A input.
mbed_official 324:406fd2029f23 991 *
mbed_official 324:406fd2029f23 992 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 993 * @param mode 0: Normal polarity, 1: Inverted polarity
mbed_official 324:406fd2029f23 994 */
mbed_official 324:406fd2029f23 995 static inline void FTM_HAL_SetQuadPhaseAPolarity(uint32_t ftmBaseAddr,
mbed_official 324:406fd2029f23 996 ftm_quad_phase_polarity_t mode)
mbed_official 324:406fd2029f23 997 {
mbed_official 324:406fd2029f23 998 BW_FTM_QDCTRL_PHAPOL(ftmBaseAddr, mode);
mbed_official 146:f64d43ff0c18 999 }
mbed_official 146:f64d43ff0c18 1000
mbed_official 324:406fd2029f23 1001 /*!
mbed_official 324:406fd2029f23 1002 * @brief Selects polarity for the quadrature decode phase B input.
mbed_official 324:406fd2029f23 1003 *
mbed_official 324:406fd2029f23 1004 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1005 * @param mode 0: Normal polarity, 1: Inverted polarity
mbed_official 324:406fd2029f23 1006 */
mbed_official 324:406fd2029f23 1007 static inline void FTM_HAL_SetQuadPhaseBPolarity(uint32_t ftmBaseAddr,
mbed_official 324:406fd2029f23 1008 ftm_quad_phase_polarity_t mode)
mbed_official 324:406fd2029f23 1009 {
mbed_official 324:406fd2029f23 1010 BW_FTM_QDCTRL_PHBPOL(ftmBaseAddr, mode);
mbed_official 324:406fd2029f23 1011 }
mbed_official 324:406fd2029f23 1012
mbed_official 324:406fd2029f23 1013 /*!
mbed_official 324:406fd2029f23 1014 * @brief Sets the encoding mode used in quadrature decoding mode.
mbed_official 324:406fd2029f23 1015 *
mbed_official 324:406fd2029f23 1016 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1017 * @param quadMode 0: Phase A and Phase B encoding mode\n
mbed_official 324:406fd2029f23 1018 * 1: Count and direction encoding mode
mbed_official 324:406fd2029f23 1019 */
mbed_official 324:406fd2029f23 1020 static inline void FTM_HAL_SetQuadMode(uint32_t ftmBaseAddr, ftm_quad_decode_mode_t quadMode)
mbed_official 324:406fd2029f23 1021 {
mbed_official 324:406fd2029f23 1022 BW_FTM_QDCTRL_QUADMODE(ftmBaseAddr, quadMode);
mbed_official 324:406fd2029f23 1023 }
mbed_official 324:406fd2029f23 1024
mbed_official 324:406fd2029f23 1025 /*!
mbed_official 324:406fd2029f23 1026 * @brief Gets the FTM counter direction in quadrature mode.
mbed_official 324:406fd2029f23 1027 *
mbed_official 324:406fd2029f23 1028 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1029 *
mbed_official 324:406fd2029f23 1030 * @retval 1 if counting direction is increasing, 0 if counting direction is decreasing
mbed_official 324:406fd2029f23 1031 */
mbed_official 324:406fd2029f23 1032 static inline uint8_t FTM_HAL_GetQuadDir(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 1033 {
mbed_official 324:406fd2029f23 1034 return BR_FTM_QDCTRL_QUADMODE(ftmBaseAddr);
mbed_official 324:406fd2029f23 1035 }
mbed_official 324:406fd2029f23 1036
mbed_official 324:406fd2029f23 1037 /*!
mbed_official 324:406fd2029f23 1038 * @brief Gets the Timer overflow direction in quadrature mode.
mbed_official 324:406fd2029f23 1039 *
mbed_official 324:406fd2029f23 1040 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1041 *
mbed_official 324:406fd2029f23 1042 * @retval 1 if TOF bit was set on the top of counting, o if TOF bit was set on the bottom of counting
mbed_official 324:406fd2029f23 1043 */
mbed_official 324:406fd2029f23 1044 static inline uint8_t FTM_HAL_GetQuadTimerOverflowDir(uint32_t ftmBaseAddr)
mbed_official 324:406fd2029f23 1045 {
mbed_official 324:406fd2029f23 1046 return BR_FTM_QDCTRL_TOFDIR(ftmBaseAddr);
mbed_official 324:406fd2029f23 1047 }
mbed_official 146:f64d43ff0c18 1048
mbed_official 146:f64d43ff0c18 1049 /*!
mbed_official 146:f64d43ff0c18 1050 * @brief Sets the FTM peripheral timer channel input capture filter value.
mbed_official 324:406fd2029f23 1051 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 1052 * @param channel The FTM peripheral channel number, only 0,1,2,3, channel 4, 5,6, 7 don't have.
mbed_official 146:f64d43ff0c18 1053 * @param val Filter value to be set
mbed_official 146:f64d43ff0c18 1054 */
mbed_official 324:406fd2029f23 1055 void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val);
mbed_official 146:f64d43ff0c18 1056
mbed_official 146:f64d43ff0c18 1057 /*!
mbed_official 324:406fd2029f23 1058 * @brief Sets the fault input filter value.
mbed_official 324:406fd2029f23 1059 *
mbed_official 324:406fd2029f23 1060 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1061 * @param val fault input filter value
mbed_official 146:f64d43ff0c18 1062 */
mbed_official 324:406fd2029f23 1063 static inline void FTM_HAL_SetFaultInputFilterVal(uint32_t ftmBaseAddr, uint32_t val)
mbed_official 146:f64d43ff0c18 1064 {
mbed_official 324:406fd2029f23 1065 BW_FTM_FLTCTRL_FFVAL(ftmBaseAddr, val);
mbed_official 146:f64d43ff0c18 1066 }
mbed_official 146:f64d43ff0c18 1067
mbed_official 146:f64d43ff0c18 1068 /*!
mbed_official 324:406fd2029f23 1069 * @brief Enables or disables the fault input filter.
mbed_official 324:406fd2029f23 1070 *
mbed_official 324:406fd2029f23 1071 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1072 * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
mbed_official 324:406fd2029f23 1073 * @param val true to enable fault input filter, false to disable fault input filter
mbed_official 146:f64d43ff0c18 1074 */
mbed_official 324:406fd2029f23 1075 static inline void FTM_HAL_SetFaultInputFilterCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
mbed_official 146:f64d43ff0c18 1076 {
mbed_official 324:406fd2029f23 1077 assert(inputNum < HW_CHAN4);
mbed_official 324:406fd2029f23 1078 val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << (inputNum + 4))) :
mbed_official 324:406fd2029f23 1079 HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << (inputNum + 4)));
mbed_official 146:f64d43ff0c18 1080 }
mbed_official 146:f64d43ff0c18 1081
mbed_official 146:f64d43ff0c18 1082 /*!
mbed_official 324:406fd2029f23 1083 * @brief Enables or disables the fault input.
mbed_official 324:406fd2029f23 1084 *
mbed_official 324:406fd2029f23 1085 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1086 * @param inputNum fault input to be configured, valid value 0, 1, 2, 3
mbed_official 324:406fd2029f23 1087 * @param val true to enable fault input, false to disable fault input
mbed_official 146:f64d43ff0c18 1088 */
mbed_official 324:406fd2029f23 1089 static inline void FTM_HAL_SetFaultInputCmd(uint32_t ftmBaseAddr, uint8_t inputNum, bool val)
mbed_official 146:f64d43ff0c18 1090 {
mbed_official 324:406fd2029f23 1091 assert(inputNum < HW_CHAN4);
mbed_official 324:406fd2029f23 1092 val ? HW_FTM_FLTCTRL_SET(ftmBaseAddr, (1U << inputNum)) :
mbed_official 324:406fd2029f23 1093 HW_FTM_FLTCTRL_CLR(ftmBaseAddr, (1U << inputNum));
mbed_official 324:406fd2029f23 1094 }
mbed_official 146:f64d43ff0c18 1095
mbed_official 324:406fd2029f23 1096 /*!
mbed_official 324:406fd2029f23 1097 * @brief Enables or disables the channel invert for a channel pair.
mbed_official 324:406fd2029f23 1098 *
mbed_official 324:406fd2029f23 1099 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1100 * @param channel The FTM peripheral channel number
mbed_official 324:406fd2029f23 1101 * @param val true to enable channel inverting, false to disable channel inverting
mbed_official 324:406fd2029f23 1102 */
mbed_official 324:406fd2029f23 1103 static inline void FTM_HAL_SetDualChnInvertCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
mbed_official 324:406fd2029f23 1104 {
mbed_official 324:406fd2029f23 1105 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 1106
mbed_official 324:406fd2029f23 1107 val ? HW_FTM_INVCTRL_SET(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel))) :
mbed_official 324:406fd2029f23 1108 HW_FTM_INVCTRL_CLR(ftmBaseAddr, (1U << FTM_HAL_GetChnPairIndex(channel)));
mbed_official 146:f64d43ff0c18 1109 }
mbed_official 146:f64d43ff0c18 1110
mbed_official 146:f64d43ff0c18 1111 /*FTM software output control*/
mbed_official 146:f64d43ff0c18 1112 /*!
mbed_official 324:406fd2029f23 1113 * @brief Enables or disables the channel software output control.
mbed_official 324:406fd2029f23 1114 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1115 * @param channel Channel to be enabled or disabled
mbed_official 324:406fd2029f23 1116 * @param val true to enable, channel output will be affected by software output control\n
mbed_official 324:406fd2029f23 1117 false to disable, channel output is unaffected
mbed_official 146:f64d43ff0c18 1118 */
mbed_official 324:406fd2029f23 1119 static inline void FTM_HAL_SetChnSoftwareCtrlCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
mbed_official 146:f64d43ff0c18 1120 {
mbed_official 324:406fd2029f23 1121 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 1122 val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << channel)) :
mbed_official 324:406fd2029f23 1123 HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << channel));
mbed_official 146:f64d43ff0c18 1124 }
mbed_official 146:f64d43ff0c18 1125 /*!
mbed_official 324:406fd2029f23 1126 * @brief Sets the channel software output control value.
mbed_official 324:406fd2029f23 1127 *
mbed_official 324:406fd2029f23 1128 * @param ftmBaseAddr The FTM base address.
mbed_official 324:406fd2029f23 1129 * @param channel Channel to be configured
mbed_official 324:406fd2029f23 1130 * @param val True to set 1, false to set 0
mbed_official 146:f64d43ff0c18 1131 */
mbed_official 324:406fd2029f23 1132 static inline void FTM_HAL_SetChnSoftwareCtrlVal(uint32_t ftmBaseAddr, uint8_t channel, bool val)
mbed_official 146:f64d43ff0c18 1133 {
mbed_official 324:406fd2029f23 1134 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 1135 val ? HW_FTM_SWOCTRL_SET(ftmBaseAddr, (1U << (channel + 8))) :
mbed_official 324:406fd2029f23 1136 HW_FTM_SWOCTRL_CLR(ftmBaseAddr, (1U << (channel + 8)));
mbed_official 146:f64d43ff0c18 1137 }
mbed_official 146:f64d43ff0c18 1138
mbed_official 146:f64d43ff0c18 1139 /*FTM PWM load control*/
mbed_official 146:f64d43ff0c18 1140 /*!
mbed_official 324:406fd2029f23 1141 * @brief Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
mbed_official 324:406fd2029f23 1142 *
mbed_official 324:406fd2029f23 1143 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1144 * @param enable true to enable, false to disable
mbed_official 146:f64d43ff0c18 1145 */
mbed_official 324:406fd2029f23 1146 static inline void FTM_HAL_SetPwmLoadCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1147 {
mbed_official 324:406fd2029f23 1148 BW_FTM_PWMLOAD_LDOK(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1149 }
mbed_official 146:f64d43ff0c18 1150
mbed_official 146:f64d43ff0c18 1151 /*!
mbed_official 324:406fd2029f23 1152 * @brief Includes or excludes the channel in the matching process.
mbed_official 324:406fd2029f23 1153 *
mbed_official 324:406fd2029f23 1154 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1155 * @param channel Channel to be configured
mbed_official 324:406fd2029f23 1156 * @param val true means include the channel in the matching process\n
mbed_official 324:406fd2029f23 1157 * false means do not include channel in the matching process
mbed_official 324:406fd2029f23 1158 */
mbed_official 324:406fd2029f23 1159 static inline void FTM_HAL_SetPwmLoadChnSelCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
mbed_official 324:406fd2029f23 1160 {
mbed_official 324:406fd2029f23 1161 assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT);
mbed_official 324:406fd2029f23 1162 val ? HW_FTM_PWMLOAD_SET(ftmBaseAddr, 1U << channel) : HW_FTM_PWMLOAD_CLR(ftmBaseAddr, 1U << channel);
mbed_official 324:406fd2029f23 1163 }
mbed_official 324:406fd2029f23 1164
mbed_official 324:406fd2029f23 1165 /*FTM configuration*/
mbed_official 324:406fd2029f23 1166 /*!
mbed_official 324:406fd2029f23 1167 * @brief Enables or disables the FTM global time base signal generation to other FTM's.
mbed_official 324:406fd2029f23 1168 *
mbed_official 324:406fd2029f23 1169 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 1170 * @param enable True to enable, false to disable
mbed_official 146:f64d43ff0c18 1171 */
mbed_official 324:406fd2029f23 1172 static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1173 {
mbed_official 324:406fd2029f23 1174 BW_FTM_CONF_GTBEOUT(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1175 }
mbed_official 146:f64d43ff0c18 1176
mbed_official 146:f64d43ff0c18 1177 /*!
mbed_official 324:406fd2029f23 1178 * @brief Enables or disables the FTM timer global time base.
mbed_official 324:406fd2029f23 1179 *
mbed_official 324:406fd2029f23 1180 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 1181 * @param enable True to enable, false to disable
mbed_official 146:f64d43ff0c18 1182 */
mbed_official 324:406fd2029f23 1183 static inline void FTM_HAL_SetGlobalTimeBaseCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1184 {
mbed_official 324:406fd2029f23 1185 BW_FTM_CONF_GTBEEN(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1186 }
mbed_official 146:f64d43ff0c18 1187
mbed_official 146:f64d43ff0c18 1188 /*!
mbed_official 324:406fd2029f23 1189 * @brief Sets the BDM mode..
mbed_official 324:406fd2029f23 1190 *
mbed_official 324:406fd2029f23 1191 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1192 * @param val FTM behaviour in BDM mode, options are 0,1,2,3
mbed_official 146:f64d43ff0c18 1193 */
mbed_official 324:406fd2029f23 1194 static inline void FTM_HAL_SetBdmMode(uint32_t ftmBaseAddr, uint8_t val)
mbed_official 146:f64d43ff0c18 1195 {
mbed_official 324:406fd2029f23 1196 BW_FTM_CONF_BDMMODE(ftmBaseAddr, val);
mbed_official 146:f64d43ff0c18 1197 }
mbed_official 146:f64d43ff0c18 1198
mbed_official 146:f64d43ff0c18 1199 /*!
mbed_official 324:406fd2029f23 1200 * @brief Sets the FTM timer TOF Frequency
mbed_official 324:406fd2029f23 1201 *
mbed_official 324:406fd2029f23 1202 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1203 * @param val Value of the TOF bit set frequency
mbed_official 146:f64d43ff0c18 1204 */
mbed_official 324:406fd2029f23 1205 static inline void FTM_HAL_SetTofFreq(uint32_t ftmBaseAddr, uint8_t val)
mbed_official 146:f64d43ff0c18 1206 {
mbed_official 324:406fd2029f23 1207 BW_FTM_CONF_NUMTOF(ftmBaseAddr, val);
mbed_official 146:f64d43ff0c18 1208 }
mbed_official 146:f64d43ff0c18 1209
mbed_official 146:f64d43ff0c18 1210 /*FTM sync configuration*/
mbed_official 146:f64d43ff0c18 1211 /*hardware sync*/
mbed_official 146:f64d43ff0c18 1212 /*!
mbed_official 324:406fd2029f23 1213 * @brief Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
mbed_official 324:406fd2029f23 1214 *
mbed_official 324:406fd2029f23 1215 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1216 * @param enable true means the hardware trigger activates register sync\n
mbed_official 324:406fd2029f23 1217 * false means the hardware trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1218 */
mbed_official 324:406fd2029f23 1219 static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1220 {
mbed_official 324:406fd2029f23 1221 BW_FTM_SYNCONF_HWSOC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1222 }
mbed_official 146:f64d43ff0c18 1223
mbed_official 146:f64d43ff0c18 1224 /*!
mbed_official 324:406fd2029f23 1225 * @brief Sets sync mode for FTM INVCTRL register when using a hardware trigger.
mbed_official 324:406fd2029f23 1226 *
mbed_official 324:406fd2029f23 1227 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1228 * @param enable true means the hardware trigger activates register sync\n
mbed_official 324:406fd2029f23 1229 * false means the hardware trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1230 */
mbed_official 324:406fd2029f23 1231 static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1232 {
mbed_official 324:406fd2029f23 1233 BW_FTM_SYNCONF_HWINVC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1234 }
mbed_official 146:f64d43ff0c18 1235
mbed_official 146:f64d43ff0c18 1236 /*!
mbed_official 324:406fd2029f23 1237 * @brief Sets sync mode for FTM OUTMASK register when using a hardware trigger.
mbed_official 146:f64d43ff0c18 1238 *
mbed_official 324:406fd2029f23 1239 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1240 * @param enable true means hardware trigger activates register sync\n
mbed_official 324:406fd2029f23 1241 * false means hardware trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1242 */
mbed_official 324:406fd2029f23 1243 static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1244 {
mbed_official 324:406fd2029f23 1245 BW_FTM_SYNCONF_HWOM(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1246 }
mbed_official 146:f64d43ff0c18 1247
mbed_official 146:f64d43ff0c18 1248 /*!
mbed_official 324:406fd2029f23 1249 * @brief Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger.
mbed_official 146:f64d43ff0c18 1250 *
mbed_official 324:406fd2029f23 1251 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1252 * @param enable true means hardware trigger activates register sync\n
mbed_official 324:406fd2029f23 1253 * false means hardware trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1254 */
mbed_official 324:406fd2029f23 1255 static inline void FTM_HAL_SetModCntinCvHardwareSycnModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1256 {
mbed_official 324:406fd2029f23 1257 BW_FTM_SYNCONF_HWWRBUF(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1258 }
mbed_official 146:f64d43ff0c18 1259
mbed_official 146:f64d43ff0c18 1260 /*!
mbed_official 324:406fd2029f23 1261 * @brief Sets sync mode for FTM counter register when using a hardware trigger.
mbed_official 324:406fd2029f23 1262 *
mbed_official 324:406fd2029f23 1263 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1264 * @param enable true means hardware trigger activates register sync\n
mbed_official 324:406fd2029f23 1265 * false means hardware trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1266 */
mbed_official 324:406fd2029f23 1267 static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1268 {
mbed_official 324:406fd2029f23 1269 BW_FTM_SYNCONF_HWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 1270 }
mbed_official 324:406fd2029f23 1271
mbed_official 324:406fd2029f23 1272 /*!
mbed_official 324:406fd2029f23 1273 * @brief Sets sync mode for FTM SWOCTRL register when using a software trigger.
mbed_official 324:406fd2029f23 1274 *
mbed_official 324:406fd2029f23 1275 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1276 * @param enable true means software trigger activates register sync\n
mbed_official 324:406fd2029f23 1277 * false means software trigger does not activate register sync.
mbed_official 324:406fd2029f23 1278 */
mbed_official 324:406fd2029f23 1279 static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 1280 {
mbed_official 324:406fd2029f23 1281 BW_FTM_SYNCONF_SWSOC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1282 }
mbed_official 146:f64d43ff0c18 1283
mbed_official 146:f64d43ff0c18 1284 /*!
mbed_official 324:406fd2029f23 1285 * @brief Sets sync mode for FTM INVCTRL register when using a software trigger.
mbed_official 324:406fd2029f23 1286 *
mbed_official 324:406fd2029f23 1287 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1288 * @param enable true means software trigger activates register sync\n
mbed_official 324:406fd2029f23 1289 * false means software trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1290 */
mbed_official 324:406fd2029f23 1291 static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1292 {
mbed_official 324:406fd2029f23 1293 BW_FTM_SYNCONF_SWINVC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1294 }
mbed_official 146:f64d43ff0c18 1295
mbed_official 146:f64d43ff0c18 1296 /*!
mbed_official 324:406fd2029f23 1297 * @brief Sets sync mode for FTM OUTMASK register when using a software trigger.
mbed_official 324:406fd2029f23 1298 *
mbed_official 324:406fd2029f23 1299 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1300 * @param enable true means software trigger activates register sync\n
mbed_official 324:406fd2029f23 1301 * false means software trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1302 */
mbed_official 324:406fd2029f23 1303 static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1304 {
mbed_official 324:406fd2029f23 1305 BW_FTM_SYNCONF_SWOM(ftmBaseAddr, enable ? 1 : 0);
mbed_official 324:406fd2029f23 1306 }
mbed_official 324:406fd2029f23 1307
mbed_official 324:406fd2029f23 1308 /*!
mbed_official 324:406fd2029f23 1309 * @brief Sets synch mode for FTM MOD, CNTIN and CV registers when using a software trigger.
mbed_official 324:406fd2029f23 1310 *
mbed_official 324:406fd2029f23 1311 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1312 * @param enable true means software trigger activates register sync\n
mbed_official 324:406fd2029f23 1313 * false means software trigger does not activate register sync.
mbed_official 324:406fd2029f23 1314 */
mbed_official 324:406fd2029f23 1315 static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 324:406fd2029f23 1316 {
mbed_official 324:406fd2029f23 1317 BW_FTM_SYNCONF_SWWRBUF(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1318 }
mbed_official 146:f64d43ff0c18 1319
mbed_official 146:f64d43ff0c18 1320 /*!
mbed_official 324:406fd2029f23 1321 * @brief Sets sync mode for FTM counter register when using a software trigger.
mbed_official 324:406fd2029f23 1322 *
mbed_official 324:406fd2029f23 1323 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1324 * @param enable true means software trigger activates register sync\n
mbed_official 324:406fd2029f23 1325 * false means software trigger does not activate register sync.
mbed_official 146:f64d43ff0c18 1326 */
mbed_official 324:406fd2029f23 1327 static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1328 {
mbed_official 324:406fd2029f23 1329 BW_FTM_SYNCONF_SWRSTCNT(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1330 }
mbed_official 146:f64d43ff0c18 1331
mbed_official 146:f64d43ff0c18 1332 /*!
mbed_official 324:406fd2029f23 1333 * @brief Sets the PWM synchronization mode to enhanced or legacy.
mbed_official 324:406fd2029f23 1334 *
mbed_official 324:406fd2029f23 1335 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1336 * @param enable true means use Enhanced PWM synchronization\n
mbed_official 324:406fd2029f23 1337 * false means to use Legacy mode
mbed_official 146:f64d43ff0c18 1338 */
mbed_official 324:406fd2029f23 1339 static inline void FTM_HAL_SetPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1340 {
mbed_official 324:406fd2029f23 1341 BW_FTM_SYNCONF_SYNCMODE(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1342 }
mbed_official 146:f64d43ff0c18 1343
mbed_official 146:f64d43ff0c18 1344 /*!
mbed_official 324:406fd2029f23 1345 * @brief Sets the SWOCTRL register PWM synchronization mode.
mbed_official 324:406fd2029f23 1346 *
mbed_official 324:406fd2029f23 1347 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1348 * @param enable true means SWOCTRL register is updated by PWM synch\n
mbed_official 324:406fd2029f23 1349 * false means SWOCTRL register is updated at all rising edges of system clock
mbed_official 146:f64d43ff0c18 1350 */
mbed_official 324:406fd2029f23 1351 static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1352 {
mbed_official 324:406fd2029f23 1353 BW_FTM_SYNCONF_SWOC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1354 }
mbed_official 146:f64d43ff0c18 1355
mbed_official 146:f64d43ff0c18 1356 /*!
mbed_official 324:406fd2029f23 1357 * @brief Sets the INVCTRL register PWM synchronization mode.
mbed_official 324:406fd2029f23 1358 *
mbed_official 324:406fd2029f23 1359 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1360 * @param enable true means INVCTRL register is updated by PWM synch\n
mbed_official 324:406fd2029f23 1361 * false means INVCTRL register is updated at all rising edges of system clock
mbed_official 146:f64d43ff0c18 1362 */
mbed_official 324:406fd2029f23 1363 static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1364 {
mbed_official 324:406fd2029f23 1365 BW_FTM_SYNCONF_INVC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1366 }
mbed_official 146:f64d43ff0c18 1367
mbed_official 146:f64d43ff0c18 1368 /*!
mbed_official 324:406fd2029f23 1369 * @brief Sets the CNTIN register PWM synchronization mode.
mbed_official 324:406fd2029f23 1370 *
mbed_official 324:406fd2029f23 1371 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1372 * @param enable true means CNTIN register is updated by PWM synch\n
mbed_official 324:406fd2029f23 1373 * false means CNTIN register is updated at all rising edges of system clock
mbed_official 146:f64d43ff0c18 1374 */
mbed_official 324:406fd2029f23 1375 static inline void FTM_HAL_SetCntinPwmSyncModeCmd(uint32_t ftmBaseAddr, bool enable)
mbed_official 146:f64d43ff0c18 1376 {
mbed_official 324:406fd2029f23 1377 BW_FTM_SYNCONF_CNTINC(ftmBaseAddr, enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1378 }
mbed_official 146:f64d43ff0c18 1379
mbed_official 146:f64d43ff0c18 1380
mbed_official 146:f64d43ff0c18 1381 /*HAL functionality*/
mbed_official 146:f64d43ff0c18 1382 /*!
mbed_official 146:f64d43ff0c18 1383 * @brief Resets the FTM registers
mbed_official 324:406fd2029f23 1384 *
mbed_official 324:406fd2029f23 1385 * @param instance The FTM instance number
mbed_official 324:406fd2029f23 1386 * @param ftmBaseAddr The FTM base address
mbed_official 146:f64d43ff0c18 1387 */
mbed_official 324:406fd2029f23 1388 void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance);
mbed_official 146:f64d43ff0c18 1389
mbed_official 146:f64d43ff0c18 1390 /*!
mbed_official 146:f64d43ff0c18 1391 * @brief Initializes the FTM.
mbed_official 324:406fd2029f23 1392 *
mbed_official 324:406fd2029f23 1393 * @param ftmBaseAddr The FTM base address.
mbed_official 324:406fd2029f23 1394 */
mbed_official 324:406fd2029f23 1395 void FTM_HAL_Init(uint32_t ftmBaseAddr);
mbed_official 324:406fd2029f23 1396
mbed_official 146:f64d43ff0c18 1397 /*Initializes the 5 FTM operating mode, input capture, output compare, PWM output(edge aligned, center-aligned, conbine), dual and quadrature).*/
mbed_official 146:f64d43ff0c18 1398
mbed_official 324:406fd2029f23 1399 /*void FTM_HAL_input_capture_mode(uint32_t ftmBaseAddr);*/
mbed_official 324:406fd2029f23 1400 /*void FTM_HAL_output_compare_mode(uint32_t ftmBaseAddr);*/
mbed_official 146:f64d43ff0c18 1401
mbed_official 146:f64d43ff0c18 1402 /*!
mbed_official 146:f64d43ff0c18 1403 * @brief Enables the FTM timer when it is PWM output mode.
mbed_official 324:406fd2029f23 1404 *
mbed_official 324:406fd2029f23 1405 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1406 * @param config PWM configuration parameter
mbed_official 324:406fd2029f23 1407 * @param channel The channel or channel pair number(combined mode).
mbed_official 146:f64d43ff0c18 1408 */
mbed_official 324:406fd2029f23 1409 void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
mbed_official 146:f64d43ff0c18 1410
mbed_official 146:f64d43ff0c18 1411 /*!
mbed_official 324:406fd2029f23 1412 * @brief Disables the PWM output mode.
mbed_official 324:406fd2029f23 1413 *
mbed_official 324:406fd2029f23 1414 * @param ftmBaseAddr The FTM base address
mbed_official 324:406fd2029f23 1415 * @param config PWM configuration parameter
mbed_official 324:406fd2029f23 1416 * @param channel The channel or channel pair number(combined mode).
mbed_official 146:f64d43ff0c18 1417 */
mbed_official 324:406fd2029f23 1418 void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel);
mbed_official 324:406fd2029f23 1419
mbed_official 324:406fd2029f23 1420 /*void FTM_HAL_dual_mode(uint32_t ftmBaseAddr);*/
mbed_official 324:406fd2029f23 1421 /*void FTM_HAL_quad_mode(uint32_t ftmBaseAddr);*/
mbed_official 146:f64d43ff0c18 1422
mbed_official 146:f64d43ff0c18 1423
mbed_official 324:406fd2029f23 1424 /*void FTM_HAL_set_counting_mode(); //up, up down or free running counting mode*/
mbed_official 324:406fd2029f23 1425 /*void FTM_HAL_set_deadtime(uint32_t ftmBaseAddr, uint_32 us);*/
mbed_official 146:f64d43ff0c18 1426
mbed_official 146:f64d43ff0c18 1427 /*! @}*/
mbed_official 146:f64d43ff0c18 1428
mbed_official 146:f64d43ff0c18 1429 #endif /* __FSL_FTM_HAL_H__*/
mbed_official 146:f64d43ff0c18 1430 /*******************************************************************************
mbed_official 146:f64d43ff0c18 1431 * EOF
mbed_official 146:f64d43ff0c18 1432 ******************************************************************************/
mbed_official 324:406fd2029f23 1433