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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_spi.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_SPI_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_SPI_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 SPI
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Serial Peripheral Interface
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_SPI_MCR - Module Configuration Register
mbed_official 324:406fd2029f23 90 * - HW_SPI_TCR - Transfer Count Register
mbed_official 324:406fd2029f23 91 * - HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
mbed_official 324:406fd2029f23 92 * - HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
mbed_official 324:406fd2029f23 93 * - HW_SPI_SR - Status Register
mbed_official 324:406fd2029f23 94 * - HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
mbed_official 324:406fd2029f23 95 * - HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
mbed_official 324:406fd2029f23 96 * - HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
mbed_official 324:406fd2029f23 97 * - HW_SPI_POPR - POP RX FIFO Register
mbed_official 324:406fd2029f23 98 * - HW_SPI_TXFRn - Transmit FIFO Registers
mbed_official 324:406fd2029f23 99 * - HW_SPI_RXFRn - Receive FIFO Registers
mbed_official 324:406fd2029f23 100 *
mbed_official 324:406fd2029f23 101 * - hw_spi_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 102 */
mbed_official 324:406fd2029f23 103
mbed_official 324:406fd2029f23 104 #define HW_SPI_INSTANCE_COUNT (2U) /*!< Number of instances of the SPI module. */
mbed_official 324:406fd2029f23 105 #define HW_SPI0 (0U) /*!< Instance number for SPI0. */
mbed_official 324:406fd2029f23 106 #define HW_SPI1 (1U) /*!< Instance number for SPI1. */
mbed_official 324:406fd2029f23 107
mbed_official 324:406fd2029f23 108 /*******************************************************************************
mbed_official 324:406fd2029f23 109 * HW_SPI_MCR - Module Configuration Register
mbed_official 324:406fd2029f23 110 ******************************************************************************/
mbed_official 324:406fd2029f23 111
mbed_official 324:406fd2029f23 112 /*!
mbed_official 324:406fd2029f23 113 * @brief HW_SPI_MCR - Module Configuration Register (RW)
mbed_official 324:406fd2029f23 114 *
mbed_official 324:406fd2029f23 115 * Reset value: 0x00004001U
mbed_official 324:406fd2029f23 116 *
mbed_official 324:406fd2029f23 117 * Contains bits to configure various attributes associated with the module
mbed_official 324:406fd2029f23 118 * operations. The HALT and MDIS bits can be changed at any time, but the effect
mbed_official 324:406fd2029f23 119 * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
mbed_official 324:406fd2029f23 120 * MCR can be changed, while the module is in the Running state.
mbed_official 324:406fd2029f23 121 */
mbed_official 324:406fd2029f23 122 typedef union _hw_spi_mcr
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 uint32_t U;
mbed_official 324:406fd2029f23 125 struct _hw_spi_mcr_bitfields
mbed_official 324:406fd2029f23 126 {
mbed_official 324:406fd2029f23 127 uint32_t HALT : 1; /*!< [0] Halt */
mbed_official 324:406fd2029f23 128 uint32_t RESERVED0 : 7; /*!< [7:1] */
mbed_official 324:406fd2029f23 129 uint32_t SMPL_PT : 2; /*!< [9:8] Sample Point */
mbed_official 324:406fd2029f23 130 uint32_t CLR_RXF : 1; /*!< [10] */
mbed_official 324:406fd2029f23 131 uint32_t CLR_TXF : 1; /*!< [11] Clear TX FIFO */
mbed_official 324:406fd2029f23 132 uint32_t DIS_RXF : 1; /*!< [12] Disable Receive FIFO */
mbed_official 324:406fd2029f23 133 uint32_t DIS_TXF : 1; /*!< [13] Disable Transmit FIFO */
mbed_official 324:406fd2029f23 134 uint32_t MDIS : 1; /*!< [14] Module Disable */
mbed_official 324:406fd2029f23 135 uint32_t DOZE : 1; /*!< [15] Doze Enable */
mbed_official 324:406fd2029f23 136 uint32_t PCSIS : 6; /*!< [21:16] Peripheral Chip Select x Inactive
mbed_official 324:406fd2029f23 137 * State */
mbed_official 324:406fd2029f23 138 uint32_t RESERVED1 : 2; /*!< [23:22] */
mbed_official 324:406fd2029f23 139 uint32_t ROOE : 1; /*!< [24] Receive FIFO Overflow Overwrite Enable */
mbed_official 324:406fd2029f23 140 uint32_t PCSSE : 1; /*!< [25] Peripheral Chip Select Strobe Enable */
mbed_official 324:406fd2029f23 141 uint32_t MTFE : 1; /*!< [26] Modified Timing Format Enable */
mbed_official 324:406fd2029f23 142 uint32_t FRZ : 1; /*!< [27] Freeze */
mbed_official 324:406fd2029f23 143 uint32_t DCONF : 2; /*!< [29:28] SPI Configuration. */
mbed_official 324:406fd2029f23 144 uint32_t CONT_SCKE : 1; /*!< [30] Continuous SCK Enable */
mbed_official 324:406fd2029f23 145 uint32_t MSTR : 1; /*!< [31] Master/Slave Mode Select */
mbed_official 324:406fd2029f23 146 } B;
mbed_official 324:406fd2029f23 147 } hw_spi_mcr_t;
mbed_official 324:406fd2029f23 148
mbed_official 324:406fd2029f23 149 /*!
mbed_official 324:406fd2029f23 150 * @name Constants and macros for entire SPI_MCR register
mbed_official 324:406fd2029f23 151 */
mbed_official 324:406fd2029f23 152 /*@{*/
mbed_official 324:406fd2029f23 153 #define HW_SPI_MCR_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 154
mbed_official 324:406fd2029f23 155 #define HW_SPI_MCR(x) (*(__IO hw_spi_mcr_t *) HW_SPI_MCR_ADDR(x))
mbed_official 324:406fd2029f23 156 #define HW_SPI_MCR_RD(x) (HW_SPI_MCR(x).U)
mbed_official 324:406fd2029f23 157 #define HW_SPI_MCR_WR(x, v) (HW_SPI_MCR(x).U = (v))
mbed_official 324:406fd2029f23 158 #define HW_SPI_MCR_SET(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) | (v)))
mbed_official 324:406fd2029f23 159 #define HW_SPI_MCR_CLR(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 160 #define HW_SPI_MCR_TOG(x, v) (HW_SPI_MCR_WR(x, HW_SPI_MCR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 161 /*@}*/
mbed_official 324:406fd2029f23 162
mbed_official 324:406fd2029f23 163 /*
mbed_official 324:406fd2029f23 164 * Constants & macros for individual SPI_MCR bitfields
mbed_official 324:406fd2029f23 165 */
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 /*!
mbed_official 324:406fd2029f23 168 * @name Register SPI_MCR, field HALT[0] (RW)
mbed_official 324:406fd2029f23 169 *
mbed_official 324:406fd2029f23 170 * The HALT bit starts and stops frame transfers. See Start and Stop of Module
mbed_official 324:406fd2029f23 171 * transfers
mbed_official 324:406fd2029f23 172 *
mbed_official 324:406fd2029f23 173 * Values:
mbed_official 324:406fd2029f23 174 * - 0 - Start transfers.
mbed_official 324:406fd2029f23 175 * - 1 - Stop transfers.
mbed_official 324:406fd2029f23 176 */
mbed_official 324:406fd2029f23 177 /*@{*/
mbed_official 324:406fd2029f23 178 #define BP_SPI_MCR_HALT (0U) /*!< Bit position for SPI_MCR_HALT. */
mbed_official 324:406fd2029f23 179 #define BM_SPI_MCR_HALT (0x00000001U) /*!< Bit mask for SPI_MCR_HALT. */
mbed_official 324:406fd2029f23 180 #define BS_SPI_MCR_HALT (1U) /*!< Bit field size in bits for SPI_MCR_HALT. */
mbed_official 324:406fd2029f23 181
mbed_official 324:406fd2029f23 182 /*! @brief Read current value of the SPI_MCR_HALT field. */
mbed_official 324:406fd2029f23 183 #define BR_SPI_MCR_HALT(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT))
mbed_official 324:406fd2029f23 184
mbed_official 324:406fd2029f23 185 /*! @brief Format value for bitfield SPI_MCR_HALT. */
mbed_official 324:406fd2029f23 186 #define BF_SPI_MCR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_HALT) & BM_SPI_MCR_HALT)
mbed_official 324:406fd2029f23 187
mbed_official 324:406fd2029f23 188 /*! @brief Set the HALT field to a new value. */
mbed_official 324:406fd2029f23 189 #define BW_SPI_MCR_HALT(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_HALT) = (v))
mbed_official 324:406fd2029f23 190 /*@}*/
mbed_official 324:406fd2029f23 191
mbed_official 324:406fd2029f23 192 /*!
mbed_official 324:406fd2029f23 193 * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
mbed_official 324:406fd2029f23 194 *
mbed_official 324:406fd2029f23 195 * Controls when the module master samples SIN in Modified Transfer Format. This
mbed_official 324:406fd2029f23 196 * field is valid only when CPHA bit in CTARn[CPHA] is 0.
mbed_official 324:406fd2029f23 197 *
mbed_official 324:406fd2029f23 198 * Values:
mbed_official 324:406fd2029f23 199 * - 00 - 0 protocol clock cycles between SCK edge and SIN sample
mbed_official 324:406fd2029f23 200 * - 01 - 1 protocol clock cycle between SCK edge and SIN sample
mbed_official 324:406fd2029f23 201 * - 10 - 2 protocol clock cycles between SCK edge and SIN sample
mbed_official 324:406fd2029f23 202 * - 11 - Reserved
mbed_official 324:406fd2029f23 203 */
mbed_official 324:406fd2029f23 204 /*@{*/
mbed_official 324:406fd2029f23 205 #define BP_SPI_MCR_SMPL_PT (8U) /*!< Bit position for SPI_MCR_SMPL_PT. */
mbed_official 324:406fd2029f23 206 #define BM_SPI_MCR_SMPL_PT (0x00000300U) /*!< Bit mask for SPI_MCR_SMPL_PT. */
mbed_official 324:406fd2029f23 207 #define BS_SPI_MCR_SMPL_PT (2U) /*!< Bit field size in bits for SPI_MCR_SMPL_PT. */
mbed_official 324:406fd2029f23 208
mbed_official 324:406fd2029f23 209 /*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
mbed_official 324:406fd2029f23 210 #define BR_SPI_MCR_SMPL_PT(x) (HW_SPI_MCR(x).B.SMPL_PT)
mbed_official 324:406fd2029f23 211
mbed_official 324:406fd2029f23 212 /*! @brief Format value for bitfield SPI_MCR_SMPL_PT. */
mbed_official 324:406fd2029f23 213 #define BF_SPI_MCR_SMPL_PT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_SMPL_PT) & BM_SPI_MCR_SMPL_PT)
mbed_official 324:406fd2029f23 214
mbed_official 324:406fd2029f23 215 /*! @brief Set the SMPL_PT field to a new value. */
mbed_official 324:406fd2029f23 216 #define BW_SPI_MCR_SMPL_PT(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_SMPL_PT) | BF_SPI_MCR_SMPL_PT(v)))
mbed_official 324:406fd2029f23 217 /*@}*/
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*!
mbed_official 324:406fd2029f23 220 * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
mbed_official 324:406fd2029f23 221 *
mbed_official 324:406fd2029f23 222 * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
mbed_official 324:406fd2029f23 223 * CLR_RXF bit is always read as zero.
mbed_official 324:406fd2029f23 224 *
mbed_official 324:406fd2029f23 225 * Values:
mbed_official 324:406fd2029f23 226 * - 0 - Do not clear the RX FIFO counter.
mbed_official 324:406fd2029f23 227 * - 1 - Clear the RX FIFO counter.
mbed_official 324:406fd2029f23 228 */
mbed_official 324:406fd2029f23 229 /*@{*/
mbed_official 324:406fd2029f23 230 #define BP_SPI_MCR_CLR_RXF (10U) /*!< Bit position for SPI_MCR_CLR_RXF. */
mbed_official 324:406fd2029f23 231 #define BM_SPI_MCR_CLR_RXF (0x00000400U) /*!< Bit mask for SPI_MCR_CLR_RXF. */
mbed_official 324:406fd2029f23 232 #define BS_SPI_MCR_CLR_RXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_RXF. */
mbed_official 324:406fd2029f23 233
mbed_official 324:406fd2029f23 234 /*! @brief Format value for bitfield SPI_MCR_CLR_RXF. */
mbed_official 324:406fd2029f23 235 #define BF_SPI_MCR_CLR_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_RXF) & BM_SPI_MCR_CLR_RXF)
mbed_official 324:406fd2029f23 236
mbed_official 324:406fd2029f23 237 /*! @brief Set the CLR_RXF field to a new value. */
mbed_official 324:406fd2029f23 238 #define BW_SPI_MCR_CLR_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_RXF) = (v))
mbed_official 324:406fd2029f23 239 /*@}*/
mbed_official 324:406fd2029f23 240
mbed_official 324:406fd2029f23 241 /*!
mbed_official 324:406fd2029f23 242 * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
mbed_official 324:406fd2029f23 243 *
mbed_official 324:406fd2029f23 244 * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
mbed_official 324:406fd2029f23 245 * CLR_TXF bit is always read as zero.
mbed_official 324:406fd2029f23 246 *
mbed_official 324:406fd2029f23 247 * Values:
mbed_official 324:406fd2029f23 248 * - 0 - Do not clear the TX FIFO counter.
mbed_official 324:406fd2029f23 249 * - 1 - Clear the TX FIFO counter.
mbed_official 324:406fd2029f23 250 */
mbed_official 324:406fd2029f23 251 /*@{*/
mbed_official 324:406fd2029f23 252 #define BP_SPI_MCR_CLR_TXF (11U) /*!< Bit position for SPI_MCR_CLR_TXF. */
mbed_official 324:406fd2029f23 253 #define BM_SPI_MCR_CLR_TXF (0x00000800U) /*!< Bit mask for SPI_MCR_CLR_TXF. */
mbed_official 324:406fd2029f23 254 #define BS_SPI_MCR_CLR_TXF (1U) /*!< Bit field size in bits for SPI_MCR_CLR_TXF. */
mbed_official 324:406fd2029f23 255
mbed_official 324:406fd2029f23 256 /*! @brief Format value for bitfield SPI_MCR_CLR_TXF. */
mbed_official 324:406fd2029f23 257 #define BF_SPI_MCR_CLR_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CLR_TXF) & BM_SPI_MCR_CLR_TXF)
mbed_official 324:406fd2029f23 258
mbed_official 324:406fd2029f23 259 /*! @brief Set the CLR_TXF field to a new value. */
mbed_official 324:406fd2029f23 260 #define BW_SPI_MCR_CLR_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CLR_TXF) = (v))
mbed_official 324:406fd2029f23 261 /*@}*/
mbed_official 324:406fd2029f23 262
mbed_official 324:406fd2029f23 263 /*!
mbed_official 324:406fd2029f23 264 * @name Register SPI_MCR, field DIS_RXF[12] (RW)
mbed_official 324:406fd2029f23 265 *
mbed_official 324:406fd2029f23 266 * When the RX FIFO is disabled, the receive part of the module operates as a
mbed_official 324:406fd2029f23 267 * simplified double-buffered SPI. This bit can only be written when the MDIS bit
mbed_official 324:406fd2029f23 268 * is cleared.
mbed_official 324:406fd2029f23 269 *
mbed_official 324:406fd2029f23 270 * Values:
mbed_official 324:406fd2029f23 271 * - 0 - RX FIFO is enabled.
mbed_official 324:406fd2029f23 272 * - 1 - RX FIFO is disabled.
mbed_official 324:406fd2029f23 273 */
mbed_official 324:406fd2029f23 274 /*@{*/
mbed_official 324:406fd2029f23 275 #define BP_SPI_MCR_DIS_RXF (12U) /*!< Bit position for SPI_MCR_DIS_RXF. */
mbed_official 324:406fd2029f23 276 #define BM_SPI_MCR_DIS_RXF (0x00001000U) /*!< Bit mask for SPI_MCR_DIS_RXF. */
mbed_official 324:406fd2029f23 277 #define BS_SPI_MCR_DIS_RXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_RXF. */
mbed_official 324:406fd2029f23 278
mbed_official 324:406fd2029f23 279 /*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
mbed_official 324:406fd2029f23 280 #define BR_SPI_MCR_DIS_RXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF))
mbed_official 324:406fd2029f23 281
mbed_official 324:406fd2029f23 282 /*! @brief Format value for bitfield SPI_MCR_DIS_RXF. */
mbed_official 324:406fd2029f23 283 #define BF_SPI_MCR_DIS_RXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_RXF) & BM_SPI_MCR_DIS_RXF)
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*! @brief Set the DIS_RXF field to a new value. */
mbed_official 324:406fd2029f23 286 #define BW_SPI_MCR_DIS_RXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_RXF) = (v))
mbed_official 324:406fd2029f23 287 /*@}*/
mbed_official 324:406fd2029f23 288
mbed_official 324:406fd2029f23 289 /*!
mbed_official 324:406fd2029f23 290 * @name Register SPI_MCR, field DIS_TXF[13] (RW)
mbed_official 324:406fd2029f23 291 *
mbed_official 324:406fd2029f23 292 * When the TX FIFO is disabled, the transmit part of the module operates as a
mbed_official 324:406fd2029f23 293 * simplified double-buffered SPI. This bit can be written only when the MDIS bit
mbed_official 324:406fd2029f23 294 * is cleared.
mbed_official 324:406fd2029f23 295 *
mbed_official 324:406fd2029f23 296 * Values:
mbed_official 324:406fd2029f23 297 * - 0 - TX FIFO is enabled.
mbed_official 324:406fd2029f23 298 * - 1 - TX FIFO is disabled.
mbed_official 324:406fd2029f23 299 */
mbed_official 324:406fd2029f23 300 /*@{*/
mbed_official 324:406fd2029f23 301 #define BP_SPI_MCR_DIS_TXF (13U) /*!< Bit position for SPI_MCR_DIS_TXF. */
mbed_official 324:406fd2029f23 302 #define BM_SPI_MCR_DIS_TXF (0x00002000U) /*!< Bit mask for SPI_MCR_DIS_TXF. */
mbed_official 324:406fd2029f23 303 #define BS_SPI_MCR_DIS_TXF (1U) /*!< Bit field size in bits for SPI_MCR_DIS_TXF. */
mbed_official 324:406fd2029f23 304
mbed_official 324:406fd2029f23 305 /*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
mbed_official 324:406fd2029f23 306 #define BR_SPI_MCR_DIS_TXF(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF))
mbed_official 324:406fd2029f23 307
mbed_official 324:406fd2029f23 308 /*! @brief Format value for bitfield SPI_MCR_DIS_TXF. */
mbed_official 324:406fd2029f23 309 #define BF_SPI_MCR_DIS_TXF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DIS_TXF) & BM_SPI_MCR_DIS_TXF)
mbed_official 324:406fd2029f23 310
mbed_official 324:406fd2029f23 311 /*! @brief Set the DIS_TXF field to a new value. */
mbed_official 324:406fd2029f23 312 #define BW_SPI_MCR_DIS_TXF(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DIS_TXF) = (v))
mbed_official 324:406fd2029f23 313 /*@}*/
mbed_official 324:406fd2029f23 314
mbed_official 324:406fd2029f23 315 /*!
mbed_official 324:406fd2029f23 316 * @name Register SPI_MCR, field MDIS[14] (RW)
mbed_official 324:406fd2029f23 317 *
mbed_official 324:406fd2029f23 318 * Allows the clock to be stopped to the non-memory mapped logic in the module
mbed_official 324:406fd2029f23 319 * effectively putting it in a software-controlled power-saving state. The reset
mbed_official 324:406fd2029f23 320 * value of the MDIS bit is parameterized, with a default reset value of 0. When
mbed_official 324:406fd2029f23 321 * the module is used in Slave Mode, we recommend leaving this bit 0, because a
mbed_official 324:406fd2029f23 322 * slave doesn't have control over master transactions.
mbed_official 324:406fd2029f23 323 *
mbed_official 324:406fd2029f23 324 * Values:
mbed_official 324:406fd2029f23 325 * - 0 - Enables the module clocks.
mbed_official 324:406fd2029f23 326 * - 1 - Allows external logic to disable the module clocks.
mbed_official 324:406fd2029f23 327 */
mbed_official 324:406fd2029f23 328 /*@{*/
mbed_official 324:406fd2029f23 329 #define BP_SPI_MCR_MDIS (14U) /*!< Bit position for SPI_MCR_MDIS. */
mbed_official 324:406fd2029f23 330 #define BM_SPI_MCR_MDIS (0x00004000U) /*!< Bit mask for SPI_MCR_MDIS. */
mbed_official 324:406fd2029f23 331 #define BS_SPI_MCR_MDIS (1U) /*!< Bit field size in bits for SPI_MCR_MDIS. */
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 /*! @brief Read current value of the SPI_MCR_MDIS field. */
mbed_official 324:406fd2029f23 334 #define BR_SPI_MCR_MDIS(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS))
mbed_official 324:406fd2029f23 335
mbed_official 324:406fd2029f23 336 /*! @brief Format value for bitfield SPI_MCR_MDIS. */
mbed_official 324:406fd2029f23 337 #define BF_SPI_MCR_MDIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MDIS) & BM_SPI_MCR_MDIS)
mbed_official 324:406fd2029f23 338
mbed_official 324:406fd2029f23 339 /*! @brief Set the MDIS field to a new value. */
mbed_official 324:406fd2029f23 340 #define BW_SPI_MCR_MDIS(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MDIS) = (v))
mbed_official 324:406fd2029f23 341 /*@}*/
mbed_official 324:406fd2029f23 342
mbed_official 324:406fd2029f23 343 /*!
mbed_official 324:406fd2029f23 344 * @name Register SPI_MCR, field DOZE[15] (RW)
mbed_official 324:406fd2029f23 345 *
mbed_official 324:406fd2029f23 346 * Provides support for an externally controlled Doze mode power-saving
mbed_official 324:406fd2029f23 347 * mechanism.
mbed_official 324:406fd2029f23 348 *
mbed_official 324:406fd2029f23 349 * Values:
mbed_official 324:406fd2029f23 350 * - 0 - Doze mode has no effect on the module.
mbed_official 324:406fd2029f23 351 * - 1 - Doze mode disables the module.
mbed_official 324:406fd2029f23 352 */
mbed_official 324:406fd2029f23 353 /*@{*/
mbed_official 324:406fd2029f23 354 #define BP_SPI_MCR_DOZE (15U) /*!< Bit position for SPI_MCR_DOZE. */
mbed_official 324:406fd2029f23 355 #define BM_SPI_MCR_DOZE (0x00008000U) /*!< Bit mask for SPI_MCR_DOZE. */
mbed_official 324:406fd2029f23 356 #define BS_SPI_MCR_DOZE (1U) /*!< Bit field size in bits for SPI_MCR_DOZE. */
mbed_official 324:406fd2029f23 357
mbed_official 324:406fd2029f23 358 /*! @brief Read current value of the SPI_MCR_DOZE field. */
mbed_official 324:406fd2029f23 359 #define BR_SPI_MCR_DOZE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE))
mbed_official 324:406fd2029f23 360
mbed_official 324:406fd2029f23 361 /*! @brief Format value for bitfield SPI_MCR_DOZE. */
mbed_official 324:406fd2029f23 362 #define BF_SPI_MCR_DOZE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_DOZE) & BM_SPI_MCR_DOZE)
mbed_official 324:406fd2029f23 363
mbed_official 324:406fd2029f23 364 /*! @brief Set the DOZE field to a new value. */
mbed_official 324:406fd2029f23 365 #define BW_SPI_MCR_DOZE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_DOZE) = (v))
mbed_official 324:406fd2029f23 366 /*@}*/
mbed_official 324:406fd2029f23 367
mbed_official 324:406fd2029f23 368 /*!
mbed_official 324:406fd2029f23 369 * @name Register SPI_MCR, field PCSIS[21:16] (RW)
mbed_official 324:406fd2029f23 370 *
mbed_official 324:406fd2029f23 371 * Determines the inactive state of PCSx.
mbed_official 324:406fd2029f23 372 *
mbed_official 324:406fd2029f23 373 * Values:
mbed_official 324:406fd2029f23 374 * - 0 - The inactive state of PCSx is low.
mbed_official 324:406fd2029f23 375 * - 1 - The inactive state of PCSx is high.
mbed_official 324:406fd2029f23 376 */
mbed_official 324:406fd2029f23 377 /*@{*/
mbed_official 324:406fd2029f23 378 #define BP_SPI_MCR_PCSIS (16U) /*!< Bit position for SPI_MCR_PCSIS. */
mbed_official 324:406fd2029f23 379 #define BM_SPI_MCR_PCSIS (0x003F0000U) /*!< Bit mask for SPI_MCR_PCSIS. */
mbed_official 324:406fd2029f23 380 #define BS_SPI_MCR_PCSIS (6U) /*!< Bit field size in bits for SPI_MCR_PCSIS. */
mbed_official 324:406fd2029f23 381
mbed_official 324:406fd2029f23 382 /*! @brief Read current value of the SPI_MCR_PCSIS field. */
mbed_official 324:406fd2029f23 383 #define BR_SPI_MCR_PCSIS(x) (HW_SPI_MCR(x).B.PCSIS)
mbed_official 324:406fd2029f23 384
mbed_official 324:406fd2029f23 385 /*! @brief Format value for bitfield SPI_MCR_PCSIS. */
mbed_official 324:406fd2029f23 386 #define BF_SPI_MCR_PCSIS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSIS) & BM_SPI_MCR_PCSIS)
mbed_official 324:406fd2029f23 387
mbed_official 324:406fd2029f23 388 /*! @brief Set the PCSIS field to a new value. */
mbed_official 324:406fd2029f23 389 #define BW_SPI_MCR_PCSIS(x, v) (HW_SPI_MCR_WR(x, (HW_SPI_MCR_RD(x) & ~BM_SPI_MCR_PCSIS) | BF_SPI_MCR_PCSIS(v)))
mbed_official 324:406fd2029f23 390 /*@}*/
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392 /*!
mbed_official 324:406fd2029f23 393 * @name Register SPI_MCR, field ROOE[24] (RW)
mbed_official 324:406fd2029f23 394 *
mbed_official 324:406fd2029f23 395 * In the RX FIFO overflow condition, configures the module to ignore the
mbed_official 324:406fd2029f23 396 * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
mbed_official 324:406fd2029f23 397 * is received, the data from the transfer, generating the overflow, is ignored
mbed_official 324:406fd2029f23 398 * or shifted into the shift register.
mbed_official 324:406fd2029f23 399 *
mbed_official 324:406fd2029f23 400 * Values:
mbed_official 324:406fd2029f23 401 * - 0 - Incoming data is ignored.
mbed_official 324:406fd2029f23 402 * - 1 - Incoming data is shifted into the shift register.
mbed_official 324:406fd2029f23 403 */
mbed_official 324:406fd2029f23 404 /*@{*/
mbed_official 324:406fd2029f23 405 #define BP_SPI_MCR_ROOE (24U) /*!< Bit position for SPI_MCR_ROOE. */
mbed_official 324:406fd2029f23 406 #define BM_SPI_MCR_ROOE (0x01000000U) /*!< Bit mask for SPI_MCR_ROOE. */
mbed_official 324:406fd2029f23 407 #define BS_SPI_MCR_ROOE (1U) /*!< Bit field size in bits for SPI_MCR_ROOE. */
mbed_official 324:406fd2029f23 408
mbed_official 324:406fd2029f23 409 /*! @brief Read current value of the SPI_MCR_ROOE field. */
mbed_official 324:406fd2029f23 410 #define BR_SPI_MCR_ROOE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE))
mbed_official 324:406fd2029f23 411
mbed_official 324:406fd2029f23 412 /*! @brief Format value for bitfield SPI_MCR_ROOE. */
mbed_official 324:406fd2029f23 413 #define BF_SPI_MCR_ROOE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_ROOE) & BM_SPI_MCR_ROOE)
mbed_official 324:406fd2029f23 414
mbed_official 324:406fd2029f23 415 /*! @brief Set the ROOE field to a new value. */
mbed_official 324:406fd2029f23 416 #define BW_SPI_MCR_ROOE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_ROOE) = (v))
mbed_official 324:406fd2029f23 417 /*@}*/
mbed_official 324:406fd2029f23 418
mbed_official 324:406fd2029f23 419 /*!
mbed_official 324:406fd2029f23 420 * @name Register SPI_MCR, field PCSSE[25] (RW)
mbed_official 324:406fd2029f23 421 *
mbed_official 324:406fd2029f23 422 * Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
mbed_official 324:406fd2029f23 423 *
mbed_official 324:406fd2029f23 424 * Values:
mbed_official 324:406fd2029f23 425 * - 0 - PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
mbed_official 324:406fd2029f23 426 * - 1 - PCS5/ PCSS is used as an active-low PCS Strobe signal.
mbed_official 324:406fd2029f23 427 */
mbed_official 324:406fd2029f23 428 /*@{*/
mbed_official 324:406fd2029f23 429 #define BP_SPI_MCR_PCSSE (25U) /*!< Bit position for SPI_MCR_PCSSE. */
mbed_official 324:406fd2029f23 430 #define BM_SPI_MCR_PCSSE (0x02000000U) /*!< Bit mask for SPI_MCR_PCSSE. */
mbed_official 324:406fd2029f23 431 #define BS_SPI_MCR_PCSSE (1U) /*!< Bit field size in bits for SPI_MCR_PCSSE. */
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Read current value of the SPI_MCR_PCSSE field. */
mbed_official 324:406fd2029f23 434 #define BR_SPI_MCR_PCSSE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE))
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*! @brief Format value for bitfield SPI_MCR_PCSSE. */
mbed_official 324:406fd2029f23 437 #define BF_SPI_MCR_PCSSE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_PCSSE) & BM_SPI_MCR_PCSSE)
mbed_official 324:406fd2029f23 438
mbed_official 324:406fd2029f23 439 /*! @brief Set the PCSSE field to a new value. */
mbed_official 324:406fd2029f23 440 #define BW_SPI_MCR_PCSSE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_PCSSE) = (v))
mbed_official 324:406fd2029f23 441 /*@}*/
mbed_official 324:406fd2029f23 442
mbed_official 324:406fd2029f23 443 /*!
mbed_official 324:406fd2029f23 444 * @name Register SPI_MCR, field MTFE[26] (RW)
mbed_official 324:406fd2029f23 445 *
mbed_official 324:406fd2029f23 446 * Enables a modified transfer format to be used.
mbed_official 324:406fd2029f23 447 *
mbed_official 324:406fd2029f23 448 * Values:
mbed_official 324:406fd2029f23 449 * - 0 - Modified SPI transfer format disabled.
mbed_official 324:406fd2029f23 450 * - 1 - Modified SPI transfer format enabled.
mbed_official 324:406fd2029f23 451 */
mbed_official 324:406fd2029f23 452 /*@{*/
mbed_official 324:406fd2029f23 453 #define BP_SPI_MCR_MTFE (26U) /*!< Bit position for SPI_MCR_MTFE. */
mbed_official 324:406fd2029f23 454 #define BM_SPI_MCR_MTFE (0x04000000U) /*!< Bit mask for SPI_MCR_MTFE. */
mbed_official 324:406fd2029f23 455 #define BS_SPI_MCR_MTFE (1U) /*!< Bit field size in bits for SPI_MCR_MTFE. */
mbed_official 324:406fd2029f23 456
mbed_official 324:406fd2029f23 457 /*! @brief Read current value of the SPI_MCR_MTFE field. */
mbed_official 324:406fd2029f23 458 #define BR_SPI_MCR_MTFE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE))
mbed_official 324:406fd2029f23 459
mbed_official 324:406fd2029f23 460 /*! @brief Format value for bitfield SPI_MCR_MTFE. */
mbed_official 324:406fd2029f23 461 #define BF_SPI_MCR_MTFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MTFE) & BM_SPI_MCR_MTFE)
mbed_official 324:406fd2029f23 462
mbed_official 324:406fd2029f23 463 /*! @brief Set the MTFE field to a new value. */
mbed_official 324:406fd2029f23 464 #define BW_SPI_MCR_MTFE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MTFE) = (v))
mbed_official 324:406fd2029f23 465 /*@}*/
mbed_official 324:406fd2029f23 466
mbed_official 324:406fd2029f23 467 /*!
mbed_official 324:406fd2029f23 468 * @name Register SPI_MCR, field FRZ[27] (RW)
mbed_official 324:406fd2029f23 469 *
mbed_official 324:406fd2029f23 470 * Enables transfers to be stopped on the next frame boundary when the device
mbed_official 324:406fd2029f23 471 * enters Debug mode.
mbed_official 324:406fd2029f23 472 *
mbed_official 324:406fd2029f23 473 * Values:
mbed_official 324:406fd2029f23 474 * - 0 - Do not halt serial transfers in Debug mode.
mbed_official 324:406fd2029f23 475 * - 1 - Halt serial transfers in Debug mode.
mbed_official 324:406fd2029f23 476 */
mbed_official 324:406fd2029f23 477 /*@{*/
mbed_official 324:406fd2029f23 478 #define BP_SPI_MCR_FRZ (27U) /*!< Bit position for SPI_MCR_FRZ. */
mbed_official 324:406fd2029f23 479 #define BM_SPI_MCR_FRZ (0x08000000U) /*!< Bit mask for SPI_MCR_FRZ. */
mbed_official 324:406fd2029f23 480 #define BS_SPI_MCR_FRZ (1U) /*!< Bit field size in bits for SPI_MCR_FRZ. */
mbed_official 324:406fd2029f23 481
mbed_official 324:406fd2029f23 482 /*! @brief Read current value of the SPI_MCR_FRZ field. */
mbed_official 324:406fd2029f23 483 #define BR_SPI_MCR_FRZ(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ))
mbed_official 324:406fd2029f23 484
mbed_official 324:406fd2029f23 485 /*! @brief Format value for bitfield SPI_MCR_FRZ. */
mbed_official 324:406fd2029f23 486 #define BF_SPI_MCR_FRZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_FRZ) & BM_SPI_MCR_FRZ)
mbed_official 324:406fd2029f23 487
mbed_official 324:406fd2029f23 488 /*! @brief Set the FRZ field to a new value. */
mbed_official 324:406fd2029f23 489 #define BW_SPI_MCR_FRZ(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_FRZ) = (v))
mbed_official 324:406fd2029f23 490 /*@}*/
mbed_official 324:406fd2029f23 491
mbed_official 324:406fd2029f23 492 /*!
mbed_official 324:406fd2029f23 493 * @name Register SPI_MCR, field DCONF[29:28] (RO)
mbed_official 324:406fd2029f23 494 *
mbed_official 324:406fd2029f23 495 * Selects among the different configurations of the module.
mbed_official 324:406fd2029f23 496 *
mbed_official 324:406fd2029f23 497 * Values:
mbed_official 324:406fd2029f23 498 * - 00 - SPI
mbed_official 324:406fd2029f23 499 * - 01 - Reserved
mbed_official 324:406fd2029f23 500 * - 10 - Reserved
mbed_official 324:406fd2029f23 501 * - 11 - Reserved
mbed_official 324:406fd2029f23 502 */
mbed_official 324:406fd2029f23 503 /*@{*/
mbed_official 324:406fd2029f23 504 #define BP_SPI_MCR_DCONF (28U) /*!< Bit position for SPI_MCR_DCONF. */
mbed_official 324:406fd2029f23 505 #define BM_SPI_MCR_DCONF (0x30000000U) /*!< Bit mask for SPI_MCR_DCONF. */
mbed_official 324:406fd2029f23 506 #define BS_SPI_MCR_DCONF (2U) /*!< Bit field size in bits for SPI_MCR_DCONF. */
mbed_official 324:406fd2029f23 507
mbed_official 324:406fd2029f23 508 /*! @brief Read current value of the SPI_MCR_DCONF field. */
mbed_official 324:406fd2029f23 509 #define BR_SPI_MCR_DCONF(x) (HW_SPI_MCR(x).B.DCONF)
mbed_official 324:406fd2029f23 510 /*@}*/
mbed_official 324:406fd2029f23 511
mbed_official 324:406fd2029f23 512 /*!
mbed_official 324:406fd2029f23 513 * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
mbed_official 324:406fd2029f23 514 *
mbed_official 324:406fd2029f23 515 * Enables the Serial Communication Clock (SCK) to run continuously.
mbed_official 324:406fd2029f23 516 *
mbed_official 324:406fd2029f23 517 * Values:
mbed_official 324:406fd2029f23 518 * - 0 - Continuous SCK disabled.
mbed_official 324:406fd2029f23 519 * - 1 - Continuous SCK enabled.
mbed_official 324:406fd2029f23 520 */
mbed_official 324:406fd2029f23 521 /*@{*/
mbed_official 324:406fd2029f23 522 #define BP_SPI_MCR_CONT_SCKE (30U) /*!< Bit position for SPI_MCR_CONT_SCKE. */
mbed_official 324:406fd2029f23 523 #define BM_SPI_MCR_CONT_SCKE (0x40000000U) /*!< Bit mask for SPI_MCR_CONT_SCKE. */
mbed_official 324:406fd2029f23 524 #define BS_SPI_MCR_CONT_SCKE (1U) /*!< Bit field size in bits for SPI_MCR_CONT_SCKE. */
mbed_official 324:406fd2029f23 525
mbed_official 324:406fd2029f23 526 /*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
mbed_official 324:406fd2029f23 527 #define BR_SPI_MCR_CONT_SCKE(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE))
mbed_official 324:406fd2029f23 528
mbed_official 324:406fd2029f23 529 /*! @brief Format value for bitfield SPI_MCR_CONT_SCKE. */
mbed_official 324:406fd2029f23 530 #define BF_SPI_MCR_CONT_SCKE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_CONT_SCKE) & BM_SPI_MCR_CONT_SCKE)
mbed_official 324:406fd2029f23 531
mbed_official 324:406fd2029f23 532 /*! @brief Set the CONT_SCKE field to a new value. */
mbed_official 324:406fd2029f23 533 #define BW_SPI_MCR_CONT_SCKE(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_CONT_SCKE) = (v))
mbed_official 324:406fd2029f23 534 /*@}*/
mbed_official 324:406fd2029f23 535
mbed_official 324:406fd2029f23 536 /*!
mbed_official 324:406fd2029f23 537 * @name Register SPI_MCR, field MSTR[31] (RW)
mbed_official 324:406fd2029f23 538 *
mbed_official 324:406fd2029f23 539 * Enables either Master mode (if supported) or Slave mode (if supported)
mbed_official 324:406fd2029f23 540 * operation.
mbed_official 324:406fd2029f23 541 *
mbed_official 324:406fd2029f23 542 * Values:
mbed_official 324:406fd2029f23 543 * - 0 - Enables Slave mode
mbed_official 324:406fd2029f23 544 * - 1 - Enables Master mode
mbed_official 324:406fd2029f23 545 */
mbed_official 324:406fd2029f23 546 /*@{*/
mbed_official 324:406fd2029f23 547 #define BP_SPI_MCR_MSTR (31U) /*!< Bit position for SPI_MCR_MSTR. */
mbed_official 324:406fd2029f23 548 #define BM_SPI_MCR_MSTR (0x80000000U) /*!< Bit mask for SPI_MCR_MSTR. */
mbed_official 324:406fd2029f23 549 #define BS_SPI_MCR_MSTR (1U) /*!< Bit field size in bits for SPI_MCR_MSTR. */
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 /*! @brief Read current value of the SPI_MCR_MSTR field. */
mbed_official 324:406fd2029f23 552 #define BR_SPI_MCR_MSTR(x) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR))
mbed_official 324:406fd2029f23 553
mbed_official 324:406fd2029f23 554 /*! @brief Format value for bitfield SPI_MCR_MSTR. */
mbed_official 324:406fd2029f23 555 #define BF_SPI_MCR_MSTR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_MCR_MSTR) & BM_SPI_MCR_MSTR)
mbed_official 324:406fd2029f23 556
mbed_official 324:406fd2029f23 557 /*! @brief Set the MSTR field to a new value. */
mbed_official 324:406fd2029f23 558 #define BW_SPI_MCR_MSTR(x, v) (BITBAND_ACCESS32(HW_SPI_MCR_ADDR(x), BP_SPI_MCR_MSTR) = (v))
mbed_official 324:406fd2029f23 559 /*@}*/
mbed_official 324:406fd2029f23 560
mbed_official 324:406fd2029f23 561 /*******************************************************************************
mbed_official 324:406fd2029f23 562 * HW_SPI_TCR - Transfer Count Register
mbed_official 324:406fd2029f23 563 ******************************************************************************/
mbed_official 324:406fd2029f23 564
mbed_official 324:406fd2029f23 565 /*!
mbed_official 324:406fd2029f23 566 * @brief HW_SPI_TCR - Transfer Count Register (RW)
mbed_official 324:406fd2029f23 567 *
mbed_official 324:406fd2029f23 568 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 569 *
mbed_official 324:406fd2029f23 570 * TCR contains a counter that indicates the number of SPI transfers made. The
mbed_official 324:406fd2029f23 571 * transfer counter is intended to assist in queue management. Do not write the
mbed_official 324:406fd2029f23 572 * TCR when the module is in the Running state.
mbed_official 324:406fd2029f23 573 */
mbed_official 324:406fd2029f23 574 typedef union _hw_spi_tcr
mbed_official 324:406fd2029f23 575 {
mbed_official 324:406fd2029f23 576 uint32_t U;
mbed_official 324:406fd2029f23 577 struct _hw_spi_tcr_bitfields
mbed_official 324:406fd2029f23 578 {
mbed_official 324:406fd2029f23 579 uint32_t RESERVED0 : 16; /*!< [15:0] */
mbed_official 324:406fd2029f23 580 uint32_t SPI_TCNT : 16; /*!< [31:16] SPI Transfer Counter */
mbed_official 324:406fd2029f23 581 } B;
mbed_official 324:406fd2029f23 582 } hw_spi_tcr_t;
mbed_official 324:406fd2029f23 583
mbed_official 324:406fd2029f23 584 /*!
mbed_official 324:406fd2029f23 585 * @name Constants and macros for entire SPI_TCR register
mbed_official 324:406fd2029f23 586 */
mbed_official 324:406fd2029f23 587 /*@{*/
mbed_official 324:406fd2029f23 588 #define HW_SPI_TCR_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 589
mbed_official 324:406fd2029f23 590 #define HW_SPI_TCR(x) (*(__IO hw_spi_tcr_t *) HW_SPI_TCR_ADDR(x))
mbed_official 324:406fd2029f23 591 #define HW_SPI_TCR_RD(x) (HW_SPI_TCR(x).U)
mbed_official 324:406fd2029f23 592 #define HW_SPI_TCR_WR(x, v) (HW_SPI_TCR(x).U = (v))
mbed_official 324:406fd2029f23 593 #define HW_SPI_TCR_SET(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) | (v)))
mbed_official 324:406fd2029f23 594 #define HW_SPI_TCR_CLR(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 595 #define HW_SPI_TCR_TOG(x, v) (HW_SPI_TCR_WR(x, HW_SPI_TCR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 596 /*@}*/
mbed_official 324:406fd2029f23 597
mbed_official 324:406fd2029f23 598 /*
mbed_official 324:406fd2029f23 599 * Constants & macros for individual SPI_TCR bitfields
mbed_official 324:406fd2029f23 600 */
mbed_official 324:406fd2029f23 601
mbed_official 324:406fd2029f23 602 /*!
mbed_official 324:406fd2029f23 603 * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
mbed_official 324:406fd2029f23 604 *
mbed_official 324:406fd2029f23 605 * Counts the number of SPI transfers the module makes. The SPI_TCNT field
mbed_official 324:406fd2029f23 606 * increments every time the last bit of an SPI frame is transmitted. A value written
mbed_official 324:406fd2029f23 607 * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
mbed_official 324:406fd2029f23 608 * the beginning of the frame when the CTCNT field is set in the executing SPI
mbed_official 324:406fd2029f23 609 * command. The Transfer Counter wraps around; incrementing the counter past 65535
mbed_official 324:406fd2029f23 610 * resets the counter to zero.
mbed_official 324:406fd2029f23 611 */
mbed_official 324:406fd2029f23 612 /*@{*/
mbed_official 324:406fd2029f23 613 #define BP_SPI_TCR_SPI_TCNT (16U) /*!< Bit position for SPI_TCR_SPI_TCNT. */
mbed_official 324:406fd2029f23 614 #define BM_SPI_TCR_SPI_TCNT (0xFFFF0000U) /*!< Bit mask for SPI_TCR_SPI_TCNT. */
mbed_official 324:406fd2029f23 615 #define BS_SPI_TCR_SPI_TCNT (16U) /*!< Bit field size in bits for SPI_TCR_SPI_TCNT. */
mbed_official 324:406fd2029f23 616
mbed_official 324:406fd2029f23 617 /*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
mbed_official 324:406fd2029f23 618 #define BR_SPI_TCR_SPI_TCNT(x) (HW_SPI_TCR(x).B.SPI_TCNT)
mbed_official 324:406fd2029f23 619
mbed_official 324:406fd2029f23 620 /*! @brief Format value for bitfield SPI_TCR_SPI_TCNT. */
mbed_official 324:406fd2029f23 621 #define BF_SPI_TCR_SPI_TCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_TCR_SPI_TCNT) & BM_SPI_TCR_SPI_TCNT)
mbed_official 324:406fd2029f23 622
mbed_official 324:406fd2029f23 623 /*! @brief Set the SPI_TCNT field to a new value. */
mbed_official 324:406fd2029f23 624 #define BW_SPI_TCR_SPI_TCNT(x, v) (HW_SPI_TCR_WR(x, (HW_SPI_TCR_RD(x) & ~BM_SPI_TCR_SPI_TCNT) | BF_SPI_TCR_SPI_TCNT(v)))
mbed_official 324:406fd2029f23 625 /*@}*/
mbed_official 324:406fd2029f23 626
mbed_official 324:406fd2029f23 627 /*******************************************************************************
mbed_official 324:406fd2029f23 628 * HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode)
mbed_official 324:406fd2029f23 629 ******************************************************************************/
mbed_official 324:406fd2029f23 630
mbed_official 324:406fd2029f23 631 /*!
mbed_official 324:406fd2029f23 632 * @brief HW_SPI_CTARn - Clock and Transfer Attributes Register (In Master Mode) (RW)
mbed_official 324:406fd2029f23 633 *
mbed_official 324:406fd2029f23 634 * Reset value: 0x78000000U
mbed_official 324:406fd2029f23 635 *
mbed_official 324:406fd2029f23 636 * CTAR registers are used to define different transfer attributes. Do not write
mbed_official 324:406fd2029f23 637 * to the CTAR registers while the module is in the Running state. In Master
mbed_official 324:406fd2029f23 638 * mode, the CTAR registers define combinations of transfer attributes such as frame
mbed_official 324:406fd2029f23 639 * size, clock phase and polarity, data bit ordering, baud rate, and various
mbed_official 324:406fd2029f23 640 * delays. In slave mode, a subset of the bitfields in CTAR0 are used to set the
mbed_official 324:406fd2029f23 641 * slave transfer attributes. When the module is configured as an SPI master, the
mbed_official 324:406fd2029f23 642 * CTAS field in the command portion of the TX FIFO entry selects which of the CTAR
mbed_official 324:406fd2029f23 643 * registers is used. When the module is configured as an SPI bus slave, it uses
mbed_official 324:406fd2029f23 644 * the CTAR0 register.
mbed_official 324:406fd2029f23 645 */
mbed_official 324:406fd2029f23 646 typedef union _hw_spi_ctarn
mbed_official 324:406fd2029f23 647 {
mbed_official 324:406fd2029f23 648 uint32_t U;
mbed_official 324:406fd2029f23 649 struct _hw_spi_ctarn_bitfields
mbed_official 324:406fd2029f23 650 {
mbed_official 324:406fd2029f23 651 uint32_t BR : 4; /*!< [3:0] Baud Rate Scaler */
mbed_official 324:406fd2029f23 652 uint32_t DT : 4; /*!< [7:4] Delay After Transfer Scaler */
mbed_official 324:406fd2029f23 653 uint32_t ASC : 4; /*!< [11:8] After SCK Delay Scaler */
mbed_official 324:406fd2029f23 654 uint32_t CSSCK : 4; /*!< [15:12] PCS to SCK Delay Scaler */
mbed_official 324:406fd2029f23 655 uint32_t PBR : 2; /*!< [17:16] Baud Rate Prescaler */
mbed_official 324:406fd2029f23 656 uint32_t PDT : 2; /*!< [19:18] Delay after Transfer Prescaler */
mbed_official 324:406fd2029f23 657 uint32_t PASC : 2; /*!< [21:20] After SCK Delay Prescaler */
mbed_official 324:406fd2029f23 658 uint32_t PCSSCK : 2; /*!< [23:22] PCS to SCK Delay Prescaler */
mbed_official 324:406fd2029f23 659 uint32_t LSBFE : 1; /*!< [24] LSB First */
mbed_official 324:406fd2029f23 660 uint32_t CPHA : 1; /*!< [25] Clock Phase */
mbed_official 324:406fd2029f23 661 uint32_t CPOL : 1; /*!< [26] Clock Polarity */
mbed_official 324:406fd2029f23 662 uint32_t FMSZ : 4; /*!< [30:27] Frame Size */
mbed_official 324:406fd2029f23 663 uint32_t DBR : 1; /*!< [31] Double Baud Rate */
mbed_official 324:406fd2029f23 664 } B;
mbed_official 324:406fd2029f23 665 } hw_spi_ctarn_t;
mbed_official 324:406fd2029f23 666
mbed_official 324:406fd2029f23 667 /*!
mbed_official 324:406fd2029f23 668 * @name Constants and macros for entire SPI_CTARn register
mbed_official 324:406fd2029f23 669 */
mbed_official 324:406fd2029f23 670 /*@{*/
mbed_official 324:406fd2029f23 671 #define HW_SPI_CTARn_COUNT (2U)
mbed_official 324:406fd2029f23 672
mbed_official 324:406fd2029f23 673 #define HW_SPI_CTARn_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
mbed_official 324:406fd2029f23 674
mbed_official 324:406fd2029f23 675 #define HW_SPI_CTARn(x, n) (*(__IO hw_spi_ctarn_t *) HW_SPI_CTARn_ADDR(x, n))
mbed_official 324:406fd2029f23 676 #define HW_SPI_CTARn_RD(x, n) (HW_SPI_CTARn(x, n).U)
mbed_official 324:406fd2029f23 677 #define HW_SPI_CTARn_WR(x, n, v) (HW_SPI_CTARn(x, n).U = (v))
mbed_official 324:406fd2029f23 678 #define HW_SPI_CTARn_SET(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 679 #define HW_SPI_CTARn_CLR(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 680 #define HW_SPI_CTARn_TOG(x, n, v) (HW_SPI_CTARn_WR(x, n, HW_SPI_CTARn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 681 /*@}*/
mbed_official 324:406fd2029f23 682
mbed_official 324:406fd2029f23 683 /*
mbed_official 324:406fd2029f23 684 * Constants & macros for individual SPI_CTARn bitfields
mbed_official 324:406fd2029f23 685 */
mbed_official 324:406fd2029f23 686
mbed_official 324:406fd2029f23 687 /*!
mbed_official 324:406fd2029f23 688 * @name Register SPI_CTARn, field BR[3:0] (RW)
mbed_official 324:406fd2029f23 689 *
mbed_official 324:406fd2029f23 690 * Selects the scaler value for the baud rate. This field is used only in master
mbed_official 324:406fd2029f23 691 * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
mbed_official 324:406fd2029f23 692 * generate the frequency of the SCK. The baud rate is computed according to the
mbed_official 324:406fd2029f23 693 * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
mbed_official 324:406fd2029f23 694 * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
mbed_official 324:406fd2029f23 695 * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
mbed_official 324:406fd2029f23 696 * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
mbed_official 324:406fd2029f23 697 */
mbed_official 324:406fd2029f23 698 /*@{*/
mbed_official 324:406fd2029f23 699 #define BP_SPI_CTARn_BR (0U) /*!< Bit position for SPI_CTARn_BR. */
mbed_official 324:406fd2029f23 700 #define BM_SPI_CTARn_BR (0x0000000FU) /*!< Bit mask for SPI_CTARn_BR. */
mbed_official 324:406fd2029f23 701 #define BS_SPI_CTARn_BR (4U) /*!< Bit field size in bits for SPI_CTARn_BR. */
mbed_official 324:406fd2029f23 702
mbed_official 324:406fd2029f23 703 /*! @brief Read current value of the SPI_CTARn_BR field. */
mbed_official 324:406fd2029f23 704 #define BR_SPI_CTARn_BR(x, n) (HW_SPI_CTARn(x, n).B.BR)
mbed_official 324:406fd2029f23 705
mbed_official 324:406fd2029f23 706 /*! @brief Format value for bitfield SPI_CTARn_BR. */
mbed_official 324:406fd2029f23 707 #define BF_SPI_CTARn_BR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_BR) & BM_SPI_CTARn_BR)
mbed_official 324:406fd2029f23 708
mbed_official 324:406fd2029f23 709 /*! @brief Set the BR field to a new value. */
mbed_official 324:406fd2029f23 710 #define BW_SPI_CTARn_BR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_BR) | BF_SPI_CTARn_BR(v)))
mbed_official 324:406fd2029f23 711 /*@}*/
mbed_official 324:406fd2029f23 712
mbed_official 324:406fd2029f23 713 /*!
mbed_official 324:406fd2029f23 714 * @name Register SPI_CTARn, field DT[7:4] (RW)
mbed_official 324:406fd2029f23 715 *
mbed_official 324:406fd2029f23 716 * Selects the Delay after Transfer Scaler. This field is used only in master
mbed_official 324:406fd2029f23 717 * mode. The Delay after Transfer is the time between the negation of the PCS
mbed_official 324:406fd2029f23 718 * signal at the end of a frame and the assertion of PCS at the beginning of the next
mbed_official 324:406fd2029f23 719 * frame. In the Continuous Serial Communications Clock operation, the DT value
mbed_official 324:406fd2029f23 720 * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
mbed_official 324:406fd2029f23 721 * protocol clock period, and it is computed according to the following
mbed_official 324:406fd2029f23 722 * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
mbed_official 324:406fd2029f23 723 * field description for scaler values.
mbed_official 324:406fd2029f23 724 */
mbed_official 324:406fd2029f23 725 /*@{*/
mbed_official 324:406fd2029f23 726 #define BP_SPI_CTARn_DT (4U) /*!< Bit position for SPI_CTARn_DT. */
mbed_official 324:406fd2029f23 727 #define BM_SPI_CTARn_DT (0x000000F0U) /*!< Bit mask for SPI_CTARn_DT. */
mbed_official 324:406fd2029f23 728 #define BS_SPI_CTARn_DT (4U) /*!< Bit field size in bits for SPI_CTARn_DT. */
mbed_official 324:406fd2029f23 729
mbed_official 324:406fd2029f23 730 /*! @brief Read current value of the SPI_CTARn_DT field. */
mbed_official 324:406fd2029f23 731 #define BR_SPI_CTARn_DT(x, n) (HW_SPI_CTARn(x, n).B.DT)
mbed_official 324:406fd2029f23 732
mbed_official 324:406fd2029f23 733 /*! @brief Format value for bitfield SPI_CTARn_DT. */
mbed_official 324:406fd2029f23 734 #define BF_SPI_CTARn_DT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DT) & BM_SPI_CTARn_DT)
mbed_official 324:406fd2029f23 735
mbed_official 324:406fd2029f23 736 /*! @brief Set the DT field to a new value. */
mbed_official 324:406fd2029f23 737 #define BW_SPI_CTARn_DT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_DT) | BF_SPI_CTARn_DT(v)))
mbed_official 324:406fd2029f23 738 /*@}*/
mbed_official 324:406fd2029f23 739
mbed_official 324:406fd2029f23 740 /*!
mbed_official 324:406fd2029f23 741 * @name Register SPI_CTARn, field ASC[11:8] (RW)
mbed_official 324:406fd2029f23 742 *
mbed_official 324:406fd2029f23 743 * Selects the scaler value for the After SCK Delay. This field is used only in
mbed_official 324:406fd2029f23 744 * master mode. The After SCK Delay is the delay between the last edge of SCK and
mbed_official 324:406fd2029f23 745 * the negation of PCS. The delay is a multiple of the protocol clock period,
mbed_official 324:406fd2029f23 746 * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
mbed_official 324:406fd2029f23 747 * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
mbed_official 324:406fd2029f23 748 * scaler values. Refer After SCK Delay (tASC ) for more details.
mbed_official 324:406fd2029f23 749 */
mbed_official 324:406fd2029f23 750 /*@{*/
mbed_official 324:406fd2029f23 751 #define BP_SPI_CTARn_ASC (8U) /*!< Bit position for SPI_CTARn_ASC. */
mbed_official 324:406fd2029f23 752 #define BM_SPI_CTARn_ASC (0x00000F00U) /*!< Bit mask for SPI_CTARn_ASC. */
mbed_official 324:406fd2029f23 753 #define BS_SPI_CTARn_ASC (4U) /*!< Bit field size in bits for SPI_CTARn_ASC. */
mbed_official 324:406fd2029f23 754
mbed_official 324:406fd2029f23 755 /*! @brief Read current value of the SPI_CTARn_ASC field. */
mbed_official 324:406fd2029f23 756 #define BR_SPI_CTARn_ASC(x, n) (HW_SPI_CTARn(x, n).B.ASC)
mbed_official 324:406fd2029f23 757
mbed_official 324:406fd2029f23 758 /*! @brief Format value for bitfield SPI_CTARn_ASC. */
mbed_official 324:406fd2029f23 759 #define BF_SPI_CTARn_ASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_ASC) & BM_SPI_CTARn_ASC)
mbed_official 324:406fd2029f23 760
mbed_official 324:406fd2029f23 761 /*! @brief Set the ASC field to a new value. */
mbed_official 324:406fd2029f23 762 #define BW_SPI_CTARn_ASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_ASC) | BF_SPI_CTARn_ASC(v)))
mbed_official 324:406fd2029f23 763 /*@}*/
mbed_official 324:406fd2029f23 764
mbed_official 324:406fd2029f23 765 /*!
mbed_official 324:406fd2029f23 766 * @name Register SPI_CTARn, field CSSCK[15:12] (RW)
mbed_official 324:406fd2029f23 767 *
mbed_official 324:406fd2029f23 768 * Selects the scaler value for the PCS to SCK delay. This field is used only in
mbed_official 324:406fd2029f23 769 * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
mbed_official 324:406fd2029f23 770 * and the first edge of the SCK. The delay is a multiple of the protocol clock
mbed_official 324:406fd2029f23 771 * period, and it is computed according to the following equation: t CSC = (1/fP )
mbed_official 324:406fd2029f23 772 * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
mbed_official 324:406fd2029f23 773 * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
mbed_official 324:406fd2029f23 774 * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
mbed_official 324:406fd2029f23 775 * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
mbed_official 324:406fd2029f23 776 * details.
mbed_official 324:406fd2029f23 777 */
mbed_official 324:406fd2029f23 778 /*@{*/
mbed_official 324:406fd2029f23 779 #define BP_SPI_CTARn_CSSCK (12U) /*!< Bit position for SPI_CTARn_CSSCK. */
mbed_official 324:406fd2029f23 780 #define BM_SPI_CTARn_CSSCK (0x0000F000U) /*!< Bit mask for SPI_CTARn_CSSCK. */
mbed_official 324:406fd2029f23 781 #define BS_SPI_CTARn_CSSCK (4U) /*!< Bit field size in bits for SPI_CTARn_CSSCK. */
mbed_official 324:406fd2029f23 782
mbed_official 324:406fd2029f23 783 /*! @brief Read current value of the SPI_CTARn_CSSCK field. */
mbed_official 324:406fd2029f23 784 #define BR_SPI_CTARn_CSSCK(x, n) (HW_SPI_CTARn(x, n).B.CSSCK)
mbed_official 324:406fd2029f23 785
mbed_official 324:406fd2029f23 786 /*! @brief Format value for bitfield SPI_CTARn_CSSCK. */
mbed_official 324:406fd2029f23 787 #define BF_SPI_CTARn_CSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CSSCK) & BM_SPI_CTARn_CSSCK)
mbed_official 324:406fd2029f23 788
mbed_official 324:406fd2029f23 789 /*! @brief Set the CSSCK field to a new value. */
mbed_official 324:406fd2029f23 790 #define BW_SPI_CTARn_CSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_CSSCK) | BF_SPI_CTARn_CSSCK(v)))
mbed_official 324:406fd2029f23 791 /*@}*/
mbed_official 324:406fd2029f23 792
mbed_official 324:406fd2029f23 793 /*!
mbed_official 324:406fd2029f23 794 * @name Register SPI_CTARn, field PBR[17:16] (RW)
mbed_official 324:406fd2029f23 795 *
mbed_official 324:406fd2029f23 796 * Selects the prescaler value for the baud rate. This field is used only in
mbed_official 324:406fd2029f23 797 * master mode. The baud rate is the frequency of the SCK. The protocol clock is
mbed_official 324:406fd2029f23 798 * divided by the prescaler value before the baud rate selection takes place. See
mbed_official 324:406fd2029f23 799 * the BR field description for details on how to compute the baud rate.
mbed_official 324:406fd2029f23 800 *
mbed_official 324:406fd2029f23 801 * Values:
mbed_official 324:406fd2029f23 802 * - 00 - Baud Rate Prescaler value is 2.
mbed_official 324:406fd2029f23 803 * - 01 - Baud Rate Prescaler value is 3.
mbed_official 324:406fd2029f23 804 * - 10 - Baud Rate Prescaler value is 5.
mbed_official 324:406fd2029f23 805 * - 11 - Baud Rate Prescaler value is 7.
mbed_official 324:406fd2029f23 806 */
mbed_official 324:406fd2029f23 807 /*@{*/
mbed_official 324:406fd2029f23 808 #define BP_SPI_CTARn_PBR (16U) /*!< Bit position for SPI_CTARn_PBR. */
mbed_official 324:406fd2029f23 809 #define BM_SPI_CTARn_PBR (0x00030000U) /*!< Bit mask for SPI_CTARn_PBR. */
mbed_official 324:406fd2029f23 810 #define BS_SPI_CTARn_PBR (2U) /*!< Bit field size in bits for SPI_CTARn_PBR. */
mbed_official 324:406fd2029f23 811
mbed_official 324:406fd2029f23 812 /*! @brief Read current value of the SPI_CTARn_PBR field. */
mbed_official 324:406fd2029f23 813 #define BR_SPI_CTARn_PBR(x, n) (HW_SPI_CTARn(x, n).B.PBR)
mbed_official 324:406fd2029f23 814
mbed_official 324:406fd2029f23 815 /*! @brief Format value for bitfield SPI_CTARn_PBR. */
mbed_official 324:406fd2029f23 816 #define BF_SPI_CTARn_PBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PBR) & BM_SPI_CTARn_PBR)
mbed_official 324:406fd2029f23 817
mbed_official 324:406fd2029f23 818 /*! @brief Set the PBR field to a new value. */
mbed_official 324:406fd2029f23 819 #define BW_SPI_CTARn_PBR(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PBR) | BF_SPI_CTARn_PBR(v)))
mbed_official 324:406fd2029f23 820 /*@}*/
mbed_official 324:406fd2029f23 821
mbed_official 324:406fd2029f23 822 /*!
mbed_official 324:406fd2029f23 823 * @name Register SPI_CTARn, field PDT[19:18] (RW)
mbed_official 324:406fd2029f23 824 *
mbed_official 324:406fd2029f23 825 * Selects the prescaler value for the delay between the negation of the PCS
mbed_official 324:406fd2029f23 826 * signal at the end of a frame and the assertion of PCS at the beginning of the
mbed_official 324:406fd2029f23 827 * next frame. The PDT field is only used in master mode. See the DT field
mbed_official 324:406fd2029f23 828 * description for details on how to compute the Delay after Transfer. Refer Delay after
mbed_official 324:406fd2029f23 829 * Transfer (tDT ) for more details.
mbed_official 324:406fd2029f23 830 *
mbed_official 324:406fd2029f23 831 * Values:
mbed_official 324:406fd2029f23 832 * - 00 - Delay after Transfer Prescaler value is 1.
mbed_official 324:406fd2029f23 833 * - 01 - Delay after Transfer Prescaler value is 3.
mbed_official 324:406fd2029f23 834 * - 10 - Delay after Transfer Prescaler value is 5.
mbed_official 324:406fd2029f23 835 * - 11 - Delay after Transfer Prescaler value is 7.
mbed_official 324:406fd2029f23 836 */
mbed_official 324:406fd2029f23 837 /*@{*/
mbed_official 324:406fd2029f23 838 #define BP_SPI_CTARn_PDT (18U) /*!< Bit position for SPI_CTARn_PDT. */
mbed_official 324:406fd2029f23 839 #define BM_SPI_CTARn_PDT (0x000C0000U) /*!< Bit mask for SPI_CTARn_PDT. */
mbed_official 324:406fd2029f23 840 #define BS_SPI_CTARn_PDT (2U) /*!< Bit field size in bits for SPI_CTARn_PDT. */
mbed_official 324:406fd2029f23 841
mbed_official 324:406fd2029f23 842 /*! @brief Read current value of the SPI_CTARn_PDT field. */
mbed_official 324:406fd2029f23 843 #define BR_SPI_CTARn_PDT(x, n) (HW_SPI_CTARn(x, n).B.PDT)
mbed_official 324:406fd2029f23 844
mbed_official 324:406fd2029f23 845 /*! @brief Format value for bitfield SPI_CTARn_PDT. */
mbed_official 324:406fd2029f23 846 #define BF_SPI_CTARn_PDT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PDT) & BM_SPI_CTARn_PDT)
mbed_official 324:406fd2029f23 847
mbed_official 324:406fd2029f23 848 /*! @brief Set the PDT field to a new value. */
mbed_official 324:406fd2029f23 849 #define BW_SPI_CTARn_PDT(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PDT) | BF_SPI_CTARn_PDT(v)))
mbed_official 324:406fd2029f23 850 /*@}*/
mbed_official 324:406fd2029f23 851
mbed_official 324:406fd2029f23 852 /*!
mbed_official 324:406fd2029f23 853 * @name Register SPI_CTARn, field PASC[21:20] (RW)
mbed_official 324:406fd2029f23 854 *
mbed_official 324:406fd2029f23 855 * Selects the prescaler value for the delay between the last edge of SCK and
mbed_official 324:406fd2029f23 856 * the negation of PCS. See the ASC field description for information on how to
mbed_official 324:406fd2029f23 857 * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
mbed_official 324:406fd2029f23 858 *
mbed_official 324:406fd2029f23 859 * Values:
mbed_official 324:406fd2029f23 860 * - 00 - Delay after Transfer Prescaler value is 1.
mbed_official 324:406fd2029f23 861 * - 01 - Delay after Transfer Prescaler value is 3.
mbed_official 324:406fd2029f23 862 * - 10 - Delay after Transfer Prescaler value is 5.
mbed_official 324:406fd2029f23 863 * - 11 - Delay after Transfer Prescaler value is 7.
mbed_official 324:406fd2029f23 864 */
mbed_official 324:406fd2029f23 865 /*@{*/
mbed_official 324:406fd2029f23 866 #define BP_SPI_CTARn_PASC (20U) /*!< Bit position for SPI_CTARn_PASC. */
mbed_official 324:406fd2029f23 867 #define BM_SPI_CTARn_PASC (0x00300000U) /*!< Bit mask for SPI_CTARn_PASC. */
mbed_official 324:406fd2029f23 868 #define BS_SPI_CTARn_PASC (2U) /*!< Bit field size in bits for SPI_CTARn_PASC. */
mbed_official 324:406fd2029f23 869
mbed_official 324:406fd2029f23 870 /*! @brief Read current value of the SPI_CTARn_PASC field. */
mbed_official 324:406fd2029f23 871 #define BR_SPI_CTARn_PASC(x, n) (HW_SPI_CTARn(x, n).B.PASC)
mbed_official 324:406fd2029f23 872
mbed_official 324:406fd2029f23 873 /*! @brief Format value for bitfield SPI_CTARn_PASC. */
mbed_official 324:406fd2029f23 874 #define BF_SPI_CTARn_PASC(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PASC) & BM_SPI_CTARn_PASC)
mbed_official 324:406fd2029f23 875
mbed_official 324:406fd2029f23 876 /*! @brief Set the PASC field to a new value. */
mbed_official 324:406fd2029f23 877 #define BW_SPI_CTARn_PASC(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PASC) | BF_SPI_CTARn_PASC(v)))
mbed_official 324:406fd2029f23 878 /*@}*/
mbed_official 324:406fd2029f23 879
mbed_official 324:406fd2029f23 880 /*!
mbed_official 324:406fd2029f23 881 * @name Register SPI_CTARn, field PCSSCK[23:22] (RW)
mbed_official 324:406fd2029f23 882 *
mbed_official 324:406fd2029f23 883 * Selects the prescaler value for the delay between assertion of PCS and the
mbed_official 324:406fd2029f23 884 * first edge of the SCK. See the CSSCK field description for information on how to
mbed_official 324:406fd2029f23 885 * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
mbed_official 324:406fd2029f23 886 *
mbed_official 324:406fd2029f23 887 * Values:
mbed_official 324:406fd2029f23 888 * - 00 - PCS to SCK Prescaler value is 1.
mbed_official 324:406fd2029f23 889 * - 01 - PCS to SCK Prescaler value is 3.
mbed_official 324:406fd2029f23 890 * - 10 - PCS to SCK Prescaler value is 5.
mbed_official 324:406fd2029f23 891 * - 11 - PCS to SCK Prescaler value is 7.
mbed_official 324:406fd2029f23 892 */
mbed_official 324:406fd2029f23 893 /*@{*/
mbed_official 324:406fd2029f23 894 #define BP_SPI_CTARn_PCSSCK (22U) /*!< Bit position for SPI_CTARn_PCSSCK. */
mbed_official 324:406fd2029f23 895 #define BM_SPI_CTARn_PCSSCK (0x00C00000U) /*!< Bit mask for SPI_CTARn_PCSSCK. */
mbed_official 324:406fd2029f23 896 #define BS_SPI_CTARn_PCSSCK (2U) /*!< Bit field size in bits for SPI_CTARn_PCSSCK. */
mbed_official 324:406fd2029f23 897
mbed_official 324:406fd2029f23 898 /*! @brief Read current value of the SPI_CTARn_PCSSCK field. */
mbed_official 324:406fd2029f23 899 #define BR_SPI_CTARn_PCSSCK(x, n) (HW_SPI_CTARn(x, n).B.PCSSCK)
mbed_official 324:406fd2029f23 900
mbed_official 324:406fd2029f23 901 /*! @brief Format value for bitfield SPI_CTARn_PCSSCK. */
mbed_official 324:406fd2029f23 902 #define BF_SPI_CTARn_PCSSCK(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_PCSSCK) & BM_SPI_CTARn_PCSSCK)
mbed_official 324:406fd2029f23 903
mbed_official 324:406fd2029f23 904 /*! @brief Set the PCSSCK field to a new value. */
mbed_official 324:406fd2029f23 905 #define BW_SPI_CTARn_PCSSCK(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_PCSSCK) | BF_SPI_CTARn_PCSSCK(v)))
mbed_official 324:406fd2029f23 906 /*@}*/
mbed_official 324:406fd2029f23 907
mbed_official 324:406fd2029f23 908 /*!
mbed_official 324:406fd2029f23 909 * @name Register SPI_CTARn, field LSBFE[24] (RW)
mbed_official 324:406fd2029f23 910 *
mbed_official 324:406fd2029f23 911 * Specifies whether the LSB or MSB of the frame is transferred first.
mbed_official 324:406fd2029f23 912 *
mbed_official 324:406fd2029f23 913 * Values:
mbed_official 324:406fd2029f23 914 * - 0 - Data is transferred MSB first.
mbed_official 324:406fd2029f23 915 * - 1 - Data is transferred LSB first.
mbed_official 324:406fd2029f23 916 */
mbed_official 324:406fd2029f23 917 /*@{*/
mbed_official 324:406fd2029f23 918 #define BP_SPI_CTARn_LSBFE (24U) /*!< Bit position for SPI_CTARn_LSBFE. */
mbed_official 324:406fd2029f23 919 #define BM_SPI_CTARn_LSBFE (0x01000000U) /*!< Bit mask for SPI_CTARn_LSBFE. */
mbed_official 324:406fd2029f23 920 #define BS_SPI_CTARn_LSBFE (1U) /*!< Bit field size in bits for SPI_CTARn_LSBFE. */
mbed_official 324:406fd2029f23 921
mbed_official 324:406fd2029f23 922 /*! @brief Read current value of the SPI_CTARn_LSBFE field. */
mbed_official 324:406fd2029f23 923 #define BR_SPI_CTARn_LSBFE(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE))
mbed_official 324:406fd2029f23 924
mbed_official 324:406fd2029f23 925 /*! @brief Format value for bitfield SPI_CTARn_LSBFE. */
mbed_official 324:406fd2029f23 926 #define BF_SPI_CTARn_LSBFE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_LSBFE) & BM_SPI_CTARn_LSBFE)
mbed_official 324:406fd2029f23 927
mbed_official 324:406fd2029f23 928 /*! @brief Set the LSBFE field to a new value. */
mbed_official 324:406fd2029f23 929 #define BW_SPI_CTARn_LSBFE(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_LSBFE) = (v))
mbed_official 324:406fd2029f23 930 /*@}*/
mbed_official 324:406fd2029f23 931
mbed_official 324:406fd2029f23 932 /*!
mbed_official 324:406fd2029f23 933 * @name Register SPI_CTARn, field CPHA[25] (RW)
mbed_official 324:406fd2029f23 934 *
mbed_official 324:406fd2029f23 935 * Selects which edge of SCK causes data to change and which edge causes data to
mbed_official 324:406fd2029f23 936 * be captured. This bit is used in both master and slave mode. For successful
mbed_official 324:406fd2029f23 937 * communication between serial devices, the devices must have identical clock
mbed_official 324:406fd2029f23 938 * phase settings. In Continuous SCK mode, the bit value is ignored and the
mbed_official 324:406fd2029f23 939 * transfers are done as if the CPHA bit is set to 1.
mbed_official 324:406fd2029f23 940 *
mbed_official 324:406fd2029f23 941 * Values:
mbed_official 324:406fd2029f23 942 * - 0 - Data is captured on the leading edge of SCK and changed on the
mbed_official 324:406fd2029f23 943 * following edge.
mbed_official 324:406fd2029f23 944 * - 1 - Data is changed on the leading edge of SCK and captured on the
mbed_official 324:406fd2029f23 945 * following edge.
mbed_official 324:406fd2029f23 946 */
mbed_official 324:406fd2029f23 947 /*@{*/
mbed_official 324:406fd2029f23 948 #define BP_SPI_CTARn_CPHA (25U) /*!< Bit position for SPI_CTARn_CPHA. */
mbed_official 324:406fd2029f23 949 #define BM_SPI_CTARn_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_CPHA. */
mbed_official 324:406fd2029f23 950 #define BS_SPI_CTARn_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_CPHA. */
mbed_official 324:406fd2029f23 951
mbed_official 324:406fd2029f23 952 /*! @brief Read current value of the SPI_CTARn_CPHA field. */
mbed_official 324:406fd2029f23 953 #define BR_SPI_CTARn_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA))
mbed_official 324:406fd2029f23 954
mbed_official 324:406fd2029f23 955 /*! @brief Format value for bitfield SPI_CTARn_CPHA. */
mbed_official 324:406fd2029f23 956 #define BF_SPI_CTARn_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPHA) & BM_SPI_CTARn_CPHA)
mbed_official 324:406fd2029f23 957
mbed_official 324:406fd2029f23 958 /*! @brief Set the CPHA field to a new value. */
mbed_official 324:406fd2029f23 959 #define BW_SPI_CTARn_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPHA) = (v))
mbed_official 324:406fd2029f23 960 /*@}*/
mbed_official 324:406fd2029f23 961
mbed_official 324:406fd2029f23 962 /*!
mbed_official 324:406fd2029f23 963 * @name Register SPI_CTARn, field CPOL[26] (RW)
mbed_official 324:406fd2029f23 964 *
mbed_official 324:406fd2029f23 965 * Selects the inactive state of the Serial Communications Clock (SCK). This bit
mbed_official 324:406fd2029f23 966 * is used in both master and slave mode. For successful communication between
mbed_official 324:406fd2029f23 967 * serial devices, the devices must have identical clock polarities. When the
mbed_official 324:406fd2029f23 968 * Continuous Selection Format is selected, switching between clock polarities
mbed_official 324:406fd2029f23 969 * without stopping the module can cause errors in the transfer due to the peripheral
mbed_official 324:406fd2029f23 970 * device interpreting the switch of clock polarity as a valid clock edge. In case
mbed_official 324:406fd2029f23 971 * of continous sck mode, when the module goes in low power mode(disabled),
mbed_official 324:406fd2029f23 972 * inactive state of sck is not guaranted.
mbed_official 324:406fd2029f23 973 *
mbed_official 324:406fd2029f23 974 * Values:
mbed_official 324:406fd2029f23 975 * - 0 - The inactive state value of SCK is low.
mbed_official 324:406fd2029f23 976 * - 1 - The inactive state value of SCK is high.
mbed_official 324:406fd2029f23 977 */
mbed_official 324:406fd2029f23 978 /*@{*/
mbed_official 324:406fd2029f23 979 #define BP_SPI_CTARn_CPOL (26U) /*!< Bit position for SPI_CTARn_CPOL. */
mbed_official 324:406fd2029f23 980 #define BM_SPI_CTARn_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_CPOL. */
mbed_official 324:406fd2029f23 981 #define BS_SPI_CTARn_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_CPOL. */
mbed_official 324:406fd2029f23 982
mbed_official 324:406fd2029f23 983 /*! @brief Read current value of the SPI_CTARn_CPOL field. */
mbed_official 324:406fd2029f23 984 #define BR_SPI_CTARn_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL))
mbed_official 324:406fd2029f23 985
mbed_official 324:406fd2029f23 986 /*! @brief Format value for bitfield SPI_CTARn_CPOL. */
mbed_official 324:406fd2029f23 987 #define BF_SPI_CTARn_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_CPOL) & BM_SPI_CTARn_CPOL)
mbed_official 324:406fd2029f23 988
mbed_official 324:406fd2029f23 989 /*! @brief Set the CPOL field to a new value. */
mbed_official 324:406fd2029f23 990 #define BW_SPI_CTARn_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_CPOL) = (v))
mbed_official 324:406fd2029f23 991 /*@}*/
mbed_official 324:406fd2029f23 992
mbed_official 324:406fd2029f23 993 /*!
mbed_official 324:406fd2029f23 994 * @name Register SPI_CTARn, field FMSZ[30:27] (RW)
mbed_official 324:406fd2029f23 995 *
mbed_official 324:406fd2029f23 996 * The number of bits transferred per frame is equal to the FMSZ value plus 1.
mbed_official 324:406fd2029f23 997 * Regardless of the transmission mode, the minimum valid frame size value is 4.
mbed_official 324:406fd2029f23 998 */
mbed_official 324:406fd2029f23 999 /*@{*/
mbed_official 324:406fd2029f23 1000 #define BP_SPI_CTARn_FMSZ (27U) /*!< Bit position for SPI_CTARn_FMSZ. */
mbed_official 324:406fd2029f23 1001 #define BM_SPI_CTARn_FMSZ (0x78000000U) /*!< Bit mask for SPI_CTARn_FMSZ. */
mbed_official 324:406fd2029f23 1002 #define BS_SPI_CTARn_FMSZ (4U) /*!< Bit field size in bits for SPI_CTARn_FMSZ. */
mbed_official 324:406fd2029f23 1003
mbed_official 324:406fd2029f23 1004 /*! @brief Read current value of the SPI_CTARn_FMSZ field. */
mbed_official 324:406fd2029f23 1005 #define BR_SPI_CTARn_FMSZ(x, n) (HW_SPI_CTARn(x, n).B.FMSZ)
mbed_official 324:406fd2029f23 1006
mbed_official 324:406fd2029f23 1007 /*! @brief Format value for bitfield SPI_CTARn_FMSZ. */
mbed_official 324:406fd2029f23 1008 #define BF_SPI_CTARn_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_FMSZ) & BM_SPI_CTARn_FMSZ)
mbed_official 324:406fd2029f23 1009
mbed_official 324:406fd2029f23 1010 /*! @brief Set the FMSZ field to a new value. */
mbed_official 324:406fd2029f23 1011 #define BW_SPI_CTARn_FMSZ(x, n, v) (HW_SPI_CTARn_WR(x, n, (HW_SPI_CTARn_RD(x, n) & ~BM_SPI_CTARn_FMSZ) | BF_SPI_CTARn_FMSZ(v)))
mbed_official 324:406fd2029f23 1012 /*@}*/
mbed_official 324:406fd2029f23 1013
mbed_official 324:406fd2029f23 1014 /*!
mbed_official 324:406fd2029f23 1015 * @name Register SPI_CTARn, field DBR[31] (RW)
mbed_official 324:406fd2029f23 1016 *
mbed_official 324:406fd2029f23 1017 * Doubles the effective baud rate of the Serial Communications Clock (SCK).
mbed_official 324:406fd2029f23 1018 * This field is used only in master mode. It effectively halves the Baud Rate
mbed_official 324:406fd2029f23 1019 * division ratio, supporting faster frequencies, and odd division ratios for the
mbed_official 324:406fd2029f23 1020 * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
mbed_official 324:406fd2029f23 1021 * Serial Communications Clock (SCK) depends on the value in the Baud Rate
mbed_official 324:406fd2029f23 1022 * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
mbed_official 324:406fd2029f23 1023 * description for details on how to compute the baud rate. SPI SCK Duty Cycle
mbed_official 324:406fd2029f23 1024 * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
mbed_official 324:406fd2029f23 1025 * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
mbed_official 324:406fd2029f23 1026 *
mbed_official 324:406fd2029f23 1027 * Values:
mbed_official 324:406fd2029f23 1028 * - 0 - The baud rate is computed normally with a 50/50 duty cycle.
mbed_official 324:406fd2029f23 1029 * - 1 - The baud rate is doubled with the duty cycle depending on the Baud Rate
mbed_official 324:406fd2029f23 1030 * Prescaler.
mbed_official 324:406fd2029f23 1031 */
mbed_official 324:406fd2029f23 1032 /*@{*/
mbed_official 324:406fd2029f23 1033 #define BP_SPI_CTARn_DBR (31U) /*!< Bit position for SPI_CTARn_DBR. */
mbed_official 324:406fd2029f23 1034 #define BM_SPI_CTARn_DBR (0x80000000U) /*!< Bit mask for SPI_CTARn_DBR. */
mbed_official 324:406fd2029f23 1035 #define BS_SPI_CTARn_DBR (1U) /*!< Bit field size in bits for SPI_CTARn_DBR. */
mbed_official 324:406fd2029f23 1036
mbed_official 324:406fd2029f23 1037 /*! @brief Read current value of the SPI_CTARn_DBR field. */
mbed_official 324:406fd2029f23 1038 #define BR_SPI_CTARn_DBR(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR))
mbed_official 324:406fd2029f23 1039
mbed_official 324:406fd2029f23 1040 /*! @brief Format value for bitfield SPI_CTARn_DBR. */
mbed_official 324:406fd2029f23 1041 #define BF_SPI_CTARn_DBR(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_DBR) & BM_SPI_CTARn_DBR)
mbed_official 324:406fd2029f23 1042
mbed_official 324:406fd2029f23 1043 /*! @brief Set the DBR field to a new value. */
mbed_official 324:406fd2029f23 1044 #define BW_SPI_CTARn_DBR(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_ADDR(x, n), BP_SPI_CTARn_DBR) = (v))
mbed_official 324:406fd2029f23 1045 /*@}*/
mbed_official 324:406fd2029f23 1046 /*******************************************************************************
mbed_official 324:406fd2029f23 1047 * HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
mbed_official 324:406fd2029f23 1048 ******************************************************************************/
mbed_official 324:406fd2029f23 1049
mbed_official 324:406fd2029f23 1050 /*!
mbed_official 324:406fd2029f23 1051 * @brief HW_SPI_CTARn_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
mbed_official 324:406fd2029f23 1052 *
mbed_official 324:406fd2029f23 1053 * Reset value: 0x78000000U
mbed_official 324:406fd2029f23 1054 *
mbed_official 324:406fd2029f23 1055 * When the module is configured as an SPI bus slave, the CTAR0 register is used.
mbed_official 324:406fd2029f23 1056 */
mbed_official 324:406fd2029f23 1057 typedef union _hw_spi_ctarn_slave
mbed_official 324:406fd2029f23 1058 {
mbed_official 324:406fd2029f23 1059 uint32_t U;
mbed_official 324:406fd2029f23 1060 struct _hw_spi_ctarn_slave_bitfields
mbed_official 324:406fd2029f23 1061 {
mbed_official 324:406fd2029f23 1062 uint32_t RESERVED0 : 25; /*!< [24:0] */
mbed_official 324:406fd2029f23 1063 uint32_t CPHA : 1; /*!< [25] Clock Phase */
mbed_official 324:406fd2029f23 1064 uint32_t CPOL : 1; /*!< [26] Clock Polarity */
mbed_official 324:406fd2029f23 1065 uint32_t FMSZ : 5; /*!< [31:27] Frame Size */
mbed_official 324:406fd2029f23 1066 } B;
mbed_official 324:406fd2029f23 1067 } hw_spi_ctarn_slave_t;
mbed_official 324:406fd2029f23 1068
mbed_official 324:406fd2029f23 1069 /*!
mbed_official 324:406fd2029f23 1070 * @name Constants and macros for entire SPI_CTARn_SLAVE register
mbed_official 324:406fd2029f23 1071 */
mbed_official 324:406fd2029f23 1072 /*@{*/
mbed_official 324:406fd2029f23 1073 #define HW_SPI_CTARn_SLAVE_COUNT (1U)
mbed_official 324:406fd2029f23 1074
mbed_official 324:406fd2029f23 1075 #define HW_SPI_CTARn_SLAVE_ADDR(x, n) ((x) + 0xCU + (0x4U * (n)))
mbed_official 324:406fd2029f23 1076
mbed_official 324:406fd2029f23 1077 #define HW_SPI_CTARn_SLAVE(x, n) (*(__IO hw_spi_ctarn_slave_t *) HW_SPI_CTARn_SLAVE_ADDR(x, n))
mbed_official 324:406fd2029f23 1078 #define HW_SPI_CTARn_SLAVE_RD(x, n) (HW_SPI_CTARn_SLAVE(x, n).U)
mbed_official 324:406fd2029f23 1079 #define HW_SPI_CTARn_SLAVE_WR(x, n, v) (HW_SPI_CTARn_SLAVE(x, n).U = (v))
mbed_official 324:406fd2029f23 1080 #define HW_SPI_CTARn_SLAVE_SET(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 1081 #define HW_SPI_CTARn_SLAVE_CLR(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 1082 #define HW_SPI_CTARn_SLAVE_TOG(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, HW_SPI_CTARn_SLAVE_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 1083 /*@}*/
mbed_official 324:406fd2029f23 1084
mbed_official 324:406fd2029f23 1085 /*
mbed_official 324:406fd2029f23 1086 * Constants & macros for individual SPI_CTARn_SLAVE bitfields
mbed_official 324:406fd2029f23 1087 */
mbed_official 324:406fd2029f23 1088
mbed_official 324:406fd2029f23 1089 /*!
mbed_official 324:406fd2029f23 1090 * @name Register SPI_CTARn_SLAVE, field CPHA[25] (RW)
mbed_official 324:406fd2029f23 1091 *
mbed_official 324:406fd2029f23 1092 * Selects which edge of SCK causes data to change and which edge causes data to
mbed_official 324:406fd2029f23 1093 * be captured. This bit is used in both master and slave mode. For successful
mbed_official 324:406fd2029f23 1094 * communication between serial devices, the devices must have identical clock
mbed_official 324:406fd2029f23 1095 * phase settings. In Continuous SCK mode, the bit value is ignored and the
mbed_official 324:406fd2029f23 1096 * transfers are done as if the CPHA bit is set to 1.
mbed_official 324:406fd2029f23 1097 *
mbed_official 324:406fd2029f23 1098 * Values:
mbed_official 324:406fd2029f23 1099 * - 0 - Data is captured on the leading edge of SCK and changed on the
mbed_official 324:406fd2029f23 1100 * following edge.
mbed_official 324:406fd2029f23 1101 * - 1 - Data is changed on the leading edge of SCK and captured on the
mbed_official 324:406fd2029f23 1102 * following edge.
mbed_official 324:406fd2029f23 1103 */
mbed_official 324:406fd2029f23 1104 /*@{*/
mbed_official 324:406fd2029f23 1105 #define BP_SPI_CTARn_SLAVE_CPHA (25U) /*!< Bit position for SPI_CTARn_SLAVE_CPHA. */
mbed_official 324:406fd2029f23 1106 #define BM_SPI_CTARn_SLAVE_CPHA (0x02000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPHA. */
mbed_official 324:406fd2029f23 1107 #define BS_SPI_CTARn_SLAVE_CPHA (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPHA. */
mbed_official 324:406fd2029f23 1108
mbed_official 324:406fd2029f23 1109 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPHA field. */
mbed_official 324:406fd2029f23 1110 #define BR_SPI_CTARn_SLAVE_CPHA(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA))
mbed_official 324:406fd2029f23 1111
mbed_official 324:406fd2029f23 1112 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPHA. */
mbed_official 324:406fd2029f23 1113 #define BF_SPI_CTARn_SLAVE_CPHA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPHA) & BM_SPI_CTARn_SLAVE_CPHA)
mbed_official 324:406fd2029f23 1114
mbed_official 324:406fd2029f23 1115 /*! @brief Set the CPHA field to a new value. */
mbed_official 324:406fd2029f23 1116 #define BW_SPI_CTARn_SLAVE_CPHA(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPHA) = (v))
mbed_official 324:406fd2029f23 1117 /*@}*/
mbed_official 324:406fd2029f23 1118
mbed_official 324:406fd2029f23 1119 /*!
mbed_official 324:406fd2029f23 1120 * @name Register SPI_CTARn_SLAVE, field CPOL[26] (RW)
mbed_official 324:406fd2029f23 1121 *
mbed_official 324:406fd2029f23 1122 * Selects the inactive state of the Serial Communications Clock (SCK). In case
mbed_official 324:406fd2029f23 1123 * of continous sck mode, when the module goes in low power mode(disabled),
mbed_official 324:406fd2029f23 1124 * inactive state of sck is not guaranted.
mbed_official 324:406fd2029f23 1125 *
mbed_official 324:406fd2029f23 1126 * Values:
mbed_official 324:406fd2029f23 1127 * - 0 - The inactive state value of SCK is low.
mbed_official 324:406fd2029f23 1128 * - 1 - The inactive state value of SCK is high.
mbed_official 324:406fd2029f23 1129 */
mbed_official 324:406fd2029f23 1130 /*@{*/
mbed_official 324:406fd2029f23 1131 #define BP_SPI_CTARn_SLAVE_CPOL (26U) /*!< Bit position for SPI_CTARn_SLAVE_CPOL. */
mbed_official 324:406fd2029f23 1132 #define BM_SPI_CTARn_SLAVE_CPOL (0x04000000U) /*!< Bit mask for SPI_CTARn_SLAVE_CPOL. */
mbed_official 324:406fd2029f23 1133 #define BS_SPI_CTARn_SLAVE_CPOL (1U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_CPOL. */
mbed_official 324:406fd2029f23 1134
mbed_official 324:406fd2029f23 1135 /*! @brief Read current value of the SPI_CTARn_SLAVE_CPOL field. */
mbed_official 324:406fd2029f23 1136 #define BR_SPI_CTARn_SLAVE_CPOL(x, n) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL))
mbed_official 324:406fd2029f23 1137
mbed_official 324:406fd2029f23 1138 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_CPOL. */
mbed_official 324:406fd2029f23 1139 #define BF_SPI_CTARn_SLAVE_CPOL(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_CPOL) & BM_SPI_CTARn_SLAVE_CPOL)
mbed_official 324:406fd2029f23 1140
mbed_official 324:406fd2029f23 1141 /*! @brief Set the CPOL field to a new value. */
mbed_official 324:406fd2029f23 1142 #define BW_SPI_CTARn_SLAVE_CPOL(x, n, v) (BITBAND_ACCESS32(HW_SPI_CTARn_SLAVE_ADDR(x, n), BP_SPI_CTARn_SLAVE_CPOL) = (v))
mbed_official 324:406fd2029f23 1143 /*@}*/
mbed_official 324:406fd2029f23 1144
mbed_official 324:406fd2029f23 1145 /*!
mbed_official 324:406fd2029f23 1146 * @name Register SPI_CTARn_SLAVE, field FMSZ[31:27] (RW)
mbed_official 324:406fd2029f23 1147 *
mbed_official 324:406fd2029f23 1148 * The number of bits transfered per frame is equal to the FMSZ field value plus
mbed_official 324:406fd2029f23 1149 * 1. Note that the minimum valid value of frame size is 4.
mbed_official 324:406fd2029f23 1150 */
mbed_official 324:406fd2029f23 1151 /*@{*/
mbed_official 324:406fd2029f23 1152 #define BP_SPI_CTARn_SLAVE_FMSZ (27U) /*!< Bit position for SPI_CTARn_SLAVE_FMSZ. */
mbed_official 324:406fd2029f23 1153 #define BM_SPI_CTARn_SLAVE_FMSZ (0xF8000000U) /*!< Bit mask for SPI_CTARn_SLAVE_FMSZ. */
mbed_official 324:406fd2029f23 1154 #define BS_SPI_CTARn_SLAVE_FMSZ (5U) /*!< Bit field size in bits for SPI_CTARn_SLAVE_FMSZ. */
mbed_official 324:406fd2029f23 1155
mbed_official 324:406fd2029f23 1156 /*! @brief Read current value of the SPI_CTARn_SLAVE_FMSZ field. */
mbed_official 324:406fd2029f23 1157 #define BR_SPI_CTARn_SLAVE_FMSZ(x, n) (HW_SPI_CTARn_SLAVE(x, n).B.FMSZ)
mbed_official 324:406fd2029f23 1158
mbed_official 324:406fd2029f23 1159 /*! @brief Format value for bitfield SPI_CTARn_SLAVE_FMSZ. */
mbed_official 324:406fd2029f23 1160 #define BF_SPI_CTARn_SLAVE_FMSZ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_CTARn_SLAVE_FMSZ) & BM_SPI_CTARn_SLAVE_FMSZ)
mbed_official 324:406fd2029f23 1161
mbed_official 324:406fd2029f23 1162 /*! @brief Set the FMSZ field to a new value. */
mbed_official 324:406fd2029f23 1163 #define BW_SPI_CTARn_SLAVE_FMSZ(x, n, v) (HW_SPI_CTARn_SLAVE_WR(x, n, (HW_SPI_CTARn_SLAVE_RD(x, n) & ~BM_SPI_CTARn_SLAVE_FMSZ) | BF_SPI_CTARn_SLAVE_FMSZ(v)))
mbed_official 324:406fd2029f23 1164 /*@}*/
mbed_official 324:406fd2029f23 1165
mbed_official 324:406fd2029f23 1166 /*******************************************************************************
mbed_official 324:406fd2029f23 1167 * HW_SPI_SR - Status Register
mbed_official 324:406fd2029f23 1168 ******************************************************************************/
mbed_official 324:406fd2029f23 1169
mbed_official 324:406fd2029f23 1170 /*!
mbed_official 324:406fd2029f23 1171 * @brief HW_SPI_SR - Status Register (RW)
mbed_official 324:406fd2029f23 1172 *
mbed_official 324:406fd2029f23 1173 * Reset value: 0x02000000U
mbed_official 324:406fd2029f23 1174 *
mbed_official 324:406fd2029f23 1175 * SR contains status and flag bits. The bits reflect the status of the module
mbed_official 324:406fd2029f23 1176 * and indicate the occurrence of events that can generate interrupt or DMA
mbed_official 324:406fd2029f23 1177 * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
mbed_official 324:406fd2029f23 1178 * to a flag bit has no effect. This register may not be writable in Module
mbed_official 324:406fd2029f23 1179 * Disable mode due to the use of power saving mechanisms.
mbed_official 324:406fd2029f23 1180 */
mbed_official 324:406fd2029f23 1181 typedef union _hw_spi_sr
mbed_official 324:406fd2029f23 1182 {
mbed_official 324:406fd2029f23 1183 uint32_t U;
mbed_official 324:406fd2029f23 1184 struct _hw_spi_sr_bitfields
mbed_official 324:406fd2029f23 1185 {
mbed_official 324:406fd2029f23 1186 uint32_t POPNXTPTR : 4; /*!< [3:0] Pop Next Pointer */
mbed_official 324:406fd2029f23 1187 uint32_t RXCTR : 4; /*!< [7:4] RX FIFO Counter */
mbed_official 324:406fd2029f23 1188 uint32_t TXNXTPTR : 4; /*!< [11:8] Transmit Next Pointer */
mbed_official 324:406fd2029f23 1189 uint32_t TXCTR : 4; /*!< [15:12] TX FIFO Counter */
mbed_official 324:406fd2029f23 1190 uint32_t RESERVED0 : 1; /*!< [16] */
mbed_official 324:406fd2029f23 1191 uint32_t RFDF : 1; /*!< [17] Receive FIFO Drain Flag */
mbed_official 324:406fd2029f23 1192 uint32_t RESERVED1 : 1; /*!< [18] */
mbed_official 324:406fd2029f23 1193 uint32_t RFOF : 1; /*!< [19] Receive FIFO Overflow Flag */
mbed_official 324:406fd2029f23 1194 uint32_t RESERVED2 : 5; /*!< [24:20] */
mbed_official 324:406fd2029f23 1195 uint32_t TFFF : 1; /*!< [25] Transmit FIFO Fill Flag */
mbed_official 324:406fd2029f23 1196 uint32_t RESERVED3 : 1; /*!< [26] */
mbed_official 324:406fd2029f23 1197 uint32_t TFUF : 1; /*!< [27] Transmit FIFO Underflow Flag */
mbed_official 324:406fd2029f23 1198 uint32_t EOQF : 1; /*!< [28] End of Queue Flag */
mbed_official 324:406fd2029f23 1199 uint32_t RESERVED4 : 1; /*!< [29] */
mbed_official 324:406fd2029f23 1200 uint32_t TXRXS : 1; /*!< [30] TX and RX Status */
mbed_official 324:406fd2029f23 1201 uint32_t TCF : 1; /*!< [31] Transfer Complete Flag */
mbed_official 324:406fd2029f23 1202 } B;
mbed_official 324:406fd2029f23 1203 } hw_spi_sr_t;
mbed_official 324:406fd2029f23 1204
mbed_official 324:406fd2029f23 1205 /*!
mbed_official 324:406fd2029f23 1206 * @name Constants and macros for entire SPI_SR register
mbed_official 324:406fd2029f23 1207 */
mbed_official 324:406fd2029f23 1208 /*@{*/
mbed_official 324:406fd2029f23 1209 #define HW_SPI_SR_ADDR(x) ((x) + 0x2CU)
mbed_official 324:406fd2029f23 1210
mbed_official 324:406fd2029f23 1211 #define HW_SPI_SR(x) (*(__IO hw_spi_sr_t *) HW_SPI_SR_ADDR(x))
mbed_official 324:406fd2029f23 1212 #define HW_SPI_SR_RD(x) (HW_SPI_SR(x).U)
mbed_official 324:406fd2029f23 1213 #define HW_SPI_SR_WR(x, v) (HW_SPI_SR(x).U = (v))
mbed_official 324:406fd2029f23 1214 #define HW_SPI_SR_SET(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) | (v)))
mbed_official 324:406fd2029f23 1215 #define HW_SPI_SR_CLR(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1216 #define HW_SPI_SR_TOG(x, v) (HW_SPI_SR_WR(x, HW_SPI_SR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1217 /*@}*/
mbed_official 324:406fd2029f23 1218
mbed_official 324:406fd2029f23 1219 /*
mbed_official 324:406fd2029f23 1220 * Constants & macros for individual SPI_SR bitfields
mbed_official 324:406fd2029f23 1221 */
mbed_official 324:406fd2029f23 1222
mbed_official 324:406fd2029f23 1223 /*!
mbed_official 324:406fd2029f23 1224 * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
mbed_official 324:406fd2029f23 1225 *
mbed_official 324:406fd2029f23 1226 * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
mbed_official 324:406fd2029f23 1227 * The POPNXTPTR is updated when the POPR is read.
mbed_official 324:406fd2029f23 1228 */
mbed_official 324:406fd2029f23 1229 /*@{*/
mbed_official 324:406fd2029f23 1230 #define BP_SPI_SR_POPNXTPTR (0U) /*!< Bit position for SPI_SR_POPNXTPTR. */
mbed_official 324:406fd2029f23 1231 #define BM_SPI_SR_POPNXTPTR (0x0000000FU) /*!< Bit mask for SPI_SR_POPNXTPTR. */
mbed_official 324:406fd2029f23 1232 #define BS_SPI_SR_POPNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_POPNXTPTR. */
mbed_official 324:406fd2029f23 1233
mbed_official 324:406fd2029f23 1234 /*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
mbed_official 324:406fd2029f23 1235 #define BR_SPI_SR_POPNXTPTR(x) (HW_SPI_SR(x).B.POPNXTPTR)
mbed_official 324:406fd2029f23 1236 /*@}*/
mbed_official 324:406fd2029f23 1237
mbed_official 324:406fd2029f23 1238 /*!
mbed_official 324:406fd2029f23 1239 * @name Register SPI_SR, field RXCTR[7:4] (RO)
mbed_official 324:406fd2029f23 1240 *
mbed_official 324:406fd2029f23 1241 * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
mbed_official 324:406fd2029f23 1242 * every time the POPR is read. The RXCTR is incremented every time data is
mbed_official 324:406fd2029f23 1243 * transferred from the shift register to the RX FIFO.
mbed_official 324:406fd2029f23 1244 */
mbed_official 324:406fd2029f23 1245 /*@{*/
mbed_official 324:406fd2029f23 1246 #define BP_SPI_SR_RXCTR (4U) /*!< Bit position for SPI_SR_RXCTR. */
mbed_official 324:406fd2029f23 1247 #define BM_SPI_SR_RXCTR (0x000000F0U) /*!< Bit mask for SPI_SR_RXCTR. */
mbed_official 324:406fd2029f23 1248 #define BS_SPI_SR_RXCTR (4U) /*!< Bit field size in bits for SPI_SR_RXCTR. */
mbed_official 324:406fd2029f23 1249
mbed_official 324:406fd2029f23 1250 /*! @brief Read current value of the SPI_SR_RXCTR field. */
mbed_official 324:406fd2029f23 1251 #define BR_SPI_SR_RXCTR(x) (HW_SPI_SR(x).B.RXCTR)
mbed_official 324:406fd2029f23 1252 /*@}*/
mbed_official 324:406fd2029f23 1253
mbed_official 324:406fd2029f23 1254 /*!
mbed_official 324:406fd2029f23 1255 * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
mbed_official 324:406fd2029f23 1256 *
mbed_official 324:406fd2029f23 1257 * Indicates which TX FIFO entry is transmitted during the next transfer. The
mbed_official 324:406fd2029f23 1258 * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
mbed_official 324:406fd2029f23 1259 * the shift register.
mbed_official 324:406fd2029f23 1260 */
mbed_official 324:406fd2029f23 1261 /*@{*/
mbed_official 324:406fd2029f23 1262 #define BP_SPI_SR_TXNXTPTR (8U) /*!< Bit position for SPI_SR_TXNXTPTR. */
mbed_official 324:406fd2029f23 1263 #define BM_SPI_SR_TXNXTPTR (0x00000F00U) /*!< Bit mask for SPI_SR_TXNXTPTR. */
mbed_official 324:406fd2029f23 1264 #define BS_SPI_SR_TXNXTPTR (4U) /*!< Bit field size in bits for SPI_SR_TXNXTPTR. */
mbed_official 324:406fd2029f23 1265
mbed_official 324:406fd2029f23 1266 /*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
mbed_official 324:406fd2029f23 1267 #define BR_SPI_SR_TXNXTPTR(x) (HW_SPI_SR(x).B.TXNXTPTR)
mbed_official 324:406fd2029f23 1268 /*@}*/
mbed_official 324:406fd2029f23 1269
mbed_official 324:406fd2029f23 1270 /*!
mbed_official 324:406fd2029f23 1271 * @name Register SPI_SR, field TXCTR[15:12] (RO)
mbed_official 324:406fd2029f23 1272 *
mbed_official 324:406fd2029f23 1273 * Indicates the number of valid entries in the TX FIFO. The TXCTR is
mbed_official 324:406fd2029f23 1274 * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
mbed_official 324:406fd2029f23 1275 * command is executed and the SPI data is transferred to the shift register.
mbed_official 324:406fd2029f23 1276 */
mbed_official 324:406fd2029f23 1277 /*@{*/
mbed_official 324:406fd2029f23 1278 #define BP_SPI_SR_TXCTR (12U) /*!< Bit position for SPI_SR_TXCTR. */
mbed_official 324:406fd2029f23 1279 #define BM_SPI_SR_TXCTR (0x0000F000U) /*!< Bit mask for SPI_SR_TXCTR. */
mbed_official 324:406fd2029f23 1280 #define BS_SPI_SR_TXCTR (4U) /*!< Bit field size in bits for SPI_SR_TXCTR. */
mbed_official 324:406fd2029f23 1281
mbed_official 324:406fd2029f23 1282 /*! @brief Read current value of the SPI_SR_TXCTR field. */
mbed_official 324:406fd2029f23 1283 #define BR_SPI_SR_TXCTR(x) (HW_SPI_SR(x).B.TXCTR)
mbed_official 324:406fd2029f23 1284 /*@}*/
mbed_official 324:406fd2029f23 1285
mbed_official 324:406fd2029f23 1286 /*!
mbed_official 324:406fd2029f23 1287 * @name Register SPI_SR, field RFDF[17] (W1C)
mbed_official 324:406fd2029f23 1288 *
mbed_official 324:406fd2029f23 1289 * Provides a method for the module to request that entries be removed from the
mbed_official 324:406fd2029f23 1290 * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
mbed_official 324:406fd2029f23 1291 * cleared by writing 1 to it or by acknowledgement from the DMA controller when
mbed_official 324:406fd2029f23 1292 * the RX FIFO is empty.
mbed_official 324:406fd2029f23 1293 *
mbed_official 324:406fd2029f23 1294 * Values:
mbed_official 324:406fd2029f23 1295 * - 0 - RX FIFO is empty.
mbed_official 324:406fd2029f23 1296 * - 1 - RX FIFO is not empty.
mbed_official 324:406fd2029f23 1297 */
mbed_official 324:406fd2029f23 1298 /*@{*/
mbed_official 324:406fd2029f23 1299 #define BP_SPI_SR_RFDF (17U) /*!< Bit position for SPI_SR_RFDF. */
mbed_official 324:406fd2029f23 1300 #define BM_SPI_SR_RFDF (0x00020000U) /*!< Bit mask for SPI_SR_RFDF. */
mbed_official 324:406fd2029f23 1301 #define BS_SPI_SR_RFDF (1U) /*!< Bit field size in bits for SPI_SR_RFDF. */
mbed_official 324:406fd2029f23 1302
mbed_official 324:406fd2029f23 1303 /*! @brief Read current value of the SPI_SR_RFDF field. */
mbed_official 324:406fd2029f23 1304 #define BR_SPI_SR_RFDF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF))
mbed_official 324:406fd2029f23 1305
mbed_official 324:406fd2029f23 1306 /*! @brief Format value for bitfield SPI_SR_RFDF. */
mbed_official 324:406fd2029f23 1307 #define BF_SPI_SR_RFDF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFDF) & BM_SPI_SR_RFDF)
mbed_official 324:406fd2029f23 1308
mbed_official 324:406fd2029f23 1309 /*! @brief Set the RFDF field to a new value. */
mbed_official 324:406fd2029f23 1310 #define BW_SPI_SR_RFDF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFDF) = (v))
mbed_official 324:406fd2029f23 1311 /*@}*/
mbed_official 324:406fd2029f23 1312
mbed_official 324:406fd2029f23 1313 /*!
mbed_official 324:406fd2029f23 1314 * @name Register SPI_SR, field RFOF[19] (W1C)
mbed_official 324:406fd2029f23 1315 *
mbed_official 324:406fd2029f23 1316 * Indicates an overflow condition in the RX FIFO. The field is set when the RX
mbed_official 324:406fd2029f23 1317 * FIFO and shift register are full and a transfer is initiated. The bit remains
mbed_official 324:406fd2029f23 1318 * set until it is cleared by writing a 1 to it.
mbed_official 324:406fd2029f23 1319 *
mbed_official 324:406fd2029f23 1320 * Values:
mbed_official 324:406fd2029f23 1321 * - 0 - No Rx FIFO overflow.
mbed_official 324:406fd2029f23 1322 * - 1 - Rx FIFO overflow has occurred.
mbed_official 324:406fd2029f23 1323 */
mbed_official 324:406fd2029f23 1324 /*@{*/
mbed_official 324:406fd2029f23 1325 #define BP_SPI_SR_RFOF (19U) /*!< Bit position for SPI_SR_RFOF. */
mbed_official 324:406fd2029f23 1326 #define BM_SPI_SR_RFOF (0x00080000U) /*!< Bit mask for SPI_SR_RFOF. */
mbed_official 324:406fd2029f23 1327 #define BS_SPI_SR_RFOF (1U) /*!< Bit field size in bits for SPI_SR_RFOF. */
mbed_official 324:406fd2029f23 1328
mbed_official 324:406fd2029f23 1329 /*! @brief Read current value of the SPI_SR_RFOF field. */
mbed_official 324:406fd2029f23 1330 #define BR_SPI_SR_RFOF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF))
mbed_official 324:406fd2029f23 1331
mbed_official 324:406fd2029f23 1332 /*! @brief Format value for bitfield SPI_SR_RFOF. */
mbed_official 324:406fd2029f23 1333 #define BF_SPI_SR_RFOF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_RFOF) & BM_SPI_SR_RFOF)
mbed_official 324:406fd2029f23 1334
mbed_official 324:406fd2029f23 1335 /*! @brief Set the RFOF field to a new value. */
mbed_official 324:406fd2029f23 1336 #define BW_SPI_SR_RFOF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_RFOF) = (v))
mbed_official 324:406fd2029f23 1337 /*@}*/
mbed_official 324:406fd2029f23 1338
mbed_official 324:406fd2029f23 1339 /*!
mbed_official 324:406fd2029f23 1340 * @name Register SPI_SR, field TFFF[25] (W1C)
mbed_official 324:406fd2029f23 1341 *
mbed_official 324:406fd2029f23 1342 * Provides a method for the module to request more entries to be added to the
mbed_official 324:406fd2029f23 1343 * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
mbed_official 324:406fd2029f23 1344 * cleared by writing 1 to it or by acknowledgement from the DMA controller to
mbed_official 324:406fd2029f23 1345 * the TX FIFO full request.
mbed_official 324:406fd2029f23 1346 *
mbed_official 324:406fd2029f23 1347 * Values:
mbed_official 324:406fd2029f23 1348 * - 0 - TX FIFO is full.
mbed_official 324:406fd2029f23 1349 * - 1 - TX FIFO is not full.
mbed_official 324:406fd2029f23 1350 */
mbed_official 324:406fd2029f23 1351 /*@{*/
mbed_official 324:406fd2029f23 1352 #define BP_SPI_SR_TFFF (25U) /*!< Bit position for SPI_SR_TFFF. */
mbed_official 324:406fd2029f23 1353 #define BM_SPI_SR_TFFF (0x02000000U) /*!< Bit mask for SPI_SR_TFFF. */
mbed_official 324:406fd2029f23 1354 #define BS_SPI_SR_TFFF (1U) /*!< Bit field size in bits for SPI_SR_TFFF. */
mbed_official 324:406fd2029f23 1355
mbed_official 324:406fd2029f23 1356 /*! @brief Read current value of the SPI_SR_TFFF field. */
mbed_official 324:406fd2029f23 1357 #define BR_SPI_SR_TFFF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF))
mbed_official 324:406fd2029f23 1358
mbed_official 324:406fd2029f23 1359 /*! @brief Format value for bitfield SPI_SR_TFFF. */
mbed_official 324:406fd2029f23 1360 #define BF_SPI_SR_TFFF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFFF) & BM_SPI_SR_TFFF)
mbed_official 324:406fd2029f23 1361
mbed_official 324:406fd2029f23 1362 /*! @brief Set the TFFF field to a new value. */
mbed_official 324:406fd2029f23 1363 #define BW_SPI_SR_TFFF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFFF) = (v))
mbed_official 324:406fd2029f23 1364 /*@}*/
mbed_official 324:406fd2029f23 1365
mbed_official 324:406fd2029f23 1366 /*!
mbed_official 324:406fd2029f23 1367 * @name Register SPI_SR, field TFUF[27] (W1C)
mbed_official 324:406fd2029f23 1368 *
mbed_official 324:406fd2029f23 1369 * Indicates an underflow condition in the TX FIFO. The transmit underflow
mbed_official 324:406fd2029f23 1370 * condition is detected only for SPI blocks operating in Slave mode and SPI
mbed_official 324:406fd2029f23 1371 * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
mbed_official 324:406fd2029f23 1372 * is empty and an external SPI master initiates a transfer. The TFUF bit remains
mbed_official 324:406fd2029f23 1373 * set until cleared by writing 1 to it.
mbed_official 324:406fd2029f23 1374 *
mbed_official 324:406fd2029f23 1375 * Values:
mbed_official 324:406fd2029f23 1376 * - 0 - No TX FIFO underflow.
mbed_official 324:406fd2029f23 1377 * - 1 - TX FIFO underflow has occurred.
mbed_official 324:406fd2029f23 1378 */
mbed_official 324:406fd2029f23 1379 /*@{*/
mbed_official 324:406fd2029f23 1380 #define BP_SPI_SR_TFUF (27U) /*!< Bit position for SPI_SR_TFUF. */
mbed_official 324:406fd2029f23 1381 #define BM_SPI_SR_TFUF (0x08000000U) /*!< Bit mask for SPI_SR_TFUF. */
mbed_official 324:406fd2029f23 1382 #define BS_SPI_SR_TFUF (1U) /*!< Bit field size in bits for SPI_SR_TFUF. */
mbed_official 324:406fd2029f23 1383
mbed_official 324:406fd2029f23 1384 /*! @brief Read current value of the SPI_SR_TFUF field. */
mbed_official 324:406fd2029f23 1385 #define BR_SPI_SR_TFUF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF))
mbed_official 324:406fd2029f23 1386
mbed_official 324:406fd2029f23 1387 /*! @brief Format value for bitfield SPI_SR_TFUF. */
mbed_official 324:406fd2029f23 1388 #define BF_SPI_SR_TFUF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TFUF) & BM_SPI_SR_TFUF)
mbed_official 324:406fd2029f23 1389
mbed_official 324:406fd2029f23 1390 /*! @brief Set the TFUF field to a new value. */
mbed_official 324:406fd2029f23 1391 #define BW_SPI_SR_TFUF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TFUF) = (v))
mbed_official 324:406fd2029f23 1392 /*@}*/
mbed_official 324:406fd2029f23 1393
mbed_official 324:406fd2029f23 1394 /*!
mbed_official 324:406fd2029f23 1395 * @name Register SPI_SR, field EOQF[28] (W1C)
mbed_official 324:406fd2029f23 1396 *
mbed_official 324:406fd2029f23 1397 * Indicates that the last entry in a queue has been transmitted when the module
mbed_official 324:406fd2029f23 1398 * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
mbed_official 324:406fd2029f23 1399 * set in the command halfword and the end of the transfer is reached. The EOQF
mbed_official 324:406fd2029f23 1400 * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
mbed_official 324:406fd2029f23 1401 * the TXRXS bit is automatically cleared.
mbed_official 324:406fd2029f23 1402 *
mbed_official 324:406fd2029f23 1403 * Values:
mbed_official 324:406fd2029f23 1404 * - 0 - EOQ is not set in the executing command.
mbed_official 324:406fd2029f23 1405 * - 1 - EOQ is set in the executing SPI command.
mbed_official 324:406fd2029f23 1406 */
mbed_official 324:406fd2029f23 1407 /*@{*/
mbed_official 324:406fd2029f23 1408 #define BP_SPI_SR_EOQF (28U) /*!< Bit position for SPI_SR_EOQF. */
mbed_official 324:406fd2029f23 1409 #define BM_SPI_SR_EOQF (0x10000000U) /*!< Bit mask for SPI_SR_EOQF. */
mbed_official 324:406fd2029f23 1410 #define BS_SPI_SR_EOQF (1U) /*!< Bit field size in bits for SPI_SR_EOQF. */
mbed_official 324:406fd2029f23 1411
mbed_official 324:406fd2029f23 1412 /*! @brief Read current value of the SPI_SR_EOQF field. */
mbed_official 324:406fd2029f23 1413 #define BR_SPI_SR_EOQF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF))
mbed_official 324:406fd2029f23 1414
mbed_official 324:406fd2029f23 1415 /*! @brief Format value for bitfield SPI_SR_EOQF. */
mbed_official 324:406fd2029f23 1416 #define BF_SPI_SR_EOQF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_EOQF) & BM_SPI_SR_EOQF)
mbed_official 324:406fd2029f23 1417
mbed_official 324:406fd2029f23 1418 /*! @brief Set the EOQF field to a new value. */
mbed_official 324:406fd2029f23 1419 #define BW_SPI_SR_EOQF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_EOQF) = (v))
mbed_official 324:406fd2029f23 1420 /*@}*/
mbed_official 324:406fd2029f23 1421
mbed_official 324:406fd2029f23 1422 /*!
mbed_official 324:406fd2029f23 1423 * @name Register SPI_SR, field TXRXS[30] (W1C)
mbed_official 324:406fd2029f23 1424 *
mbed_official 324:406fd2029f23 1425 * Reflects the run status of the module.
mbed_official 324:406fd2029f23 1426 *
mbed_official 324:406fd2029f23 1427 * Values:
mbed_official 324:406fd2029f23 1428 * - 0 - Transmit and receive operations are disabled (The module is in Stopped
mbed_official 324:406fd2029f23 1429 * state).
mbed_official 324:406fd2029f23 1430 * - 1 - Transmit and receive operations are enabled (The module is in Running
mbed_official 324:406fd2029f23 1431 * state).
mbed_official 324:406fd2029f23 1432 */
mbed_official 324:406fd2029f23 1433 /*@{*/
mbed_official 324:406fd2029f23 1434 #define BP_SPI_SR_TXRXS (30U) /*!< Bit position for SPI_SR_TXRXS. */
mbed_official 324:406fd2029f23 1435 #define BM_SPI_SR_TXRXS (0x40000000U) /*!< Bit mask for SPI_SR_TXRXS. */
mbed_official 324:406fd2029f23 1436 #define BS_SPI_SR_TXRXS (1U) /*!< Bit field size in bits for SPI_SR_TXRXS. */
mbed_official 324:406fd2029f23 1437
mbed_official 324:406fd2029f23 1438 /*! @brief Read current value of the SPI_SR_TXRXS field. */
mbed_official 324:406fd2029f23 1439 #define BR_SPI_SR_TXRXS(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS))
mbed_official 324:406fd2029f23 1440
mbed_official 324:406fd2029f23 1441 /*! @brief Format value for bitfield SPI_SR_TXRXS. */
mbed_official 324:406fd2029f23 1442 #define BF_SPI_SR_TXRXS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TXRXS) & BM_SPI_SR_TXRXS)
mbed_official 324:406fd2029f23 1443
mbed_official 324:406fd2029f23 1444 /*! @brief Set the TXRXS field to a new value. */
mbed_official 324:406fd2029f23 1445 #define BW_SPI_SR_TXRXS(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TXRXS) = (v))
mbed_official 324:406fd2029f23 1446 /*@}*/
mbed_official 324:406fd2029f23 1447
mbed_official 324:406fd2029f23 1448 /*!
mbed_official 324:406fd2029f23 1449 * @name Register SPI_SR, field TCF[31] (W1C)
mbed_official 324:406fd2029f23 1450 *
mbed_official 324:406fd2029f23 1451 * Indicates that all bits in a frame have been shifted out. TCF remains set
mbed_official 324:406fd2029f23 1452 * until it is cleared by writing a 1 to it.
mbed_official 324:406fd2029f23 1453 *
mbed_official 324:406fd2029f23 1454 * Values:
mbed_official 324:406fd2029f23 1455 * - 0 - Transfer not complete.
mbed_official 324:406fd2029f23 1456 * - 1 - Transfer complete.
mbed_official 324:406fd2029f23 1457 */
mbed_official 324:406fd2029f23 1458 /*@{*/
mbed_official 324:406fd2029f23 1459 #define BP_SPI_SR_TCF (31U) /*!< Bit position for SPI_SR_TCF. */
mbed_official 324:406fd2029f23 1460 #define BM_SPI_SR_TCF (0x80000000U) /*!< Bit mask for SPI_SR_TCF. */
mbed_official 324:406fd2029f23 1461 #define BS_SPI_SR_TCF (1U) /*!< Bit field size in bits for SPI_SR_TCF. */
mbed_official 324:406fd2029f23 1462
mbed_official 324:406fd2029f23 1463 /*! @brief Read current value of the SPI_SR_TCF field. */
mbed_official 324:406fd2029f23 1464 #define BR_SPI_SR_TCF(x) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF))
mbed_official 324:406fd2029f23 1465
mbed_official 324:406fd2029f23 1466 /*! @brief Format value for bitfield SPI_SR_TCF. */
mbed_official 324:406fd2029f23 1467 #define BF_SPI_SR_TCF(v) ((uint32_t)((uint32_t)(v) << BP_SPI_SR_TCF) & BM_SPI_SR_TCF)
mbed_official 324:406fd2029f23 1468
mbed_official 324:406fd2029f23 1469 /*! @brief Set the TCF field to a new value. */
mbed_official 324:406fd2029f23 1470 #define BW_SPI_SR_TCF(x, v) (BITBAND_ACCESS32(HW_SPI_SR_ADDR(x), BP_SPI_SR_TCF) = (v))
mbed_official 324:406fd2029f23 1471 /*@}*/
mbed_official 324:406fd2029f23 1472
mbed_official 324:406fd2029f23 1473 /*******************************************************************************
mbed_official 324:406fd2029f23 1474 * HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register
mbed_official 324:406fd2029f23 1475 ******************************************************************************/
mbed_official 324:406fd2029f23 1476
mbed_official 324:406fd2029f23 1477 /*!
mbed_official 324:406fd2029f23 1478 * @brief HW_SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
mbed_official 324:406fd2029f23 1479 *
mbed_official 324:406fd2029f23 1480 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1481 *
mbed_official 324:406fd2029f23 1482 * RSER controls DMA and interrupt requests. Do not write to the RSER while the
mbed_official 324:406fd2029f23 1483 * module is in the Running state.
mbed_official 324:406fd2029f23 1484 */
mbed_official 324:406fd2029f23 1485 typedef union _hw_spi_rser
mbed_official 324:406fd2029f23 1486 {
mbed_official 324:406fd2029f23 1487 uint32_t U;
mbed_official 324:406fd2029f23 1488 struct _hw_spi_rser_bitfields
mbed_official 324:406fd2029f23 1489 {
mbed_official 324:406fd2029f23 1490 uint32_t RESERVED0 : 16; /*!< [15:0] */
mbed_official 324:406fd2029f23 1491 uint32_t RFDF_DIRS : 1; /*!< [16] Receive FIFO Drain DMA or Interrupt
mbed_official 324:406fd2029f23 1492 * Request Select */
mbed_official 324:406fd2029f23 1493 uint32_t RFDF_RE : 1; /*!< [17] Receive FIFO Drain Request Enable */
mbed_official 324:406fd2029f23 1494 uint32_t RESERVED1 : 1; /*!< [18] */
mbed_official 324:406fd2029f23 1495 uint32_t RFOF_RE : 1; /*!< [19] Receive FIFO Overflow Request Enable
mbed_official 324:406fd2029f23 1496 * */
mbed_official 324:406fd2029f23 1497 uint32_t RESERVED2 : 4; /*!< [23:20] */
mbed_official 324:406fd2029f23 1498 uint32_t TFFF_DIRS : 1; /*!< [24] Transmit FIFO Fill DMA or Interrupt
mbed_official 324:406fd2029f23 1499 * Request Select */
mbed_official 324:406fd2029f23 1500 uint32_t TFFF_RE : 1; /*!< [25] Transmit FIFO Fill Request Enable */
mbed_official 324:406fd2029f23 1501 uint32_t RESERVED3 : 1; /*!< [26] */
mbed_official 324:406fd2029f23 1502 uint32_t TFUF_RE : 1; /*!< [27] Transmit FIFO Underflow Request
mbed_official 324:406fd2029f23 1503 * Enable */
mbed_official 324:406fd2029f23 1504 uint32_t EOQF_RE : 1; /*!< [28] Finished Request Enable */
mbed_official 324:406fd2029f23 1505 uint32_t RESERVED4 : 2; /*!< [30:29] */
mbed_official 324:406fd2029f23 1506 uint32_t TCF_RE : 1; /*!< [31] Transmission Complete Request Enable */
mbed_official 324:406fd2029f23 1507 } B;
mbed_official 324:406fd2029f23 1508 } hw_spi_rser_t;
mbed_official 324:406fd2029f23 1509
mbed_official 324:406fd2029f23 1510 /*!
mbed_official 324:406fd2029f23 1511 * @name Constants and macros for entire SPI_RSER register
mbed_official 324:406fd2029f23 1512 */
mbed_official 324:406fd2029f23 1513 /*@{*/
mbed_official 324:406fd2029f23 1514 #define HW_SPI_RSER_ADDR(x) ((x) + 0x30U)
mbed_official 324:406fd2029f23 1515
mbed_official 324:406fd2029f23 1516 #define HW_SPI_RSER(x) (*(__IO hw_spi_rser_t *) HW_SPI_RSER_ADDR(x))
mbed_official 324:406fd2029f23 1517 #define HW_SPI_RSER_RD(x) (HW_SPI_RSER(x).U)
mbed_official 324:406fd2029f23 1518 #define HW_SPI_RSER_WR(x, v) (HW_SPI_RSER(x).U = (v))
mbed_official 324:406fd2029f23 1519 #define HW_SPI_RSER_SET(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) | (v)))
mbed_official 324:406fd2029f23 1520 #define HW_SPI_RSER_CLR(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1521 #define HW_SPI_RSER_TOG(x, v) (HW_SPI_RSER_WR(x, HW_SPI_RSER_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1522 /*@}*/
mbed_official 324:406fd2029f23 1523
mbed_official 324:406fd2029f23 1524 /*
mbed_official 324:406fd2029f23 1525 * Constants & macros for individual SPI_RSER bitfields
mbed_official 324:406fd2029f23 1526 */
mbed_official 324:406fd2029f23 1527
mbed_official 324:406fd2029f23 1528 /*!
mbed_official 324:406fd2029f23 1529 * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
mbed_official 324:406fd2029f23 1530 *
mbed_official 324:406fd2029f23 1531 * Selects between generating a DMA request or an interrupt request. When the
mbed_official 324:406fd2029f23 1532 * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
mbed_official 324:406fd2029f23 1533 * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
mbed_official 324:406fd2029f23 1534 *
mbed_official 324:406fd2029f23 1535 * Values:
mbed_official 324:406fd2029f23 1536 * - 0 - Interrupt request.
mbed_official 324:406fd2029f23 1537 * - 1 - DMA request.
mbed_official 324:406fd2029f23 1538 */
mbed_official 324:406fd2029f23 1539 /*@{*/
mbed_official 324:406fd2029f23 1540 #define BP_SPI_RSER_RFDF_DIRS (16U) /*!< Bit position for SPI_RSER_RFDF_DIRS. */
mbed_official 324:406fd2029f23 1541 #define BM_SPI_RSER_RFDF_DIRS (0x00010000U) /*!< Bit mask for SPI_RSER_RFDF_DIRS. */
mbed_official 324:406fd2029f23 1542 #define BS_SPI_RSER_RFDF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_DIRS. */
mbed_official 324:406fd2029f23 1543
mbed_official 324:406fd2029f23 1544 /*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
mbed_official 324:406fd2029f23 1545 #define BR_SPI_RSER_RFDF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS))
mbed_official 324:406fd2029f23 1546
mbed_official 324:406fd2029f23 1547 /*! @brief Format value for bitfield SPI_RSER_RFDF_DIRS. */
mbed_official 324:406fd2029f23 1548 #define BF_SPI_RSER_RFDF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_DIRS) & BM_SPI_RSER_RFDF_DIRS)
mbed_official 324:406fd2029f23 1549
mbed_official 324:406fd2029f23 1550 /*! @brief Set the RFDF_DIRS field to a new value. */
mbed_official 324:406fd2029f23 1551 #define BW_SPI_RSER_RFDF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_DIRS) = (v))
mbed_official 324:406fd2029f23 1552 /*@}*/
mbed_official 324:406fd2029f23 1553
mbed_official 324:406fd2029f23 1554 /*!
mbed_official 324:406fd2029f23 1555 * @name Register SPI_RSER, field RFDF_RE[17] (RW)
mbed_official 324:406fd2029f23 1556 *
mbed_official 324:406fd2029f23 1557 * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
mbed_official 324:406fd2029f23 1558 * selects between generating an interrupt request or a DMA request.
mbed_official 324:406fd2029f23 1559 *
mbed_official 324:406fd2029f23 1560 * Values:
mbed_official 324:406fd2029f23 1561 * - 0 - RFDF interrupt or DMA requests are disabled.
mbed_official 324:406fd2029f23 1562 * - 1 - RFDF interrupt or DMA requests are enabled.
mbed_official 324:406fd2029f23 1563 */
mbed_official 324:406fd2029f23 1564 /*@{*/
mbed_official 324:406fd2029f23 1565 #define BP_SPI_RSER_RFDF_RE (17U) /*!< Bit position for SPI_RSER_RFDF_RE. */
mbed_official 324:406fd2029f23 1566 #define BM_SPI_RSER_RFDF_RE (0x00020000U) /*!< Bit mask for SPI_RSER_RFDF_RE. */
mbed_official 324:406fd2029f23 1567 #define BS_SPI_RSER_RFDF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFDF_RE. */
mbed_official 324:406fd2029f23 1568
mbed_official 324:406fd2029f23 1569 /*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
mbed_official 324:406fd2029f23 1570 #define BR_SPI_RSER_RFDF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE))
mbed_official 324:406fd2029f23 1571
mbed_official 324:406fd2029f23 1572 /*! @brief Format value for bitfield SPI_RSER_RFDF_RE. */
mbed_official 324:406fd2029f23 1573 #define BF_SPI_RSER_RFDF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFDF_RE) & BM_SPI_RSER_RFDF_RE)
mbed_official 324:406fd2029f23 1574
mbed_official 324:406fd2029f23 1575 /*! @brief Set the RFDF_RE field to a new value. */
mbed_official 324:406fd2029f23 1576 #define BW_SPI_RSER_RFDF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFDF_RE) = (v))
mbed_official 324:406fd2029f23 1577 /*@}*/
mbed_official 324:406fd2029f23 1578
mbed_official 324:406fd2029f23 1579 /*!
mbed_official 324:406fd2029f23 1580 * @name Register SPI_RSER, field RFOF_RE[19] (RW)
mbed_official 324:406fd2029f23 1581 *
mbed_official 324:406fd2029f23 1582 * Enables the RFOF flag in the SR to generate an interrupt request.
mbed_official 324:406fd2029f23 1583 *
mbed_official 324:406fd2029f23 1584 * Values:
mbed_official 324:406fd2029f23 1585 * - 0 - RFOF interrupt requests are disabled.
mbed_official 324:406fd2029f23 1586 * - 1 - RFOF interrupt requests are enabled.
mbed_official 324:406fd2029f23 1587 */
mbed_official 324:406fd2029f23 1588 /*@{*/
mbed_official 324:406fd2029f23 1589 #define BP_SPI_RSER_RFOF_RE (19U) /*!< Bit position for SPI_RSER_RFOF_RE. */
mbed_official 324:406fd2029f23 1590 #define BM_SPI_RSER_RFOF_RE (0x00080000U) /*!< Bit mask for SPI_RSER_RFOF_RE. */
mbed_official 324:406fd2029f23 1591 #define BS_SPI_RSER_RFOF_RE (1U) /*!< Bit field size in bits for SPI_RSER_RFOF_RE. */
mbed_official 324:406fd2029f23 1592
mbed_official 324:406fd2029f23 1593 /*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
mbed_official 324:406fd2029f23 1594 #define BR_SPI_RSER_RFOF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE))
mbed_official 324:406fd2029f23 1595
mbed_official 324:406fd2029f23 1596 /*! @brief Format value for bitfield SPI_RSER_RFOF_RE. */
mbed_official 324:406fd2029f23 1597 #define BF_SPI_RSER_RFOF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_RFOF_RE) & BM_SPI_RSER_RFOF_RE)
mbed_official 324:406fd2029f23 1598
mbed_official 324:406fd2029f23 1599 /*! @brief Set the RFOF_RE field to a new value. */
mbed_official 324:406fd2029f23 1600 #define BW_SPI_RSER_RFOF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_RFOF_RE) = (v))
mbed_official 324:406fd2029f23 1601 /*@}*/
mbed_official 324:406fd2029f23 1602
mbed_official 324:406fd2029f23 1603 /*!
mbed_official 324:406fd2029f23 1604 * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
mbed_official 324:406fd2029f23 1605 *
mbed_official 324:406fd2029f23 1606 * Selects between generating a DMA request or an interrupt request. When
mbed_official 324:406fd2029f23 1607 * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
mbed_official 324:406fd2029f23 1608 * interrupt request or a DMA request.
mbed_official 324:406fd2029f23 1609 *
mbed_official 324:406fd2029f23 1610 * Values:
mbed_official 324:406fd2029f23 1611 * - 0 - TFFF flag generates interrupt requests.
mbed_official 324:406fd2029f23 1612 * - 1 - TFFF flag generates DMA requests.
mbed_official 324:406fd2029f23 1613 */
mbed_official 324:406fd2029f23 1614 /*@{*/
mbed_official 324:406fd2029f23 1615 #define BP_SPI_RSER_TFFF_DIRS (24U) /*!< Bit position for SPI_RSER_TFFF_DIRS. */
mbed_official 324:406fd2029f23 1616 #define BM_SPI_RSER_TFFF_DIRS (0x01000000U) /*!< Bit mask for SPI_RSER_TFFF_DIRS. */
mbed_official 324:406fd2029f23 1617 #define BS_SPI_RSER_TFFF_DIRS (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_DIRS. */
mbed_official 324:406fd2029f23 1618
mbed_official 324:406fd2029f23 1619 /*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
mbed_official 324:406fd2029f23 1620 #define BR_SPI_RSER_TFFF_DIRS(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS))
mbed_official 324:406fd2029f23 1621
mbed_official 324:406fd2029f23 1622 /*! @brief Format value for bitfield SPI_RSER_TFFF_DIRS. */
mbed_official 324:406fd2029f23 1623 #define BF_SPI_RSER_TFFF_DIRS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_DIRS) & BM_SPI_RSER_TFFF_DIRS)
mbed_official 324:406fd2029f23 1624
mbed_official 324:406fd2029f23 1625 /*! @brief Set the TFFF_DIRS field to a new value. */
mbed_official 324:406fd2029f23 1626 #define BW_SPI_RSER_TFFF_DIRS(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_DIRS) = (v))
mbed_official 324:406fd2029f23 1627 /*@}*/
mbed_official 324:406fd2029f23 1628
mbed_official 324:406fd2029f23 1629 /*!
mbed_official 324:406fd2029f23 1630 * @name Register SPI_RSER, field TFFF_RE[25] (RW)
mbed_official 324:406fd2029f23 1631 *
mbed_official 324:406fd2029f23 1632 * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
mbed_official 324:406fd2029f23 1633 * selects between generating an interrupt request or a DMA request.
mbed_official 324:406fd2029f23 1634 *
mbed_official 324:406fd2029f23 1635 * Values:
mbed_official 324:406fd2029f23 1636 * - 0 - TFFF interrupts or DMA requests are disabled.
mbed_official 324:406fd2029f23 1637 * - 1 - TFFF interrupts or DMA requests are enabled.
mbed_official 324:406fd2029f23 1638 */
mbed_official 324:406fd2029f23 1639 /*@{*/
mbed_official 324:406fd2029f23 1640 #define BP_SPI_RSER_TFFF_RE (25U) /*!< Bit position for SPI_RSER_TFFF_RE. */
mbed_official 324:406fd2029f23 1641 #define BM_SPI_RSER_TFFF_RE (0x02000000U) /*!< Bit mask for SPI_RSER_TFFF_RE. */
mbed_official 324:406fd2029f23 1642 #define BS_SPI_RSER_TFFF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFFF_RE. */
mbed_official 324:406fd2029f23 1643
mbed_official 324:406fd2029f23 1644 /*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
mbed_official 324:406fd2029f23 1645 #define BR_SPI_RSER_TFFF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE))
mbed_official 324:406fd2029f23 1646
mbed_official 324:406fd2029f23 1647 /*! @brief Format value for bitfield SPI_RSER_TFFF_RE. */
mbed_official 324:406fd2029f23 1648 #define BF_SPI_RSER_TFFF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFFF_RE) & BM_SPI_RSER_TFFF_RE)
mbed_official 324:406fd2029f23 1649
mbed_official 324:406fd2029f23 1650 /*! @brief Set the TFFF_RE field to a new value. */
mbed_official 324:406fd2029f23 1651 #define BW_SPI_RSER_TFFF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFFF_RE) = (v))
mbed_official 324:406fd2029f23 1652 /*@}*/
mbed_official 324:406fd2029f23 1653
mbed_official 324:406fd2029f23 1654 /*!
mbed_official 324:406fd2029f23 1655 * @name Register SPI_RSER, field TFUF_RE[27] (RW)
mbed_official 324:406fd2029f23 1656 *
mbed_official 324:406fd2029f23 1657 * Enables the TFUF flag in the SR to generate an interrupt request.
mbed_official 324:406fd2029f23 1658 *
mbed_official 324:406fd2029f23 1659 * Values:
mbed_official 324:406fd2029f23 1660 * - 0 - TFUF interrupt requests are disabled.
mbed_official 324:406fd2029f23 1661 * - 1 - TFUF interrupt requests are enabled.
mbed_official 324:406fd2029f23 1662 */
mbed_official 324:406fd2029f23 1663 /*@{*/
mbed_official 324:406fd2029f23 1664 #define BP_SPI_RSER_TFUF_RE (27U) /*!< Bit position for SPI_RSER_TFUF_RE. */
mbed_official 324:406fd2029f23 1665 #define BM_SPI_RSER_TFUF_RE (0x08000000U) /*!< Bit mask for SPI_RSER_TFUF_RE. */
mbed_official 324:406fd2029f23 1666 #define BS_SPI_RSER_TFUF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TFUF_RE. */
mbed_official 324:406fd2029f23 1667
mbed_official 324:406fd2029f23 1668 /*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
mbed_official 324:406fd2029f23 1669 #define BR_SPI_RSER_TFUF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE))
mbed_official 324:406fd2029f23 1670
mbed_official 324:406fd2029f23 1671 /*! @brief Format value for bitfield SPI_RSER_TFUF_RE. */
mbed_official 324:406fd2029f23 1672 #define BF_SPI_RSER_TFUF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TFUF_RE) & BM_SPI_RSER_TFUF_RE)
mbed_official 324:406fd2029f23 1673
mbed_official 324:406fd2029f23 1674 /*! @brief Set the TFUF_RE field to a new value. */
mbed_official 324:406fd2029f23 1675 #define BW_SPI_RSER_TFUF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TFUF_RE) = (v))
mbed_official 324:406fd2029f23 1676 /*@}*/
mbed_official 324:406fd2029f23 1677
mbed_official 324:406fd2029f23 1678 /*!
mbed_official 324:406fd2029f23 1679 * @name Register SPI_RSER, field EOQF_RE[28] (RW)
mbed_official 324:406fd2029f23 1680 *
mbed_official 324:406fd2029f23 1681 * Enables the EOQF flag in the SR to generate an interrupt request.
mbed_official 324:406fd2029f23 1682 *
mbed_official 324:406fd2029f23 1683 * Values:
mbed_official 324:406fd2029f23 1684 * - 0 - EOQF interrupt requests are disabled.
mbed_official 324:406fd2029f23 1685 * - 1 - EOQF interrupt requests are enabled.
mbed_official 324:406fd2029f23 1686 */
mbed_official 324:406fd2029f23 1687 /*@{*/
mbed_official 324:406fd2029f23 1688 #define BP_SPI_RSER_EOQF_RE (28U) /*!< Bit position for SPI_RSER_EOQF_RE. */
mbed_official 324:406fd2029f23 1689 #define BM_SPI_RSER_EOQF_RE (0x10000000U) /*!< Bit mask for SPI_RSER_EOQF_RE. */
mbed_official 324:406fd2029f23 1690 #define BS_SPI_RSER_EOQF_RE (1U) /*!< Bit field size in bits for SPI_RSER_EOQF_RE. */
mbed_official 324:406fd2029f23 1691
mbed_official 324:406fd2029f23 1692 /*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
mbed_official 324:406fd2029f23 1693 #define BR_SPI_RSER_EOQF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE))
mbed_official 324:406fd2029f23 1694
mbed_official 324:406fd2029f23 1695 /*! @brief Format value for bitfield SPI_RSER_EOQF_RE. */
mbed_official 324:406fd2029f23 1696 #define BF_SPI_RSER_EOQF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_EOQF_RE) & BM_SPI_RSER_EOQF_RE)
mbed_official 324:406fd2029f23 1697
mbed_official 324:406fd2029f23 1698 /*! @brief Set the EOQF_RE field to a new value. */
mbed_official 324:406fd2029f23 1699 #define BW_SPI_RSER_EOQF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_EOQF_RE) = (v))
mbed_official 324:406fd2029f23 1700 /*@}*/
mbed_official 324:406fd2029f23 1701
mbed_official 324:406fd2029f23 1702 /*!
mbed_official 324:406fd2029f23 1703 * @name Register SPI_RSER, field TCF_RE[31] (RW)
mbed_official 324:406fd2029f23 1704 *
mbed_official 324:406fd2029f23 1705 * Enables TCF flag in the SR to generate an interrupt request.
mbed_official 324:406fd2029f23 1706 *
mbed_official 324:406fd2029f23 1707 * Values:
mbed_official 324:406fd2029f23 1708 * - 0 - TCF interrupt requests are disabled.
mbed_official 324:406fd2029f23 1709 * - 1 - TCF interrupt requests are enabled.
mbed_official 324:406fd2029f23 1710 */
mbed_official 324:406fd2029f23 1711 /*@{*/
mbed_official 324:406fd2029f23 1712 #define BP_SPI_RSER_TCF_RE (31U) /*!< Bit position for SPI_RSER_TCF_RE. */
mbed_official 324:406fd2029f23 1713 #define BM_SPI_RSER_TCF_RE (0x80000000U) /*!< Bit mask for SPI_RSER_TCF_RE. */
mbed_official 324:406fd2029f23 1714 #define BS_SPI_RSER_TCF_RE (1U) /*!< Bit field size in bits for SPI_RSER_TCF_RE. */
mbed_official 324:406fd2029f23 1715
mbed_official 324:406fd2029f23 1716 /*! @brief Read current value of the SPI_RSER_TCF_RE field. */
mbed_official 324:406fd2029f23 1717 #define BR_SPI_RSER_TCF_RE(x) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE))
mbed_official 324:406fd2029f23 1718
mbed_official 324:406fd2029f23 1719 /*! @brief Format value for bitfield SPI_RSER_TCF_RE. */
mbed_official 324:406fd2029f23 1720 #define BF_SPI_RSER_TCF_RE(v) ((uint32_t)((uint32_t)(v) << BP_SPI_RSER_TCF_RE) & BM_SPI_RSER_TCF_RE)
mbed_official 324:406fd2029f23 1721
mbed_official 324:406fd2029f23 1722 /*! @brief Set the TCF_RE field to a new value. */
mbed_official 324:406fd2029f23 1723 #define BW_SPI_RSER_TCF_RE(x, v) (BITBAND_ACCESS32(HW_SPI_RSER_ADDR(x), BP_SPI_RSER_TCF_RE) = (v))
mbed_official 324:406fd2029f23 1724 /*@}*/
mbed_official 324:406fd2029f23 1725
mbed_official 324:406fd2029f23 1726 /*******************************************************************************
mbed_official 324:406fd2029f23 1727 * HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode
mbed_official 324:406fd2029f23 1728 ******************************************************************************/
mbed_official 324:406fd2029f23 1729
mbed_official 324:406fd2029f23 1730 /*!
mbed_official 324:406fd2029f23 1731 * @brief HW_SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
mbed_official 324:406fd2029f23 1732 *
mbed_official 324:406fd2029f23 1733 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1734 *
mbed_official 324:406fd2029f23 1735 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
mbed_official 324:406fd2029f23 1736 * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
mbed_official 324:406fd2029f23 1737 * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
mbed_official 324:406fd2029f23 1738 * can be used as data, supporting up to 32-bit frame operation. A read access
mbed_official 324:406fd2029f23 1739 * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
mbed_official 324:406fd2029f23 1740 * writing to this register does not update the FIFO. Therefore, any reads performed
mbed_official 324:406fd2029f23 1741 * while the module is disabled return the last PUSHR write performed while the
mbed_official 324:406fd2029f23 1742 * module was still enabled.
mbed_official 324:406fd2029f23 1743 */
mbed_official 324:406fd2029f23 1744 typedef union _hw_spi_pushr
mbed_official 324:406fd2029f23 1745 {
mbed_official 324:406fd2029f23 1746 uint32_t U;
mbed_official 324:406fd2029f23 1747 struct _hw_spi_pushr_bitfields
mbed_official 324:406fd2029f23 1748 {
mbed_official 324:406fd2029f23 1749 uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */
mbed_official 324:406fd2029f23 1750 uint32_t PCS : 6; /*!< [21:16] */
mbed_official 324:406fd2029f23 1751 uint32_t RESERVED0 : 4; /*!< [25:22] */
mbed_official 324:406fd2029f23 1752 uint32_t CTCNT : 1; /*!< [26] Clear Transfer Counter */
mbed_official 324:406fd2029f23 1753 uint32_t EOQ : 1; /*!< [27] End Of Queue */
mbed_official 324:406fd2029f23 1754 uint32_t CTAS : 3; /*!< [30:28] Clock and Transfer Attributes Select
mbed_official 324:406fd2029f23 1755 * */
mbed_official 324:406fd2029f23 1756 uint32_t CONT : 1; /*!< [31] Continuous Peripheral Chip Select Enable
mbed_official 324:406fd2029f23 1757 * */
mbed_official 324:406fd2029f23 1758 } B;
mbed_official 324:406fd2029f23 1759 } hw_spi_pushr_t;
mbed_official 324:406fd2029f23 1760
mbed_official 324:406fd2029f23 1761 /*!
mbed_official 324:406fd2029f23 1762 * @name Constants and macros for entire SPI_PUSHR register
mbed_official 324:406fd2029f23 1763 */
mbed_official 324:406fd2029f23 1764 /*@{*/
mbed_official 324:406fd2029f23 1765 #define HW_SPI_PUSHR_ADDR(x) ((x) + 0x34U)
mbed_official 324:406fd2029f23 1766
mbed_official 324:406fd2029f23 1767 #define HW_SPI_PUSHR(x) (*(__IO hw_spi_pushr_t *) HW_SPI_PUSHR_ADDR(x))
mbed_official 324:406fd2029f23 1768 #define HW_SPI_PUSHR_RD(x) (HW_SPI_PUSHR(x).U)
mbed_official 324:406fd2029f23 1769 #define HW_SPI_PUSHR_WR(x, v) (HW_SPI_PUSHR(x).U = (v))
mbed_official 324:406fd2029f23 1770 #define HW_SPI_PUSHR_SET(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) | (v)))
mbed_official 324:406fd2029f23 1771 #define HW_SPI_PUSHR_CLR(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1772 #define HW_SPI_PUSHR_TOG(x, v) (HW_SPI_PUSHR_WR(x, HW_SPI_PUSHR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1773 /*@}*/
mbed_official 324:406fd2029f23 1774
mbed_official 324:406fd2029f23 1775 /*
mbed_official 324:406fd2029f23 1776 * Constants & macros for individual SPI_PUSHR bitfields
mbed_official 324:406fd2029f23 1777 */
mbed_official 324:406fd2029f23 1778
mbed_official 324:406fd2029f23 1779 /*!
mbed_official 324:406fd2029f23 1780 * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
mbed_official 324:406fd2029f23 1781 *
mbed_official 324:406fd2029f23 1782 * Holds SPI data to be transferred according to the associated SPI command.
mbed_official 324:406fd2029f23 1783 */
mbed_official 324:406fd2029f23 1784 /*@{*/
mbed_official 324:406fd2029f23 1785 #define BP_SPI_PUSHR_TXDATA (0U) /*!< Bit position for SPI_PUSHR_TXDATA. */
mbed_official 324:406fd2029f23 1786 #define BM_SPI_PUSHR_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_PUSHR_TXDATA. */
mbed_official 324:406fd2029f23 1787 #define BS_SPI_PUSHR_TXDATA (16U) /*!< Bit field size in bits for SPI_PUSHR_TXDATA. */
mbed_official 324:406fd2029f23 1788
mbed_official 324:406fd2029f23 1789 /*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
mbed_official 324:406fd2029f23 1790 #define BR_SPI_PUSHR_TXDATA(x) (HW_SPI_PUSHR(x).B.TXDATA)
mbed_official 324:406fd2029f23 1791
mbed_official 324:406fd2029f23 1792 /*! @brief Format value for bitfield SPI_PUSHR_TXDATA. */
mbed_official 324:406fd2029f23 1793 #define BF_SPI_PUSHR_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_TXDATA) & BM_SPI_PUSHR_TXDATA)
mbed_official 324:406fd2029f23 1794
mbed_official 324:406fd2029f23 1795 /*! @brief Set the TXDATA field to a new value. */
mbed_official 324:406fd2029f23 1796 #define BW_SPI_PUSHR_TXDATA(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_TXDATA) | BF_SPI_PUSHR_TXDATA(v)))
mbed_official 324:406fd2029f23 1797 /*@}*/
mbed_official 324:406fd2029f23 1798
mbed_official 324:406fd2029f23 1799 /*!
mbed_official 324:406fd2029f23 1800 * @name Register SPI_PUSHR, field PCS[21:16] (RW)
mbed_official 324:406fd2029f23 1801 *
mbed_official 324:406fd2029f23 1802 * Select which PCS signals are to be asserted for the transfer. Refer to the
mbed_official 324:406fd2029f23 1803 * chip configuration details for the number of PCS signals used in this MCU.
mbed_official 324:406fd2029f23 1804 *
mbed_official 324:406fd2029f23 1805 * Values:
mbed_official 324:406fd2029f23 1806 * - 0 - Negate the PCS[x] signal.
mbed_official 324:406fd2029f23 1807 * - 1 - Assert the PCS[x] signal.
mbed_official 324:406fd2029f23 1808 */
mbed_official 324:406fd2029f23 1809 /*@{*/
mbed_official 324:406fd2029f23 1810 #define BP_SPI_PUSHR_PCS (16U) /*!< Bit position for SPI_PUSHR_PCS. */
mbed_official 324:406fd2029f23 1811 #define BM_SPI_PUSHR_PCS (0x003F0000U) /*!< Bit mask for SPI_PUSHR_PCS. */
mbed_official 324:406fd2029f23 1812 #define BS_SPI_PUSHR_PCS (6U) /*!< Bit field size in bits for SPI_PUSHR_PCS. */
mbed_official 324:406fd2029f23 1813
mbed_official 324:406fd2029f23 1814 /*! @brief Read current value of the SPI_PUSHR_PCS field. */
mbed_official 324:406fd2029f23 1815 #define BR_SPI_PUSHR_PCS(x) (HW_SPI_PUSHR(x).B.PCS)
mbed_official 324:406fd2029f23 1816
mbed_official 324:406fd2029f23 1817 /*! @brief Format value for bitfield SPI_PUSHR_PCS. */
mbed_official 324:406fd2029f23 1818 #define BF_SPI_PUSHR_PCS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_PCS) & BM_SPI_PUSHR_PCS)
mbed_official 324:406fd2029f23 1819
mbed_official 324:406fd2029f23 1820 /*! @brief Set the PCS field to a new value. */
mbed_official 324:406fd2029f23 1821 #define BW_SPI_PUSHR_PCS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_PCS) | BF_SPI_PUSHR_PCS(v)))
mbed_official 324:406fd2029f23 1822 /*@}*/
mbed_official 324:406fd2029f23 1823
mbed_official 324:406fd2029f23 1824 /*!
mbed_official 324:406fd2029f23 1825 * @name Register SPI_PUSHR, field CTCNT[26] (RW)
mbed_official 324:406fd2029f23 1826 *
mbed_official 324:406fd2029f23 1827 * Clears the TCNT field in the TCR register. The TCNT field is cleared before
mbed_official 324:406fd2029f23 1828 * the module starts transmitting the current SPI frame.
mbed_official 324:406fd2029f23 1829 *
mbed_official 324:406fd2029f23 1830 * Values:
mbed_official 324:406fd2029f23 1831 * - 0 - Do not clear the TCR[TCNT] field.
mbed_official 324:406fd2029f23 1832 * - 1 - Clear the TCR[TCNT] field.
mbed_official 324:406fd2029f23 1833 */
mbed_official 324:406fd2029f23 1834 /*@{*/
mbed_official 324:406fd2029f23 1835 #define BP_SPI_PUSHR_CTCNT (26U) /*!< Bit position for SPI_PUSHR_CTCNT. */
mbed_official 324:406fd2029f23 1836 #define BM_SPI_PUSHR_CTCNT (0x04000000U) /*!< Bit mask for SPI_PUSHR_CTCNT. */
mbed_official 324:406fd2029f23 1837 #define BS_SPI_PUSHR_CTCNT (1U) /*!< Bit field size in bits for SPI_PUSHR_CTCNT. */
mbed_official 324:406fd2029f23 1838
mbed_official 324:406fd2029f23 1839 /*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
mbed_official 324:406fd2029f23 1840 #define BR_SPI_PUSHR_CTCNT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT))
mbed_official 324:406fd2029f23 1841
mbed_official 324:406fd2029f23 1842 /*! @brief Format value for bitfield SPI_PUSHR_CTCNT. */
mbed_official 324:406fd2029f23 1843 #define BF_SPI_PUSHR_CTCNT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTCNT) & BM_SPI_PUSHR_CTCNT)
mbed_official 324:406fd2029f23 1844
mbed_official 324:406fd2029f23 1845 /*! @brief Set the CTCNT field to a new value. */
mbed_official 324:406fd2029f23 1846 #define BW_SPI_PUSHR_CTCNT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CTCNT) = (v))
mbed_official 324:406fd2029f23 1847 /*@}*/
mbed_official 324:406fd2029f23 1848
mbed_official 324:406fd2029f23 1849 /*!
mbed_official 324:406fd2029f23 1850 * @name Register SPI_PUSHR, field EOQ[27] (RW)
mbed_official 324:406fd2029f23 1851 *
mbed_official 324:406fd2029f23 1852 * Host software uses this bit to signal to the module that the current SPI
mbed_official 324:406fd2029f23 1853 * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
mbed_official 324:406fd2029f23 1854 * SR is set.
mbed_official 324:406fd2029f23 1855 *
mbed_official 324:406fd2029f23 1856 * Values:
mbed_official 324:406fd2029f23 1857 * - 0 - The SPI data is not the last data to transfer.
mbed_official 324:406fd2029f23 1858 * - 1 - The SPI data is the last data to transfer.
mbed_official 324:406fd2029f23 1859 */
mbed_official 324:406fd2029f23 1860 /*@{*/
mbed_official 324:406fd2029f23 1861 #define BP_SPI_PUSHR_EOQ (27U) /*!< Bit position for SPI_PUSHR_EOQ. */
mbed_official 324:406fd2029f23 1862 #define BM_SPI_PUSHR_EOQ (0x08000000U) /*!< Bit mask for SPI_PUSHR_EOQ. */
mbed_official 324:406fd2029f23 1863 #define BS_SPI_PUSHR_EOQ (1U) /*!< Bit field size in bits for SPI_PUSHR_EOQ. */
mbed_official 324:406fd2029f23 1864
mbed_official 324:406fd2029f23 1865 /*! @brief Read current value of the SPI_PUSHR_EOQ field. */
mbed_official 324:406fd2029f23 1866 #define BR_SPI_PUSHR_EOQ(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ))
mbed_official 324:406fd2029f23 1867
mbed_official 324:406fd2029f23 1868 /*! @brief Format value for bitfield SPI_PUSHR_EOQ. */
mbed_official 324:406fd2029f23 1869 #define BF_SPI_PUSHR_EOQ(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_EOQ) & BM_SPI_PUSHR_EOQ)
mbed_official 324:406fd2029f23 1870
mbed_official 324:406fd2029f23 1871 /*! @brief Set the EOQ field to a new value. */
mbed_official 324:406fd2029f23 1872 #define BW_SPI_PUSHR_EOQ(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_EOQ) = (v))
mbed_official 324:406fd2029f23 1873 /*@}*/
mbed_official 324:406fd2029f23 1874
mbed_official 324:406fd2029f23 1875 /*!
mbed_official 324:406fd2029f23 1876 * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
mbed_official 324:406fd2029f23 1877 *
mbed_official 324:406fd2029f23 1878 * Selects which CTAR to use in master mode to specify the transfer attributes
mbed_official 324:406fd2029f23 1879 * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
mbed_official 324:406fd2029f23 1880 * configuration details to determine how many CTARs this device has. You should
mbed_official 324:406fd2029f23 1881 * not program a value in this field for a register that is not present.
mbed_official 324:406fd2029f23 1882 *
mbed_official 324:406fd2029f23 1883 * Values:
mbed_official 324:406fd2029f23 1884 * - 000 - CTAR0
mbed_official 324:406fd2029f23 1885 * - 001 - CTAR1
mbed_official 324:406fd2029f23 1886 * - 010 - Reserved
mbed_official 324:406fd2029f23 1887 * - 011 - Reserved
mbed_official 324:406fd2029f23 1888 * - 100 - Reserved
mbed_official 324:406fd2029f23 1889 * - 101 - Reserved
mbed_official 324:406fd2029f23 1890 * - 110 - Reserved
mbed_official 324:406fd2029f23 1891 * - 111 - Reserved
mbed_official 324:406fd2029f23 1892 */
mbed_official 324:406fd2029f23 1893 /*@{*/
mbed_official 324:406fd2029f23 1894 #define BP_SPI_PUSHR_CTAS (28U) /*!< Bit position for SPI_PUSHR_CTAS. */
mbed_official 324:406fd2029f23 1895 #define BM_SPI_PUSHR_CTAS (0x70000000U) /*!< Bit mask for SPI_PUSHR_CTAS. */
mbed_official 324:406fd2029f23 1896 #define BS_SPI_PUSHR_CTAS (3U) /*!< Bit field size in bits for SPI_PUSHR_CTAS. */
mbed_official 324:406fd2029f23 1897
mbed_official 324:406fd2029f23 1898 /*! @brief Read current value of the SPI_PUSHR_CTAS field. */
mbed_official 324:406fd2029f23 1899 #define BR_SPI_PUSHR_CTAS(x) (HW_SPI_PUSHR(x).B.CTAS)
mbed_official 324:406fd2029f23 1900
mbed_official 324:406fd2029f23 1901 /*! @brief Format value for bitfield SPI_PUSHR_CTAS. */
mbed_official 324:406fd2029f23 1902 #define BF_SPI_PUSHR_CTAS(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CTAS) & BM_SPI_PUSHR_CTAS)
mbed_official 324:406fd2029f23 1903
mbed_official 324:406fd2029f23 1904 /*! @brief Set the CTAS field to a new value. */
mbed_official 324:406fd2029f23 1905 #define BW_SPI_PUSHR_CTAS(x, v) (HW_SPI_PUSHR_WR(x, (HW_SPI_PUSHR_RD(x) & ~BM_SPI_PUSHR_CTAS) | BF_SPI_PUSHR_CTAS(v)))
mbed_official 324:406fd2029f23 1906 /*@}*/
mbed_official 324:406fd2029f23 1907
mbed_official 324:406fd2029f23 1908 /*!
mbed_official 324:406fd2029f23 1909 * @name Register SPI_PUSHR, field CONT[31] (RW)
mbed_official 324:406fd2029f23 1910 *
mbed_official 324:406fd2029f23 1911 * Selects a continuous selection format. The bit is used in SPI Master mode.
mbed_official 324:406fd2029f23 1912 * The bit enables the selected PCS signals to remain asserted between transfers.
mbed_official 324:406fd2029f23 1913 *
mbed_official 324:406fd2029f23 1914 * Values:
mbed_official 324:406fd2029f23 1915 * - 0 - Return PCSn signals to their inactive state between transfers.
mbed_official 324:406fd2029f23 1916 * - 1 - Keep PCSn signals asserted between transfers.
mbed_official 324:406fd2029f23 1917 */
mbed_official 324:406fd2029f23 1918 /*@{*/
mbed_official 324:406fd2029f23 1919 #define BP_SPI_PUSHR_CONT (31U) /*!< Bit position for SPI_PUSHR_CONT. */
mbed_official 324:406fd2029f23 1920 #define BM_SPI_PUSHR_CONT (0x80000000U) /*!< Bit mask for SPI_PUSHR_CONT. */
mbed_official 324:406fd2029f23 1921 #define BS_SPI_PUSHR_CONT (1U) /*!< Bit field size in bits for SPI_PUSHR_CONT. */
mbed_official 324:406fd2029f23 1922
mbed_official 324:406fd2029f23 1923 /*! @brief Read current value of the SPI_PUSHR_CONT field. */
mbed_official 324:406fd2029f23 1924 #define BR_SPI_PUSHR_CONT(x) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT))
mbed_official 324:406fd2029f23 1925
mbed_official 324:406fd2029f23 1926 /*! @brief Format value for bitfield SPI_PUSHR_CONT. */
mbed_official 324:406fd2029f23 1927 #define BF_SPI_PUSHR_CONT(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_CONT) & BM_SPI_PUSHR_CONT)
mbed_official 324:406fd2029f23 1928
mbed_official 324:406fd2029f23 1929 /*! @brief Set the CONT field to a new value. */
mbed_official 324:406fd2029f23 1930 #define BW_SPI_PUSHR_CONT(x, v) (BITBAND_ACCESS32(HW_SPI_PUSHR_ADDR(x), BP_SPI_PUSHR_CONT) = (v))
mbed_official 324:406fd2029f23 1931 /*@}*/
mbed_official 324:406fd2029f23 1932 /*******************************************************************************
mbed_official 324:406fd2029f23 1933 * HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
mbed_official 324:406fd2029f23 1934 ******************************************************************************/
mbed_official 324:406fd2029f23 1935
mbed_official 324:406fd2029f23 1936 /*!
mbed_official 324:406fd2029f23 1937 * @brief HW_SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
mbed_official 324:406fd2029f23 1938 *
mbed_official 324:406fd2029f23 1939 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1940 *
mbed_official 324:406fd2029f23 1941 * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
mbed_official 324:406fd2029f23 1942 * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
mbed_official 324:406fd2029f23 1943 * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
mbed_official 324:406fd2029f23 1944 * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
mbed_official 324:406fd2029f23 1945 * SPI Frame operation.
mbed_official 324:406fd2029f23 1946 */
mbed_official 324:406fd2029f23 1947 typedef union _hw_spi_pushr_slave
mbed_official 324:406fd2029f23 1948 {
mbed_official 324:406fd2029f23 1949 uint32_t U;
mbed_official 324:406fd2029f23 1950 struct _hw_spi_pushr_slave_bitfields
mbed_official 324:406fd2029f23 1951 {
mbed_official 324:406fd2029f23 1952 uint32_t TXDATA : 32; /*!< [31:0] Transmit Data */
mbed_official 324:406fd2029f23 1953 } B;
mbed_official 324:406fd2029f23 1954 } hw_spi_pushr_slave_t;
mbed_official 324:406fd2029f23 1955
mbed_official 324:406fd2029f23 1956 /*!
mbed_official 324:406fd2029f23 1957 * @name Constants and macros for entire SPI_PUSHR_SLAVE register
mbed_official 324:406fd2029f23 1958 */
mbed_official 324:406fd2029f23 1959 /*@{*/
mbed_official 324:406fd2029f23 1960 #define HW_SPI_PUSHR_SLAVE_ADDR(x) ((x) + 0x34U)
mbed_official 324:406fd2029f23 1961
mbed_official 324:406fd2029f23 1962 #define HW_SPI_PUSHR_SLAVE(x) (*(__IO hw_spi_pushr_slave_t *) HW_SPI_PUSHR_SLAVE_ADDR(x))
mbed_official 324:406fd2029f23 1963 #define HW_SPI_PUSHR_SLAVE_RD(x) (HW_SPI_PUSHR_SLAVE(x).U)
mbed_official 324:406fd2029f23 1964 #define HW_SPI_PUSHR_SLAVE_WR(x, v) (HW_SPI_PUSHR_SLAVE(x).U = (v))
mbed_official 324:406fd2029f23 1965 #define HW_SPI_PUSHR_SLAVE_SET(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) | (v)))
mbed_official 324:406fd2029f23 1966 #define HW_SPI_PUSHR_SLAVE_CLR(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1967 #define HW_SPI_PUSHR_SLAVE_TOG(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, HW_SPI_PUSHR_SLAVE_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1968 /*@}*/
mbed_official 324:406fd2029f23 1969
mbed_official 324:406fd2029f23 1970 /*
mbed_official 324:406fd2029f23 1971 * Constants & macros for individual SPI_PUSHR_SLAVE bitfields
mbed_official 324:406fd2029f23 1972 */
mbed_official 324:406fd2029f23 1973
mbed_official 324:406fd2029f23 1974 /*!
mbed_official 324:406fd2029f23 1975 * @name Register SPI_PUSHR_SLAVE, field TXDATA[31:0] (RW)
mbed_official 324:406fd2029f23 1976 *
mbed_official 324:406fd2029f23 1977 * Holds SPI data to be transferred according to the associated SPI command.
mbed_official 324:406fd2029f23 1978 */
mbed_official 324:406fd2029f23 1979 /*@{*/
mbed_official 324:406fd2029f23 1980 #define BP_SPI_PUSHR_SLAVE_TXDATA (0U) /*!< Bit position for SPI_PUSHR_SLAVE_TXDATA. */
mbed_official 324:406fd2029f23 1981 #define BM_SPI_PUSHR_SLAVE_TXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_PUSHR_SLAVE_TXDATA. */
mbed_official 324:406fd2029f23 1982 #define BS_SPI_PUSHR_SLAVE_TXDATA (32U) /*!< Bit field size in bits for SPI_PUSHR_SLAVE_TXDATA. */
mbed_official 324:406fd2029f23 1983
mbed_official 324:406fd2029f23 1984 /*! @brief Read current value of the SPI_PUSHR_SLAVE_TXDATA field. */
mbed_official 324:406fd2029f23 1985 #define BR_SPI_PUSHR_SLAVE_TXDATA(x) (HW_SPI_PUSHR_SLAVE(x).U)
mbed_official 324:406fd2029f23 1986
mbed_official 324:406fd2029f23 1987 /*! @brief Format value for bitfield SPI_PUSHR_SLAVE_TXDATA. */
mbed_official 324:406fd2029f23 1988 #define BF_SPI_PUSHR_SLAVE_TXDATA(v) ((uint32_t)((uint32_t)(v) << BP_SPI_PUSHR_SLAVE_TXDATA) & BM_SPI_PUSHR_SLAVE_TXDATA)
mbed_official 324:406fd2029f23 1989
mbed_official 324:406fd2029f23 1990 /*! @brief Set the TXDATA field to a new value. */
mbed_official 324:406fd2029f23 1991 #define BW_SPI_PUSHR_SLAVE_TXDATA(x, v) (HW_SPI_PUSHR_SLAVE_WR(x, v))
mbed_official 324:406fd2029f23 1992 /*@}*/
mbed_official 324:406fd2029f23 1993
mbed_official 324:406fd2029f23 1994 /*******************************************************************************
mbed_official 324:406fd2029f23 1995 * HW_SPI_POPR - POP RX FIFO Register
mbed_official 324:406fd2029f23 1996 ******************************************************************************/
mbed_official 324:406fd2029f23 1997
mbed_official 324:406fd2029f23 1998 /*!
mbed_official 324:406fd2029f23 1999 * @brief HW_SPI_POPR - POP RX FIFO Register (RO)
mbed_official 324:406fd2029f23 2000 *
mbed_official 324:406fd2029f23 2001 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2002 *
mbed_official 324:406fd2029f23 2003 * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
mbed_official 324:406fd2029f23 2004 * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
mbed_official 324:406fd2029f23 2005 * this register will generate a Transfer Error.
mbed_official 324:406fd2029f23 2006 */
mbed_official 324:406fd2029f23 2007 typedef union _hw_spi_popr
mbed_official 324:406fd2029f23 2008 {
mbed_official 324:406fd2029f23 2009 uint32_t U;
mbed_official 324:406fd2029f23 2010 struct _hw_spi_popr_bitfields
mbed_official 324:406fd2029f23 2011 {
mbed_official 324:406fd2029f23 2012 uint32_t RXDATA : 32; /*!< [31:0] Received Data */
mbed_official 324:406fd2029f23 2013 } B;
mbed_official 324:406fd2029f23 2014 } hw_spi_popr_t;
mbed_official 324:406fd2029f23 2015
mbed_official 324:406fd2029f23 2016 /*!
mbed_official 324:406fd2029f23 2017 * @name Constants and macros for entire SPI_POPR register
mbed_official 324:406fd2029f23 2018 */
mbed_official 324:406fd2029f23 2019 /*@{*/
mbed_official 324:406fd2029f23 2020 #define HW_SPI_POPR_ADDR(x) ((x) + 0x38U)
mbed_official 324:406fd2029f23 2021
mbed_official 324:406fd2029f23 2022 #define HW_SPI_POPR(x) (*(__I hw_spi_popr_t *) HW_SPI_POPR_ADDR(x))
mbed_official 324:406fd2029f23 2023 #define HW_SPI_POPR_RD(x) (HW_SPI_POPR(x).U)
mbed_official 324:406fd2029f23 2024 /*@}*/
mbed_official 324:406fd2029f23 2025
mbed_official 324:406fd2029f23 2026 /*
mbed_official 324:406fd2029f23 2027 * Constants & macros for individual SPI_POPR bitfields
mbed_official 324:406fd2029f23 2028 */
mbed_official 324:406fd2029f23 2029
mbed_official 324:406fd2029f23 2030 /*!
mbed_official 324:406fd2029f23 2031 * @name Register SPI_POPR, field RXDATA[31:0] (RO)
mbed_official 324:406fd2029f23 2032 *
mbed_official 324:406fd2029f23 2033 * Contains the SPI data from the RX FIFO entry to which the Pop Next Data
mbed_official 324:406fd2029f23 2034 * Pointer points.
mbed_official 324:406fd2029f23 2035 */
mbed_official 324:406fd2029f23 2036 /*@{*/
mbed_official 324:406fd2029f23 2037 #define BP_SPI_POPR_RXDATA (0U) /*!< Bit position for SPI_POPR_RXDATA. */
mbed_official 324:406fd2029f23 2038 #define BM_SPI_POPR_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_POPR_RXDATA. */
mbed_official 324:406fd2029f23 2039 #define BS_SPI_POPR_RXDATA (32U) /*!< Bit field size in bits for SPI_POPR_RXDATA. */
mbed_official 324:406fd2029f23 2040
mbed_official 324:406fd2029f23 2041 /*! @brief Read current value of the SPI_POPR_RXDATA field. */
mbed_official 324:406fd2029f23 2042 #define BR_SPI_POPR_RXDATA(x) (HW_SPI_POPR(x).U)
mbed_official 324:406fd2029f23 2043 /*@}*/
mbed_official 324:406fd2029f23 2044
mbed_official 324:406fd2029f23 2045 /*******************************************************************************
mbed_official 324:406fd2029f23 2046 * HW_SPI_TXFRn - Transmit FIFO Registers
mbed_official 324:406fd2029f23 2047 ******************************************************************************/
mbed_official 324:406fd2029f23 2048
mbed_official 324:406fd2029f23 2049 /*!
mbed_official 324:406fd2029f23 2050 * @brief HW_SPI_TXFRn - Transmit FIFO Registers (RO)
mbed_official 324:406fd2029f23 2051 *
mbed_official 324:406fd2029f23 2052 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2053 *
mbed_official 324:406fd2029f23 2054 * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
mbed_official 324:406fd2029f23 2055 * Each register is an entry in the TX FIFO. The registers are read-only and
mbed_official 324:406fd2029f23 2056 * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
mbed_official 324:406fd2029f23 2057 * FIFO.
mbed_official 324:406fd2029f23 2058 */
mbed_official 324:406fd2029f23 2059 typedef union _hw_spi_txfrn
mbed_official 324:406fd2029f23 2060 {
mbed_official 324:406fd2029f23 2061 uint32_t U;
mbed_official 324:406fd2029f23 2062 struct _hw_spi_txfrn_bitfields
mbed_official 324:406fd2029f23 2063 {
mbed_official 324:406fd2029f23 2064 uint32_t TXDATA : 16; /*!< [15:0] Transmit Data */
mbed_official 324:406fd2029f23 2065 uint32_t TXCMD_TXDATA : 16; /*!< [31:16] Transmit Command or Transmit
mbed_official 324:406fd2029f23 2066 * Data */
mbed_official 324:406fd2029f23 2067 } B;
mbed_official 324:406fd2029f23 2068 } hw_spi_txfrn_t;
mbed_official 324:406fd2029f23 2069
mbed_official 324:406fd2029f23 2070 /*!
mbed_official 324:406fd2029f23 2071 * @name Constants and macros for entire SPI_TXFRn register
mbed_official 324:406fd2029f23 2072 */
mbed_official 324:406fd2029f23 2073 /*@{*/
mbed_official 324:406fd2029f23 2074 #define HW_SPI_TXFRn_COUNT (4U)
mbed_official 324:406fd2029f23 2075
mbed_official 324:406fd2029f23 2076 #define HW_SPI_TXFRn_ADDR(x, n) ((x) + 0x3CU + (0x4U * (n)))
mbed_official 324:406fd2029f23 2077
mbed_official 324:406fd2029f23 2078 #define HW_SPI_TXFRn(x, n) (*(__I hw_spi_txfrn_t *) HW_SPI_TXFRn_ADDR(x, n))
mbed_official 324:406fd2029f23 2079 #define HW_SPI_TXFRn_RD(x, n) (HW_SPI_TXFRn(x, n).U)
mbed_official 324:406fd2029f23 2080 /*@}*/
mbed_official 324:406fd2029f23 2081
mbed_official 324:406fd2029f23 2082 /*
mbed_official 324:406fd2029f23 2083 * Constants & macros for individual SPI_TXFRn bitfields
mbed_official 324:406fd2029f23 2084 */
mbed_official 324:406fd2029f23 2085
mbed_official 324:406fd2029f23 2086 /*!
mbed_official 324:406fd2029f23 2087 * @name Register SPI_TXFRn, field TXDATA[15:0] (RO)
mbed_official 324:406fd2029f23 2088 *
mbed_official 324:406fd2029f23 2089 * Contains the SPI data to be shifted out.
mbed_official 324:406fd2029f23 2090 */
mbed_official 324:406fd2029f23 2091 /*@{*/
mbed_official 324:406fd2029f23 2092 #define BP_SPI_TXFRn_TXDATA (0U) /*!< Bit position for SPI_TXFRn_TXDATA. */
mbed_official 324:406fd2029f23 2093 #define BM_SPI_TXFRn_TXDATA (0x0000FFFFU) /*!< Bit mask for SPI_TXFRn_TXDATA. */
mbed_official 324:406fd2029f23 2094 #define BS_SPI_TXFRn_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXDATA. */
mbed_official 324:406fd2029f23 2095
mbed_official 324:406fd2029f23 2096 /*! @brief Read current value of the SPI_TXFRn_TXDATA field. */
mbed_official 324:406fd2029f23 2097 #define BR_SPI_TXFRn_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXDATA)
mbed_official 324:406fd2029f23 2098 /*@}*/
mbed_official 324:406fd2029f23 2099
mbed_official 324:406fd2029f23 2100 /*!
mbed_official 324:406fd2029f23 2101 * @name Register SPI_TXFRn, field TXCMD_TXDATA[31:16] (RO)
mbed_official 324:406fd2029f23 2102 *
mbed_official 324:406fd2029f23 2103 * In Master mode the TXCMD field contains the command that sets the transfer
mbed_official 324:406fd2029f23 2104 * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
mbed_official 324:406fd2029f23 2105 * the SPI data to be shifted out.
mbed_official 324:406fd2029f23 2106 */
mbed_official 324:406fd2029f23 2107 /*@{*/
mbed_official 324:406fd2029f23 2108 #define BP_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit position for SPI_TXFRn_TXCMD_TXDATA. */
mbed_official 324:406fd2029f23 2109 #define BM_SPI_TXFRn_TXCMD_TXDATA (0xFFFF0000U) /*!< Bit mask for SPI_TXFRn_TXCMD_TXDATA. */
mbed_official 324:406fd2029f23 2110 #define BS_SPI_TXFRn_TXCMD_TXDATA (16U) /*!< Bit field size in bits for SPI_TXFRn_TXCMD_TXDATA. */
mbed_official 324:406fd2029f23 2111
mbed_official 324:406fd2029f23 2112 /*! @brief Read current value of the SPI_TXFRn_TXCMD_TXDATA field. */
mbed_official 324:406fd2029f23 2113 #define BR_SPI_TXFRn_TXCMD_TXDATA(x, n) (HW_SPI_TXFRn(x, n).B.TXCMD_TXDATA)
mbed_official 324:406fd2029f23 2114 /*@}*/
mbed_official 324:406fd2029f23 2115
mbed_official 324:406fd2029f23 2116 /*******************************************************************************
mbed_official 324:406fd2029f23 2117 * HW_SPI_RXFRn - Receive FIFO Registers
mbed_official 324:406fd2029f23 2118 ******************************************************************************/
mbed_official 324:406fd2029f23 2119
mbed_official 324:406fd2029f23 2120 /*!
mbed_official 324:406fd2029f23 2121 * @brief HW_SPI_RXFRn - Receive FIFO Registers (RO)
mbed_official 324:406fd2029f23 2122 *
mbed_official 324:406fd2029f23 2123 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2124 *
mbed_official 324:406fd2029f23 2125 * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
mbed_official 324:406fd2029f23 2126 * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
mbed_official 324:406fd2029f23 2127 * RXFRx registers does not alter the state of the RX FIFO.
mbed_official 324:406fd2029f23 2128 */
mbed_official 324:406fd2029f23 2129 typedef union _hw_spi_rxfrn
mbed_official 324:406fd2029f23 2130 {
mbed_official 324:406fd2029f23 2131 uint32_t U;
mbed_official 324:406fd2029f23 2132 struct _hw_spi_rxfrn_bitfields
mbed_official 324:406fd2029f23 2133 {
mbed_official 324:406fd2029f23 2134 uint32_t RXDATA : 32; /*!< [31:0] Receive Data */
mbed_official 324:406fd2029f23 2135 } B;
mbed_official 324:406fd2029f23 2136 } hw_spi_rxfrn_t;
mbed_official 324:406fd2029f23 2137
mbed_official 324:406fd2029f23 2138 /*!
mbed_official 324:406fd2029f23 2139 * @name Constants and macros for entire SPI_RXFRn register
mbed_official 324:406fd2029f23 2140 */
mbed_official 324:406fd2029f23 2141 /*@{*/
mbed_official 324:406fd2029f23 2142 #define HW_SPI_RXFRn_COUNT (4U)
mbed_official 324:406fd2029f23 2143
mbed_official 324:406fd2029f23 2144 #define HW_SPI_RXFRn_ADDR(x, n) ((x) + 0x7CU + (0x4U * (n)))
mbed_official 324:406fd2029f23 2145
mbed_official 324:406fd2029f23 2146 #define HW_SPI_RXFRn(x, n) (*(__I hw_spi_rxfrn_t *) HW_SPI_RXFRn_ADDR(x, n))
mbed_official 324:406fd2029f23 2147 #define HW_SPI_RXFRn_RD(x, n) (HW_SPI_RXFRn(x, n).U)
mbed_official 324:406fd2029f23 2148 /*@}*/
mbed_official 324:406fd2029f23 2149
mbed_official 324:406fd2029f23 2150 /*
mbed_official 324:406fd2029f23 2151 * Constants & macros for individual SPI_RXFRn bitfields
mbed_official 324:406fd2029f23 2152 */
mbed_official 324:406fd2029f23 2153
mbed_official 324:406fd2029f23 2154 /*!
mbed_official 324:406fd2029f23 2155 * @name Register SPI_RXFRn, field RXDATA[31:0] (RO)
mbed_official 324:406fd2029f23 2156 *
mbed_official 324:406fd2029f23 2157 * Contains the received SPI data.
mbed_official 324:406fd2029f23 2158 */
mbed_official 324:406fd2029f23 2159 /*@{*/
mbed_official 324:406fd2029f23 2160 #define BP_SPI_RXFRn_RXDATA (0U) /*!< Bit position for SPI_RXFRn_RXDATA. */
mbed_official 324:406fd2029f23 2161 #define BM_SPI_RXFRn_RXDATA (0xFFFFFFFFU) /*!< Bit mask for SPI_RXFRn_RXDATA. */
mbed_official 324:406fd2029f23 2162 #define BS_SPI_RXFRn_RXDATA (32U) /*!< Bit field size in bits for SPI_RXFRn_RXDATA. */
mbed_official 324:406fd2029f23 2163
mbed_official 324:406fd2029f23 2164 /*! @brief Read current value of the SPI_RXFRn_RXDATA field. */
mbed_official 324:406fd2029f23 2165 #define BR_SPI_RXFRn_RXDATA(x, n) (HW_SPI_RXFRn(x, n).U)
mbed_official 324:406fd2029f23 2166 /*@}*/
mbed_official 324:406fd2029f23 2167
mbed_official 324:406fd2029f23 2168 /*
mbed_official 324:406fd2029f23 2169 ** Start of section using anonymous unions
mbed_official 324:406fd2029f23 2170 */
mbed_official 324:406fd2029f23 2171
mbed_official 324:406fd2029f23 2172 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 2173 #pragma push
mbed_official 324:406fd2029f23 2174 #pragma anon_unions
mbed_official 324:406fd2029f23 2175 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 2176 #pragma push
mbed_official 324:406fd2029f23 2177 #pragma cpp_extensions on
mbed_official 324:406fd2029f23 2178 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 2179 /* anonymous unions are enabled by default */
mbed_official 324:406fd2029f23 2180 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 2181 #pragma language=extended
mbed_official 324:406fd2029f23 2182 #else
mbed_official 324:406fd2029f23 2183 #error Not supported compiler type
mbed_official 324:406fd2029f23 2184 #endif
mbed_official 324:406fd2029f23 2185
mbed_official 324:406fd2029f23 2186 /*******************************************************************************
mbed_official 324:406fd2029f23 2187 * hw_spi_t - module struct
mbed_official 324:406fd2029f23 2188 ******************************************************************************/
mbed_official 324:406fd2029f23 2189 /*!
mbed_official 324:406fd2029f23 2190 * @brief All SPI module registers.
mbed_official 324:406fd2029f23 2191 */
mbed_official 324:406fd2029f23 2192 #pragma pack(1)
mbed_official 324:406fd2029f23 2193 typedef struct _hw_spi
mbed_official 324:406fd2029f23 2194 {
mbed_official 324:406fd2029f23 2195 __IO hw_spi_mcr_t MCR; /*!< [0x0] Module Configuration Register */
mbed_official 324:406fd2029f23 2196 uint8_t _reserved0[4];
mbed_official 324:406fd2029f23 2197 __IO hw_spi_tcr_t TCR; /*!< [0x8] Transfer Count Register */
mbed_official 324:406fd2029f23 2198 union {
mbed_official 324:406fd2029f23 2199 __IO hw_spi_ctarn_t CTARn[2]; /*!< [0xC] Clock and Transfer Attributes Register (In Master Mode) */
mbed_official 324:406fd2029f23 2200 __IO hw_spi_ctarn_slave_t CTARn_SLAVE[1]; /*!< [0xC] Clock and Transfer Attributes Register (In Slave Mode) */
mbed_official 324:406fd2029f23 2201 };
mbed_official 324:406fd2029f23 2202 uint8_t _reserved1[24];
mbed_official 324:406fd2029f23 2203 __IO hw_spi_sr_t SR; /*!< [0x2C] Status Register */
mbed_official 324:406fd2029f23 2204 __IO hw_spi_rser_t RSER; /*!< [0x30] DMA/Interrupt Request Select and Enable Register */
mbed_official 324:406fd2029f23 2205 union {
mbed_official 324:406fd2029f23 2206 __IO hw_spi_pushr_t PUSHR; /*!< [0x34] PUSH TX FIFO Register In Master Mode */
mbed_official 324:406fd2029f23 2207 __IO hw_spi_pushr_slave_t PUSHR_SLAVE; /*!< [0x34] PUSH TX FIFO Register In Slave Mode */
mbed_official 324:406fd2029f23 2208 };
mbed_official 324:406fd2029f23 2209 __I hw_spi_popr_t POPR; /*!< [0x38] POP RX FIFO Register */
mbed_official 324:406fd2029f23 2210 __I hw_spi_txfrn_t TXFRn[4]; /*!< [0x3C] Transmit FIFO Registers */
mbed_official 324:406fd2029f23 2211 uint8_t _reserved2[48];
mbed_official 324:406fd2029f23 2212 __I hw_spi_rxfrn_t RXFRn[4]; /*!< [0x7C] Receive FIFO Registers */
mbed_official 324:406fd2029f23 2213 } hw_spi_t;
mbed_official 324:406fd2029f23 2214 #pragma pack()
mbed_official 324:406fd2029f23 2215
mbed_official 324:406fd2029f23 2216 /*! @brief Macro to access all SPI registers. */
mbed_official 324:406fd2029f23 2217 /*! @param x SPI module instance base address. */
mbed_official 324:406fd2029f23 2218 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 2219 * use the '&' operator, like <code>&HW_SPI(SPI0_BASE)</code>. */
mbed_official 324:406fd2029f23 2220 #define HW_SPI(x) (*(hw_spi_t *)(x))
mbed_official 324:406fd2029f23 2221
mbed_official 324:406fd2029f23 2222 /*
mbed_official 324:406fd2029f23 2223 ** End of section using anonymous unions
mbed_official 324:406fd2029f23 2224 */
mbed_official 324:406fd2029f23 2225
mbed_official 324:406fd2029f23 2226 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 2227 #pragma pop
mbed_official 324:406fd2029f23 2228 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 2229 #pragma pop
mbed_official 324:406fd2029f23 2230 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 2231 /* leave anonymous unions enabled */
mbed_official 324:406fd2029f23 2232 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 2233 #pragma language=default
mbed_official 324:406fd2029f23 2234 #else
mbed_official 324:406fd2029f23 2235 #error Not supported compiler type
mbed_official 324:406fd2029f23 2236 #endif
mbed_official 324:406fd2029f23 2237
mbed_official 324:406fd2029f23 2238 #endif /* __HW_SPI_REGISTERS_H__ */
mbed_official 324:406fd2029f23 2239 /* EOF */