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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_smc.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_SMC_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_SMC_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 SMC
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * System Mode Controller
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_SMC_PMPROT - Power Mode Protection register
mbed_official 324:406fd2029f23 90 * - HW_SMC_PMCTRL - Power Mode Control register
mbed_official 324:406fd2029f23 91 * - HW_SMC_STOPCTRL - Stop Control Register
mbed_official 324:406fd2029f23 92 * - HW_SMC_PMSTAT - Power Mode Status register
mbed_official 324:406fd2029f23 93 *
mbed_official 324:406fd2029f23 94 * - hw_smc_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 95 */
mbed_official 324:406fd2029f23 96
mbed_official 324:406fd2029f23 97 #define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
mbed_official 324:406fd2029f23 98
mbed_official 324:406fd2029f23 99 /*******************************************************************************
mbed_official 324:406fd2029f23 100 * HW_SMC_PMPROT - Power Mode Protection register
mbed_official 324:406fd2029f23 101 ******************************************************************************/
mbed_official 324:406fd2029f23 102
mbed_official 324:406fd2029f23 103 /*!
mbed_official 324:406fd2029f23 104 * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
mbed_official 324:406fd2029f23 105 *
mbed_official 324:406fd2029f23 106 * Reset value: 0x00U
mbed_official 324:406fd2029f23 107 *
mbed_official 324:406fd2029f23 108 * This register provides protection for entry into any low-power run or stop
mbed_official 324:406fd2029f23 109 * mode. The enabling of the low-power run or stop mode occurs by configuring the
mbed_official 324:406fd2029f23 110 * Power Mode Control register (PMCTRL). The PMPROT register can be written only
mbed_official 324:406fd2029f23 111 * once after any system reset. If the MCU is configured for a disallowed or
mbed_official 324:406fd2029f23 112 * reserved power mode, the MCU remains in its current power mode. For example, if the
mbed_official 324:406fd2029f23 113 * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
mbed_official 324:406fd2029f23 114 * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
mbed_official 324:406fd2029f23 115 * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
mbed_official 324:406fd2029f23 116 * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
mbed_official 324:406fd2029f23 117 * that do not trigger Chip Reset not VLLS. See the Reset section details for more
mbed_official 324:406fd2029f23 118 * information.
mbed_official 324:406fd2029f23 119 */
mbed_official 324:406fd2029f23 120 typedef union _hw_smc_pmprot
mbed_official 324:406fd2029f23 121 {
mbed_official 324:406fd2029f23 122 uint8_t U;
mbed_official 324:406fd2029f23 123 struct _hw_smc_pmprot_bitfields
mbed_official 324:406fd2029f23 124 {
mbed_official 324:406fd2029f23 125 uint8_t RESERVED0 : 1; /*!< [0] */
mbed_official 324:406fd2029f23 126 uint8_t AVLLS : 1; /*!< [1] Allow Very-Low-Leakage Stop Mode */
mbed_official 324:406fd2029f23 127 uint8_t RESERVED1 : 1; /*!< [2] */
mbed_official 324:406fd2029f23 128 uint8_t ALLS : 1; /*!< [3] Allow Low-Leakage Stop Mode */
mbed_official 324:406fd2029f23 129 uint8_t RESERVED2 : 1; /*!< [4] */
mbed_official 324:406fd2029f23 130 uint8_t AVLP : 1; /*!< [5] Allow Very-Low-Power Modes */
mbed_official 324:406fd2029f23 131 uint8_t RESERVED3 : 1; /*!< [6] */
mbed_official 324:406fd2029f23 132 uint8_t AHSRUN : 1; /*!< [7] Allow High Speed Run mode */
mbed_official 324:406fd2029f23 133 } B;
mbed_official 324:406fd2029f23 134 } hw_smc_pmprot_t;
mbed_official 324:406fd2029f23 135
mbed_official 324:406fd2029f23 136 /*!
mbed_official 324:406fd2029f23 137 * @name Constants and macros for entire SMC_PMPROT register
mbed_official 324:406fd2029f23 138 */
mbed_official 324:406fd2029f23 139 /*@{*/
mbed_official 324:406fd2029f23 140 #define HW_SMC_PMPROT_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 141
mbed_official 324:406fd2029f23 142 #define HW_SMC_PMPROT(x) (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
mbed_official 324:406fd2029f23 143 #define HW_SMC_PMPROT_RD(x) (HW_SMC_PMPROT(x).U)
mbed_official 324:406fd2029f23 144 #define HW_SMC_PMPROT_WR(x, v) (HW_SMC_PMPROT(x).U = (v))
mbed_official 324:406fd2029f23 145 #define HW_SMC_PMPROT_SET(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) | (v)))
mbed_official 324:406fd2029f23 146 #define HW_SMC_PMPROT_CLR(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 147 #define HW_SMC_PMPROT_TOG(x, v) (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 148 /*@}*/
mbed_official 324:406fd2029f23 149
mbed_official 324:406fd2029f23 150 /*
mbed_official 324:406fd2029f23 151 * Constants & macros for individual SMC_PMPROT bitfields
mbed_official 324:406fd2029f23 152 */
mbed_official 324:406fd2029f23 153
mbed_official 324:406fd2029f23 154 /*!
mbed_official 324:406fd2029f23 155 * @name Register SMC_PMPROT, field AVLLS[1] (RW)
mbed_official 324:406fd2029f23 156 *
mbed_official 324:406fd2029f23 157 * Provided the appropriate control bits are set up in PMCTRL, this write once
mbed_official 324:406fd2029f23 158 * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
mbed_official 324:406fd2029f23 159 *
mbed_official 324:406fd2029f23 160 * Values:
mbed_official 324:406fd2029f23 161 * - 0 - Any VLLSx mode is not allowed
mbed_official 324:406fd2029f23 162 * - 1 - Any VLLSx mode is allowed
mbed_official 324:406fd2029f23 163 */
mbed_official 324:406fd2029f23 164 /*@{*/
mbed_official 324:406fd2029f23 165 #define BP_SMC_PMPROT_AVLLS (1U) /*!< Bit position for SMC_PMPROT_AVLLS. */
mbed_official 324:406fd2029f23 166 #define BM_SMC_PMPROT_AVLLS (0x02U) /*!< Bit mask for SMC_PMPROT_AVLLS. */
mbed_official 324:406fd2029f23 167 #define BS_SMC_PMPROT_AVLLS (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
mbed_official 324:406fd2029f23 168
mbed_official 324:406fd2029f23 169 /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
mbed_official 324:406fd2029f23 170 #define BR_SMC_PMPROT_AVLLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS))
mbed_official 324:406fd2029f23 171
mbed_official 324:406fd2029f23 172 /*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
mbed_official 324:406fd2029f23 173 #define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
mbed_official 324:406fd2029f23 174
mbed_official 324:406fd2029f23 175 /*! @brief Set the AVLLS field to a new value. */
mbed_official 324:406fd2029f23 176 #define BW_SMC_PMPROT_AVLLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS) = (v))
mbed_official 324:406fd2029f23 177 /*@}*/
mbed_official 324:406fd2029f23 178
mbed_official 324:406fd2029f23 179 /*!
mbed_official 324:406fd2029f23 180 * @name Register SMC_PMPROT, field ALLS[3] (RW)
mbed_official 324:406fd2029f23 181 *
mbed_official 324:406fd2029f23 182 * Provided the appropriate control bits are set up in PMCTRL, this write-once
mbed_official 324:406fd2029f23 183 * field allows the MCU to enter any low-leakage stop mode (LLS).
mbed_official 324:406fd2029f23 184 *
mbed_official 324:406fd2029f23 185 * Values:
mbed_official 324:406fd2029f23 186 * - 0 - Any LLSx mode is not allowed
mbed_official 324:406fd2029f23 187 * - 1 - Any LLSx mode is allowed
mbed_official 324:406fd2029f23 188 */
mbed_official 324:406fd2029f23 189 /*@{*/
mbed_official 324:406fd2029f23 190 #define BP_SMC_PMPROT_ALLS (3U) /*!< Bit position for SMC_PMPROT_ALLS. */
mbed_official 324:406fd2029f23 191 #define BM_SMC_PMPROT_ALLS (0x08U) /*!< Bit mask for SMC_PMPROT_ALLS. */
mbed_official 324:406fd2029f23 192 #define BS_SMC_PMPROT_ALLS (1U) /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
mbed_official 324:406fd2029f23 193
mbed_official 324:406fd2029f23 194 /*! @brief Read current value of the SMC_PMPROT_ALLS field. */
mbed_official 324:406fd2029f23 195 #define BR_SMC_PMPROT_ALLS(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS))
mbed_official 324:406fd2029f23 196
mbed_official 324:406fd2029f23 197 /*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
mbed_official 324:406fd2029f23 198 #define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
mbed_official 324:406fd2029f23 199
mbed_official 324:406fd2029f23 200 /*! @brief Set the ALLS field to a new value. */
mbed_official 324:406fd2029f23 201 #define BW_SMC_PMPROT_ALLS(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS) = (v))
mbed_official 324:406fd2029f23 202 /*@}*/
mbed_official 324:406fd2029f23 203
mbed_official 324:406fd2029f23 204 /*!
mbed_official 324:406fd2029f23 205 * @name Register SMC_PMPROT, field AVLP[5] (RW)
mbed_official 324:406fd2029f23 206 *
mbed_official 324:406fd2029f23 207 * Provided the appropriate control bits are set up in PMCTRL, this write-once
mbed_official 324:406fd2029f23 208 * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
mbed_official 324:406fd2029f23 209 *
mbed_official 324:406fd2029f23 210 * Values:
mbed_official 324:406fd2029f23 211 * - 0 - VLPR, VLPW, and VLPS are not allowed.
mbed_official 324:406fd2029f23 212 * - 1 - VLPR, VLPW, and VLPS are allowed.
mbed_official 324:406fd2029f23 213 */
mbed_official 324:406fd2029f23 214 /*@{*/
mbed_official 324:406fd2029f23 215 #define BP_SMC_PMPROT_AVLP (5U) /*!< Bit position for SMC_PMPROT_AVLP. */
mbed_official 324:406fd2029f23 216 #define BM_SMC_PMPROT_AVLP (0x20U) /*!< Bit mask for SMC_PMPROT_AVLP. */
mbed_official 324:406fd2029f23 217 #define BS_SMC_PMPROT_AVLP (1U) /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*! @brief Read current value of the SMC_PMPROT_AVLP field. */
mbed_official 324:406fd2029f23 220 #define BR_SMC_PMPROT_AVLP(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP))
mbed_official 324:406fd2029f23 221
mbed_official 324:406fd2029f23 222 /*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
mbed_official 324:406fd2029f23 223 #define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
mbed_official 324:406fd2029f23 224
mbed_official 324:406fd2029f23 225 /*! @brief Set the AVLP field to a new value. */
mbed_official 324:406fd2029f23 226 #define BW_SMC_PMPROT_AVLP(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP) = (v))
mbed_official 324:406fd2029f23 227 /*@}*/
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*!
mbed_official 324:406fd2029f23 230 * @name Register SMC_PMPROT, field AHSRUN[7] (RW)
mbed_official 324:406fd2029f23 231 *
mbed_official 324:406fd2029f23 232 * Provided the appropriate control bits are set up in PMCTRL, this write-once
mbed_official 324:406fd2029f23 233 * field allows the MCU to enter High Speed Run mode (HSRUN).
mbed_official 324:406fd2029f23 234 *
mbed_official 324:406fd2029f23 235 * Values:
mbed_official 324:406fd2029f23 236 * - 0 - HSRUN is not allowed
mbed_official 324:406fd2029f23 237 * - 1 - HSRUN is allowed
mbed_official 324:406fd2029f23 238 */
mbed_official 324:406fd2029f23 239 /*@{*/
mbed_official 324:406fd2029f23 240 #define BP_SMC_PMPROT_AHSRUN (7U) /*!< Bit position for SMC_PMPROT_AHSRUN. */
mbed_official 324:406fd2029f23 241 #define BM_SMC_PMPROT_AHSRUN (0x80U) /*!< Bit mask for SMC_PMPROT_AHSRUN. */
mbed_official 324:406fd2029f23 242 #define BS_SMC_PMPROT_AHSRUN (1U) /*!< Bit field size in bits for SMC_PMPROT_AHSRUN. */
mbed_official 324:406fd2029f23 243
mbed_official 324:406fd2029f23 244 /*! @brief Read current value of the SMC_PMPROT_AHSRUN field. */
mbed_official 324:406fd2029f23 245 #define BR_SMC_PMPROT_AHSRUN(x) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN))
mbed_official 324:406fd2029f23 246
mbed_official 324:406fd2029f23 247 /*! @brief Format value for bitfield SMC_PMPROT_AHSRUN. */
mbed_official 324:406fd2029f23 248 #define BF_SMC_PMPROT_AHSRUN(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AHSRUN) & BM_SMC_PMPROT_AHSRUN)
mbed_official 324:406fd2029f23 249
mbed_official 324:406fd2029f23 250 /*! @brief Set the AHSRUN field to a new value. */
mbed_official 324:406fd2029f23 251 #define BW_SMC_PMPROT_AHSRUN(x, v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AHSRUN) = (v))
mbed_official 324:406fd2029f23 252 /*@}*/
mbed_official 324:406fd2029f23 253
mbed_official 324:406fd2029f23 254 /*******************************************************************************
mbed_official 324:406fd2029f23 255 * HW_SMC_PMCTRL - Power Mode Control register
mbed_official 324:406fd2029f23 256 ******************************************************************************/
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 /*!
mbed_official 324:406fd2029f23 259 * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
mbed_official 324:406fd2029f23 260 *
mbed_official 324:406fd2029f23 261 * Reset value: 0x00U
mbed_official 324:406fd2029f23 262 *
mbed_official 324:406fd2029f23 263 * The PMCTRL register controls entry into low-power Run and Stop modes,
mbed_official 324:406fd2029f23 264 * provided that the selected power mode is allowed via an appropriate setting of the
mbed_official 324:406fd2029f23 265 * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
mbed_official 324:406fd2029f23 266 * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
mbed_official 324:406fd2029f23 267 * that do not trigger Chip POR not VLLS. See the Reset section details for more
mbed_official 324:406fd2029f23 268 * information.
mbed_official 324:406fd2029f23 269 */
mbed_official 324:406fd2029f23 270 typedef union _hw_smc_pmctrl
mbed_official 324:406fd2029f23 271 {
mbed_official 324:406fd2029f23 272 uint8_t U;
mbed_official 324:406fd2029f23 273 struct _hw_smc_pmctrl_bitfields
mbed_official 324:406fd2029f23 274 {
mbed_official 324:406fd2029f23 275 uint8_t STOPM : 3; /*!< [2:0] Stop Mode Control */
mbed_official 324:406fd2029f23 276 uint8_t STOPA : 1; /*!< [3] Stop Aborted */
mbed_official 324:406fd2029f23 277 uint8_t RESERVED0 : 1; /*!< [4] */
mbed_official 324:406fd2029f23 278 uint8_t RUNM : 2; /*!< [6:5] Run Mode Control */
mbed_official 324:406fd2029f23 279 uint8_t RESERVED1 : 1; /*!< [7] */
mbed_official 324:406fd2029f23 280 } B;
mbed_official 324:406fd2029f23 281 } hw_smc_pmctrl_t;
mbed_official 324:406fd2029f23 282
mbed_official 324:406fd2029f23 283 /*!
mbed_official 324:406fd2029f23 284 * @name Constants and macros for entire SMC_PMCTRL register
mbed_official 324:406fd2029f23 285 */
mbed_official 324:406fd2029f23 286 /*@{*/
mbed_official 324:406fd2029f23 287 #define HW_SMC_PMCTRL_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 288
mbed_official 324:406fd2029f23 289 #define HW_SMC_PMCTRL(x) (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
mbed_official 324:406fd2029f23 290 #define HW_SMC_PMCTRL_RD(x) (HW_SMC_PMCTRL(x).U)
mbed_official 324:406fd2029f23 291 #define HW_SMC_PMCTRL_WR(x, v) (HW_SMC_PMCTRL(x).U = (v))
mbed_official 324:406fd2029f23 292 #define HW_SMC_PMCTRL_SET(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 293 #define HW_SMC_PMCTRL_CLR(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 294 #define HW_SMC_PMCTRL_TOG(x, v) (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 295 /*@}*/
mbed_official 324:406fd2029f23 296
mbed_official 324:406fd2029f23 297 /*
mbed_official 324:406fd2029f23 298 * Constants & macros for individual SMC_PMCTRL bitfields
mbed_official 324:406fd2029f23 299 */
mbed_official 324:406fd2029f23 300
mbed_official 324:406fd2029f23 301 /*!
mbed_official 324:406fd2029f23 302 * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
mbed_official 324:406fd2029f23 303 *
mbed_official 324:406fd2029f23 304 * When written, controls entry into the selected stop mode when Sleep-Now or
mbed_official 324:406fd2029f23 305 * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
mbed_official 324:406fd2029f23 306 * blocked if the protection level has not been enabled using the PMPROT register.
mbed_official 324:406fd2029f23 307 * After any system reset, this field is cleared by hardware on any successful write
mbed_official 324:406fd2029f23 308 * to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL
mbed_official 324:406fd2029f23 309 * register is used to further select the particular VLLSor LLS submode which will
mbed_official 324:406fd2029f23 310 * be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be
mbed_official 324:406fd2029f23 311 * used to select a Partial Stop mode if desired.
mbed_official 324:406fd2029f23 312 *
mbed_official 324:406fd2029f23 313 * Values:
mbed_official 324:406fd2029f23 314 * - 000 - Normal Stop (STOP)
mbed_official 324:406fd2029f23 315 * - 001 - Reserved
mbed_official 324:406fd2029f23 316 * - 010 - Very-Low-Power Stop (VLPS)
mbed_official 324:406fd2029f23 317 * - 011 - Low-Leakage Stop (LLSx)
mbed_official 324:406fd2029f23 318 * - 100 - Very-Low-Leakage Stop (VLLSx)
mbed_official 324:406fd2029f23 319 * - 101 - Reserved
mbed_official 324:406fd2029f23 320 * - 110 - Reseved
mbed_official 324:406fd2029f23 321 * - 111 - Reserved
mbed_official 324:406fd2029f23 322 */
mbed_official 324:406fd2029f23 323 /*@{*/
mbed_official 324:406fd2029f23 324 #define BP_SMC_PMCTRL_STOPM (0U) /*!< Bit position for SMC_PMCTRL_STOPM. */
mbed_official 324:406fd2029f23 325 #define BM_SMC_PMCTRL_STOPM (0x07U) /*!< Bit mask for SMC_PMCTRL_STOPM. */
mbed_official 324:406fd2029f23 326 #define BS_SMC_PMCTRL_STOPM (3U) /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
mbed_official 324:406fd2029f23 327
mbed_official 324:406fd2029f23 328 /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
mbed_official 324:406fd2029f23 329 #define BR_SMC_PMCTRL_STOPM(x) (HW_SMC_PMCTRL(x).B.STOPM)
mbed_official 324:406fd2029f23 330
mbed_official 324:406fd2029f23 331 /*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
mbed_official 324:406fd2029f23 332 #define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
mbed_official 324:406fd2029f23 333
mbed_official 324:406fd2029f23 334 /*! @brief Set the STOPM field to a new value. */
mbed_official 324:406fd2029f23 335 #define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
mbed_official 324:406fd2029f23 336 /*@}*/
mbed_official 324:406fd2029f23 337
mbed_official 324:406fd2029f23 338 /*!
mbed_official 324:406fd2029f23 339 * @name Register SMC_PMCTRL, field STOPA[3] (RO)
mbed_official 324:406fd2029f23 340 *
mbed_official 324:406fd2029f23 341 * When set, this read-only status bit indicates an interrupt occured during the
mbed_official 324:406fd2029f23 342 * previous stop mode entry sequence, preventing the system from entering that
mbed_official 324:406fd2029f23 343 * mode. This field is cleared by reset or by hardware at the beginning of any
mbed_official 324:406fd2029f23 344 * stop mode entry sequence and is set if the sequence was aborted.
mbed_official 324:406fd2029f23 345 *
mbed_official 324:406fd2029f23 346 * Values:
mbed_official 324:406fd2029f23 347 * - 0 - The previous stop mode entry was successsful.
mbed_official 324:406fd2029f23 348 * - 1 - The previous stop mode entry was aborted.
mbed_official 324:406fd2029f23 349 */
mbed_official 324:406fd2029f23 350 /*@{*/
mbed_official 324:406fd2029f23 351 #define BP_SMC_PMCTRL_STOPA (3U) /*!< Bit position for SMC_PMCTRL_STOPA. */
mbed_official 324:406fd2029f23 352 #define BM_SMC_PMCTRL_STOPA (0x08U) /*!< Bit mask for SMC_PMCTRL_STOPA. */
mbed_official 324:406fd2029f23 353 #define BS_SMC_PMCTRL_STOPA (1U) /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
mbed_official 324:406fd2029f23 354
mbed_official 324:406fd2029f23 355 /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
mbed_official 324:406fd2029f23 356 #define BR_SMC_PMCTRL_STOPA(x) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA))
mbed_official 324:406fd2029f23 357 /*@}*/
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*!
mbed_official 324:406fd2029f23 360 * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
mbed_official 324:406fd2029f23 361 *
mbed_official 324:406fd2029f23 362 * When written, causes entry into the selected run mode. Writes to this field
mbed_official 324:406fd2029f23 363 * are blocked if the protection level has not been enabled using the PMPROT
mbed_official 324:406fd2029f23 364 * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
mbed_official 324:406fd2029f23 365 * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR. RUNM may be set to
mbed_official 324:406fd2029f23 366 * HSRUN only when PMSTAT=RUN. After being programmed to HSRUN, RUNM should not
mbed_official 324:406fd2029f23 367 * be programmed back to RUN until PMSTAT=HSRUN. Also, stop mode entry should not
mbed_official 324:406fd2029f23 368 * be attempted while RUNM=HSRUN or PMSTAT=HSRUN.
mbed_official 324:406fd2029f23 369 *
mbed_official 324:406fd2029f23 370 * Values:
mbed_official 324:406fd2029f23 371 * - 00 - Normal Run mode (RUN)
mbed_official 324:406fd2029f23 372 * - 01 - Reserved
mbed_official 324:406fd2029f23 373 * - 10 - Very-Low-Power Run mode (VLPR)
mbed_official 324:406fd2029f23 374 * - 11 - High Speed Run mode (HSRUN)
mbed_official 324:406fd2029f23 375 */
mbed_official 324:406fd2029f23 376 /*@{*/
mbed_official 324:406fd2029f23 377 #define BP_SMC_PMCTRL_RUNM (5U) /*!< Bit position for SMC_PMCTRL_RUNM. */
mbed_official 324:406fd2029f23 378 #define BM_SMC_PMCTRL_RUNM (0x60U) /*!< Bit mask for SMC_PMCTRL_RUNM. */
mbed_official 324:406fd2029f23 379 #define BS_SMC_PMCTRL_RUNM (2U) /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
mbed_official 324:406fd2029f23 380
mbed_official 324:406fd2029f23 381 /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
mbed_official 324:406fd2029f23 382 #define BR_SMC_PMCTRL_RUNM(x) (HW_SMC_PMCTRL(x).B.RUNM)
mbed_official 324:406fd2029f23 383
mbed_official 324:406fd2029f23 384 /*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
mbed_official 324:406fd2029f23 385 #define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
mbed_official 324:406fd2029f23 386
mbed_official 324:406fd2029f23 387 /*! @brief Set the RUNM field to a new value. */
mbed_official 324:406fd2029f23 388 #define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
mbed_official 324:406fd2029f23 389 /*@}*/
mbed_official 324:406fd2029f23 390
mbed_official 324:406fd2029f23 391 /*******************************************************************************
mbed_official 324:406fd2029f23 392 * HW_SMC_STOPCTRL - Stop Control Register
mbed_official 324:406fd2029f23 393 ******************************************************************************/
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395 /*!
mbed_official 324:406fd2029f23 396 * @brief HW_SMC_STOPCTRL - Stop Control Register (RW)
mbed_official 324:406fd2029f23 397 *
mbed_official 324:406fd2029f23 398 * Reset value: 0x03U
mbed_official 324:406fd2029f23 399 *
mbed_official 324:406fd2029f23 400 * The STOPCTRL register provides various control bits allowing the user to fine
mbed_official 324:406fd2029f23 401 * tune power consumption during the stop mode selected by the STOPM field. This
mbed_official 324:406fd2029f23 402 * register is reset on Chip POR not VLLS and by reset types that trigger Chip
mbed_official 324:406fd2029f23 403 * POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
mbed_official 324:406fd2029f23 404 * VLLS. See the Reset section details for more information.
mbed_official 324:406fd2029f23 405 */
mbed_official 324:406fd2029f23 406 typedef union _hw_smc_stopctrl
mbed_official 324:406fd2029f23 407 {
mbed_official 324:406fd2029f23 408 uint8_t U;
mbed_official 324:406fd2029f23 409 struct _hw_smc_stopctrl_bitfields
mbed_official 324:406fd2029f23 410 {
mbed_official 324:406fd2029f23 411 uint8_t LLSM : 3; /*!< [2:0] LLS or VLLS Mode Control */
mbed_official 324:406fd2029f23 412 uint8_t RESERVED0 : 2; /*!< [4:3] */
mbed_official 324:406fd2029f23 413 uint8_t PORPO : 1; /*!< [5] POR Power Option */
mbed_official 324:406fd2029f23 414 uint8_t PSTOPO : 2; /*!< [7:6] Partial Stop Option */
mbed_official 324:406fd2029f23 415 } B;
mbed_official 324:406fd2029f23 416 } hw_smc_stopctrl_t;
mbed_official 324:406fd2029f23 417
mbed_official 324:406fd2029f23 418 /*!
mbed_official 324:406fd2029f23 419 * @name Constants and macros for entire SMC_STOPCTRL register
mbed_official 324:406fd2029f23 420 */
mbed_official 324:406fd2029f23 421 /*@{*/
mbed_official 324:406fd2029f23 422 #define HW_SMC_STOPCTRL_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 423
mbed_official 324:406fd2029f23 424 #define HW_SMC_STOPCTRL(x) (*(__IO hw_smc_stopctrl_t *) HW_SMC_STOPCTRL_ADDR(x))
mbed_official 324:406fd2029f23 425 #define HW_SMC_STOPCTRL_RD(x) (HW_SMC_STOPCTRL(x).U)
mbed_official 324:406fd2029f23 426 #define HW_SMC_STOPCTRL_WR(x, v) (HW_SMC_STOPCTRL(x).U = (v))
mbed_official 324:406fd2029f23 427 #define HW_SMC_STOPCTRL_SET(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 428 #define HW_SMC_STOPCTRL_CLR(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 429 #define HW_SMC_STOPCTRL_TOG(x, v) (HW_SMC_STOPCTRL_WR(x, HW_SMC_STOPCTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 430 /*@}*/
mbed_official 324:406fd2029f23 431
mbed_official 324:406fd2029f23 432 /*
mbed_official 324:406fd2029f23 433 * Constants & macros for individual SMC_STOPCTRL bitfields
mbed_official 324:406fd2029f23 434 */
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*!
mbed_official 324:406fd2029f23 437 * @name Register SMC_STOPCTRL, field LLSM[2:0] (RW)
mbed_official 324:406fd2029f23 438 *
mbed_official 324:406fd2029f23 439 * This field controls which LLS or VLLS sub-mode to enter if STOPM=LLSx or
mbed_official 324:406fd2029f23 440 * VLLSx.
mbed_official 324:406fd2029f23 441 *
mbed_official 324:406fd2029f23 442 * Values:
mbed_official 324:406fd2029f23 443 * - 000 - VLLS0 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
mbed_official 324:406fd2029f23 444 * - 001 - VLLS1 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
mbed_official 324:406fd2029f23 445 * - 010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
mbed_official 324:406fd2029f23 446 * - 011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
mbed_official 324:406fd2029f23 447 * - 100 - Reserved
mbed_official 324:406fd2029f23 448 * - 101 - Reserved
mbed_official 324:406fd2029f23 449 * - 110 - Reserved
mbed_official 324:406fd2029f23 450 * - 111 - Reserved
mbed_official 324:406fd2029f23 451 */
mbed_official 324:406fd2029f23 452 /*@{*/
mbed_official 324:406fd2029f23 453 #define BP_SMC_STOPCTRL_LLSM (0U) /*!< Bit position for SMC_STOPCTRL_LLSM. */
mbed_official 324:406fd2029f23 454 #define BM_SMC_STOPCTRL_LLSM (0x07U) /*!< Bit mask for SMC_STOPCTRL_LLSM. */
mbed_official 324:406fd2029f23 455 #define BS_SMC_STOPCTRL_LLSM (3U) /*!< Bit field size in bits for SMC_STOPCTRL_LLSM. */
mbed_official 324:406fd2029f23 456
mbed_official 324:406fd2029f23 457 /*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */
mbed_official 324:406fd2029f23 458 #define BR_SMC_STOPCTRL_LLSM(x) (HW_SMC_STOPCTRL(x).B.LLSM)
mbed_official 324:406fd2029f23 459
mbed_official 324:406fd2029f23 460 /*! @brief Format value for bitfield SMC_STOPCTRL_LLSM. */
mbed_official 324:406fd2029f23 461 #define BF_SMC_STOPCTRL_LLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_LLSM) & BM_SMC_STOPCTRL_LLSM)
mbed_official 324:406fd2029f23 462
mbed_official 324:406fd2029f23 463 /*! @brief Set the LLSM field to a new value. */
mbed_official 324:406fd2029f23 464 #define BW_SMC_STOPCTRL_LLSM(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_LLSM) | BF_SMC_STOPCTRL_LLSM(v)))
mbed_official 324:406fd2029f23 465 /*@}*/
mbed_official 324:406fd2029f23 466
mbed_official 324:406fd2029f23 467 /*!
mbed_official 324:406fd2029f23 468 * @name Register SMC_STOPCTRL, field PORPO[5] (RW)
mbed_official 324:406fd2029f23 469 *
mbed_official 324:406fd2029f23 470 * This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
mbed_official 324:406fd2029f23 471 *
mbed_official 324:406fd2029f23 472 * Values:
mbed_official 324:406fd2029f23 473 * - 0 - POR detect circuit is enabled in VLLS0
mbed_official 324:406fd2029f23 474 * - 1 - POR detect circuit is disabled in VLLS0
mbed_official 324:406fd2029f23 475 */
mbed_official 324:406fd2029f23 476 /*@{*/
mbed_official 324:406fd2029f23 477 #define BP_SMC_STOPCTRL_PORPO (5U) /*!< Bit position for SMC_STOPCTRL_PORPO. */
mbed_official 324:406fd2029f23 478 #define BM_SMC_STOPCTRL_PORPO (0x20U) /*!< Bit mask for SMC_STOPCTRL_PORPO. */
mbed_official 324:406fd2029f23 479 #define BS_SMC_STOPCTRL_PORPO (1U) /*!< Bit field size in bits for SMC_STOPCTRL_PORPO. */
mbed_official 324:406fd2029f23 480
mbed_official 324:406fd2029f23 481 /*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
mbed_official 324:406fd2029f23 482 #define BR_SMC_STOPCTRL_PORPO(x) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO))
mbed_official 324:406fd2029f23 483
mbed_official 324:406fd2029f23 484 /*! @brief Format value for bitfield SMC_STOPCTRL_PORPO. */
mbed_official 324:406fd2029f23 485 #define BF_SMC_STOPCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PORPO) & BM_SMC_STOPCTRL_PORPO)
mbed_official 324:406fd2029f23 486
mbed_official 324:406fd2029f23 487 /*! @brief Set the PORPO field to a new value. */
mbed_official 324:406fd2029f23 488 #define BW_SMC_STOPCTRL_PORPO(x, v) (BITBAND_ACCESS8(HW_SMC_STOPCTRL_ADDR(x), BP_SMC_STOPCTRL_PORPO) = (v))
mbed_official 324:406fd2029f23 489 /*@}*/
mbed_official 324:406fd2029f23 490
mbed_official 324:406fd2029f23 491 /*!
mbed_official 324:406fd2029f23 492 * @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
mbed_official 324:406fd2029f23 493 *
mbed_official 324:406fd2029f23 494 * These bits control whether a Partial Stop mode is entered when STOPM=STOP.
mbed_official 324:406fd2029f23 495 * When entering a Partial Stop mode from RUN mode, the PMC, MCG and flash remain
mbed_official 324:406fd2029f23 496 * fully powered, allowing the device to wakeup almost instantaneously at the
mbed_official 324:406fd2029f23 497 * expense of higher power consumption. In PSTOP2, only system clocks are gated
mbed_official 324:406fd2029f23 498 * allowing peripherals running on bus clock to remain fully functional. In PSTOP1,
mbed_official 324:406fd2029f23 499 * both system and bus clocks are gated.
mbed_official 324:406fd2029f23 500 *
mbed_official 324:406fd2029f23 501 * Values:
mbed_official 324:406fd2029f23 502 * - 00 - STOP - Normal Stop mode
mbed_official 324:406fd2029f23 503 * - 01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
mbed_official 324:406fd2029f23 504 * - 10 - PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
mbed_official 324:406fd2029f23 505 * - 11 - Reserved
mbed_official 324:406fd2029f23 506 */
mbed_official 324:406fd2029f23 507 /*@{*/
mbed_official 324:406fd2029f23 508 #define BP_SMC_STOPCTRL_PSTOPO (6U) /*!< Bit position for SMC_STOPCTRL_PSTOPO. */
mbed_official 324:406fd2029f23 509 #define BM_SMC_STOPCTRL_PSTOPO (0xC0U) /*!< Bit mask for SMC_STOPCTRL_PSTOPO. */
mbed_official 324:406fd2029f23 510 #define BS_SMC_STOPCTRL_PSTOPO (2U) /*!< Bit field size in bits for SMC_STOPCTRL_PSTOPO. */
mbed_official 324:406fd2029f23 511
mbed_official 324:406fd2029f23 512 /*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
mbed_official 324:406fd2029f23 513 #define BR_SMC_STOPCTRL_PSTOPO(x) (HW_SMC_STOPCTRL(x).B.PSTOPO)
mbed_official 324:406fd2029f23 514
mbed_official 324:406fd2029f23 515 /*! @brief Format value for bitfield SMC_STOPCTRL_PSTOPO. */
mbed_official 324:406fd2029f23 516 #define BF_SMC_STOPCTRL_PSTOPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_STOPCTRL_PSTOPO) & BM_SMC_STOPCTRL_PSTOPO)
mbed_official 324:406fd2029f23 517
mbed_official 324:406fd2029f23 518 /*! @brief Set the PSTOPO field to a new value. */
mbed_official 324:406fd2029f23 519 #define BW_SMC_STOPCTRL_PSTOPO(x, v) (HW_SMC_STOPCTRL_WR(x, (HW_SMC_STOPCTRL_RD(x) & ~BM_SMC_STOPCTRL_PSTOPO) | BF_SMC_STOPCTRL_PSTOPO(v)))
mbed_official 324:406fd2029f23 520 /*@}*/
mbed_official 324:406fd2029f23 521
mbed_official 324:406fd2029f23 522 /*******************************************************************************
mbed_official 324:406fd2029f23 523 * HW_SMC_PMSTAT - Power Mode Status register
mbed_official 324:406fd2029f23 524 ******************************************************************************/
mbed_official 324:406fd2029f23 525
mbed_official 324:406fd2029f23 526 /*!
mbed_official 324:406fd2029f23 527 * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
mbed_official 324:406fd2029f23 528 *
mbed_official 324:406fd2029f23 529 * Reset value: 0x01U
mbed_official 324:406fd2029f23 530 *
mbed_official 324:406fd2029f23 531 * PMSTAT is a read-only, one-hot register which indicates the current power
mbed_official 324:406fd2029f23 532 * mode of the system. This register is reset on Chip POR not VLLS and by reset
mbed_official 324:406fd2029f23 533 * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
mbed_official 324:406fd2029f23 534 * trigger Chip POR not VLLS. See the Reset section details for more information.
mbed_official 324:406fd2029f23 535 */
mbed_official 324:406fd2029f23 536 typedef union _hw_smc_pmstat
mbed_official 324:406fd2029f23 537 {
mbed_official 324:406fd2029f23 538 uint8_t U;
mbed_official 324:406fd2029f23 539 struct _hw_smc_pmstat_bitfields
mbed_official 324:406fd2029f23 540 {
mbed_official 324:406fd2029f23 541 uint8_t PMSTAT : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 542 } B;
mbed_official 324:406fd2029f23 543 } hw_smc_pmstat_t;
mbed_official 324:406fd2029f23 544
mbed_official 324:406fd2029f23 545 /*!
mbed_official 324:406fd2029f23 546 * @name Constants and macros for entire SMC_PMSTAT register
mbed_official 324:406fd2029f23 547 */
mbed_official 324:406fd2029f23 548 /*@{*/
mbed_official 324:406fd2029f23 549 #define HW_SMC_PMSTAT_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 #define HW_SMC_PMSTAT(x) (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
mbed_official 324:406fd2029f23 552 #define HW_SMC_PMSTAT_RD(x) (HW_SMC_PMSTAT(x).U)
mbed_official 324:406fd2029f23 553 /*@}*/
mbed_official 324:406fd2029f23 554
mbed_official 324:406fd2029f23 555 /*
mbed_official 324:406fd2029f23 556 * Constants & macros for individual SMC_PMSTAT bitfields
mbed_official 324:406fd2029f23 557 */
mbed_official 324:406fd2029f23 558
mbed_official 324:406fd2029f23 559 /*!
mbed_official 324:406fd2029f23 560 * @name Register SMC_PMSTAT, field PMSTAT[7:0] (RO)
mbed_official 324:406fd2029f23 561 *
mbed_official 324:406fd2029f23 562 * When debug is enabled, the PMSTAT will not update to STOP or VLPS When a
mbed_official 324:406fd2029f23 563 * PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS
mbed_official 324:406fd2029f23 564 */
mbed_official 324:406fd2029f23 565 /*@{*/
mbed_official 324:406fd2029f23 566 #define BP_SMC_PMSTAT_PMSTAT (0U) /*!< Bit position for SMC_PMSTAT_PMSTAT. */
mbed_official 324:406fd2029f23 567 #define BM_SMC_PMSTAT_PMSTAT (0xFFU) /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
mbed_official 324:406fd2029f23 568 #define BS_SMC_PMSTAT_PMSTAT (8U) /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
mbed_official 324:406fd2029f23 569
mbed_official 324:406fd2029f23 570 /*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
mbed_official 324:406fd2029f23 571 #define BR_SMC_PMSTAT_PMSTAT(x) (HW_SMC_PMSTAT(x).U)
mbed_official 324:406fd2029f23 572 /*@}*/
mbed_official 324:406fd2029f23 573
mbed_official 324:406fd2029f23 574 /*******************************************************************************
mbed_official 324:406fd2029f23 575 * hw_smc_t - module struct
mbed_official 324:406fd2029f23 576 ******************************************************************************/
mbed_official 324:406fd2029f23 577 /*!
mbed_official 324:406fd2029f23 578 * @brief All SMC module registers.
mbed_official 324:406fd2029f23 579 */
mbed_official 324:406fd2029f23 580 #pragma pack(1)
mbed_official 324:406fd2029f23 581 typedef struct _hw_smc
mbed_official 324:406fd2029f23 582 {
mbed_official 324:406fd2029f23 583 __IO hw_smc_pmprot_t PMPROT; /*!< [0x0] Power Mode Protection register */
mbed_official 324:406fd2029f23 584 __IO hw_smc_pmctrl_t PMCTRL; /*!< [0x1] Power Mode Control register */
mbed_official 324:406fd2029f23 585 __IO hw_smc_stopctrl_t STOPCTRL; /*!< [0x2] Stop Control Register */
mbed_official 324:406fd2029f23 586 __I hw_smc_pmstat_t PMSTAT; /*!< [0x3] Power Mode Status register */
mbed_official 324:406fd2029f23 587 } hw_smc_t;
mbed_official 324:406fd2029f23 588 #pragma pack()
mbed_official 324:406fd2029f23 589
mbed_official 324:406fd2029f23 590 /*! @brief Macro to access all SMC registers. */
mbed_official 324:406fd2029f23 591 /*! @param x SMC module instance base address. */
mbed_official 324:406fd2029f23 592 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 593 * use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
mbed_official 324:406fd2029f23 594 #define HW_SMC(x) (*(hw_smc_t *)(x))
mbed_official 324:406fd2029f23 595
mbed_official 324:406fd2029f23 596 #endif /* __HW_SMC_REGISTERS_H__ */
mbed_official 324:406fd2029f23 597 /* EOF */