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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_port.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_PORT_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_PORT_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 PORT
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Pin Control and Interrupts
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_PORT_PCRn - Pin Control Register n
mbed_official 324:406fd2029f23 90 * - HW_PORT_GPCLR - Global Pin Control Low Register
mbed_official 324:406fd2029f23 91 * - HW_PORT_GPCHR - Global Pin Control High Register
mbed_official 324:406fd2029f23 92 * - HW_PORT_ISFR - Interrupt Status Flag Register
mbed_official 324:406fd2029f23 93 * - HW_PORT_DFER - Digital Filter Enable Register
mbed_official 324:406fd2029f23 94 * - HW_PORT_DFCR - Digital Filter Clock Register
mbed_official 324:406fd2029f23 95 * - HW_PORT_DFWR - Digital Filter Width Register
mbed_official 324:406fd2029f23 96 *
mbed_official 324:406fd2029f23 97 * - hw_port_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 98 */
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
mbed_official 324:406fd2029f23 101 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
mbed_official 324:406fd2029f23 102 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
mbed_official 324:406fd2029f23 103 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
mbed_official 324:406fd2029f23 104 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
mbed_official 324:406fd2029f23 105 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
mbed_official 324:406fd2029f23 106
mbed_official 324:406fd2029f23 107 /*******************************************************************************
mbed_official 324:406fd2029f23 108 * HW_PORT_PCRn - Pin Control Register n
mbed_official 324:406fd2029f23 109 ******************************************************************************/
mbed_official 324:406fd2029f23 110
mbed_official 324:406fd2029f23 111 /*!
mbed_official 324:406fd2029f23 112 * @brief HW_PORT_PCRn - Pin Control Register n (RW)
mbed_official 324:406fd2029f23 113 *
mbed_official 324:406fd2029f23 114 * Reset value: 0x00000700U
mbed_official 324:406fd2029f23 115 *
mbed_official 324:406fd2029f23 116 * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
mbed_official 324:406fd2029f23 117 * this device. See the GPIO Configuration section for details on the available
mbed_official 324:406fd2029f23 118 * functions for each pin. Do not modify pin configuration registers associated
mbed_official 324:406fd2029f23 119 * with pins not available in your selected package. All unbonded pins not
mbed_official 324:406fd2029f23 120 * available in your package will default to DISABLE state for lowest power consumption.
mbed_official 324:406fd2029f23 121 */
mbed_official 324:406fd2029f23 122 typedef union _hw_port_pcrn
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 uint32_t U;
mbed_official 324:406fd2029f23 125 struct _hw_port_pcrn_bitfields
mbed_official 324:406fd2029f23 126 {
mbed_official 324:406fd2029f23 127 uint32_t PS : 1; /*!< [0] Pull Select */
mbed_official 324:406fd2029f23 128 uint32_t PE : 1; /*!< [1] Pull Enable */
mbed_official 324:406fd2029f23 129 uint32_t SRE : 1; /*!< [2] Slew Rate Enable */
mbed_official 324:406fd2029f23 130 uint32_t RESERVED0 : 1; /*!< [3] */
mbed_official 324:406fd2029f23 131 uint32_t PFE : 1; /*!< [4] Passive Filter Enable */
mbed_official 324:406fd2029f23 132 uint32_t ODE : 1; /*!< [5] Open Drain Enable */
mbed_official 324:406fd2029f23 133 uint32_t DSE : 1; /*!< [6] Drive Strength Enable */
mbed_official 324:406fd2029f23 134 uint32_t RESERVED1 : 1; /*!< [7] */
mbed_official 324:406fd2029f23 135 uint32_t MUX : 3; /*!< [10:8] Pin Mux Control */
mbed_official 324:406fd2029f23 136 uint32_t RESERVED2 : 4; /*!< [14:11] */
mbed_official 324:406fd2029f23 137 uint32_t LK : 1; /*!< [15] Lock Register */
mbed_official 324:406fd2029f23 138 uint32_t IRQC : 4; /*!< [19:16] Interrupt Configuration */
mbed_official 324:406fd2029f23 139 uint32_t RESERVED3 : 4; /*!< [23:20] */
mbed_official 324:406fd2029f23 140 uint32_t ISF : 1; /*!< [24] Interrupt Status Flag */
mbed_official 324:406fd2029f23 141 uint32_t RESERVED4 : 7; /*!< [31:25] */
mbed_official 324:406fd2029f23 142 } B;
mbed_official 324:406fd2029f23 143 } hw_port_pcrn_t;
mbed_official 324:406fd2029f23 144
mbed_official 324:406fd2029f23 145 /*!
mbed_official 324:406fd2029f23 146 * @name Constants and macros for entire PORT_PCRn register
mbed_official 324:406fd2029f23 147 */
mbed_official 324:406fd2029f23 148 /*@{*/
mbed_official 324:406fd2029f23 149 #define HW_PORT_PCRn_COUNT (32U)
mbed_official 324:406fd2029f23 150
mbed_official 324:406fd2029f23 151 #define HW_PORT_PCRn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
mbed_official 324:406fd2029f23 152
mbed_official 324:406fd2029f23 153 #define HW_PORT_PCRn(x, n) (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
mbed_official 324:406fd2029f23 154 #define HW_PORT_PCRn_RD(x, n) (HW_PORT_PCRn(x, n).U)
mbed_official 324:406fd2029f23 155 #define HW_PORT_PCRn_WR(x, n, v) (HW_PORT_PCRn(x, n).U = (v))
mbed_official 324:406fd2029f23 156 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 157 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 158 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 159 /*@}*/
mbed_official 324:406fd2029f23 160
mbed_official 324:406fd2029f23 161 /*
mbed_official 324:406fd2029f23 162 * Constants & macros for individual PORT_PCRn bitfields
mbed_official 324:406fd2029f23 163 */
mbed_official 324:406fd2029f23 164
mbed_official 324:406fd2029f23 165 /*!
mbed_official 324:406fd2029f23 166 * @name Register PORT_PCRn, field PS[0] (RW)
mbed_official 324:406fd2029f23 167 *
mbed_official 324:406fd2029f23 168 * Pull configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 169 *
mbed_official 324:406fd2029f23 170 * Values:
mbed_official 324:406fd2029f23 171 * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
mbed_official 324:406fd2029f23 172 * corresponding PE field is set.
mbed_official 324:406fd2029f23 173 * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
mbed_official 324:406fd2029f23 174 * corresponding PE field is set.
mbed_official 324:406fd2029f23 175 */
mbed_official 324:406fd2029f23 176 /*@{*/
mbed_official 324:406fd2029f23 177 #define BP_PORT_PCRn_PS (0U) /*!< Bit position for PORT_PCRn_PS. */
mbed_official 324:406fd2029f23 178 #define BM_PORT_PCRn_PS (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
mbed_official 324:406fd2029f23 179 #define BS_PORT_PCRn_PS (1U) /*!< Bit field size in bits for PORT_PCRn_PS. */
mbed_official 324:406fd2029f23 180
mbed_official 324:406fd2029f23 181 /*! @brief Read current value of the PORT_PCRn_PS field. */
mbed_official 324:406fd2029f23 182 #define BR_PORT_PCRn_PS(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS))
mbed_official 324:406fd2029f23 183
mbed_official 324:406fd2029f23 184 /*! @brief Format value for bitfield PORT_PCRn_PS. */
mbed_official 324:406fd2029f23 185 #define BF_PORT_PCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
mbed_official 324:406fd2029f23 186
mbed_official 324:406fd2029f23 187 /*! @brief Set the PS field to a new value. */
mbed_official 324:406fd2029f23 188 #define BW_PORT_PCRn_PS(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS) = (v))
mbed_official 324:406fd2029f23 189 /*@}*/
mbed_official 324:406fd2029f23 190
mbed_official 324:406fd2029f23 191 /*!
mbed_official 324:406fd2029f23 192 * @name Register PORT_PCRn, field PE[1] (RW)
mbed_official 324:406fd2029f23 193 *
mbed_official 324:406fd2029f23 194 * Pull configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 195 *
mbed_official 324:406fd2029f23 196 * Values:
mbed_official 324:406fd2029f23 197 * - 0 - Internal pullup or pulldown resistor is not enabled on the
mbed_official 324:406fd2029f23 198 * corresponding pin.
mbed_official 324:406fd2029f23 199 * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
mbed_official 324:406fd2029f23 200 * pin, if the pin is configured as a digital input.
mbed_official 324:406fd2029f23 201 */
mbed_official 324:406fd2029f23 202 /*@{*/
mbed_official 324:406fd2029f23 203 #define BP_PORT_PCRn_PE (1U) /*!< Bit position for PORT_PCRn_PE. */
mbed_official 324:406fd2029f23 204 #define BM_PORT_PCRn_PE (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
mbed_official 324:406fd2029f23 205 #define BS_PORT_PCRn_PE (1U) /*!< Bit field size in bits for PORT_PCRn_PE. */
mbed_official 324:406fd2029f23 206
mbed_official 324:406fd2029f23 207 /*! @brief Read current value of the PORT_PCRn_PE field. */
mbed_official 324:406fd2029f23 208 #define BR_PORT_PCRn_PE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE))
mbed_official 324:406fd2029f23 209
mbed_official 324:406fd2029f23 210 /*! @brief Format value for bitfield PORT_PCRn_PE. */
mbed_official 324:406fd2029f23 211 #define BF_PORT_PCRn_PE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
mbed_official 324:406fd2029f23 212
mbed_official 324:406fd2029f23 213 /*! @brief Set the PE field to a new value. */
mbed_official 324:406fd2029f23 214 #define BW_PORT_PCRn_PE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE) = (v))
mbed_official 324:406fd2029f23 215 /*@}*/
mbed_official 324:406fd2029f23 216
mbed_official 324:406fd2029f23 217 /*!
mbed_official 324:406fd2029f23 218 * @name Register PORT_PCRn, field SRE[2] (RW)
mbed_official 324:406fd2029f23 219 *
mbed_official 324:406fd2029f23 220 * Slew rate configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 221 *
mbed_official 324:406fd2029f23 222 * Values:
mbed_official 324:406fd2029f23 223 * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
mbed_official 324:406fd2029f23 224 * configured as a digital output.
mbed_official 324:406fd2029f23 225 * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
mbed_official 324:406fd2029f23 226 * configured as a digital output.
mbed_official 324:406fd2029f23 227 */
mbed_official 324:406fd2029f23 228 /*@{*/
mbed_official 324:406fd2029f23 229 #define BP_PORT_PCRn_SRE (2U) /*!< Bit position for PORT_PCRn_SRE. */
mbed_official 324:406fd2029f23 230 #define BM_PORT_PCRn_SRE (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
mbed_official 324:406fd2029f23 231 #define BS_PORT_PCRn_SRE (1U) /*!< Bit field size in bits for PORT_PCRn_SRE. */
mbed_official 324:406fd2029f23 232
mbed_official 324:406fd2029f23 233 /*! @brief Read current value of the PORT_PCRn_SRE field. */
mbed_official 324:406fd2029f23 234 #define BR_PORT_PCRn_SRE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE))
mbed_official 324:406fd2029f23 235
mbed_official 324:406fd2029f23 236 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
mbed_official 324:406fd2029f23 237 #define BF_PORT_PCRn_SRE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*! @brief Set the SRE field to a new value. */
mbed_official 324:406fd2029f23 240 #define BW_PORT_PCRn_SRE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE) = (v))
mbed_official 324:406fd2029f23 241 /*@}*/
mbed_official 324:406fd2029f23 242
mbed_official 324:406fd2029f23 243 /*!
mbed_official 324:406fd2029f23 244 * @name Register PORT_PCRn, field PFE[4] (RW)
mbed_official 324:406fd2029f23 245 *
mbed_official 324:406fd2029f23 246 * Passive filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 247 *
mbed_official 324:406fd2029f23 248 * Values:
mbed_official 324:406fd2029f23 249 * - 0 - Passive input filter is disabled on the corresponding pin.
mbed_official 324:406fd2029f23 250 * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
mbed_official 324:406fd2029f23 251 * configured as a digital input. Refer to the device data sheet for filter
mbed_official 324:406fd2029f23 252 * characteristics.
mbed_official 324:406fd2029f23 253 */
mbed_official 324:406fd2029f23 254 /*@{*/
mbed_official 324:406fd2029f23 255 #define BP_PORT_PCRn_PFE (4U) /*!< Bit position for PORT_PCRn_PFE. */
mbed_official 324:406fd2029f23 256 #define BM_PORT_PCRn_PFE (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
mbed_official 324:406fd2029f23 257 #define BS_PORT_PCRn_PFE (1U) /*!< Bit field size in bits for PORT_PCRn_PFE. */
mbed_official 324:406fd2029f23 258
mbed_official 324:406fd2029f23 259 /*! @brief Read current value of the PORT_PCRn_PFE field. */
mbed_official 324:406fd2029f23 260 #define BR_PORT_PCRn_PFE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE))
mbed_official 324:406fd2029f23 261
mbed_official 324:406fd2029f23 262 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
mbed_official 324:406fd2029f23 263 #define BF_PORT_PCRn_PFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*! @brief Set the PFE field to a new value. */
mbed_official 324:406fd2029f23 266 #define BW_PORT_PCRn_PFE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE) = (v))
mbed_official 324:406fd2029f23 267 /*@}*/
mbed_official 324:406fd2029f23 268
mbed_official 324:406fd2029f23 269 /*!
mbed_official 324:406fd2029f23 270 * @name Register PORT_PCRn, field ODE[5] (RW)
mbed_official 324:406fd2029f23 271 *
mbed_official 324:406fd2029f23 272 * Open drain configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 273 *
mbed_official 324:406fd2029f23 274 * Values:
mbed_official 324:406fd2029f23 275 * - 0 - Open drain output is disabled on the corresponding pin.
mbed_official 324:406fd2029f23 276 * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
mbed_official 324:406fd2029f23 277 * configured as a digital output.
mbed_official 324:406fd2029f23 278 */
mbed_official 324:406fd2029f23 279 /*@{*/
mbed_official 324:406fd2029f23 280 #define BP_PORT_PCRn_ODE (5U) /*!< Bit position for PORT_PCRn_ODE. */
mbed_official 324:406fd2029f23 281 #define BM_PORT_PCRn_ODE (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
mbed_official 324:406fd2029f23 282 #define BS_PORT_PCRn_ODE (1U) /*!< Bit field size in bits for PORT_PCRn_ODE. */
mbed_official 324:406fd2029f23 283
mbed_official 324:406fd2029f23 284 /*! @brief Read current value of the PORT_PCRn_ODE field. */
mbed_official 324:406fd2029f23 285 #define BR_PORT_PCRn_ODE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE))
mbed_official 324:406fd2029f23 286
mbed_official 324:406fd2029f23 287 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
mbed_official 324:406fd2029f23 288 #define BF_PORT_PCRn_ODE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
mbed_official 324:406fd2029f23 289
mbed_official 324:406fd2029f23 290 /*! @brief Set the ODE field to a new value. */
mbed_official 324:406fd2029f23 291 #define BW_PORT_PCRn_ODE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE) = (v))
mbed_official 324:406fd2029f23 292 /*@}*/
mbed_official 324:406fd2029f23 293
mbed_official 324:406fd2029f23 294 /*!
mbed_official 324:406fd2029f23 295 * @name Register PORT_PCRn, field DSE[6] (RW)
mbed_official 324:406fd2029f23 296 *
mbed_official 324:406fd2029f23 297 * Drive strength configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 298 *
mbed_official 324:406fd2029f23 299 * Values:
mbed_official 324:406fd2029f23 300 * - 0 - Low drive strength is configured on the corresponding pin, if pin is
mbed_official 324:406fd2029f23 301 * configured as a digital output.
mbed_official 324:406fd2029f23 302 * - 1 - High drive strength is configured on the corresponding pin, if pin is
mbed_official 324:406fd2029f23 303 * configured as a digital output.
mbed_official 324:406fd2029f23 304 */
mbed_official 324:406fd2029f23 305 /*@{*/
mbed_official 324:406fd2029f23 306 #define BP_PORT_PCRn_DSE (6U) /*!< Bit position for PORT_PCRn_DSE. */
mbed_official 324:406fd2029f23 307 #define BM_PORT_PCRn_DSE (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
mbed_official 324:406fd2029f23 308 #define BS_PORT_PCRn_DSE (1U) /*!< Bit field size in bits for PORT_PCRn_DSE. */
mbed_official 324:406fd2029f23 309
mbed_official 324:406fd2029f23 310 /*! @brief Read current value of the PORT_PCRn_DSE field. */
mbed_official 324:406fd2029f23 311 #define BR_PORT_PCRn_DSE(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE))
mbed_official 324:406fd2029f23 312
mbed_official 324:406fd2029f23 313 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
mbed_official 324:406fd2029f23 314 #define BF_PORT_PCRn_DSE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 /*! @brief Set the DSE field to a new value. */
mbed_official 324:406fd2029f23 317 #define BW_PORT_PCRn_DSE(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE) = (v))
mbed_official 324:406fd2029f23 318 /*@}*/
mbed_official 324:406fd2029f23 319
mbed_official 324:406fd2029f23 320 /*!
mbed_official 324:406fd2029f23 321 * @name Register PORT_PCRn, field MUX[10:8] (RW)
mbed_official 324:406fd2029f23 322 *
mbed_official 324:406fd2029f23 323 * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
mbed_official 324:406fd2029f23 324 * reserved and may result in configuring the pin for a different pin muxing
mbed_official 324:406fd2029f23 325 * slot. The corresponding pin is configured in the following pin muxing slot as
mbed_official 324:406fd2029f23 326 * follows:
mbed_official 324:406fd2029f23 327 *
mbed_official 324:406fd2029f23 328 * Values:
mbed_official 324:406fd2029f23 329 * - 000 - Pin disabled (analog).
mbed_official 324:406fd2029f23 330 * - 001 - Alternative 1 (GPIO).
mbed_official 324:406fd2029f23 331 * - 010 - Alternative 2 (chip-specific).
mbed_official 324:406fd2029f23 332 * - 011 - Alternative 3 (chip-specific).
mbed_official 324:406fd2029f23 333 * - 100 - Alternative 4 (chip-specific).
mbed_official 324:406fd2029f23 334 * - 101 - Alternative 5 (chip-specific).
mbed_official 324:406fd2029f23 335 * - 110 - Alternative 6 (chip-specific).
mbed_official 324:406fd2029f23 336 * - 111 - Alternative 7 (chip-specific).
mbed_official 324:406fd2029f23 337 */
mbed_official 324:406fd2029f23 338 /*@{*/
mbed_official 324:406fd2029f23 339 #define BP_PORT_PCRn_MUX (8U) /*!< Bit position for PORT_PCRn_MUX. */
mbed_official 324:406fd2029f23 340 #define BM_PORT_PCRn_MUX (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
mbed_official 324:406fd2029f23 341 #define BS_PORT_PCRn_MUX (3U) /*!< Bit field size in bits for PORT_PCRn_MUX. */
mbed_official 324:406fd2029f23 342
mbed_official 324:406fd2029f23 343 /*! @brief Read current value of the PORT_PCRn_MUX field. */
mbed_official 324:406fd2029f23 344 #define BR_PORT_PCRn_MUX(x, n) (HW_PORT_PCRn(x, n).B.MUX)
mbed_official 324:406fd2029f23 345
mbed_official 324:406fd2029f23 346 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
mbed_official 324:406fd2029f23 347 #define BF_PORT_PCRn_MUX(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
mbed_official 324:406fd2029f23 348
mbed_official 324:406fd2029f23 349 /*! @brief Set the MUX field to a new value. */
mbed_official 324:406fd2029f23 350 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
mbed_official 324:406fd2029f23 351 /*@}*/
mbed_official 324:406fd2029f23 352
mbed_official 324:406fd2029f23 353 /*!
mbed_official 324:406fd2029f23 354 * @name Register PORT_PCRn, field LK[15] (RW)
mbed_official 324:406fd2029f23 355 *
mbed_official 324:406fd2029f23 356 * Values:
mbed_official 324:406fd2029f23 357 * - 0 - Pin Control Register fields [15:0] are not locked.
mbed_official 324:406fd2029f23 358 * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
mbed_official 324:406fd2029f23 359 * until the next system reset.
mbed_official 324:406fd2029f23 360 */
mbed_official 324:406fd2029f23 361 /*@{*/
mbed_official 324:406fd2029f23 362 #define BP_PORT_PCRn_LK (15U) /*!< Bit position for PORT_PCRn_LK. */
mbed_official 324:406fd2029f23 363 #define BM_PORT_PCRn_LK (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
mbed_official 324:406fd2029f23 364 #define BS_PORT_PCRn_LK (1U) /*!< Bit field size in bits for PORT_PCRn_LK. */
mbed_official 324:406fd2029f23 365
mbed_official 324:406fd2029f23 366 /*! @brief Read current value of the PORT_PCRn_LK field. */
mbed_official 324:406fd2029f23 367 #define BR_PORT_PCRn_LK(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK))
mbed_official 324:406fd2029f23 368
mbed_official 324:406fd2029f23 369 /*! @brief Format value for bitfield PORT_PCRn_LK. */
mbed_official 324:406fd2029f23 370 #define BF_PORT_PCRn_LK(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
mbed_official 324:406fd2029f23 371
mbed_official 324:406fd2029f23 372 /*! @brief Set the LK field to a new value. */
mbed_official 324:406fd2029f23 373 #define BW_PORT_PCRn_LK(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK) = (v))
mbed_official 324:406fd2029f23 374 /*@}*/
mbed_official 324:406fd2029f23 375
mbed_official 324:406fd2029f23 376 /*!
mbed_official 324:406fd2029f23 377 * @name Register PORT_PCRn, field IRQC[19:16] (RW)
mbed_official 324:406fd2029f23 378 *
mbed_official 324:406fd2029f23 379 * The pin interrupt configuration is valid in all digital pin muxing modes. The
mbed_official 324:406fd2029f23 380 * corresponding pin is configured to generate interrupt/DMA request as follows:
mbed_official 324:406fd2029f23 381 *
mbed_official 324:406fd2029f23 382 * Values:
mbed_official 324:406fd2029f23 383 * - 0000 - Interrupt/DMA request disabled.
mbed_official 324:406fd2029f23 384 * - 0001 - DMA request on rising edge.
mbed_official 324:406fd2029f23 385 * - 0010 - DMA request on falling edge.
mbed_official 324:406fd2029f23 386 * - 0011 - DMA request on either edge.
mbed_official 324:406fd2029f23 387 * - 1000 - Interrupt when logic 0.
mbed_official 324:406fd2029f23 388 * - 1001 - Interrupt on rising-edge.
mbed_official 324:406fd2029f23 389 * - 1010 - Interrupt on falling-edge.
mbed_official 324:406fd2029f23 390 * - 1011 - Interrupt on either edge.
mbed_official 324:406fd2029f23 391 * - 1100 - Interrupt when logic 1.
mbed_official 324:406fd2029f23 392 */
mbed_official 324:406fd2029f23 393 /*@{*/
mbed_official 324:406fd2029f23 394 #define BP_PORT_PCRn_IRQC (16U) /*!< Bit position for PORT_PCRn_IRQC. */
mbed_official 324:406fd2029f23 395 #define BM_PORT_PCRn_IRQC (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
mbed_official 324:406fd2029f23 396 #define BS_PORT_PCRn_IRQC (4U) /*!< Bit field size in bits for PORT_PCRn_IRQC. */
mbed_official 324:406fd2029f23 397
mbed_official 324:406fd2029f23 398 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
mbed_official 324:406fd2029f23 399 #define BR_PORT_PCRn_IRQC(x, n) (HW_PORT_PCRn(x, n).B.IRQC)
mbed_official 324:406fd2029f23 400
mbed_official 324:406fd2029f23 401 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
mbed_official 324:406fd2029f23 402 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
mbed_official 324:406fd2029f23 403
mbed_official 324:406fd2029f23 404 /*! @brief Set the IRQC field to a new value. */
mbed_official 324:406fd2029f23 405 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
mbed_official 324:406fd2029f23 406 /*@}*/
mbed_official 324:406fd2029f23 407
mbed_official 324:406fd2029f23 408 /*!
mbed_official 324:406fd2029f23 409 * @name Register PORT_PCRn, field ISF[24] (W1C)
mbed_official 324:406fd2029f23 410 *
mbed_official 324:406fd2029f23 411 * The pin interrupt configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 412 *
mbed_official 324:406fd2029f23 413 * Values:
mbed_official 324:406fd2029f23 414 * - 0 - Configured interrupt is not detected.
mbed_official 324:406fd2029f23 415 * - 1 - Configured interrupt is detected. If the pin is configured to generate
mbed_official 324:406fd2029f23 416 * a DMA request, then the corresponding flag will be cleared automatically
mbed_official 324:406fd2029f23 417 * at the completion of the requested DMA transfer. Otherwise, the flag
mbed_official 324:406fd2029f23 418 * remains set until a logic 1 is written to the flag. If the pin is configured for
mbed_official 324:406fd2029f23 419 * a level sensitive interrupt and the pin remains asserted, then the flag
mbed_official 324:406fd2029f23 420 * is set again immediately after it is cleared.
mbed_official 324:406fd2029f23 421 */
mbed_official 324:406fd2029f23 422 /*@{*/
mbed_official 324:406fd2029f23 423 #define BP_PORT_PCRn_ISF (24U) /*!< Bit position for PORT_PCRn_ISF. */
mbed_official 324:406fd2029f23 424 #define BM_PORT_PCRn_ISF (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
mbed_official 324:406fd2029f23 425 #define BS_PORT_PCRn_ISF (1U) /*!< Bit field size in bits for PORT_PCRn_ISF. */
mbed_official 324:406fd2029f23 426
mbed_official 324:406fd2029f23 427 /*! @brief Read current value of the PORT_PCRn_ISF field. */
mbed_official 324:406fd2029f23 428 #define BR_PORT_PCRn_ISF(x, n) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF))
mbed_official 324:406fd2029f23 429
mbed_official 324:406fd2029f23 430 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
mbed_official 324:406fd2029f23 431 #define BF_PORT_PCRn_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Set the ISF field to a new value. */
mbed_official 324:406fd2029f23 434 #define BW_PORT_PCRn_ISF(x, n, v) (BITBAND_ACCESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF) = (v))
mbed_official 324:406fd2029f23 435 /*@}*/
mbed_official 324:406fd2029f23 436
mbed_official 324:406fd2029f23 437 /*******************************************************************************
mbed_official 324:406fd2029f23 438 * HW_PORT_GPCLR - Global Pin Control Low Register
mbed_official 324:406fd2029f23 439 ******************************************************************************/
mbed_official 324:406fd2029f23 440
mbed_official 324:406fd2029f23 441 /*!
mbed_official 324:406fd2029f23 442 * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
mbed_official 324:406fd2029f23 443 *
mbed_official 324:406fd2029f23 444 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 445 *
mbed_official 324:406fd2029f23 446 * Only 32-bit writes are supported to this register.
mbed_official 324:406fd2029f23 447 */
mbed_official 324:406fd2029f23 448 typedef union _hw_port_gpclr
mbed_official 324:406fd2029f23 449 {
mbed_official 324:406fd2029f23 450 uint32_t U;
mbed_official 324:406fd2029f23 451 struct _hw_port_gpclr_bitfields
mbed_official 324:406fd2029f23 452 {
mbed_official 324:406fd2029f23 453 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
mbed_official 324:406fd2029f23 454 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
mbed_official 324:406fd2029f23 455 } B;
mbed_official 324:406fd2029f23 456 } hw_port_gpclr_t;
mbed_official 324:406fd2029f23 457
mbed_official 324:406fd2029f23 458 /*!
mbed_official 324:406fd2029f23 459 * @name Constants and macros for entire PORT_GPCLR register
mbed_official 324:406fd2029f23 460 */
mbed_official 324:406fd2029f23 461 /*@{*/
mbed_official 324:406fd2029f23 462 #define HW_PORT_GPCLR_ADDR(x) ((x) + 0x80U)
mbed_official 324:406fd2029f23 463
mbed_official 324:406fd2029f23 464 #define HW_PORT_GPCLR(x) (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
mbed_official 324:406fd2029f23 465 #define HW_PORT_GPCLR_RD(x) (HW_PORT_GPCLR(x).U)
mbed_official 324:406fd2029f23 466 #define HW_PORT_GPCLR_WR(x, v) (HW_PORT_GPCLR(x).U = (v))
mbed_official 324:406fd2029f23 467 /*@}*/
mbed_official 324:406fd2029f23 468
mbed_official 324:406fd2029f23 469 /*
mbed_official 324:406fd2029f23 470 * Constants & macros for individual PORT_GPCLR bitfields
mbed_official 324:406fd2029f23 471 */
mbed_official 324:406fd2029f23 472
mbed_official 324:406fd2029f23 473 /*!
mbed_official 324:406fd2029f23 474 * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
mbed_official 324:406fd2029f23 475 *
mbed_official 324:406fd2029f23 476 * Write value that is written to all Pin Control Registers bits [15:0] that are
mbed_official 324:406fd2029f23 477 * selected by GPWE.
mbed_official 324:406fd2029f23 478 */
mbed_official 324:406fd2029f23 479 /*@{*/
mbed_official 324:406fd2029f23 480 #define BP_PORT_GPCLR_GPWD (0U) /*!< Bit position for PORT_GPCLR_GPWD. */
mbed_official 324:406fd2029f23 481 #define BM_PORT_GPCLR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
mbed_official 324:406fd2029f23 482 #define BS_PORT_GPCLR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
mbed_official 324:406fd2029f23 483
mbed_official 324:406fd2029f23 484 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
mbed_official 324:406fd2029f23 485 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
mbed_official 324:406fd2029f23 486
mbed_official 324:406fd2029f23 487 /*! @brief Set the GPWD field to a new value. */
mbed_official 324:406fd2029f23 488 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
mbed_official 324:406fd2029f23 489 /*@}*/
mbed_official 324:406fd2029f23 490
mbed_official 324:406fd2029f23 491 /*!
mbed_official 324:406fd2029f23 492 * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
mbed_official 324:406fd2029f23 493 *
mbed_official 324:406fd2029f23 494 * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
mbed_official 324:406fd2029f23 495 * the value in GPWD. If a selected Pin Control Register is locked then the write
mbed_official 324:406fd2029f23 496 * to that register is ignored.
mbed_official 324:406fd2029f23 497 *
mbed_official 324:406fd2029f23 498 * Values:
mbed_official 324:406fd2029f23 499 * - 0 - Corresponding Pin Control Register is not updated with the value in
mbed_official 324:406fd2029f23 500 * GPWD.
mbed_official 324:406fd2029f23 501 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
mbed_official 324:406fd2029f23 502 */
mbed_official 324:406fd2029f23 503 /*@{*/
mbed_official 324:406fd2029f23 504 #define BP_PORT_GPCLR_GPWE (16U) /*!< Bit position for PORT_GPCLR_GPWE. */
mbed_official 324:406fd2029f23 505 #define BM_PORT_GPCLR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
mbed_official 324:406fd2029f23 506 #define BS_PORT_GPCLR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
mbed_official 324:406fd2029f23 507
mbed_official 324:406fd2029f23 508 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
mbed_official 324:406fd2029f23 509 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
mbed_official 324:406fd2029f23 510
mbed_official 324:406fd2029f23 511 /*! @brief Set the GPWE field to a new value. */
mbed_official 324:406fd2029f23 512 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
mbed_official 324:406fd2029f23 513 /*@}*/
mbed_official 324:406fd2029f23 514
mbed_official 324:406fd2029f23 515 /*******************************************************************************
mbed_official 324:406fd2029f23 516 * HW_PORT_GPCHR - Global Pin Control High Register
mbed_official 324:406fd2029f23 517 ******************************************************************************/
mbed_official 324:406fd2029f23 518
mbed_official 324:406fd2029f23 519 /*!
mbed_official 324:406fd2029f23 520 * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
mbed_official 324:406fd2029f23 521 *
mbed_official 324:406fd2029f23 522 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 523 *
mbed_official 324:406fd2029f23 524 * Only 32-bit writes are supported to this register.
mbed_official 324:406fd2029f23 525 */
mbed_official 324:406fd2029f23 526 typedef union _hw_port_gpchr
mbed_official 324:406fd2029f23 527 {
mbed_official 324:406fd2029f23 528 uint32_t U;
mbed_official 324:406fd2029f23 529 struct _hw_port_gpchr_bitfields
mbed_official 324:406fd2029f23 530 {
mbed_official 324:406fd2029f23 531 uint32_t GPWD : 16; /*!< [15:0] Global Pin Write Data */
mbed_official 324:406fd2029f23 532 uint32_t GPWE : 16; /*!< [31:16] Global Pin Write Enable */
mbed_official 324:406fd2029f23 533 } B;
mbed_official 324:406fd2029f23 534 } hw_port_gpchr_t;
mbed_official 324:406fd2029f23 535
mbed_official 324:406fd2029f23 536 /*!
mbed_official 324:406fd2029f23 537 * @name Constants and macros for entire PORT_GPCHR register
mbed_official 324:406fd2029f23 538 */
mbed_official 324:406fd2029f23 539 /*@{*/
mbed_official 324:406fd2029f23 540 #define HW_PORT_GPCHR_ADDR(x) ((x) + 0x84U)
mbed_official 324:406fd2029f23 541
mbed_official 324:406fd2029f23 542 #define HW_PORT_GPCHR(x) (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
mbed_official 324:406fd2029f23 543 #define HW_PORT_GPCHR_RD(x) (HW_PORT_GPCHR(x).U)
mbed_official 324:406fd2029f23 544 #define HW_PORT_GPCHR_WR(x, v) (HW_PORT_GPCHR(x).U = (v))
mbed_official 324:406fd2029f23 545 /*@}*/
mbed_official 324:406fd2029f23 546
mbed_official 324:406fd2029f23 547 /*
mbed_official 324:406fd2029f23 548 * Constants & macros for individual PORT_GPCHR bitfields
mbed_official 324:406fd2029f23 549 */
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 /*!
mbed_official 324:406fd2029f23 552 * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
mbed_official 324:406fd2029f23 553 *
mbed_official 324:406fd2029f23 554 * Write value that is written to all Pin Control Registers bits [15:0] that are
mbed_official 324:406fd2029f23 555 * selected by GPWE.
mbed_official 324:406fd2029f23 556 */
mbed_official 324:406fd2029f23 557 /*@{*/
mbed_official 324:406fd2029f23 558 #define BP_PORT_GPCHR_GPWD (0U) /*!< Bit position for PORT_GPCHR_GPWD. */
mbed_official 324:406fd2029f23 559 #define BM_PORT_GPCHR_GPWD (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
mbed_official 324:406fd2029f23 560 #define BS_PORT_GPCHR_GPWD (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
mbed_official 324:406fd2029f23 561
mbed_official 324:406fd2029f23 562 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
mbed_official 324:406fd2029f23 563 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
mbed_official 324:406fd2029f23 564
mbed_official 324:406fd2029f23 565 /*! @brief Set the GPWD field to a new value. */
mbed_official 324:406fd2029f23 566 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
mbed_official 324:406fd2029f23 567 /*@}*/
mbed_official 324:406fd2029f23 568
mbed_official 324:406fd2029f23 569 /*!
mbed_official 324:406fd2029f23 570 * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
mbed_official 324:406fd2029f23 571 *
mbed_official 324:406fd2029f23 572 * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
mbed_official 324:406fd2029f23 573 * the value in GPWD. If a selected Pin Control Register is locked then the write
mbed_official 324:406fd2029f23 574 * to that register is ignored.
mbed_official 324:406fd2029f23 575 *
mbed_official 324:406fd2029f23 576 * Values:
mbed_official 324:406fd2029f23 577 * - 0 - Corresponding Pin Control Register is not updated with the value in
mbed_official 324:406fd2029f23 578 * GPWD.
mbed_official 324:406fd2029f23 579 * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
mbed_official 324:406fd2029f23 580 */
mbed_official 324:406fd2029f23 581 /*@{*/
mbed_official 324:406fd2029f23 582 #define BP_PORT_GPCHR_GPWE (16U) /*!< Bit position for PORT_GPCHR_GPWE. */
mbed_official 324:406fd2029f23 583 #define BM_PORT_GPCHR_GPWE (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
mbed_official 324:406fd2029f23 584 #define BS_PORT_GPCHR_GPWE (16U) /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
mbed_official 324:406fd2029f23 585
mbed_official 324:406fd2029f23 586 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
mbed_official 324:406fd2029f23 587 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
mbed_official 324:406fd2029f23 588
mbed_official 324:406fd2029f23 589 /*! @brief Set the GPWE field to a new value. */
mbed_official 324:406fd2029f23 590 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
mbed_official 324:406fd2029f23 591 /*@}*/
mbed_official 324:406fd2029f23 592
mbed_official 324:406fd2029f23 593 /*******************************************************************************
mbed_official 324:406fd2029f23 594 * HW_PORT_ISFR - Interrupt Status Flag Register
mbed_official 324:406fd2029f23 595 ******************************************************************************/
mbed_official 324:406fd2029f23 596
mbed_official 324:406fd2029f23 597 /*!
mbed_official 324:406fd2029f23 598 * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
mbed_official 324:406fd2029f23 599 *
mbed_official 324:406fd2029f23 600 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 601 *
mbed_official 324:406fd2029f23 602 * The pin interrupt configuration is valid in all digital pin muxing modes. The
mbed_official 324:406fd2029f23 603 * Interrupt Status Flag for each pin is also visible in the corresponding Pin
mbed_official 324:406fd2029f23 604 * Control Register, and each flag can be cleared in either location.
mbed_official 324:406fd2029f23 605 */
mbed_official 324:406fd2029f23 606 typedef union _hw_port_isfr
mbed_official 324:406fd2029f23 607 {
mbed_official 324:406fd2029f23 608 uint32_t U;
mbed_official 324:406fd2029f23 609 struct _hw_port_isfr_bitfields
mbed_official 324:406fd2029f23 610 {
mbed_official 324:406fd2029f23 611 uint32_t ISF : 32; /*!< [31:0] Interrupt Status Flag */
mbed_official 324:406fd2029f23 612 } B;
mbed_official 324:406fd2029f23 613 } hw_port_isfr_t;
mbed_official 324:406fd2029f23 614
mbed_official 324:406fd2029f23 615 /*!
mbed_official 324:406fd2029f23 616 * @name Constants and macros for entire PORT_ISFR register
mbed_official 324:406fd2029f23 617 */
mbed_official 324:406fd2029f23 618 /*@{*/
mbed_official 324:406fd2029f23 619 #define HW_PORT_ISFR_ADDR(x) ((x) + 0xA0U)
mbed_official 324:406fd2029f23 620
mbed_official 324:406fd2029f23 621 #define HW_PORT_ISFR(x) (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
mbed_official 324:406fd2029f23 622 #define HW_PORT_ISFR_RD(x) (HW_PORT_ISFR(x).U)
mbed_official 324:406fd2029f23 623 #define HW_PORT_ISFR_WR(x, v) (HW_PORT_ISFR(x).U = (v))
mbed_official 324:406fd2029f23 624 #define HW_PORT_ISFR_SET(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) | (v)))
mbed_official 324:406fd2029f23 625 #define HW_PORT_ISFR_CLR(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 626 #define HW_PORT_ISFR_TOG(x, v) (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 627 /*@}*/
mbed_official 324:406fd2029f23 628
mbed_official 324:406fd2029f23 629 /*
mbed_official 324:406fd2029f23 630 * Constants & macros for individual PORT_ISFR bitfields
mbed_official 324:406fd2029f23 631 */
mbed_official 324:406fd2029f23 632
mbed_official 324:406fd2029f23 633 /*!
mbed_official 324:406fd2029f23 634 * @name Register PORT_ISFR, field ISF[31:0] (W1C)
mbed_official 324:406fd2029f23 635 *
mbed_official 324:406fd2029f23 636 * Each bit in the field indicates the detection of the configured interrupt of
mbed_official 324:406fd2029f23 637 * the same number as the field.
mbed_official 324:406fd2029f23 638 *
mbed_official 324:406fd2029f23 639 * Values:
mbed_official 324:406fd2029f23 640 * - 0 - Configured interrupt is not detected.
mbed_official 324:406fd2029f23 641 * - 1 - Configured interrupt is detected. If the pin is configured to generate
mbed_official 324:406fd2029f23 642 * a DMA request, then the corresponding flag will be cleared automatically
mbed_official 324:406fd2029f23 643 * at the completion of the requested DMA transfer. Otherwise, the flag
mbed_official 324:406fd2029f23 644 * remains set until a logic 1 is written to the flag. If the pin is configured for
mbed_official 324:406fd2029f23 645 * a level sensitive interrupt and the pin remains asserted, then the flag
mbed_official 324:406fd2029f23 646 * is set again immediately after it is cleared.
mbed_official 324:406fd2029f23 647 */
mbed_official 324:406fd2029f23 648 /*@{*/
mbed_official 324:406fd2029f23 649 #define BP_PORT_ISFR_ISF (0U) /*!< Bit position for PORT_ISFR_ISF. */
mbed_official 324:406fd2029f23 650 #define BM_PORT_ISFR_ISF (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
mbed_official 324:406fd2029f23 651 #define BS_PORT_ISFR_ISF (32U) /*!< Bit field size in bits for PORT_ISFR_ISF. */
mbed_official 324:406fd2029f23 652
mbed_official 324:406fd2029f23 653 /*! @brief Read current value of the PORT_ISFR_ISF field. */
mbed_official 324:406fd2029f23 654 #define BR_PORT_ISFR_ISF(x) (HW_PORT_ISFR(x).U)
mbed_official 324:406fd2029f23 655
mbed_official 324:406fd2029f23 656 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
mbed_official 324:406fd2029f23 657 #define BF_PORT_ISFR_ISF(v) ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
mbed_official 324:406fd2029f23 658
mbed_official 324:406fd2029f23 659 /*! @brief Set the ISF field to a new value. */
mbed_official 324:406fd2029f23 660 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
mbed_official 324:406fd2029f23 661 /*@}*/
mbed_official 324:406fd2029f23 662
mbed_official 324:406fd2029f23 663 /*******************************************************************************
mbed_official 324:406fd2029f23 664 * HW_PORT_DFER - Digital Filter Enable Register
mbed_official 324:406fd2029f23 665 ******************************************************************************/
mbed_official 324:406fd2029f23 666
mbed_official 324:406fd2029f23 667 /*!
mbed_official 324:406fd2029f23 668 * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
mbed_official 324:406fd2029f23 669 *
mbed_official 324:406fd2029f23 670 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 671 *
mbed_official 324:406fd2029f23 672 * The corresponding bit is read only for pins that do not support a digital
mbed_official 324:406fd2029f23 673 * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
mbed_official 324:406fd2029f23 674 * the pins that support digital filter. The digital filter configuration is valid
mbed_official 324:406fd2029f23 675 * in all digital pin muxing modes.
mbed_official 324:406fd2029f23 676 */
mbed_official 324:406fd2029f23 677 typedef union _hw_port_dfer
mbed_official 324:406fd2029f23 678 {
mbed_official 324:406fd2029f23 679 uint32_t U;
mbed_official 324:406fd2029f23 680 struct _hw_port_dfer_bitfields
mbed_official 324:406fd2029f23 681 {
mbed_official 324:406fd2029f23 682 uint32_t DFE : 32; /*!< [31:0] Digital Filter Enable */
mbed_official 324:406fd2029f23 683 } B;
mbed_official 324:406fd2029f23 684 } hw_port_dfer_t;
mbed_official 324:406fd2029f23 685
mbed_official 324:406fd2029f23 686 /*!
mbed_official 324:406fd2029f23 687 * @name Constants and macros for entire PORT_DFER register
mbed_official 324:406fd2029f23 688 */
mbed_official 324:406fd2029f23 689 /*@{*/
mbed_official 324:406fd2029f23 690 #define HW_PORT_DFER_ADDR(x) ((x) + 0xC0U)
mbed_official 324:406fd2029f23 691
mbed_official 324:406fd2029f23 692 #define HW_PORT_DFER(x) (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
mbed_official 324:406fd2029f23 693 #define HW_PORT_DFER_RD(x) (HW_PORT_DFER(x).U)
mbed_official 324:406fd2029f23 694 #define HW_PORT_DFER_WR(x, v) (HW_PORT_DFER(x).U = (v))
mbed_official 324:406fd2029f23 695 #define HW_PORT_DFER_SET(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) | (v)))
mbed_official 324:406fd2029f23 696 #define HW_PORT_DFER_CLR(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 697 #define HW_PORT_DFER_TOG(x, v) (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 698 /*@}*/
mbed_official 324:406fd2029f23 699
mbed_official 324:406fd2029f23 700 /*
mbed_official 324:406fd2029f23 701 * Constants & macros for individual PORT_DFER bitfields
mbed_official 324:406fd2029f23 702 */
mbed_official 324:406fd2029f23 703
mbed_official 324:406fd2029f23 704 /*!
mbed_official 324:406fd2029f23 705 * @name Register PORT_DFER, field DFE[31:0] (RW)
mbed_official 324:406fd2029f23 706 *
mbed_official 324:406fd2029f23 707 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 708 * The output of each digital filter is reset to zero at system reset and whenever
mbed_official 324:406fd2029f23 709 * the digital filter is disabled. Each bit in the field enables the digital
mbed_official 324:406fd2029f23 710 * filter of the same number as the field.
mbed_official 324:406fd2029f23 711 *
mbed_official 324:406fd2029f23 712 * Values:
mbed_official 324:406fd2029f23 713 * - 0 - Digital filter is disabled on the corresponding pin and output of the
mbed_official 324:406fd2029f23 714 * digital filter is reset to zero.
mbed_official 324:406fd2029f23 715 * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
mbed_official 324:406fd2029f23 716 * configured as a digital input.
mbed_official 324:406fd2029f23 717 */
mbed_official 324:406fd2029f23 718 /*@{*/
mbed_official 324:406fd2029f23 719 #define BP_PORT_DFER_DFE (0U) /*!< Bit position for PORT_DFER_DFE. */
mbed_official 324:406fd2029f23 720 #define BM_PORT_DFER_DFE (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
mbed_official 324:406fd2029f23 721 #define BS_PORT_DFER_DFE (32U) /*!< Bit field size in bits for PORT_DFER_DFE. */
mbed_official 324:406fd2029f23 722
mbed_official 324:406fd2029f23 723 /*! @brief Read current value of the PORT_DFER_DFE field. */
mbed_official 324:406fd2029f23 724 #define BR_PORT_DFER_DFE(x) (HW_PORT_DFER(x).U)
mbed_official 324:406fd2029f23 725
mbed_official 324:406fd2029f23 726 /*! @brief Format value for bitfield PORT_DFER_DFE. */
mbed_official 324:406fd2029f23 727 #define BF_PORT_DFER_DFE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
mbed_official 324:406fd2029f23 728
mbed_official 324:406fd2029f23 729 /*! @brief Set the DFE field to a new value. */
mbed_official 324:406fd2029f23 730 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
mbed_official 324:406fd2029f23 731 /*@}*/
mbed_official 324:406fd2029f23 732
mbed_official 324:406fd2029f23 733 /*******************************************************************************
mbed_official 324:406fd2029f23 734 * HW_PORT_DFCR - Digital Filter Clock Register
mbed_official 324:406fd2029f23 735 ******************************************************************************/
mbed_official 324:406fd2029f23 736
mbed_official 324:406fd2029f23 737 /*!
mbed_official 324:406fd2029f23 738 * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
mbed_official 324:406fd2029f23 739 *
mbed_official 324:406fd2029f23 740 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 741 *
mbed_official 324:406fd2029f23 742 * This register is read only for ports that do not support a digital filter.
mbed_official 324:406fd2029f23 743 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 744 */
mbed_official 324:406fd2029f23 745 typedef union _hw_port_dfcr
mbed_official 324:406fd2029f23 746 {
mbed_official 324:406fd2029f23 747 uint32_t U;
mbed_official 324:406fd2029f23 748 struct _hw_port_dfcr_bitfields
mbed_official 324:406fd2029f23 749 {
mbed_official 324:406fd2029f23 750 uint32_t CS : 1; /*!< [0] Clock Source */
mbed_official 324:406fd2029f23 751 uint32_t RESERVED0 : 31; /*!< [31:1] */
mbed_official 324:406fd2029f23 752 } B;
mbed_official 324:406fd2029f23 753 } hw_port_dfcr_t;
mbed_official 324:406fd2029f23 754
mbed_official 324:406fd2029f23 755 /*!
mbed_official 324:406fd2029f23 756 * @name Constants and macros for entire PORT_DFCR register
mbed_official 324:406fd2029f23 757 */
mbed_official 324:406fd2029f23 758 /*@{*/
mbed_official 324:406fd2029f23 759 #define HW_PORT_DFCR_ADDR(x) ((x) + 0xC4U)
mbed_official 324:406fd2029f23 760
mbed_official 324:406fd2029f23 761 #define HW_PORT_DFCR(x) (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
mbed_official 324:406fd2029f23 762 #define HW_PORT_DFCR_RD(x) (HW_PORT_DFCR(x).U)
mbed_official 324:406fd2029f23 763 #define HW_PORT_DFCR_WR(x, v) (HW_PORT_DFCR(x).U = (v))
mbed_official 324:406fd2029f23 764 #define HW_PORT_DFCR_SET(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) | (v)))
mbed_official 324:406fd2029f23 765 #define HW_PORT_DFCR_CLR(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 766 #define HW_PORT_DFCR_TOG(x, v) (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 767 /*@}*/
mbed_official 324:406fd2029f23 768
mbed_official 324:406fd2029f23 769 /*
mbed_official 324:406fd2029f23 770 * Constants & macros for individual PORT_DFCR bitfields
mbed_official 324:406fd2029f23 771 */
mbed_official 324:406fd2029f23 772
mbed_official 324:406fd2029f23 773 /*!
mbed_official 324:406fd2029f23 774 * @name Register PORT_DFCR, field CS[0] (RW)
mbed_official 324:406fd2029f23 775 *
mbed_official 324:406fd2029f23 776 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 777 * Configures the clock source for the digital input filters. Changing the filter
mbed_official 324:406fd2029f23 778 * clock source must be done only when all digital filters are disabled.
mbed_official 324:406fd2029f23 779 *
mbed_official 324:406fd2029f23 780 * Values:
mbed_official 324:406fd2029f23 781 * - 0 - Digital filters are clocked by the bus clock.
mbed_official 324:406fd2029f23 782 * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
mbed_official 324:406fd2029f23 783 */
mbed_official 324:406fd2029f23 784 /*@{*/
mbed_official 324:406fd2029f23 785 #define BP_PORT_DFCR_CS (0U) /*!< Bit position for PORT_DFCR_CS. */
mbed_official 324:406fd2029f23 786 #define BM_PORT_DFCR_CS (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
mbed_official 324:406fd2029f23 787 #define BS_PORT_DFCR_CS (1U) /*!< Bit field size in bits for PORT_DFCR_CS. */
mbed_official 324:406fd2029f23 788
mbed_official 324:406fd2029f23 789 /*! @brief Read current value of the PORT_DFCR_CS field. */
mbed_official 324:406fd2029f23 790 #define BR_PORT_DFCR_CS(x) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS))
mbed_official 324:406fd2029f23 791
mbed_official 324:406fd2029f23 792 /*! @brief Format value for bitfield PORT_DFCR_CS. */
mbed_official 324:406fd2029f23 793 #define BF_PORT_DFCR_CS(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
mbed_official 324:406fd2029f23 794
mbed_official 324:406fd2029f23 795 /*! @brief Set the CS field to a new value. */
mbed_official 324:406fd2029f23 796 #define BW_PORT_DFCR_CS(x, v) (BITBAND_ACCESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS) = (v))
mbed_official 324:406fd2029f23 797 /*@}*/
mbed_official 324:406fd2029f23 798
mbed_official 324:406fd2029f23 799 /*******************************************************************************
mbed_official 324:406fd2029f23 800 * HW_PORT_DFWR - Digital Filter Width Register
mbed_official 324:406fd2029f23 801 ******************************************************************************/
mbed_official 324:406fd2029f23 802
mbed_official 324:406fd2029f23 803 /*!
mbed_official 324:406fd2029f23 804 * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
mbed_official 324:406fd2029f23 805 *
mbed_official 324:406fd2029f23 806 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 807 *
mbed_official 324:406fd2029f23 808 * This register is read only for ports that do not support a digital filter.
mbed_official 324:406fd2029f23 809 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 810 */
mbed_official 324:406fd2029f23 811 typedef union _hw_port_dfwr
mbed_official 324:406fd2029f23 812 {
mbed_official 324:406fd2029f23 813 uint32_t U;
mbed_official 324:406fd2029f23 814 struct _hw_port_dfwr_bitfields
mbed_official 324:406fd2029f23 815 {
mbed_official 324:406fd2029f23 816 uint32_t FILT : 5; /*!< [4:0] Filter Length */
mbed_official 324:406fd2029f23 817 uint32_t RESERVED0 : 27; /*!< [31:5] */
mbed_official 324:406fd2029f23 818 } B;
mbed_official 324:406fd2029f23 819 } hw_port_dfwr_t;
mbed_official 324:406fd2029f23 820
mbed_official 324:406fd2029f23 821 /*!
mbed_official 324:406fd2029f23 822 * @name Constants and macros for entire PORT_DFWR register
mbed_official 324:406fd2029f23 823 */
mbed_official 324:406fd2029f23 824 /*@{*/
mbed_official 324:406fd2029f23 825 #define HW_PORT_DFWR_ADDR(x) ((x) + 0xC8U)
mbed_official 324:406fd2029f23 826
mbed_official 324:406fd2029f23 827 #define HW_PORT_DFWR(x) (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
mbed_official 324:406fd2029f23 828 #define HW_PORT_DFWR_RD(x) (HW_PORT_DFWR(x).U)
mbed_official 324:406fd2029f23 829 #define HW_PORT_DFWR_WR(x, v) (HW_PORT_DFWR(x).U = (v))
mbed_official 324:406fd2029f23 830 #define HW_PORT_DFWR_SET(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) | (v)))
mbed_official 324:406fd2029f23 831 #define HW_PORT_DFWR_CLR(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 832 #define HW_PORT_DFWR_TOG(x, v) (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 833 /*@}*/
mbed_official 324:406fd2029f23 834
mbed_official 324:406fd2029f23 835 /*
mbed_official 324:406fd2029f23 836 * Constants & macros for individual PORT_DFWR bitfields
mbed_official 324:406fd2029f23 837 */
mbed_official 324:406fd2029f23 838
mbed_official 324:406fd2029f23 839 /*!
mbed_official 324:406fd2029f23 840 * @name Register PORT_DFWR, field FILT[4:0] (RW)
mbed_official 324:406fd2029f23 841 *
mbed_official 324:406fd2029f23 842 * The digital filter configuration is valid in all digital pin muxing modes.
mbed_official 324:406fd2029f23 843 * Configures the maximum size of the glitches, in clock cycles, that the digital
mbed_official 324:406fd2029f23 844 * filter absorbs for the enabled digital filters. Glitches that are longer than
mbed_official 324:406fd2029f23 845 * this register setting will pass through the digital filter, and glitches that
mbed_official 324:406fd2029f23 846 * are equal to or less than this register setting are filtered. Changing the
mbed_official 324:406fd2029f23 847 * filter length must be done only after all filters are disabled.
mbed_official 324:406fd2029f23 848 */
mbed_official 324:406fd2029f23 849 /*@{*/
mbed_official 324:406fd2029f23 850 #define BP_PORT_DFWR_FILT (0U) /*!< Bit position for PORT_DFWR_FILT. */
mbed_official 324:406fd2029f23 851 #define BM_PORT_DFWR_FILT (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
mbed_official 324:406fd2029f23 852 #define BS_PORT_DFWR_FILT (5U) /*!< Bit field size in bits for PORT_DFWR_FILT. */
mbed_official 324:406fd2029f23 853
mbed_official 324:406fd2029f23 854 /*! @brief Read current value of the PORT_DFWR_FILT field. */
mbed_official 324:406fd2029f23 855 #define BR_PORT_DFWR_FILT(x) (HW_PORT_DFWR(x).B.FILT)
mbed_official 324:406fd2029f23 856
mbed_official 324:406fd2029f23 857 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
mbed_official 324:406fd2029f23 858 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
mbed_official 324:406fd2029f23 859
mbed_official 324:406fd2029f23 860 /*! @brief Set the FILT field to a new value. */
mbed_official 324:406fd2029f23 861 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
mbed_official 324:406fd2029f23 862 /*@}*/
mbed_official 324:406fd2029f23 863
mbed_official 324:406fd2029f23 864 /*******************************************************************************
mbed_official 324:406fd2029f23 865 * hw_port_t - module struct
mbed_official 324:406fd2029f23 866 ******************************************************************************/
mbed_official 324:406fd2029f23 867 /*!
mbed_official 324:406fd2029f23 868 * @brief All PORT module registers.
mbed_official 324:406fd2029f23 869 */
mbed_official 324:406fd2029f23 870 #pragma pack(1)
mbed_official 324:406fd2029f23 871 typedef struct _hw_port
mbed_official 324:406fd2029f23 872 {
mbed_official 324:406fd2029f23 873 __IO hw_port_pcrn_t PCRn[32]; /*!< [0x0] Pin Control Register n */
mbed_official 324:406fd2029f23 874 __O hw_port_gpclr_t GPCLR; /*!< [0x80] Global Pin Control Low Register */
mbed_official 324:406fd2029f23 875 __O hw_port_gpchr_t GPCHR; /*!< [0x84] Global Pin Control High Register */
mbed_official 324:406fd2029f23 876 uint8_t _reserved0[24];
mbed_official 324:406fd2029f23 877 __IO hw_port_isfr_t ISFR; /*!< [0xA0] Interrupt Status Flag Register */
mbed_official 324:406fd2029f23 878 uint8_t _reserved1[28];
mbed_official 324:406fd2029f23 879 __IO hw_port_dfer_t DFER; /*!< [0xC0] Digital Filter Enable Register */
mbed_official 324:406fd2029f23 880 __IO hw_port_dfcr_t DFCR; /*!< [0xC4] Digital Filter Clock Register */
mbed_official 324:406fd2029f23 881 __IO hw_port_dfwr_t DFWR; /*!< [0xC8] Digital Filter Width Register */
mbed_official 324:406fd2029f23 882 } hw_port_t;
mbed_official 324:406fd2029f23 883 #pragma pack()
mbed_official 324:406fd2029f23 884
mbed_official 324:406fd2029f23 885 /*! @brief Macro to access all PORT registers. */
mbed_official 324:406fd2029f23 886 /*! @param x PORT module instance base address. */
mbed_official 324:406fd2029f23 887 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 888 * use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
mbed_official 324:406fd2029f23 889 #define HW_PORT(x) (*(hw_port_t *)(x))
mbed_official 324:406fd2029f23 890
mbed_official 324:406fd2029f23 891 #endif /* __HW_PORT_REGISTERS_H__ */
mbed_official 324:406fd2029f23 892 /* EOF */