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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-05-06
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-07-23)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 1.1 (2013-09-17)
mbed_official	324:406fd2029f23	50	** RM rev. 0.4 update.
mbed_official	324:406fd2029f23	51	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	52	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	53	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	54	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	55	** System initialization updated.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-20)
mbed_official	324:406fd2029f23	59	** Update according to reference manual rev. 0.6,
mbed_official	324:406fd2029f23	60	** - rev. 2.3 (2014-01-13)
mbed_official	324:406fd2029f23	61	** Update according to reference manual rev. 0.61,
mbed_official	324:406fd2029f23	62	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	63	** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official	324:406fd2029f23	64	** - rev. 2.5 (2014-05-06)
mbed_official	324:406fd2029f23	65	** Update according to reference manual rev. 1.0,
mbed_official	324:406fd2029f23	66	** Update of system and startup files.
mbed_official	324:406fd2029f23	67	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	68	**
mbed_official	324:406fd2029f23	69	** ###################################################################
mbed_official	324:406fd2029f23	70	*/
mbed_official	324:406fd2029f23	71
mbed_official	324:406fd2029f23	72	/*
mbed_official	324:406fd2029f23	73	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	74	*
mbed_official	324:406fd2029f23	75	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	76	*/
mbed_official	324:406fd2029f23	77	#ifndef __HW_PDB_REGISTERS_H__
mbed_official	324:406fd2029f23	78	#define __HW_PDB_REGISTERS_H__
mbed_official	324:406fd2029f23	79
mbed_official	324:406fd2029f23	80	#include "MK22F51212.h"
mbed_official	324:406fd2029f23	81	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	/*
mbed_official	324:406fd2029f23	84	* MK22F51212 PDB
mbed_official	324:406fd2029f23	85	*
mbed_official	324:406fd2029f23	86	* Programmable Delay Block
mbed_official	324:406fd2029f23	87	*
mbed_official	324:406fd2029f23	88	* Registers defined in this header file:
mbed_official	324:406fd2029f23	89	* - HW_PDB_SC - Status and Control register
mbed_official	324:406fd2029f23	90	* - HW_PDB_MOD - Modulus register
mbed_official	324:406fd2029f23	91	* - HW_PDB_CNT - Counter register
mbed_official	324:406fd2029f23	92	* - HW_PDB_IDLY - Interrupt Delay register
mbed_official	324:406fd2029f23	93	* - HW_PDB_CHnC1 - Channel n Control register 1
mbed_official	324:406fd2029f23	94	* - HW_PDB_CHnS - Channel n Status register
mbed_official	324:406fd2029f23	95	* - HW_PDB_CHnDLY0 - Channel n Delay 0 register
mbed_official	324:406fd2029f23	96	* - HW_PDB_CHnDLY1 - Channel n Delay 1 register
mbed_official	324:406fd2029f23	97	* - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
mbed_official	324:406fd2029f23	98	* - HW_PDB_DACINTn - DAC Interval n register
mbed_official	324:406fd2029f23	99	* - HW_PDB_POEN - Pulse-Out n Enable register
mbed_official	324:406fd2029f23	100	* - HW_PDB_POnDLY - Pulse-Out n Delay register
mbed_official	324:406fd2029f23	101	*
mbed_official	324:406fd2029f23	102	* - hw_pdb_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	103	*/
mbed_official	324:406fd2029f23	104
mbed_official	324:406fd2029f23	105	#define HW_PDB_INSTANCE_COUNT (1U) /!< Number of instances of the PDB module. /
mbed_official	324:406fd2029f23	106
mbed_official	324:406fd2029f23	107	/*******************************************************************************
mbed_official	324:406fd2029f23	108	* HW_PDB_SC - Status and Control register
mbed_official	324:406fd2029f23	109	******************************************************************************/
mbed_official	324:406fd2029f23	110
mbed_official	324:406fd2029f23	111	/*!
mbed_official	324:406fd2029f23	112	* @brief HW_PDB_SC - Status and Control register (RW)
mbed_official	324:406fd2029f23	113	*
mbed_official	324:406fd2029f23	114	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	115	*/
mbed_official	324:406fd2029f23	116	typedef union _hw_pdb_sc
mbed_official	324:406fd2029f23	117	{
mbed_official	324:406fd2029f23	118	uint32_t U;
mbed_official	324:406fd2029f23	119	struct _hw_pdb_sc_bitfields
mbed_official	324:406fd2029f23	120	{
mbed_official	324:406fd2029f23	121	uint32_t LDOK : 1; /!< [0] Load OK /
mbed_official	324:406fd2029f23	122	uint32_t CONT : 1; /!< [1] Continuous Mode Enable /
mbed_official	324:406fd2029f23	123	uint32_t MULT : 2; /*!< [3:2] Multiplication Factor Select for
mbed_official	324:406fd2029f23	124	* Prescaler */
mbed_official	324:406fd2029f23	125	uint32_t RESERVED0 : 1; /!< [4] /
mbed_official	324:406fd2029f23	126	uint32_t PDBIE : 1; /!< [5] PDB Interrupt Enable /
mbed_official	324:406fd2029f23	127	uint32_t PDBIF : 1; /!< [6] PDB Interrupt Flag /
mbed_official	324:406fd2029f23	128	uint32_t PDBEN : 1; /!< [7] PDB Enable /
mbed_official	324:406fd2029f23	129	uint32_t TRGSEL : 4; /!< [11:8] Trigger Input Source Select /
mbed_official	324:406fd2029f23	130	uint32_t PRESCALER : 3; /!< [14:12] Prescaler Divider Select /
mbed_official	324:406fd2029f23	131	uint32_t DMAEN : 1; /!< [15] DMA Enable /
mbed_official	324:406fd2029f23	132	uint32_t SWTRIG : 1; /!< [16] Software Trigger /
mbed_official	324:406fd2029f23	133	uint32_t PDBEIE : 1; /!< [17] PDB Sequence Error Interrupt Enable /
mbed_official	324:406fd2029f23	134	uint32_t LDMOD : 2; /!< [19:18] Load Mode Select /
mbed_official	324:406fd2029f23	135	uint32_t RESERVED1 : 12; /!< [31:20] /
mbed_official	324:406fd2029f23	136	} B;
mbed_official	324:406fd2029f23	137	} hw_pdb_sc_t;
mbed_official	324:406fd2029f23	138
mbed_official	324:406fd2029f23	139	/*!
mbed_official	324:406fd2029f23	140	* @name Constants and macros for entire PDB_SC register
mbed_official	324:406fd2029f23	141	*/
mbed_official	324:406fd2029f23	142	/@{/
mbed_official	324:406fd2029f23	143	#define HW_PDB_SC_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	144
mbed_official	324:406fd2029f23	145	#define HW_PDB_SC(x) ((__IO hw_pdb_sc_t ) HW_PDB_SC_ADDR(x))
mbed_official	324:406fd2029f23	146	#define HW_PDB_SC_RD(x) (HW_PDB_SC(x).U)
mbed_official	324:406fd2029f23	147	#define HW_PDB_SC_WR(x, v) (HW_PDB_SC(x).U = (v))
mbed_official	324:406fd2029f23	148	#define HW_PDB_SC_SET(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) \| (v)))
mbed_official	324:406fd2029f23	149	#define HW_PDB_SC_CLR(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	150	#define HW_PDB_SC_TOG(x, v) (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	151	/@}/
mbed_official	324:406fd2029f23	152
mbed_official	324:406fd2029f23	153	/*
mbed_official	324:406fd2029f23	154	* Constants & macros for individual PDB_SC bitfields
mbed_official	324:406fd2029f23	155	*/
mbed_official	324:406fd2029f23	156
mbed_official	324:406fd2029f23	157	/*!
mbed_official	324:406fd2029f23	158	* @name Register PDB_SC, field LDOK[0] (RW)
mbed_official	324:406fd2029f23	159	*
mbed_official	324:406fd2029f23	160	* Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
mbed_official	324:406fd2029f23	161	* DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
mbed_official	324:406fd2029f23	162	* CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
mbed_official	324:406fd2029f23	163	* written to the LDOK field, the values in the buffers of above registers are
mbed_official	324:406fd2029f23	164	* not effective and the buffers cannot be written until the values in buffers are
mbed_official	324:406fd2029f23	165	* loaded into their internal registers. LDOK can be written only when PDBEN is
mbed_official	324:406fd2029f23	166	* set or it can be written at the same time with PDBEN being written to 1. It is
mbed_official	324:406fd2029f23	167	* automatically cleared when the values in buffers are loaded into the internal
mbed_official	324:406fd2029f23	168	* registers or the PDBEN is cleared. Writing 0 to it has no effect.
mbed_official	324:406fd2029f23	169	*/
mbed_official	324:406fd2029f23	170	/@{/
mbed_official	324:406fd2029f23	171	#define BP_PDB_SC_LDOK (0U) /!< Bit position for PDB_SC_LDOK. /
mbed_official	324:406fd2029f23	172	#define BM_PDB_SC_LDOK (0x00000001U) /!< Bit mask for PDB_SC_LDOK. /
mbed_official	324:406fd2029f23	173	#define BS_PDB_SC_LDOK (1U) /!< Bit field size in bits for PDB_SC_LDOK. /
mbed_official	324:406fd2029f23	174
mbed_official	324:406fd2029f23	175	/! @brief Read current value of the PDB_SC_LDOK field. /
mbed_official	324:406fd2029f23	176	#define BR_PDB_SC_LDOK(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK))
mbed_official	324:406fd2029f23	177
mbed_official	324:406fd2029f23	178	/! @brief Format value for bitfield PDB_SC_LDOK. /
mbed_official	324:406fd2029f23	179	#define BF_PDB_SC_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
mbed_official	324:406fd2029f23	180
mbed_official	324:406fd2029f23	181	/! @brief Set the LDOK field to a new value. /
mbed_official	324:406fd2029f23	182	#define BW_PDB_SC_LDOK(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK) = (v))
mbed_official	324:406fd2029f23	183	/@}/
mbed_official	324:406fd2029f23	184
mbed_official	324:406fd2029f23	185	/*!
mbed_official	324:406fd2029f23	186	* @name Register PDB_SC, field CONT[1] (RW)
mbed_official	324:406fd2029f23	187	*
mbed_official	324:406fd2029f23	188	* Enables the PDB operation in Continuous mode.
mbed_official	324:406fd2029f23	189	*
mbed_official	324:406fd2029f23	190	* Values:
mbed_official	324:406fd2029f23	191	* - 0 - PDB operation in One-Shot mode
mbed_official	324:406fd2029f23	192	* - 1 - PDB operation in Continuous mode
mbed_official	324:406fd2029f23	193	*/
mbed_official	324:406fd2029f23	194	/@{/
mbed_official	324:406fd2029f23	195	#define BP_PDB_SC_CONT (1U) /!< Bit position for PDB_SC_CONT. /
mbed_official	324:406fd2029f23	196	#define BM_PDB_SC_CONT (0x00000002U) /!< Bit mask for PDB_SC_CONT. /
mbed_official	324:406fd2029f23	197	#define BS_PDB_SC_CONT (1U) /!< Bit field size in bits for PDB_SC_CONT. /
mbed_official	324:406fd2029f23	198
mbed_official	324:406fd2029f23	199	/! @brief Read current value of the PDB_SC_CONT field. /
mbed_official	324:406fd2029f23	200	#define BR_PDB_SC_CONT(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT))
mbed_official	324:406fd2029f23	201
mbed_official	324:406fd2029f23	202	/! @brief Format value for bitfield PDB_SC_CONT. /
mbed_official	324:406fd2029f23	203	#define BF_PDB_SC_CONT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
mbed_official	324:406fd2029f23	204
mbed_official	324:406fd2029f23	205	/! @brief Set the CONT field to a new value. /
mbed_official	324:406fd2029f23	206	#define BW_PDB_SC_CONT(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT) = (v))
mbed_official	324:406fd2029f23	207	/@}/
mbed_official	324:406fd2029f23	208
mbed_official	324:406fd2029f23	209	/*!
mbed_official	324:406fd2029f23	210	* @name Register PDB_SC, field MULT[3:2] (RW)
mbed_official	324:406fd2029f23	211	*
mbed_official	324:406fd2029f23	212	* Selects the multiplication factor of the prescaler divider for the counter
mbed_official	324:406fd2029f23	213	* clock.
mbed_official	324:406fd2029f23	214	*
mbed_official	324:406fd2029f23	215	* Values:
mbed_official	324:406fd2029f23	216	* - 00 - Multiplication factor is 1.
mbed_official	324:406fd2029f23	217	* - 01 - Multiplication factor is 10.
mbed_official	324:406fd2029f23	218	* - 10 - Multiplication factor is 20.
mbed_official	324:406fd2029f23	219	* - 11 - Multiplication factor is 40.
mbed_official	324:406fd2029f23	220	*/
mbed_official	324:406fd2029f23	221	/@{/
mbed_official	324:406fd2029f23	222	#define BP_PDB_SC_MULT (2U) /!< Bit position for PDB_SC_MULT. /
mbed_official	324:406fd2029f23	223	#define BM_PDB_SC_MULT (0x0000000CU) /!< Bit mask for PDB_SC_MULT. /
mbed_official	324:406fd2029f23	224	#define BS_PDB_SC_MULT (2U) /!< Bit field size in bits for PDB_SC_MULT. /
mbed_official	324:406fd2029f23	225
mbed_official	324:406fd2029f23	226	/! @brief Read current value of the PDB_SC_MULT field. /
mbed_official	324:406fd2029f23	227	#define BR_PDB_SC_MULT(x) (HW_PDB_SC(x).B.MULT)
mbed_official	324:406fd2029f23	228
mbed_official	324:406fd2029f23	229	/! @brief Format value for bitfield PDB_SC_MULT. /
mbed_official	324:406fd2029f23	230	#define BF_PDB_SC_MULT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
mbed_official	324:406fd2029f23	231
mbed_official	324:406fd2029f23	232	/! @brief Set the MULT field to a new value. /
mbed_official	324:406fd2029f23	233	#define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) \| BF_PDB_SC_MULT(v)))
mbed_official	324:406fd2029f23	234	/@}/
mbed_official	324:406fd2029f23	235
mbed_official	324:406fd2029f23	236	/*!
mbed_official	324:406fd2029f23	237	* @name Register PDB_SC, field PDBIE[5] (RW)
mbed_official	324:406fd2029f23	238	*
mbed_official	324:406fd2029f23	239	* Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
mbed_official	324:406fd2029f23	240	* generates a PDB interrupt.
mbed_official	324:406fd2029f23	241	*
mbed_official	324:406fd2029f23	242	* Values:
mbed_official	324:406fd2029f23	243	* - 0 - PDB interrupt disabled.
mbed_official	324:406fd2029f23	244	* - 1 - PDB interrupt enabled.
mbed_official	324:406fd2029f23	245	*/
mbed_official	324:406fd2029f23	246	/@{/
mbed_official	324:406fd2029f23	247	#define BP_PDB_SC_PDBIE (5U) /!< Bit position for PDB_SC_PDBIE. /
mbed_official	324:406fd2029f23	248	#define BM_PDB_SC_PDBIE (0x00000020U) /!< Bit mask for PDB_SC_PDBIE. /
mbed_official	324:406fd2029f23	249	#define BS_PDB_SC_PDBIE (1U) /!< Bit field size in bits for PDB_SC_PDBIE. /
mbed_official	324:406fd2029f23	250
mbed_official	324:406fd2029f23	251	/! @brief Read current value of the PDB_SC_PDBIE field. /
mbed_official	324:406fd2029f23	252	#define BR_PDB_SC_PDBIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE))
mbed_official	324:406fd2029f23	253
mbed_official	324:406fd2029f23	254	/! @brief Format value for bitfield PDB_SC_PDBIE. /
mbed_official	324:406fd2029f23	255	#define BF_PDB_SC_PDBIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
mbed_official	324:406fd2029f23	256
mbed_official	324:406fd2029f23	257	/! @brief Set the PDBIE field to a new value. /
mbed_official	324:406fd2029f23	258	#define BW_PDB_SC_PDBIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE) = (v))
mbed_official	324:406fd2029f23	259	/@}/
mbed_official	324:406fd2029f23	260
mbed_official	324:406fd2029f23	261	/*!
mbed_official	324:406fd2029f23	262	* @name Register PDB_SC, field PDBIF[6] (RW)
mbed_official	324:406fd2029f23	263	*
mbed_official	324:406fd2029f23	264	* This field is set when the counter value is equal to the IDLY register.
mbed_official	324:406fd2029f23	265	* Writing zero clears this field.
mbed_official	324:406fd2029f23	266	*/
mbed_official	324:406fd2029f23	267	/@{/
mbed_official	324:406fd2029f23	268	#define BP_PDB_SC_PDBIF (6U) /!< Bit position for PDB_SC_PDBIF. /
mbed_official	324:406fd2029f23	269	#define BM_PDB_SC_PDBIF (0x00000040U) /!< Bit mask for PDB_SC_PDBIF. /
mbed_official	324:406fd2029f23	270	#define BS_PDB_SC_PDBIF (1U) /!< Bit field size in bits for PDB_SC_PDBIF. /
mbed_official	324:406fd2029f23	271
mbed_official	324:406fd2029f23	272	/! @brief Read current value of the PDB_SC_PDBIF field. /
mbed_official	324:406fd2029f23	273	#define BR_PDB_SC_PDBIF(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF))
mbed_official	324:406fd2029f23	274
mbed_official	324:406fd2029f23	275	/! @brief Format value for bitfield PDB_SC_PDBIF. /
mbed_official	324:406fd2029f23	276	#define BF_PDB_SC_PDBIF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
mbed_official	324:406fd2029f23	277
mbed_official	324:406fd2029f23	278	/! @brief Set the PDBIF field to a new value. /
mbed_official	324:406fd2029f23	279	#define BW_PDB_SC_PDBIF(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF) = (v))
mbed_official	324:406fd2029f23	280	/@}/
mbed_official	324:406fd2029f23	281
mbed_official	324:406fd2029f23	282	/*!
mbed_official	324:406fd2029f23	283	* @name Register PDB_SC, field PDBEN[7] (RW)
mbed_official	324:406fd2029f23	284	*
mbed_official	324:406fd2029f23	285	* Values:
mbed_official	324:406fd2029f23	286	* - 0 - PDB disabled. Counter is off.
mbed_official	324:406fd2029f23	287	* - 1 - PDB enabled.
mbed_official	324:406fd2029f23	288	*/
mbed_official	324:406fd2029f23	289	/@{/
mbed_official	324:406fd2029f23	290	#define BP_PDB_SC_PDBEN (7U) /!< Bit position for PDB_SC_PDBEN. /
mbed_official	324:406fd2029f23	291	#define BM_PDB_SC_PDBEN (0x00000080U) /!< Bit mask for PDB_SC_PDBEN. /
mbed_official	324:406fd2029f23	292	#define BS_PDB_SC_PDBEN (1U) /!< Bit field size in bits for PDB_SC_PDBEN. /
mbed_official	324:406fd2029f23	293
mbed_official	324:406fd2029f23	294	/! @brief Read current value of the PDB_SC_PDBEN field. /
mbed_official	324:406fd2029f23	295	#define BR_PDB_SC_PDBEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN))
mbed_official	324:406fd2029f23	296
mbed_official	324:406fd2029f23	297	/! @brief Format value for bitfield PDB_SC_PDBEN. /
mbed_official	324:406fd2029f23	298	#define BF_PDB_SC_PDBEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
mbed_official	324:406fd2029f23	299
mbed_official	324:406fd2029f23	300	/! @brief Set the PDBEN field to a new value. /
mbed_official	324:406fd2029f23	301	#define BW_PDB_SC_PDBEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN) = (v))
mbed_official	324:406fd2029f23	302	/@}/
mbed_official	324:406fd2029f23	303
mbed_official	324:406fd2029f23	304	/*!
mbed_official	324:406fd2029f23	305	* @name Register PDB_SC, field TRGSEL[11:8] (RW)
mbed_official	324:406fd2029f23	306	*
mbed_official	324:406fd2029f23	307	* Selects the trigger input source for the PDB. The trigger input source can be
mbed_official	324:406fd2029f23	308	* internal or external (EXTRG pin), or the software trigger. Refer to chip
mbed_official	324:406fd2029f23	309	* configuration details for the actual PDB input trigger connections.
mbed_official	324:406fd2029f23	310	*
mbed_official	324:406fd2029f23	311	* Values:
mbed_official	324:406fd2029f23	312	* - 0000 - Trigger-In 0 is selected.
mbed_official	324:406fd2029f23	313	* - 0001 - Trigger-In 1 is selected.
mbed_official	324:406fd2029f23	314	* - 0010 - Trigger-In 2 is selected.
mbed_official	324:406fd2029f23	315	* - 0011 - Trigger-In 3 is selected.
mbed_official	324:406fd2029f23	316	* - 0100 - Trigger-In 4 is selected.
mbed_official	324:406fd2029f23	317	* - 0101 - Trigger-In 5 is selected.
mbed_official	324:406fd2029f23	318	* - 0110 - Trigger-In 6 is selected.
mbed_official	324:406fd2029f23	319	* - 0111 - Trigger-In 7 is selected.
mbed_official	324:406fd2029f23	320	* - 1000 - Trigger-In 8 is selected.
mbed_official	324:406fd2029f23	321	* - 1001 - Trigger-In 9 is selected.
mbed_official	324:406fd2029f23	322	* - 1010 - Trigger-In 10 is selected.
mbed_official	324:406fd2029f23	323	* - 1011 - Trigger-In 11 is selected.
mbed_official	324:406fd2029f23	324	* - 1100 - Trigger-In 12 is selected.
mbed_official	324:406fd2029f23	325	* - 1101 - Trigger-In 13 is selected.
mbed_official	324:406fd2029f23	326	* - 1110 - Trigger-In 14 is selected.
mbed_official	324:406fd2029f23	327	* - 1111 - Software trigger is selected.
mbed_official	324:406fd2029f23	328	*/
mbed_official	324:406fd2029f23	329	/@{/
mbed_official	324:406fd2029f23	330	#define BP_PDB_SC_TRGSEL (8U) /!< Bit position for PDB_SC_TRGSEL. /
mbed_official	324:406fd2029f23	331	#define BM_PDB_SC_TRGSEL (0x00000F00U) /!< Bit mask for PDB_SC_TRGSEL. /
mbed_official	324:406fd2029f23	332	#define BS_PDB_SC_TRGSEL (4U) /!< Bit field size in bits for PDB_SC_TRGSEL. /
mbed_official	324:406fd2029f23	333
mbed_official	324:406fd2029f23	334	/! @brief Read current value of the PDB_SC_TRGSEL field. /
mbed_official	324:406fd2029f23	335	#define BR_PDB_SC_TRGSEL(x) (HW_PDB_SC(x).B.TRGSEL)
mbed_official	324:406fd2029f23	336
mbed_official	324:406fd2029f23	337	/! @brief Format value for bitfield PDB_SC_TRGSEL. /
mbed_official	324:406fd2029f23	338	#define BF_PDB_SC_TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
mbed_official	324:406fd2029f23	339
mbed_official	324:406fd2029f23	340	/! @brief Set the TRGSEL field to a new value. /
mbed_official	324:406fd2029f23	341	#define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) \| BF_PDB_SC_TRGSEL(v)))
mbed_official	324:406fd2029f23	342	/@}/
mbed_official	324:406fd2029f23	343
mbed_official	324:406fd2029f23	344	/*!
mbed_official	324:406fd2029f23	345	* @name Register PDB_SC, field PRESCALER[14:12] (RW)
mbed_official	324:406fd2029f23	346	*
mbed_official	324:406fd2029f23	347	* Values:
mbed_official	324:406fd2029f23	348	* - 000 - Counting uses the peripheral clock divided by multiplication factor
mbed_official	324:406fd2029f23	349	* selected by MULT.
mbed_official	324:406fd2029f23	350	* - 001 - Counting uses the peripheral clock divided by twice of the
mbed_official	324:406fd2029f23	351	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	352	* - 010 - Counting uses the peripheral clock divided by four times of the
mbed_official	324:406fd2029f23	353	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	354	* - 011 - Counting uses the peripheral clock divided by eight times of the
mbed_official	324:406fd2029f23	355	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	356	* - 100 - Counting uses the peripheral clock divided by 16 times of the
mbed_official	324:406fd2029f23	357	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	358	* - 101 - Counting uses the peripheral clock divided by 32 times of the
mbed_official	324:406fd2029f23	359	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	360	* - 110 - Counting uses the peripheral clock divided by 64 times of the
mbed_official	324:406fd2029f23	361	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	362	* - 111 - Counting uses the peripheral clock divided by 128 times of the
mbed_official	324:406fd2029f23	363	* multiplication factor selected by MULT.
mbed_official	324:406fd2029f23	364	*/
mbed_official	324:406fd2029f23	365	/@{/
mbed_official	324:406fd2029f23	366	#define BP_PDB_SC_PRESCALER (12U) /!< Bit position for PDB_SC_PRESCALER. /
mbed_official	324:406fd2029f23	367	#define BM_PDB_SC_PRESCALER (0x00007000U) /!< Bit mask for PDB_SC_PRESCALER. /
mbed_official	324:406fd2029f23	368	#define BS_PDB_SC_PRESCALER (3U) /!< Bit field size in bits for PDB_SC_PRESCALER. /
mbed_official	324:406fd2029f23	369
mbed_official	324:406fd2029f23	370	/! @brief Read current value of the PDB_SC_PRESCALER field. /
mbed_official	324:406fd2029f23	371	#define BR_PDB_SC_PRESCALER(x) (HW_PDB_SC(x).B.PRESCALER)
mbed_official	324:406fd2029f23	372
mbed_official	324:406fd2029f23	373	/! @brief Format value for bitfield PDB_SC_PRESCALER. /
mbed_official	324:406fd2029f23	374	#define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
mbed_official	324:406fd2029f23	375
mbed_official	324:406fd2029f23	376	/! @brief Set the PRESCALER field to a new value. /
mbed_official	324:406fd2029f23	377	#define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) \| BF_PDB_SC_PRESCALER(v)))
mbed_official	324:406fd2029f23	378	/@}/
mbed_official	324:406fd2029f23	379
mbed_official	324:406fd2029f23	380	/*!
mbed_official	324:406fd2029f23	381	* @name Register PDB_SC, field DMAEN[15] (RW)
mbed_official	324:406fd2029f23	382	*
mbed_official	324:406fd2029f23	383	* When DMA is enabled, the PDBIF flag generates a DMA request instead of an
mbed_official	324:406fd2029f23	384	* interrupt.
mbed_official	324:406fd2029f23	385	*
mbed_official	324:406fd2029f23	386	* Values:
mbed_official	324:406fd2029f23	387	* - 0 - DMA disabled.
mbed_official	324:406fd2029f23	388	* - 1 - DMA enabled.
mbed_official	324:406fd2029f23	389	*/
mbed_official	324:406fd2029f23	390	/@{/
mbed_official	324:406fd2029f23	391	#define BP_PDB_SC_DMAEN (15U) /!< Bit position for PDB_SC_DMAEN. /
mbed_official	324:406fd2029f23	392	#define BM_PDB_SC_DMAEN (0x00008000U) /!< Bit mask for PDB_SC_DMAEN. /
mbed_official	324:406fd2029f23	393	#define BS_PDB_SC_DMAEN (1U) /!< Bit field size in bits for PDB_SC_DMAEN. /
mbed_official	324:406fd2029f23	394
mbed_official	324:406fd2029f23	395	/! @brief Read current value of the PDB_SC_DMAEN field. /
mbed_official	324:406fd2029f23	396	#define BR_PDB_SC_DMAEN(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN))
mbed_official	324:406fd2029f23	397
mbed_official	324:406fd2029f23	398	/! @brief Format value for bitfield PDB_SC_DMAEN. /
mbed_official	324:406fd2029f23	399	#define BF_PDB_SC_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
mbed_official	324:406fd2029f23	400
mbed_official	324:406fd2029f23	401	/! @brief Set the DMAEN field to a new value. /
mbed_official	324:406fd2029f23	402	#define BW_PDB_SC_DMAEN(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN) = (v))
mbed_official	324:406fd2029f23	403	/@}/
mbed_official	324:406fd2029f23	404
mbed_official	324:406fd2029f23	405	/*!
mbed_official	324:406fd2029f23	406	* @name Register PDB_SC, field SWTRIG[16] (WORZ)
mbed_official	324:406fd2029f23	407	*
mbed_official	324:406fd2029f23	408	* When PDB is enabled and the software trigger is selected as the trigger input
mbed_official	324:406fd2029f23	409	* source, writing 1 to this field resets and restarts the counter. Writing 0 to
mbed_official	324:406fd2029f23	410	* this field has no effect. Reading this field results 0.
mbed_official	324:406fd2029f23	411	*/
mbed_official	324:406fd2029f23	412	/@{/
mbed_official	324:406fd2029f23	413	#define BP_PDB_SC_SWTRIG (16U) /!< Bit position for PDB_SC_SWTRIG. /
mbed_official	324:406fd2029f23	414	#define BM_PDB_SC_SWTRIG (0x00010000U) /!< Bit mask for PDB_SC_SWTRIG. /
mbed_official	324:406fd2029f23	415	#define BS_PDB_SC_SWTRIG (1U) /!< Bit field size in bits for PDB_SC_SWTRIG. /
mbed_official	324:406fd2029f23	416
mbed_official	324:406fd2029f23	417	/! @brief Format value for bitfield PDB_SC_SWTRIG. /
mbed_official	324:406fd2029f23	418	#define BF_PDB_SC_SWTRIG(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
mbed_official	324:406fd2029f23	419
mbed_official	324:406fd2029f23	420	/! @brief Set the SWTRIG field to a new value. /
mbed_official	324:406fd2029f23	421	#define BW_PDB_SC_SWTRIG(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG) = (v))
mbed_official	324:406fd2029f23	422	/@}/
mbed_official	324:406fd2029f23	423
mbed_official	324:406fd2029f23	424	/*!
mbed_official	324:406fd2029f23	425	* @name Register PDB_SC, field PDBEIE[17] (RW)
mbed_official	324:406fd2029f23	426	*
mbed_official	324:406fd2029f23	427	* Enables the PDB sequence error interrupt. When this field is set, any of the
mbed_official	324:406fd2029f23	428	* PDB channel sequence error flags generates a PDB sequence error interrupt.
mbed_official	324:406fd2029f23	429	*
mbed_official	324:406fd2029f23	430	* Values:
mbed_official	324:406fd2029f23	431	* - 0 - PDB sequence error interrupt disabled.
mbed_official	324:406fd2029f23	432	* - 1 - PDB sequence error interrupt enabled.
mbed_official	324:406fd2029f23	433	*/
mbed_official	324:406fd2029f23	434	/@{/
mbed_official	324:406fd2029f23	435	#define BP_PDB_SC_PDBEIE (17U) /!< Bit position for PDB_SC_PDBEIE. /
mbed_official	324:406fd2029f23	436	#define BM_PDB_SC_PDBEIE (0x00020000U) /!< Bit mask for PDB_SC_PDBEIE. /
mbed_official	324:406fd2029f23	437	#define BS_PDB_SC_PDBEIE (1U) /!< Bit field size in bits for PDB_SC_PDBEIE. /
mbed_official	324:406fd2029f23	438
mbed_official	324:406fd2029f23	439	/! @brief Read current value of the PDB_SC_PDBEIE field. /
mbed_official	324:406fd2029f23	440	#define BR_PDB_SC_PDBEIE(x) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE))
mbed_official	324:406fd2029f23	441
mbed_official	324:406fd2029f23	442	/! @brief Format value for bitfield PDB_SC_PDBEIE. /
mbed_official	324:406fd2029f23	443	#define BF_PDB_SC_PDBEIE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
mbed_official	324:406fd2029f23	444
mbed_official	324:406fd2029f23	445	/! @brief Set the PDBEIE field to a new value. /
mbed_official	324:406fd2029f23	446	#define BW_PDB_SC_PDBEIE(x, v) (BITBAND_ACCESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE) = (v))
mbed_official	324:406fd2029f23	447	/@}/
mbed_official	324:406fd2029f23	448
mbed_official	324:406fd2029f23	449	/*!
mbed_official	324:406fd2029f23	450	* @name Register PDB_SC, field LDMOD[19:18] (RW)
mbed_official	324:406fd2029f23	451	*
mbed_official	324:406fd2029f23	452	* Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
mbed_official	324:406fd2029f23	453	* after 1 is written to LDOK.
mbed_official	324:406fd2029f23	454	*
mbed_official	324:406fd2029f23	455	* Values:
mbed_official	324:406fd2029f23	456	* - 00 - The internal registers are loaded with the values from their buffers
mbed_official	324:406fd2029f23	457	* immediately after 1 is written to LDOK.
mbed_official	324:406fd2029f23	458	* - 01 - The internal registers are loaded with the values from their buffers
mbed_official	324:406fd2029f23	459	* when the PDB counter reaches the MOD register value after 1 is written to
mbed_official	324:406fd2029f23	460	* LDOK.
mbed_official	324:406fd2029f23	461	* - 10 - The internal registers are loaded with the values from their buffers
mbed_official	324:406fd2029f23	462	* when a trigger input event is detected after 1 is written to LDOK.
mbed_official	324:406fd2029f23	463	* - 11 - The internal registers are loaded with the values from their buffers
mbed_official	324:406fd2029f23	464	* when either the PDB counter reaches the MOD register value or a trigger
mbed_official	324:406fd2029f23	465	* input event is detected, after 1 is written to LDOK.
mbed_official	324:406fd2029f23	466	*/
mbed_official	324:406fd2029f23	467	/@{/
mbed_official	324:406fd2029f23	468	#define BP_PDB_SC_LDMOD (18U) /!< Bit position for PDB_SC_LDMOD. /
mbed_official	324:406fd2029f23	469	#define BM_PDB_SC_LDMOD (0x000C0000U) /!< Bit mask for PDB_SC_LDMOD. /
mbed_official	324:406fd2029f23	470	#define BS_PDB_SC_LDMOD (2U) /!< Bit field size in bits for PDB_SC_LDMOD. /
mbed_official	324:406fd2029f23	471
mbed_official	324:406fd2029f23	472	/! @brief Read current value of the PDB_SC_LDMOD field. /
mbed_official	324:406fd2029f23	473	#define BR_PDB_SC_LDMOD(x) (HW_PDB_SC(x).B.LDMOD)
mbed_official	324:406fd2029f23	474
mbed_official	324:406fd2029f23	475	/! @brief Format value for bitfield PDB_SC_LDMOD. /
mbed_official	324:406fd2029f23	476	#define BF_PDB_SC_LDMOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
mbed_official	324:406fd2029f23	477
mbed_official	324:406fd2029f23	478	/! @brief Set the LDMOD field to a new value. /
mbed_official	324:406fd2029f23	479	#define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) \| BF_PDB_SC_LDMOD(v)))
mbed_official	324:406fd2029f23	480	/@}/
mbed_official	324:406fd2029f23	481
mbed_official	324:406fd2029f23	482	/*******************************************************************************
mbed_official	324:406fd2029f23	483	* HW_PDB_MOD - Modulus register
mbed_official	324:406fd2029f23	484	******************************************************************************/
mbed_official	324:406fd2029f23	485
mbed_official	324:406fd2029f23	486	/*!
mbed_official	324:406fd2029f23	487	* @brief HW_PDB_MOD - Modulus register (RW)
mbed_official	324:406fd2029f23	488	*
mbed_official	324:406fd2029f23	489	* Reset value: 0x0000FFFFU
mbed_official	324:406fd2029f23	490	*/
mbed_official	324:406fd2029f23	491	typedef union _hw_pdb_mod
mbed_official	324:406fd2029f23	492	{
mbed_official	324:406fd2029f23	493	uint32_t U;
mbed_official	324:406fd2029f23	494	struct _hw_pdb_mod_bitfields
mbed_official	324:406fd2029f23	495	{
mbed_official	324:406fd2029f23	496	uint32_t MOD : 16; /!< [15:0] PDB Modulus /
mbed_official	324:406fd2029f23	497	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	498	} B;
mbed_official	324:406fd2029f23	499	} hw_pdb_mod_t;
mbed_official	324:406fd2029f23	500
mbed_official	324:406fd2029f23	501	/*!
mbed_official	324:406fd2029f23	502	* @name Constants and macros for entire PDB_MOD register
mbed_official	324:406fd2029f23	503	*/
mbed_official	324:406fd2029f23	504	/@{/
mbed_official	324:406fd2029f23	505	#define HW_PDB_MOD_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	506
mbed_official	324:406fd2029f23	507	#define HW_PDB_MOD(x) ((__IO hw_pdb_mod_t ) HW_PDB_MOD_ADDR(x))
mbed_official	324:406fd2029f23	508	#define HW_PDB_MOD_RD(x) (HW_PDB_MOD(x).U)
mbed_official	324:406fd2029f23	509	#define HW_PDB_MOD_WR(x, v) (HW_PDB_MOD(x).U = (v))
mbed_official	324:406fd2029f23	510	#define HW_PDB_MOD_SET(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) \| (v)))
mbed_official	324:406fd2029f23	511	#define HW_PDB_MOD_CLR(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	512	#define HW_PDB_MOD_TOG(x, v) (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	513	/@}/
mbed_official	324:406fd2029f23	514
mbed_official	324:406fd2029f23	515	/*
mbed_official	324:406fd2029f23	516	* Constants & macros for individual PDB_MOD bitfields
mbed_official	324:406fd2029f23	517	*/
mbed_official	324:406fd2029f23	518
mbed_official	324:406fd2029f23	519	/*!
mbed_official	324:406fd2029f23	520	* @name Register PDB_MOD, field MOD[15:0] (RW)
mbed_official	324:406fd2029f23	521	*
mbed_official	324:406fd2029f23	522	* Specifies the period of the counter. When the counter reaches this value, it
mbed_official	324:406fd2029f23	523	* will be reset back to zero. If the PDB is in Continuous mode, the count begins
mbed_official	324:406fd2029f23	524	* anew. Reading this field returns the value of the internal register that is
mbed_official	324:406fd2029f23	525	* effective for the current cycle of PDB.
mbed_official	324:406fd2029f23	526	*/
mbed_official	324:406fd2029f23	527	/@{/
mbed_official	324:406fd2029f23	528	#define BP_PDB_MOD_MOD (0U) /!< Bit position for PDB_MOD_MOD. /
mbed_official	324:406fd2029f23	529	#define BM_PDB_MOD_MOD (0x0000FFFFU) /!< Bit mask for PDB_MOD_MOD. /
mbed_official	324:406fd2029f23	530	#define BS_PDB_MOD_MOD (16U) /!< Bit field size in bits for PDB_MOD_MOD. /
mbed_official	324:406fd2029f23	531
mbed_official	324:406fd2029f23	532	/! @brief Read current value of the PDB_MOD_MOD field. /
mbed_official	324:406fd2029f23	533	#define BR_PDB_MOD_MOD(x) (HW_PDB_MOD(x).B.MOD)
mbed_official	324:406fd2029f23	534
mbed_official	324:406fd2029f23	535	/! @brief Format value for bitfield PDB_MOD_MOD. /
mbed_official	324:406fd2029f23	536	#define BF_PDB_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
mbed_official	324:406fd2029f23	537
mbed_official	324:406fd2029f23	538	/! @brief Set the MOD field to a new value. /
mbed_official	324:406fd2029f23	539	#define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) \| BF_PDB_MOD_MOD(v)))
mbed_official	324:406fd2029f23	540	/@}/
mbed_official	324:406fd2029f23	541
mbed_official	324:406fd2029f23	542	/*******************************************************************************
mbed_official	324:406fd2029f23	543	* HW_PDB_CNT - Counter register
mbed_official	324:406fd2029f23	544	******************************************************************************/
mbed_official	324:406fd2029f23	545
mbed_official	324:406fd2029f23	546	/*!
mbed_official	324:406fd2029f23	547	* @brief HW_PDB_CNT - Counter register (RO)
mbed_official	324:406fd2029f23	548	*
mbed_official	324:406fd2029f23	549	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	550	*/
mbed_official	324:406fd2029f23	551	typedef union _hw_pdb_cnt
mbed_official	324:406fd2029f23	552	{
mbed_official	324:406fd2029f23	553	uint32_t U;
mbed_official	324:406fd2029f23	554	struct _hw_pdb_cnt_bitfields
mbed_official	324:406fd2029f23	555	{
mbed_official	324:406fd2029f23	556	uint32_t CNT : 16; /!< [15:0] PDB Counter /
mbed_official	324:406fd2029f23	557	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	558	} B;
mbed_official	324:406fd2029f23	559	} hw_pdb_cnt_t;
mbed_official	324:406fd2029f23	560
mbed_official	324:406fd2029f23	561	/*!
mbed_official	324:406fd2029f23	562	* @name Constants and macros for entire PDB_CNT register
mbed_official	324:406fd2029f23	563	*/
mbed_official	324:406fd2029f23	564	/@{/
mbed_official	324:406fd2029f23	565	#define HW_PDB_CNT_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	566
mbed_official	324:406fd2029f23	567	#define HW_PDB_CNT(x) ((__I hw_pdb_cnt_t ) HW_PDB_CNT_ADDR(x))
mbed_official	324:406fd2029f23	568	#define HW_PDB_CNT_RD(x) (HW_PDB_CNT(x).U)
mbed_official	324:406fd2029f23	569	/@}/
mbed_official	324:406fd2029f23	570
mbed_official	324:406fd2029f23	571	/*
mbed_official	324:406fd2029f23	572	* Constants & macros for individual PDB_CNT bitfields
mbed_official	324:406fd2029f23	573	*/
mbed_official	324:406fd2029f23	574
mbed_official	324:406fd2029f23	575	/*!
mbed_official	324:406fd2029f23	576	* @name Register PDB_CNT, field CNT[15:0] (RO)
mbed_official	324:406fd2029f23	577	*
mbed_official	324:406fd2029f23	578	* Contains the current value of the counter.
mbed_official	324:406fd2029f23	579	*/
mbed_official	324:406fd2029f23	580	/@{/
mbed_official	324:406fd2029f23	581	#define BP_PDB_CNT_CNT (0U) /!< Bit position for PDB_CNT_CNT. /
mbed_official	324:406fd2029f23	582	#define BM_PDB_CNT_CNT (0x0000FFFFU) /!< Bit mask for PDB_CNT_CNT. /
mbed_official	324:406fd2029f23	583	#define BS_PDB_CNT_CNT (16U) /!< Bit field size in bits for PDB_CNT_CNT. /
mbed_official	324:406fd2029f23	584
mbed_official	324:406fd2029f23	585	/! @brief Read current value of the PDB_CNT_CNT field. /
mbed_official	324:406fd2029f23	586	#define BR_PDB_CNT_CNT(x) (HW_PDB_CNT(x).B.CNT)
mbed_official	324:406fd2029f23	587	/@}/
mbed_official	324:406fd2029f23	588
mbed_official	324:406fd2029f23	589	/*******************************************************************************
mbed_official	324:406fd2029f23	590	* HW_PDB_IDLY - Interrupt Delay register
mbed_official	324:406fd2029f23	591	******************************************************************************/
mbed_official	324:406fd2029f23	592
mbed_official	324:406fd2029f23	593	/*!
mbed_official	324:406fd2029f23	594	* @brief HW_PDB_IDLY - Interrupt Delay register (RW)
mbed_official	324:406fd2029f23	595	*
mbed_official	324:406fd2029f23	596	* Reset value: 0x0000FFFFU
mbed_official	324:406fd2029f23	597	*/
mbed_official	324:406fd2029f23	598	typedef union _hw_pdb_idly
mbed_official	324:406fd2029f23	599	{
mbed_official	324:406fd2029f23	600	uint32_t U;
mbed_official	324:406fd2029f23	601	struct _hw_pdb_idly_bitfields
mbed_official	324:406fd2029f23	602	{
mbed_official	324:406fd2029f23	603	uint32_t IDLY : 16; /!< [15:0] PDB Interrupt Delay /
mbed_official	324:406fd2029f23	604	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	605	} B;
mbed_official	324:406fd2029f23	606	} hw_pdb_idly_t;
mbed_official	324:406fd2029f23	607
mbed_official	324:406fd2029f23	608	/*!
mbed_official	324:406fd2029f23	609	* @name Constants and macros for entire PDB_IDLY register
mbed_official	324:406fd2029f23	610	*/
mbed_official	324:406fd2029f23	611	/@{/
mbed_official	324:406fd2029f23	612	#define HW_PDB_IDLY_ADDR(x) ((x) + 0xCU)
mbed_official	324:406fd2029f23	613
mbed_official	324:406fd2029f23	614	#define HW_PDB_IDLY(x) ((__IO hw_pdb_idly_t ) HW_PDB_IDLY_ADDR(x))
mbed_official	324:406fd2029f23	615	#define HW_PDB_IDLY_RD(x) (HW_PDB_IDLY(x).U)
mbed_official	324:406fd2029f23	616	#define HW_PDB_IDLY_WR(x, v) (HW_PDB_IDLY(x).U = (v))
mbed_official	324:406fd2029f23	617	#define HW_PDB_IDLY_SET(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) \| (v)))
mbed_official	324:406fd2029f23	618	#define HW_PDB_IDLY_CLR(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	619	#define HW_PDB_IDLY_TOG(x, v) (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	620	/@}/
mbed_official	324:406fd2029f23	621
mbed_official	324:406fd2029f23	622	/*
mbed_official	324:406fd2029f23	623	* Constants & macros for individual PDB_IDLY bitfields
mbed_official	324:406fd2029f23	624	*/
mbed_official	324:406fd2029f23	625
mbed_official	324:406fd2029f23	626	/*!
mbed_official	324:406fd2029f23	627	* @name Register PDB_IDLY, field IDLY[15:0] (RW)
mbed_official	324:406fd2029f23	628	*
mbed_official	324:406fd2029f23	629	* Specifies the delay value to schedule the PDB interrupt. It can be used to
mbed_official	324:406fd2029f23	630	* schedule an independent interrupt at some point in the PDB cycle. If enabled, a
mbed_official	324:406fd2029f23	631	* PDB interrupt is generated, when the counter is equal to the IDLY. Reading
mbed_official	324:406fd2029f23	632	* this field returns the value of internal register that is effective for the
mbed_official	324:406fd2029f23	633	* current cycle of the PDB.
mbed_official	324:406fd2029f23	634	*/
mbed_official	324:406fd2029f23	635	/@{/
mbed_official	324:406fd2029f23	636	#define BP_PDB_IDLY_IDLY (0U) /!< Bit position for PDB_IDLY_IDLY. /
mbed_official	324:406fd2029f23	637	#define BM_PDB_IDLY_IDLY (0x0000FFFFU) /!< Bit mask for PDB_IDLY_IDLY. /
mbed_official	324:406fd2029f23	638	#define BS_PDB_IDLY_IDLY (16U) /!< Bit field size in bits for PDB_IDLY_IDLY. /
mbed_official	324:406fd2029f23	639
mbed_official	324:406fd2029f23	640	/! @brief Read current value of the PDB_IDLY_IDLY field. /
mbed_official	324:406fd2029f23	641	#define BR_PDB_IDLY_IDLY(x) (HW_PDB_IDLY(x).B.IDLY)
mbed_official	324:406fd2029f23	642
mbed_official	324:406fd2029f23	643	/! @brief Format value for bitfield PDB_IDLY_IDLY. /
mbed_official	324:406fd2029f23	644	#define BF_PDB_IDLY_IDLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
mbed_official	324:406fd2029f23	645
mbed_official	324:406fd2029f23	646	/! @brief Set the IDLY field to a new value. /
mbed_official	324:406fd2029f23	647	#define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) \| BF_PDB_IDLY_IDLY(v)))
mbed_official	324:406fd2029f23	648	/@}/
mbed_official	324:406fd2029f23	649
mbed_official	324:406fd2029f23	650	/*******************************************************************************
mbed_official	324:406fd2029f23	651	* HW_PDB_CHnC1 - Channel n Control register 1
mbed_official	324:406fd2029f23	652	******************************************************************************/
mbed_official	324:406fd2029f23	653
mbed_official	324:406fd2029f23	654	/*!
mbed_official	324:406fd2029f23	655	* @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
mbed_official	324:406fd2029f23	656	*
mbed_official	324:406fd2029f23	657	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	658	*
mbed_official	324:406fd2029f23	659	* Each PDB channel has one control register, CHnC1. The bits in this register
mbed_official	324:406fd2029f23	660	* control the functionality of each PDB channel operation.
mbed_official	324:406fd2029f23	661	*/
mbed_official	324:406fd2029f23	662	typedef union _hw_pdb_chnc1
mbed_official	324:406fd2029f23	663	{
mbed_official	324:406fd2029f23	664	uint32_t U;
mbed_official	324:406fd2029f23	665	struct _hw_pdb_chnc1_bitfields
mbed_official	324:406fd2029f23	666	{
mbed_official	324:406fd2029f23	667	uint32_t EN : 8; /!< [7:0] PDB Channel Pre-Trigger Enable /
mbed_official	324:406fd2029f23	668	uint32_t TOS : 8; /!< [15:8] PDB Channel Pre-Trigger Output Select /
mbed_official	324:406fd2029f23	669	uint32_t BB : 8; /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
mbed_official	324:406fd2029f23	670	* Operation Enable */
mbed_official	324:406fd2029f23	671	uint32_t RESERVED0 : 8; /!< [31:24] /
mbed_official	324:406fd2029f23	672	} B;
mbed_official	324:406fd2029f23	673	} hw_pdb_chnc1_t;
mbed_official	324:406fd2029f23	674
mbed_official	324:406fd2029f23	675	/*!
mbed_official	324:406fd2029f23	676	* @name Constants and macros for entire PDB_CHnC1 register
mbed_official	324:406fd2029f23	677	*/
mbed_official	324:406fd2029f23	678	/@{/
mbed_official	324:406fd2029f23	679	#define HW_PDB_CHnC1_COUNT (2U)
mbed_official	324:406fd2029f23	680
mbed_official	324:406fd2029f23	681	#define HW_PDB_CHnC1_ADDR(x, n) ((x) + 0x10U + (0x28U * (n)))
mbed_official	324:406fd2029f23	682
mbed_official	324:406fd2029f23	683	#define HW_PDB_CHnC1(x, n) ((__IO hw_pdb_chnc1_t ) HW_PDB_CHnC1_ADDR(x, n))
mbed_official	324:406fd2029f23	684	#define HW_PDB_CHnC1_RD(x, n) (HW_PDB_CHnC1(x, n).U)
mbed_official	324:406fd2029f23	685	#define HW_PDB_CHnC1_WR(x, n, v) (HW_PDB_CHnC1(x, n).U = (v))
mbed_official	324:406fd2029f23	686	#define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	687	#define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	688	#define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	689	/@}/
mbed_official	324:406fd2029f23	690
mbed_official	324:406fd2029f23	691	/*
mbed_official	324:406fd2029f23	692	* Constants & macros for individual PDB_CHnC1 bitfields
mbed_official	324:406fd2029f23	693	*/
mbed_official	324:406fd2029f23	694
mbed_official	324:406fd2029f23	695	/*!
mbed_official	324:406fd2029f23	696	* @name Register PDB_CHnC1, field EN[7:0] (RW)
mbed_official	324:406fd2029f23	697	*
mbed_official	324:406fd2029f23	698	* These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
mbed_official	324:406fd2029f23	699	* bits are implemented in this MCU.
mbed_official	324:406fd2029f23	700	*
mbed_official	324:406fd2029f23	701	* Values:
mbed_official	324:406fd2029f23	702	* - 0 - PDB channel's corresponding pre-trigger disabled.
mbed_official	324:406fd2029f23	703	* - 1 - PDB channel's corresponding pre-trigger enabled.
mbed_official	324:406fd2029f23	704	*/
mbed_official	324:406fd2029f23	705	/@{/
mbed_official	324:406fd2029f23	706	#define BP_PDB_CHnC1_EN (0U) /!< Bit position for PDB_CHnC1_EN. /
mbed_official	324:406fd2029f23	707	#define BM_PDB_CHnC1_EN (0x000000FFU) /!< Bit mask for PDB_CHnC1_EN. /
mbed_official	324:406fd2029f23	708	#define BS_PDB_CHnC1_EN (8U) /!< Bit field size in bits for PDB_CHnC1_EN. /
mbed_official	324:406fd2029f23	709
mbed_official	324:406fd2029f23	710	/! @brief Read current value of the PDB_CHnC1_EN field. /
mbed_official	324:406fd2029f23	711	#define BR_PDB_CHnC1_EN(x, n) (HW_PDB_CHnC1(x, n).B.EN)
mbed_official	324:406fd2029f23	712
mbed_official	324:406fd2029f23	713	/! @brief Format value for bitfield PDB_CHnC1_EN. /
mbed_official	324:406fd2029f23	714	#define BF_PDB_CHnC1_EN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
mbed_official	324:406fd2029f23	715
mbed_official	324:406fd2029f23	716	/! @brief Set the EN field to a new value. /
mbed_official	324:406fd2029f23	717	#define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) \| BF_PDB_CHnC1_EN(v)))
mbed_official	324:406fd2029f23	718	/@}/
mbed_official	324:406fd2029f23	719
mbed_official	324:406fd2029f23	720	/*!
mbed_official	324:406fd2029f23	721	* @name Register PDB_CHnC1, field TOS[15:8] (RW)
mbed_official	324:406fd2029f23	722	*
mbed_official	324:406fd2029f23	723	* Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
mbed_official	324:406fd2029f23	724	* implemented in this MCU.
mbed_official	324:406fd2029f23	725	*
mbed_official	324:406fd2029f23	726	* Values:
mbed_official	324:406fd2029f23	727	* - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
mbed_official	324:406fd2029f23	728	* pre-trigger asserts one peripheral clock cycle after a rising edge is detected
mbed_official	324:406fd2029f23	729	* on selected trigger input source or software trigger is selected and SWTRIG
mbed_official	324:406fd2029f23	730	* is written with 1.
mbed_official	324:406fd2029f23	731	* - 1 - PDB channel's corresponding pre-trigger asserts when the counter
mbed_official	324:406fd2029f23	732	* reaches the channel delay register and one peripheral clock cycle after a rising
mbed_official	324:406fd2029f23	733	* edge is detected on selected trigger input source or software trigger is
mbed_official	324:406fd2029f23	734	* selected and SETRIG is written with 1.
mbed_official	324:406fd2029f23	735	*/
mbed_official	324:406fd2029f23	736	/@{/
mbed_official	324:406fd2029f23	737	#define BP_PDB_CHnC1_TOS (8U) /!< Bit position for PDB_CHnC1_TOS. /
mbed_official	324:406fd2029f23	738	#define BM_PDB_CHnC1_TOS (0x0000FF00U) /!< Bit mask for PDB_CHnC1_TOS. /
mbed_official	324:406fd2029f23	739	#define BS_PDB_CHnC1_TOS (8U) /!< Bit field size in bits for PDB_CHnC1_TOS. /
mbed_official	324:406fd2029f23	740
mbed_official	324:406fd2029f23	741	/! @brief Read current value of the PDB_CHnC1_TOS field. /
mbed_official	324:406fd2029f23	742	#define BR_PDB_CHnC1_TOS(x, n) (HW_PDB_CHnC1(x, n).B.TOS)
mbed_official	324:406fd2029f23	743
mbed_official	324:406fd2029f23	744	/! @brief Format value for bitfield PDB_CHnC1_TOS. /
mbed_official	324:406fd2029f23	745	#define BF_PDB_CHnC1_TOS(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
mbed_official	324:406fd2029f23	746
mbed_official	324:406fd2029f23	747	/! @brief Set the TOS field to a new value. /
mbed_official	324:406fd2029f23	748	#define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) \| BF_PDB_CHnC1_TOS(v)))
mbed_official	324:406fd2029f23	749	/@}/
mbed_official	324:406fd2029f23	750
mbed_official	324:406fd2029f23	751	/*!
mbed_official	324:406fd2029f23	752	* @name Register PDB_CHnC1, field BB[23:16] (RW)
mbed_official	324:406fd2029f23	753	*
mbed_official	324:406fd2029f23	754	* These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
mbed_official	324:406fd2029f23	755	* Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
mbed_official	324:406fd2029f23	756	* enables the ADC conversions complete to trigger the next PDB channel
mbed_official	324:406fd2029f23	757	* pre-trigger and trigger output, so that the ADC conversions can be triggered on next
mbed_official	324:406fd2029f23	758	* set of configuration and results registers. Application code must only enable
mbed_official	324:406fd2029f23	759	* the back-to-back operation of the PDB pre-triggers at the leading of the
mbed_official	324:406fd2029f23	760	* back-to-back connection chain.
mbed_official	324:406fd2029f23	761	*
mbed_official	324:406fd2029f23	762	* Values:
mbed_official	324:406fd2029f23	763	* - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
mbed_official	324:406fd2029f23	764	* - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
mbed_official	324:406fd2029f23	765	*/
mbed_official	324:406fd2029f23	766	/@{/
mbed_official	324:406fd2029f23	767	#define BP_PDB_CHnC1_BB (16U) /!< Bit position for PDB_CHnC1_BB. /
mbed_official	324:406fd2029f23	768	#define BM_PDB_CHnC1_BB (0x00FF0000U) /!< Bit mask for PDB_CHnC1_BB. /
mbed_official	324:406fd2029f23	769	#define BS_PDB_CHnC1_BB (8U) /!< Bit field size in bits for PDB_CHnC1_BB. /
mbed_official	324:406fd2029f23	770
mbed_official	324:406fd2029f23	771	/! @brief Read current value of the PDB_CHnC1_BB field. /
mbed_official	324:406fd2029f23	772	#define BR_PDB_CHnC1_BB(x, n) (HW_PDB_CHnC1(x, n).B.BB)
mbed_official	324:406fd2029f23	773
mbed_official	324:406fd2029f23	774	/! @brief Format value for bitfield PDB_CHnC1_BB. /
mbed_official	324:406fd2029f23	775	#define BF_PDB_CHnC1_BB(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
mbed_official	324:406fd2029f23	776
mbed_official	324:406fd2029f23	777	/! @brief Set the BB field to a new value. /
mbed_official	324:406fd2029f23	778	#define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) \| BF_PDB_CHnC1_BB(v)))
mbed_official	324:406fd2029f23	779	/@}/
mbed_official	324:406fd2029f23	780	/*******************************************************************************
mbed_official	324:406fd2029f23	781	* HW_PDB_CHnS - Channel n Status register
mbed_official	324:406fd2029f23	782	******************************************************************************/
mbed_official	324:406fd2029f23	783
mbed_official	324:406fd2029f23	784	/*!
mbed_official	324:406fd2029f23	785	* @brief HW_PDB_CHnS - Channel n Status register (RW)
mbed_official	324:406fd2029f23	786	*
mbed_official	324:406fd2029f23	787	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	788	*/
mbed_official	324:406fd2029f23	789	typedef union _hw_pdb_chns
mbed_official	324:406fd2029f23	790	{
mbed_official	324:406fd2029f23	791	uint32_t U;
mbed_official	324:406fd2029f23	792	struct _hw_pdb_chns_bitfields
mbed_official	324:406fd2029f23	793	{
mbed_official	324:406fd2029f23	794	uint32_t ERR : 8; /!< [7:0] PDB Channel Sequence Error Flags /
mbed_official	324:406fd2029f23	795	uint32_t RESERVED0 : 8; /!< [15:8] /
mbed_official	324:406fd2029f23	796	uint32_t CF : 8; /!< [23:16] PDB Channel Flags /
mbed_official	324:406fd2029f23	797	uint32_t RESERVED1 : 8; /!< [31:24] /
mbed_official	324:406fd2029f23	798	} B;
mbed_official	324:406fd2029f23	799	} hw_pdb_chns_t;
mbed_official	324:406fd2029f23	800
mbed_official	324:406fd2029f23	801	/*!
mbed_official	324:406fd2029f23	802	* @name Constants and macros for entire PDB_CHnS register
mbed_official	324:406fd2029f23	803	*/
mbed_official	324:406fd2029f23	804	/@{/
mbed_official	324:406fd2029f23	805	#define HW_PDB_CHnS_COUNT (2U)
mbed_official	324:406fd2029f23	806
mbed_official	324:406fd2029f23	807	#define HW_PDB_CHnS_ADDR(x, n) ((x) + 0x14U + (0x28U * (n)))
mbed_official	324:406fd2029f23	808
mbed_official	324:406fd2029f23	809	#define HW_PDB_CHnS(x, n) ((__IO hw_pdb_chns_t ) HW_PDB_CHnS_ADDR(x, n))
mbed_official	324:406fd2029f23	810	#define HW_PDB_CHnS_RD(x, n) (HW_PDB_CHnS(x, n).U)
mbed_official	324:406fd2029f23	811	#define HW_PDB_CHnS_WR(x, n, v) (HW_PDB_CHnS(x, n).U = (v))
mbed_official	324:406fd2029f23	812	#define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	813	#define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	814	#define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	815	/@}/
mbed_official	324:406fd2029f23	816
mbed_official	324:406fd2029f23	817	/*
mbed_official	324:406fd2029f23	818	* Constants & macros for individual PDB_CHnS bitfields
mbed_official	324:406fd2029f23	819	*/
mbed_official	324:406fd2029f23	820
mbed_official	324:406fd2029f23	821	/*!
mbed_official	324:406fd2029f23	822	* @name Register PDB_CHnS, field ERR[7:0] (RW)
mbed_official	324:406fd2029f23	823	*
mbed_official	324:406fd2029f23	824	* Only the lower M bits are implemented in this MCU.
mbed_official	324:406fd2029f23	825	*
mbed_official	324:406fd2029f23	826	* Values:
mbed_official	324:406fd2029f23	827	* - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
mbed_official	324:406fd2029f23	828	* - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
mbed_official	324:406fd2029f23	829	* ADCn block can be triggered for a conversion by one pre-trigger from PDB
mbed_official	324:406fd2029f23	830	* channel n. When one conversion, which is triggered by one of the pre-triggers
mbed_official	324:406fd2029f23	831	* from PDB channel n, is in progress, new trigger from PDB channel's
mbed_official	324:406fd2029f23	832	* corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
mbed_official	324:406fd2029f23	833	* Writing 0's to clear the sequence error flags.
mbed_official	324:406fd2029f23	834	*/
mbed_official	324:406fd2029f23	835	/@{/
mbed_official	324:406fd2029f23	836	#define BP_PDB_CHnS_ERR (0U) /!< Bit position for PDB_CHnS_ERR. /
mbed_official	324:406fd2029f23	837	#define BM_PDB_CHnS_ERR (0x000000FFU) /!< Bit mask for PDB_CHnS_ERR. /
mbed_official	324:406fd2029f23	838	#define BS_PDB_CHnS_ERR (8U) /!< Bit field size in bits for PDB_CHnS_ERR. /
mbed_official	324:406fd2029f23	839
mbed_official	324:406fd2029f23	840	/! @brief Read current value of the PDB_CHnS_ERR field. /
mbed_official	324:406fd2029f23	841	#define BR_PDB_CHnS_ERR(x, n) (HW_PDB_CHnS(x, n).B.ERR)
mbed_official	324:406fd2029f23	842
mbed_official	324:406fd2029f23	843	/! @brief Format value for bitfield PDB_CHnS_ERR. /
mbed_official	324:406fd2029f23	844	#define BF_PDB_CHnS_ERR(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
mbed_official	324:406fd2029f23	845
mbed_official	324:406fd2029f23	846	/! @brief Set the ERR field to a new value. /
mbed_official	324:406fd2029f23	847	#define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) \| BF_PDB_CHnS_ERR(v)))
mbed_official	324:406fd2029f23	848	/@}/
mbed_official	324:406fd2029f23	849
mbed_official	324:406fd2029f23	850	/*!
mbed_official	324:406fd2029f23	851	* @name Register PDB_CHnS, field CF[23:16] (RW)
mbed_official	324:406fd2029f23	852	*
mbed_official	324:406fd2029f23	853	* The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
mbed_official	324:406fd2029f23	854	* clear these bits.
mbed_official	324:406fd2029f23	855	*/
mbed_official	324:406fd2029f23	856	/@{/
mbed_official	324:406fd2029f23	857	#define BP_PDB_CHnS_CF (16U) /!< Bit position for PDB_CHnS_CF. /
mbed_official	324:406fd2029f23	858	#define BM_PDB_CHnS_CF (0x00FF0000U) /!< Bit mask for PDB_CHnS_CF. /
mbed_official	324:406fd2029f23	859	#define BS_PDB_CHnS_CF (8U) /!< Bit field size in bits for PDB_CHnS_CF. /
mbed_official	324:406fd2029f23	860
mbed_official	324:406fd2029f23	861	/! @brief Read current value of the PDB_CHnS_CF field. /
mbed_official	324:406fd2029f23	862	#define BR_PDB_CHnS_CF(x, n) (HW_PDB_CHnS(x, n).B.CF)
mbed_official	324:406fd2029f23	863
mbed_official	324:406fd2029f23	864	/! @brief Format value for bitfield PDB_CHnS_CF. /
mbed_official	324:406fd2029f23	865	#define BF_PDB_CHnS_CF(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
mbed_official	324:406fd2029f23	866
mbed_official	324:406fd2029f23	867	/! @brief Set the CF field to a new value. /
mbed_official	324:406fd2029f23	868	#define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) \| BF_PDB_CHnS_CF(v)))
mbed_official	324:406fd2029f23	869	/@}/
mbed_official	324:406fd2029f23	870	/*******************************************************************************
mbed_official	324:406fd2029f23	871	* HW_PDB_CHnDLY0 - Channel n Delay 0 register
mbed_official	324:406fd2029f23	872	******************************************************************************/
mbed_official	324:406fd2029f23	873
mbed_official	324:406fd2029f23	874	/*!
mbed_official	324:406fd2029f23	875	* @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
mbed_official	324:406fd2029f23	876	*
mbed_official	324:406fd2029f23	877	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	878	*/
mbed_official	324:406fd2029f23	879	typedef union _hw_pdb_chndly0
mbed_official	324:406fd2029f23	880	{
mbed_official	324:406fd2029f23	881	uint32_t U;
mbed_official	324:406fd2029f23	882	struct _hw_pdb_chndly0_bitfields
mbed_official	324:406fd2029f23	883	{
mbed_official	324:406fd2029f23	884	uint32_t DLY : 16; /!< [15:0] PDB Channel Delay /
mbed_official	324:406fd2029f23	885	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	886	} B;
mbed_official	324:406fd2029f23	887	} hw_pdb_chndly0_t;
mbed_official	324:406fd2029f23	888
mbed_official	324:406fd2029f23	889	/*!
mbed_official	324:406fd2029f23	890	* @name Constants and macros for entire PDB_CHnDLY0 register
mbed_official	324:406fd2029f23	891	*/
mbed_official	324:406fd2029f23	892	/@{/
mbed_official	324:406fd2029f23	893	#define HW_PDB_CHnDLY0_COUNT (2U)
mbed_official	324:406fd2029f23	894
mbed_official	324:406fd2029f23	895	#define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
mbed_official	324:406fd2029f23	896
mbed_official	324:406fd2029f23	897	#define HW_PDB_CHnDLY0(x, n) ((__IO hw_pdb_chndly0_t ) HW_PDB_CHnDLY0_ADDR(x, n))
mbed_official	324:406fd2029f23	898	#define HW_PDB_CHnDLY0_RD(x, n) (HW_PDB_CHnDLY0(x, n).U)
mbed_official	324:406fd2029f23	899	#define HW_PDB_CHnDLY0_WR(x, n, v) (HW_PDB_CHnDLY0(x, n).U = (v))
mbed_official	324:406fd2029f23	900	#define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	901	#define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	902	#define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	903	/@}/
mbed_official	324:406fd2029f23	904
mbed_official	324:406fd2029f23	905	/*
mbed_official	324:406fd2029f23	906	* Constants & macros for individual PDB_CHnDLY0 bitfields
mbed_official	324:406fd2029f23	907	*/
mbed_official	324:406fd2029f23	908
mbed_official	324:406fd2029f23	909	/*!
mbed_official	324:406fd2029f23	910	* @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
mbed_official	324:406fd2029f23	911	*
mbed_official	324:406fd2029f23	912	* Specifies the delay value for the channel's corresponding pre-trigger. The
mbed_official	324:406fd2029f23	913	* pre-trigger asserts when the counter is equal to DLY. Reading this field returns
mbed_official	324:406fd2029f23	914	* the value of internal register that is effective for the current PDB cycle.
mbed_official	324:406fd2029f23	915	*/
mbed_official	324:406fd2029f23	916	/@{/
mbed_official	324:406fd2029f23	917	#define BP_PDB_CHnDLY0_DLY (0U) /!< Bit position for PDB_CHnDLY0_DLY. /
mbed_official	324:406fd2029f23	918	#define BM_PDB_CHnDLY0_DLY (0x0000FFFFU) /!< Bit mask for PDB_CHnDLY0_DLY. /
mbed_official	324:406fd2029f23	919	#define BS_PDB_CHnDLY0_DLY (16U) /!< Bit field size in bits for PDB_CHnDLY0_DLY. /
mbed_official	324:406fd2029f23	920
mbed_official	324:406fd2029f23	921	/! @brief Read current value of the PDB_CHnDLY0_DLY field. /
mbed_official	324:406fd2029f23	922	#define BR_PDB_CHnDLY0_DLY(x, n) (HW_PDB_CHnDLY0(x, n).B.DLY)
mbed_official	324:406fd2029f23	923
mbed_official	324:406fd2029f23	924	/! @brief Format value for bitfield PDB_CHnDLY0_DLY. /
mbed_official	324:406fd2029f23	925	#define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
mbed_official	324:406fd2029f23	926
mbed_official	324:406fd2029f23	927	/! @brief Set the DLY field to a new value. /
mbed_official	324:406fd2029f23	928	#define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) \| BF_PDB_CHnDLY0_DLY(v)))
mbed_official	324:406fd2029f23	929	/@}/
mbed_official	324:406fd2029f23	930	/*******************************************************************************
mbed_official	324:406fd2029f23	931	* HW_PDB_CHnDLY1 - Channel n Delay 1 register
mbed_official	324:406fd2029f23	932	******************************************************************************/
mbed_official	324:406fd2029f23	933
mbed_official	324:406fd2029f23	934	/*!
mbed_official	324:406fd2029f23	935	* @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
mbed_official	324:406fd2029f23	936	*
mbed_official	324:406fd2029f23	937	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	938	*/
mbed_official	324:406fd2029f23	939	typedef union _hw_pdb_chndly1
mbed_official	324:406fd2029f23	940	{
mbed_official	324:406fd2029f23	941	uint32_t U;
mbed_official	324:406fd2029f23	942	struct _hw_pdb_chndly1_bitfields
mbed_official	324:406fd2029f23	943	{
mbed_official	324:406fd2029f23	944	uint32_t DLY : 16; /!< [15:0] PDB Channel Delay /
mbed_official	324:406fd2029f23	945	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	946	} B;
mbed_official	324:406fd2029f23	947	} hw_pdb_chndly1_t;
mbed_official	324:406fd2029f23	948
mbed_official	324:406fd2029f23	949	/*!
mbed_official	324:406fd2029f23	950	* @name Constants and macros for entire PDB_CHnDLY1 register
mbed_official	324:406fd2029f23	951	*/
mbed_official	324:406fd2029f23	952	/@{/
mbed_official	324:406fd2029f23	953	#define HW_PDB_CHnDLY1_COUNT (2U)
mbed_official	324:406fd2029f23	954
mbed_official	324:406fd2029f23	955	#define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
mbed_official	324:406fd2029f23	956
mbed_official	324:406fd2029f23	957	#define HW_PDB_CHnDLY1(x, n) ((__IO hw_pdb_chndly1_t ) HW_PDB_CHnDLY1_ADDR(x, n))
mbed_official	324:406fd2029f23	958	#define HW_PDB_CHnDLY1_RD(x, n) (HW_PDB_CHnDLY1(x, n).U)
mbed_official	324:406fd2029f23	959	#define HW_PDB_CHnDLY1_WR(x, n, v) (HW_PDB_CHnDLY1(x, n).U = (v))
mbed_official	324:406fd2029f23	960	#define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	961	#define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	962	#define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	963	/@}/
mbed_official	324:406fd2029f23	964
mbed_official	324:406fd2029f23	965	/*
mbed_official	324:406fd2029f23	966	* Constants & macros for individual PDB_CHnDLY1 bitfields
mbed_official	324:406fd2029f23	967	*/
mbed_official	324:406fd2029f23	968
mbed_official	324:406fd2029f23	969	/*!
mbed_official	324:406fd2029f23	970	* @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
mbed_official	324:406fd2029f23	971	*
mbed_official	324:406fd2029f23	972	* These bits specify the delay value for the channel's corresponding
mbed_official	324:406fd2029f23	973	* pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
mbed_official	324:406fd2029f23	974	* bits returns the value of internal register that is effective for the current PDB
mbed_official	324:406fd2029f23	975	* cycle.
mbed_official	324:406fd2029f23	976	*/
mbed_official	324:406fd2029f23	977	/@{/
mbed_official	324:406fd2029f23	978	#define BP_PDB_CHnDLY1_DLY (0U) /!< Bit position for PDB_CHnDLY1_DLY. /
mbed_official	324:406fd2029f23	979	#define BM_PDB_CHnDLY1_DLY (0x0000FFFFU) /!< Bit mask for PDB_CHnDLY1_DLY. /
mbed_official	324:406fd2029f23	980	#define BS_PDB_CHnDLY1_DLY (16U) /!< Bit field size in bits for PDB_CHnDLY1_DLY. /
mbed_official	324:406fd2029f23	981
mbed_official	324:406fd2029f23	982	/! @brief Read current value of the PDB_CHnDLY1_DLY field. /
mbed_official	324:406fd2029f23	983	#define BR_PDB_CHnDLY1_DLY(x, n) (HW_PDB_CHnDLY1(x, n).B.DLY)
mbed_official	324:406fd2029f23	984
mbed_official	324:406fd2029f23	985	/! @brief Format value for bitfield PDB_CHnDLY1_DLY. /
mbed_official	324:406fd2029f23	986	#define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
mbed_official	324:406fd2029f23	987
mbed_official	324:406fd2029f23	988	/! @brief Set the DLY field to a new value. /
mbed_official	324:406fd2029f23	989	#define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) \| BF_PDB_CHnDLY1_DLY(v)))
mbed_official	324:406fd2029f23	990	/@}/
mbed_official	324:406fd2029f23	991
mbed_official	324:406fd2029f23	992	/*******************************************************************************
mbed_official	324:406fd2029f23	993	* HW_PDB_DACINTCn - DAC Interval Trigger n Control register
mbed_official	324:406fd2029f23	994	******************************************************************************/
mbed_official	324:406fd2029f23	995
mbed_official	324:406fd2029f23	996	/*!
mbed_official	324:406fd2029f23	997	* @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
mbed_official	324:406fd2029f23	998	*
mbed_official	324:406fd2029f23	999	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1000	*/
mbed_official	324:406fd2029f23	1001	typedef union _hw_pdb_dacintcn
mbed_official	324:406fd2029f23	1002	{
mbed_official	324:406fd2029f23	1003	uint32_t U;
mbed_official	324:406fd2029f23	1004	struct _hw_pdb_dacintcn_bitfields
mbed_official	324:406fd2029f23	1005	{
mbed_official	324:406fd2029f23	1006	uint32_t TOE : 1; /!< [0] DAC Interval Trigger Enable /
mbed_official	324:406fd2029f23	1007	uint32_t EXT : 1; /!< [1] DAC External Trigger Input Enable /
mbed_official	324:406fd2029f23	1008	uint32_t RESERVED0 : 30; /!< [31:2] /
mbed_official	324:406fd2029f23	1009	} B;
mbed_official	324:406fd2029f23	1010	} hw_pdb_dacintcn_t;
mbed_official	324:406fd2029f23	1011
mbed_official	324:406fd2029f23	1012	/*!
mbed_official	324:406fd2029f23	1013	* @name Constants and macros for entire PDB_DACINTCn register
mbed_official	324:406fd2029f23	1014	*/
mbed_official	324:406fd2029f23	1015	/@{/
mbed_official	324:406fd2029f23	1016	#define HW_PDB_DACINTCn_COUNT (2U)
mbed_official	324:406fd2029f23	1017
mbed_official	324:406fd2029f23	1018	#define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
mbed_official	324:406fd2029f23	1019
mbed_official	324:406fd2029f23	1020	#define HW_PDB_DACINTCn(x, n) ((__IO hw_pdb_dacintcn_t ) HW_PDB_DACINTCn_ADDR(x, n))
mbed_official	324:406fd2029f23	1021	#define HW_PDB_DACINTCn_RD(x, n) (HW_PDB_DACINTCn(x, n).U)
mbed_official	324:406fd2029f23	1022	#define HW_PDB_DACINTCn_WR(x, n, v) (HW_PDB_DACINTCn(x, n).U = (v))
mbed_official	324:406fd2029f23	1023	#define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	1024	#define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	1025	#define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	1026	/@}/
mbed_official	324:406fd2029f23	1027
mbed_official	324:406fd2029f23	1028	/*
mbed_official	324:406fd2029f23	1029	* Constants & macros for individual PDB_DACINTCn bitfields
mbed_official	324:406fd2029f23	1030	*/
mbed_official	324:406fd2029f23	1031
mbed_official	324:406fd2029f23	1032	/*!
mbed_official	324:406fd2029f23	1033	* @name Register PDB_DACINTCn, field TOE[0] (RW)
mbed_official	324:406fd2029f23	1034	*
mbed_official	324:406fd2029f23	1035	* This bit enables the DAC interval trigger.
mbed_official	324:406fd2029f23	1036	*
mbed_official	324:406fd2029f23	1037	* Values:
mbed_official	324:406fd2029f23	1038	* - 0 - DAC interval trigger disabled.
mbed_official	324:406fd2029f23	1039	* - 1 - DAC interval trigger enabled.
mbed_official	324:406fd2029f23	1040	*/
mbed_official	324:406fd2029f23	1041	/@{/
mbed_official	324:406fd2029f23	1042	#define BP_PDB_DACINTCn_TOE (0U) /!< Bit position for PDB_DACINTCn_TOE. /
mbed_official	324:406fd2029f23	1043	#define BM_PDB_DACINTCn_TOE (0x00000001U) /!< Bit mask for PDB_DACINTCn_TOE. /
mbed_official	324:406fd2029f23	1044	#define BS_PDB_DACINTCn_TOE (1U) /!< Bit field size in bits for PDB_DACINTCn_TOE. /
mbed_official	324:406fd2029f23	1045
mbed_official	324:406fd2029f23	1046	/! @brief Read current value of the PDB_DACINTCn_TOE field. /
mbed_official	324:406fd2029f23	1047	#define BR_PDB_DACINTCn_TOE(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE))
mbed_official	324:406fd2029f23	1048
mbed_official	324:406fd2029f23	1049	/! @brief Format value for bitfield PDB_DACINTCn_TOE. /
mbed_official	324:406fd2029f23	1050	#define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
mbed_official	324:406fd2029f23	1051
mbed_official	324:406fd2029f23	1052	/! @brief Set the TOE field to a new value. /
mbed_official	324:406fd2029f23	1053	#define BW_PDB_DACINTCn_TOE(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE) = (v))
mbed_official	324:406fd2029f23	1054	/@}/
mbed_official	324:406fd2029f23	1055
mbed_official	324:406fd2029f23	1056	/*!
mbed_official	324:406fd2029f23	1057	* @name Register PDB_DACINTCn, field EXT[1] (RW)
mbed_official	324:406fd2029f23	1058	*
mbed_official	324:406fd2029f23	1059	* Enables the external trigger for DAC interval counter.
mbed_official	324:406fd2029f23	1060	*
mbed_official	324:406fd2029f23	1061	* Values:
mbed_official	324:406fd2029f23	1062	* - 0 - DAC external trigger input disabled. DAC interval counter is reset and
mbed_official	324:406fd2029f23	1063	* counting starts when a rising edge is detected on selected trigger input
mbed_official	324:406fd2029f23	1064	* source or software trigger is selected and SWTRIG is written with 1.
mbed_official	324:406fd2029f23	1065	* - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
mbed_official	324:406fd2029f23	1066	* and DAC external trigger input triggers the DAC interval trigger.
mbed_official	324:406fd2029f23	1067	*/
mbed_official	324:406fd2029f23	1068	/@{/
mbed_official	324:406fd2029f23	1069	#define BP_PDB_DACINTCn_EXT (1U) /!< Bit position for PDB_DACINTCn_EXT. /
mbed_official	324:406fd2029f23	1070	#define BM_PDB_DACINTCn_EXT (0x00000002U) /!< Bit mask for PDB_DACINTCn_EXT. /
mbed_official	324:406fd2029f23	1071	#define BS_PDB_DACINTCn_EXT (1U) /!< Bit field size in bits for PDB_DACINTCn_EXT. /
mbed_official	324:406fd2029f23	1072
mbed_official	324:406fd2029f23	1073	/! @brief Read current value of the PDB_DACINTCn_EXT field. /
mbed_official	324:406fd2029f23	1074	#define BR_PDB_DACINTCn_EXT(x, n) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT))
mbed_official	324:406fd2029f23	1075
mbed_official	324:406fd2029f23	1076	/! @brief Format value for bitfield PDB_DACINTCn_EXT. /
mbed_official	324:406fd2029f23	1077	#define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
mbed_official	324:406fd2029f23	1078
mbed_official	324:406fd2029f23	1079	/! @brief Set the EXT field to a new value. /
mbed_official	324:406fd2029f23	1080	#define BW_PDB_DACINTCn_EXT(x, n, v) (BITBAND_ACCESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT) = (v))
mbed_official	324:406fd2029f23	1081	/@}/
mbed_official	324:406fd2029f23	1082	/*******************************************************************************
mbed_official	324:406fd2029f23	1083	* HW_PDB_DACINTn - DAC Interval n register
mbed_official	324:406fd2029f23	1084	******************************************************************************/
mbed_official	324:406fd2029f23	1085
mbed_official	324:406fd2029f23	1086	/*!
mbed_official	324:406fd2029f23	1087	* @brief HW_PDB_DACINTn - DAC Interval n register (RW)
mbed_official	324:406fd2029f23	1088	*
mbed_official	324:406fd2029f23	1089	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1090	*/
mbed_official	324:406fd2029f23	1091	typedef union _hw_pdb_dacintn
mbed_official	324:406fd2029f23	1092	{
mbed_official	324:406fd2029f23	1093	uint32_t U;
mbed_official	324:406fd2029f23	1094	struct _hw_pdb_dacintn_bitfields
mbed_official	324:406fd2029f23	1095	{
mbed_official	324:406fd2029f23	1096	uint32_t INT : 16; /!< [15:0] DAC Interval /
mbed_official	324:406fd2029f23	1097	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	1098	} B;
mbed_official	324:406fd2029f23	1099	} hw_pdb_dacintn_t;
mbed_official	324:406fd2029f23	1100
mbed_official	324:406fd2029f23	1101	/*!
mbed_official	324:406fd2029f23	1102	* @name Constants and macros for entire PDB_DACINTn register
mbed_official	324:406fd2029f23	1103	*/
mbed_official	324:406fd2029f23	1104	/@{/
mbed_official	324:406fd2029f23	1105	#define HW_PDB_DACINTn_COUNT (2U)
mbed_official	324:406fd2029f23	1106
mbed_official	324:406fd2029f23	1107	#define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
mbed_official	324:406fd2029f23	1108
mbed_official	324:406fd2029f23	1109	#define HW_PDB_DACINTn(x, n) ((__IO hw_pdb_dacintn_t ) HW_PDB_DACINTn_ADDR(x, n))
mbed_official	324:406fd2029f23	1110	#define HW_PDB_DACINTn_RD(x, n) (HW_PDB_DACINTn(x, n).U)
mbed_official	324:406fd2029f23	1111	#define HW_PDB_DACINTn_WR(x, n, v) (HW_PDB_DACINTn(x, n).U = (v))
mbed_official	324:406fd2029f23	1112	#define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	1113	#define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	1114	#define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	1115	/@}/
mbed_official	324:406fd2029f23	1116
mbed_official	324:406fd2029f23	1117	/*
mbed_official	324:406fd2029f23	1118	* Constants & macros for individual PDB_DACINTn bitfields
mbed_official	324:406fd2029f23	1119	*/
mbed_official	324:406fd2029f23	1120
mbed_official	324:406fd2029f23	1121	/*!
mbed_official	324:406fd2029f23	1122	* @name Register PDB_DACINTn, field INT[15:0] (RW)
mbed_official	324:406fd2029f23	1123	*
mbed_official	324:406fd2029f23	1124	* Specifies the interval value for DAC interval trigger. DAC interval trigger
mbed_official	324:406fd2029f23	1125	* triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
mbed_official	324:406fd2029f23	1126	* Reading this field returns the value of internal register that is effective
mbed_official	324:406fd2029f23	1127	* for the current PDB cycle.
mbed_official	324:406fd2029f23	1128	*/
mbed_official	324:406fd2029f23	1129	/@{/
mbed_official	324:406fd2029f23	1130	#define BP_PDB_DACINTn_INT (0U) /!< Bit position for PDB_DACINTn_INT. /
mbed_official	324:406fd2029f23	1131	#define BM_PDB_DACINTn_INT (0x0000FFFFU) /!< Bit mask for PDB_DACINTn_INT. /
mbed_official	324:406fd2029f23	1132	#define BS_PDB_DACINTn_INT (16U) /!< Bit field size in bits for PDB_DACINTn_INT. /
mbed_official	324:406fd2029f23	1133
mbed_official	324:406fd2029f23	1134	/! @brief Read current value of the PDB_DACINTn_INT field. /
mbed_official	324:406fd2029f23	1135	#define BR_PDB_DACINTn_INT(x, n) (HW_PDB_DACINTn(x, n).B.INT)
mbed_official	324:406fd2029f23	1136
mbed_official	324:406fd2029f23	1137	/! @brief Format value for bitfield PDB_DACINTn_INT. /
mbed_official	324:406fd2029f23	1138	#define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
mbed_official	324:406fd2029f23	1139
mbed_official	324:406fd2029f23	1140	/! @brief Set the INT field to a new value. /
mbed_official	324:406fd2029f23	1141	#define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) \| BF_PDB_DACINTn_INT(v)))
mbed_official	324:406fd2029f23	1142	/@}/
mbed_official	324:406fd2029f23	1143
mbed_official	324:406fd2029f23	1144	/*******************************************************************************
mbed_official	324:406fd2029f23	1145	* HW_PDB_POEN - Pulse-Out n Enable register
mbed_official	324:406fd2029f23	1146	******************************************************************************/
mbed_official	324:406fd2029f23	1147
mbed_official	324:406fd2029f23	1148	/*!
mbed_official	324:406fd2029f23	1149	* @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
mbed_official	324:406fd2029f23	1150	*
mbed_official	324:406fd2029f23	1151	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1152	*/
mbed_official	324:406fd2029f23	1153	typedef union _hw_pdb_poen
mbed_official	324:406fd2029f23	1154	{
mbed_official	324:406fd2029f23	1155	uint32_t U;
mbed_official	324:406fd2029f23	1156	struct _hw_pdb_poen_bitfields
mbed_official	324:406fd2029f23	1157	{
mbed_official	324:406fd2029f23	1158	uint32_t POEN : 8; /!< [7:0] PDB Pulse-Out Enable /
mbed_official	324:406fd2029f23	1159	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1160	} B;
mbed_official	324:406fd2029f23	1161	} hw_pdb_poen_t;
mbed_official	324:406fd2029f23	1162
mbed_official	324:406fd2029f23	1163	/*!
mbed_official	324:406fd2029f23	1164	* @name Constants and macros for entire PDB_POEN register
mbed_official	324:406fd2029f23	1165	*/
mbed_official	324:406fd2029f23	1166	/@{/
mbed_official	324:406fd2029f23	1167	#define HW_PDB_POEN_ADDR(x) ((x) + 0x190U)
mbed_official	324:406fd2029f23	1168
mbed_official	324:406fd2029f23	1169	#define HW_PDB_POEN(x) ((__IO hw_pdb_poen_t ) HW_PDB_POEN_ADDR(x))
mbed_official	324:406fd2029f23	1170	#define HW_PDB_POEN_RD(x) (HW_PDB_POEN(x).U)
mbed_official	324:406fd2029f23	1171	#define HW_PDB_POEN_WR(x, v) (HW_PDB_POEN(x).U = (v))
mbed_official	324:406fd2029f23	1172	#define HW_PDB_POEN_SET(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1173	#define HW_PDB_POEN_CLR(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1174	#define HW_PDB_POEN_TOG(x, v) (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1175	/@}/
mbed_official	324:406fd2029f23	1176
mbed_official	324:406fd2029f23	1177	/*
mbed_official	324:406fd2029f23	1178	* Constants & macros for individual PDB_POEN bitfields
mbed_official	324:406fd2029f23	1179	*/
mbed_official	324:406fd2029f23	1180
mbed_official	324:406fd2029f23	1181	/*!
mbed_official	324:406fd2029f23	1182	* @name Register PDB_POEN, field POEN[7:0] (RW)
mbed_official	324:406fd2029f23	1183	*
mbed_official	324:406fd2029f23	1184	* Enables the pulse output. Only lower Y bits are implemented in this MCU.
mbed_official	324:406fd2029f23	1185	*
mbed_official	324:406fd2029f23	1186	* Values:
mbed_official	324:406fd2029f23	1187	* - 0 - PDB Pulse-Out disabled
mbed_official	324:406fd2029f23	1188	* - 1 - PDB Pulse-Out enabled
mbed_official	324:406fd2029f23	1189	*/
mbed_official	324:406fd2029f23	1190	/@{/
mbed_official	324:406fd2029f23	1191	#define BP_PDB_POEN_POEN (0U) /!< Bit position for PDB_POEN_POEN. /
mbed_official	324:406fd2029f23	1192	#define BM_PDB_POEN_POEN (0x000000FFU) /!< Bit mask for PDB_POEN_POEN. /
mbed_official	324:406fd2029f23	1193	#define BS_PDB_POEN_POEN (8U) /!< Bit field size in bits for PDB_POEN_POEN. /
mbed_official	324:406fd2029f23	1194
mbed_official	324:406fd2029f23	1195	/! @brief Read current value of the PDB_POEN_POEN field. /
mbed_official	324:406fd2029f23	1196	#define BR_PDB_POEN_POEN(x) (HW_PDB_POEN(x).B.POEN)
mbed_official	324:406fd2029f23	1197
mbed_official	324:406fd2029f23	1198	/! @brief Format value for bitfield PDB_POEN_POEN. /
mbed_official	324:406fd2029f23	1199	#define BF_PDB_POEN_POEN(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
mbed_official	324:406fd2029f23	1200
mbed_official	324:406fd2029f23	1201	/! @brief Set the POEN field to a new value. /
mbed_official	324:406fd2029f23	1202	#define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) \| BF_PDB_POEN_POEN(v)))
mbed_official	324:406fd2029f23	1203	/@}/
mbed_official	324:406fd2029f23	1204
mbed_official	324:406fd2029f23	1205	/*******************************************************************************
mbed_official	324:406fd2029f23	1206	* HW_PDB_POnDLY - Pulse-Out n Delay register
mbed_official	324:406fd2029f23	1207	******************************************************************************/
mbed_official	324:406fd2029f23	1208
mbed_official	324:406fd2029f23	1209	/*!
mbed_official	324:406fd2029f23	1210	* @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
mbed_official	324:406fd2029f23	1211	*
mbed_official	324:406fd2029f23	1212	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1213	*/
mbed_official	324:406fd2029f23	1214	typedef union _hw_pdb_pondly
mbed_official	324:406fd2029f23	1215	{
mbed_official	324:406fd2029f23	1216	uint32_t U;
mbed_official	324:406fd2029f23	1217	struct _hw_pdb_pondly_bitfields
mbed_official	324:406fd2029f23	1218	{
mbed_official	324:406fd2029f23	1219	uint32_t DLY2 : 16; /!< [15:0] PDB Pulse-Out Delay 2 /
mbed_official	324:406fd2029f23	1220	uint32_t DLY1 : 16; /!< [31:16] PDB Pulse-Out Delay 1 /
mbed_official	324:406fd2029f23	1221	} B;
mbed_official	324:406fd2029f23	1222	} hw_pdb_pondly_t;
mbed_official	324:406fd2029f23	1223
mbed_official	324:406fd2029f23	1224	/*!
mbed_official	324:406fd2029f23	1225	* @name Constants and macros for entire PDB_POnDLY register
mbed_official	324:406fd2029f23	1226	*/
mbed_official	324:406fd2029f23	1227	/@{/
mbed_official	324:406fd2029f23	1228	#define HW_PDB_POnDLY_COUNT (2U)
mbed_official	324:406fd2029f23	1229
mbed_official	324:406fd2029f23	1230	#define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
mbed_official	324:406fd2029f23	1231
mbed_official	324:406fd2029f23	1232	#define HW_PDB_POnDLY(x, n) ((__IO hw_pdb_pondly_t ) HW_PDB_POnDLY_ADDR(x, n))
mbed_official	324:406fd2029f23	1233	#define HW_PDB_POnDLY_RD(x, n) (HW_PDB_POnDLY(x, n).U)
mbed_official	324:406fd2029f23	1234	#define HW_PDB_POnDLY_WR(x, n, v) (HW_PDB_POnDLY(x, n).U = (v))
mbed_official	324:406fd2029f23	1235	#define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	1236	#define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	1237	#define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	1238	/@}/
mbed_official	324:406fd2029f23	1239
mbed_official	324:406fd2029f23	1240	/*
mbed_official	324:406fd2029f23	1241	* Constants & macros for individual PDB_POnDLY bitfields
mbed_official	324:406fd2029f23	1242	*/
mbed_official	324:406fd2029f23	1243
mbed_official	324:406fd2029f23	1244	/*!
mbed_official	324:406fd2029f23	1245	* @name Register PDB_POnDLY, field DLY2[15:0] (RW)
mbed_official	324:406fd2029f23	1246	*
mbed_official	324:406fd2029f23	1247	* Specifies the delay 2 value for the PDB Pulse-Out. Pulse-Out goes low when
mbed_official	324:406fd2029f23	1248	* the PDB counter is equal to the DLY2. Reading this field returns the value of
mbed_official	324:406fd2029f23	1249	* internal register that is effective for the current PDB cycle.
mbed_official	324:406fd2029f23	1250	*/
mbed_official	324:406fd2029f23	1251	/@{/
mbed_official	324:406fd2029f23	1252	#define BP_PDB_POnDLY_DLY2 (0U) /!< Bit position for PDB_POnDLY_DLY2. /
mbed_official	324:406fd2029f23	1253	#define BM_PDB_POnDLY_DLY2 (0x0000FFFFU) /!< Bit mask for PDB_POnDLY_DLY2. /
mbed_official	324:406fd2029f23	1254	#define BS_PDB_POnDLY_DLY2 (16U) /!< Bit field size in bits for PDB_POnDLY_DLY2. /
mbed_official	324:406fd2029f23	1255
mbed_official	324:406fd2029f23	1256	/! @brief Read current value of the PDB_POnDLY_DLY2 field. /
mbed_official	324:406fd2029f23	1257	#define BR_PDB_POnDLY_DLY2(x, n) (HW_PDB_POnDLY(x, n).B.DLY2)
mbed_official	324:406fd2029f23	1258
mbed_official	324:406fd2029f23	1259	/! @brief Format value for bitfield PDB_POnDLY_DLY2. /
mbed_official	324:406fd2029f23	1260	#define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
mbed_official	324:406fd2029f23	1261
mbed_official	324:406fd2029f23	1262	/! @brief Set the DLY2 field to a new value. /
mbed_official	324:406fd2029f23	1263	#define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) \| BF_PDB_POnDLY_DLY2(v)))
mbed_official	324:406fd2029f23	1264	/@}/
mbed_official	324:406fd2029f23	1265
mbed_official	324:406fd2029f23	1266	/*!
mbed_official	324:406fd2029f23	1267	* @name Register PDB_POnDLY, field DLY1[31:16] (RW)
mbed_official	324:406fd2029f23	1268	*
mbed_official	324:406fd2029f23	1269	* Specifies the delay 1 value for the PDB Pulse-Out. Pulse-Out goes high when
mbed_official	324:406fd2029f23	1270	* the PDB counter is equal to the DLY1. Reading this field returns the value of
mbed_official	324:406fd2029f23	1271	* internal register that is effective for the current PDB cycle.
mbed_official	324:406fd2029f23	1272	*/
mbed_official	324:406fd2029f23	1273	/@{/
mbed_official	324:406fd2029f23	1274	#define BP_PDB_POnDLY_DLY1 (16U) /!< Bit position for PDB_POnDLY_DLY1. /
mbed_official	324:406fd2029f23	1275	#define BM_PDB_POnDLY_DLY1 (0xFFFF0000U) /!< Bit mask for PDB_POnDLY_DLY1. /
mbed_official	324:406fd2029f23	1276	#define BS_PDB_POnDLY_DLY1 (16U) /!< Bit field size in bits for PDB_POnDLY_DLY1. /
mbed_official	324:406fd2029f23	1277
mbed_official	324:406fd2029f23	1278	/! @brief Read current value of the PDB_POnDLY_DLY1 field. /
mbed_official	324:406fd2029f23	1279	#define BR_PDB_POnDLY_DLY1(x, n) (HW_PDB_POnDLY(x, n).B.DLY1)
mbed_official	324:406fd2029f23	1280
mbed_official	324:406fd2029f23	1281	/! @brief Format value for bitfield PDB_POnDLY_DLY1. /
mbed_official	324:406fd2029f23	1282	#define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
mbed_official	324:406fd2029f23	1283
mbed_official	324:406fd2029f23	1284	/! @brief Set the DLY1 field to a new value. /
mbed_official	324:406fd2029f23	1285	#define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) \| BF_PDB_POnDLY_DLY1(v)))
mbed_official	324:406fd2029f23	1286	/@}/
mbed_official	324:406fd2029f23	1287
mbed_official	324:406fd2029f23	1288	/*******************************************************************************
mbed_official	324:406fd2029f23	1289	* hw_pdb_t - module struct
mbed_official	324:406fd2029f23	1290	******************************************************************************/
mbed_official	324:406fd2029f23	1291	/*!
mbed_official	324:406fd2029f23	1292	* @brief All PDB module registers.
mbed_official	324:406fd2029f23	1293	*/
mbed_official	324:406fd2029f23	1294	#pragma pack(1)
mbed_official	324:406fd2029f23	1295	typedef struct _hw_pdb
mbed_official	324:406fd2029f23	1296	{
mbed_official	324:406fd2029f23	1297	__IO hw_pdb_sc_t SC; /!< [0x0] Status and Control register /
mbed_official	324:406fd2029f23	1298	__IO hw_pdb_mod_t MOD; /!< [0x4] Modulus register /
mbed_official	324:406fd2029f23	1299	__I hw_pdb_cnt_t CNT; /!< [0x8] Counter register /
mbed_official	324:406fd2029f23	1300	__IO hw_pdb_idly_t IDLY; /!< [0xC] Interrupt Delay register /
mbed_official	324:406fd2029f23	1301	struct {
mbed_official	324:406fd2029f23	1302	__IO hw_pdb_chnc1_t CHnC1; /!< [0x10] Channel n Control register 1 /
mbed_official	324:406fd2029f23	1303	__IO hw_pdb_chns_t CHnS; /!< [0x14] Channel n Status register /
mbed_official	324:406fd2029f23	1304	__IO hw_pdb_chndly0_t CHnDLY0; /!< [0x18] Channel n Delay 0 register /
mbed_official	324:406fd2029f23	1305	__IO hw_pdb_chndly1_t CHnDLY1; /!< [0x1C] Channel n Delay 1 register /
mbed_official	324:406fd2029f23	1306	uint8_t _reserved0[24];
mbed_official	324:406fd2029f23	1307	} CH[2];
mbed_official	324:406fd2029f23	1308	uint8_t _reserved0[240];
mbed_official	324:406fd2029f23	1309	struct {
mbed_official	324:406fd2029f23	1310	__IO hw_pdb_dacintcn_t DACINTCn; /!< [0x150] DAC Interval Trigger n Control register /
mbed_official	324:406fd2029f23	1311	__IO hw_pdb_dacintn_t DACINTn; /!< [0x154] DAC Interval n register /
mbed_official	324:406fd2029f23	1312	} DAC[2];
mbed_official	324:406fd2029f23	1313	uint8_t _reserved1[48];
mbed_official	324:406fd2029f23	1314	__IO hw_pdb_poen_t POEN; /!< [0x190] Pulse-Out n Enable register /
mbed_official	324:406fd2029f23	1315	__IO hw_pdb_pondly_t POnDLY[2]; /!< [0x194] Pulse-Out n Delay register /
mbed_official	324:406fd2029f23	1316	} hw_pdb_t;
mbed_official	324:406fd2029f23	1317	#pragma pack()
mbed_official	324:406fd2029f23	1318
mbed_official	324:406fd2029f23	1319	/! @brief Macro to access all PDB registers. /
mbed_official	324:406fd2029f23	1320	/! @param x PDB module instance base address. /
mbed_official	324:406fd2029f23	1321	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	1322	* use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
mbed_official	324:406fd2029f23	1323	#define HW_PDB(x) ((hw_pdb_t )(x))
mbed_official	324:406fd2029f23	1324
mbed_official	324:406fd2029f23	1325	#endif /* __HW_PDB_REGISTERS_H__ */
mbed_official	324:406fd2029f23	1326	/* EOF */

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Type:	Library
Created:	20 Nov 2012
Imports:	32253
Forks:	59
Commits:	636
Dependents:	278
Dependencies:	0
Followers:	872
Issues:	17

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The code in this repository is Apache licensed.

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_pdb.h@324:406fd2029f23, 2014-09-18 (annotated)

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