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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_mcm.h@324:406fd2029f23, 2014-09-18 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Sep 18 14:00:17 2014 +0100
- Revision:
- 324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5
Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/
Extended #476, which does not break ethernet for K64F
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 324:406fd2029f23 | 1 | /* |
| mbed_official | 324:406fd2029f23 | 2 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 3 | ** Compilers: Keil ARM C/C++ Compiler |
| mbed_official | 324:406fd2029f23 | 4 | ** Freescale C/C++ for Embedded ARM |
| mbed_official | 324:406fd2029f23 | 5 | ** GNU C Compiler |
| mbed_official | 324:406fd2029f23 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
| mbed_official | 324:406fd2029f23 | 7 | ** |
| mbed_official | 324:406fd2029f23 | 8 | ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014 |
| mbed_official | 324:406fd2029f23 | 9 | ** Version: rev. 2.5, 2014-05-06 |
| mbed_official | 324:406fd2029f23 | 10 | ** Build: b140604 |
| mbed_official | 324:406fd2029f23 | 11 | ** |
| mbed_official | 324:406fd2029f23 | 12 | ** Abstract: |
| mbed_official | 324:406fd2029f23 | 13 | ** Extension to the CMSIS register access layer header. |
| mbed_official | 324:406fd2029f23 | 14 | ** |
| mbed_official | 324:406fd2029f23 | 15 | ** Copyright (c) 2014 Freescale Semiconductor, Inc. |
| mbed_official | 324:406fd2029f23 | 16 | ** All rights reserved. |
| mbed_official | 324:406fd2029f23 | 17 | ** |
| mbed_official | 324:406fd2029f23 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 324:406fd2029f23 | 19 | ** are permitted provided that the following conditions are met: |
| mbed_official | 324:406fd2029f23 | 20 | ** |
| mbed_official | 324:406fd2029f23 | 21 | ** o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 324:406fd2029f23 | 22 | ** of conditions and the following disclaimer. |
| mbed_official | 324:406fd2029f23 | 23 | ** |
| mbed_official | 324:406fd2029f23 | 24 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 324:406fd2029f23 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 324:406fd2029f23 | 26 | ** other materials provided with the distribution. |
| mbed_official | 324:406fd2029f23 | 27 | ** |
| mbed_official | 324:406fd2029f23 | 28 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 324:406fd2029f23 | 29 | ** contributors may be used to endorse or promote products derived from this |
| mbed_official | 324:406fd2029f23 | 30 | ** software without specific prior written permission. |
| mbed_official | 324:406fd2029f23 | 31 | ** |
| mbed_official | 324:406fd2029f23 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 324:406fd2029f23 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 324:406fd2029f23 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 324:406fd2029f23 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 324:406fd2029f23 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 324:406fd2029f23 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 324:406fd2029f23 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 324:406fd2029f23 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 324:406fd2029f23 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 324:406fd2029f23 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 324:406fd2029f23 | 42 | ** |
| mbed_official | 324:406fd2029f23 | 43 | ** http: www.freescale.com |
| mbed_official | 324:406fd2029f23 | 44 | ** mail: support@freescale.com |
| mbed_official | 324:406fd2029f23 | 45 | ** |
| mbed_official | 324:406fd2029f23 | 46 | ** Revisions: |
| mbed_official | 324:406fd2029f23 | 47 | ** - rev. 1.0 (2013-07-23) |
| mbed_official | 324:406fd2029f23 | 48 | ** Initial version. |
| mbed_official | 324:406fd2029f23 | 49 | ** - rev. 1.1 (2013-09-17) |
| mbed_official | 324:406fd2029f23 | 50 | ** RM rev. 0.4 update. |
| mbed_official | 324:406fd2029f23 | 51 | ** - rev. 2.0 (2013-10-29) |
| mbed_official | 324:406fd2029f23 | 52 | ** Register accessor macros added to the memory map. |
| mbed_official | 324:406fd2029f23 | 53 | ** Symbols for Processor Expert memory map compatibility added to the memory map. |
| mbed_official | 324:406fd2029f23 | 54 | ** Startup file for gcc has been updated according to CMSIS 3.2. |
| mbed_official | 324:406fd2029f23 | 55 | ** System initialization updated. |
| mbed_official | 324:406fd2029f23 | 56 | ** - rev. 2.1 (2013-10-30) |
| mbed_official | 324:406fd2029f23 | 57 | ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. |
| mbed_official | 324:406fd2029f23 | 58 | ** - rev. 2.2 (2013-12-20) |
| mbed_official | 324:406fd2029f23 | 59 | ** Update according to reference manual rev. 0.6, |
| mbed_official | 324:406fd2029f23 | 60 | ** - rev. 2.3 (2014-01-13) |
| mbed_official | 324:406fd2029f23 | 61 | ** Update according to reference manual rev. 0.61, |
| mbed_official | 324:406fd2029f23 | 62 | ** - rev. 2.4 (2014-02-10) |
| mbed_official | 324:406fd2029f23 | 63 | ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h |
| mbed_official | 324:406fd2029f23 | 64 | ** - rev. 2.5 (2014-05-06) |
| mbed_official | 324:406fd2029f23 | 65 | ** Update according to reference manual rev. 1.0, |
| mbed_official | 324:406fd2029f23 | 66 | ** Update of system and startup files. |
| mbed_official | 324:406fd2029f23 | 67 | ** Module access macro module_BASES replaced by module_BASE_PTRS. |
| mbed_official | 324:406fd2029f23 | 68 | ** |
| mbed_official | 324:406fd2029f23 | 69 | ** ################################################################### |
| mbed_official | 324:406fd2029f23 | 70 | */ |
| mbed_official | 324:406fd2029f23 | 71 | |
| mbed_official | 324:406fd2029f23 | 72 | /* |
| mbed_official | 324:406fd2029f23 | 73 | * WARNING! DO NOT EDIT THIS FILE DIRECTLY! |
| mbed_official | 324:406fd2029f23 | 74 | * |
| mbed_official | 324:406fd2029f23 | 75 | * This file was generated automatically and any changes may be lost. |
| mbed_official | 324:406fd2029f23 | 76 | */ |
| mbed_official | 324:406fd2029f23 | 77 | #ifndef __HW_MCM_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 78 | #define __HW_MCM_REGISTERS_H__ |
| mbed_official | 324:406fd2029f23 | 79 | |
| mbed_official | 324:406fd2029f23 | 80 | #include "MK22F51212.h" |
| mbed_official | 324:406fd2029f23 | 81 | #include "fsl_bitaccess.h" |
| mbed_official | 324:406fd2029f23 | 82 | |
| mbed_official | 324:406fd2029f23 | 83 | /* |
| mbed_official | 324:406fd2029f23 | 84 | * MK22F51212 MCM |
| mbed_official | 324:406fd2029f23 | 85 | * |
| mbed_official | 324:406fd2029f23 | 86 | * Core Platform Miscellaneous Control Module |
| mbed_official | 324:406fd2029f23 | 87 | * |
| mbed_official | 324:406fd2029f23 | 88 | * Registers defined in this header file: |
| mbed_official | 324:406fd2029f23 | 89 | * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration |
| mbed_official | 324:406fd2029f23 | 90 | * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration |
| mbed_official | 324:406fd2029f23 | 91 | * - HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register |
| mbed_official | 324:406fd2029f23 | 92 | * - HW_MCM_ISCR - Interrupt Status and Control Register |
| mbed_official | 324:406fd2029f23 | 93 | * - HW_MCM_CPO - Compute Operation Control Register |
| mbed_official | 324:406fd2029f23 | 94 | * |
| mbed_official | 324:406fd2029f23 | 95 | * - hw_mcm_t - Struct containing all module registers. |
| mbed_official | 324:406fd2029f23 | 96 | */ |
| mbed_official | 324:406fd2029f23 | 97 | |
| mbed_official | 324:406fd2029f23 | 98 | #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */ |
| mbed_official | 324:406fd2029f23 | 99 | |
| mbed_official | 324:406fd2029f23 | 100 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 101 | * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration |
| mbed_official | 324:406fd2029f23 | 102 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 103 | |
| mbed_official | 324:406fd2029f23 | 104 | /*! |
| mbed_official | 324:406fd2029f23 | 105 | * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO) |
| mbed_official | 324:406fd2029f23 | 106 | * |
| mbed_official | 324:406fd2029f23 | 107 | * Reset value: 0x001FU |
| mbed_official | 324:406fd2029f23 | 108 | * |
| mbed_official | 324:406fd2029f23 | 109 | * PLASC is a 16-bit read-only register identifying the presence/absence of bus |
| mbed_official | 324:406fd2029f23 | 110 | * slave connections to the device's crossbar switch. |
| mbed_official | 324:406fd2029f23 | 111 | */ |
| mbed_official | 324:406fd2029f23 | 112 | typedef union _hw_mcm_plasc |
| mbed_official | 324:406fd2029f23 | 113 | { |
| mbed_official | 324:406fd2029f23 | 114 | uint16_t U; |
| mbed_official | 324:406fd2029f23 | 115 | struct _hw_mcm_plasc_bitfields |
| mbed_official | 324:406fd2029f23 | 116 | { |
| mbed_official | 324:406fd2029f23 | 117 | uint16_t ASC : 8; /*!< [7:0] Each bit in the ASC field indicates |
| mbed_official | 324:406fd2029f23 | 118 | * whether there is a corresponding connection to the crossbar switch's slave |
| mbed_official | 324:406fd2029f23 | 119 | * input port. */ |
| mbed_official | 324:406fd2029f23 | 120 | uint16_t RESERVED0 : 8; /*!< [15:8] */ |
| mbed_official | 324:406fd2029f23 | 121 | } B; |
| mbed_official | 324:406fd2029f23 | 122 | } hw_mcm_plasc_t; |
| mbed_official | 324:406fd2029f23 | 123 | |
| mbed_official | 324:406fd2029f23 | 124 | /*! |
| mbed_official | 324:406fd2029f23 | 125 | * @name Constants and macros for entire MCM_PLASC register |
| mbed_official | 324:406fd2029f23 | 126 | */ |
| mbed_official | 324:406fd2029f23 | 127 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 128 | #define HW_MCM_PLASC_ADDR(x) ((x) + 0x8U) |
| mbed_official | 324:406fd2029f23 | 129 | |
| mbed_official | 324:406fd2029f23 | 130 | #define HW_MCM_PLASC(x) (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 131 | #define HW_MCM_PLASC_RD(x) (HW_MCM_PLASC(x).U) |
| mbed_official | 324:406fd2029f23 | 132 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 133 | |
| mbed_official | 324:406fd2029f23 | 134 | /* |
| mbed_official | 324:406fd2029f23 | 135 | * Constants & macros for individual MCM_PLASC bitfields |
| mbed_official | 324:406fd2029f23 | 136 | */ |
| mbed_official | 324:406fd2029f23 | 137 | |
| mbed_official | 324:406fd2029f23 | 138 | /*! |
| mbed_official | 324:406fd2029f23 | 139 | * @name Register MCM_PLASC, field ASC[7:0] (RO) |
| mbed_official | 324:406fd2029f23 | 140 | * |
| mbed_official | 324:406fd2029f23 | 141 | * Values: |
| mbed_official | 324:406fd2029f23 | 142 | * - 0 - A bus slave connection to AXBS input port n is absent |
| mbed_official | 324:406fd2029f23 | 143 | * - 1 - A bus slave connection to AXBS input port n is present |
| mbed_official | 324:406fd2029f23 | 144 | */ |
| mbed_official | 324:406fd2029f23 | 145 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 146 | #define BP_MCM_PLASC_ASC (0U) /*!< Bit position for MCM_PLASC_ASC. */ |
| mbed_official | 324:406fd2029f23 | 147 | #define BM_MCM_PLASC_ASC (0x00FFU) /*!< Bit mask for MCM_PLASC_ASC. */ |
| mbed_official | 324:406fd2029f23 | 148 | #define BS_MCM_PLASC_ASC (8U) /*!< Bit field size in bits for MCM_PLASC_ASC. */ |
| mbed_official | 324:406fd2029f23 | 149 | |
| mbed_official | 324:406fd2029f23 | 150 | /*! @brief Read current value of the MCM_PLASC_ASC field. */ |
| mbed_official | 324:406fd2029f23 | 151 | #define BR_MCM_PLASC_ASC(x) (HW_MCM_PLASC(x).B.ASC) |
| mbed_official | 324:406fd2029f23 | 152 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 153 | |
| mbed_official | 324:406fd2029f23 | 154 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 155 | * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration |
| mbed_official | 324:406fd2029f23 | 156 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 157 | |
| mbed_official | 324:406fd2029f23 | 158 | /*! |
| mbed_official | 324:406fd2029f23 | 159 | * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO) |
| mbed_official | 324:406fd2029f23 | 160 | * |
| mbed_official | 324:406fd2029f23 | 161 | * Reset value: 0x0017U |
| mbed_official | 324:406fd2029f23 | 162 | * |
| mbed_official | 324:406fd2029f23 | 163 | * PLAMC is a 16-bit read-only register identifying the presence/absence of bus |
| mbed_official | 324:406fd2029f23 | 164 | * master connections to the device's crossbar switch. |
| mbed_official | 324:406fd2029f23 | 165 | */ |
| mbed_official | 324:406fd2029f23 | 166 | typedef union _hw_mcm_plamc |
| mbed_official | 324:406fd2029f23 | 167 | { |
| mbed_official | 324:406fd2029f23 | 168 | uint16_t U; |
| mbed_official | 324:406fd2029f23 | 169 | struct _hw_mcm_plamc_bitfields |
| mbed_official | 324:406fd2029f23 | 170 | { |
| mbed_official | 324:406fd2029f23 | 171 | uint16_t AMC : 8; /*!< [7:0] Each bit in the AMC field indicates |
| mbed_official | 324:406fd2029f23 | 172 | * whether there is a corresponding connection to the AXBS master input port. */ |
| mbed_official | 324:406fd2029f23 | 173 | uint16_t RESERVED0 : 8; /*!< [15:8] */ |
| mbed_official | 324:406fd2029f23 | 174 | } B; |
| mbed_official | 324:406fd2029f23 | 175 | } hw_mcm_plamc_t; |
| mbed_official | 324:406fd2029f23 | 176 | |
| mbed_official | 324:406fd2029f23 | 177 | /*! |
| mbed_official | 324:406fd2029f23 | 178 | * @name Constants and macros for entire MCM_PLAMC register |
| mbed_official | 324:406fd2029f23 | 179 | */ |
| mbed_official | 324:406fd2029f23 | 180 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 181 | #define HW_MCM_PLAMC_ADDR(x) ((x) + 0xAU) |
| mbed_official | 324:406fd2029f23 | 182 | |
| mbed_official | 324:406fd2029f23 | 183 | #define HW_MCM_PLAMC(x) (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 184 | #define HW_MCM_PLAMC_RD(x) (HW_MCM_PLAMC(x).U) |
| mbed_official | 324:406fd2029f23 | 185 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 186 | |
| mbed_official | 324:406fd2029f23 | 187 | /* |
| mbed_official | 324:406fd2029f23 | 188 | * Constants & macros for individual MCM_PLAMC bitfields |
| mbed_official | 324:406fd2029f23 | 189 | */ |
| mbed_official | 324:406fd2029f23 | 190 | |
| mbed_official | 324:406fd2029f23 | 191 | /*! |
| mbed_official | 324:406fd2029f23 | 192 | * @name Register MCM_PLAMC, field AMC[7:0] (RO) |
| mbed_official | 324:406fd2029f23 | 193 | * |
| mbed_official | 324:406fd2029f23 | 194 | * Values: |
| mbed_official | 324:406fd2029f23 | 195 | * - 0 - A bus master connection to AXBS input port n is absent |
| mbed_official | 324:406fd2029f23 | 196 | * - 1 - A bus master connection to AXBS input port n is present |
| mbed_official | 324:406fd2029f23 | 197 | */ |
| mbed_official | 324:406fd2029f23 | 198 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 199 | #define BP_MCM_PLAMC_AMC (0U) /*!< Bit position for MCM_PLAMC_AMC. */ |
| mbed_official | 324:406fd2029f23 | 200 | #define BM_MCM_PLAMC_AMC (0x00FFU) /*!< Bit mask for MCM_PLAMC_AMC. */ |
| mbed_official | 324:406fd2029f23 | 201 | #define BS_MCM_PLAMC_AMC (8U) /*!< Bit field size in bits for MCM_PLAMC_AMC. */ |
| mbed_official | 324:406fd2029f23 | 202 | |
| mbed_official | 324:406fd2029f23 | 203 | /*! @brief Read current value of the MCM_PLAMC_AMC field. */ |
| mbed_official | 324:406fd2029f23 | 204 | #define BR_MCM_PLAMC_AMC(x) (HW_MCM_PLAMC(x).B.AMC) |
| mbed_official | 324:406fd2029f23 | 205 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 206 | |
| mbed_official | 324:406fd2029f23 | 207 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 208 | * HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register |
| mbed_official | 324:406fd2029f23 | 209 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 210 | |
| mbed_official | 324:406fd2029f23 | 211 | /*! |
| mbed_official | 324:406fd2029f23 | 212 | * @brief HW_MCM_PLACR - Crossbar Switch (AXBS) Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 213 | * |
| mbed_official | 324:406fd2029f23 | 214 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 215 | * |
| mbed_official | 324:406fd2029f23 | 216 | * The PLACR register selects the arbitration policy for the crossbar masters. |
| mbed_official | 324:406fd2029f23 | 217 | */ |
| mbed_official | 324:406fd2029f23 | 218 | typedef union _hw_mcm_placr |
| mbed_official | 324:406fd2029f23 | 219 | { |
| mbed_official | 324:406fd2029f23 | 220 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 221 | struct _hw_mcm_placr_bitfields |
| mbed_official | 324:406fd2029f23 | 222 | { |
| mbed_official | 324:406fd2029f23 | 223 | uint32_t RESERVED0 : 9; /*!< [8:0] */ |
| mbed_official | 324:406fd2029f23 | 224 | uint32_t ARB : 1; /*!< [9] Arbitration select */ |
| mbed_official | 324:406fd2029f23 | 225 | uint32_t RESERVED1 : 22; /*!< [31:10] */ |
| mbed_official | 324:406fd2029f23 | 226 | } B; |
| mbed_official | 324:406fd2029f23 | 227 | } hw_mcm_placr_t; |
| mbed_official | 324:406fd2029f23 | 228 | |
| mbed_official | 324:406fd2029f23 | 229 | /*! |
| mbed_official | 324:406fd2029f23 | 230 | * @name Constants and macros for entire MCM_PLACR register |
| mbed_official | 324:406fd2029f23 | 231 | */ |
| mbed_official | 324:406fd2029f23 | 232 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 233 | #define HW_MCM_PLACR_ADDR(x) ((x) + 0xCU) |
| mbed_official | 324:406fd2029f23 | 234 | |
| mbed_official | 324:406fd2029f23 | 235 | #define HW_MCM_PLACR(x) (*(__IO hw_mcm_placr_t *) HW_MCM_PLACR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 236 | #define HW_MCM_PLACR_RD(x) (HW_MCM_PLACR(x).U) |
| mbed_official | 324:406fd2029f23 | 237 | #define HW_MCM_PLACR_WR(x, v) (HW_MCM_PLACR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 238 | #define HW_MCM_PLACR_SET(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 239 | #define HW_MCM_PLACR_CLR(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 240 | #define HW_MCM_PLACR_TOG(x, v) (HW_MCM_PLACR_WR(x, HW_MCM_PLACR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 241 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 242 | |
| mbed_official | 324:406fd2029f23 | 243 | /* |
| mbed_official | 324:406fd2029f23 | 244 | * Constants & macros for individual MCM_PLACR bitfields |
| mbed_official | 324:406fd2029f23 | 245 | */ |
| mbed_official | 324:406fd2029f23 | 246 | |
| mbed_official | 324:406fd2029f23 | 247 | /*! |
| mbed_official | 324:406fd2029f23 | 248 | * @name Register MCM_PLACR, field ARB[9] (RW) |
| mbed_official | 324:406fd2029f23 | 249 | * |
| mbed_official | 324:406fd2029f23 | 250 | * Values: |
| mbed_official | 324:406fd2029f23 | 251 | * - 0 - Fixed-priority arbitration for the crossbar masters |
| mbed_official | 324:406fd2029f23 | 252 | * - 1 - Round-robin arbitration for the crossbar masters |
| mbed_official | 324:406fd2029f23 | 253 | */ |
| mbed_official | 324:406fd2029f23 | 254 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 255 | #define BP_MCM_PLACR_ARB (9U) /*!< Bit position for MCM_PLACR_ARB. */ |
| mbed_official | 324:406fd2029f23 | 256 | #define BM_MCM_PLACR_ARB (0x00000200U) /*!< Bit mask for MCM_PLACR_ARB. */ |
| mbed_official | 324:406fd2029f23 | 257 | #define BS_MCM_PLACR_ARB (1U) /*!< Bit field size in bits for MCM_PLACR_ARB. */ |
| mbed_official | 324:406fd2029f23 | 258 | |
| mbed_official | 324:406fd2029f23 | 259 | /*! @brief Read current value of the MCM_PLACR_ARB field. */ |
| mbed_official | 324:406fd2029f23 | 260 | #define BR_MCM_PLACR_ARB(x) (HW_MCM_PLACR(x).B.ARB) |
| mbed_official | 324:406fd2029f23 | 261 | |
| mbed_official | 324:406fd2029f23 | 262 | /*! @brief Format value for bitfield MCM_PLACR_ARB. */ |
| mbed_official | 324:406fd2029f23 | 263 | #define BF_MCM_PLACR_ARB(v) ((uint32_t)((uint32_t)(v) << BP_MCM_PLACR_ARB) & BM_MCM_PLACR_ARB) |
| mbed_official | 324:406fd2029f23 | 264 | |
| mbed_official | 324:406fd2029f23 | 265 | /*! @brief Set the ARB field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 266 | #define BW_MCM_PLACR_ARB(x, v) (HW_MCM_PLACR_WR(x, (HW_MCM_PLACR_RD(x) & ~BM_MCM_PLACR_ARB) | BF_MCM_PLACR_ARB(v))) |
| mbed_official | 324:406fd2029f23 | 267 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 268 | |
| mbed_official | 324:406fd2029f23 | 269 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 270 | * HW_MCM_ISCR - Interrupt Status and Control Register |
| mbed_official | 324:406fd2029f23 | 271 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 272 | |
| mbed_official | 324:406fd2029f23 | 273 | /*! |
| mbed_official | 324:406fd2029f23 | 274 | * @brief HW_MCM_ISCR - Interrupt Status and Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 275 | * |
| mbed_official | 324:406fd2029f23 | 276 | * Reset value: 0x00020000U |
| mbed_official | 324:406fd2029f23 | 277 | * |
| mbed_official | 324:406fd2029f23 | 278 | * The MCM_ISCR register includes the enable and status bits associated with the |
| mbed_official | 324:406fd2029f23 | 279 | * core's floating-point exceptions. The individual event indicators are first |
| mbed_official | 324:406fd2029f23 | 280 | * qualified with their exception enables and then logically summed to form an |
| mbed_official | 324:406fd2029f23 | 281 | * interrupt request sent to the core's NVIC. Bits 15-8 are read-only indicator |
| mbed_official | 324:406fd2029f23 | 282 | * flags based on the processor's FPSCR register. Attempted writes to these bits are |
| mbed_official | 324:406fd2029f23 | 283 | * ignored. Once set, the flags remain asserted until software clears the |
| mbed_official | 324:406fd2029f23 | 284 | * corresponding FPSCR bit. |
| mbed_official | 324:406fd2029f23 | 285 | */ |
| mbed_official | 324:406fd2029f23 | 286 | typedef union _hw_mcm_iscr |
| mbed_official | 324:406fd2029f23 | 287 | { |
| mbed_official | 324:406fd2029f23 | 288 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 289 | struct _hw_mcm_iscr_bitfields |
| mbed_official | 324:406fd2029f23 | 290 | { |
| mbed_official | 324:406fd2029f23 | 291 | uint32_t RESERVED0 : 8; /*!< [7:0] */ |
| mbed_official | 324:406fd2029f23 | 292 | uint32_t FIOC : 1; /*!< [8] FPU invalid operation interrupt status */ |
| mbed_official | 324:406fd2029f23 | 293 | uint32_t FDZC : 1; /*!< [9] FPU divide-by-zero interrupt status */ |
| mbed_official | 324:406fd2029f23 | 294 | uint32_t FOFC : 1; /*!< [10] FPU overflow interrupt status */ |
| mbed_official | 324:406fd2029f23 | 295 | uint32_t FUFC : 1; /*!< [11] FPU underflow interrupt status */ |
| mbed_official | 324:406fd2029f23 | 296 | uint32_t FIXC : 1; /*!< [12] FPU inexact interrupt status */ |
| mbed_official | 324:406fd2029f23 | 297 | uint32_t RESERVED1 : 2; /*!< [14:13] */ |
| mbed_official | 324:406fd2029f23 | 298 | uint32_t FIDC : 1; /*!< [15] FPU input denormal interrupt status */ |
| mbed_official | 324:406fd2029f23 | 299 | uint32_t RESERVED2 : 8; /*!< [23:16] */ |
| mbed_official | 324:406fd2029f23 | 300 | uint32_t FIOCE : 1; /*!< [24] FPU invalid operation interrupt enable |
| mbed_official | 324:406fd2029f23 | 301 | * */ |
| mbed_official | 324:406fd2029f23 | 302 | uint32_t FDZCE : 1; /*!< [25] FPU divide-by-zero interrupt enable */ |
| mbed_official | 324:406fd2029f23 | 303 | uint32_t FOFCE : 1; /*!< [26] FPU overflow interrupt enable */ |
| mbed_official | 324:406fd2029f23 | 304 | uint32_t FUFCE : 1; /*!< [27] FPU underflow interrupt enable */ |
| mbed_official | 324:406fd2029f23 | 305 | uint32_t FIXCE : 1; /*!< [28] FPU inexact interrupt enable */ |
| mbed_official | 324:406fd2029f23 | 306 | uint32_t RESERVED3 : 2; /*!< [30:29] */ |
| mbed_official | 324:406fd2029f23 | 307 | uint32_t FIDCE : 1; /*!< [31] FPU input denormal interrupt enable */ |
| mbed_official | 324:406fd2029f23 | 308 | } B; |
| mbed_official | 324:406fd2029f23 | 309 | } hw_mcm_iscr_t; |
| mbed_official | 324:406fd2029f23 | 310 | |
| mbed_official | 324:406fd2029f23 | 311 | /*! |
| mbed_official | 324:406fd2029f23 | 312 | * @name Constants and macros for entire MCM_ISCR register |
| mbed_official | 324:406fd2029f23 | 313 | */ |
| mbed_official | 324:406fd2029f23 | 314 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 315 | #define HW_MCM_ISCR_ADDR(x) ((x) + 0x10U) |
| mbed_official | 324:406fd2029f23 | 316 | |
| mbed_official | 324:406fd2029f23 | 317 | #define HW_MCM_ISCR(x) (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 318 | #define HW_MCM_ISCR_RD(x) (HW_MCM_ISCR(x).U) |
| mbed_official | 324:406fd2029f23 | 319 | #define HW_MCM_ISCR_WR(x, v) (HW_MCM_ISCR(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 320 | #define HW_MCM_ISCR_SET(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 321 | #define HW_MCM_ISCR_CLR(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 322 | #define HW_MCM_ISCR_TOG(x, v) (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 323 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 324 | |
| mbed_official | 324:406fd2029f23 | 325 | /* |
| mbed_official | 324:406fd2029f23 | 326 | * Constants & macros for individual MCM_ISCR bitfields |
| mbed_official | 324:406fd2029f23 | 327 | */ |
| mbed_official | 324:406fd2029f23 | 328 | |
| mbed_official | 324:406fd2029f23 | 329 | /*! |
| mbed_official | 324:406fd2029f23 | 330 | * @name Register MCM_ISCR, field FIOC[8] (RO) |
| mbed_official | 324:406fd2029f23 | 331 | * |
| mbed_official | 324:406fd2029f23 | 332 | * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an |
| mbed_official | 324:406fd2029f23 | 333 | * illegal operation has been detected in the processor's FPU. Once set, this bit |
| mbed_official | 324:406fd2029f23 | 334 | * remains set until software clears the FPSCR[IOC] bit. |
| mbed_official | 324:406fd2029f23 | 335 | * |
| mbed_official | 324:406fd2029f23 | 336 | * Values: |
| mbed_official | 324:406fd2029f23 | 337 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 338 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 339 | */ |
| mbed_official | 324:406fd2029f23 | 340 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 341 | #define BP_MCM_ISCR_FIOC (8U) /*!< Bit position for MCM_ISCR_FIOC. */ |
| mbed_official | 324:406fd2029f23 | 342 | #define BM_MCM_ISCR_FIOC (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */ |
| mbed_official | 324:406fd2029f23 | 343 | #define BS_MCM_ISCR_FIOC (1U) /*!< Bit field size in bits for MCM_ISCR_FIOC. */ |
| mbed_official | 324:406fd2029f23 | 344 | |
| mbed_official | 324:406fd2029f23 | 345 | /*! @brief Read current value of the MCM_ISCR_FIOC field. */ |
| mbed_official | 324:406fd2029f23 | 346 | #define BR_MCM_ISCR_FIOC(x) (HW_MCM_ISCR(x).B.FIOC) |
| mbed_official | 324:406fd2029f23 | 347 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 348 | |
| mbed_official | 324:406fd2029f23 | 349 | /*! |
| mbed_official | 324:406fd2029f23 | 350 | * @name Register MCM_ISCR, field FDZC[9] (RO) |
| mbed_official | 324:406fd2029f23 | 351 | * |
| mbed_official | 324:406fd2029f23 | 352 | * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a |
| mbed_official | 324:406fd2029f23 | 353 | * divide by zero has been detected in the processor's FPU. Once set, this bit remains |
| mbed_official | 324:406fd2029f23 | 354 | * set until software clears the FPSCR[DZC] bit. |
| mbed_official | 324:406fd2029f23 | 355 | * |
| mbed_official | 324:406fd2029f23 | 356 | * Values: |
| mbed_official | 324:406fd2029f23 | 357 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 358 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 359 | */ |
| mbed_official | 324:406fd2029f23 | 360 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 361 | #define BP_MCM_ISCR_FDZC (9U) /*!< Bit position for MCM_ISCR_FDZC. */ |
| mbed_official | 324:406fd2029f23 | 362 | #define BM_MCM_ISCR_FDZC (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */ |
| mbed_official | 324:406fd2029f23 | 363 | #define BS_MCM_ISCR_FDZC (1U) /*!< Bit field size in bits for MCM_ISCR_FDZC. */ |
| mbed_official | 324:406fd2029f23 | 364 | |
| mbed_official | 324:406fd2029f23 | 365 | /*! @brief Read current value of the MCM_ISCR_FDZC field. */ |
| mbed_official | 324:406fd2029f23 | 366 | #define BR_MCM_ISCR_FDZC(x) (HW_MCM_ISCR(x).B.FDZC) |
| mbed_official | 324:406fd2029f23 | 367 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 368 | |
| mbed_official | 324:406fd2029f23 | 369 | /*! |
| mbed_official | 324:406fd2029f23 | 370 | * @name Register MCM_ISCR, field FOFC[10] (RO) |
| mbed_official | 324:406fd2029f23 | 371 | * |
| mbed_official | 324:406fd2029f23 | 372 | * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an |
| mbed_official | 324:406fd2029f23 | 373 | * overflow has been detected in the processor's FPU. Once set, this bit remains set |
| mbed_official | 324:406fd2029f23 | 374 | * until software clears the FPSCR[OFC] bit. |
| mbed_official | 324:406fd2029f23 | 375 | * |
| mbed_official | 324:406fd2029f23 | 376 | * Values: |
| mbed_official | 324:406fd2029f23 | 377 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 378 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 379 | */ |
| mbed_official | 324:406fd2029f23 | 380 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 381 | #define BP_MCM_ISCR_FOFC (10U) /*!< Bit position for MCM_ISCR_FOFC. */ |
| mbed_official | 324:406fd2029f23 | 382 | #define BM_MCM_ISCR_FOFC (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */ |
| mbed_official | 324:406fd2029f23 | 383 | #define BS_MCM_ISCR_FOFC (1U) /*!< Bit field size in bits for MCM_ISCR_FOFC. */ |
| mbed_official | 324:406fd2029f23 | 384 | |
| mbed_official | 324:406fd2029f23 | 385 | /*! @brief Read current value of the MCM_ISCR_FOFC field. */ |
| mbed_official | 324:406fd2029f23 | 386 | #define BR_MCM_ISCR_FOFC(x) (HW_MCM_ISCR(x).B.FOFC) |
| mbed_official | 324:406fd2029f23 | 387 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 388 | |
| mbed_official | 324:406fd2029f23 | 389 | /*! |
| mbed_official | 324:406fd2029f23 | 390 | * @name Register MCM_ISCR, field FUFC[11] (RO) |
| mbed_official | 324:406fd2029f23 | 391 | * |
| mbed_official | 324:406fd2029f23 | 392 | * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an |
| mbed_official | 324:406fd2029f23 | 393 | * underflow has been detected in the processor's FPU. Once set, this bit remains set |
| mbed_official | 324:406fd2029f23 | 394 | * until software clears the FPSCR[UFC] bit. |
| mbed_official | 324:406fd2029f23 | 395 | * |
| mbed_official | 324:406fd2029f23 | 396 | * Values: |
| mbed_official | 324:406fd2029f23 | 397 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 398 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 399 | */ |
| mbed_official | 324:406fd2029f23 | 400 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 401 | #define BP_MCM_ISCR_FUFC (11U) /*!< Bit position for MCM_ISCR_FUFC. */ |
| mbed_official | 324:406fd2029f23 | 402 | #define BM_MCM_ISCR_FUFC (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */ |
| mbed_official | 324:406fd2029f23 | 403 | #define BS_MCM_ISCR_FUFC (1U) /*!< Bit field size in bits for MCM_ISCR_FUFC. */ |
| mbed_official | 324:406fd2029f23 | 404 | |
| mbed_official | 324:406fd2029f23 | 405 | /*! @brief Read current value of the MCM_ISCR_FUFC field. */ |
| mbed_official | 324:406fd2029f23 | 406 | #define BR_MCM_ISCR_FUFC(x) (HW_MCM_ISCR(x).B.FUFC) |
| mbed_official | 324:406fd2029f23 | 407 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 408 | |
| mbed_official | 324:406fd2029f23 | 409 | /*! |
| mbed_official | 324:406fd2029f23 | 410 | * @name Register MCM_ISCR, field FIXC[12] (RO) |
| mbed_official | 324:406fd2029f23 | 411 | * |
| mbed_official | 324:406fd2029f23 | 412 | * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an |
| mbed_official | 324:406fd2029f23 | 413 | * inexact number has been detected in the processor's FPU. Once set, this bit |
| mbed_official | 324:406fd2029f23 | 414 | * remains set until software clears the FPSCR[IXC] bit. |
| mbed_official | 324:406fd2029f23 | 415 | * |
| mbed_official | 324:406fd2029f23 | 416 | * Values: |
| mbed_official | 324:406fd2029f23 | 417 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 418 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 419 | */ |
| mbed_official | 324:406fd2029f23 | 420 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 421 | #define BP_MCM_ISCR_FIXC (12U) /*!< Bit position for MCM_ISCR_FIXC. */ |
| mbed_official | 324:406fd2029f23 | 422 | #define BM_MCM_ISCR_FIXC (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */ |
| mbed_official | 324:406fd2029f23 | 423 | #define BS_MCM_ISCR_FIXC (1U) /*!< Bit field size in bits for MCM_ISCR_FIXC. */ |
| mbed_official | 324:406fd2029f23 | 424 | |
| mbed_official | 324:406fd2029f23 | 425 | /*! @brief Read current value of the MCM_ISCR_FIXC field. */ |
| mbed_official | 324:406fd2029f23 | 426 | #define BR_MCM_ISCR_FIXC(x) (HW_MCM_ISCR(x).B.FIXC) |
| mbed_official | 324:406fd2029f23 | 427 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 428 | |
| mbed_official | 324:406fd2029f23 | 429 | /*! |
| mbed_official | 324:406fd2029f23 | 430 | * @name Register MCM_ISCR, field FIDC[15] (RO) |
| mbed_official | 324:406fd2029f23 | 431 | * |
| mbed_official | 324:406fd2029f23 | 432 | * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input |
| mbed_official | 324:406fd2029f23 | 433 | * denormalized number has been detected in the processor's FPU. Once set, this |
| mbed_official | 324:406fd2029f23 | 434 | * bit remains set until software clears the FPSCR[IDC] bit. |
| mbed_official | 324:406fd2029f23 | 435 | * |
| mbed_official | 324:406fd2029f23 | 436 | * Values: |
| mbed_official | 324:406fd2029f23 | 437 | * - 0 - No interrupt |
| mbed_official | 324:406fd2029f23 | 438 | * - 1 - Interrupt occurred |
| mbed_official | 324:406fd2029f23 | 439 | */ |
| mbed_official | 324:406fd2029f23 | 440 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 441 | #define BP_MCM_ISCR_FIDC (15U) /*!< Bit position for MCM_ISCR_FIDC. */ |
| mbed_official | 324:406fd2029f23 | 442 | #define BM_MCM_ISCR_FIDC (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */ |
| mbed_official | 324:406fd2029f23 | 443 | #define BS_MCM_ISCR_FIDC (1U) /*!< Bit field size in bits for MCM_ISCR_FIDC. */ |
| mbed_official | 324:406fd2029f23 | 444 | |
| mbed_official | 324:406fd2029f23 | 445 | /*! @brief Read current value of the MCM_ISCR_FIDC field. */ |
| mbed_official | 324:406fd2029f23 | 446 | #define BR_MCM_ISCR_FIDC(x) (HW_MCM_ISCR(x).B.FIDC) |
| mbed_official | 324:406fd2029f23 | 447 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 448 | |
| mbed_official | 324:406fd2029f23 | 449 | /*! |
| mbed_official | 324:406fd2029f23 | 450 | * @name Register MCM_ISCR, field FIOCE[24] (RW) |
| mbed_official | 324:406fd2029f23 | 451 | * |
| mbed_official | 324:406fd2029f23 | 452 | * Values: |
| mbed_official | 324:406fd2029f23 | 453 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 454 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 455 | */ |
| mbed_official | 324:406fd2029f23 | 456 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 457 | #define BP_MCM_ISCR_FIOCE (24U) /*!< Bit position for MCM_ISCR_FIOCE. */ |
| mbed_official | 324:406fd2029f23 | 458 | #define BM_MCM_ISCR_FIOCE (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */ |
| mbed_official | 324:406fd2029f23 | 459 | #define BS_MCM_ISCR_FIOCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIOCE. */ |
| mbed_official | 324:406fd2029f23 | 460 | |
| mbed_official | 324:406fd2029f23 | 461 | /*! @brief Read current value of the MCM_ISCR_FIOCE field. */ |
| mbed_official | 324:406fd2029f23 | 462 | #define BR_MCM_ISCR_FIOCE(x) (HW_MCM_ISCR(x).B.FIOCE) |
| mbed_official | 324:406fd2029f23 | 463 | |
| mbed_official | 324:406fd2029f23 | 464 | /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */ |
| mbed_official | 324:406fd2029f23 | 465 | #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE) |
| mbed_official | 324:406fd2029f23 | 466 | |
| mbed_official | 324:406fd2029f23 | 467 | /*! @brief Set the FIOCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 468 | #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v))) |
| mbed_official | 324:406fd2029f23 | 469 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 470 | |
| mbed_official | 324:406fd2029f23 | 471 | /*! |
| mbed_official | 324:406fd2029f23 | 472 | * @name Register MCM_ISCR, field FDZCE[25] (RW) |
| mbed_official | 324:406fd2029f23 | 473 | * |
| mbed_official | 324:406fd2029f23 | 474 | * Values: |
| mbed_official | 324:406fd2029f23 | 475 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 476 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 477 | */ |
| mbed_official | 324:406fd2029f23 | 478 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 479 | #define BP_MCM_ISCR_FDZCE (25U) /*!< Bit position for MCM_ISCR_FDZCE. */ |
| mbed_official | 324:406fd2029f23 | 480 | #define BM_MCM_ISCR_FDZCE (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */ |
| mbed_official | 324:406fd2029f23 | 481 | #define BS_MCM_ISCR_FDZCE (1U) /*!< Bit field size in bits for MCM_ISCR_FDZCE. */ |
| mbed_official | 324:406fd2029f23 | 482 | |
| mbed_official | 324:406fd2029f23 | 483 | /*! @brief Read current value of the MCM_ISCR_FDZCE field. */ |
| mbed_official | 324:406fd2029f23 | 484 | #define BR_MCM_ISCR_FDZCE(x) (HW_MCM_ISCR(x).B.FDZCE) |
| mbed_official | 324:406fd2029f23 | 485 | |
| mbed_official | 324:406fd2029f23 | 486 | /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */ |
| mbed_official | 324:406fd2029f23 | 487 | #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE) |
| mbed_official | 324:406fd2029f23 | 488 | |
| mbed_official | 324:406fd2029f23 | 489 | /*! @brief Set the FDZCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 490 | #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v))) |
| mbed_official | 324:406fd2029f23 | 491 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 492 | |
| mbed_official | 324:406fd2029f23 | 493 | /*! |
| mbed_official | 324:406fd2029f23 | 494 | * @name Register MCM_ISCR, field FOFCE[26] (RW) |
| mbed_official | 324:406fd2029f23 | 495 | * |
| mbed_official | 324:406fd2029f23 | 496 | * Values: |
| mbed_official | 324:406fd2029f23 | 497 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 498 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 499 | */ |
| mbed_official | 324:406fd2029f23 | 500 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 501 | #define BP_MCM_ISCR_FOFCE (26U) /*!< Bit position for MCM_ISCR_FOFCE. */ |
| mbed_official | 324:406fd2029f23 | 502 | #define BM_MCM_ISCR_FOFCE (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */ |
| mbed_official | 324:406fd2029f23 | 503 | #define BS_MCM_ISCR_FOFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FOFCE. */ |
| mbed_official | 324:406fd2029f23 | 504 | |
| mbed_official | 324:406fd2029f23 | 505 | /*! @brief Read current value of the MCM_ISCR_FOFCE field. */ |
| mbed_official | 324:406fd2029f23 | 506 | #define BR_MCM_ISCR_FOFCE(x) (HW_MCM_ISCR(x).B.FOFCE) |
| mbed_official | 324:406fd2029f23 | 507 | |
| mbed_official | 324:406fd2029f23 | 508 | /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */ |
| mbed_official | 324:406fd2029f23 | 509 | #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE) |
| mbed_official | 324:406fd2029f23 | 510 | |
| mbed_official | 324:406fd2029f23 | 511 | /*! @brief Set the FOFCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 512 | #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v))) |
| mbed_official | 324:406fd2029f23 | 513 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 514 | |
| mbed_official | 324:406fd2029f23 | 515 | /*! |
| mbed_official | 324:406fd2029f23 | 516 | * @name Register MCM_ISCR, field FUFCE[27] (RW) |
| mbed_official | 324:406fd2029f23 | 517 | * |
| mbed_official | 324:406fd2029f23 | 518 | * Values: |
| mbed_official | 324:406fd2029f23 | 519 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 520 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 521 | */ |
| mbed_official | 324:406fd2029f23 | 522 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 523 | #define BP_MCM_ISCR_FUFCE (27U) /*!< Bit position for MCM_ISCR_FUFCE. */ |
| mbed_official | 324:406fd2029f23 | 524 | #define BM_MCM_ISCR_FUFCE (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */ |
| mbed_official | 324:406fd2029f23 | 525 | #define BS_MCM_ISCR_FUFCE (1U) /*!< Bit field size in bits for MCM_ISCR_FUFCE. */ |
| mbed_official | 324:406fd2029f23 | 526 | |
| mbed_official | 324:406fd2029f23 | 527 | /*! @brief Read current value of the MCM_ISCR_FUFCE field. */ |
| mbed_official | 324:406fd2029f23 | 528 | #define BR_MCM_ISCR_FUFCE(x) (HW_MCM_ISCR(x).B.FUFCE) |
| mbed_official | 324:406fd2029f23 | 529 | |
| mbed_official | 324:406fd2029f23 | 530 | /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */ |
| mbed_official | 324:406fd2029f23 | 531 | #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE) |
| mbed_official | 324:406fd2029f23 | 532 | |
| mbed_official | 324:406fd2029f23 | 533 | /*! @brief Set the FUFCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 534 | #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v))) |
| mbed_official | 324:406fd2029f23 | 535 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 536 | |
| mbed_official | 324:406fd2029f23 | 537 | /*! |
| mbed_official | 324:406fd2029f23 | 538 | * @name Register MCM_ISCR, field FIXCE[28] (RW) |
| mbed_official | 324:406fd2029f23 | 539 | * |
| mbed_official | 324:406fd2029f23 | 540 | * Values: |
| mbed_official | 324:406fd2029f23 | 541 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 542 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 543 | */ |
| mbed_official | 324:406fd2029f23 | 544 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 545 | #define BP_MCM_ISCR_FIXCE (28U) /*!< Bit position for MCM_ISCR_FIXCE. */ |
| mbed_official | 324:406fd2029f23 | 546 | #define BM_MCM_ISCR_FIXCE (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */ |
| mbed_official | 324:406fd2029f23 | 547 | #define BS_MCM_ISCR_FIXCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIXCE. */ |
| mbed_official | 324:406fd2029f23 | 548 | |
| mbed_official | 324:406fd2029f23 | 549 | /*! @brief Read current value of the MCM_ISCR_FIXCE field. */ |
| mbed_official | 324:406fd2029f23 | 550 | #define BR_MCM_ISCR_FIXCE(x) (HW_MCM_ISCR(x).B.FIXCE) |
| mbed_official | 324:406fd2029f23 | 551 | |
| mbed_official | 324:406fd2029f23 | 552 | /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */ |
| mbed_official | 324:406fd2029f23 | 553 | #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE) |
| mbed_official | 324:406fd2029f23 | 554 | |
| mbed_official | 324:406fd2029f23 | 555 | /*! @brief Set the FIXCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 556 | #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v))) |
| mbed_official | 324:406fd2029f23 | 557 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 558 | |
| mbed_official | 324:406fd2029f23 | 559 | /*! |
| mbed_official | 324:406fd2029f23 | 560 | * @name Register MCM_ISCR, field FIDCE[31] (RW) |
| mbed_official | 324:406fd2029f23 | 561 | * |
| mbed_official | 324:406fd2029f23 | 562 | * Values: |
| mbed_official | 324:406fd2029f23 | 563 | * - 0 - Disable interrupt |
| mbed_official | 324:406fd2029f23 | 564 | * - 1 - Enable interrupt |
| mbed_official | 324:406fd2029f23 | 565 | */ |
| mbed_official | 324:406fd2029f23 | 566 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 567 | #define BP_MCM_ISCR_FIDCE (31U) /*!< Bit position for MCM_ISCR_FIDCE. */ |
| mbed_official | 324:406fd2029f23 | 568 | #define BM_MCM_ISCR_FIDCE (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */ |
| mbed_official | 324:406fd2029f23 | 569 | #define BS_MCM_ISCR_FIDCE (1U) /*!< Bit field size in bits for MCM_ISCR_FIDCE. */ |
| mbed_official | 324:406fd2029f23 | 570 | |
| mbed_official | 324:406fd2029f23 | 571 | /*! @brief Read current value of the MCM_ISCR_FIDCE field. */ |
| mbed_official | 324:406fd2029f23 | 572 | #define BR_MCM_ISCR_FIDCE(x) (HW_MCM_ISCR(x).B.FIDCE) |
| mbed_official | 324:406fd2029f23 | 573 | |
| mbed_official | 324:406fd2029f23 | 574 | /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */ |
| mbed_official | 324:406fd2029f23 | 575 | #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE) |
| mbed_official | 324:406fd2029f23 | 576 | |
| mbed_official | 324:406fd2029f23 | 577 | /*! @brief Set the FIDCE field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 578 | #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v))) |
| mbed_official | 324:406fd2029f23 | 579 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 580 | |
| mbed_official | 324:406fd2029f23 | 581 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 582 | * HW_MCM_CPO - Compute Operation Control Register |
| mbed_official | 324:406fd2029f23 | 583 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 584 | |
| mbed_official | 324:406fd2029f23 | 585 | /*! |
| mbed_official | 324:406fd2029f23 | 586 | * @brief HW_MCM_CPO - Compute Operation Control Register (RW) |
| mbed_official | 324:406fd2029f23 | 587 | * |
| mbed_official | 324:406fd2029f23 | 588 | * Reset value: 0x00000000U |
| mbed_official | 324:406fd2029f23 | 589 | * |
| mbed_official | 324:406fd2029f23 | 590 | * This register controls the Compute Operation. |
| mbed_official | 324:406fd2029f23 | 591 | */ |
| mbed_official | 324:406fd2029f23 | 592 | typedef union _hw_mcm_cpo |
| mbed_official | 324:406fd2029f23 | 593 | { |
| mbed_official | 324:406fd2029f23 | 594 | uint32_t U; |
| mbed_official | 324:406fd2029f23 | 595 | struct _hw_mcm_cpo_bitfields |
| mbed_official | 324:406fd2029f23 | 596 | { |
| mbed_official | 324:406fd2029f23 | 597 | uint32_t CPOREQ : 1; /*!< [0] Compute Operation request */ |
| mbed_official | 324:406fd2029f23 | 598 | uint32_t CPOACK : 1; /*!< [1] Compute Operation acknowledge */ |
| mbed_official | 324:406fd2029f23 | 599 | uint32_t CPOWOI : 1; /*!< [2] Compute Operation wakeup on interrupt */ |
| mbed_official | 324:406fd2029f23 | 600 | uint32_t RESERVED0 : 29; /*!< [31:3] */ |
| mbed_official | 324:406fd2029f23 | 601 | } B; |
| mbed_official | 324:406fd2029f23 | 602 | } hw_mcm_cpo_t; |
| mbed_official | 324:406fd2029f23 | 603 | |
| mbed_official | 324:406fd2029f23 | 604 | /*! |
| mbed_official | 324:406fd2029f23 | 605 | * @name Constants and macros for entire MCM_CPO register |
| mbed_official | 324:406fd2029f23 | 606 | */ |
| mbed_official | 324:406fd2029f23 | 607 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 608 | #define HW_MCM_CPO_ADDR(x) ((x) + 0x40U) |
| mbed_official | 324:406fd2029f23 | 609 | |
| mbed_official | 324:406fd2029f23 | 610 | #define HW_MCM_CPO(x) (*(__IO hw_mcm_cpo_t *) HW_MCM_CPO_ADDR(x)) |
| mbed_official | 324:406fd2029f23 | 611 | #define HW_MCM_CPO_RD(x) (HW_MCM_CPO(x).U) |
| mbed_official | 324:406fd2029f23 | 612 | #define HW_MCM_CPO_WR(x, v) (HW_MCM_CPO(x).U = (v)) |
| mbed_official | 324:406fd2029f23 | 613 | #define HW_MCM_CPO_SET(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) | (v))) |
| mbed_official | 324:406fd2029f23 | 614 | #define HW_MCM_CPO_CLR(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) & ~(v))) |
| mbed_official | 324:406fd2029f23 | 615 | #define HW_MCM_CPO_TOG(x, v) (HW_MCM_CPO_WR(x, HW_MCM_CPO_RD(x) ^ (v))) |
| mbed_official | 324:406fd2029f23 | 616 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 617 | |
| mbed_official | 324:406fd2029f23 | 618 | /* |
| mbed_official | 324:406fd2029f23 | 619 | * Constants & macros for individual MCM_CPO bitfields |
| mbed_official | 324:406fd2029f23 | 620 | */ |
| mbed_official | 324:406fd2029f23 | 621 | |
| mbed_official | 324:406fd2029f23 | 622 | /*! |
| mbed_official | 324:406fd2029f23 | 623 | * @name Register MCM_CPO, field CPOREQ[0] (RW) |
| mbed_official | 324:406fd2029f23 | 624 | * |
| mbed_official | 324:406fd2029f23 | 625 | * This bit is auto-cleared by vector fetching if CPOWOI = 1. |
| mbed_official | 324:406fd2029f23 | 626 | * |
| mbed_official | 324:406fd2029f23 | 627 | * Values: |
| mbed_official | 324:406fd2029f23 | 628 | * - 0 - Request is cleared. |
| mbed_official | 324:406fd2029f23 | 629 | * - 1 - Request Compute Operation. |
| mbed_official | 324:406fd2029f23 | 630 | */ |
| mbed_official | 324:406fd2029f23 | 631 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 632 | #define BP_MCM_CPO_CPOREQ (0U) /*!< Bit position for MCM_CPO_CPOREQ. */ |
| mbed_official | 324:406fd2029f23 | 633 | #define BM_MCM_CPO_CPOREQ (0x00000001U) /*!< Bit mask for MCM_CPO_CPOREQ. */ |
| mbed_official | 324:406fd2029f23 | 634 | #define BS_MCM_CPO_CPOREQ (1U) /*!< Bit field size in bits for MCM_CPO_CPOREQ. */ |
| mbed_official | 324:406fd2029f23 | 635 | |
| mbed_official | 324:406fd2029f23 | 636 | /*! @brief Read current value of the MCM_CPO_CPOREQ field. */ |
| mbed_official | 324:406fd2029f23 | 637 | #define BR_MCM_CPO_CPOREQ(x) (HW_MCM_CPO(x).B.CPOREQ) |
| mbed_official | 324:406fd2029f23 | 638 | |
| mbed_official | 324:406fd2029f23 | 639 | /*! @brief Format value for bitfield MCM_CPO_CPOREQ. */ |
| mbed_official | 324:406fd2029f23 | 640 | #define BF_MCM_CPO_CPOREQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOREQ) & BM_MCM_CPO_CPOREQ) |
| mbed_official | 324:406fd2029f23 | 641 | |
| mbed_official | 324:406fd2029f23 | 642 | /*! @brief Set the CPOREQ field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 643 | #define BW_MCM_CPO_CPOREQ(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOREQ) | BF_MCM_CPO_CPOREQ(v))) |
| mbed_official | 324:406fd2029f23 | 644 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 645 | |
| mbed_official | 324:406fd2029f23 | 646 | /*! |
| mbed_official | 324:406fd2029f23 | 647 | * @name Register MCM_CPO, field CPOACK[1] (RO) |
| mbed_official | 324:406fd2029f23 | 648 | * |
| mbed_official | 324:406fd2029f23 | 649 | * Values: |
| mbed_official | 324:406fd2029f23 | 650 | * - 0 - Compute operation entry has not completed or compute operation exit has |
| mbed_official | 324:406fd2029f23 | 651 | * completed. |
| mbed_official | 324:406fd2029f23 | 652 | * - 1 - Compute operation entry has completed or compute operation exit has not |
| mbed_official | 324:406fd2029f23 | 653 | * completed. |
| mbed_official | 324:406fd2029f23 | 654 | */ |
| mbed_official | 324:406fd2029f23 | 655 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 656 | #define BP_MCM_CPO_CPOACK (1U) /*!< Bit position for MCM_CPO_CPOACK. */ |
| mbed_official | 324:406fd2029f23 | 657 | #define BM_MCM_CPO_CPOACK (0x00000002U) /*!< Bit mask for MCM_CPO_CPOACK. */ |
| mbed_official | 324:406fd2029f23 | 658 | #define BS_MCM_CPO_CPOACK (1U) /*!< Bit field size in bits for MCM_CPO_CPOACK. */ |
| mbed_official | 324:406fd2029f23 | 659 | |
| mbed_official | 324:406fd2029f23 | 660 | /*! @brief Read current value of the MCM_CPO_CPOACK field. */ |
| mbed_official | 324:406fd2029f23 | 661 | #define BR_MCM_CPO_CPOACK(x) (HW_MCM_CPO(x).B.CPOACK) |
| mbed_official | 324:406fd2029f23 | 662 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 663 | |
| mbed_official | 324:406fd2029f23 | 664 | /*! |
| mbed_official | 324:406fd2029f23 | 665 | * @name Register MCM_CPO, field CPOWOI[2] (RW) |
| mbed_official | 324:406fd2029f23 | 666 | * |
| mbed_official | 324:406fd2029f23 | 667 | * Values: |
| mbed_official | 324:406fd2029f23 | 668 | * - 0 - No effect. |
| mbed_official | 324:406fd2029f23 | 669 | * - 1 - When set, the CPOREQ is cleared on any interrupt or exception vector |
| mbed_official | 324:406fd2029f23 | 670 | * fetch. |
| mbed_official | 324:406fd2029f23 | 671 | */ |
| mbed_official | 324:406fd2029f23 | 672 | /*@{*/ |
| mbed_official | 324:406fd2029f23 | 673 | #define BP_MCM_CPO_CPOWOI (2U) /*!< Bit position for MCM_CPO_CPOWOI. */ |
| mbed_official | 324:406fd2029f23 | 674 | #define BM_MCM_CPO_CPOWOI (0x00000004U) /*!< Bit mask for MCM_CPO_CPOWOI. */ |
| mbed_official | 324:406fd2029f23 | 675 | #define BS_MCM_CPO_CPOWOI (1U) /*!< Bit field size in bits for MCM_CPO_CPOWOI. */ |
| mbed_official | 324:406fd2029f23 | 676 | |
| mbed_official | 324:406fd2029f23 | 677 | /*! @brief Read current value of the MCM_CPO_CPOWOI field. */ |
| mbed_official | 324:406fd2029f23 | 678 | #define BR_MCM_CPO_CPOWOI(x) (HW_MCM_CPO(x).B.CPOWOI) |
| mbed_official | 324:406fd2029f23 | 679 | |
| mbed_official | 324:406fd2029f23 | 680 | /*! @brief Format value for bitfield MCM_CPO_CPOWOI. */ |
| mbed_official | 324:406fd2029f23 | 681 | #define BF_MCM_CPO_CPOWOI(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CPO_CPOWOI) & BM_MCM_CPO_CPOWOI) |
| mbed_official | 324:406fd2029f23 | 682 | |
| mbed_official | 324:406fd2029f23 | 683 | /*! @brief Set the CPOWOI field to a new value. */ |
| mbed_official | 324:406fd2029f23 | 684 | #define BW_MCM_CPO_CPOWOI(x, v) (HW_MCM_CPO_WR(x, (HW_MCM_CPO_RD(x) & ~BM_MCM_CPO_CPOWOI) | BF_MCM_CPO_CPOWOI(v))) |
| mbed_official | 324:406fd2029f23 | 685 | /*@}*/ |
| mbed_official | 324:406fd2029f23 | 686 | |
| mbed_official | 324:406fd2029f23 | 687 | /******************************************************************************* |
| mbed_official | 324:406fd2029f23 | 688 | * hw_mcm_t - module struct |
| mbed_official | 324:406fd2029f23 | 689 | ******************************************************************************/ |
| mbed_official | 324:406fd2029f23 | 690 | /*! |
| mbed_official | 324:406fd2029f23 | 691 | * @brief All MCM module registers. |
| mbed_official | 324:406fd2029f23 | 692 | */ |
| mbed_official | 324:406fd2029f23 | 693 | #pragma pack(1) |
| mbed_official | 324:406fd2029f23 | 694 | typedef struct _hw_mcm |
| mbed_official | 324:406fd2029f23 | 695 | { |
| mbed_official | 324:406fd2029f23 | 696 | uint8_t _reserved0[8]; |
| mbed_official | 324:406fd2029f23 | 697 | __I hw_mcm_plasc_t PLASC; /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */ |
| mbed_official | 324:406fd2029f23 | 698 | __I hw_mcm_plamc_t PLAMC; /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */ |
| mbed_official | 324:406fd2029f23 | 699 | __IO hw_mcm_placr_t PLACR; /*!< [0xC] Crossbar Switch (AXBS) Control Register */ |
| mbed_official | 324:406fd2029f23 | 700 | __IO hw_mcm_iscr_t ISCR; /*!< [0x10] Interrupt Status and Control Register */ |
| mbed_official | 324:406fd2029f23 | 701 | uint8_t _reserved1[44]; |
| mbed_official | 324:406fd2029f23 | 702 | __IO hw_mcm_cpo_t CPO; /*!< [0x40] Compute Operation Control Register */ |
| mbed_official | 324:406fd2029f23 | 703 | } hw_mcm_t; |
| mbed_official | 324:406fd2029f23 | 704 | #pragma pack() |
| mbed_official | 324:406fd2029f23 | 705 | |
| mbed_official | 324:406fd2029f23 | 706 | /*! @brief Macro to access all MCM registers. */ |
| mbed_official | 324:406fd2029f23 | 707 | /*! @param x MCM module instance base address. */ |
| mbed_official | 324:406fd2029f23 | 708 | /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, |
| mbed_official | 324:406fd2029f23 | 709 | * use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */ |
| mbed_official | 324:406fd2029f23 | 710 | #define HW_MCM(x) (*(hw_mcm_t *)(x)) |
| mbed_official | 324:406fd2029f23 | 711 | |
| mbed_official | 324:406fd2029f23 | 712 | #endif /* __HW_MCM_REGISTERS_H__ */ |
| mbed_official | 324:406fd2029f23 | 713 | /* EOF */ |
