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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_lpuart.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-05-06
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-07-23)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 1.1 (2013-09-17)
mbed_official	324:406fd2029f23	50	** RM rev. 0.4 update.
mbed_official	324:406fd2029f23	51	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	52	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	53	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	54	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	55	** System initialization updated.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-20)
mbed_official	324:406fd2029f23	59	** Update according to reference manual rev. 0.6,
mbed_official	324:406fd2029f23	60	** - rev. 2.3 (2014-01-13)
mbed_official	324:406fd2029f23	61	** Update according to reference manual rev. 0.61,
mbed_official	324:406fd2029f23	62	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	63	** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official	324:406fd2029f23	64	** - rev. 2.5 (2014-05-06)
mbed_official	324:406fd2029f23	65	** Update according to reference manual rev. 1.0,
mbed_official	324:406fd2029f23	66	** Update of system and startup files.
mbed_official	324:406fd2029f23	67	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	68	**
mbed_official	324:406fd2029f23	69	** ###################################################################
mbed_official	324:406fd2029f23	70	*/
mbed_official	324:406fd2029f23	71
mbed_official	324:406fd2029f23	72	/*
mbed_official	324:406fd2029f23	73	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	74	*
mbed_official	324:406fd2029f23	75	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	76	*/
mbed_official	324:406fd2029f23	77	#ifndef __HW_LPUART_REGISTERS_H__
mbed_official	324:406fd2029f23	78	#define __HW_LPUART_REGISTERS_H__
mbed_official	324:406fd2029f23	79
mbed_official	324:406fd2029f23	80	#include "MK22F51212.h"
mbed_official	324:406fd2029f23	81	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	/*
mbed_official	324:406fd2029f23	84	* MK22F51212 LPUART
mbed_official	324:406fd2029f23	85	*
mbed_official	324:406fd2029f23	86	* Universal Asynchronous Receiver/Transmitter
mbed_official	324:406fd2029f23	87	*
mbed_official	324:406fd2029f23	88	* Registers defined in this header file:
mbed_official	324:406fd2029f23	89	* - HW_LPUART_BAUD - LPUART Baud Rate Register
mbed_official	324:406fd2029f23	90	* - HW_LPUART_STAT - LPUART Status Register
mbed_official	324:406fd2029f23	91	* - HW_LPUART_CTRL - LPUART Control Register
mbed_official	324:406fd2029f23	92	* - HW_LPUART_DATA - LPUART Data Register
mbed_official	324:406fd2029f23	93	* - HW_LPUART_MATCH - LPUART Match Address Register
mbed_official	324:406fd2029f23	94	* - HW_LPUART_MODIR - LPUART Modem IrDA Register
mbed_official	324:406fd2029f23	95	*
mbed_official	324:406fd2029f23	96	* - hw_lpuart_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	97	*/
mbed_official	324:406fd2029f23	98
mbed_official	324:406fd2029f23	99	#define HW_LPUART_INSTANCE_COUNT (1U) /!< Number of instances of the LPUART module. /
mbed_official	324:406fd2029f23	100
mbed_official	324:406fd2029f23	101	/*******************************************************************************
mbed_official	324:406fd2029f23	102	* HW_LPUART_BAUD - LPUART Baud Rate Register
mbed_official	324:406fd2029f23	103	******************************************************************************/
mbed_official	324:406fd2029f23	104
mbed_official	324:406fd2029f23	105	/*!
mbed_official	324:406fd2029f23	106	* @brief HW_LPUART_BAUD - LPUART Baud Rate Register (RW)
mbed_official	324:406fd2029f23	107	*
mbed_official	324:406fd2029f23	108	* Reset value: 0x0F000004U
mbed_official	324:406fd2029f23	109	*/
mbed_official	324:406fd2029f23	110	typedef union _hw_lpuart_baud
mbed_official	324:406fd2029f23	111	{
mbed_official	324:406fd2029f23	112	uint32_t U;
mbed_official	324:406fd2029f23	113	struct _hw_lpuart_baud_bitfields
mbed_official	324:406fd2029f23	114	{
mbed_official	324:406fd2029f23	115	uint32_t SBR : 13; /!< [12:0] Baud Rate Modulo Divisor. /
mbed_official	324:406fd2029f23	116	uint32_t SBNS : 1; /!< [13] Stop Bit Number Select /
mbed_official	324:406fd2029f23	117	uint32_t RXEDGIE : 1; /*!< [14] RX Input Active Edge Interrupt Enable
mbed_official	324:406fd2029f23	118	* */
mbed_official	324:406fd2029f23	119	uint32_t LBKDIE : 1; /!< [15] LIN Break Detect Interrupt Enable /
mbed_official	324:406fd2029f23	120	uint32_t RESYNCDIS : 1; /!< [16] Resynchronization Disable /
mbed_official	324:406fd2029f23	121	uint32_t BOTHEDGE : 1; /!< [17] Both Edge Sampling /
mbed_official	324:406fd2029f23	122	uint32_t MATCFG : 2; /!< [19:18] Match Configuration /
mbed_official	324:406fd2029f23	123	uint32_t RESERVED0 : 1; /!< [20] /
mbed_official	324:406fd2029f23	124	uint32_t RDMAE : 1; /!< [21] Receiver Full DMA Enable /
mbed_official	324:406fd2029f23	125	uint32_t RESERVED1 : 1; /!< [22] /
mbed_official	324:406fd2029f23	126	uint32_t TDMAE : 1; /!< [23] Transmitter DMA Enable /
mbed_official	324:406fd2029f23	127	uint32_t OSR : 5; /!< [28:24] Over Sampling Ratio /
mbed_official	324:406fd2029f23	128	uint32_t M10 : 1; /!< [29] 10-bit Mode select /
mbed_official	324:406fd2029f23	129	uint32_t MAEN2 : 1; /!< [30] Match Address Mode Enable 2 /
mbed_official	324:406fd2029f23	130	uint32_t MAEN1 : 1; /!< [31] Match Address Mode Enable 1 /
mbed_official	324:406fd2029f23	131	} B;
mbed_official	324:406fd2029f23	132	} hw_lpuart_baud_t;
mbed_official	324:406fd2029f23	133
mbed_official	324:406fd2029f23	134	/*!
mbed_official	324:406fd2029f23	135	* @name Constants and macros for entire LPUART_BAUD register
mbed_official	324:406fd2029f23	136	*/
mbed_official	324:406fd2029f23	137	/@{/
mbed_official	324:406fd2029f23	138	#define HW_LPUART_BAUD_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	139
mbed_official	324:406fd2029f23	140	#define HW_LPUART_BAUD(x) ((__IO hw_lpuart_baud_t ) HW_LPUART_BAUD_ADDR(x))
mbed_official	324:406fd2029f23	141	#define HW_LPUART_BAUD_RD(x) (HW_LPUART_BAUD(x).U)
mbed_official	324:406fd2029f23	142	#define HW_LPUART_BAUD_WR(x, v) (HW_LPUART_BAUD(x).U = (v))
mbed_official	324:406fd2029f23	143	#define HW_LPUART_BAUD_SET(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) \| (v)))
mbed_official	324:406fd2029f23	144	#define HW_LPUART_BAUD_CLR(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	145	#define HW_LPUART_BAUD_TOG(x, v) (HW_LPUART_BAUD_WR(x, HW_LPUART_BAUD_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	146	/@}/
mbed_official	324:406fd2029f23	147
mbed_official	324:406fd2029f23	148	/*
mbed_official	324:406fd2029f23	149	* Constants & macros for individual LPUART_BAUD bitfields
mbed_official	324:406fd2029f23	150	*/
mbed_official	324:406fd2029f23	151
mbed_official	324:406fd2029f23	152	/*!
mbed_official	324:406fd2029f23	153	* @name Register LPUART_BAUD, field SBR[12:0] (RW)
mbed_official	324:406fd2029f23	154	*
mbed_official	324:406fd2029f23	155	* The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate
mbed_official	324:406fd2029f23	156	* generator. When SBR is 1 - 8191, the baud rate equals "baud clock / ((OSR+1) * SBR)".
mbed_official	324:406fd2029f23	157	* The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the
mbed_official	324:406fd2029f23	158	* transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are
mbed_official	324:406fd2029f23	159	* both 0).
mbed_official	324:406fd2029f23	160	*/
mbed_official	324:406fd2029f23	161	/@{/
mbed_official	324:406fd2029f23	162	#define BP_LPUART_BAUD_SBR (0U) /!< Bit position for LPUART_BAUD_SBR. /
mbed_official	324:406fd2029f23	163	#define BM_LPUART_BAUD_SBR (0x00001FFFU) /!< Bit mask for LPUART_BAUD_SBR. /
mbed_official	324:406fd2029f23	164	#define BS_LPUART_BAUD_SBR (13U) /!< Bit field size in bits for LPUART_BAUD_SBR. /
mbed_official	324:406fd2029f23	165
mbed_official	324:406fd2029f23	166	/! @brief Read current value of the LPUART_BAUD_SBR field. /
mbed_official	324:406fd2029f23	167	#define BR_LPUART_BAUD_SBR(x) (HW_LPUART_BAUD(x).B.SBR)
mbed_official	324:406fd2029f23	168
mbed_official	324:406fd2029f23	169	/! @brief Format value for bitfield LPUART_BAUD_SBR. /
mbed_official	324:406fd2029f23	170	#define BF_LPUART_BAUD_SBR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_SBR) & BM_LPUART_BAUD_SBR)
mbed_official	324:406fd2029f23	171
mbed_official	324:406fd2029f23	172	/! @brief Set the SBR field to a new value. /
mbed_official	324:406fd2029f23	173	#define BW_LPUART_BAUD_SBR(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_SBR) \| BF_LPUART_BAUD_SBR(v)))
mbed_official	324:406fd2029f23	174	/@}/
mbed_official	324:406fd2029f23	175
mbed_official	324:406fd2029f23	176	/*!
mbed_official	324:406fd2029f23	177	* @name Register LPUART_BAUD, field SBNS[13] (RW)
mbed_official	324:406fd2029f23	178	*
mbed_official	324:406fd2029f23	179	* SBNS determines whether data characters are one or two stop bits. This bit
mbed_official	324:406fd2029f23	180	* should only be changed when the transmitter and receiver are both disabled.
mbed_official	324:406fd2029f23	181	*
mbed_official	324:406fd2029f23	182	* Values:
mbed_official	324:406fd2029f23	183	* - 0 - One stop bit.
mbed_official	324:406fd2029f23	184	* - 1 - Two stop bits.
mbed_official	324:406fd2029f23	185	*/
mbed_official	324:406fd2029f23	186	/@{/
mbed_official	324:406fd2029f23	187	#define BP_LPUART_BAUD_SBNS (13U) /!< Bit position for LPUART_BAUD_SBNS. /
mbed_official	324:406fd2029f23	188	#define BM_LPUART_BAUD_SBNS (0x00002000U) /!< Bit mask for LPUART_BAUD_SBNS. /
mbed_official	324:406fd2029f23	189	#define BS_LPUART_BAUD_SBNS (1U) /!< Bit field size in bits for LPUART_BAUD_SBNS. /
mbed_official	324:406fd2029f23	190
mbed_official	324:406fd2029f23	191	/! @brief Read current value of the LPUART_BAUD_SBNS field. /
mbed_official	324:406fd2029f23	192	#define BR_LPUART_BAUD_SBNS(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_SBNS))
mbed_official	324:406fd2029f23	193
mbed_official	324:406fd2029f23	194	/! @brief Format value for bitfield LPUART_BAUD_SBNS. /
mbed_official	324:406fd2029f23	195	#define BF_LPUART_BAUD_SBNS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_SBNS) & BM_LPUART_BAUD_SBNS)
mbed_official	324:406fd2029f23	196
mbed_official	324:406fd2029f23	197	/! @brief Set the SBNS field to a new value. /
mbed_official	324:406fd2029f23	198	#define BW_LPUART_BAUD_SBNS(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_SBNS) = (v))
mbed_official	324:406fd2029f23	199	/@}/
mbed_official	324:406fd2029f23	200
mbed_official	324:406fd2029f23	201	/*!
mbed_official	324:406fd2029f23	202	* @name Register LPUART_BAUD, field RXEDGIE[14] (RW)
mbed_official	324:406fd2029f23	203	*
mbed_official	324:406fd2029f23	204	* Enables the receive input active edge, RXEDGIF, to generate interrupt
mbed_official	324:406fd2029f23	205	* requests. Changing CTRL[LOOP] or CTRL[RSRC] when RXEDGIE is set can cause the RXEDGIF
mbed_official	324:406fd2029f23	206	* to set.
mbed_official	324:406fd2029f23	207	*
mbed_official	324:406fd2029f23	208	* Values:
mbed_official	324:406fd2029f23	209	* - 0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
mbed_official	324:406fd2029f23	210	* - 1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
mbed_official	324:406fd2029f23	211	*/
mbed_official	324:406fd2029f23	212	/@{/
mbed_official	324:406fd2029f23	213	#define BP_LPUART_BAUD_RXEDGIE (14U) /!< Bit position for LPUART_BAUD_RXEDGIE. /
mbed_official	324:406fd2029f23	214	#define BM_LPUART_BAUD_RXEDGIE (0x00004000U) /!< Bit mask for LPUART_BAUD_RXEDGIE. /
mbed_official	324:406fd2029f23	215	#define BS_LPUART_BAUD_RXEDGIE (1U) /!< Bit field size in bits for LPUART_BAUD_RXEDGIE. /
mbed_official	324:406fd2029f23	216
mbed_official	324:406fd2029f23	217	/! @brief Read current value of the LPUART_BAUD_RXEDGIE field. /
mbed_official	324:406fd2029f23	218	#define BR_LPUART_BAUD_RXEDGIE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RXEDGIE))
mbed_official	324:406fd2029f23	219
mbed_official	324:406fd2029f23	220	/! @brief Format value for bitfield LPUART_BAUD_RXEDGIE. /
mbed_official	324:406fd2029f23	221	#define BF_LPUART_BAUD_RXEDGIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RXEDGIE) & BM_LPUART_BAUD_RXEDGIE)
mbed_official	324:406fd2029f23	222
mbed_official	324:406fd2029f23	223	/! @brief Set the RXEDGIE field to a new value. /
mbed_official	324:406fd2029f23	224	#define BW_LPUART_BAUD_RXEDGIE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RXEDGIE) = (v))
mbed_official	324:406fd2029f23	225	/@}/
mbed_official	324:406fd2029f23	226
mbed_official	324:406fd2029f23	227	/*!
mbed_official	324:406fd2029f23	228	* @name Register LPUART_BAUD, field LBKDIE[15] (RW)
mbed_official	324:406fd2029f23	229	*
mbed_official	324:406fd2029f23	230	* LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt
mbed_official	324:406fd2029f23	231	* requests.
mbed_official	324:406fd2029f23	232	*
mbed_official	324:406fd2029f23	233	* Values:
mbed_official	324:406fd2029f23	234	* - 0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
mbed_official	324:406fd2029f23	235	* - 1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
mbed_official	324:406fd2029f23	236	*/
mbed_official	324:406fd2029f23	237	/@{/
mbed_official	324:406fd2029f23	238	#define BP_LPUART_BAUD_LBKDIE (15U) /!< Bit position for LPUART_BAUD_LBKDIE. /
mbed_official	324:406fd2029f23	239	#define BM_LPUART_BAUD_LBKDIE (0x00008000U) /!< Bit mask for LPUART_BAUD_LBKDIE. /
mbed_official	324:406fd2029f23	240	#define BS_LPUART_BAUD_LBKDIE (1U) /!< Bit field size in bits for LPUART_BAUD_LBKDIE. /
mbed_official	324:406fd2029f23	241
mbed_official	324:406fd2029f23	242	/! @brief Read current value of the LPUART_BAUD_LBKDIE field. /
mbed_official	324:406fd2029f23	243	#define BR_LPUART_BAUD_LBKDIE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_LBKDIE))
mbed_official	324:406fd2029f23	244
mbed_official	324:406fd2029f23	245	/! @brief Format value for bitfield LPUART_BAUD_LBKDIE. /
mbed_official	324:406fd2029f23	246	#define BF_LPUART_BAUD_LBKDIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_LBKDIE) & BM_LPUART_BAUD_LBKDIE)
mbed_official	324:406fd2029f23	247
mbed_official	324:406fd2029f23	248	/! @brief Set the LBKDIE field to a new value. /
mbed_official	324:406fd2029f23	249	#define BW_LPUART_BAUD_LBKDIE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_LBKDIE) = (v))
mbed_official	324:406fd2029f23	250	/@}/
mbed_official	324:406fd2029f23	251
mbed_official	324:406fd2029f23	252	/*!
mbed_official	324:406fd2029f23	253	* @name Register LPUART_BAUD, field RESYNCDIS[16] (RW)
mbed_official	324:406fd2029f23	254	*
mbed_official	324:406fd2029f23	255	* When set, disables the resynchronization of the received data word when a
mbed_official	324:406fd2029f23	256	* data one followed by data zero transition is detected. This bit should only be
mbed_official	324:406fd2029f23	257	* changed when the receiver is disabled.
mbed_official	324:406fd2029f23	258	*
mbed_official	324:406fd2029f23	259	* Values:
mbed_official	324:406fd2029f23	260	* - 0 - Resynchronization during received data word is supported
mbed_official	324:406fd2029f23	261	* - 1 - Resynchronization during received data word is disabled
mbed_official	324:406fd2029f23	262	*/
mbed_official	324:406fd2029f23	263	/@{/
mbed_official	324:406fd2029f23	264	#define BP_LPUART_BAUD_RESYNCDIS (16U) /!< Bit position for LPUART_BAUD_RESYNCDIS. /
mbed_official	324:406fd2029f23	265	#define BM_LPUART_BAUD_RESYNCDIS (0x00010000U) /!< Bit mask for LPUART_BAUD_RESYNCDIS. /
mbed_official	324:406fd2029f23	266	#define BS_LPUART_BAUD_RESYNCDIS (1U) /!< Bit field size in bits for LPUART_BAUD_RESYNCDIS. /
mbed_official	324:406fd2029f23	267
mbed_official	324:406fd2029f23	268	/! @brief Read current value of the LPUART_BAUD_RESYNCDIS field. /
mbed_official	324:406fd2029f23	269	#define BR_LPUART_BAUD_RESYNCDIS(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RESYNCDIS))
mbed_official	324:406fd2029f23	270
mbed_official	324:406fd2029f23	271	/! @brief Format value for bitfield LPUART_BAUD_RESYNCDIS. /
mbed_official	324:406fd2029f23	272	#define BF_LPUART_BAUD_RESYNCDIS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RESYNCDIS) & BM_LPUART_BAUD_RESYNCDIS)
mbed_official	324:406fd2029f23	273
mbed_official	324:406fd2029f23	274	/! @brief Set the RESYNCDIS field to a new value. /
mbed_official	324:406fd2029f23	275	#define BW_LPUART_BAUD_RESYNCDIS(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RESYNCDIS) = (v))
mbed_official	324:406fd2029f23	276	/@}/
mbed_official	324:406fd2029f23	277
mbed_official	324:406fd2029f23	278	/*!
mbed_official	324:406fd2029f23	279	* @name Register LPUART_BAUD, field BOTHEDGE[17] (RW)
mbed_official	324:406fd2029f23	280	*
mbed_official	324:406fd2029f23	281	* Enables sampling of the received data on both edges of the baud rate clock,
mbed_official	324:406fd2029f23	282	* effectively doubling the number of times the receiver samples the input data
mbed_official	324:406fd2029f23	283	* for a given oversampling ratio. This bit must be set for oversampling ratios
mbed_official	324:406fd2029f23	284	* between x4 and x7 and is optional for higher oversampling ratios. This bit should
mbed_official	324:406fd2029f23	285	* only be changed when the receiver is disabled.
mbed_official	324:406fd2029f23	286	*
mbed_official	324:406fd2029f23	287	* Values:
mbed_official	324:406fd2029f23	288	* - 0 - Receiver samples input data using the rising edge of the baud rate
mbed_official	324:406fd2029f23	289	* clock.
mbed_official	324:406fd2029f23	290	* - 1 - Receiver samples input data using the rising and falling edge of the
mbed_official	324:406fd2029f23	291	* baud rate clock.
mbed_official	324:406fd2029f23	292	*/
mbed_official	324:406fd2029f23	293	/@{/
mbed_official	324:406fd2029f23	294	#define BP_LPUART_BAUD_BOTHEDGE (17U) /!< Bit position for LPUART_BAUD_BOTHEDGE. /
mbed_official	324:406fd2029f23	295	#define BM_LPUART_BAUD_BOTHEDGE (0x00020000U) /!< Bit mask for LPUART_BAUD_BOTHEDGE. /
mbed_official	324:406fd2029f23	296	#define BS_LPUART_BAUD_BOTHEDGE (1U) /!< Bit field size in bits for LPUART_BAUD_BOTHEDGE. /
mbed_official	324:406fd2029f23	297
mbed_official	324:406fd2029f23	298	/! @brief Read current value of the LPUART_BAUD_BOTHEDGE field. /
mbed_official	324:406fd2029f23	299	#define BR_LPUART_BAUD_BOTHEDGE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_BOTHEDGE))
mbed_official	324:406fd2029f23	300
mbed_official	324:406fd2029f23	301	/! @brief Format value for bitfield LPUART_BAUD_BOTHEDGE. /
mbed_official	324:406fd2029f23	302	#define BF_LPUART_BAUD_BOTHEDGE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_BOTHEDGE) & BM_LPUART_BAUD_BOTHEDGE)
mbed_official	324:406fd2029f23	303
mbed_official	324:406fd2029f23	304	/! @brief Set the BOTHEDGE field to a new value. /
mbed_official	324:406fd2029f23	305	#define BW_LPUART_BAUD_BOTHEDGE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_BOTHEDGE) = (v))
mbed_official	324:406fd2029f23	306	/@}/
mbed_official	324:406fd2029f23	307
mbed_official	324:406fd2029f23	308	/*!
mbed_official	324:406fd2029f23	309	* @name Register LPUART_BAUD, field MATCFG[19:18] (RW)
mbed_official	324:406fd2029f23	310	*
mbed_official	324:406fd2029f23	311	* Configures the match addressing mode used.
mbed_official	324:406fd2029f23	312	*
mbed_official	324:406fd2029f23	313	* Values:
mbed_official	324:406fd2029f23	314	* - 00 - Address Match Wakeup
mbed_official	324:406fd2029f23	315	* - 01 - Idle Match Wakeup
mbed_official	324:406fd2029f23	316	* - 10 - Match On and Match Off
mbed_official	324:406fd2029f23	317	* - 11 - Enables RWU on Data Match and Match On/Off for transmitter CTS input
mbed_official	324:406fd2029f23	318	*/
mbed_official	324:406fd2029f23	319	/@{/
mbed_official	324:406fd2029f23	320	#define BP_LPUART_BAUD_MATCFG (18U) /!< Bit position for LPUART_BAUD_MATCFG. /
mbed_official	324:406fd2029f23	321	#define BM_LPUART_BAUD_MATCFG (0x000C0000U) /!< Bit mask for LPUART_BAUD_MATCFG. /
mbed_official	324:406fd2029f23	322	#define BS_LPUART_BAUD_MATCFG (2U) /!< Bit field size in bits for LPUART_BAUD_MATCFG. /
mbed_official	324:406fd2029f23	323
mbed_official	324:406fd2029f23	324	/! @brief Read current value of the LPUART_BAUD_MATCFG field. /
mbed_official	324:406fd2029f23	325	#define BR_LPUART_BAUD_MATCFG(x) (HW_LPUART_BAUD(x).B.MATCFG)
mbed_official	324:406fd2029f23	326
mbed_official	324:406fd2029f23	327	/! @brief Format value for bitfield LPUART_BAUD_MATCFG. /
mbed_official	324:406fd2029f23	328	#define BF_LPUART_BAUD_MATCFG(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MATCFG) & BM_LPUART_BAUD_MATCFG)
mbed_official	324:406fd2029f23	329
mbed_official	324:406fd2029f23	330	/! @brief Set the MATCFG field to a new value. /
mbed_official	324:406fd2029f23	331	#define BW_LPUART_BAUD_MATCFG(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_MATCFG) \| BF_LPUART_BAUD_MATCFG(v)))
mbed_official	324:406fd2029f23	332	/@}/
mbed_official	324:406fd2029f23	333
mbed_official	324:406fd2029f23	334	/*!
mbed_official	324:406fd2029f23	335	* @name Register LPUART_BAUD, field RDMAE[21] (RW)
mbed_official	324:406fd2029f23	336	*
mbed_official	324:406fd2029f23	337	* RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to
mbed_official	324:406fd2029f23	338	* generate a DMA request.
mbed_official	324:406fd2029f23	339	*
mbed_official	324:406fd2029f23	340	* Values:
mbed_official	324:406fd2029f23	341	* - 0 - DMA request disabled.
mbed_official	324:406fd2029f23	342	* - 1 - DMA request enabled.
mbed_official	324:406fd2029f23	343	*/
mbed_official	324:406fd2029f23	344	/@{/
mbed_official	324:406fd2029f23	345	#define BP_LPUART_BAUD_RDMAE (21U) /!< Bit position for LPUART_BAUD_RDMAE. /
mbed_official	324:406fd2029f23	346	#define BM_LPUART_BAUD_RDMAE (0x00200000U) /!< Bit mask for LPUART_BAUD_RDMAE. /
mbed_official	324:406fd2029f23	347	#define BS_LPUART_BAUD_RDMAE (1U) /!< Bit field size in bits for LPUART_BAUD_RDMAE. /
mbed_official	324:406fd2029f23	348
mbed_official	324:406fd2029f23	349	/! @brief Read current value of the LPUART_BAUD_RDMAE field. /
mbed_official	324:406fd2029f23	350	#define BR_LPUART_BAUD_RDMAE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RDMAE))
mbed_official	324:406fd2029f23	351
mbed_official	324:406fd2029f23	352	/! @brief Format value for bitfield LPUART_BAUD_RDMAE. /
mbed_official	324:406fd2029f23	353	#define BF_LPUART_BAUD_RDMAE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_RDMAE) & BM_LPUART_BAUD_RDMAE)
mbed_official	324:406fd2029f23	354
mbed_official	324:406fd2029f23	355	/! @brief Set the RDMAE field to a new value. /
mbed_official	324:406fd2029f23	356	#define BW_LPUART_BAUD_RDMAE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_RDMAE) = (v))
mbed_official	324:406fd2029f23	357	/@}/
mbed_official	324:406fd2029f23	358
mbed_official	324:406fd2029f23	359	/*!
mbed_official	324:406fd2029f23	360	* @name Register LPUART_BAUD, field TDMAE[23] (RW)
mbed_official	324:406fd2029f23	361	*
mbed_official	324:406fd2029f23	362	* TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to
mbed_official	324:406fd2029f23	363	* generate a DMA request.
mbed_official	324:406fd2029f23	364	*
mbed_official	324:406fd2029f23	365	* Values:
mbed_official	324:406fd2029f23	366	* - 0 - DMA request disabled.
mbed_official	324:406fd2029f23	367	* - 1 - DMA request enabled.
mbed_official	324:406fd2029f23	368	*/
mbed_official	324:406fd2029f23	369	/@{/
mbed_official	324:406fd2029f23	370	#define BP_LPUART_BAUD_TDMAE (23U) /!< Bit position for LPUART_BAUD_TDMAE. /
mbed_official	324:406fd2029f23	371	#define BM_LPUART_BAUD_TDMAE (0x00800000U) /!< Bit mask for LPUART_BAUD_TDMAE. /
mbed_official	324:406fd2029f23	372	#define BS_LPUART_BAUD_TDMAE (1U) /!< Bit field size in bits for LPUART_BAUD_TDMAE. /
mbed_official	324:406fd2029f23	373
mbed_official	324:406fd2029f23	374	/! @brief Read current value of the LPUART_BAUD_TDMAE field. /
mbed_official	324:406fd2029f23	375	#define BR_LPUART_BAUD_TDMAE(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_TDMAE))
mbed_official	324:406fd2029f23	376
mbed_official	324:406fd2029f23	377	/! @brief Format value for bitfield LPUART_BAUD_TDMAE. /
mbed_official	324:406fd2029f23	378	#define BF_LPUART_BAUD_TDMAE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_TDMAE) & BM_LPUART_BAUD_TDMAE)
mbed_official	324:406fd2029f23	379
mbed_official	324:406fd2029f23	380	/! @brief Set the TDMAE field to a new value. /
mbed_official	324:406fd2029f23	381	#define BW_LPUART_BAUD_TDMAE(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_TDMAE) = (v))
mbed_official	324:406fd2029f23	382	/@}/
mbed_official	324:406fd2029f23	383
mbed_official	324:406fd2029f23	384	/*!
mbed_official	324:406fd2029f23	385	* @name Register LPUART_BAUD, field OSR[28:24] (RW)
mbed_official	324:406fd2029f23	386	*
mbed_official	324:406fd2029f23	387	* This field configures the oversampling ratio for the receiver between 4x
mbed_official	324:406fd2029f23	388	* (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an
mbed_official	324:406fd2029f23	389	* oversampling ratio of 16 (01111). This field should only be changed when the
mbed_official	324:406fd2029f23	390	* transmitter and receiver are both disabled.
mbed_official	324:406fd2029f23	391	*/
mbed_official	324:406fd2029f23	392	/@{/
mbed_official	324:406fd2029f23	393	#define BP_LPUART_BAUD_OSR (24U) /!< Bit position for LPUART_BAUD_OSR. /
mbed_official	324:406fd2029f23	394	#define BM_LPUART_BAUD_OSR (0x1F000000U) /!< Bit mask for LPUART_BAUD_OSR. /
mbed_official	324:406fd2029f23	395	#define BS_LPUART_BAUD_OSR (5U) /!< Bit field size in bits for LPUART_BAUD_OSR. /
mbed_official	324:406fd2029f23	396
mbed_official	324:406fd2029f23	397	/! @brief Read current value of the LPUART_BAUD_OSR field. /
mbed_official	324:406fd2029f23	398	#define BR_LPUART_BAUD_OSR(x) (HW_LPUART_BAUD(x).B.OSR)
mbed_official	324:406fd2029f23	399
mbed_official	324:406fd2029f23	400	/! @brief Format value for bitfield LPUART_BAUD_OSR. /
mbed_official	324:406fd2029f23	401	#define BF_LPUART_BAUD_OSR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_OSR) & BM_LPUART_BAUD_OSR)
mbed_official	324:406fd2029f23	402
mbed_official	324:406fd2029f23	403	/! @brief Set the OSR field to a new value. /
mbed_official	324:406fd2029f23	404	#define BW_LPUART_BAUD_OSR(x, v) (HW_LPUART_BAUD_WR(x, (HW_LPUART_BAUD_RD(x) & ~BM_LPUART_BAUD_OSR) \| BF_LPUART_BAUD_OSR(v)))
mbed_official	324:406fd2029f23	405	/@}/
mbed_official	324:406fd2029f23	406
mbed_official	324:406fd2029f23	407	/*!
mbed_official	324:406fd2029f23	408	* @name Register LPUART_BAUD, field M10[29] (RW)
mbed_official	324:406fd2029f23	409	*
mbed_official	324:406fd2029f23	410	* The M10 bit causes a tenth bit to be part of the serial transmission. This
mbed_official	324:406fd2029f23	411	* bit should only be changed when the transmitter and receiver are both disabled.
mbed_official	324:406fd2029f23	412	*
mbed_official	324:406fd2029f23	413	* Values:
mbed_official	324:406fd2029f23	414	* - 0 - Receiver and transmitter use 8-bit or 9-bit data characters.
mbed_official	324:406fd2029f23	415	* - 1 - Receiver and transmitter use 10-bit data characters.
mbed_official	324:406fd2029f23	416	*/
mbed_official	324:406fd2029f23	417	/@{/
mbed_official	324:406fd2029f23	418	#define BP_LPUART_BAUD_M10 (29U) /!< Bit position for LPUART_BAUD_M10. /
mbed_official	324:406fd2029f23	419	#define BM_LPUART_BAUD_M10 (0x20000000U) /!< Bit mask for LPUART_BAUD_M10. /
mbed_official	324:406fd2029f23	420	#define BS_LPUART_BAUD_M10 (1U) /!< Bit field size in bits for LPUART_BAUD_M10. /
mbed_official	324:406fd2029f23	421
mbed_official	324:406fd2029f23	422	/! @brief Read current value of the LPUART_BAUD_M10 field. /
mbed_official	324:406fd2029f23	423	#define BR_LPUART_BAUD_M10(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_M10))
mbed_official	324:406fd2029f23	424
mbed_official	324:406fd2029f23	425	/! @brief Format value for bitfield LPUART_BAUD_M10. /
mbed_official	324:406fd2029f23	426	#define BF_LPUART_BAUD_M10(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_M10) & BM_LPUART_BAUD_M10)
mbed_official	324:406fd2029f23	427
mbed_official	324:406fd2029f23	428	/! @brief Set the M10 field to a new value. /
mbed_official	324:406fd2029f23	429	#define BW_LPUART_BAUD_M10(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_M10) = (v))
mbed_official	324:406fd2029f23	430	/@}/
mbed_official	324:406fd2029f23	431
mbed_official	324:406fd2029f23	432	/*!
mbed_official	324:406fd2029f23	433	* @name Register LPUART_BAUD, field MAEN2[30] (RW)
mbed_official	324:406fd2029f23	434	*
mbed_official	324:406fd2029f23	435	* Values:
mbed_official	324:406fd2029f23	436	* - 0 - Normal operation.
mbed_official	324:406fd2029f23	437	* - 1 - Enables automatic address matching or data matching mode for MATCH[MA2].
mbed_official	324:406fd2029f23	438	*/
mbed_official	324:406fd2029f23	439	/@{/
mbed_official	324:406fd2029f23	440	#define BP_LPUART_BAUD_MAEN2 (30U) /!< Bit position for LPUART_BAUD_MAEN2. /
mbed_official	324:406fd2029f23	441	#define BM_LPUART_BAUD_MAEN2 (0x40000000U) /!< Bit mask for LPUART_BAUD_MAEN2. /
mbed_official	324:406fd2029f23	442	#define BS_LPUART_BAUD_MAEN2 (1U) /!< Bit field size in bits for LPUART_BAUD_MAEN2. /
mbed_official	324:406fd2029f23	443
mbed_official	324:406fd2029f23	444	/! @brief Read current value of the LPUART_BAUD_MAEN2 field. /
mbed_official	324:406fd2029f23	445	#define BR_LPUART_BAUD_MAEN2(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN2))
mbed_official	324:406fd2029f23	446
mbed_official	324:406fd2029f23	447	/! @brief Format value for bitfield LPUART_BAUD_MAEN2. /
mbed_official	324:406fd2029f23	448	#define BF_LPUART_BAUD_MAEN2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MAEN2) & BM_LPUART_BAUD_MAEN2)
mbed_official	324:406fd2029f23	449
mbed_official	324:406fd2029f23	450	/! @brief Set the MAEN2 field to a new value. /
mbed_official	324:406fd2029f23	451	#define BW_LPUART_BAUD_MAEN2(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN2) = (v))
mbed_official	324:406fd2029f23	452	/@}/
mbed_official	324:406fd2029f23	453
mbed_official	324:406fd2029f23	454	/*!
mbed_official	324:406fd2029f23	455	* @name Register LPUART_BAUD, field MAEN1[31] (RW)
mbed_official	324:406fd2029f23	456	*
mbed_official	324:406fd2029f23	457	* Values:
mbed_official	324:406fd2029f23	458	* - 0 - Normal operation.
mbed_official	324:406fd2029f23	459	* - 1 - Enables automatic address matching or data matching mode for MATCH[MA1].
mbed_official	324:406fd2029f23	460	*/
mbed_official	324:406fd2029f23	461	/@{/
mbed_official	324:406fd2029f23	462	#define BP_LPUART_BAUD_MAEN1 (31U) /!< Bit position for LPUART_BAUD_MAEN1. /
mbed_official	324:406fd2029f23	463	#define BM_LPUART_BAUD_MAEN1 (0x80000000U) /!< Bit mask for LPUART_BAUD_MAEN1. /
mbed_official	324:406fd2029f23	464	#define BS_LPUART_BAUD_MAEN1 (1U) /!< Bit field size in bits for LPUART_BAUD_MAEN1. /
mbed_official	324:406fd2029f23	465
mbed_official	324:406fd2029f23	466	/! @brief Read current value of the LPUART_BAUD_MAEN1 field. /
mbed_official	324:406fd2029f23	467	#define BR_LPUART_BAUD_MAEN1(x) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN1))
mbed_official	324:406fd2029f23	468
mbed_official	324:406fd2029f23	469	/! @brief Format value for bitfield LPUART_BAUD_MAEN1. /
mbed_official	324:406fd2029f23	470	#define BF_LPUART_BAUD_MAEN1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_BAUD_MAEN1) & BM_LPUART_BAUD_MAEN1)
mbed_official	324:406fd2029f23	471
mbed_official	324:406fd2029f23	472	/! @brief Set the MAEN1 field to a new value. /
mbed_official	324:406fd2029f23	473	#define BW_LPUART_BAUD_MAEN1(x, v) (BITBAND_ACCESS32(HW_LPUART_BAUD_ADDR(x), BP_LPUART_BAUD_MAEN1) = (v))
mbed_official	324:406fd2029f23	474	/@}/
mbed_official	324:406fd2029f23	475
mbed_official	324:406fd2029f23	476	/*******************************************************************************
mbed_official	324:406fd2029f23	477	* HW_LPUART_STAT - LPUART Status Register
mbed_official	324:406fd2029f23	478	******************************************************************************/
mbed_official	324:406fd2029f23	479
mbed_official	324:406fd2029f23	480	/*!
mbed_official	324:406fd2029f23	481	* @brief HW_LPUART_STAT - LPUART Status Register (RW)
mbed_official	324:406fd2029f23	482	*
mbed_official	324:406fd2029f23	483	* Reset value: 0x00C00000U
mbed_official	324:406fd2029f23	484	*/
mbed_official	324:406fd2029f23	485	typedef union _hw_lpuart_stat
mbed_official	324:406fd2029f23	486	{
mbed_official	324:406fd2029f23	487	uint32_t U;
mbed_official	324:406fd2029f23	488	struct _hw_lpuart_stat_bitfields
mbed_official	324:406fd2029f23	489	{
mbed_official	324:406fd2029f23	490	uint32_t RESERVED0 : 14; /!< [13:0] /
mbed_official	324:406fd2029f23	491	uint32_t MA2F : 1; /!< [14] Match 2 Flag /
mbed_official	324:406fd2029f23	492	uint32_t MA1F : 1; /!< [15] Match 1 Flag /
mbed_official	324:406fd2029f23	493	uint32_t PF : 1; /!< [16] Parity Error Flag /
mbed_official	324:406fd2029f23	494	uint32_t FE : 1; /!< [17] Framing Error Flag /
mbed_official	324:406fd2029f23	495	uint32_t NF : 1; /!< [18] Noise Flag /
mbed_official	324:406fd2029f23	496	uint32_t OR : 1; /!< [19] Receiver Overrun Flag /
mbed_official	324:406fd2029f23	497	uint32_t IDLE : 1; /!< [20] Idle Line Flag /
mbed_official	324:406fd2029f23	498	uint32_t RDRF : 1; /!< [21] Receive Data Register Full Flag /
mbed_official	324:406fd2029f23	499	uint32_t TC : 1; /!< [22] Transmission Complete Flag /
mbed_official	324:406fd2029f23	500	uint32_t TDRE : 1; /!< [23] Transmit Data Register Empty Flag /
mbed_official	324:406fd2029f23	501	uint32_t RAF : 1; /!< [24] Receiver Active Flag /
mbed_official	324:406fd2029f23	502	uint32_t LBKDE : 1; /!< [25] LIN Break Detection Enable /
mbed_official	324:406fd2029f23	503	uint32_t BRK13 : 1; /!< [26] Break Character Generation Length /
mbed_official	324:406fd2029f23	504	uint32_t RWUID : 1; /!< [27] Receive Wake Up Idle Detect /
mbed_official	324:406fd2029f23	505	uint32_t RXINV : 1; /!< [28] Receive Data Inversion /
mbed_official	324:406fd2029f23	506	uint32_t MSBF : 1; /!< [29] MSB First /
mbed_official	324:406fd2029f23	507	uint32_t RXEDGIF : 1; /*!< [30] LPUART_RX Pin Active Edge Interrupt
mbed_official	324:406fd2029f23	508	* Flag */
mbed_official	324:406fd2029f23	509	uint32_t LBKDIF : 1; /!< [31] LIN Break Detect Interrupt Flag /
mbed_official	324:406fd2029f23	510	} B;
mbed_official	324:406fd2029f23	511	} hw_lpuart_stat_t;
mbed_official	324:406fd2029f23	512
mbed_official	324:406fd2029f23	513	/*!
mbed_official	324:406fd2029f23	514	* @name Constants and macros for entire LPUART_STAT register
mbed_official	324:406fd2029f23	515	*/
mbed_official	324:406fd2029f23	516	/@{/
mbed_official	324:406fd2029f23	517	#define HW_LPUART_STAT_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	518
mbed_official	324:406fd2029f23	519	#define HW_LPUART_STAT(x) ((__IO hw_lpuart_stat_t ) HW_LPUART_STAT_ADDR(x))
mbed_official	324:406fd2029f23	520	#define HW_LPUART_STAT_RD(x) (HW_LPUART_STAT(x).U)
mbed_official	324:406fd2029f23	521	#define HW_LPUART_STAT_WR(x, v) (HW_LPUART_STAT(x).U = (v))
mbed_official	324:406fd2029f23	522	#define HW_LPUART_STAT_SET(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	523	#define HW_LPUART_STAT_CLR(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	524	#define HW_LPUART_STAT_TOG(x, v) (HW_LPUART_STAT_WR(x, HW_LPUART_STAT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	525	/@}/
mbed_official	324:406fd2029f23	526
mbed_official	324:406fd2029f23	527	/*
mbed_official	324:406fd2029f23	528	* Constants & macros for individual LPUART_STAT bitfields
mbed_official	324:406fd2029f23	529	*/
mbed_official	324:406fd2029f23	530
mbed_official	324:406fd2029f23	531	/*!
mbed_official	324:406fd2029f23	532	* @name Register LPUART_STAT, field MA2F[14] (W1C)
mbed_official	324:406fd2029f23	533	*
mbed_official	324:406fd2029f23	534	* MA2F is set whenever the next character to be read from LPUART_DATA matches
mbed_official	324:406fd2029f23	535	* MA2. To clear MA2F, write a logic one to the MA2F.
mbed_official	324:406fd2029f23	536	*
mbed_official	324:406fd2029f23	537	* Values:
mbed_official	324:406fd2029f23	538	* - 0 - Received data is not equal to MA2
mbed_official	324:406fd2029f23	539	* - 1 - Received data is equal to MA2
mbed_official	324:406fd2029f23	540	*/
mbed_official	324:406fd2029f23	541	/@{/
mbed_official	324:406fd2029f23	542	#define BP_LPUART_STAT_MA2F (14U) /!< Bit position for LPUART_STAT_MA2F. /
mbed_official	324:406fd2029f23	543	#define BM_LPUART_STAT_MA2F (0x00004000U) /!< Bit mask for LPUART_STAT_MA2F. /
mbed_official	324:406fd2029f23	544	#define BS_LPUART_STAT_MA2F (1U) /!< Bit field size in bits for LPUART_STAT_MA2F. /
mbed_official	324:406fd2029f23	545
mbed_official	324:406fd2029f23	546	/! @brief Read current value of the LPUART_STAT_MA2F field. /
mbed_official	324:406fd2029f23	547	#define BR_LPUART_STAT_MA2F(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA2F))
mbed_official	324:406fd2029f23	548
mbed_official	324:406fd2029f23	549	/! @brief Format value for bitfield LPUART_STAT_MA2F. /
mbed_official	324:406fd2029f23	550	#define BF_LPUART_STAT_MA2F(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MA2F) & BM_LPUART_STAT_MA2F)
mbed_official	324:406fd2029f23	551
mbed_official	324:406fd2029f23	552	/! @brief Set the MA2F field to a new value. /
mbed_official	324:406fd2029f23	553	#define BW_LPUART_STAT_MA2F(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA2F) = (v))
mbed_official	324:406fd2029f23	554	/@}/
mbed_official	324:406fd2029f23	555
mbed_official	324:406fd2029f23	556	/*!
mbed_official	324:406fd2029f23	557	* @name Register LPUART_STAT, field MA1F[15] (W1C)
mbed_official	324:406fd2029f23	558	*
mbed_official	324:406fd2029f23	559	* MA1F is set whenever the next character to be read from LPUART_DATA matches
mbed_official	324:406fd2029f23	560	* MA1. To clear MA1F, write a logic one to the MA1F.
mbed_official	324:406fd2029f23	561	*
mbed_official	324:406fd2029f23	562	* Values:
mbed_official	324:406fd2029f23	563	* - 0 - Received data is not equal to MA1
mbed_official	324:406fd2029f23	564	* - 1 - Received data is equal to MA1
mbed_official	324:406fd2029f23	565	*/
mbed_official	324:406fd2029f23	566	/@{/
mbed_official	324:406fd2029f23	567	#define BP_LPUART_STAT_MA1F (15U) /!< Bit position for LPUART_STAT_MA1F. /
mbed_official	324:406fd2029f23	568	#define BM_LPUART_STAT_MA1F (0x00008000U) /!< Bit mask for LPUART_STAT_MA1F. /
mbed_official	324:406fd2029f23	569	#define BS_LPUART_STAT_MA1F (1U) /!< Bit field size in bits for LPUART_STAT_MA1F. /
mbed_official	324:406fd2029f23	570
mbed_official	324:406fd2029f23	571	/! @brief Read current value of the LPUART_STAT_MA1F field. /
mbed_official	324:406fd2029f23	572	#define BR_LPUART_STAT_MA1F(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA1F))
mbed_official	324:406fd2029f23	573
mbed_official	324:406fd2029f23	574	/! @brief Format value for bitfield LPUART_STAT_MA1F. /
mbed_official	324:406fd2029f23	575	#define BF_LPUART_STAT_MA1F(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MA1F) & BM_LPUART_STAT_MA1F)
mbed_official	324:406fd2029f23	576
mbed_official	324:406fd2029f23	577	/! @brief Set the MA1F field to a new value. /
mbed_official	324:406fd2029f23	578	#define BW_LPUART_STAT_MA1F(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MA1F) = (v))
mbed_official	324:406fd2029f23	579	/@}/
mbed_official	324:406fd2029f23	580
mbed_official	324:406fd2029f23	581	/*!
mbed_official	324:406fd2029f23	582	* @name Register LPUART_STAT, field PF[16] (W1C)
mbed_official	324:406fd2029f23	583	*
mbed_official	324:406fd2029f23	584	* PF is set whenever the next character to be read from LPUART_DATA was
mbed_official	324:406fd2029f23	585	* received when parity is enabled (PE = 1) and the parity bit in the received character
mbed_official	324:406fd2029f23	586	* does not agree with the expected parity value. To clear PF, write a logic one
mbed_official	324:406fd2029f23	587	* to the PF.
mbed_official	324:406fd2029f23	588	*
mbed_official	324:406fd2029f23	589	* Values:
mbed_official	324:406fd2029f23	590	* - 0 - No parity error.
mbed_official	324:406fd2029f23	591	* - 1 - Parity error.
mbed_official	324:406fd2029f23	592	*/
mbed_official	324:406fd2029f23	593	/@{/
mbed_official	324:406fd2029f23	594	#define BP_LPUART_STAT_PF (16U) /!< Bit position for LPUART_STAT_PF. /
mbed_official	324:406fd2029f23	595	#define BM_LPUART_STAT_PF (0x00010000U) /!< Bit mask for LPUART_STAT_PF. /
mbed_official	324:406fd2029f23	596	#define BS_LPUART_STAT_PF (1U) /!< Bit field size in bits for LPUART_STAT_PF. /
mbed_official	324:406fd2029f23	597
mbed_official	324:406fd2029f23	598	/! @brief Read current value of the LPUART_STAT_PF field. /
mbed_official	324:406fd2029f23	599	#define BR_LPUART_STAT_PF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_PF))
mbed_official	324:406fd2029f23	600
mbed_official	324:406fd2029f23	601	/! @brief Format value for bitfield LPUART_STAT_PF. /
mbed_official	324:406fd2029f23	602	#define BF_LPUART_STAT_PF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_PF) & BM_LPUART_STAT_PF)
mbed_official	324:406fd2029f23	603
mbed_official	324:406fd2029f23	604	/! @brief Set the PF field to a new value. /
mbed_official	324:406fd2029f23	605	#define BW_LPUART_STAT_PF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_PF) = (v))
mbed_official	324:406fd2029f23	606	/@}/
mbed_official	324:406fd2029f23	607
mbed_official	324:406fd2029f23	608	/*!
mbed_official	324:406fd2029f23	609	* @name Register LPUART_STAT, field FE[17] (W1C)
mbed_official	324:406fd2029f23	610	*
mbed_official	324:406fd2029f23	611	* FE is set whenever the next character to be read from LPUART_DATA was
mbed_official	324:406fd2029f23	612	* received with logic 0 detected where a stop bit was expected. To clear NF, write
mbed_official	324:406fd2029f23	613	* logic one to the NF.
mbed_official	324:406fd2029f23	614	*
mbed_official	324:406fd2029f23	615	* Values:
mbed_official	324:406fd2029f23	616	* - 0 - No framing error detected. This does not guarantee the framing is
mbed_official	324:406fd2029f23	617	* correct.
mbed_official	324:406fd2029f23	618	* - 1 - Framing error.
mbed_official	324:406fd2029f23	619	*/
mbed_official	324:406fd2029f23	620	/@{/
mbed_official	324:406fd2029f23	621	#define BP_LPUART_STAT_FE (17U) /!< Bit position for LPUART_STAT_FE. /
mbed_official	324:406fd2029f23	622	#define BM_LPUART_STAT_FE (0x00020000U) /!< Bit mask for LPUART_STAT_FE. /
mbed_official	324:406fd2029f23	623	#define BS_LPUART_STAT_FE (1U) /!< Bit field size in bits for LPUART_STAT_FE. /
mbed_official	324:406fd2029f23	624
mbed_official	324:406fd2029f23	625	/! @brief Read current value of the LPUART_STAT_FE field. /
mbed_official	324:406fd2029f23	626	#define BR_LPUART_STAT_FE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_FE))
mbed_official	324:406fd2029f23	627
mbed_official	324:406fd2029f23	628	/! @brief Format value for bitfield LPUART_STAT_FE. /
mbed_official	324:406fd2029f23	629	#define BF_LPUART_STAT_FE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_FE) & BM_LPUART_STAT_FE)
mbed_official	324:406fd2029f23	630
mbed_official	324:406fd2029f23	631	/! @brief Set the FE field to a new value. /
mbed_official	324:406fd2029f23	632	#define BW_LPUART_STAT_FE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_FE) = (v))
mbed_official	324:406fd2029f23	633	/@}/
mbed_official	324:406fd2029f23	634
mbed_official	324:406fd2029f23	635	/*!
mbed_official	324:406fd2029f23	636	* @name Register LPUART_STAT, field NF[18] (W1C)
mbed_official	324:406fd2029f23	637	*
mbed_official	324:406fd2029f23	638	* The advanced sampling technique used in the receiver takes three samples in
mbed_official	324:406fd2029f23	639	* each of the received bits. If any of these samples disagrees with the rest of
mbed_official	324:406fd2029f23	640	* the samples within any bit time in the frame then noise is detected for that
mbed_official	324:406fd2029f23	641	* character. NF is set whenever the next character to be read from LPUART_DATA was
mbed_official	324:406fd2029f23	642	* received with noise detected within the character. To clear NF, write logic
mbed_official	324:406fd2029f23	643	* one to the NF.
mbed_official	324:406fd2029f23	644	*
mbed_official	324:406fd2029f23	645	* Values:
mbed_official	324:406fd2029f23	646	* - 0 - No noise detected.
mbed_official	324:406fd2029f23	647	* - 1 - Noise detected in the received character in LPUART_DATA.
mbed_official	324:406fd2029f23	648	*/
mbed_official	324:406fd2029f23	649	/@{/
mbed_official	324:406fd2029f23	650	#define BP_LPUART_STAT_NF (18U) /!< Bit position for LPUART_STAT_NF. /
mbed_official	324:406fd2029f23	651	#define BM_LPUART_STAT_NF (0x00040000U) /!< Bit mask for LPUART_STAT_NF. /
mbed_official	324:406fd2029f23	652	#define BS_LPUART_STAT_NF (1U) /!< Bit field size in bits for LPUART_STAT_NF. /
mbed_official	324:406fd2029f23	653
mbed_official	324:406fd2029f23	654	/! @brief Read current value of the LPUART_STAT_NF field. /
mbed_official	324:406fd2029f23	655	#define BR_LPUART_STAT_NF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_NF))
mbed_official	324:406fd2029f23	656
mbed_official	324:406fd2029f23	657	/! @brief Format value for bitfield LPUART_STAT_NF. /
mbed_official	324:406fd2029f23	658	#define BF_LPUART_STAT_NF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_NF) & BM_LPUART_STAT_NF)
mbed_official	324:406fd2029f23	659
mbed_official	324:406fd2029f23	660	/! @brief Set the NF field to a new value. /
mbed_official	324:406fd2029f23	661	#define BW_LPUART_STAT_NF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_NF) = (v))
mbed_official	324:406fd2029f23	662	/@}/
mbed_official	324:406fd2029f23	663
mbed_official	324:406fd2029f23	664	/*!
mbed_official	324:406fd2029f23	665	* @name Register LPUART_STAT, field OR[19] (W1C)
mbed_official	324:406fd2029f23	666	*
mbed_official	324:406fd2029f23	667	* OR is set when software fails to prevent the receive data register from
mbed_official	324:406fd2029f23	668	* overflowing with data. The OR bit is set immediately after the stop bit has been
mbed_official	324:406fd2029f23	669	* completely received for the dataword that overflows the buffer and all the other
mbed_official	324:406fd2029f23	670	* error flags (FE, NF, and PF) are prevented from setting. The data in the
mbed_official	324:406fd2029f23	671	* shift register is lost, but the data already in the LPUART data registers is not
mbed_official	324:406fd2029f23	672	* affected. If LBKDE is enabled and a LIN Break is detected, the OR field asserts
mbed_official	324:406fd2029f23	673	* if LBKDIF is not cleared before the next data character is received. While
mbed_official	324:406fd2029f23	674	* the OR flag is set, no additional data is stored in the data buffer even if
mbed_official	324:406fd2029f23	675	* sufficient room exists. To clear OR, write logic 1 to the OR flag.
mbed_official	324:406fd2029f23	676	*
mbed_official	324:406fd2029f23	677	* Values:
mbed_official	324:406fd2029f23	678	* - 0 - No overrun.
mbed_official	324:406fd2029f23	679	* - 1 - Receive overrun (new LPUART data lost).
mbed_official	324:406fd2029f23	680	*/
mbed_official	324:406fd2029f23	681	/@{/
mbed_official	324:406fd2029f23	682	#define BP_LPUART_STAT_OR (19U) /!< Bit position for LPUART_STAT_OR. /
mbed_official	324:406fd2029f23	683	#define BM_LPUART_STAT_OR (0x00080000U) /!< Bit mask for LPUART_STAT_OR. /
mbed_official	324:406fd2029f23	684	#define BS_LPUART_STAT_OR (1U) /!< Bit field size in bits for LPUART_STAT_OR. /
mbed_official	324:406fd2029f23	685
mbed_official	324:406fd2029f23	686	/! @brief Read current value of the LPUART_STAT_OR field. /
mbed_official	324:406fd2029f23	687	#define BR_LPUART_STAT_OR(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_OR))
mbed_official	324:406fd2029f23	688
mbed_official	324:406fd2029f23	689	/! @brief Format value for bitfield LPUART_STAT_OR. /
mbed_official	324:406fd2029f23	690	#define BF_LPUART_STAT_OR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_OR) & BM_LPUART_STAT_OR)
mbed_official	324:406fd2029f23	691
mbed_official	324:406fd2029f23	692	/! @brief Set the OR field to a new value. /
mbed_official	324:406fd2029f23	693	#define BW_LPUART_STAT_OR(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_OR) = (v))
mbed_official	324:406fd2029f23	694	/@}/
mbed_official	324:406fd2029f23	695
mbed_official	324:406fd2029f23	696	/*!
mbed_official	324:406fd2029f23	697	* @name Register LPUART_STAT, field IDLE[20] (W1C)
mbed_official	324:406fd2029f23	698	*
mbed_official	324:406fd2029f23	699	* IDLE is set when the LPUART receive line becomes idle for a full character
mbed_official	324:406fd2029f23	700	* time after a period of activity. When ILT is cleared, the receiver starts
mbed_official	324:406fd2029f23	701	* counting idle bit times after the start bit. If the receive character is all 1s,
mbed_official	324:406fd2029f23	702	* these bit times and the stop bits time count toward the full character time of
mbed_official	324:406fd2029f23	703	* logic high, 10 to 13 bit times, needed for the receiver to detect an idle line.
mbed_official	324:406fd2029f23	704	* When ILT is set, the receiver doesn't start counting idle bit times until
mbed_official	324:406fd2029f23	705	* after the stop bits. The stop bits and any logic high bit times at the end of the
mbed_official	324:406fd2029f23	706	* previous character do not count toward the full character time of logic high
mbed_official	324:406fd2029f23	707	* needed for the receiver to detect an idle line. To clear IDLE, write logic 1 to
mbed_official	324:406fd2029f23	708	* the IDLE flag. After IDLE has been cleared, it cannot become set again until
mbed_official	324:406fd2029f23	709	* after a new character has been stored in the receive buffer or a LIN break
mbed_official	324:406fd2029f23	710	* character has set the LBKDIF flag . IDLE is set only once even if the receive
mbed_official	324:406fd2029f23	711	* line remains idle for an extended period.
mbed_official	324:406fd2029f23	712	*
mbed_official	324:406fd2029f23	713	* Values:
mbed_official	324:406fd2029f23	714	* - 0 - No idle line detected.
mbed_official	324:406fd2029f23	715	* - 1 - Idle line was detected.
mbed_official	324:406fd2029f23	716	*/
mbed_official	324:406fd2029f23	717	/@{/
mbed_official	324:406fd2029f23	718	#define BP_LPUART_STAT_IDLE (20U) /!< Bit position for LPUART_STAT_IDLE. /
mbed_official	324:406fd2029f23	719	#define BM_LPUART_STAT_IDLE (0x00100000U) /!< Bit mask for LPUART_STAT_IDLE. /
mbed_official	324:406fd2029f23	720	#define BS_LPUART_STAT_IDLE (1U) /!< Bit field size in bits for LPUART_STAT_IDLE. /
mbed_official	324:406fd2029f23	721
mbed_official	324:406fd2029f23	722	/! @brief Read current value of the LPUART_STAT_IDLE field. /
mbed_official	324:406fd2029f23	723	#define BR_LPUART_STAT_IDLE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_IDLE))
mbed_official	324:406fd2029f23	724
mbed_official	324:406fd2029f23	725	/! @brief Format value for bitfield LPUART_STAT_IDLE. /
mbed_official	324:406fd2029f23	726	#define BF_LPUART_STAT_IDLE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_IDLE) & BM_LPUART_STAT_IDLE)
mbed_official	324:406fd2029f23	727
mbed_official	324:406fd2029f23	728	/! @brief Set the IDLE field to a new value. /
mbed_official	324:406fd2029f23	729	#define BW_LPUART_STAT_IDLE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_IDLE) = (v))
mbed_official	324:406fd2029f23	730	/@}/
mbed_official	324:406fd2029f23	731
mbed_official	324:406fd2029f23	732	/*!
mbed_official	324:406fd2029f23	733	* @name Register LPUART_STAT, field RDRF[21] (RO)
mbed_official	324:406fd2029f23	734	*
mbed_official	324:406fd2029f23	735	* RDRF is set when the receive buffer (LPUART_DATA) is full. To clear RDRF,
mbed_official	324:406fd2029f23	736	* read the LPUART_DATA register. A character that is in the process of being
mbed_official	324:406fd2029f23	737	* received does not cause a change in RDRF until the entire character is received.
mbed_official	324:406fd2029f23	738	* Even if RDRF is set, the character will continue to be received until an overrun
mbed_official	324:406fd2029f23	739	* condition occurs once the entire character is received.
mbed_official	324:406fd2029f23	740	*
mbed_official	324:406fd2029f23	741	* Values:
mbed_official	324:406fd2029f23	742	* - 0 - Receive data buffer empty.
mbed_official	324:406fd2029f23	743	* - 1 - Receive data buffer full.
mbed_official	324:406fd2029f23	744	*/
mbed_official	324:406fd2029f23	745	/@{/
mbed_official	324:406fd2029f23	746	#define BP_LPUART_STAT_RDRF (21U) /!< Bit position for LPUART_STAT_RDRF. /
mbed_official	324:406fd2029f23	747	#define BM_LPUART_STAT_RDRF (0x00200000U) /!< Bit mask for LPUART_STAT_RDRF. /
mbed_official	324:406fd2029f23	748	#define BS_LPUART_STAT_RDRF (1U) /!< Bit field size in bits for LPUART_STAT_RDRF. /
mbed_official	324:406fd2029f23	749
mbed_official	324:406fd2029f23	750	/! @brief Read current value of the LPUART_STAT_RDRF field. /
mbed_official	324:406fd2029f23	751	#define BR_LPUART_STAT_RDRF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RDRF))
mbed_official	324:406fd2029f23	752	/@}/
mbed_official	324:406fd2029f23	753
mbed_official	324:406fd2029f23	754	/*!
mbed_official	324:406fd2029f23	755	* @name Register LPUART_STAT, field TC[22] (RO)
mbed_official	324:406fd2029f23	756	*
mbed_official	324:406fd2029f23	757	* TC is cleared when there is a transmission in progress or when a preamble or
mbed_official	324:406fd2029f23	758	* break character is loaded. TC is set when the transmit buffer is empty and no
mbed_official	324:406fd2029f23	759	* data, preamble, or break character is being transmitted. When TC is set, the
mbed_official	324:406fd2029f23	760	* transmit data output signal becomes idle (logic 1). TC is cleared by writing to
mbed_official	324:406fd2029f23	761	* LPUART_DATA to transmit new data, queuing a preamble by clearing and then
mbed_official	324:406fd2029f23	762	* setting LPUART_CTRL[TE], queuing a break character by writing 1 to
mbed_official	324:406fd2029f23	763	* LPUART_CTRL[SBK].
mbed_official	324:406fd2029f23	764	*
mbed_official	324:406fd2029f23	765	* Values:
mbed_official	324:406fd2029f23	766	* - 0 - Transmitter active (sending data, a preamble, or a break).
mbed_official	324:406fd2029f23	767	* - 1 - Transmitter idle (transmission activity complete).
mbed_official	324:406fd2029f23	768	*/
mbed_official	324:406fd2029f23	769	/@{/
mbed_official	324:406fd2029f23	770	#define BP_LPUART_STAT_TC (22U) /!< Bit position for LPUART_STAT_TC. /
mbed_official	324:406fd2029f23	771	#define BM_LPUART_STAT_TC (0x00400000U) /!< Bit mask for LPUART_STAT_TC. /
mbed_official	324:406fd2029f23	772	#define BS_LPUART_STAT_TC (1U) /!< Bit field size in bits for LPUART_STAT_TC. /
mbed_official	324:406fd2029f23	773
mbed_official	324:406fd2029f23	774	/! @brief Read current value of the LPUART_STAT_TC field. /
mbed_official	324:406fd2029f23	775	#define BR_LPUART_STAT_TC(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_TC))
mbed_official	324:406fd2029f23	776	/@}/
mbed_official	324:406fd2029f23	777
mbed_official	324:406fd2029f23	778	/*!
mbed_official	324:406fd2029f23	779	* @name Register LPUART_STAT, field TDRE[23] (RO)
mbed_official	324:406fd2029f23	780	*
mbed_official	324:406fd2029f23	781	* TDRE will set when the transmit data register (LPUART_DATA) is empty. To
mbed_official	324:406fd2029f23	782	* clear TDRE, write to the LPUART data register (LPUART_DATA). TDRE is not affected
mbed_official	324:406fd2029f23	783	* by a character that is in the process of being transmitted, it is updated at
mbed_official	324:406fd2029f23	784	* the start of each transmitted character.
mbed_official	324:406fd2029f23	785	*
mbed_official	324:406fd2029f23	786	* Values:
mbed_official	324:406fd2029f23	787	* - 0 - Transmit data buffer full.
mbed_official	324:406fd2029f23	788	* - 1 - Transmit data buffer empty.
mbed_official	324:406fd2029f23	789	*/
mbed_official	324:406fd2029f23	790	/@{/
mbed_official	324:406fd2029f23	791	#define BP_LPUART_STAT_TDRE (23U) /!< Bit position for LPUART_STAT_TDRE. /
mbed_official	324:406fd2029f23	792	#define BM_LPUART_STAT_TDRE (0x00800000U) /!< Bit mask for LPUART_STAT_TDRE. /
mbed_official	324:406fd2029f23	793	#define BS_LPUART_STAT_TDRE (1U) /!< Bit field size in bits for LPUART_STAT_TDRE. /
mbed_official	324:406fd2029f23	794
mbed_official	324:406fd2029f23	795	/! @brief Read current value of the LPUART_STAT_TDRE field. /
mbed_official	324:406fd2029f23	796	#define BR_LPUART_STAT_TDRE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_TDRE))
mbed_official	324:406fd2029f23	797	/@}/
mbed_official	324:406fd2029f23	798
mbed_official	324:406fd2029f23	799	/*!
mbed_official	324:406fd2029f23	800	* @name Register LPUART_STAT, field RAF[24] (RO)
mbed_official	324:406fd2029f23	801	*
mbed_official	324:406fd2029f23	802	* RAF is set when the receiver detects the beginning of a valid start bit, and
mbed_official	324:406fd2029f23	803	* RAF is cleared automatically when the receiver detects an idle line.
mbed_official	324:406fd2029f23	804	*
mbed_official	324:406fd2029f23	805	* Values:
mbed_official	324:406fd2029f23	806	* - 0 - LPUART receiver idle waiting for a start bit.
mbed_official	324:406fd2029f23	807	* - 1 - LPUART receiver active (LPUART_RX input not idle).
mbed_official	324:406fd2029f23	808	*/
mbed_official	324:406fd2029f23	809	/@{/
mbed_official	324:406fd2029f23	810	#define BP_LPUART_STAT_RAF (24U) /!< Bit position for LPUART_STAT_RAF. /
mbed_official	324:406fd2029f23	811	#define BM_LPUART_STAT_RAF (0x01000000U) /!< Bit mask for LPUART_STAT_RAF. /
mbed_official	324:406fd2029f23	812	#define BS_LPUART_STAT_RAF (1U) /!< Bit field size in bits for LPUART_STAT_RAF. /
mbed_official	324:406fd2029f23	813
mbed_official	324:406fd2029f23	814	/! @brief Read current value of the LPUART_STAT_RAF field. /
mbed_official	324:406fd2029f23	815	#define BR_LPUART_STAT_RAF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RAF))
mbed_official	324:406fd2029f23	816	/@}/
mbed_official	324:406fd2029f23	817
mbed_official	324:406fd2029f23	818	/*!
mbed_official	324:406fd2029f23	819	* @name Register LPUART_STAT, field LBKDE[25] (RW)
mbed_official	324:406fd2029f23	820	*
mbed_official	324:406fd2029f23	821	* LBKDE selects a longer break character detection length. While LBKDE is set,
mbed_official	324:406fd2029f23	822	* receive data is not stored in the receive data buffer.
mbed_official	324:406fd2029f23	823	*
mbed_official	324:406fd2029f23	824	* Values:
mbed_official	324:406fd2029f23	825	* - 0 - Break character is detected at length 10 bit times (if M = 0, SBNS = 0)
mbed_official	324:406fd2029f23	826	* or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1
mbed_official	324:406fd2029f23	827	* or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
mbed_official	324:406fd2029f23	828	* - 1 - Break character is detected at length of 11 bit times (if M = 0, SBNS =
mbed_official	324:406fd2029f23	829	* 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS =
mbed_official	324:406fd2029f23	830	* 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
mbed_official	324:406fd2029f23	831	*/
mbed_official	324:406fd2029f23	832	/@{/
mbed_official	324:406fd2029f23	833	#define BP_LPUART_STAT_LBKDE (25U) /!< Bit position for LPUART_STAT_LBKDE. /
mbed_official	324:406fd2029f23	834	#define BM_LPUART_STAT_LBKDE (0x02000000U) /!< Bit mask for LPUART_STAT_LBKDE. /
mbed_official	324:406fd2029f23	835	#define BS_LPUART_STAT_LBKDE (1U) /!< Bit field size in bits for LPUART_STAT_LBKDE. /
mbed_official	324:406fd2029f23	836
mbed_official	324:406fd2029f23	837	/! @brief Read current value of the LPUART_STAT_LBKDE field. /
mbed_official	324:406fd2029f23	838	#define BR_LPUART_STAT_LBKDE(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDE))
mbed_official	324:406fd2029f23	839
mbed_official	324:406fd2029f23	840	/! @brief Format value for bitfield LPUART_STAT_LBKDE. /
mbed_official	324:406fd2029f23	841	#define BF_LPUART_STAT_LBKDE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_LBKDE) & BM_LPUART_STAT_LBKDE)
mbed_official	324:406fd2029f23	842
mbed_official	324:406fd2029f23	843	/! @brief Set the LBKDE field to a new value. /
mbed_official	324:406fd2029f23	844	#define BW_LPUART_STAT_LBKDE(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDE) = (v))
mbed_official	324:406fd2029f23	845	/@}/
mbed_official	324:406fd2029f23	846
mbed_official	324:406fd2029f23	847	/*!
mbed_official	324:406fd2029f23	848	* @name Register LPUART_STAT, field BRK13[26] (RW)
mbed_official	324:406fd2029f23	849	*
mbed_official	324:406fd2029f23	850	* BRK13 selects a longer transmitted break character length. Detection of a
mbed_official	324:406fd2029f23	851	* framing error is not affected by the state of this bit. This bit should only be
mbed_official	324:406fd2029f23	852	* changed when the transmitter is disabled.
mbed_official	324:406fd2029f23	853	*
mbed_official	324:406fd2029f23	854	* Values:
mbed_official	324:406fd2029f23	855	* - 0 - Break character is transmitted with length of 10 bit times (if M = 0,
mbed_official	324:406fd2029f23	856	* SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
mbed_official	324:406fd2029f23	857	* SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
mbed_official	324:406fd2029f23	858	* - 1 - Break character is transmitted with length of 13 bit times (if M = 0,
mbed_official	324:406fd2029f23	859	* SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
mbed_official	324:406fd2029f23	860	* SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
mbed_official	324:406fd2029f23	861	*/
mbed_official	324:406fd2029f23	862	/@{/
mbed_official	324:406fd2029f23	863	#define BP_LPUART_STAT_BRK13 (26U) /!< Bit position for LPUART_STAT_BRK13. /
mbed_official	324:406fd2029f23	864	#define BM_LPUART_STAT_BRK13 (0x04000000U) /!< Bit mask for LPUART_STAT_BRK13. /
mbed_official	324:406fd2029f23	865	#define BS_LPUART_STAT_BRK13 (1U) /!< Bit field size in bits for LPUART_STAT_BRK13. /
mbed_official	324:406fd2029f23	866
mbed_official	324:406fd2029f23	867	/! @brief Read current value of the LPUART_STAT_BRK13 field. /
mbed_official	324:406fd2029f23	868	#define BR_LPUART_STAT_BRK13(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_BRK13))
mbed_official	324:406fd2029f23	869
mbed_official	324:406fd2029f23	870	/! @brief Format value for bitfield LPUART_STAT_BRK13. /
mbed_official	324:406fd2029f23	871	#define BF_LPUART_STAT_BRK13(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_BRK13) & BM_LPUART_STAT_BRK13)
mbed_official	324:406fd2029f23	872
mbed_official	324:406fd2029f23	873	/! @brief Set the BRK13 field to a new value. /
mbed_official	324:406fd2029f23	874	#define BW_LPUART_STAT_BRK13(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_BRK13) = (v))
mbed_official	324:406fd2029f23	875	/@}/
mbed_official	324:406fd2029f23	876
mbed_official	324:406fd2029f23	877	/*!
mbed_official	324:406fd2029f23	878	* @name Register LPUART_STAT, field RWUID[27] (RW)
mbed_official	324:406fd2029f23	879	*
mbed_official	324:406fd2029f23	880	* For RWU on idle character, RWUID controls whether the idle character that
mbed_official	324:406fd2029f23	881	* wakes up the receiver sets the IDLE bit. For address match wakeup, RWUID controls
mbed_official	324:406fd2029f23	882	* if the IDLE bit is set when the address does not match. This bit should only
mbed_official	324:406fd2029f23	883	* be changed when the receiver is disabled.
mbed_official	324:406fd2029f23	884	*
mbed_official	324:406fd2029f23	885	* Values:
mbed_official	324:406fd2029f23	886	* - 0 - During receive standby state (RWU = 1), the IDLE bit does not get set
mbed_official	324:406fd2029f23	887	* upon detection of an idle character. During address match wakeup, the IDLE
mbed_official	324:406fd2029f23	888	* bit does not get set when an address does not match.
mbed_official	324:406fd2029f23	889	* - 1 - During receive standby state (RWU = 1), the IDLE bit gets set upon
mbed_official	324:406fd2029f23	890	* detection of an idle character. During address match wakeup, the IDLE bit does
mbed_official	324:406fd2029f23	891	* get set when an address does not match.
mbed_official	324:406fd2029f23	892	*/
mbed_official	324:406fd2029f23	893	/@{/
mbed_official	324:406fd2029f23	894	#define BP_LPUART_STAT_RWUID (27U) /!< Bit position for LPUART_STAT_RWUID. /
mbed_official	324:406fd2029f23	895	#define BM_LPUART_STAT_RWUID (0x08000000U) /!< Bit mask for LPUART_STAT_RWUID. /
mbed_official	324:406fd2029f23	896	#define BS_LPUART_STAT_RWUID (1U) /!< Bit field size in bits for LPUART_STAT_RWUID. /
mbed_official	324:406fd2029f23	897
mbed_official	324:406fd2029f23	898	/! @brief Read current value of the LPUART_STAT_RWUID field. /
mbed_official	324:406fd2029f23	899	#define BR_LPUART_STAT_RWUID(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RWUID))
mbed_official	324:406fd2029f23	900
mbed_official	324:406fd2029f23	901	/! @brief Format value for bitfield LPUART_STAT_RWUID. /
mbed_official	324:406fd2029f23	902	#define BF_LPUART_STAT_RWUID(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RWUID) & BM_LPUART_STAT_RWUID)
mbed_official	324:406fd2029f23	903
mbed_official	324:406fd2029f23	904	/! @brief Set the RWUID field to a new value. /
mbed_official	324:406fd2029f23	905	#define BW_LPUART_STAT_RWUID(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RWUID) = (v))
mbed_official	324:406fd2029f23	906	/@}/
mbed_official	324:406fd2029f23	907
mbed_official	324:406fd2029f23	908	/*!
mbed_official	324:406fd2029f23	909	* @name Register LPUART_STAT, field RXINV[28] (RW)
mbed_official	324:406fd2029f23	910	*
mbed_official	324:406fd2029f23	911	* Setting this bit reverses the polarity of the received data input. Setting
mbed_official	324:406fd2029f23	912	* RXINV inverts the LPUART_RX input for all cases: data bits, start and stop bits,
mbed_official	324:406fd2029f23	913	* break, and idle.
mbed_official	324:406fd2029f23	914	*
mbed_official	324:406fd2029f23	915	* Values:
mbed_official	324:406fd2029f23	916	* - 0 - Receive data not inverted.
mbed_official	324:406fd2029f23	917	* - 1 - Receive data inverted.
mbed_official	324:406fd2029f23	918	*/
mbed_official	324:406fd2029f23	919	/@{/
mbed_official	324:406fd2029f23	920	#define BP_LPUART_STAT_RXINV (28U) /!< Bit position for LPUART_STAT_RXINV. /
mbed_official	324:406fd2029f23	921	#define BM_LPUART_STAT_RXINV (0x10000000U) /!< Bit mask for LPUART_STAT_RXINV. /
mbed_official	324:406fd2029f23	922	#define BS_LPUART_STAT_RXINV (1U) /!< Bit field size in bits for LPUART_STAT_RXINV. /
mbed_official	324:406fd2029f23	923
mbed_official	324:406fd2029f23	924	/! @brief Read current value of the LPUART_STAT_RXINV field. /
mbed_official	324:406fd2029f23	925	#define BR_LPUART_STAT_RXINV(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXINV))
mbed_official	324:406fd2029f23	926
mbed_official	324:406fd2029f23	927	/! @brief Format value for bitfield LPUART_STAT_RXINV. /
mbed_official	324:406fd2029f23	928	#define BF_LPUART_STAT_RXINV(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RXINV) & BM_LPUART_STAT_RXINV)
mbed_official	324:406fd2029f23	929
mbed_official	324:406fd2029f23	930	/! @brief Set the RXINV field to a new value. /
mbed_official	324:406fd2029f23	931	#define BW_LPUART_STAT_RXINV(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXINV) = (v))
mbed_official	324:406fd2029f23	932	/@}/
mbed_official	324:406fd2029f23	933
mbed_official	324:406fd2029f23	934	/*!
mbed_official	324:406fd2029f23	935	* @name Register LPUART_STAT, field MSBF[29] (RW)
mbed_official	324:406fd2029f23	936	*
mbed_official	324:406fd2029f23	937	* Setting this bit reverses the order of the bits that are transmitted and
mbed_official	324:406fd2029f23	938	* received on the wire. This bit does not affect the polarity of the bits, the
mbed_official	324:406fd2029f23	939	* location of the parity bit or the location of the start or stop bits. This bit
mbed_official	324:406fd2029f23	940	* should only be changed when the transmitter and receiver are both disabled.
mbed_official	324:406fd2029f23	941	*
mbed_official	324:406fd2029f23	942	* Values:
mbed_official	324:406fd2029f23	943	* - 0 - LSB (bit0) is the first bit that is transmitted following the start
mbed_official	324:406fd2029f23	944	* bit. Further, the first bit received after the start bit is identified as
mbed_official	324:406fd2029f23	945	* bit0.
mbed_official	324:406fd2029f23	946	* - 1 - MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted
mbed_official	324:406fd2029f23	947	* following the start bit depending on the setting of CTRL[M], CTRL[PE] and
mbed_official	324:406fd2029f23	948	* BAUD[M10]. Further, the first bit received after the start bit is identified
mbed_official	324:406fd2029f23	949	* as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and
mbed_official	324:406fd2029f23	950	* CTRL[PE].
mbed_official	324:406fd2029f23	951	*/
mbed_official	324:406fd2029f23	952	/@{/
mbed_official	324:406fd2029f23	953	#define BP_LPUART_STAT_MSBF (29U) /!< Bit position for LPUART_STAT_MSBF. /
mbed_official	324:406fd2029f23	954	#define BM_LPUART_STAT_MSBF (0x20000000U) /!< Bit mask for LPUART_STAT_MSBF. /
mbed_official	324:406fd2029f23	955	#define BS_LPUART_STAT_MSBF (1U) /!< Bit field size in bits for LPUART_STAT_MSBF. /
mbed_official	324:406fd2029f23	956
mbed_official	324:406fd2029f23	957	/! @brief Read current value of the LPUART_STAT_MSBF field. /
mbed_official	324:406fd2029f23	958	#define BR_LPUART_STAT_MSBF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MSBF))
mbed_official	324:406fd2029f23	959
mbed_official	324:406fd2029f23	960	/! @brief Format value for bitfield LPUART_STAT_MSBF. /
mbed_official	324:406fd2029f23	961	#define BF_LPUART_STAT_MSBF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_MSBF) & BM_LPUART_STAT_MSBF)
mbed_official	324:406fd2029f23	962
mbed_official	324:406fd2029f23	963	/! @brief Set the MSBF field to a new value. /
mbed_official	324:406fd2029f23	964	#define BW_LPUART_STAT_MSBF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_MSBF) = (v))
mbed_official	324:406fd2029f23	965	/@}/
mbed_official	324:406fd2029f23	966
mbed_official	324:406fd2029f23	967	/*!
mbed_official	324:406fd2029f23	968	* @name Register LPUART_STAT, field RXEDGIF[30] (W1C)
mbed_official	324:406fd2029f23	969	*
mbed_official	324:406fd2029f23	970	* RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1,
mbed_official	324:406fd2029f23	971	* on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it.
mbed_official	324:406fd2029f23	972	*
mbed_official	324:406fd2029f23	973	* Values:
mbed_official	324:406fd2029f23	974	* - 0 - No active edge on the receive pin has occurred.
mbed_official	324:406fd2029f23	975	* - 1 - An active edge on the receive pin has occurred.
mbed_official	324:406fd2029f23	976	*/
mbed_official	324:406fd2029f23	977	/@{/
mbed_official	324:406fd2029f23	978	#define BP_LPUART_STAT_RXEDGIF (30U) /!< Bit position for LPUART_STAT_RXEDGIF. /
mbed_official	324:406fd2029f23	979	#define BM_LPUART_STAT_RXEDGIF (0x40000000U) /!< Bit mask for LPUART_STAT_RXEDGIF. /
mbed_official	324:406fd2029f23	980	#define BS_LPUART_STAT_RXEDGIF (1U) /!< Bit field size in bits for LPUART_STAT_RXEDGIF. /
mbed_official	324:406fd2029f23	981
mbed_official	324:406fd2029f23	982	/! @brief Read current value of the LPUART_STAT_RXEDGIF field. /
mbed_official	324:406fd2029f23	983	#define BR_LPUART_STAT_RXEDGIF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXEDGIF))
mbed_official	324:406fd2029f23	984
mbed_official	324:406fd2029f23	985	/! @brief Format value for bitfield LPUART_STAT_RXEDGIF. /
mbed_official	324:406fd2029f23	986	#define BF_LPUART_STAT_RXEDGIF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_RXEDGIF) & BM_LPUART_STAT_RXEDGIF)
mbed_official	324:406fd2029f23	987
mbed_official	324:406fd2029f23	988	/! @brief Set the RXEDGIF field to a new value. /
mbed_official	324:406fd2029f23	989	#define BW_LPUART_STAT_RXEDGIF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_RXEDGIF) = (v))
mbed_official	324:406fd2029f23	990	/@}/
mbed_official	324:406fd2029f23	991
mbed_official	324:406fd2029f23	992	/*!
mbed_official	324:406fd2029f23	993	* @name Register LPUART_STAT, field LBKDIF[31] (W1C)
mbed_official	324:406fd2029f23	994	*
mbed_official	324:406fd2029f23	995	* LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
mbed_official	324:406fd2029f23	996	* character is detected. LBKDIF is cleared by writing a 1 to it.
mbed_official	324:406fd2029f23	997	*
mbed_official	324:406fd2029f23	998	* Values:
mbed_official	324:406fd2029f23	999	* - 0 - No LIN break character has been detected.
mbed_official	324:406fd2029f23	1000	* - 1 - LIN break character has been detected.
mbed_official	324:406fd2029f23	1001	*/
mbed_official	324:406fd2029f23	1002	/@{/
mbed_official	324:406fd2029f23	1003	#define BP_LPUART_STAT_LBKDIF (31U) /!< Bit position for LPUART_STAT_LBKDIF. /
mbed_official	324:406fd2029f23	1004	#define BM_LPUART_STAT_LBKDIF (0x80000000U) /!< Bit mask for LPUART_STAT_LBKDIF. /
mbed_official	324:406fd2029f23	1005	#define BS_LPUART_STAT_LBKDIF (1U) /!< Bit field size in bits for LPUART_STAT_LBKDIF. /
mbed_official	324:406fd2029f23	1006
mbed_official	324:406fd2029f23	1007	/! @brief Read current value of the LPUART_STAT_LBKDIF field. /
mbed_official	324:406fd2029f23	1008	#define BR_LPUART_STAT_LBKDIF(x) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDIF))
mbed_official	324:406fd2029f23	1009
mbed_official	324:406fd2029f23	1010	/! @brief Format value for bitfield LPUART_STAT_LBKDIF. /
mbed_official	324:406fd2029f23	1011	#define BF_LPUART_STAT_LBKDIF(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_STAT_LBKDIF) & BM_LPUART_STAT_LBKDIF)
mbed_official	324:406fd2029f23	1012
mbed_official	324:406fd2029f23	1013	/! @brief Set the LBKDIF field to a new value. /
mbed_official	324:406fd2029f23	1014	#define BW_LPUART_STAT_LBKDIF(x, v) (BITBAND_ACCESS32(HW_LPUART_STAT_ADDR(x), BP_LPUART_STAT_LBKDIF) = (v))
mbed_official	324:406fd2029f23	1015	/@}/
mbed_official	324:406fd2029f23	1016
mbed_official	324:406fd2029f23	1017	/*******************************************************************************
mbed_official	324:406fd2029f23	1018	* HW_LPUART_CTRL - LPUART Control Register
mbed_official	324:406fd2029f23	1019	******************************************************************************/
mbed_official	324:406fd2029f23	1020
mbed_official	324:406fd2029f23	1021	/*!
mbed_official	324:406fd2029f23	1022	* @brief HW_LPUART_CTRL - LPUART Control Register (RW)
mbed_official	324:406fd2029f23	1023	*
mbed_official	324:406fd2029f23	1024	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1025	*
mbed_official	324:406fd2029f23	1026	* This read/write register controls various optional features of the LPUART
mbed_official	324:406fd2029f23	1027	* system. This register should only be altered when the transmitter and receiver
mbed_official	324:406fd2029f23	1028	* are both disabled.
mbed_official	324:406fd2029f23	1029	*/
mbed_official	324:406fd2029f23	1030	typedef union _hw_lpuart_ctrl
mbed_official	324:406fd2029f23	1031	{
mbed_official	324:406fd2029f23	1032	uint32_t U;
mbed_official	324:406fd2029f23	1033	struct _hw_lpuart_ctrl_bitfields
mbed_official	324:406fd2029f23	1034	{
mbed_official	324:406fd2029f23	1035	uint32_t PT : 1; /!< [0] Parity Type /
mbed_official	324:406fd2029f23	1036	uint32_t PE : 1; /!< [1] Parity Enable /
mbed_official	324:406fd2029f23	1037	uint32_t ILT : 1; /!< [2] Idle Line Type Select /
mbed_official	324:406fd2029f23	1038	uint32_t WAKE : 1; /!< [3] Receiver Wakeup Method Select /
mbed_official	324:406fd2029f23	1039	uint32_t M : 1; /!< [4] 9-Bit or 8-Bit Mode Select /
mbed_official	324:406fd2029f23	1040	uint32_t RSRC : 1; /!< [5] Receiver Source Select /
mbed_official	324:406fd2029f23	1041	uint32_t DOZEEN : 1; /!< [6] Doze Enable /
mbed_official	324:406fd2029f23	1042	uint32_t LOOPS : 1; /!< [7] Loop Mode Select /
mbed_official	324:406fd2029f23	1043	uint32_t IDLECFG : 3; /!< [10:8] Idle Configuration /
mbed_official	324:406fd2029f23	1044	uint32_t RESERVED0 : 3; /!< [13:11] /
mbed_official	324:406fd2029f23	1045	uint32_t MA2IE : 1; /!< [14] Match 2 Interrupt Enable /
mbed_official	324:406fd2029f23	1046	uint32_t MA1IE : 1; /!< [15] Match 1 Interrupt Enable /
mbed_official	324:406fd2029f23	1047	uint32_t SBK : 1; /!< [16] Send Break /
mbed_official	324:406fd2029f23	1048	uint32_t RWU : 1; /!< [17] Receiver Wakeup Control /
mbed_official	324:406fd2029f23	1049	uint32_t RE : 1; /!< [18] Receiver Enable /
mbed_official	324:406fd2029f23	1050	uint32_t TE : 1; /!< [19] Transmitter Enable /
mbed_official	324:406fd2029f23	1051	uint32_t ILIE : 1; /!< [20] Idle Line Interrupt Enable /
mbed_official	324:406fd2029f23	1052	uint32_t RIE : 1; /!< [21] Receiver Interrupt Enable /
mbed_official	324:406fd2029f23	1053	uint32_t TCIE : 1; /*!< [22] Transmission Complete Interrupt Enable
mbed_official	324:406fd2029f23	1054	* for */
mbed_official	324:406fd2029f23	1055	uint32_t TIE : 1; /!< [23] Transmit Interrupt Enable /
mbed_official	324:406fd2029f23	1056	uint32_t PEIE : 1; /!< [24] Parity Error Interrupt Enable /
mbed_official	324:406fd2029f23	1057	uint32_t FEIE : 1; /!< [25] Framing Error Interrupt Enable /
mbed_official	324:406fd2029f23	1058	uint32_t NEIE : 1; /!< [26] Noise Error Interrupt Enable /
mbed_official	324:406fd2029f23	1059	uint32_t ORIE : 1; /!< [27] Overrun Interrupt Enable /
mbed_official	324:406fd2029f23	1060	uint32_t TXINV : 1; /!< [28] Transmit Data Inversion /
mbed_official	324:406fd2029f23	1061	uint32_t TXDIR : 1; /*!< [29] LPUART_TX Pin Direction in Single-Wire
mbed_official	324:406fd2029f23	1062	* Mode */
mbed_official	324:406fd2029f23	1063	uint32_t R9T8 : 1; /!< [30] Receive Bit 9 / Transmit Bit 8 /
mbed_official	324:406fd2029f23	1064	uint32_t R8T9 : 1; /!< [31] Receive Bit 8 / Transmit Bit 9 /
mbed_official	324:406fd2029f23	1065	} B;
mbed_official	324:406fd2029f23	1066	} hw_lpuart_ctrl_t;
mbed_official	324:406fd2029f23	1067
mbed_official	324:406fd2029f23	1068	/*!
mbed_official	324:406fd2029f23	1069	* @name Constants and macros for entire LPUART_CTRL register
mbed_official	324:406fd2029f23	1070	*/
mbed_official	324:406fd2029f23	1071	/@{/
mbed_official	324:406fd2029f23	1072	#define HW_LPUART_CTRL_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	1073
mbed_official	324:406fd2029f23	1074	#define HW_LPUART_CTRL(x) ((__IO hw_lpuart_ctrl_t ) HW_LPUART_CTRL_ADDR(x))
mbed_official	324:406fd2029f23	1075	#define HW_LPUART_CTRL_RD(x) (HW_LPUART_CTRL(x).U)
mbed_official	324:406fd2029f23	1076	#define HW_LPUART_CTRL_WR(x, v) (HW_LPUART_CTRL(x).U = (v))
mbed_official	324:406fd2029f23	1077	#define HW_LPUART_CTRL_SET(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1078	#define HW_LPUART_CTRL_CLR(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1079	#define HW_LPUART_CTRL_TOG(x, v) (HW_LPUART_CTRL_WR(x, HW_LPUART_CTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1080	/@}/
mbed_official	324:406fd2029f23	1081
mbed_official	324:406fd2029f23	1082	/*
mbed_official	324:406fd2029f23	1083	* Constants & macros for individual LPUART_CTRL bitfields
mbed_official	324:406fd2029f23	1084	*/
mbed_official	324:406fd2029f23	1085
mbed_official	324:406fd2029f23	1086	/*!
mbed_official	324:406fd2029f23	1087	* @name Register LPUART_CTRL, field PT[0] (RW)
mbed_official	324:406fd2029f23	1088	*
mbed_official	324:406fd2029f23	1089	* Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd
mbed_official	324:406fd2029f23	1090	* parity means the total number of 1s in the data character, including the
mbed_official	324:406fd2029f23	1091	* parity bit, is odd. Even parity means the total number of 1s in the data
mbed_official	324:406fd2029f23	1092	* character, including the parity bit, is even.
mbed_official	324:406fd2029f23	1093	*
mbed_official	324:406fd2029f23	1094	* Values:
mbed_official	324:406fd2029f23	1095	* - 0 - Even parity.
mbed_official	324:406fd2029f23	1096	* - 1 - Odd parity.
mbed_official	324:406fd2029f23	1097	*/
mbed_official	324:406fd2029f23	1098	/@{/
mbed_official	324:406fd2029f23	1099	#define BP_LPUART_CTRL_PT (0U) /!< Bit position for LPUART_CTRL_PT. /
mbed_official	324:406fd2029f23	1100	#define BM_LPUART_CTRL_PT (0x00000001U) /!< Bit mask for LPUART_CTRL_PT. /
mbed_official	324:406fd2029f23	1101	#define BS_LPUART_CTRL_PT (1U) /!< Bit field size in bits for LPUART_CTRL_PT. /
mbed_official	324:406fd2029f23	1102
mbed_official	324:406fd2029f23	1103	/! @brief Read current value of the LPUART_CTRL_PT field. /
mbed_official	324:406fd2029f23	1104	#define BR_LPUART_CTRL_PT(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PT))
mbed_official	324:406fd2029f23	1105
mbed_official	324:406fd2029f23	1106	/! @brief Format value for bitfield LPUART_CTRL_PT. /
mbed_official	324:406fd2029f23	1107	#define BF_LPUART_CTRL_PT(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PT) & BM_LPUART_CTRL_PT)
mbed_official	324:406fd2029f23	1108
mbed_official	324:406fd2029f23	1109	/! @brief Set the PT field to a new value. /
mbed_official	324:406fd2029f23	1110	#define BW_LPUART_CTRL_PT(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PT) = (v))
mbed_official	324:406fd2029f23	1111	/@}/
mbed_official	324:406fd2029f23	1112
mbed_official	324:406fd2029f23	1113	/*!
mbed_official	324:406fd2029f23	1114	* @name Register LPUART_CTRL, field PE[1] (RW)
mbed_official	324:406fd2029f23	1115	*
mbed_official	324:406fd2029f23	1116	* Enables hardware parity generation and checking. When parity is enabled, the
mbed_official	324:406fd2029f23	1117	* bit immediately before the stop bit is treated as the parity bit.
mbed_official	324:406fd2029f23	1118	*
mbed_official	324:406fd2029f23	1119	* Values:
mbed_official	324:406fd2029f23	1120	* - 0 - No hardware parity generation or checking.
mbed_official	324:406fd2029f23	1121	* - 1 - Parity enabled.
mbed_official	324:406fd2029f23	1122	*/
mbed_official	324:406fd2029f23	1123	/@{/
mbed_official	324:406fd2029f23	1124	#define BP_LPUART_CTRL_PE (1U) /!< Bit position for LPUART_CTRL_PE. /
mbed_official	324:406fd2029f23	1125	#define BM_LPUART_CTRL_PE (0x00000002U) /!< Bit mask for LPUART_CTRL_PE. /
mbed_official	324:406fd2029f23	1126	#define BS_LPUART_CTRL_PE (1U) /!< Bit field size in bits for LPUART_CTRL_PE. /
mbed_official	324:406fd2029f23	1127
mbed_official	324:406fd2029f23	1128	/! @brief Read current value of the LPUART_CTRL_PE field. /
mbed_official	324:406fd2029f23	1129	#define BR_LPUART_CTRL_PE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PE))
mbed_official	324:406fd2029f23	1130
mbed_official	324:406fd2029f23	1131	/! @brief Format value for bitfield LPUART_CTRL_PE. /
mbed_official	324:406fd2029f23	1132	#define BF_LPUART_CTRL_PE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PE) & BM_LPUART_CTRL_PE)
mbed_official	324:406fd2029f23	1133
mbed_official	324:406fd2029f23	1134	/! @brief Set the PE field to a new value. /
mbed_official	324:406fd2029f23	1135	#define BW_LPUART_CTRL_PE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PE) = (v))
mbed_official	324:406fd2029f23	1136	/@}/
mbed_official	324:406fd2029f23	1137
mbed_official	324:406fd2029f23	1138	/*!
mbed_official	324:406fd2029f23	1139	* @name Register LPUART_CTRL, field ILT[2] (RW)
mbed_official	324:406fd2029f23	1140	*
mbed_official	324:406fd2029f23	1141	* Determines when the receiver starts counting logic 1s as idle character bits.
mbed_official	324:406fd2029f23	1142	* The count begins either after a valid start bit or after the stop bit. If the
mbed_official	324:406fd2029f23	1143	* count begins after the start bit, then a string of logic 1s preceding the
mbed_official	324:406fd2029f23	1144	* stop bit can cause false recognition of an idle character. Beginning the count
mbed_official	324:406fd2029f23	1145	* after the stop bit avoids false idle character recognition, but requires
mbed_official	324:406fd2029f23	1146	* properly synchronized transmissions. In case the LPUART is programmed with ILT = 1, a
mbed_official	324:406fd2029f23	1147	* logic 0 is automatically shifted after a received stop bit, therefore
mbed_official	324:406fd2029f23	1148	* resetting the idle count.
mbed_official	324:406fd2029f23	1149	*
mbed_official	324:406fd2029f23	1150	* Values:
mbed_official	324:406fd2029f23	1151	* - 0 - Idle character bit count starts after start bit.
mbed_official	324:406fd2029f23	1152	* - 1 - Idle character bit count starts after stop bit.
mbed_official	324:406fd2029f23	1153	*/
mbed_official	324:406fd2029f23	1154	/@{/
mbed_official	324:406fd2029f23	1155	#define BP_LPUART_CTRL_ILT (2U) /!< Bit position for LPUART_CTRL_ILT. /
mbed_official	324:406fd2029f23	1156	#define BM_LPUART_CTRL_ILT (0x00000004U) /!< Bit mask for LPUART_CTRL_ILT. /
mbed_official	324:406fd2029f23	1157	#define BS_LPUART_CTRL_ILT (1U) /!< Bit field size in bits for LPUART_CTRL_ILT. /
mbed_official	324:406fd2029f23	1158
mbed_official	324:406fd2029f23	1159	/! @brief Read current value of the LPUART_CTRL_ILT field. /
mbed_official	324:406fd2029f23	1160	#define BR_LPUART_CTRL_ILT(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILT))
mbed_official	324:406fd2029f23	1161
mbed_official	324:406fd2029f23	1162	/! @brief Format value for bitfield LPUART_CTRL_ILT. /
mbed_official	324:406fd2029f23	1163	#define BF_LPUART_CTRL_ILT(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ILT) & BM_LPUART_CTRL_ILT)
mbed_official	324:406fd2029f23	1164
mbed_official	324:406fd2029f23	1165	/! @brief Set the ILT field to a new value. /
mbed_official	324:406fd2029f23	1166	#define BW_LPUART_CTRL_ILT(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILT) = (v))
mbed_official	324:406fd2029f23	1167	/@}/
mbed_official	324:406fd2029f23	1168
mbed_official	324:406fd2029f23	1169	/*!
mbed_official	324:406fd2029f23	1170	* @name Register LPUART_CTRL, field WAKE[3] (RW)
mbed_official	324:406fd2029f23	1171	*
mbed_official	324:406fd2029f23	1172	* Determines which condition wakes the LPUART when RWU=1: Address mark in the
mbed_official	324:406fd2029f23	1173	* most significant bit position of a received data character, or An idle
mbed_official	324:406fd2029f23	1174	* condition on the receive pin input signal.
mbed_official	324:406fd2029f23	1175	*
mbed_official	324:406fd2029f23	1176	* Values:
mbed_official	324:406fd2029f23	1177	* - 0 - Configures RWU for idle-line wakeup.
mbed_official	324:406fd2029f23	1178	* - 1 - Configures RWU with address-mark wakeup.
mbed_official	324:406fd2029f23	1179	*/
mbed_official	324:406fd2029f23	1180	/@{/
mbed_official	324:406fd2029f23	1181	#define BP_LPUART_CTRL_WAKE (3U) /!< Bit position for LPUART_CTRL_WAKE. /
mbed_official	324:406fd2029f23	1182	#define BM_LPUART_CTRL_WAKE (0x00000008U) /!< Bit mask for LPUART_CTRL_WAKE. /
mbed_official	324:406fd2029f23	1183	#define BS_LPUART_CTRL_WAKE (1U) /!< Bit field size in bits for LPUART_CTRL_WAKE. /
mbed_official	324:406fd2029f23	1184
mbed_official	324:406fd2029f23	1185	/! @brief Read current value of the LPUART_CTRL_WAKE field. /
mbed_official	324:406fd2029f23	1186	#define BR_LPUART_CTRL_WAKE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_WAKE))
mbed_official	324:406fd2029f23	1187
mbed_official	324:406fd2029f23	1188	/! @brief Format value for bitfield LPUART_CTRL_WAKE. /
mbed_official	324:406fd2029f23	1189	#define BF_LPUART_CTRL_WAKE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_WAKE) & BM_LPUART_CTRL_WAKE)
mbed_official	324:406fd2029f23	1190
mbed_official	324:406fd2029f23	1191	/! @brief Set the WAKE field to a new value. /
mbed_official	324:406fd2029f23	1192	#define BW_LPUART_CTRL_WAKE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_WAKE) = (v))
mbed_official	324:406fd2029f23	1193	/@}/
mbed_official	324:406fd2029f23	1194
mbed_official	324:406fd2029f23	1195	/*!
mbed_official	324:406fd2029f23	1196	* @name Register LPUART_CTRL, field M[4] (RW)
mbed_official	324:406fd2029f23	1197	*
mbed_official	324:406fd2029f23	1198	* Values:
mbed_official	324:406fd2029f23	1199	* - 0 - Receiver and transmitter use 8-bit data characters.
mbed_official	324:406fd2029f23	1200	* - 1 - Receiver and transmitter use 9-bit data characters.
mbed_official	324:406fd2029f23	1201	*/
mbed_official	324:406fd2029f23	1202	/@{/
mbed_official	324:406fd2029f23	1203	#define BP_LPUART_CTRL_M (4U) /!< Bit position for LPUART_CTRL_M. /
mbed_official	324:406fd2029f23	1204	#define BM_LPUART_CTRL_M (0x00000010U) /!< Bit mask for LPUART_CTRL_M. /
mbed_official	324:406fd2029f23	1205	#define BS_LPUART_CTRL_M (1U) /!< Bit field size in bits for LPUART_CTRL_M. /
mbed_official	324:406fd2029f23	1206
mbed_official	324:406fd2029f23	1207	/! @brief Read current value of the LPUART_CTRL_M field. /
mbed_official	324:406fd2029f23	1208	#define BR_LPUART_CTRL_M(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_M))
mbed_official	324:406fd2029f23	1209
mbed_official	324:406fd2029f23	1210	/! @brief Format value for bitfield LPUART_CTRL_M. /
mbed_official	324:406fd2029f23	1211	#define BF_LPUART_CTRL_M(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_M) & BM_LPUART_CTRL_M)
mbed_official	324:406fd2029f23	1212
mbed_official	324:406fd2029f23	1213	/! @brief Set the M field to a new value. /
mbed_official	324:406fd2029f23	1214	#define BW_LPUART_CTRL_M(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_M) = (v))
mbed_official	324:406fd2029f23	1215	/@}/
mbed_official	324:406fd2029f23	1216
mbed_official	324:406fd2029f23	1217	/*!
mbed_official	324:406fd2029f23	1218	* @name Register LPUART_CTRL, field RSRC[5] (RW)
mbed_official	324:406fd2029f23	1219	*
mbed_official	324:406fd2029f23	1220	* This field has no meaning or effect unless the LOOPS field is set. When LOOPS
mbed_official	324:406fd2029f23	1221	* is set, the RSRC field determines the source for the receiver shift register
mbed_official	324:406fd2029f23	1222	* input.
mbed_official	324:406fd2029f23	1223	*
mbed_official	324:406fd2029f23	1224	* Values:
mbed_official	324:406fd2029f23	1225	* - 0 - Provided LOOPS is set, RSRC is cleared, selects internal loop back mode
mbed_official	324:406fd2029f23	1226	* and the LPUART does not use the LPUART_RX pin.
mbed_official	324:406fd2029f23	1227	* - 1 - Single-wire LPUART mode where the LPUART_TX pin is connected to the
mbed_official	324:406fd2029f23	1228	* transmitter output and receiver input.
mbed_official	324:406fd2029f23	1229	*/
mbed_official	324:406fd2029f23	1230	/@{/
mbed_official	324:406fd2029f23	1231	#define BP_LPUART_CTRL_RSRC (5U) /!< Bit position for LPUART_CTRL_RSRC. /
mbed_official	324:406fd2029f23	1232	#define BM_LPUART_CTRL_RSRC (0x00000020U) /!< Bit mask for LPUART_CTRL_RSRC. /
mbed_official	324:406fd2029f23	1233	#define BS_LPUART_CTRL_RSRC (1U) /!< Bit field size in bits for LPUART_CTRL_RSRC. /
mbed_official	324:406fd2029f23	1234
mbed_official	324:406fd2029f23	1235	/! @brief Read current value of the LPUART_CTRL_RSRC field. /
mbed_official	324:406fd2029f23	1236	#define BR_LPUART_CTRL_RSRC(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RSRC))
mbed_official	324:406fd2029f23	1237
mbed_official	324:406fd2029f23	1238	/! @brief Format value for bitfield LPUART_CTRL_RSRC. /
mbed_official	324:406fd2029f23	1239	#define BF_LPUART_CTRL_RSRC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RSRC) & BM_LPUART_CTRL_RSRC)
mbed_official	324:406fd2029f23	1240
mbed_official	324:406fd2029f23	1241	/! @brief Set the RSRC field to a new value. /
mbed_official	324:406fd2029f23	1242	#define BW_LPUART_CTRL_RSRC(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RSRC) = (v))
mbed_official	324:406fd2029f23	1243	/@}/
mbed_official	324:406fd2029f23	1244
mbed_official	324:406fd2029f23	1245	/*!
mbed_official	324:406fd2029f23	1246	* @name Register LPUART_CTRL, field DOZEEN[6] (RW)
mbed_official	324:406fd2029f23	1247	*
mbed_official	324:406fd2029f23	1248	* Values:
mbed_official	324:406fd2029f23	1249	* - 0 - LPUART is enabled in Doze mode.
mbed_official	324:406fd2029f23	1250	* - 1 - LPUART is disabled in Doze mode.
mbed_official	324:406fd2029f23	1251	*/
mbed_official	324:406fd2029f23	1252	/@{/
mbed_official	324:406fd2029f23	1253	#define BP_LPUART_CTRL_DOZEEN (6U) /!< Bit position for LPUART_CTRL_DOZEEN. /
mbed_official	324:406fd2029f23	1254	#define BM_LPUART_CTRL_DOZEEN (0x00000040U) /!< Bit mask for LPUART_CTRL_DOZEEN. /
mbed_official	324:406fd2029f23	1255	#define BS_LPUART_CTRL_DOZEEN (1U) /!< Bit field size in bits for LPUART_CTRL_DOZEEN. /
mbed_official	324:406fd2029f23	1256
mbed_official	324:406fd2029f23	1257	/! @brief Read current value of the LPUART_CTRL_DOZEEN field. /
mbed_official	324:406fd2029f23	1258	#define BR_LPUART_CTRL_DOZEEN(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_DOZEEN))
mbed_official	324:406fd2029f23	1259
mbed_official	324:406fd2029f23	1260	/! @brief Format value for bitfield LPUART_CTRL_DOZEEN. /
mbed_official	324:406fd2029f23	1261	#define BF_LPUART_CTRL_DOZEEN(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_DOZEEN) & BM_LPUART_CTRL_DOZEEN)
mbed_official	324:406fd2029f23	1262
mbed_official	324:406fd2029f23	1263	/! @brief Set the DOZEEN field to a new value. /
mbed_official	324:406fd2029f23	1264	#define BW_LPUART_CTRL_DOZEEN(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_DOZEEN) = (v))
mbed_official	324:406fd2029f23	1265	/@}/
mbed_official	324:406fd2029f23	1266
mbed_official	324:406fd2029f23	1267	/*!
mbed_official	324:406fd2029f23	1268	* @name Register LPUART_CTRL, field LOOPS[7] (RW)
mbed_official	324:406fd2029f23	1269	*
mbed_official	324:406fd2029f23	1270	* When LOOPS is set, the LPUART_RX pin is disconnected from the LPUART and the
mbed_official	324:406fd2029f23	1271	* transmitter output is internally connected to the receiver input. The
mbed_official	324:406fd2029f23	1272	* transmitter and the receiver must be enabled to use the loop function.
mbed_official	324:406fd2029f23	1273	*
mbed_official	324:406fd2029f23	1274	* Values:
mbed_official	324:406fd2029f23	1275	* - 0 - Normal operation - LPUART_RX and LPUART_TX use separate pins.
mbed_official	324:406fd2029f23	1276	* - 1 - Loop mode or single-wire mode where transmitter outputs are internally
mbed_official	324:406fd2029f23	1277	* connected to receiver input (see RSRC bit).
mbed_official	324:406fd2029f23	1278	*/
mbed_official	324:406fd2029f23	1279	/@{/
mbed_official	324:406fd2029f23	1280	#define BP_LPUART_CTRL_LOOPS (7U) /!< Bit position for LPUART_CTRL_LOOPS. /
mbed_official	324:406fd2029f23	1281	#define BM_LPUART_CTRL_LOOPS (0x00000080U) /!< Bit mask for LPUART_CTRL_LOOPS. /
mbed_official	324:406fd2029f23	1282	#define BS_LPUART_CTRL_LOOPS (1U) /!< Bit field size in bits for LPUART_CTRL_LOOPS. /
mbed_official	324:406fd2029f23	1283
mbed_official	324:406fd2029f23	1284	/! @brief Read current value of the LPUART_CTRL_LOOPS field. /
mbed_official	324:406fd2029f23	1285	#define BR_LPUART_CTRL_LOOPS(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_LOOPS))
mbed_official	324:406fd2029f23	1286
mbed_official	324:406fd2029f23	1287	/! @brief Format value for bitfield LPUART_CTRL_LOOPS. /
mbed_official	324:406fd2029f23	1288	#define BF_LPUART_CTRL_LOOPS(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_LOOPS) & BM_LPUART_CTRL_LOOPS)
mbed_official	324:406fd2029f23	1289
mbed_official	324:406fd2029f23	1290	/! @brief Set the LOOPS field to a new value. /
mbed_official	324:406fd2029f23	1291	#define BW_LPUART_CTRL_LOOPS(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_LOOPS) = (v))
mbed_official	324:406fd2029f23	1292	/@}/
mbed_official	324:406fd2029f23	1293
mbed_official	324:406fd2029f23	1294	/*!
mbed_official	324:406fd2029f23	1295	* @name Register LPUART_CTRL, field IDLECFG[10:8] (RW)
mbed_official	324:406fd2029f23	1296	*
mbed_official	324:406fd2029f23	1297	* Configures the number of idle characters that must be received before the
mbed_official	324:406fd2029f23	1298	* IDLE flag is set.
mbed_official	324:406fd2029f23	1299	*
mbed_official	324:406fd2029f23	1300	* Values:
mbed_official	324:406fd2029f23	1301	* - 000 - 1 idle character
mbed_official	324:406fd2029f23	1302	* - 001 - 2 idle characters
mbed_official	324:406fd2029f23	1303	* - 010 - 4 idle characters
mbed_official	324:406fd2029f23	1304	* - 011 - 8 idle characters
mbed_official	324:406fd2029f23	1305	* - 100 - 16 idle characters
mbed_official	324:406fd2029f23	1306	* - 101 - 32 idle characters
mbed_official	324:406fd2029f23	1307	* - 110 - 64 idle characters
mbed_official	324:406fd2029f23	1308	* - 111 - 128 idle characters
mbed_official	324:406fd2029f23	1309	*/
mbed_official	324:406fd2029f23	1310	/@{/
mbed_official	324:406fd2029f23	1311	#define BP_LPUART_CTRL_IDLECFG (8U) /!< Bit position for LPUART_CTRL_IDLECFG. /
mbed_official	324:406fd2029f23	1312	#define BM_LPUART_CTRL_IDLECFG (0x00000700U) /!< Bit mask for LPUART_CTRL_IDLECFG. /
mbed_official	324:406fd2029f23	1313	#define BS_LPUART_CTRL_IDLECFG (3U) /!< Bit field size in bits for LPUART_CTRL_IDLECFG. /
mbed_official	324:406fd2029f23	1314
mbed_official	324:406fd2029f23	1315	/! @brief Read current value of the LPUART_CTRL_IDLECFG field. /
mbed_official	324:406fd2029f23	1316	#define BR_LPUART_CTRL_IDLECFG(x) (HW_LPUART_CTRL(x).B.IDLECFG)
mbed_official	324:406fd2029f23	1317
mbed_official	324:406fd2029f23	1318	/! @brief Format value for bitfield LPUART_CTRL_IDLECFG. /
mbed_official	324:406fd2029f23	1319	#define BF_LPUART_CTRL_IDLECFG(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_IDLECFG) & BM_LPUART_CTRL_IDLECFG)
mbed_official	324:406fd2029f23	1320
mbed_official	324:406fd2029f23	1321	/! @brief Set the IDLECFG field to a new value. /
mbed_official	324:406fd2029f23	1322	#define BW_LPUART_CTRL_IDLECFG(x, v) (HW_LPUART_CTRL_WR(x, (HW_LPUART_CTRL_RD(x) & ~BM_LPUART_CTRL_IDLECFG) \| BF_LPUART_CTRL_IDLECFG(v)))
mbed_official	324:406fd2029f23	1323	/@}/
mbed_official	324:406fd2029f23	1324
mbed_official	324:406fd2029f23	1325	/*!
mbed_official	324:406fd2029f23	1326	* @name Register LPUART_CTRL, field MA2IE[14] (RW)
mbed_official	324:406fd2029f23	1327	*
mbed_official	324:406fd2029f23	1328	* Values:
mbed_official	324:406fd2029f23	1329	* - 0 - MA2F interrupt disabled
mbed_official	324:406fd2029f23	1330	* - 1 - MA2F interrupt enabled
mbed_official	324:406fd2029f23	1331	*/
mbed_official	324:406fd2029f23	1332	/@{/
mbed_official	324:406fd2029f23	1333	#define BP_LPUART_CTRL_MA2IE (14U) /!< Bit position for LPUART_CTRL_MA2IE. /
mbed_official	324:406fd2029f23	1334	#define BM_LPUART_CTRL_MA2IE (0x00004000U) /!< Bit mask for LPUART_CTRL_MA2IE. /
mbed_official	324:406fd2029f23	1335	#define BS_LPUART_CTRL_MA2IE (1U) /!< Bit field size in bits for LPUART_CTRL_MA2IE. /
mbed_official	324:406fd2029f23	1336
mbed_official	324:406fd2029f23	1337	/! @brief Read current value of the LPUART_CTRL_MA2IE field. /
mbed_official	324:406fd2029f23	1338	#define BR_LPUART_CTRL_MA2IE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA2IE))
mbed_official	324:406fd2029f23	1339
mbed_official	324:406fd2029f23	1340	/! @brief Format value for bitfield LPUART_CTRL_MA2IE. /
mbed_official	324:406fd2029f23	1341	#define BF_LPUART_CTRL_MA2IE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_MA2IE) & BM_LPUART_CTRL_MA2IE)
mbed_official	324:406fd2029f23	1342
mbed_official	324:406fd2029f23	1343	/! @brief Set the MA2IE field to a new value. /
mbed_official	324:406fd2029f23	1344	#define BW_LPUART_CTRL_MA2IE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA2IE) = (v))
mbed_official	324:406fd2029f23	1345	/@}/
mbed_official	324:406fd2029f23	1346
mbed_official	324:406fd2029f23	1347	/*!
mbed_official	324:406fd2029f23	1348	* @name Register LPUART_CTRL, field MA1IE[15] (RW)
mbed_official	324:406fd2029f23	1349	*
mbed_official	324:406fd2029f23	1350	* Values:
mbed_official	324:406fd2029f23	1351	* - 0 - MA1F interrupt disabled
mbed_official	324:406fd2029f23	1352	* - 1 - MA1F interrupt enabled
mbed_official	324:406fd2029f23	1353	*/
mbed_official	324:406fd2029f23	1354	/@{/
mbed_official	324:406fd2029f23	1355	#define BP_LPUART_CTRL_MA1IE (15U) /!< Bit position for LPUART_CTRL_MA1IE. /
mbed_official	324:406fd2029f23	1356	#define BM_LPUART_CTRL_MA1IE (0x00008000U) /!< Bit mask for LPUART_CTRL_MA1IE. /
mbed_official	324:406fd2029f23	1357	#define BS_LPUART_CTRL_MA1IE (1U) /!< Bit field size in bits for LPUART_CTRL_MA1IE. /
mbed_official	324:406fd2029f23	1358
mbed_official	324:406fd2029f23	1359	/! @brief Read current value of the LPUART_CTRL_MA1IE field. /
mbed_official	324:406fd2029f23	1360	#define BR_LPUART_CTRL_MA1IE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA1IE))
mbed_official	324:406fd2029f23	1361
mbed_official	324:406fd2029f23	1362	/! @brief Format value for bitfield LPUART_CTRL_MA1IE. /
mbed_official	324:406fd2029f23	1363	#define BF_LPUART_CTRL_MA1IE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_MA1IE) & BM_LPUART_CTRL_MA1IE)
mbed_official	324:406fd2029f23	1364
mbed_official	324:406fd2029f23	1365	/! @brief Set the MA1IE field to a new value. /
mbed_official	324:406fd2029f23	1366	#define BW_LPUART_CTRL_MA1IE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_MA1IE) = (v))
mbed_official	324:406fd2029f23	1367	/@}/
mbed_official	324:406fd2029f23	1368
mbed_official	324:406fd2029f23	1369	/*!
mbed_official	324:406fd2029f23	1370	* @name Register LPUART_CTRL, field SBK[16] (RW)
mbed_official	324:406fd2029f23	1371	*
mbed_official	324:406fd2029f23	1372	* Writing a 1 and then a 0 to SBK queues a break character in the transmit data
mbed_official	324:406fd2029f23	1373	* stream. Additional break characters of 10 to 13, or 13 to 16 if
mbed_official	324:406fd2029f23	1374	* LPUART_STATBRK13] is set, bit times of logic 0 are queued as long as SBK is set. Depending
mbed_official	324:406fd2029f23	1375	* on the timing of the set and clear of SBK relative to the information
mbed_official	324:406fd2029f23	1376	* currently being transmitted, a second break character may be queued before software
mbed_official	324:406fd2029f23	1377	* clears SBK.
mbed_official	324:406fd2029f23	1378	*
mbed_official	324:406fd2029f23	1379	* Values:
mbed_official	324:406fd2029f23	1380	* - 0 - Normal transmitter operation.
mbed_official	324:406fd2029f23	1381	* - 1 - Queue break character(s) to be sent.
mbed_official	324:406fd2029f23	1382	*/
mbed_official	324:406fd2029f23	1383	/@{/
mbed_official	324:406fd2029f23	1384	#define BP_LPUART_CTRL_SBK (16U) /!< Bit position for LPUART_CTRL_SBK. /
mbed_official	324:406fd2029f23	1385	#define BM_LPUART_CTRL_SBK (0x00010000U) /!< Bit mask for LPUART_CTRL_SBK. /
mbed_official	324:406fd2029f23	1386	#define BS_LPUART_CTRL_SBK (1U) /!< Bit field size in bits for LPUART_CTRL_SBK. /
mbed_official	324:406fd2029f23	1387
mbed_official	324:406fd2029f23	1388	/! @brief Read current value of the LPUART_CTRL_SBK field. /
mbed_official	324:406fd2029f23	1389	#define BR_LPUART_CTRL_SBK(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_SBK))
mbed_official	324:406fd2029f23	1390
mbed_official	324:406fd2029f23	1391	/! @brief Format value for bitfield LPUART_CTRL_SBK. /
mbed_official	324:406fd2029f23	1392	#define BF_LPUART_CTRL_SBK(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_SBK) & BM_LPUART_CTRL_SBK)
mbed_official	324:406fd2029f23	1393
mbed_official	324:406fd2029f23	1394	/! @brief Set the SBK field to a new value. /
mbed_official	324:406fd2029f23	1395	#define BW_LPUART_CTRL_SBK(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_SBK) = (v))
mbed_official	324:406fd2029f23	1396	/@}/
mbed_official	324:406fd2029f23	1397
mbed_official	324:406fd2029f23	1398	/*!
mbed_official	324:406fd2029f23	1399	* @name Register LPUART_CTRL, field RWU[17] (RW)
mbed_official	324:406fd2029f23	1400	*
mbed_official	324:406fd2029f23	1401	* This field can be set to place the LPUART receiver in a standby state. RWU
mbed_official	324:406fd2029f23	1402	* automatically clears when an RWU event occurs, that is, an IDLE event when
mbed_official	324:406fd2029f23	1403	* CTRL[WAKE] is clear or an address match when CTRL[WAKE] is set with STAT[RWUID] is
mbed_official	324:406fd2029f23	1404	* clear. RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the
mbed_official	324:406fd2029f23	1405	* channel is currently not idle. This can be determined by STAT[RAF]. If the flag is
mbed_official	324:406fd2029f23	1406	* set to wake up an IDLE event and the channel is already idle, it is possible
mbed_official	324:406fd2029f23	1407	* that the LPUART will discard data. This is because the data must be received or
mbed_official	324:406fd2029f23	1408	* a LIN break detected after an IDLE is detected before IDLE is allowed to
mbed_official	324:406fd2029f23	1409	* reasserted.
mbed_official	324:406fd2029f23	1410	*
mbed_official	324:406fd2029f23	1411	* Values:
mbed_official	324:406fd2029f23	1412	* - 0 - Normal receiver operation.
mbed_official	324:406fd2029f23	1413	* - 1 - LPUART receiver in standby waiting for wakeup condition.
mbed_official	324:406fd2029f23	1414	*/
mbed_official	324:406fd2029f23	1415	/@{/
mbed_official	324:406fd2029f23	1416	#define BP_LPUART_CTRL_RWU (17U) /!< Bit position for LPUART_CTRL_RWU. /
mbed_official	324:406fd2029f23	1417	#define BM_LPUART_CTRL_RWU (0x00020000U) /!< Bit mask for LPUART_CTRL_RWU. /
mbed_official	324:406fd2029f23	1418	#define BS_LPUART_CTRL_RWU (1U) /!< Bit field size in bits for LPUART_CTRL_RWU. /
mbed_official	324:406fd2029f23	1419
mbed_official	324:406fd2029f23	1420	/! @brief Read current value of the LPUART_CTRL_RWU field. /
mbed_official	324:406fd2029f23	1421	#define BR_LPUART_CTRL_RWU(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RWU))
mbed_official	324:406fd2029f23	1422
mbed_official	324:406fd2029f23	1423	/! @brief Format value for bitfield LPUART_CTRL_RWU. /
mbed_official	324:406fd2029f23	1424	#define BF_LPUART_CTRL_RWU(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RWU) & BM_LPUART_CTRL_RWU)
mbed_official	324:406fd2029f23	1425
mbed_official	324:406fd2029f23	1426	/! @brief Set the RWU field to a new value. /
mbed_official	324:406fd2029f23	1427	#define BW_LPUART_CTRL_RWU(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RWU) = (v))
mbed_official	324:406fd2029f23	1428	/@}/
mbed_official	324:406fd2029f23	1429
mbed_official	324:406fd2029f23	1430	/*!
mbed_official	324:406fd2029f23	1431	* @name Register LPUART_CTRL, field RE[18] (RW)
mbed_official	324:406fd2029f23	1432	*
mbed_official	324:406fd2029f23	1433	* Enables the LPUART receiver. When RE is written to 0, this register bit will
mbed_official	324:406fd2029f23	1434	* read as 1 until the receiver finishes receiving the current character (if any).
mbed_official	324:406fd2029f23	1435	*
mbed_official	324:406fd2029f23	1436	* Values:
mbed_official	324:406fd2029f23	1437	* - 0 - Receiver disabled.
mbed_official	324:406fd2029f23	1438	* - 1 - Receiver enabled.
mbed_official	324:406fd2029f23	1439	*/
mbed_official	324:406fd2029f23	1440	/@{/
mbed_official	324:406fd2029f23	1441	#define BP_LPUART_CTRL_RE (18U) /!< Bit position for LPUART_CTRL_RE. /
mbed_official	324:406fd2029f23	1442	#define BM_LPUART_CTRL_RE (0x00040000U) /!< Bit mask for LPUART_CTRL_RE. /
mbed_official	324:406fd2029f23	1443	#define BS_LPUART_CTRL_RE (1U) /!< Bit field size in bits for LPUART_CTRL_RE. /
mbed_official	324:406fd2029f23	1444
mbed_official	324:406fd2029f23	1445	/! @brief Read current value of the LPUART_CTRL_RE field. /
mbed_official	324:406fd2029f23	1446	#define BR_LPUART_CTRL_RE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RE))
mbed_official	324:406fd2029f23	1447
mbed_official	324:406fd2029f23	1448	/! @brief Format value for bitfield LPUART_CTRL_RE. /
mbed_official	324:406fd2029f23	1449	#define BF_LPUART_CTRL_RE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RE) & BM_LPUART_CTRL_RE)
mbed_official	324:406fd2029f23	1450
mbed_official	324:406fd2029f23	1451	/! @brief Set the RE field to a new value. /
mbed_official	324:406fd2029f23	1452	#define BW_LPUART_CTRL_RE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RE) = (v))
mbed_official	324:406fd2029f23	1453	/@}/
mbed_official	324:406fd2029f23	1454
mbed_official	324:406fd2029f23	1455	/*!
mbed_official	324:406fd2029f23	1456	* @name Register LPUART_CTRL, field TE[19] (RW)
mbed_official	324:406fd2029f23	1457	*
mbed_official	324:406fd2029f23	1458	* Enables the LPUART transmitter. TE can also be used to queue an idle preamble
mbed_official	324:406fd2029f23	1459	* by clearing and then setting TE. When TE is cleared, this register bit will
mbed_official	324:406fd2029f23	1460	* read as 1 until the transmitter has completed the current character and the
mbed_official	324:406fd2029f23	1461	* LPUART_TX pin is tristated.
mbed_official	324:406fd2029f23	1462	*
mbed_official	324:406fd2029f23	1463	* Values:
mbed_official	324:406fd2029f23	1464	* - 0 - Transmitter disabled.
mbed_official	324:406fd2029f23	1465	* - 1 - Transmitter enabled.
mbed_official	324:406fd2029f23	1466	*/
mbed_official	324:406fd2029f23	1467	/@{/
mbed_official	324:406fd2029f23	1468	#define BP_LPUART_CTRL_TE (19U) /!< Bit position for LPUART_CTRL_TE. /
mbed_official	324:406fd2029f23	1469	#define BM_LPUART_CTRL_TE (0x00080000U) /!< Bit mask for LPUART_CTRL_TE. /
mbed_official	324:406fd2029f23	1470	#define BS_LPUART_CTRL_TE (1U) /!< Bit field size in bits for LPUART_CTRL_TE. /
mbed_official	324:406fd2029f23	1471
mbed_official	324:406fd2029f23	1472	/! @brief Read current value of the LPUART_CTRL_TE field. /
mbed_official	324:406fd2029f23	1473	#define BR_LPUART_CTRL_TE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TE))
mbed_official	324:406fd2029f23	1474
mbed_official	324:406fd2029f23	1475	/! @brief Format value for bitfield LPUART_CTRL_TE. /
mbed_official	324:406fd2029f23	1476	#define BF_LPUART_CTRL_TE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TE) & BM_LPUART_CTRL_TE)
mbed_official	324:406fd2029f23	1477
mbed_official	324:406fd2029f23	1478	/! @brief Set the TE field to a new value. /
mbed_official	324:406fd2029f23	1479	#define BW_LPUART_CTRL_TE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TE) = (v))
mbed_official	324:406fd2029f23	1480	/@}/
mbed_official	324:406fd2029f23	1481
mbed_official	324:406fd2029f23	1482	/*!
mbed_official	324:406fd2029f23	1483	* @name Register LPUART_CTRL, field ILIE[20] (RW)
mbed_official	324:406fd2029f23	1484	*
mbed_official	324:406fd2029f23	1485	* ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
mbed_official	324:406fd2029f23	1486	*
mbed_official	324:406fd2029f23	1487	* Values:
mbed_official	324:406fd2029f23	1488	* - 0 - Hardware interrupts from IDLE disabled; use polling.
mbed_official	324:406fd2029f23	1489	* - 1 - Hardware interrupt requested when IDLE flag is 1.
mbed_official	324:406fd2029f23	1490	*/
mbed_official	324:406fd2029f23	1491	/@{/
mbed_official	324:406fd2029f23	1492	#define BP_LPUART_CTRL_ILIE (20U) /!< Bit position for LPUART_CTRL_ILIE. /
mbed_official	324:406fd2029f23	1493	#define BM_LPUART_CTRL_ILIE (0x00100000U) /!< Bit mask for LPUART_CTRL_ILIE. /
mbed_official	324:406fd2029f23	1494	#define BS_LPUART_CTRL_ILIE (1U) /!< Bit field size in bits for LPUART_CTRL_ILIE. /
mbed_official	324:406fd2029f23	1495
mbed_official	324:406fd2029f23	1496	/! @brief Read current value of the LPUART_CTRL_ILIE field. /
mbed_official	324:406fd2029f23	1497	#define BR_LPUART_CTRL_ILIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILIE))
mbed_official	324:406fd2029f23	1498
mbed_official	324:406fd2029f23	1499	/! @brief Format value for bitfield LPUART_CTRL_ILIE. /
mbed_official	324:406fd2029f23	1500	#define BF_LPUART_CTRL_ILIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ILIE) & BM_LPUART_CTRL_ILIE)
mbed_official	324:406fd2029f23	1501
mbed_official	324:406fd2029f23	1502	/! @brief Set the ILIE field to a new value. /
mbed_official	324:406fd2029f23	1503	#define BW_LPUART_CTRL_ILIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ILIE) = (v))
mbed_official	324:406fd2029f23	1504	/@}/
mbed_official	324:406fd2029f23	1505
mbed_official	324:406fd2029f23	1506	/*!
mbed_official	324:406fd2029f23	1507	* @name Register LPUART_CTRL, field RIE[21] (RW)
mbed_official	324:406fd2029f23	1508	*
mbed_official	324:406fd2029f23	1509	* Enables STAT[RDRF] to generate interrupt requests.
mbed_official	324:406fd2029f23	1510	*
mbed_official	324:406fd2029f23	1511	* Values:
mbed_official	324:406fd2029f23	1512	* - 0 - Hardware interrupts from RDRF disabled; use polling.
mbed_official	324:406fd2029f23	1513	* - 1 - Hardware interrupt requested when RDRF flag is 1.
mbed_official	324:406fd2029f23	1514	*/
mbed_official	324:406fd2029f23	1515	/@{/
mbed_official	324:406fd2029f23	1516	#define BP_LPUART_CTRL_RIE (21U) /!< Bit position for LPUART_CTRL_RIE. /
mbed_official	324:406fd2029f23	1517	#define BM_LPUART_CTRL_RIE (0x00200000U) /!< Bit mask for LPUART_CTRL_RIE. /
mbed_official	324:406fd2029f23	1518	#define BS_LPUART_CTRL_RIE (1U) /!< Bit field size in bits for LPUART_CTRL_RIE. /
mbed_official	324:406fd2029f23	1519
mbed_official	324:406fd2029f23	1520	/! @brief Read current value of the LPUART_CTRL_RIE field. /
mbed_official	324:406fd2029f23	1521	#define BR_LPUART_CTRL_RIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RIE))
mbed_official	324:406fd2029f23	1522
mbed_official	324:406fd2029f23	1523	/! @brief Format value for bitfield LPUART_CTRL_RIE. /
mbed_official	324:406fd2029f23	1524	#define BF_LPUART_CTRL_RIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_RIE) & BM_LPUART_CTRL_RIE)
mbed_official	324:406fd2029f23	1525
mbed_official	324:406fd2029f23	1526	/! @brief Set the RIE field to a new value. /
mbed_official	324:406fd2029f23	1527	#define BW_LPUART_CTRL_RIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_RIE) = (v))
mbed_official	324:406fd2029f23	1528	/@}/
mbed_official	324:406fd2029f23	1529
mbed_official	324:406fd2029f23	1530	/*!
mbed_official	324:406fd2029f23	1531	* @name Register LPUART_CTRL, field TCIE[22] (RW)
mbed_official	324:406fd2029f23	1532	*
mbed_official	324:406fd2029f23	1533	* TCIE enables the transmission complete flag, TC, to generate interrupt
mbed_official	324:406fd2029f23	1534	* requests.
mbed_official	324:406fd2029f23	1535	*
mbed_official	324:406fd2029f23	1536	* Values:
mbed_official	324:406fd2029f23	1537	* - 0 - Hardware interrupts from TC disabled; use polling.
mbed_official	324:406fd2029f23	1538	* - 1 - Hardware interrupt requested when TC flag is 1.
mbed_official	324:406fd2029f23	1539	*/
mbed_official	324:406fd2029f23	1540	/@{/
mbed_official	324:406fd2029f23	1541	#define BP_LPUART_CTRL_TCIE (22U) /!< Bit position for LPUART_CTRL_TCIE. /
mbed_official	324:406fd2029f23	1542	#define BM_LPUART_CTRL_TCIE (0x00400000U) /!< Bit mask for LPUART_CTRL_TCIE. /
mbed_official	324:406fd2029f23	1543	#define BS_LPUART_CTRL_TCIE (1U) /!< Bit field size in bits for LPUART_CTRL_TCIE. /
mbed_official	324:406fd2029f23	1544
mbed_official	324:406fd2029f23	1545	/! @brief Read current value of the LPUART_CTRL_TCIE field. /
mbed_official	324:406fd2029f23	1546	#define BR_LPUART_CTRL_TCIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TCIE))
mbed_official	324:406fd2029f23	1547
mbed_official	324:406fd2029f23	1548	/! @brief Format value for bitfield LPUART_CTRL_TCIE. /
mbed_official	324:406fd2029f23	1549	#define BF_LPUART_CTRL_TCIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TCIE) & BM_LPUART_CTRL_TCIE)
mbed_official	324:406fd2029f23	1550
mbed_official	324:406fd2029f23	1551	/! @brief Set the TCIE field to a new value. /
mbed_official	324:406fd2029f23	1552	#define BW_LPUART_CTRL_TCIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TCIE) = (v))
mbed_official	324:406fd2029f23	1553	/@}/
mbed_official	324:406fd2029f23	1554
mbed_official	324:406fd2029f23	1555	/*!
mbed_official	324:406fd2029f23	1556	* @name Register LPUART_CTRL, field TIE[23] (RW)
mbed_official	324:406fd2029f23	1557	*
mbed_official	324:406fd2029f23	1558	* Enables STAT[TDRE] to generate interrupt requests.
mbed_official	324:406fd2029f23	1559	*
mbed_official	324:406fd2029f23	1560	* Values:
mbed_official	324:406fd2029f23	1561	* - 0 - Hardware interrupts from TDRE disabled; use polling.
mbed_official	324:406fd2029f23	1562	* - 1 - Hardware interrupt requested when TDRE flag is 1.
mbed_official	324:406fd2029f23	1563	*/
mbed_official	324:406fd2029f23	1564	/@{/
mbed_official	324:406fd2029f23	1565	#define BP_LPUART_CTRL_TIE (23U) /!< Bit position for LPUART_CTRL_TIE. /
mbed_official	324:406fd2029f23	1566	#define BM_LPUART_CTRL_TIE (0x00800000U) /!< Bit mask for LPUART_CTRL_TIE. /
mbed_official	324:406fd2029f23	1567	#define BS_LPUART_CTRL_TIE (1U) /!< Bit field size in bits for LPUART_CTRL_TIE. /
mbed_official	324:406fd2029f23	1568
mbed_official	324:406fd2029f23	1569	/! @brief Read current value of the LPUART_CTRL_TIE field. /
mbed_official	324:406fd2029f23	1570	#define BR_LPUART_CTRL_TIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TIE))
mbed_official	324:406fd2029f23	1571
mbed_official	324:406fd2029f23	1572	/! @brief Format value for bitfield LPUART_CTRL_TIE. /
mbed_official	324:406fd2029f23	1573	#define BF_LPUART_CTRL_TIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TIE) & BM_LPUART_CTRL_TIE)
mbed_official	324:406fd2029f23	1574
mbed_official	324:406fd2029f23	1575	/! @brief Set the TIE field to a new value. /
mbed_official	324:406fd2029f23	1576	#define BW_LPUART_CTRL_TIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TIE) = (v))
mbed_official	324:406fd2029f23	1577	/@}/
mbed_official	324:406fd2029f23	1578
mbed_official	324:406fd2029f23	1579	/*!
mbed_official	324:406fd2029f23	1580	* @name Register LPUART_CTRL, field PEIE[24] (RW)
mbed_official	324:406fd2029f23	1581	*
mbed_official	324:406fd2029f23	1582	* This bit enables the parity error flag (PF) to generate hardware interrupt
mbed_official	324:406fd2029f23	1583	* requests.
mbed_official	324:406fd2029f23	1584	*
mbed_official	324:406fd2029f23	1585	* Values:
mbed_official	324:406fd2029f23	1586	* - 0 - PF interrupts disabled; use polling).
mbed_official	324:406fd2029f23	1587	* - 1 - Hardware interrupt requested when PF is set.
mbed_official	324:406fd2029f23	1588	*/
mbed_official	324:406fd2029f23	1589	/@{/
mbed_official	324:406fd2029f23	1590	#define BP_LPUART_CTRL_PEIE (24U) /!< Bit position for LPUART_CTRL_PEIE. /
mbed_official	324:406fd2029f23	1591	#define BM_LPUART_CTRL_PEIE (0x01000000U) /!< Bit mask for LPUART_CTRL_PEIE. /
mbed_official	324:406fd2029f23	1592	#define BS_LPUART_CTRL_PEIE (1U) /!< Bit field size in bits for LPUART_CTRL_PEIE. /
mbed_official	324:406fd2029f23	1593
mbed_official	324:406fd2029f23	1594	/! @brief Read current value of the LPUART_CTRL_PEIE field. /
mbed_official	324:406fd2029f23	1595	#define BR_LPUART_CTRL_PEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PEIE))
mbed_official	324:406fd2029f23	1596
mbed_official	324:406fd2029f23	1597	/! @brief Format value for bitfield LPUART_CTRL_PEIE. /
mbed_official	324:406fd2029f23	1598	#define BF_LPUART_CTRL_PEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_PEIE) & BM_LPUART_CTRL_PEIE)
mbed_official	324:406fd2029f23	1599
mbed_official	324:406fd2029f23	1600	/! @brief Set the PEIE field to a new value. /
mbed_official	324:406fd2029f23	1601	#define BW_LPUART_CTRL_PEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_PEIE) = (v))
mbed_official	324:406fd2029f23	1602	/@}/
mbed_official	324:406fd2029f23	1603
mbed_official	324:406fd2029f23	1604	/*!
mbed_official	324:406fd2029f23	1605	* @name Register LPUART_CTRL, field FEIE[25] (RW)
mbed_official	324:406fd2029f23	1606	*
mbed_official	324:406fd2029f23	1607	* This bit enables the framing error flag (FE) to generate hardware interrupt
mbed_official	324:406fd2029f23	1608	* requests.
mbed_official	324:406fd2029f23	1609	*
mbed_official	324:406fd2029f23	1610	* Values:
mbed_official	324:406fd2029f23	1611	* - 0 - FE interrupts disabled; use polling.
mbed_official	324:406fd2029f23	1612	* - 1 - Hardware interrupt requested when FE is set.
mbed_official	324:406fd2029f23	1613	*/
mbed_official	324:406fd2029f23	1614	/@{/
mbed_official	324:406fd2029f23	1615	#define BP_LPUART_CTRL_FEIE (25U) /!< Bit position for LPUART_CTRL_FEIE. /
mbed_official	324:406fd2029f23	1616	#define BM_LPUART_CTRL_FEIE (0x02000000U) /!< Bit mask for LPUART_CTRL_FEIE. /
mbed_official	324:406fd2029f23	1617	#define BS_LPUART_CTRL_FEIE (1U) /!< Bit field size in bits for LPUART_CTRL_FEIE. /
mbed_official	324:406fd2029f23	1618
mbed_official	324:406fd2029f23	1619	/! @brief Read current value of the LPUART_CTRL_FEIE field. /
mbed_official	324:406fd2029f23	1620	#define BR_LPUART_CTRL_FEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_FEIE))
mbed_official	324:406fd2029f23	1621
mbed_official	324:406fd2029f23	1622	/! @brief Format value for bitfield LPUART_CTRL_FEIE. /
mbed_official	324:406fd2029f23	1623	#define BF_LPUART_CTRL_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_FEIE) & BM_LPUART_CTRL_FEIE)
mbed_official	324:406fd2029f23	1624
mbed_official	324:406fd2029f23	1625	/! @brief Set the FEIE field to a new value. /
mbed_official	324:406fd2029f23	1626	#define BW_LPUART_CTRL_FEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_FEIE) = (v))
mbed_official	324:406fd2029f23	1627	/@}/
mbed_official	324:406fd2029f23	1628
mbed_official	324:406fd2029f23	1629	/*!
mbed_official	324:406fd2029f23	1630	* @name Register LPUART_CTRL, field NEIE[26] (RW)
mbed_official	324:406fd2029f23	1631	*
mbed_official	324:406fd2029f23	1632	* This bit enables the noise flag (NF) to generate hardware interrupt requests.
mbed_official	324:406fd2029f23	1633	*
mbed_official	324:406fd2029f23	1634	* Values:
mbed_official	324:406fd2029f23	1635	* - 0 - NF interrupts disabled; use polling.
mbed_official	324:406fd2029f23	1636	* - 1 - Hardware interrupt requested when NF is set.
mbed_official	324:406fd2029f23	1637	*/
mbed_official	324:406fd2029f23	1638	/@{/
mbed_official	324:406fd2029f23	1639	#define BP_LPUART_CTRL_NEIE (26U) /!< Bit position for LPUART_CTRL_NEIE. /
mbed_official	324:406fd2029f23	1640	#define BM_LPUART_CTRL_NEIE (0x04000000U) /!< Bit mask for LPUART_CTRL_NEIE. /
mbed_official	324:406fd2029f23	1641	#define BS_LPUART_CTRL_NEIE (1U) /!< Bit field size in bits for LPUART_CTRL_NEIE. /
mbed_official	324:406fd2029f23	1642
mbed_official	324:406fd2029f23	1643	/! @brief Read current value of the LPUART_CTRL_NEIE field. /
mbed_official	324:406fd2029f23	1644	#define BR_LPUART_CTRL_NEIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_NEIE))
mbed_official	324:406fd2029f23	1645
mbed_official	324:406fd2029f23	1646	/! @brief Format value for bitfield LPUART_CTRL_NEIE. /
mbed_official	324:406fd2029f23	1647	#define BF_LPUART_CTRL_NEIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_NEIE) & BM_LPUART_CTRL_NEIE)
mbed_official	324:406fd2029f23	1648
mbed_official	324:406fd2029f23	1649	/! @brief Set the NEIE field to a new value. /
mbed_official	324:406fd2029f23	1650	#define BW_LPUART_CTRL_NEIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_NEIE) = (v))
mbed_official	324:406fd2029f23	1651	/@}/
mbed_official	324:406fd2029f23	1652
mbed_official	324:406fd2029f23	1653	/*!
mbed_official	324:406fd2029f23	1654	* @name Register LPUART_CTRL, field ORIE[27] (RW)
mbed_official	324:406fd2029f23	1655	*
mbed_official	324:406fd2029f23	1656	* This bit enables the overrun flag (OR) to generate hardware interrupt
mbed_official	324:406fd2029f23	1657	* requests.
mbed_official	324:406fd2029f23	1658	*
mbed_official	324:406fd2029f23	1659	* Values:
mbed_official	324:406fd2029f23	1660	* - 0 - OR interrupts disabled; use polling.
mbed_official	324:406fd2029f23	1661	* - 1 - Hardware interrupt requested when OR is set.
mbed_official	324:406fd2029f23	1662	*/
mbed_official	324:406fd2029f23	1663	/@{/
mbed_official	324:406fd2029f23	1664	#define BP_LPUART_CTRL_ORIE (27U) /!< Bit position for LPUART_CTRL_ORIE. /
mbed_official	324:406fd2029f23	1665	#define BM_LPUART_CTRL_ORIE (0x08000000U) /!< Bit mask for LPUART_CTRL_ORIE. /
mbed_official	324:406fd2029f23	1666	#define BS_LPUART_CTRL_ORIE (1U) /!< Bit field size in bits for LPUART_CTRL_ORIE. /
mbed_official	324:406fd2029f23	1667
mbed_official	324:406fd2029f23	1668	/! @brief Read current value of the LPUART_CTRL_ORIE field. /
mbed_official	324:406fd2029f23	1669	#define BR_LPUART_CTRL_ORIE(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ORIE))
mbed_official	324:406fd2029f23	1670
mbed_official	324:406fd2029f23	1671	/! @brief Format value for bitfield LPUART_CTRL_ORIE. /
mbed_official	324:406fd2029f23	1672	#define BF_LPUART_CTRL_ORIE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_ORIE) & BM_LPUART_CTRL_ORIE)
mbed_official	324:406fd2029f23	1673
mbed_official	324:406fd2029f23	1674	/! @brief Set the ORIE field to a new value. /
mbed_official	324:406fd2029f23	1675	#define BW_LPUART_CTRL_ORIE(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_ORIE) = (v))
mbed_official	324:406fd2029f23	1676	/@}/
mbed_official	324:406fd2029f23	1677
mbed_official	324:406fd2029f23	1678	/*!
mbed_official	324:406fd2029f23	1679	* @name Register LPUART_CTRL, field TXINV[28] (RW)
mbed_official	324:406fd2029f23	1680	*
mbed_official	324:406fd2029f23	1681	* Setting this bit reverses the polarity of the transmitted data output.
mbed_official	324:406fd2029f23	1682	* Setting TXINV inverts the LPUART_TX output for all cases: data bits, start and stop
mbed_official	324:406fd2029f23	1683	* bits, break, and idle.
mbed_official	324:406fd2029f23	1684	*
mbed_official	324:406fd2029f23	1685	* Values:
mbed_official	324:406fd2029f23	1686	* - 0 - Transmit data not inverted.
mbed_official	324:406fd2029f23	1687	* - 1 - Transmit data inverted.
mbed_official	324:406fd2029f23	1688	*/
mbed_official	324:406fd2029f23	1689	/@{/
mbed_official	324:406fd2029f23	1690	#define BP_LPUART_CTRL_TXINV (28U) /!< Bit position for LPUART_CTRL_TXINV. /
mbed_official	324:406fd2029f23	1691	#define BM_LPUART_CTRL_TXINV (0x10000000U) /!< Bit mask for LPUART_CTRL_TXINV. /
mbed_official	324:406fd2029f23	1692	#define BS_LPUART_CTRL_TXINV (1U) /!< Bit field size in bits for LPUART_CTRL_TXINV. /
mbed_official	324:406fd2029f23	1693
mbed_official	324:406fd2029f23	1694	/! @brief Read current value of the LPUART_CTRL_TXINV field. /
mbed_official	324:406fd2029f23	1695	#define BR_LPUART_CTRL_TXINV(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXINV))
mbed_official	324:406fd2029f23	1696
mbed_official	324:406fd2029f23	1697	/! @brief Format value for bitfield LPUART_CTRL_TXINV. /
mbed_official	324:406fd2029f23	1698	#define BF_LPUART_CTRL_TXINV(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TXINV) & BM_LPUART_CTRL_TXINV)
mbed_official	324:406fd2029f23	1699
mbed_official	324:406fd2029f23	1700	/! @brief Set the TXINV field to a new value. /
mbed_official	324:406fd2029f23	1701	#define BW_LPUART_CTRL_TXINV(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXINV) = (v))
mbed_official	324:406fd2029f23	1702	/@}/
mbed_official	324:406fd2029f23	1703
mbed_official	324:406fd2029f23	1704	/*!
mbed_official	324:406fd2029f23	1705	* @name Register LPUART_CTRL, field TXDIR[29] (RW)
mbed_official	324:406fd2029f23	1706	*
mbed_official	324:406fd2029f23	1707	* When the LPUART is configured for single-wire half-duplex operation (LOOPS =
mbed_official	324:406fd2029f23	1708	* RSRC = 1), this bit determines the direction of data at the LPUART_TX pin.
mbed_official	324:406fd2029f23	1709	* When clearing TXDIR, the transmitter will finish receiving the current character
mbed_official	324:406fd2029f23	1710	* (if any) before the receiver starts receiving data from the LPUART_TX pin.
mbed_official	324:406fd2029f23	1711	*
mbed_official	324:406fd2029f23	1712	* Values:
mbed_official	324:406fd2029f23	1713	* - 0 - LPUART_TX pin is an input in single-wire mode.
mbed_official	324:406fd2029f23	1714	* - 1 - LPUART_TX pin is an output in single-wire mode.
mbed_official	324:406fd2029f23	1715	*/
mbed_official	324:406fd2029f23	1716	/@{/
mbed_official	324:406fd2029f23	1717	#define BP_LPUART_CTRL_TXDIR (29U) /!< Bit position for LPUART_CTRL_TXDIR. /
mbed_official	324:406fd2029f23	1718	#define BM_LPUART_CTRL_TXDIR (0x20000000U) /!< Bit mask for LPUART_CTRL_TXDIR. /
mbed_official	324:406fd2029f23	1719	#define BS_LPUART_CTRL_TXDIR (1U) /!< Bit field size in bits for LPUART_CTRL_TXDIR. /
mbed_official	324:406fd2029f23	1720
mbed_official	324:406fd2029f23	1721	/! @brief Read current value of the LPUART_CTRL_TXDIR field. /
mbed_official	324:406fd2029f23	1722	#define BR_LPUART_CTRL_TXDIR(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXDIR))
mbed_official	324:406fd2029f23	1723
mbed_official	324:406fd2029f23	1724	/! @brief Format value for bitfield LPUART_CTRL_TXDIR. /
mbed_official	324:406fd2029f23	1725	#define BF_LPUART_CTRL_TXDIR(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_TXDIR) & BM_LPUART_CTRL_TXDIR)
mbed_official	324:406fd2029f23	1726
mbed_official	324:406fd2029f23	1727	/! @brief Set the TXDIR field to a new value. /
mbed_official	324:406fd2029f23	1728	#define BW_LPUART_CTRL_TXDIR(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_TXDIR) = (v))
mbed_official	324:406fd2029f23	1729	/@}/
mbed_official	324:406fd2029f23	1730
mbed_official	324:406fd2029f23	1731	/*!
mbed_official	324:406fd2029f23	1732	* @name Register LPUART_CTRL, field R9T8[30] (RW)
mbed_official	324:406fd2029f23	1733	*
mbed_official	324:406fd2029f23	1734	* R9 is the tenth data bit received when the LPUART is configured for 10-bit
mbed_official	324:406fd2029f23	1735	* data formats. When reading 10-bit data, read R9 before reading LPUART_DATA T8 is
mbed_official	324:406fd2029f23	1736	* the ninth data bit received when the LPUART is configured for 9-bit or 10-bit
mbed_official	324:406fd2029f23	1737	* data formats. When writing 9-bit or 10-bit data, write T8 before writing
mbed_official	324:406fd2029f23	1738	* LPUART_DATA. If T8 does not need to change from its previous value, such as when
mbed_official	324:406fd2029f23	1739	* it is used to generate address mark or parity, they it need not be written each
mbed_official	324:406fd2029f23	1740	* time LPUART_DATA is written.
mbed_official	324:406fd2029f23	1741	*/
mbed_official	324:406fd2029f23	1742	/@{/
mbed_official	324:406fd2029f23	1743	#define BP_LPUART_CTRL_R9T8 (30U) /!< Bit position for LPUART_CTRL_R9T8. /
mbed_official	324:406fd2029f23	1744	#define BM_LPUART_CTRL_R9T8 (0x40000000U) /!< Bit mask for LPUART_CTRL_R9T8. /
mbed_official	324:406fd2029f23	1745	#define BS_LPUART_CTRL_R9T8 (1U) /!< Bit field size in bits for LPUART_CTRL_R9T8. /
mbed_official	324:406fd2029f23	1746
mbed_official	324:406fd2029f23	1747	/! @brief Read current value of the LPUART_CTRL_R9T8 field. /
mbed_official	324:406fd2029f23	1748	#define BR_LPUART_CTRL_R9T8(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R9T8))
mbed_official	324:406fd2029f23	1749
mbed_official	324:406fd2029f23	1750	/! @brief Format value for bitfield LPUART_CTRL_R9T8. /
mbed_official	324:406fd2029f23	1751	#define BF_LPUART_CTRL_R9T8(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_R9T8) & BM_LPUART_CTRL_R9T8)
mbed_official	324:406fd2029f23	1752
mbed_official	324:406fd2029f23	1753	/! @brief Set the R9T8 field to a new value. /
mbed_official	324:406fd2029f23	1754	#define BW_LPUART_CTRL_R9T8(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R9T8) = (v))
mbed_official	324:406fd2029f23	1755	/@}/
mbed_official	324:406fd2029f23	1756
mbed_official	324:406fd2029f23	1757	/*!
mbed_official	324:406fd2029f23	1758	* @name Register LPUART_CTRL, field R8T9[31] (RW)
mbed_official	324:406fd2029f23	1759	*
mbed_official	324:406fd2029f23	1760	* R8 is the ninth data bit received when the LPUART is configured for 9-bit or
mbed_official	324:406fd2029f23	1761	* 10-bit data formats. When reading 9-bit or 10-bit data, read R8 before reading
mbed_official	324:406fd2029f23	1762	* LPUART_DATA. T9 is the tenth data bit received when the LPUART is configured
mbed_official	324:406fd2029f23	1763	* for 10-bit data formats. When writing 10-bit data, write T9 before writing
mbed_official	324:406fd2029f23	1764	* LPUART_DATA. If T9 does not need to change from its previous value, such as when
mbed_official	324:406fd2029f23	1765	* it is used to generate address mark or parity, they it need not be written
mbed_official	324:406fd2029f23	1766	* each time LPUART_DATA is written.
mbed_official	324:406fd2029f23	1767	*/
mbed_official	324:406fd2029f23	1768	/@{/
mbed_official	324:406fd2029f23	1769	#define BP_LPUART_CTRL_R8T9 (31U) /!< Bit position for LPUART_CTRL_R8T9. /
mbed_official	324:406fd2029f23	1770	#define BM_LPUART_CTRL_R8T9 (0x80000000U) /!< Bit mask for LPUART_CTRL_R8T9. /
mbed_official	324:406fd2029f23	1771	#define BS_LPUART_CTRL_R8T9 (1U) /!< Bit field size in bits for LPUART_CTRL_R8T9. /
mbed_official	324:406fd2029f23	1772
mbed_official	324:406fd2029f23	1773	/! @brief Read current value of the LPUART_CTRL_R8T9 field. /
mbed_official	324:406fd2029f23	1774	#define BR_LPUART_CTRL_R8T9(x) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R8T9))
mbed_official	324:406fd2029f23	1775
mbed_official	324:406fd2029f23	1776	/! @brief Format value for bitfield LPUART_CTRL_R8T9. /
mbed_official	324:406fd2029f23	1777	#define BF_LPUART_CTRL_R8T9(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_CTRL_R8T9) & BM_LPUART_CTRL_R8T9)
mbed_official	324:406fd2029f23	1778
mbed_official	324:406fd2029f23	1779	/! @brief Set the R8T9 field to a new value. /
mbed_official	324:406fd2029f23	1780	#define BW_LPUART_CTRL_R8T9(x, v) (BITBAND_ACCESS32(HW_LPUART_CTRL_ADDR(x), BP_LPUART_CTRL_R8T9) = (v))
mbed_official	324:406fd2029f23	1781	/@}/
mbed_official	324:406fd2029f23	1782
mbed_official	324:406fd2029f23	1783	/*******************************************************************************
mbed_official	324:406fd2029f23	1784	* HW_LPUART_DATA - LPUART Data Register
mbed_official	324:406fd2029f23	1785	******************************************************************************/
mbed_official	324:406fd2029f23	1786
mbed_official	324:406fd2029f23	1787	/*!
mbed_official	324:406fd2029f23	1788	* @brief HW_LPUART_DATA - LPUART Data Register (RW)
mbed_official	324:406fd2029f23	1789	*
mbed_official	324:406fd2029f23	1790	* Reset value: 0x00001000U
mbed_official	324:406fd2029f23	1791	*
mbed_official	324:406fd2029f23	1792	* This register is actually two separate registers. Reads return the contents
mbed_official	324:406fd2029f23	1793	* of the read-only receive data buffer and writes go to the write-only transmit
mbed_official	324:406fd2029f23	1794	* data buffer. Reads and writes of this register are also involved in the
mbed_official	324:406fd2029f23	1795	* automatic flag clearing mechanisms for some of the LPUART status flags.
mbed_official	324:406fd2029f23	1796	*/
mbed_official	324:406fd2029f23	1797	typedef union _hw_lpuart_data
mbed_official	324:406fd2029f23	1798	{
mbed_official	324:406fd2029f23	1799	uint32_t U;
mbed_official	324:406fd2029f23	1800	struct _hw_lpuart_data_bitfields
mbed_official	324:406fd2029f23	1801	{
mbed_official	324:406fd2029f23	1802	uint32_t R0T0 : 1; /!< [0] /
mbed_official	324:406fd2029f23	1803	uint32_t R1T1 : 1; /!< [1] /
mbed_official	324:406fd2029f23	1804	uint32_t R2T2 : 1; /!< [2] /
mbed_official	324:406fd2029f23	1805	uint32_t R3T3 : 1; /!< [3] /
mbed_official	324:406fd2029f23	1806	uint32_t R4T4 : 1; /!< [4] /
mbed_official	324:406fd2029f23	1807	uint32_t R5T5 : 1; /!< [5] /
mbed_official	324:406fd2029f23	1808	uint32_t R6T6 : 1; /!< [6] /
mbed_official	324:406fd2029f23	1809	uint32_t R7T7 : 1; /!< [7] /
mbed_official	324:406fd2029f23	1810	uint32_t R8T8 : 1; /!< [8] /
mbed_official	324:406fd2029f23	1811	uint32_t R9T9 : 1; /!< [9] /
mbed_official	324:406fd2029f23	1812	uint32_t RESERVED0 : 1; /!< [10] /
mbed_official	324:406fd2029f23	1813	uint32_t IDLINE : 1; /!< [11] Idle Line /
mbed_official	324:406fd2029f23	1814	uint32_t RXEMPT : 1; /!< [12] Receive Buffer Empty /
mbed_official	324:406fd2029f23	1815	uint32_t FRETSC : 1; /*!< [13] Frame Error / Transmit Special
mbed_official	324:406fd2029f23	1816	* Character */
mbed_official	324:406fd2029f23	1817	uint32_t PARITYE : 1; /!< [14] /
mbed_official	324:406fd2029f23	1818	uint32_t NOISY : 1; /!< [15] /
mbed_official	324:406fd2029f23	1819	uint32_t RESERVED1 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	1820	} B;
mbed_official	324:406fd2029f23	1821	} hw_lpuart_data_t;
mbed_official	324:406fd2029f23	1822
mbed_official	324:406fd2029f23	1823	/*!
mbed_official	324:406fd2029f23	1824	* @name Constants and macros for entire LPUART_DATA register
mbed_official	324:406fd2029f23	1825	*/
mbed_official	324:406fd2029f23	1826	/@{/
mbed_official	324:406fd2029f23	1827	#define HW_LPUART_DATA_ADDR(x) ((x) + 0xCU)
mbed_official	324:406fd2029f23	1828
mbed_official	324:406fd2029f23	1829	#define HW_LPUART_DATA(x) ((__IO hw_lpuart_data_t ) HW_LPUART_DATA_ADDR(x))
mbed_official	324:406fd2029f23	1830	#define HW_LPUART_DATA_RD(x) (HW_LPUART_DATA(x).U)
mbed_official	324:406fd2029f23	1831	#define HW_LPUART_DATA_WR(x, v) (HW_LPUART_DATA(x).U = (v))
mbed_official	324:406fd2029f23	1832	#define HW_LPUART_DATA_SET(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1833	#define HW_LPUART_DATA_CLR(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1834	#define HW_LPUART_DATA_TOG(x, v) (HW_LPUART_DATA_WR(x, HW_LPUART_DATA_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1835	/@}/
mbed_official	324:406fd2029f23	1836
mbed_official	324:406fd2029f23	1837	/*
mbed_official	324:406fd2029f23	1838	* Constants & macros for individual LPUART_DATA bitfields
mbed_official	324:406fd2029f23	1839	*/
mbed_official	324:406fd2029f23	1840
mbed_official	324:406fd2029f23	1841	/*!
mbed_official	324:406fd2029f23	1842	* @name Register LPUART_DATA, field R0T0[0] (RW)
mbed_official	324:406fd2029f23	1843	*
mbed_official	324:406fd2029f23	1844	* Read receive data buffer 0 or write transmit data buffer 0.
mbed_official	324:406fd2029f23	1845	*/
mbed_official	324:406fd2029f23	1846	/@{/
mbed_official	324:406fd2029f23	1847	#define BP_LPUART_DATA_R0T0 (0U) /!< Bit position for LPUART_DATA_R0T0. /
mbed_official	324:406fd2029f23	1848	#define BM_LPUART_DATA_R0T0 (0x00000001U) /!< Bit mask for LPUART_DATA_R0T0. /
mbed_official	324:406fd2029f23	1849	#define BS_LPUART_DATA_R0T0 (1U) /!< Bit field size in bits for LPUART_DATA_R0T0. /
mbed_official	324:406fd2029f23	1850
mbed_official	324:406fd2029f23	1851	/! @brief Read current value of the LPUART_DATA_R0T0 field. /
mbed_official	324:406fd2029f23	1852	#define BR_LPUART_DATA_R0T0(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R0T0))
mbed_official	324:406fd2029f23	1853
mbed_official	324:406fd2029f23	1854	/! @brief Format value for bitfield LPUART_DATA_R0T0. /
mbed_official	324:406fd2029f23	1855	#define BF_LPUART_DATA_R0T0(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R0T0) & BM_LPUART_DATA_R0T0)
mbed_official	324:406fd2029f23	1856
mbed_official	324:406fd2029f23	1857	/! @brief Set the R0T0 field to a new value. /
mbed_official	324:406fd2029f23	1858	#define BW_LPUART_DATA_R0T0(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R0T0) = (v))
mbed_official	324:406fd2029f23	1859	/@}/
mbed_official	324:406fd2029f23	1860
mbed_official	324:406fd2029f23	1861	/*!
mbed_official	324:406fd2029f23	1862	* @name Register LPUART_DATA, field R1T1[1] (RW)
mbed_official	324:406fd2029f23	1863	*
mbed_official	324:406fd2029f23	1864	* Read receive data buffer 1 or write transmit data buffer 1.
mbed_official	324:406fd2029f23	1865	*/
mbed_official	324:406fd2029f23	1866	/@{/
mbed_official	324:406fd2029f23	1867	#define BP_LPUART_DATA_R1T1 (1U) /!< Bit position for LPUART_DATA_R1T1. /
mbed_official	324:406fd2029f23	1868	#define BM_LPUART_DATA_R1T1 (0x00000002U) /!< Bit mask for LPUART_DATA_R1T1. /
mbed_official	324:406fd2029f23	1869	#define BS_LPUART_DATA_R1T1 (1U) /!< Bit field size in bits for LPUART_DATA_R1T1. /
mbed_official	324:406fd2029f23	1870
mbed_official	324:406fd2029f23	1871	/! @brief Read current value of the LPUART_DATA_R1T1 field. /
mbed_official	324:406fd2029f23	1872	#define BR_LPUART_DATA_R1T1(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R1T1))
mbed_official	324:406fd2029f23	1873
mbed_official	324:406fd2029f23	1874	/! @brief Format value for bitfield LPUART_DATA_R1T1. /
mbed_official	324:406fd2029f23	1875	#define BF_LPUART_DATA_R1T1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R1T1) & BM_LPUART_DATA_R1T1)
mbed_official	324:406fd2029f23	1876
mbed_official	324:406fd2029f23	1877	/! @brief Set the R1T1 field to a new value. /
mbed_official	324:406fd2029f23	1878	#define BW_LPUART_DATA_R1T1(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R1T1) = (v))
mbed_official	324:406fd2029f23	1879	/@}/
mbed_official	324:406fd2029f23	1880
mbed_official	324:406fd2029f23	1881	/*!
mbed_official	324:406fd2029f23	1882	* @name Register LPUART_DATA, field R2T2[2] (RW)
mbed_official	324:406fd2029f23	1883	*
mbed_official	324:406fd2029f23	1884	* Read receive data buffer 2 or write transmit data buffer 2.
mbed_official	324:406fd2029f23	1885	*/
mbed_official	324:406fd2029f23	1886	/@{/
mbed_official	324:406fd2029f23	1887	#define BP_LPUART_DATA_R2T2 (2U) /!< Bit position for LPUART_DATA_R2T2. /
mbed_official	324:406fd2029f23	1888	#define BM_LPUART_DATA_R2T2 (0x00000004U) /!< Bit mask for LPUART_DATA_R2T2. /
mbed_official	324:406fd2029f23	1889	#define BS_LPUART_DATA_R2T2 (1U) /!< Bit field size in bits for LPUART_DATA_R2T2. /
mbed_official	324:406fd2029f23	1890
mbed_official	324:406fd2029f23	1891	/! @brief Read current value of the LPUART_DATA_R2T2 field. /
mbed_official	324:406fd2029f23	1892	#define BR_LPUART_DATA_R2T2(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R2T2))
mbed_official	324:406fd2029f23	1893
mbed_official	324:406fd2029f23	1894	/! @brief Format value for bitfield LPUART_DATA_R2T2. /
mbed_official	324:406fd2029f23	1895	#define BF_LPUART_DATA_R2T2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R2T2) & BM_LPUART_DATA_R2T2)
mbed_official	324:406fd2029f23	1896
mbed_official	324:406fd2029f23	1897	/! @brief Set the R2T2 field to a new value. /
mbed_official	324:406fd2029f23	1898	#define BW_LPUART_DATA_R2T2(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R2T2) = (v))
mbed_official	324:406fd2029f23	1899	/@}/
mbed_official	324:406fd2029f23	1900
mbed_official	324:406fd2029f23	1901	/*!
mbed_official	324:406fd2029f23	1902	* @name Register LPUART_DATA, field R3T3[3] (RW)
mbed_official	324:406fd2029f23	1903	*
mbed_official	324:406fd2029f23	1904	* Read receive data buffer 3 or write transmit data buffer 3.
mbed_official	324:406fd2029f23	1905	*/
mbed_official	324:406fd2029f23	1906	/@{/
mbed_official	324:406fd2029f23	1907	#define BP_LPUART_DATA_R3T3 (3U) /!< Bit position for LPUART_DATA_R3T3. /
mbed_official	324:406fd2029f23	1908	#define BM_LPUART_DATA_R3T3 (0x00000008U) /!< Bit mask for LPUART_DATA_R3T3. /
mbed_official	324:406fd2029f23	1909	#define BS_LPUART_DATA_R3T3 (1U) /!< Bit field size in bits for LPUART_DATA_R3T3. /
mbed_official	324:406fd2029f23	1910
mbed_official	324:406fd2029f23	1911	/! @brief Read current value of the LPUART_DATA_R3T3 field. /
mbed_official	324:406fd2029f23	1912	#define BR_LPUART_DATA_R3T3(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R3T3))
mbed_official	324:406fd2029f23	1913
mbed_official	324:406fd2029f23	1914	/! @brief Format value for bitfield LPUART_DATA_R3T3. /
mbed_official	324:406fd2029f23	1915	#define BF_LPUART_DATA_R3T3(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R3T3) & BM_LPUART_DATA_R3T3)
mbed_official	324:406fd2029f23	1916
mbed_official	324:406fd2029f23	1917	/! @brief Set the R3T3 field to a new value. /
mbed_official	324:406fd2029f23	1918	#define BW_LPUART_DATA_R3T3(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R3T3) = (v))
mbed_official	324:406fd2029f23	1919	/@}/
mbed_official	324:406fd2029f23	1920
mbed_official	324:406fd2029f23	1921	/*!
mbed_official	324:406fd2029f23	1922	* @name Register LPUART_DATA, field R4T4[4] (RW)
mbed_official	324:406fd2029f23	1923	*
mbed_official	324:406fd2029f23	1924	* Read receive data buffer 4 or write transmit data buffer 4.
mbed_official	324:406fd2029f23	1925	*/
mbed_official	324:406fd2029f23	1926	/@{/
mbed_official	324:406fd2029f23	1927	#define BP_LPUART_DATA_R4T4 (4U) /!< Bit position for LPUART_DATA_R4T4. /
mbed_official	324:406fd2029f23	1928	#define BM_LPUART_DATA_R4T4 (0x00000010U) /!< Bit mask for LPUART_DATA_R4T4. /
mbed_official	324:406fd2029f23	1929	#define BS_LPUART_DATA_R4T4 (1U) /!< Bit field size in bits for LPUART_DATA_R4T4. /
mbed_official	324:406fd2029f23	1930
mbed_official	324:406fd2029f23	1931	/! @brief Read current value of the LPUART_DATA_R4T4 field. /
mbed_official	324:406fd2029f23	1932	#define BR_LPUART_DATA_R4T4(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R4T4))
mbed_official	324:406fd2029f23	1933
mbed_official	324:406fd2029f23	1934	/! @brief Format value for bitfield LPUART_DATA_R4T4. /
mbed_official	324:406fd2029f23	1935	#define BF_LPUART_DATA_R4T4(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R4T4) & BM_LPUART_DATA_R4T4)
mbed_official	324:406fd2029f23	1936
mbed_official	324:406fd2029f23	1937	/! @brief Set the R4T4 field to a new value. /
mbed_official	324:406fd2029f23	1938	#define BW_LPUART_DATA_R4T4(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R4T4) = (v))
mbed_official	324:406fd2029f23	1939	/@}/
mbed_official	324:406fd2029f23	1940
mbed_official	324:406fd2029f23	1941	/*!
mbed_official	324:406fd2029f23	1942	* @name Register LPUART_DATA, field R5T5[5] (RW)
mbed_official	324:406fd2029f23	1943	*
mbed_official	324:406fd2029f23	1944	* Read receive data buffer 5 or write transmit data buffer 5.
mbed_official	324:406fd2029f23	1945	*/
mbed_official	324:406fd2029f23	1946	/@{/
mbed_official	324:406fd2029f23	1947	#define BP_LPUART_DATA_R5T5 (5U) /!< Bit position for LPUART_DATA_R5T5. /
mbed_official	324:406fd2029f23	1948	#define BM_LPUART_DATA_R5T5 (0x00000020U) /!< Bit mask for LPUART_DATA_R5T5. /
mbed_official	324:406fd2029f23	1949	#define BS_LPUART_DATA_R5T5 (1U) /!< Bit field size in bits for LPUART_DATA_R5T5. /
mbed_official	324:406fd2029f23	1950
mbed_official	324:406fd2029f23	1951	/! @brief Read current value of the LPUART_DATA_R5T5 field. /
mbed_official	324:406fd2029f23	1952	#define BR_LPUART_DATA_R5T5(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R5T5))
mbed_official	324:406fd2029f23	1953
mbed_official	324:406fd2029f23	1954	/! @brief Format value for bitfield LPUART_DATA_R5T5. /
mbed_official	324:406fd2029f23	1955	#define BF_LPUART_DATA_R5T5(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R5T5) & BM_LPUART_DATA_R5T5)
mbed_official	324:406fd2029f23	1956
mbed_official	324:406fd2029f23	1957	/! @brief Set the R5T5 field to a new value. /
mbed_official	324:406fd2029f23	1958	#define BW_LPUART_DATA_R5T5(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R5T5) = (v))
mbed_official	324:406fd2029f23	1959	/@}/
mbed_official	324:406fd2029f23	1960
mbed_official	324:406fd2029f23	1961	/*!
mbed_official	324:406fd2029f23	1962	* @name Register LPUART_DATA, field R6T6[6] (RW)
mbed_official	324:406fd2029f23	1963	*
mbed_official	324:406fd2029f23	1964	* Read receive data buffer 6 or write transmit data buffer 6.
mbed_official	324:406fd2029f23	1965	*/
mbed_official	324:406fd2029f23	1966	/@{/
mbed_official	324:406fd2029f23	1967	#define BP_LPUART_DATA_R6T6 (6U) /!< Bit position for LPUART_DATA_R6T6. /
mbed_official	324:406fd2029f23	1968	#define BM_LPUART_DATA_R6T6 (0x00000040U) /!< Bit mask for LPUART_DATA_R6T6. /
mbed_official	324:406fd2029f23	1969	#define BS_LPUART_DATA_R6T6 (1U) /!< Bit field size in bits for LPUART_DATA_R6T6. /
mbed_official	324:406fd2029f23	1970
mbed_official	324:406fd2029f23	1971	/! @brief Read current value of the LPUART_DATA_R6T6 field. /
mbed_official	324:406fd2029f23	1972	#define BR_LPUART_DATA_R6T6(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R6T6))
mbed_official	324:406fd2029f23	1973
mbed_official	324:406fd2029f23	1974	/! @brief Format value for bitfield LPUART_DATA_R6T6. /
mbed_official	324:406fd2029f23	1975	#define BF_LPUART_DATA_R6T6(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R6T6) & BM_LPUART_DATA_R6T6)
mbed_official	324:406fd2029f23	1976
mbed_official	324:406fd2029f23	1977	/! @brief Set the R6T6 field to a new value. /
mbed_official	324:406fd2029f23	1978	#define BW_LPUART_DATA_R6T6(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R6T6) = (v))
mbed_official	324:406fd2029f23	1979	/@}/
mbed_official	324:406fd2029f23	1980
mbed_official	324:406fd2029f23	1981	/*!
mbed_official	324:406fd2029f23	1982	* @name Register LPUART_DATA, field R7T7[7] (RW)
mbed_official	324:406fd2029f23	1983	*
mbed_official	324:406fd2029f23	1984	* Read receive data buffer 7 or write transmit data buffer 7.
mbed_official	324:406fd2029f23	1985	*/
mbed_official	324:406fd2029f23	1986	/@{/
mbed_official	324:406fd2029f23	1987	#define BP_LPUART_DATA_R7T7 (7U) /!< Bit position for LPUART_DATA_R7T7. /
mbed_official	324:406fd2029f23	1988	#define BM_LPUART_DATA_R7T7 (0x00000080U) /!< Bit mask for LPUART_DATA_R7T7. /
mbed_official	324:406fd2029f23	1989	#define BS_LPUART_DATA_R7T7 (1U) /!< Bit field size in bits for LPUART_DATA_R7T7. /
mbed_official	324:406fd2029f23	1990
mbed_official	324:406fd2029f23	1991	/! @brief Read current value of the LPUART_DATA_R7T7 field. /
mbed_official	324:406fd2029f23	1992	#define BR_LPUART_DATA_R7T7(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R7T7))
mbed_official	324:406fd2029f23	1993
mbed_official	324:406fd2029f23	1994	/! @brief Format value for bitfield LPUART_DATA_R7T7. /
mbed_official	324:406fd2029f23	1995	#define BF_LPUART_DATA_R7T7(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R7T7) & BM_LPUART_DATA_R7T7)
mbed_official	324:406fd2029f23	1996
mbed_official	324:406fd2029f23	1997	/! @brief Set the R7T7 field to a new value. /
mbed_official	324:406fd2029f23	1998	#define BW_LPUART_DATA_R7T7(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R7T7) = (v))
mbed_official	324:406fd2029f23	1999	/@}/
mbed_official	324:406fd2029f23	2000
mbed_official	324:406fd2029f23	2001	/*!
mbed_official	324:406fd2029f23	2002	* @name Register LPUART_DATA, field R8T8[8] (RW)
mbed_official	324:406fd2029f23	2003	*
mbed_official	324:406fd2029f23	2004	* Read receive data buffer 8 or write transmit data buffer 8.
mbed_official	324:406fd2029f23	2005	*/
mbed_official	324:406fd2029f23	2006	/@{/
mbed_official	324:406fd2029f23	2007	#define BP_LPUART_DATA_R8T8 (8U) /!< Bit position for LPUART_DATA_R8T8. /
mbed_official	324:406fd2029f23	2008	#define BM_LPUART_DATA_R8T8 (0x00000100U) /!< Bit mask for LPUART_DATA_R8T8. /
mbed_official	324:406fd2029f23	2009	#define BS_LPUART_DATA_R8T8 (1U) /!< Bit field size in bits for LPUART_DATA_R8T8. /
mbed_official	324:406fd2029f23	2010
mbed_official	324:406fd2029f23	2011	/! @brief Read current value of the LPUART_DATA_R8T8 field. /
mbed_official	324:406fd2029f23	2012	#define BR_LPUART_DATA_R8T8(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R8T8))
mbed_official	324:406fd2029f23	2013
mbed_official	324:406fd2029f23	2014	/! @brief Format value for bitfield LPUART_DATA_R8T8. /
mbed_official	324:406fd2029f23	2015	#define BF_LPUART_DATA_R8T8(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R8T8) & BM_LPUART_DATA_R8T8)
mbed_official	324:406fd2029f23	2016
mbed_official	324:406fd2029f23	2017	/! @brief Set the R8T8 field to a new value. /
mbed_official	324:406fd2029f23	2018	#define BW_LPUART_DATA_R8T8(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R8T8) = (v))
mbed_official	324:406fd2029f23	2019	/@}/
mbed_official	324:406fd2029f23	2020
mbed_official	324:406fd2029f23	2021	/*!
mbed_official	324:406fd2029f23	2022	* @name Register LPUART_DATA, field R9T9[9] (RW)
mbed_official	324:406fd2029f23	2023	*
mbed_official	324:406fd2029f23	2024	* Read receive data buffer 9 or write transmit data buffer 9.
mbed_official	324:406fd2029f23	2025	*/
mbed_official	324:406fd2029f23	2026	/@{/
mbed_official	324:406fd2029f23	2027	#define BP_LPUART_DATA_R9T9 (9U) /!< Bit position for LPUART_DATA_R9T9. /
mbed_official	324:406fd2029f23	2028	#define BM_LPUART_DATA_R9T9 (0x00000200U) /!< Bit mask for LPUART_DATA_R9T9. /
mbed_official	324:406fd2029f23	2029	#define BS_LPUART_DATA_R9T9 (1U) /!< Bit field size in bits for LPUART_DATA_R9T9. /
mbed_official	324:406fd2029f23	2030
mbed_official	324:406fd2029f23	2031	/! @brief Read current value of the LPUART_DATA_R9T9 field. /
mbed_official	324:406fd2029f23	2032	#define BR_LPUART_DATA_R9T9(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R9T9))
mbed_official	324:406fd2029f23	2033
mbed_official	324:406fd2029f23	2034	/! @brief Format value for bitfield LPUART_DATA_R9T9. /
mbed_official	324:406fd2029f23	2035	#define BF_LPUART_DATA_R9T9(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_R9T9) & BM_LPUART_DATA_R9T9)
mbed_official	324:406fd2029f23	2036
mbed_official	324:406fd2029f23	2037	/! @brief Set the R9T9 field to a new value. /
mbed_official	324:406fd2029f23	2038	#define BW_LPUART_DATA_R9T9(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_R9T9) = (v))
mbed_official	324:406fd2029f23	2039	/@}/
mbed_official	324:406fd2029f23	2040
mbed_official	324:406fd2029f23	2041	/*!
mbed_official	324:406fd2029f23	2042	* @name Register LPUART_DATA, field IDLINE[11] (RO)
mbed_official	324:406fd2029f23	2043	*
mbed_official	324:406fd2029f23	2044	* Indicates the receiver line was idle before receiving the character in
mbed_official	324:406fd2029f23	2045	* DATA[9:0]. Unlike the IDLE flag, this bit can set for the first character received
mbed_official	324:406fd2029f23	2046	* when the receiver is first enabled.
mbed_official	324:406fd2029f23	2047	*
mbed_official	324:406fd2029f23	2048	* Values:
mbed_official	324:406fd2029f23	2049	* - 0 - Receiver was not idle before receiving this character.
mbed_official	324:406fd2029f23	2050	* - 1 - Receiver was idle before receiving this character.
mbed_official	324:406fd2029f23	2051	*/
mbed_official	324:406fd2029f23	2052	/@{/
mbed_official	324:406fd2029f23	2053	#define BP_LPUART_DATA_IDLINE (11U) /!< Bit position for LPUART_DATA_IDLINE. /
mbed_official	324:406fd2029f23	2054	#define BM_LPUART_DATA_IDLINE (0x00000800U) /!< Bit mask for LPUART_DATA_IDLINE. /
mbed_official	324:406fd2029f23	2055	#define BS_LPUART_DATA_IDLINE (1U) /!< Bit field size in bits for LPUART_DATA_IDLINE. /
mbed_official	324:406fd2029f23	2056
mbed_official	324:406fd2029f23	2057	/! @brief Read current value of the LPUART_DATA_IDLINE field. /
mbed_official	324:406fd2029f23	2058	#define BR_LPUART_DATA_IDLINE(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_IDLINE))
mbed_official	324:406fd2029f23	2059	/@}/
mbed_official	324:406fd2029f23	2060
mbed_official	324:406fd2029f23	2061	/*!
mbed_official	324:406fd2029f23	2062	* @name Register LPUART_DATA, field RXEMPT[12] (RO)
mbed_official	324:406fd2029f23	2063	*
mbed_official	324:406fd2029f23	2064	* Asserts when there is no data in the receive buffer. This field does not take
mbed_official	324:406fd2029f23	2065	* into account data that is in the receive shift register.
mbed_official	324:406fd2029f23	2066	*
mbed_official	324:406fd2029f23	2067	* Values:
mbed_official	324:406fd2029f23	2068	* - 0 - Receive buffer contains valid data.
mbed_official	324:406fd2029f23	2069	* - 1 - Receive buffer is empty, data returned on read is not valid.
mbed_official	324:406fd2029f23	2070	*/
mbed_official	324:406fd2029f23	2071	/@{/
mbed_official	324:406fd2029f23	2072	#define BP_LPUART_DATA_RXEMPT (12U) /!< Bit position for LPUART_DATA_RXEMPT. /
mbed_official	324:406fd2029f23	2073	#define BM_LPUART_DATA_RXEMPT (0x00001000U) /!< Bit mask for LPUART_DATA_RXEMPT. /
mbed_official	324:406fd2029f23	2074	#define BS_LPUART_DATA_RXEMPT (1U) /!< Bit field size in bits for LPUART_DATA_RXEMPT. /
mbed_official	324:406fd2029f23	2075
mbed_official	324:406fd2029f23	2076	/! @brief Read current value of the LPUART_DATA_RXEMPT field. /
mbed_official	324:406fd2029f23	2077	#define BR_LPUART_DATA_RXEMPT(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_RXEMPT))
mbed_official	324:406fd2029f23	2078	/@}/
mbed_official	324:406fd2029f23	2079
mbed_official	324:406fd2029f23	2080	/*!
mbed_official	324:406fd2029f23	2081	* @name Register LPUART_DATA, field FRETSC[13] (RW)
mbed_official	324:406fd2029f23	2082	*
mbed_official	324:406fd2029f23	2083	* For reads, indicates the current received dataword contained in DATA[R9:R0]
mbed_official	324:406fd2029f23	2084	* was received with a frame error. For writes, indicates a break or idle
mbed_official	324:406fd2029f23	2085	* character is to be transmitted instead of the contents in DATA[T9:T0]. T9 is used to
mbed_official	324:406fd2029f23	2086	* indicate a break character when 0 and a idle character when 1, he contents of
mbed_official	324:406fd2029f23	2087	* DATA[T8:T0] should be zero.
mbed_official	324:406fd2029f23	2088	*
mbed_official	324:406fd2029f23	2089	* Values:
mbed_official	324:406fd2029f23	2090	* - 0 - The dataword was received without a frame error on read, transmit a
mbed_official	324:406fd2029f23	2091	* normal character on write.
mbed_official	324:406fd2029f23	2092	* - 1 - The dataword was received with a frame error, transmit an idle or break
mbed_official	324:406fd2029f23	2093	* character on transmit.
mbed_official	324:406fd2029f23	2094	*/
mbed_official	324:406fd2029f23	2095	/@{/
mbed_official	324:406fd2029f23	2096	#define BP_LPUART_DATA_FRETSC (13U) /!< Bit position for LPUART_DATA_FRETSC. /
mbed_official	324:406fd2029f23	2097	#define BM_LPUART_DATA_FRETSC (0x00002000U) /!< Bit mask for LPUART_DATA_FRETSC. /
mbed_official	324:406fd2029f23	2098	#define BS_LPUART_DATA_FRETSC (1U) /!< Bit field size in bits for LPUART_DATA_FRETSC. /
mbed_official	324:406fd2029f23	2099
mbed_official	324:406fd2029f23	2100	/! @brief Read current value of the LPUART_DATA_FRETSC field. /
mbed_official	324:406fd2029f23	2101	#define BR_LPUART_DATA_FRETSC(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_FRETSC))
mbed_official	324:406fd2029f23	2102
mbed_official	324:406fd2029f23	2103	/! @brief Format value for bitfield LPUART_DATA_FRETSC. /
mbed_official	324:406fd2029f23	2104	#define BF_LPUART_DATA_FRETSC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_DATA_FRETSC) & BM_LPUART_DATA_FRETSC)
mbed_official	324:406fd2029f23	2105
mbed_official	324:406fd2029f23	2106	/! @brief Set the FRETSC field to a new value. /
mbed_official	324:406fd2029f23	2107	#define BW_LPUART_DATA_FRETSC(x, v) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_FRETSC) = (v))
mbed_official	324:406fd2029f23	2108	/@}/
mbed_official	324:406fd2029f23	2109
mbed_official	324:406fd2029f23	2110	/*!
mbed_official	324:406fd2029f23	2111	* @name Register LPUART_DATA, field PARITYE[14] (RO)
mbed_official	324:406fd2029f23	2112	*
mbed_official	324:406fd2029f23	2113	* The current received dataword contained in DATA[R9:R0] was received with a
mbed_official	324:406fd2029f23	2114	* parity error.
mbed_official	324:406fd2029f23	2115	*
mbed_official	324:406fd2029f23	2116	* Values:
mbed_official	324:406fd2029f23	2117	* - 0 - The dataword was received without a parity error.
mbed_official	324:406fd2029f23	2118	* - 1 - The dataword was received with a parity error.
mbed_official	324:406fd2029f23	2119	*/
mbed_official	324:406fd2029f23	2120	/@{/
mbed_official	324:406fd2029f23	2121	#define BP_LPUART_DATA_PARITYE (14U) /!< Bit position for LPUART_DATA_PARITYE. /
mbed_official	324:406fd2029f23	2122	#define BM_LPUART_DATA_PARITYE (0x00004000U) /!< Bit mask for LPUART_DATA_PARITYE. /
mbed_official	324:406fd2029f23	2123	#define BS_LPUART_DATA_PARITYE (1U) /!< Bit field size in bits for LPUART_DATA_PARITYE. /
mbed_official	324:406fd2029f23	2124
mbed_official	324:406fd2029f23	2125	/! @brief Read current value of the LPUART_DATA_PARITYE field. /
mbed_official	324:406fd2029f23	2126	#define BR_LPUART_DATA_PARITYE(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_PARITYE))
mbed_official	324:406fd2029f23	2127	/@}/
mbed_official	324:406fd2029f23	2128
mbed_official	324:406fd2029f23	2129	/*!
mbed_official	324:406fd2029f23	2130	* @name Register LPUART_DATA, field NOISY[15] (RO)
mbed_official	324:406fd2029f23	2131	*
mbed_official	324:406fd2029f23	2132	* The current received dataword contained in DATA[R9:R0] was received with
mbed_official	324:406fd2029f23	2133	* noise.
mbed_official	324:406fd2029f23	2134	*
mbed_official	324:406fd2029f23	2135	* Values:
mbed_official	324:406fd2029f23	2136	* - 0 - The dataword was received without noise.
mbed_official	324:406fd2029f23	2137	* - 1 - The data was received with noise.
mbed_official	324:406fd2029f23	2138	*/
mbed_official	324:406fd2029f23	2139	/@{/
mbed_official	324:406fd2029f23	2140	#define BP_LPUART_DATA_NOISY (15U) /!< Bit position for LPUART_DATA_NOISY. /
mbed_official	324:406fd2029f23	2141	#define BM_LPUART_DATA_NOISY (0x00008000U) /!< Bit mask for LPUART_DATA_NOISY. /
mbed_official	324:406fd2029f23	2142	#define BS_LPUART_DATA_NOISY (1U) /!< Bit field size in bits for LPUART_DATA_NOISY. /
mbed_official	324:406fd2029f23	2143
mbed_official	324:406fd2029f23	2144	/! @brief Read current value of the LPUART_DATA_NOISY field. /
mbed_official	324:406fd2029f23	2145	#define BR_LPUART_DATA_NOISY(x) (BITBAND_ACCESS32(HW_LPUART_DATA_ADDR(x), BP_LPUART_DATA_NOISY))
mbed_official	324:406fd2029f23	2146	/@}/
mbed_official	324:406fd2029f23	2147
mbed_official	324:406fd2029f23	2148	/*******************************************************************************
mbed_official	324:406fd2029f23	2149	* HW_LPUART_MATCH - LPUART Match Address Register
mbed_official	324:406fd2029f23	2150	******************************************************************************/
mbed_official	324:406fd2029f23	2151
mbed_official	324:406fd2029f23	2152	/*!
mbed_official	324:406fd2029f23	2153	* @brief HW_LPUART_MATCH - LPUART Match Address Register (RW)
mbed_official	324:406fd2029f23	2154	*
mbed_official	324:406fd2029f23	2155	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2156	*/
mbed_official	324:406fd2029f23	2157	typedef union _hw_lpuart_match
mbed_official	324:406fd2029f23	2158	{
mbed_official	324:406fd2029f23	2159	uint32_t U;
mbed_official	324:406fd2029f23	2160	struct _hw_lpuart_match_bitfields
mbed_official	324:406fd2029f23	2161	{
mbed_official	324:406fd2029f23	2162	uint32_t MA1 : 10; /!< [9:0] Match Address 1 /
mbed_official	324:406fd2029f23	2163	uint32_t RESERVED0 : 6; /!< [15:10] /
mbed_official	324:406fd2029f23	2164	uint32_t MA2 : 10; /!< [25:16] Match Address 2 /
mbed_official	324:406fd2029f23	2165	uint32_t RESERVED1 : 6; /!< [31:26] /
mbed_official	324:406fd2029f23	2166	} B;
mbed_official	324:406fd2029f23	2167	} hw_lpuart_match_t;
mbed_official	324:406fd2029f23	2168
mbed_official	324:406fd2029f23	2169	/*!
mbed_official	324:406fd2029f23	2170	* @name Constants and macros for entire LPUART_MATCH register
mbed_official	324:406fd2029f23	2171	*/
mbed_official	324:406fd2029f23	2172	/@{/
mbed_official	324:406fd2029f23	2173	#define HW_LPUART_MATCH_ADDR(x) ((x) + 0x10U)
mbed_official	324:406fd2029f23	2174
mbed_official	324:406fd2029f23	2175	#define HW_LPUART_MATCH(x) ((__IO hw_lpuart_match_t ) HW_LPUART_MATCH_ADDR(x))
mbed_official	324:406fd2029f23	2176	#define HW_LPUART_MATCH_RD(x) (HW_LPUART_MATCH(x).U)
mbed_official	324:406fd2029f23	2177	#define HW_LPUART_MATCH_WR(x, v) (HW_LPUART_MATCH(x).U = (v))
mbed_official	324:406fd2029f23	2178	#define HW_LPUART_MATCH_SET(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2179	#define HW_LPUART_MATCH_CLR(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2180	#define HW_LPUART_MATCH_TOG(x, v) (HW_LPUART_MATCH_WR(x, HW_LPUART_MATCH_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2181	/@}/
mbed_official	324:406fd2029f23	2182
mbed_official	324:406fd2029f23	2183	/*
mbed_official	324:406fd2029f23	2184	* Constants & macros for individual LPUART_MATCH bitfields
mbed_official	324:406fd2029f23	2185	*/
mbed_official	324:406fd2029f23	2186
mbed_official	324:406fd2029f23	2187	/*!
mbed_official	324:406fd2029f23	2188	* @name Register LPUART_MATCH, field MA1[9:0] (RW)
mbed_official	324:406fd2029f23	2189	*
mbed_official	324:406fd2029f23	2190	* The MA1 and MA2 registers are compared to input data addresses when the most
mbed_official	324:406fd2029f23	2191	* significant bit is set and the associated BAUD[MAEN] bit is set. If a match
mbed_official	324:406fd2029f23	2192	* occurs, the following data is transferred to the data register. If a match
mbed_official	324:406fd2029f23	2193	* fails, the following data is discarded. Software should only write a MA register
mbed_official	324:406fd2029f23	2194	* when the associated BAUD[MAEN] bit is clear.
mbed_official	324:406fd2029f23	2195	*/
mbed_official	324:406fd2029f23	2196	/@{/
mbed_official	324:406fd2029f23	2197	#define BP_LPUART_MATCH_MA1 (0U) /!< Bit position for LPUART_MATCH_MA1. /
mbed_official	324:406fd2029f23	2198	#define BM_LPUART_MATCH_MA1 (0x000003FFU) /!< Bit mask for LPUART_MATCH_MA1. /
mbed_official	324:406fd2029f23	2199	#define BS_LPUART_MATCH_MA1 (10U) /!< Bit field size in bits for LPUART_MATCH_MA1. /
mbed_official	324:406fd2029f23	2200
mbed_official	324:406fd2029f23	2201	/! @brief Read current value of the LPUART_MATCH_MA1 field. /
mbed_official	324:406fd2029f23	2202	#define BR_LPUART_MATCH_MA1(x) (HW_LPUART_MATCH(x).B.MA1)
mbed_official	324:406fd2029f23	2203
mbed_official	324:406fd2029f23	2204	/! @brief Format value for bitfield LPUART_MATCH_MA1. /
mbed_official	324:406fd2029f23	2205	#define BF_LPUART_MATCH_MA1(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MATCH_MA1) & BM_LPUART_MATCH_MA1)
mbed_official	324:406fd2029f23	2206
mbed_official	324:406fd2029f23	2207	/! @brief Set the MA1 field to a new value. /
mbed_official	324:406fd2029f23	2208	#define BW_LPUART_MATCH_MA1(x, v) (HW_LPUART_MATCH_WR(x, (HW_LPUART_MATCH_RD(x) & ~BM_LPUART_MATCH_MA1) \| BF_LPUART_MATCH_MA1(v)))
mbed_official	324:406fd2029f23	2209	/@}/
mbed_official	324:406fd2029f23	2210
mbed_official	324:406fd2029f23	2211	/*!
mbed_official	324:406fd2029f23	2212	* @name Register LPUART_MATCH, field MA2[25:16] (RW)
mbed_official	324:406fd2029f23	2213	*
mbed_official	324:406fd2029f23	2214	* The MA1 and MA2 registers are compared to input data addresses when the most
mbed_official	324:406fd2029f23	2215	* significant bit is set and the associated BAUD[MAEN] bit is set. If a match
mbed_official	324:406fd2029f23	2216	* occurs, the following data is transferred to the data register. If a match
mbed_official	324:406fd2029f23	2217	* fails, the following data is discarded. Software should only write a MA register
mbed_official	324:406fd2029f23	2218	* when the associated BAUD[MAEN] bit is clear.
mbed_official	324:406fd2029f23	2219	*/
mbed_official	324:406fd2029f23	2220	/@{/
mbed_official	324:406fd2029f23	2221	#define BP_LPUART_MATCH_MA2 (16U) /!< Bit position for LPUART_MATCH_MA2. /
mbed_official	324:406fd2029f23	2222	#define BM_LPUART_MATCH_MA2 (0x03FF0000U) /!< Bit mask for LPUART_MATCH_MA2. /
mbed_official	324:406fd2029f23	2223	#define BS_LPUART_MATCH_MA2 (10U) /!< Bit field size in bits for LPUART_MATCH_MA2. /
mbed_official	324:406fd2029f23	2224
mbed_official	324:406fd2029f23	2225	/! @brief Read current value of the LPUART_MATCH_MA2 field. /
mbed_official	324:406fd2029f23	2226	#define BR_LPUART_MATCH_MA2(x) (HW_LPUART_MATCH(x).B.MA2)
mbed_official	324:406fd2029f23	2227
mbed_official	324:406fd2029f23	2228	/! @brief Format value for bitfield LPUART_MATCH_MA2. /
mbed_official	324:406fd2029f23	2229	#define BF_LPUART_MATCH_MA2(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MATCH_MA2) & BM_LPUART_MATCH_MA2)
mbed_official	324:406fd2029f23	2230
mbed_official	324:406fd2029f23	2231	/! @brief Set the MA2 field to a new value. /
mbed_official	324:406fd2029f23	2232	#define BW_LPUART_MATCH_MA2(x, v) (HW_LPUART_MATCH_WR(x, (HW_LPUART_MATCH_RD(x) & ~BM_LPUART_MATCH_MA2) \| BF_LPUART_MATCH_MA2(v)))
mbed_official	324:406fd2029f23	2233	/@}/
mbed_official	324:406fd2029f23	2234
mbed_official	324:406fd2029f23	2235	/*******************************************************************************
mbed_official	324:406fd2029f23	2236	* HW_LPUART_MODIR - LPUART Modem IrDA Register
mbed_official	324:406fd2029f23	2237	******************************************************************************/
mbed_official	324:406fd2029f23	2238
mbed_official	324:406fd2029f23	2239	/*!
mbed_official	324:406fd2029f23	2240	* @brief HW_LPUART_MODIR - LPUART Modem IrDA Register (RW)
mbed_official	324:406fd2029f23	2241	*
mbed_official	324:406fd2029f23	2242	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2243	*
mbed_official	324:406fd2029f23	2244	* The MODEM register controls options for setting the modem configuration.
mbed_official	324:406fd2029f23	2245	*/
mbed_official	324:406fd2029f23	2246	typedef union _hw_lpuart_modir
mbed_official	324:406fd2029f23	2247	{
mbed_official	324:406fd2029f23	2248	uint32_t U;
mbed_official	324:406fd2029f23	2249	struct _hw_lpuart_modir_bitfields
mbed_official	324:406fd2029f23	2250	{
mbed_official	324:406fd2029f23	2251	uint32_t TXCTSE : 1; /!< [0] Transmitter clear-to-send enable /
mbed_official	324:406fd2029f23	2252	uint32_t TXRTSE : 1; /!< [1] Transmitter request-to-send enable /
mbed_official	324:406fd2029f23	2253	uint32_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity
mbed_official	324:406fd2029f23	2254	* */
mbed_official	324:406fd2029f23	2255	uint32_t RXRTSE : 1; /!< [3] Receiver request-to-send enable /
mbed_official	324:406fd2029f23	2256	uint32_t TXCTSC : 1; /!< [4] Transmit CTS Configuration /
mbed_official	324:406fd2029f23	2257	uint32_t TXCTSSRC : 1; /!< [5] Transmit CTS Source /
mbed_official	324:406fd2029f23	2258	uint32_t RESERVED0 : 10; /!< [15:6] /
mbed_official	324:406fd2029f23	2259	uint32_t TNP : 2; /!< [17:16] Transmitter narrow pulse /
mbed_official	324:406fd2029f23	2260	uint32_t IREN : 1; /!< [18] Infrared enable /
mbed_official	324:406fd2029f23	2261	uint32_t RESERVED1 : 13; /!< [31:19] /
mbed_official	324:406fd2029f23	2262	} B;
mbed_official	324:406fd2029f23	2263	} hw_lpuart_modir_t;
mbed_official	324:406fd2029f23	2264
mbed_official	324:406fd2029f23	2265	/*!
mbed_official	324:406fd2029f23	2266	* @name Constants and macros for entire LPUART_MODIR register
mbed_official	324:406fd2029f23	2267	*/
mbed_official	324:406fd2029f23	2268	/@{/
mbed_official	324:406fd2029f23	2269	#define HW_LPUART_MODIR_ADDR(x) ((x) + 0x14U)
mbed_official	324:406fd2029f23	2270
mbed_official	324:406fd2029f23	2271	#define HW_LPUART_MODIR(x) ((__IO hw_lpuart_modir_t ) HW_LPUART_MODIR_ADDR(x))
mbed_official	324:406fd2029f23	2272	#define HW_LPUART_MODIR_RD(x) (HW_LPUART_MODIR(x).U)
mbed_official	324:406fd2029f23	2273	#define HW_LPUART_MODIR_WR(x, v) (HW_LPUART_MODIR(x).U = (v))
mbed_official	324:406fd2029f23	2274	#define HW_LPUART_MODIR_SET(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2275	#define HW_LPUART_MODIR_CLR(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2276	#define HW_LPUART_MODIR_TOG(x, v) (HW_LPUART_MODIR_WR(x, HW_LPUART_MODIR_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2277	/@}/
mbed_official	324:406fd2029f23	2278
mbed_official	324:406fd2029f23	2279	/*
mbed_official	324:406fd2029f23	2280	* Constants & macros for individual LPUART_MODIR bitfields
mbed_official	324:406fd2029f23	2281	*/
mbed_official	324:406fd2029f23	2282
mbed_official	324:406fd2029f23	2283	/*!
mbed_official	324:406fd2029f23	2284	* @name Register LPUART_MODIR, field TXCTSE[0] (RW)
mbed_official	324:406fd2029f23	2285	*
mbed_official	324:406fd2029f23	2286	* TXCTSE controls the operation of the transmitter. TXCTSE can be set
mbed_official	324:406fd2029f23	2287	* independently from the state of TXRTSE and RXRTSE.
mbed_official	324:406fd2029f23	2288	*
mbed_official	324:406fd2029f23	2289	* Values:
mbed_official	324:406fd2029f23	2290	* - 0 - CTS has no effect on the transmitter.
mbed_official	324:406fd2029f23	2291	* - 1 - Enables clear-to-send operation. The transmitter checks the state of
mbed_official	324:406fd2029f23	2292	* CTS each time it is ready to send a character. If CTS is asserted, the
mbed_official	324:406fd2029f23	2293	* character is sent. If CTS is deasserted, the signal TXD remains in the mark
mbed_official	324:406fd2029f23	2294	* state and transmission is delayed until CTS is asserted. Changes in CTS as a
mbed_official	324:406fd2029f23	2295	* character is being sent do not affect its transmission.
mbed_official	324:406fd2029f23	2296	*/
mbed_official	324:406fd2029f23	2297	/@{/
mbed_official	324:406fd2029f23	2298	#define BP_LPUART_MODIR_TXCTSE (0U) /!< Bit position for LPUART_MODIR_TXCTSE. /
mbed_official	324:406fd2029f23	2299	#define BM_LPUART_MODIR_TXCTSE (0x00000001U) /!< Bit mask for LPUART_MODIR_TXCTSE. /
mbed_official	324:406fd2029f23	2300	#define BS_LPUART_MODIR_TXCTSE (1U) /!< Bit field size in bits for LPUART_MODIR_TXCTSE. /
mbed_official	324:406fd2029f23	2301
mbed_official	324:406fd2029f23	2302	/! @brief Read current value of the LPUART_MODIR_TXCTSE field. /
mbed_official	324:406fd2029f23	2303	#define BR_LPUART_MODIR_TXCTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSE))
mbed_official	324:406fd2029f23	2304
mbed_official	324:406fd2029f23	2305	/! @brief Format value for bitfield LPUART_MODIR_TXCTSE. /
mbed_official	324:406fd2029f23	2306	#define BF_LPUART_MODIR_TXCTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSE) & BM_LPUART_MODIR_TXCTSE)
mbed_official	324:406fd2029f23	2307
mbed_official	324:406fd2029f23	2308	/! @brief Set the TXCTSE field to a new value. /
mbed_official	324:406fd2029f23	2309	#define BW_LPUART_MODIR_TXCTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSE) = (v))
mbed_official	324:406fd2029f23	2310	/@}/
mbed_official	324:406fd2029f23	2311
mbed_official	324:406fd2029f23	2312	/*!
mbed_official	324:406fd2029f23	2313	* @name Register LPUART_MODIR, field TXRTSE[1] (RW)
mbed_official	324:406fd2029f23	2314	*
mbed_official	324:406fd2029f23	2315	* Controls RTS before and after a transmission.
mbed_official	324:406fd2029f23	2316	*
mbed_official	324:406fd2029f23	2317	* Values:
mbed_official	324:406fd2029f23	2318	* - 0 - The transmitter has no effect on RTS.
mbed_official	324:406fd2029f23	2319	* - 1 - When a character is placed into an empty transmitter data buffer , RTS
mbed_official	324:406fd2029f23	2320	* asserts one bit time before the start bit is transmitted. RTS deasserts
mbed_official	324:406fd2029f23	2321	* one bit time after all characters in the transmitter data buffer and shift
mbed_official	324:406fd2029f23	2322	* register are completely sent, including the last stop bit.
mbed_official	324:406fd2029f23	2323	*/
mbed_official	324:406fd2029f23	2324	/@{/
mbed_official	324:406fd2029f23	2325	#define BP_LPUART_MODIR_TXRTSE (1U) /!< Bit position for LPUART_MODIR_TXRTSE. /
mbed_official	324:406fd2029f23	2326	#define BM_LPUART_MODIR_TXRTSE (0x00000002U) /!< Bit mask for LPUART_MODIR_TXRTSE. /
mbed_official	324:406fd2029f23	2327	#define BS_LPUART_MODIR_TXRTSE (1U) /!< Bit field size in bits for LPUART_MODIR_TXRTSE. /
mbed_official	324:406fd2029f23	2328
mbed_official	324:406fd2029f23	2329	/! @brief Read current value of the LPUART_MODIR_TXRTSE field. /
mbed_official	324:406fd2029f23	2330	#define BR_LPUART_MODIR_TXRTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSE))
mbed_official	324:406fd2029f23	2331
mbed_official	324:406fd2029f23	2332	/! @brief Format value for bitfield LPUART_MODIR_TXRTSE. /
mbed_official	324:406fd2029f23	2333	#define BF_LPUART_MODIR_TXRTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXRTSE) & BM_LPUART_MODIR_TXRTSE)
mbed_official	324:406fd2029f23	2334
mbed_official	324:406fd2029f23	2335	/! @brief Set the TXRTSE field to a new value. /
mbed_official	324:406fd2029f23	2336	#define BW_LPUART_MODIR_TXRTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSE) = (v))
mbed_official	324:406fd2029f23	2337	/@}/
mbed_official	324:406fd2029f23	2338
mbed_official	324:406fd2029f23	2339	/*!
mbed_official	324:406fd2029f23	2340	* @name Register LPUART_MODIR, field TXRTSPOL[2] (RW)
mbed_official	324:406fd2029f23	2341	*
mbed_official	324:406fd2029f23	2342	* Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
mbed_official	324:406fd2029f23	2343	* polarity of the receiver RTS. RTS will remain negated in the active low state
mbed_official	324:406fd2029f23	2344	* unless TXRTSE is set.
mbed_official	324:406fd2029f23	2345	*
mbed_official	324:406fd2029f23	2346	* Values:
mbed_official	324:406fd2029f23	2347	* - 0 - Transmitter RTS is active low.
mbed_official	324:406fd2029f23	2348	* - 1 - Transmitter RTS is active high.
mbed_official	324:406fd2029f23	2349	*/
mbed_official	324:406fd2029f23	2350	/@{/
mbed_official	324:406fd2029f23	2351	#define BP_LPUART_MODIR_TXRTSPOL (2U) /!< Bit position for LPUART_MODIR_TXRTSPOL. /
mbed_official	324:406fd2029f23	2352	#define BM_LPUART_MODIR_TXRTSPOL (0x00000004U) /!< Bit mask for LPUART_MODIR_TXRTSPOL. /
mbed_official	324:406fd2029f23	2353	#define BS_LPUART_MODIR_TXRTSPOL (1U) /!< Bit field size in bits for LPUART_MODIR_TXRTSPOL. /
mbed_official	324:406fd2029f23	2354
mbed_official	324:406fd2029f23	2355	/! @brief Read current value of the LPUART_MODIR_TXRTSPOL field. /
mbed_official	324:406fd2029f23	2356	#define BR_LPUART_MODIR_TXRTSPOL(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSPOL))
mbed_official	324:406fd2029f23	2357
mbed_official	324:406fd2029f23	2358	/! @brief Format value for bitfield LPUART_MODIR_TXRTSPOL. /
mbed_official	324:406fd2029f23	2359	#define BF_LPUART_MODIR_TXRTSPOL(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXRTSPOL) & BM_LPUART_MODIR_TXRTSPOL)
mbed_official	324:406fd2029f23	2360
mbed_official	324:406fd2029f23	2361	/! @brief Set the TXRTSPOL field to a new value. /
mbed_official	324:406fd2029f23	2362	#define BW_LPUART_MODIR_TXRTSPOL(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXRTSPOL) = (v))
mbed_official	324:406fd2029f23	2363	/@}/
mbed_official	324:406fd2029f23	2364
mbed_official	324:406fd2029f23	2365	/*!
mbed_official	324:406fd2029f23	2366	* @name Register LPUART_MODIR, field RXRTSE[3] (RW)
mbed_official	324:406fd2029f23	2367	*
mbed_official	324:406fd2029f23	2368	* Allows the RTS output to control the CTS input of the transmitting device to
mbed_official	324:406fd2029f23	2369	* prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
mbed_official	324:406fd2029f23	2370	*
mbed_official	324:406fd2029f23	2371	* Values:
mbed_official	324:406fd2029f23	2372	* - 0 - The receiver has no effect on RTS.
mbed_official	324:406fd2029f23	2373	* - 1 - RTS is deasserted if the receiver data register is full or a start bit
mbed_official	324:406fd2029f23	2374	* has been detected that would cause the receiver data register to become
mbed_official	324:406fd2029f23	2375	* full. RTS is asserted if the receiver data register is not full and has not
mbed_official	324:406fd2029f23	2376	* detected a start bit that would cause the receiver data register to become
mbed_official	324:406fd2029f23	2377	* full.
mbed_official	324:406fd2029f23	2378	*/
mbed_official	324:406fd2029f23	2379	/@{/
mbed_official	324:406fd2029f23	2380	#define BP_LPUART_MODIR_RXRTSE (3U) /!< Bit position for LPUART_MODIR_RXRTSE. /
mbed_official	324:406fd2029f23	2381	#define BM_LPUART_MODIR_RXRTSE (0x00000008U) /!< Bit mask for LPUART_MODIR_RXRTSE. /
mbed_official	324:406fd2029f23	2382	#define BS_LPUART_MODIR_RXRTSE (1U) /!< Bit field size in bits for LPUART_MODIR_RXRTSE. /
mbed_official	324:406fd2029f23	2383
mbed_official	324:406fd2029f23	2384	/! @brief Read current value of the LPUART_MODIR_RXRTSE field. /
mbed_official	324:406fd2029f23	2385	#define BR_LPUART_MODIR_RXRTSE(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_RXRTSE))
mbed_official	324:406fd2029f23	2386
mbed_official	324:406fd2029f23	2387	/! @brief Format value for bitfield LPUART_MODIR_RXRTSE. /
mbed_official	324:406fd2029f23	2388	#define BF_LPUART_MODIR_RXRTSE(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_RXRTSE) & BM_LPUART_MODIR_RXRTSE)
mbed_official	324:406fd2029f23	2389
mbed_official	324:406fd2029f23	2390	/! @brief Set the RXRTSE field to a new value. /
mbed_official	324:406fd2029f23	2391	#define BW_LPUART_MODIR_RXRTSE(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_RXRTSE) = (v))
mbed_official	324:406fd2029f23	2392	/@}/
mbed_official	324:406fd2029f23	2393
mbed_official	324:406fd2029f23	2394	/*!
mbed_official	324:406fd2029f23	2395	* @name Register LPUART_MODIR, field TXCTSC[4] (RW)
mbed_official	324:406fd2029f23	2396	*
mbed_official	324:406fd2029f23	2397	* Configures if the CTS state is checked at the start of each character or only
mbed_official	324:406fd2029f23	2398	* when the transmitter is idle.
mbed_official	324:406fd2029f23	2399	*
mbed_official	324:406fd2029f23	2400	* Values:
mbed_official	324:406fd2029f23	2401	* - 0 - CTS input is sampled at the start of each character.
mbed_official	324:406fd2029f23	2402	* - 1 - CTS input is sampled when the transmitter is idle.
mbed_official	324:406fd2029f23	2403	*/
mbed_official	324:406fd2029f23	2404	/@{/
mbed_official	324:406fd2029f23	2405	#define BP_LPUART_MODIR_TXCTSC (4U) /!< Bit position for LPUART_MODIR_TXCTSC. /
mbed_official	324:406fd2029f23	2406	#define BM_LPUART_MODIR_TXCTSC (0x00000010U) /!< Bit mask for LPUART_MODIR_TXCTSC. /
mbed_official	324:406fd2029f23	2407	#define BS_LPUART_MODIR_TXCTSC (1U) /!< Bit field size in bits for LPUART_MODIR_TXCTSC. /
mbed_official	324:406fd2029f23	2408
mbed_official	324:406fd2029f23	2409	/! @brief Read current value of the LPUART_MODIR_TXCTSC field. /
mbed_official	324:406fd2029f23	2410	#define BR_LPUART_MODIR_TXCTSC(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSC))
mbed_official	324:406fd2029f23	2411
mbed_official	324:406fd2029f23	2412	/! @brief Format value for bitfield LPUART_MODIR_TXCTSC. /
mbed_official	324:406fd2029f23	2413	#define BF_LPUART_MODIR_TXCTSC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSC) & BM_LPUART_MODIR_TXCTSC)
mbed_official	324:406fd2029f23	2414
mbed_official	324:406fd2029f23	2415	/! @brief Set the TXCTSC field to a new value. /
mbed_official	324:406fd2029f23	2416	#define BW_LPUART_MODIR_TXCTSC(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSC) = (v))
mbed_official	324:406fd2029f23	2417	/@}/
mbed_official	324:406fd2029f23	2418
mbed_official	324:406fd2029f23	2419	/*!
mbed_official	324:406fd2029f23	2420	* @name Register LPUART_MODIR, field TXCTSSRC[5] (RW)
mbed_official	324:406fd2029f23	2421	*
mbed_official	324:406fd2029f23	2422	* Configures the source of the CTS input.
mbed_official	324:406fd2029f23	2423	*
mbed_official	324:406fd2029f23	2424	* Values:
mbed_official	324:406fd2029f23	2425	* - 0 - CTS input is the LPUART_CTS pin.
mbed_official	324:406fd2029f23	2426	* - 1 - CTS input is the inverted Receiver Match result.
mbed_official	324:406fd2029f23	2427	*/
mbed_official	324:406fd2029f23	2428	/@{/
mbed_official	324:406fd2029f23	2429	#define BP_LPUART_MODIR_TXCTSSRC (5U) /!< Bit position for LPUART_MODIR_TXCTSSRC. /
mbed_official	324:406fd2029f23	2430	#define BM_LPUART_MODIR_TXCTSSRC (0x00000020U) /!< Bit mask for LPUART_MODIR_TXCTSSRC. /
mbed_official	324:406fd2029f23	2431	#define BS_LPUART_MODIR_TXCTSSRC (1U) /!< Bit field size in bits for LPUART_MODIR_TXCTSSRC. /
mbed_official	324:406fd2029f23	2432
mbed_official	324:406fd2029f23	2433	/! @brief Read current value of the LPUART_MODIR_TXCTSSRC field. /
mbed_official	324:406fd2029f23	2434	#define BR_LPUART_MODIR_TXCTSSRC(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSSRC))
mbed_official	324:406fd2029f23	2435
mbed_official	324:406fd2029f23	2436	/! @brief Format value for bitfield LPUART_MODIR_TXCTSSRC. /
mbed_official	324:406fd2029f23	2437	#define BF_LPUART_MODIR_TXCTSSRC(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TXCTSSRC) & BM_LPUART_MODIR_TXCTSSRC)
mbed_official	324:406fd2029f23	2438
mbed_official	324:406fd2029f23	2439	/! @brief Set the TXCTSSRC field to a new value. /
mbed_official	324:406fd2029f23	2440	#define BW_LPUART_MODIR_TXCTSSRC(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_TXCTSSRC) = (v))
mbed_official	324:406fd2029f23	2441	/@}/
mbed_official	324:406fd2029f23	2442
mbed_official	324:406fd2029f23	2443	/*!
mbed_official	324:406fd2029f23	2444	* @name Register LPUART_MODIR, field TNP[17:16] (RW)
mbed_official	324:406fd2029f23	2445	*
mbed_official	324:406fd2029f23	2446	* Enables whether the LPUART transmits a 1/OSR, 2/OSR, 3/OSR or 4/OSR narrow
mbed_official	324:406fd2029f23	2447	* pulse.
mbed_official	324:406fd2029f23	2448	*
mbed_official	324:406fd2029f23	2449	* Values:
mbed_official	324:406fd2029f23	2450	* - 00 - 1/OSR.
mbed_official	324:406fd2029f23	2451	* - 01 - 2/OSR.
mbed_official	324:406fd2029f23	2452	* - 10 - 3/OSR.
mbed_official	324:406fd2029f23	2453	* - 11 - 4/OSR.
mbed_official	324:406fd2029f23	2454	*/
mbed_official	324:406fd2029f23	2455	/@{/
mbed_official	324:406fd2029f23	2456	#define BP_LPUART_MODIR_TNP (16U) /!< Bit position for LPUART_MODIR_TNP. /
mbed_official	324:406fd2029f23	2457	#define BM_LPUART_MODIR_TNP (0x00030000U) /!< Bit mask for LPUART_MODIR_TNP. /
mbed_official	324:406fd2029f23	2458	#define BS_LPUART_MODIR_TNP (2U) /!< Bit field size in bits for LPUART_MODIR_TNP. /
mbed_official	324:406fd2029f23	2459
mbed_official	324:406fd2029f23	2460	/! @brief Read current value of the LPUART_MODIR_TNP field. /
mbed_official	324:406fd2029f23	2461	#define BR_LPUART_MODIR_TNP(x) (HW_LPUART_MODIR(x).B.TNP)
mbed_official	324:406fd2029f23	2462
mbed_official	324:406fd2029f23	2463	/! @brief Format value for bitfield LPUART_MODIR_TNP. /
mbed_official	324:406fd2029f23	2464	#define BF_LPUART_MODIR_TNP(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_TNP) & BM_LPUART_MODIR_TNP)
mbed_official	324:406fd2029f23	2465
mbed_official	324:406fd2029f23	2466	/! @brief Set the TNP field to a new value. /
mbed_official	324:406fd2029f23	2467	#define BW_LPUART_MODIR_TNP(x, v) (HW_LPUART_MODIR_WR(x, (HW_LPUART_MODIR_RD(x) & ~BM_LPUART_MODIR_TNP) \| BF_LPUART_MODIR_TNP(v)))
mbed_official	324:406fd2029f23	2468	/@}/
mbed_official	324:406fd2029f23	2469
mbed_official	324:406fd2029f23	2470	/*!
mbed_official	324:406fd2029f23	2471	* @name Register LPUART_MODIR, field IREN[18] (RW)
mbed_official	324:406fd2029f23	2472	*
mbed_official	324:406fd2029f23	2473	* Enables/disables the infrared modulation/demodulation.
mbed_official	324:406fd2029f23	2474	*
mbed_official	324:406fd2029f23	2475	* Values:
mbed_official	324:406fd2029f23	2476	* - 0 - IR disabled.
mbed_official	324:406fd2029f23	2477	* - 1 - IR enabled.
mbed_official	324:406fd2029f23	2478	*/
mbed_official	324:406fd2029f23	2479	/@{/
mbed_official	324:406fd2029f23	2480	#define BP_LPUART_MODIR_IREN (18U) /!< Bit position for LPUART_MODIR_IREN. /
mbed_official	324:406fd2029f23	2481	#define BM_LPUART_MODIR_IREN (0x00040000U) /!< Bit mask for LPUART_MODIR_IREN. /
mbed_official	324:406fd2029f23	2482	#define BS_LPUART_MODIR_IREN (1U) /!< Bit field size in bits for LPUART_MODIR_IREN. /
mbed_official	324:406fd2029f23	2483
mbed_official	324:406fd2029f23	2484	/! @brief Read current value of the LPUART_MODIR_IREN field. /
mbed_official	324:406fd2029f23	2485	#define BR_LPUART_MODIR_IREN(x) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_IREN))
mbed_official	324:406fd2029f23	2486
mbed_official	324:406fd2029f23	2487	/! @brief Format value for bitfield LPUART_MODIR_IREN. /
mbed_official	324:406fd2029f23	2488	#define BF_LPUART_MODIR_IREN(v) ((uint32_t)((uint32_t)(v) << BP_LPUART_MODIR_IREN) & BM_LPUART_MODIR_IREN)
mbed_official	324:406fd2029f23	2489
mbed_official	324:406fd2029f23	2490	/! @brief Set the IREN field to a new value. /
mbed_official	324:406fd2029f23	2491	#define BW_LPUART_MODIR_IREN(x, v) (BITBAND_ACCESS32(HW_LPUART_MODIR_ADDR(x), BP_LPUART_MODIR_IREN) = (v))
mbed_official	324:406fd2029f23	2492	/@}/
mbed_official	324:406fd2029f23	2493
mbed_official	324:406fd2029f23	2494	/*******************************************************************************
mbed_official	324:406fd2029f23	2495	* hw_lpuart_t - module struct
mbed_official	324:406fd2029f23	2496	******************************************************************************/
mbed_official	324:406fd2029f23	2497	/*!
mbed_official	324:406fd2029f23	2498	* @brief All LPUART module registers.
mbed_official	324:406fd2029f23	2499	*/
mbed_official	324:406fd2029f23	2500	#pragma pack(1)
mbed_official	324:406fd2029f23	2501	typedef struct _hw_lpuart
mbed_official	324:406fd2029f23	2502	{
mbed_official	324:406fd2029f23	2503	__IO hw_lpuart_baud_t BAUD; /!< [0x0] LPUART Baud Rate Register /
mbed_official	324:406fd2029f23	2504	__IO hw_lpuart_stat_t STAT; /!< [0x4] LPUART Status Register /
mbed_official	324:406fd2029f23	2505	__IO hw_lpuart_ctrl_t CTRL; /!< [0x8] LPUART Control Register /
mbed_official	324:406fd2029f23	2506	__IO hw_lpuart_data_t DATA; /!< [0xC] LPUART Data Register /
mbed_official	324:406fd2029f23	2507	__IO hw_lpuart_match_t MATCH; /!< [0x10] LPUART Match Address Register /
mbed_official	324:406fd2029f23	2508	__IO hw_lpuart_modir_t MODIR; /!< [0x14] LPUART Modem IrDA Register /
mbed_official	324:406fd2029f23	2509	} hw_lpuart_t;
mbed_official	324:406fd2029f23	2510	#pragma pack()
mbed_official	324:406fd2029f23	2511
mbed_official	324:406fd2029f23	2512	/! @brief Macro to access all LPUART registers. /
mbed_official	324:406fd2029f23	2513	/! @param x LPUART module instance base address. /
mbed_official	324:406fd2029f23	2514	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	2515	* use the '&' operator, like <code>&HW_LPUART(LPUART0_BASE)</code>. */
mbed_official	324:406fd2029f23	2516	#define HW_LPUART(x) ((hw_lpuart_t )(x))
mbed_official	324:406fd2029f23	2517
mbed_official	324:406fd2029f23	2518	#endif /* __HW_LPUART_REGISTERS_H__ */
mbed_official	324:406fd2029f23	2519	/* EOF */