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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_llwu.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_LLWU_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_LLWU_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 LLWU
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Low leakage wakeup unit
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_LLWU_PE1 - LLWU Pin Enable 1 register
mbed_official 324:406fd2029f23 90 * - HW_LLWU_PE2 - LLWU Pin Enable 2 register
mbed_official 324:406fd2029f23 91 * - HW_LLWU_PE3 - LLWU Pin Enable 3 register
mbed_official 324:406fd2029f23 92 * - HW_LLWU_PE4 - LLWU Pin Enable 4 register
mbed_official 324:406fd2029f23 93 * - HW_LLWU_ME - LLWU Module Enable register
mbed_official 324:406fd2029f23 94 * - HW_LLWU_F1 - LLWU Flag 1 register
mbed_official 324:406fd2029f23 95 * - HW_LLWU_F2 - LLWU Flag 2 register
mbed_official 324:406fd2029f23 96 * - HW_LLWU_F3 - LLWU Flag 3 register
mbed_official 324:406fd2029f23 97 * - HW_LLWU_FILT1 - LLWU Pin Filter 1 register
mbed_official 324:406fd2029f23 98 * - HW_LLWU_FILT2 - LLWU Pin Filter 2 register
mbed_official 324:406fd2029f23 99 *
mbed_official 324:406fd2029f23 100 * - hw_llwu_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 101 */
mbed_official 324:406fd2029f23 102
mbed_official 324:406fd2029f23 103 #define HW_LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
mbed_official 324:406fd2029f23 104
mbed_official 324:406fd2029f23 105 /*******************************************************************************
mbed_official 324:406fd2029f23 106 * HW_LLWU_PE1 - LLWU Pin Enable 1 register
mbed_official 324:406fd2029f23 107 ******************************************************************************/
mbed_official 324:406fd2029f23 108
mbed_official 324:406fd2029f23 109 /*!
mbed_official 324:406fd2029f23 110 * @brief HW_LLWU_PE1 - LLWU Pin Enable 1 register (RW)
mbed_official 324:406fd2029f23 111 *
mbed_official 324:406fd2029f23 112 * Reset value: 0x00U
mbed_official 324:406fd2029f23 113 *
mbed_official 324:406fd2029f23 114 * LLWU_PE1 contains the field to enable and select the edge detect type for the
mbed_official 324:406fd2029f23 115 * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
mbed_official 324:406fd2029f23 116 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 117 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 118 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 324:406fd2029f23 119 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 120 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 121 */
mbed_official 324:406fd2029f23 122 typedef union _hw_llwu_pe1
mbed_official 324:406fd2029f23 123 {
mbed_official 324:406fd2029f23 124 uint8_t U;
mbed_official 324:406fd2029f23 125 struct _hw_llwu_pe1_bitfields
mbed_official 324:406fd2029f23 126 {
mbed_official 324:406fd2029f23 127 uint8_t WUPE0 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P0 */
mbed_official 324:406fd2029f23 128 uint8_t WUPE1 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P1 */
mbed_official 324:406fd2029f23 129 uint8_t WUPE2 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P2 */
mbed_official 324:406fd2029f23 130 uint8_t WUPE3 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P3 */
mbed_official 324:406fd2029f23 131 } B;
mbed_official 324:406fd2029f23 132 } hw_llwu_pe1_t;
mbed_official 324:406fd2029f23 133
mbed_official 324:406fd2029f23 134 /*!
mbed_official 324:406fd2029f23 135 * @name Constants and macros for entire LLWU_PE1 register
mbed_official 324:406fd2029f23 136 */
mbed_official 324:406fd2029f23 137 /*@{*/
mbed_official 324:406fd2029f23 138 #define HW_LLWU_PE1_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 139
mbed_official 324:406fd2029f23 140 #define HW_LLWU_PE1(x) (*(__IO hw_llwu_pe1_t *) HW_LLWU_PE1_ADDR(x))
mbed_official 324:406fd2029f23 141 #define HW_LLWU_PE1_RD(x) (HW_LLWU_PE1(x).U)
mbed_official 324:406fd2029f23 142 #define HW_LLWU_PE1_WR(x, v) (HW_LLWU_PE1(x).U = (v))
mbed_official 324:406fd2029f23 143 #define HW_LLWU_PE1_SET(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) | (v)))
mbed_official 324:406fd2029f23 144 #define HW_LLWU_PE1_CLR(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 145 #define HW_LLWU_PE1_TOG(x, v) (HW_LLWU_PE1_WR(x, HW_LLWU_PE1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 146 /*@}*/
mbed_official 324:406fd2029f23 147
mbed_official 324:406fd2029f23 148 /*
mbed_official 324:406fd2029f23 149 * Constants & macros for individual LLWU_PE1 bitfields
mbed_official 324:406fd2029f23 150 */
mbed_official 324:406fd2029f23 151
mbed_official 324:406fd2029f23 152 /*!
mbed_official 324:406fd2029f23 153 * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
mbed_official 324:406fd2029f23 154 *
mbed_official 324:406fd2029f23 155 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 156 *
mbed_official 324:406fd2029f23 157 * Values:
mbed_official 324:406fd2029f23 158 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 159 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 160 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 161 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 162 */
mbed_official 324:406fd2029f23 163 /*@{*/
mbed_official 324:406fd2029f23 164 #define BP_LLWU_PE1_WUPE0 (0U) /*!< Bit position for LLWU_PE1_WUPE0. */
mbed_official 324:406fd2029f23 165 #define BM_LLWU_PE1_WUPE0 (0x03U) /*!< Bit mask for LLWU_PE1_WUPE0. */
mbed_official 324:406fd2029f23 166 #define BS_LLWU_PE1_WUPE0 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE0. */
mbed_official 324:406fd2029f23 167
mbed_official 324:406fd2029f23 168 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
mbed_official 324:406fd2029f23 169 #define BR_LLWU_PE1_WUPE0(x) (HW_LLWU_PE1(x).B.WUPE0)
mbed_official 324:406fd2029f23 170
mbed_official 324:406fd2029f23 171 /*! @brief Format value for bitfield LLWU_PE1_WUPE0. */
mbed_official 324:406fd2029f23 172 #define BF_LLWU_PE1_WUPE0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE0) & BM_LLWU_PE1_WUPE0)
mbed_official 324:406fd2029f23 173
mbed_official 324:406fd2029f23 174 /*! @brief Set the WUPE0 field to a new value. */
mbed_official 324:406fd2029f23 175 #define BW_LLWU_PE1_WUPE0(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE0) | BF_LLWU_PE1_WUPE0(v)))
mbed_official 324:406fd2029f23 176 /*@}*/
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*!
mbed_official 324:406fd2029f23 179 * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
mbed_official 324:406fd2029f23 180 *
mbed_official 324:406fd2029f23 181 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 182 *
mbed_official 324:406fd2029f23 183 * Values:
mbed_official 324:406fd2029f23 184 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 185 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 186 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 187 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 188 */
mbed_official 324:406fd2029f23 189 /*@{*/
mbed_official 324:406fd2029f23 190 #define BP_LLWU_PE1_WUPE1 (2U) /*!< Bit position for LLWU_PE1_WUPE1. */
mbed_official 324:406fd2029f23 191 #define BM_LLWU_PE1_WUPE1 (0x0CU) /*!< Bit mask for LLWU_PE1_WUPE1. */
mbed_official 324:406fd2029f23 192 #define BS_LLWU_PE1_WUPE1 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE1. */
mbed_official 324:406fd2029f23 193
mbed_official 324:406fd2029f23 194 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
mbed_official 324:406fd2029f23 195 #define BR_LLWU_PE1_WUPE1(x) (HW_LLWU_PE1(x).B.WUPE1)
mbed_official 324:406fd2029f23 196
mbed_official 324:406fd2029f23 197 /*! @brief Format value for bitfield LLWU_PE1_WUPE1. */
mbed_official 324:406fd2029f23 198 #define BF_LLWU_PE1_WUPE1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE1) & BM_LLWU_PE1_WUPE1)
mbed_official 324:406fd2029f23 199
mbed_official 324:406fd2029f23 200 /*! @brief Set the WUPE1 field to a new value. */
mbed_official 324:406fd2029f23 201 #define BW_LLWU_PE1_WUPE1(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE1) | BF_LLWU_PE1_WUPE1(v)))
mbed_official 324:406fd2029f23 202 /*@}*/
mbed_official 324:406fd2029f23 203
mbed_official 324:406fd2029f23 204 /*!
mbed_official 324:406fd2029f23 205 * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
mbed_official 324:406fd2029f23 206 *
mbed_official 324:406fd2029f23 207 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 208 *
mbed_official 324:406fd2029f23 209 * Values:
mbed_official 324:406fd2029f23 210 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 211 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 212 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 213 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 214 */
mbed_official 324:406fd2029f23 215 /*@{*/
mbed_official 324:406fd2029f23 216 #define BP_LLWU_PE1_WUPE2 (4U) /*!< Bit position for LLWU_PE1_WUPE2. */
mbed_official 324:406fd2029f23 217 #define BM_LLWU_PE1_WUPE2 (0x30U) /*!< Bit mask for LLWU_PE1_WUPE2. */
mbed_official 324:406fd2029f23 218 #define BS_LLWU_PE1_WUPE2 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE2. */
mbed_official 324:406fd2029f23 219
mbed_official 324:406fd2029f23 220 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
mbed_official 324:406fd2029f23 221 #define BR_LLWU_PE1_WUPE2(x) (HW_LLWU_PE1(x).B.WUPE2)
mbed_official 324:406fd2029f23 222
mbed_official 324:406fd2029f23 223 /*! @brief Format value for bitfield LLWU_PE1_WUPE2. */
mbed_official 324:406fd2029f23 224 #define BF_LLWU_PE1_WUPE2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE2) & BM_LLWU_PE1_WUPE2)
mbed_official 324:406fd2029f23 225
mbed_official 324:406fd2029f23 226 /*! @brief Set the WUPE2 field to a new value. */
mbed_official 324:406fd2029f23 227 #define BW_LLWU_PE1_WUPE2(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE2) | BF_LLWU_PE1_WUPE2(v)))
mbed_official 324:406fd2029f23 228 /*@}*/
mbed_official 324:406fd2029f23 229
mbed_official 324:406fd2029f23 230 /*!
mbed_official 324:406fd2029f23 231 * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
mbed_official 324:406fd2029f23 232 *
mbed_official 324:406fd2029f23 233 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 234 *
mbed_official 324:406fd2029f23 235 * Values:
mbed_official 324:406fd2029f23 236 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 237 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 238 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 239 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 240 */
mbed_official 324:406fd2029f23 241 /*@{*/
mbed_official 324:406fd2029f23 242 #define BP_LLWU_PE1_WUPE3 (6U) /*!< Bit position for LLWU_PE1_WUPE3. */
mbed_official 324:406fd2029f23 243 #define BM_LLWU_PE1_WUPE3 (0xC0U) /*!< Bit mask for LLWU_PE1_WUPE3. */
mbed_official 324:406fd2029f23 244 #define BS_LLWU_PE1_WUPE3 (2U) /*!< Bit field size in bits for LLWU_PE1_WUPE3. */
mbed_official 324:406fd2029f23 245
mbed_official 324:406fd2029f23 246 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
mbed_official 324:406fd2029f23 247 #define BR_LLWU_PE1_WUPE3(x) (HW_LLWU_PE1(x).B.WUPE3)
mbed_official 324:406fd2029f23 248
mbed_official 324:406fd2029f23 249 /*! @brief Format value for bitfield LLWU_PE1_WUPE3. */
mbed_official 324:406fd2029f23 250 #define BF_LLWU_PE1_WUPE3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE1_WUPE3) & BM_LLWU_PE1_WUPE3)
mbed_official 324:406fd2029f23 251
mbed_official 324:406fd2029f23 252 /*! @brief Set the WUPE3 field to a new value. */
mbed_official 324:406fd2029f23 253 #define BW_LLWU_PE1_WUPE3(x, v) (HW_LLWU_PE1_WR(x, (HW_LLWU_PE1_RD(x) & ~BM_LLWU_PE1_WUPE3) | BF_LLWU_PE1_WUPE3(v)))
mbed_official 324:406fd2029f23 254 /*@}*/
mbed_official 324:406fd2029f23 255
mbed_official 324:406fd2029f23 256 /*******************************************************************************
mbed_official 324:406fd2029f23 257 * HW_LLWU_PE2 - LLWU Pin Enable 2 register
mbed_official 324:406fd2029f23 258 ******************************************************************************/
mbed_official 324:406fd2029f23 259
mbed_official 324:406fd2029f23 260 /*!
mbed_official 324:406fd2029f23 261 * @brief HW_LLWU_PE2 - LLWU Pin Enable 2 register (RW)
mbed_official 324:406fd2029f23 262 *
mbed_official 324:406fd2029f23 263 * Reset value: 0x00U
mbed_official 324:406fd2029f23 264 *
mbed_official 324:406fd2029f23 265 * LLWU_PE2 contains the field to enable and select the edge detect type for the
mbed_official 324:406fd2029f23 266 * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
mbed_official 324:406fd2029f23 267 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 268 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 269 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 324:406fd2029f23 270 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 271 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 272 */
mbed_official 324:406fd2029f23 273 typedef union _hw_llwu_pe2
mbed_official 324:406fd2029f23 274 {
mbed_official 324:406fd2029f23 275 uint8_t U;
mbed_official 324:406fd2029f23 276 struct _hw_llwu_pe2_bitfields
mbed_official 324:406fd2029f23 277 {
mbed_official 324:406fd2029f23 278 uint8_t WUPE4 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P4 */
mbed_official 324:406fd2029f23 279 uint8_t WUPE5 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P5 */
mbed_official 324:406fd2029f23 280 uint8_t WUPE6 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P6 */
mbed_official 324:406fd2029f23 281 uint8_t WUPE7 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P7 */
mbed_official 324:406fd2029f23 282 } B;
mbed_official 324:406fd2029f23 283 } hw_llwu_pe2_t;
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*!
mbed_official 324:406fd2029f23 286 * @name Constants and macros for entire LLWU_PE2 register
mbed_official 324:406fd2029f23 287 */
mbed_official 324:406fd2029f23 288 /*@{*/
mbed_official 324:406fd2029f23 289 #define HW_LLWU_PE2_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 290
mbed_official 324:406fd2029f23 291 #define HW_LLWU_PE2(x) (*(__IO hw_llwu_pe2_t *) HW_LLWU_PE2_ADDR(x))
mbed_official 324:406fd2029f23 292 #define HW_LLWU_PE2_RD(x) (HW_LLWU_PE2(x).U)
mbed_official 324:406fd2029f23 293 #define HW_LLWU_PE2_WR(x, v) (HW_LLWU_PE2(x).U = (v))
mbed_official 324:406fd2029f23 294 #define HW_LLWU_PE2_SET(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) | (v)))
mbed_official 324:406fd2029f23 295 #define HW_LLWU_PE2_CLR(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 296 #define HW_LLWU_PE2_TOG(x, v) (HW_LLWU_PE2_WR(x, HW_LLWU_PE2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 297 /*@}*/
mbed_official 324:406fd2029f23 298
mbed_official 324:406fd2029f23 299 /*
mbed_official 324:406fd2029f23 300 * Constants & macros for individual LLWU_PE2 bitfields
mbed_official 324:406fd2029f23 301 */
mbed_official 324:406fd2029f23 302
mbed_official 324:406fd2029f23 303 /*!
mbed_official 324:406fd2029f23 304 * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
mbed_official 324:406fd2029f23 305 *
mbed_official 324:406fd2029f23 306 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 307 *
mbed_official 324:406fd2029f23 308 * Values:
mbed_official 324:406fd2029f23 309 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 310 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 311 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 312 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 313 */
mbed_official 324:406fd2029f23 314 /*@{*/
mbed_official 324:406fd2029f23 315 #define BP_LLWU_PE2_WUPE4 (0U) /*!< Bit position for LLWU_PE2_WUPE4. */
mbed_official 324:406fd2029f23 316 #define BM_LLWU_PE2_WUPE4 (0x03U) /*!< Bit mask for LLWU_PE2_WUPE4. */
mbed_official 324:406fd2029f23 317 #define BS_LLWU_PE2_WUPE4 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE4. */
mbed_official 324:406fd2029f23 318
mbed_official 324:406fd2029f23 319 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
mbed_official 324:406fd2029f23 320 #define BR_LLWU_PE2_WUPE4(x) (HW_LLWU_PE2(x).B.WUPE4)
mbed_official 324:406fd2029f23 321
mbed_official 324:406fd2029f23 322 /*! @brief Format value for bitfield LLWU_PE2_WUPE4. */
mbed_official 324:406fd2029f23 323 #define BF_LLWU_PE2_WUPE4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE4) & BM_LLWU_PE2_WUPE4)
mbed_official 324:406fd2029f23 324
mbed_official 324:406fd2029f23 325 /*! @brief Set the WUPE4 field to a new value. */
mbed_official 324:406fd2029f23 326 #define BW_LLWU_PE2_WUPE4(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE4) | BF_LLWU_PE2_WUPE4(v)))
mbed_official 324:406fd2029f23 327 /*@}*/
mbed_official 324:406fd2029f23 328
mbed_official 324:406fd2029f23 329 /*!
mbed_official 324:406fd2029f23 330 * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
mbed_official 324:406fd2029f23 331 *
mbed_official 324:406fd2029f23 332 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 333 *
mbed_official 324:406fd2029f23 334 * Values:
mbed_official 324:406fd2029f23 335 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 336 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 337 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 338 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 339 */
mbed_official 324:406fd2029f23 340 /*@{*/
mbed_official 324:406fd2029f23 341 #define BP_LLWU_PE2_WUPE5 (2U) /*!< Bit position for LLWU_PE2_WUPE5. */
mbed_official 324:406fd2029f23 342 #define BM_LLWU_PE2_WUPE5 (0x0CU) /*!< Bit mask for LLWU_PE2_WUPE5. */
mbed_official 324:406fd2029f23 343 #define BS_LLWU_PE2_WUPE5 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE5. */
mbed_official 324:406fd2029f23 344
mbed_official 324:406fd2029f23 345 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
mbed_official 324:406fd2029f23 346 #define BR_LLWU_PE2_WUPE5(x) (HW_LLWU_PE2(x).B.WUPE5)
mbed_official 324:406fd2029f23 347
mbed_official 324:406fd2029f23 348 /*! @brief Format value for bitfield LLWU_PE2_WUPE5. */
mbed_official 324:406fd2029f23 349 #define BF_LLWU_PE2_WUPE5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE5) & BM_LLWU_PE2_WUPE5)
mbed_official 324:406fd2029f23 350
mbed_official 324:406fd2029f23 351 /*! @brief Set the WUPE5 field to a new value. */
mbed_official 324:406fd2029f23 352 #define BW_LLWU_PE2_WUPE5(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE5) | BF_LLWU_PE2_WUPE5(v)))
mbed_official 324:406fd2029f23 353 /*@}*/
mbed_official 324:406fd2029f23 354
mbed_official 324:406fd2029f23 355 /*!
mbed_official 324:406fd2029f23 356 * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
mbed_official 324:406fd2029f23 357 *
mbed_official 324:406fd2029f23 358 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 359 *
mbed_official 324:406fd2029f23 360 * Values:
mbed_official 324:406fd2029f23 361 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 362 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 363 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 364 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 365 */
mbed_official 324:406fd2029f23 366 /*@{*/
mbed_official 324:406fd2029f23 367 #define BP_LLWU_PE2_WUPE6 (4U) /*!< Bit position for LLWU_PE2_WUPE6. */
mbed_official 324:406fd2029f23 368 #define BM_LLWU_PE2_WUPE6 (0x30U) /*!< Bit mask for LLWU_PE2_WUPE6. */
mbed_official 324:406fd2029f23 369 #define BS_LLWU_PE2_WUPE6 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE6. */
mbed_official 324:406fd2029f23 370
mbed_official 324:406fd2029f23 371 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
mbed_official 324:406fd2029f23 372 #define BR_LLWU_PE2_WUPE6(x) (HW_LLWU_PE2(x).B.WUPE6)
mbed_official 324:406fd2029f23 373
mbed_official 324:406fd2029f23 374 /*! @brief Format value for bitfield LLWU_PE2_WUPE6. */
mbed_official 324:406fd2029f23 375 #define BF_LLWU_PE2_WUPE6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE6) & BM_LLWU_PE2_WUPE6)
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*! @brief Set the WUPE6 field to a new value. */
mbed_official 324:406fd2029f23 378 #define BW_LLWU_PE2_WUPE6(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE6) | BF_LLWU_PE2_WUPE6(v)))
mbed_official 324:406fd2029f23 379 /*@}*/
mbed_official 324:406fd2029f23 380
mbed_official 324:406fd2029f23 381 /*!
mbed_official 324:406fd2029f23 382 * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
mbed_official 324:406fd2029f23 383 *
mbed_official 324:406fd2029f23 384 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 385 *
mbed_official 324:406fd2029f23 386 * Values:
mbed_official 324:406fd2029f23 387 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 388 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 389 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 390 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 391 */
mbed_official 324:406fd2029f23 392 /*@{*/
mbed_official 324:406fd2029f23 393 #define BP_LLWU_PE2_WUPE7 (6U) /*!< Bit position for LLWU_PE2_WUPE7. */
mbed_official 324:406fd2029f23 394 #define BM_LLWU_PE2_WUPE7 (0xC0U) /*!< Bit mask for LLWU_PE2_WUPE7. */
mbed_official 324:406fd2029f23 395 #define BS_LLWU_PE2_WUPE7 (2U) /*!< Bit field size in bits for LLWU_PE2_WUPE7. */
mbed_official 324:406fd2029f23 396
mbed_official 324:406fd2029f23 397 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
mbed_official 324:406fd2029f23 398 #define BR_LLWU_PE2_WUPE7(x) (HW_LLWU_PE2(x).B.WUPE7)
mbed_official 324:406fd2029f23 399
mbed_official 324:406fd2029f23 400 /*! @brief Format value for bitfield LLWU_PE2_WUPE7. */
mbed_official 324:406fd2029f23 401 #define BF_LLWU_PE2_WUPE7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE2_WUPE7) & BM_LLWU_PE2_WUPE7)
mbed_official 324:406fd2029f23 402
mbed_official 324:406fd2029f23 403 /*! @brief Set the WUPE7 field to a new value. */
mbed_official 324:406fd2029f23 404 #define BW_LLWU_PE2_WUPE7(x, v) (HW_LLWU_PE2_WR(x, (HW_LLWU_PE2_RD(x) & ~BM_LLWU_PE2_WUPE7) | BF_LLWU_PE2_WUPE7(v)))
mbed_official 324:406fd2029f23 405 /*@}*/
mbed_official 324:406fd2029f23 406
mbed_official 324:406fd2029f23 407 /*******************************************************************************
mbed_official 324:406fd2029f23 408 * HW_LLWU_PE3 - LLWU Pin Enable 3 register
mbed_official 324:406fd2029f23 409 ******************************************************************************/
mbed_official 324:406fd2029f23 410
mbed_official 324:406fd2029f23 411 /*!
mbed_official 324:406fd2029f23 412 * @brief HW_LLWU_PE3 - LLWU Pin Enable 3 register (RW)
mbed_official 324:406fd2029f23 413 *
mbed_official 324:406fd2029f23 414 * Reset value: 0x00U
mbed_official 324:406fd2029f23 415 *
mbed_official 324:406fd2029f23 416 * LLWU_PE3 contains the field to enable and select the edge detect type for the
mbed_official 324:406fd2029f23 417 * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
mbed_official 324:406fd2029f23 418 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 419 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 420 * IntroductionInformation found here describes the registers of the Reset Control Module
mbed_official 324:406fd2029f23 421 * (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 422 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 423 */
mbed_official 324:406fd2029f23 424 typedef union _hw_llwu_pe3
mbed_official 324:406fd2029f23 425 {
mbed_official 324:406fd2029f23 426 uint8_t U;
mbed_official 324:406fd2029f23 427 struct _hw_llwu_pe3_bitfields
mbed_official 324:406fd2029f23 428 {
mbed_official 324:406fd2029f23 429 uint8_t WUPE8 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P8 */
mbed_official 324:406fd2029f23 430 uint8_t WUPE9 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P9 */
mbed_official 324:406fd2029f23 431 uint8_t WUPE10 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P10 */
mbed_official 324:406fd2029f23 432 uint8_t WUPE11 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P11 */
mbed_official 324:406fd2029f23 433 } B;
mbed_official 324:406fd2029f23 434 } hw_llwu_pe3_t;
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*!
mbed_official 324:406fd2029f23 437 * @name Constants and macros for entire LLWU_PE3 register
mbed_official 324:406fd2029f23 438 */
mbed_official 324:406fd2029f23 439 /*@{*/
mbed_official 324:406fd2029f23 440 #define HW_LLWU_PE3_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 441
mbed_official 324:406fd2029f23 442 #define HW_LLWU_PE3(x) (*(__IO hw_llwu_pe3_t *) HW_LLWU_PE3_ADDR(x))
mbed_official 324:406fd2029f23 443 #define HW_LLWU_PE3_RD(x) (HW_LLWU_PE3(x).U)
mbed_official 324:406fd2029f23 444 #define HW_LLWU_PE3_WR(x, v) (HW_LLWU_PE3(x).U = (v))
mbed_official 324:406fd2029f23 445 #define HW_LLWU_PE3_SET(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) | (v)))
mbed_official 324:406fd2029f23 446 #define HW_LLWU_PE3_CLR(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 447 #define HW_LLWU_PE3_TOG(x, v) (HW_LLWU_PE3_WR(x, HW_LLWU_PE3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 448 /*@}*/
mbed_official 324:406fd2029f23 449
mbed_official 324:406fd2029f23 450 /*
mbed_official 324:406fd2029f23 451 * Constants & macros for individual LLWU_PE3 bitfields
mbed_official 324:406fd2029f23 452 */
mbed_official 324:406fd2029f23 453
mbed_official 324:406fd2029f23 454 /*!
mbed_official 324:406fd2029f23 455 * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
mbed_official 324:406fd2029f23 456 *
mbed_official 324:406fd2029f23 457 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 458 *
mbed_official 324:406fd2029f23 459 * Values:
mbed_official 324:406fd2029f23 460 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 461 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 462 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 463 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 464 */
mbed_official 324:406fd2029f23 465 /*@{*/
mbed_official 324:406fd2029f23 466 #define BP_LLWU_PE3_WUPE8 (0U) /*!< Bit position for LLWU_PE3_WUPE8. */
mbed_official 324:406fd2029f23 467 #define BM_LLWU_PE3_WUPE8 (0x03U) /*!< Bit mask for LLWU_PE3_WUPE8. */
mbed_official 324:406fd2029f23 468 #define BS_LLWU_PE3_WUPE8 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE8. */
mbed_official 324:406fd2029f23 469
mbed_official 324:406fd2029f23 470 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
mbed_official 324:406fd2029f23 471 #define BR_LLWU_PE3_WUPE8(x) (HW_LLWU_PE3(x).B.WUPE8)
mbed_official 324:406fd2029f23 472
mbed_official 324:406fd2029f23 473 /*! @brief Format value for bitfield LLWU_PE3_WUPE8. */
mbed_official 324:406fd2029f23 474 #define BF_LLWU_PE3_WUPE8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE8) & BM_LLWU_PE3_WUPE8)
mbed_official 324:406fd2029f23 475
mbed_official 324:406fd2029f23 476 /*! @brief Set the WUPE8 field to a new value. */
mbed_official 324:406fd2029f23 477 #define BW_LLWU_PE3_WUPE8(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE8) | BF_LLWU_PE3_WUPE8(v)))
mbed_official 324:406fd2029f23 478 /*@}*/
mbed_official 324:406fd2029f23 479
mbed_official 324:406fd2029f23 480 /*!
mbed_official 324:406fd2029f23 481 * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
mbed_official 324:406fd2029f23 482 *
mbed_official 324:406fd2029f23 483 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 484 *
mbed_official 324:406fd2029f23 485 * Values:
mbed_official 324:406fd2029f23 486 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 487 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 488 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 489 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 490 */
mbed_official 324:406fd2029f23 491 /*@{*/
mbed_official 324:406fd2029f23 492 #define BP_LLWU_PE3_WUPE9 (2U) /*!< Bit position for LLWU_PE3_WUPE9. */
mbed_official 324:406fd2029f23 493 #define BM_LLWU_PE3_WUPE9 (0x0CU) /*!< Bit mask for LLWU_PE3_WUPE9. */
mbed_official 324:406fd2029f23 494 #define BS_LLWU_PE3_WUPE9 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE9. */
mbed_official 324:406fd2029f23 495
mbed_official 324:406fd2029f23 496 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
mbed_official 324:406fd2029f23 497 #define BR_LLWU_PE3_WUPE9(x) (HW_LLWU_PE3(x).B.WUPE9)
mbed_official 324:406fd2029f23 498
mbed_official 324:406fd2029f23 499 /*! @brief Format value for bitfield LLWU_PE3_WUPE9. */
mbed_official 324:406fd2029f23 500 #define BF_LLWU_PE3_WUPE9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE9) & BM_LLWU_PE3_WUPE9)
mbed_official 324:406fd2029f23 501
mbed_official 324:406fd2029f23 502 /*! @brief Set the WUPE9 field to a new value. */
mbed_official 324:406fd2029f23 503 #define BW_LLWU_PE3_WUPE9(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE9) | BF_LLWU_PE3_WUPE9(v)))
mbed_official 324:406fd2029f23 504 /*@}*/
mbed_official 324:406fd2029f23 505
mbed_official 324:406fd2029f23 506 /*!
mbed_official 324:406fd2029f23 507 * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
mbed_official 324:406fd2029f23 508 *
mbed_official 324:406fd2029f23 509 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 510 *
mbed_official 324:406fd2029f23 511 * Values:
mbed_official 324:406fd2029f23 512 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 513 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 514 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 515 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 516 */
mbed_official 324:406fd2029f23 517 /*@{*/
mbed_official 324:406fd2029f23 518 #define BP_LLWU_PE3_WUPE10 (4U) /*!< Bit position for LLWU_PE3_WUPE10. */
mbed_official 324:406fd2029f23 519 #define BM_LLWU_PE3_WUPE10 (0x30U) /*!< Bit mask for LLWU_PE3_WUPE10. */
mbed_official 324:406fd2029f23 520 #define BS_LLWU_PE3_WUPE10 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE10. */
mbed_official 324:406fd2029f23 521
mbed_official 324:406fd2029f23 522 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
mbed_official 324:406fd2029f23 523 #define BR_LLWU_PE3_WUPE10(x) (HW_LLWU_PE3(x).B.WUPE10)
mbed_official 324:406fd2029f23 524
mbed_official 324:406fd2029f23 525 /*! @brief Format value for bitfield LLWU_PE3_WUPE10. */
mbed_official 324:406fd2029f23 526 #define BF_LLWU_PE3_WUPE10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE10) & BM_LLWU_PE3_WUPE10)
mbed_official 324:406fd2029f23 527
mbed_official 324:406fd2029f23 528 /*! @brief Set the WUPE10 field to a new value. */
mbed_official 324:406fd2029f23 529 #define BW_LLWU_PE3_WUPE10(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE10) | BF_LLWU_PE3_WUPE10(v)))
mbed_official 324:406fd2029f23 530 /*@}*/
mbed_official 324:406fd2029f23 531
mbed_official 324:406fd2029f23 532 /*!
mbed_official 324:406fd2029f23 533 * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
mbed_official 324:406fd2029f23 534 *
mbed_official 324:406fd2029f23 535 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 536 *
mbed_official 324:406fd2029f23 537 * Values:
mbed_official 324:406fd2029f23 538 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 539 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 540 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 541 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 542 */
mbed_official 324:406fd2029f23 543 /*@{*/
mbed_official 324:406fd2029f23 544 #define BP_LLWU_PE3_WUPE11 (6U) /*!< Bit position for LLWU_PE3_WUPE11. */
mbed_official 324:406fd2029f23 545 #define BM_LLWU_PE3_WUPE11 (0xC0U) /*!< Bit mask for LLWU_PE3_WUPE11. */
mbed_official 324:406fd2029f23 546 #define BS_LLWU_PE3_WUPE11 (2U) /*!< Bit field size in bits for LLWU_PE3_WUPE11. */
mbed_official 324:406fd2029f23 547
mbed_official 324:406fd2029f23 548 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
mbed_official 324:406fd2029f23 549 #define BR_LLWU_PE3_WUPE11(x) (HW_LLWU_PE3(x).B.WUPE11)
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 /*! @brief Format value for bitfield LLWU_PE3_WUPE11. */
mbed_official 324:406fd2029f23 552 #define BF_LLWU_PE3_WUPE11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE3_WUPE11) & BM_LLWU_PE3_WUPE11)
mbed_official 324:406fd2029f23 553
mbed_official 324:406fd2029f23 554 /*! @brief Set the WUPE11 field to a new value. */
mbed_official 324:406fd2029f23 555 #define BW_LLWU_PE3_WUPE11(x, v) (HW_LLWU_PE3_WR(x, (HW_LLWU_PE3_RD(x) & ~BM_LLWU_PE3_WUPE11) | BF_LLWU_PE3_WUPE11(v)))
mbed_official 324:406fd2029f23 556 /*@}*/
mbed_official 324:406fd2029f23 557
mbed_official 324:406fd2029f23 558 /*******************************************************************************
mbed_official 324:406fd2029f23 559 * HW_LLWU_PE4 - LLWU Pin Enable 4 register
mbed_official 324:406fd2029f23 560 ******************************************************************************/
mbed_official 324:406fd2029f23 561
mbed_official 324:406fd2029f23 562 /*!
mbed_official 324:406fd2029f23 563 * @brief HW_LLWU_PE4 - LLWU Pin Enable 4 register (RW)
mbed_official 324:406fd2029f23 564 *
mbed_official 324:406fd2029f23 565 * Reset value: 0x00U
mbed_official 324:406fd2029f23 566 *
mbed_official 324:406fd2029f23 567 * LLWU_PE4 contains the field to enable and select the edge detect type for the
mbed_official 324:406fd2029f23 568 * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
mbed_official 324:406fd2029f23 569 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 570 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 571 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 324:406fd2029f23 572 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 573 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 574 */
mbed_official 324:406fd2029f23 575 typedef union _hw_llwu_pe4
mbed_official 324:406fd2029f23 576 {
mbed_official 324:406fd2029f23 577 uint8_t U;
mbed_official 324:406fd2029f23 578 struct _hw_llwu_pe4_bitfields
mbed_official 324:406fd2029f23 579 {
mbed_official 324:406fd2029f23 580 uint8_t WUPE12 : 2; /*!< [1:0] Wakeup Pin Enable For LLWU_P12 */
mbed_official 324:406fd2029f23 581 uint8_t WUPE13 : 2; /*!< [3:2] Wakeup Pin Enable For LLWU_P13 */
mbed_official 324:406fd2029f23 582 uint8_t WUPE14 : 2; /*!< [5:4] Wakeup Pin Enable For LLWU_P14 */
mbed_official 324:406fd2029f23 583 uint8_t WUPE15 : 2; /*!< [7:6] Wakeup Pin Enable For LLWU_P15 */
mbed_official 324:406fd2029f23 584 } B;
mbed_official 324:406fd2029f23 585 } hw_llwu_pe4_t;
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /*!
mbed_official 324:406fd2029f23 588 * @name Constants and macros for entire LLWU_PE4 register
mbed_official 324:406fd2029f23 589 */
mbed_official 324:406fd2029f23 590 /*@{*/
mbed_official 324:406fd2029f23 591 #define HW_LLWU_PE4_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 592
mbed_official 324:406fd2029f23 593 #define HW_LLWU_PE4(x) (*(__IO hw_llwu_pe4_t *) HW_LLWU_PE4_ADDR(x))
mbed_official 324:406fd2029f23 594 #define HW_LLWU_PE4_RD(x) (HW_LLWU_PE4(x).U)
mbed_official 324:406fd2029f23 595 #define HW_LLWU_PE4_WR(x, v) (HW_LLWU_PE4(x).U = (v))
mbed_official 324:406fd2029f23 596 #define HW_LLWU_PE4_SET(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) | (v)))
mbed_official 324:406fd2029f23 597 #define HW_LLWU_PE4_CLR(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 598 #define HW_LLWU_PE4_TOG(x, v) (HW_LLWU_PE4_WR(x, HW_LLWU_PE4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 599 /*@}*/
mbed_official 324:406fd2029f23 600
mbed_official 324:406fd2029f23 601 /*
mbed_official 324:406fd2029f23 602 * Constants & macros for individual LLWU_PE4 bitfields
mbed_official 324:406fd2029f23 603 */
mbed_official 324:406fd2029f23 604
mbed_official 324:406fd2029f23 605 /*!
mbed_official 324:406fd2029f23 606 * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
mbed_official 324:406fd2029f23 607 *
mbed_official 324:406fd2029f23 608 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 609 *
mbed_official 324:406fd2029f23 610 * Values:
mbed_official 324:406fd2029f23 611 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 612 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 613 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 614 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 615 */
mbed_official 324:406fd2029f23 616 /*@{*/
mbed_official 324:406fd2029f23 617 #define BP_LLWU_PE4_WUPE12 (0U) /*!< Bit position for LLWU_PE4_WUPE12. */
mbed_official 324:406fd2029f23 618 #define BM_LLWU_PE4_WUPE12 (0x03U) /*!< Bit mask for LLWU_PE4_WUPE12. */
mbed_official 324:406fd2029f23 619 #define BS_LLWU_PE4_WUPE12 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE12. */
mbed_official 324:406fd2029f23 620
mbed_official 324:406fd2029f23 621 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
mbed_official 324:406fd2029f23 622 #define BR_LLWU_PE4_WUPE12(x) (HW_LLWU_PE4(x).B.WUPE12)
mbed_official 324:406fd2029f23 623
mbed_official 324:406fd2029f23 624 /*! @brief Format value for bitfield LLWU_PE4_WUPE12. */
mbed_official 324:406fd2029f23 625 #define BF_LLWU_PE4_WUPE12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE12) & BM_LLWU_PE4_WUPE12)
mbed_official 324:406fd2029f23 626
mbed_official 324:406fd2029f23 627 /*! @brief Set the WUPE12 field to a new value. */
mbed_official 324:406fd2029f23 628 #define BW_LLWU_PE4_WUPE12(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE12) | BF_LLWU_PE4_WUPE12(v)))
mbed_official 324:406fd2029f23 629 /*@}*/
mbed_official 324:406fd2029f23 630
mbed_official 324:406fd2029f23 631 /*!
mbed_official 324:406fd2029f23 632 * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
mbed_official 324:406fd2029f23 633 *
mbed_official 324:406fd2029f23 634 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 635 *
mbed_official 324:406fd2029f23 636 * Values:
mbed_official 324:406fd2029f23 637 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 638 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 639 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 640 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 641 */
mbed_official 324:406fd2029f23 642 /*@{*/
mbed_official 324:406fd2029f23 643 #define BP_LLWU_PE4_WUPE13 (2U) /*!< Bit position for LLWU_PE4_WUPE13. */
mbed_official 324:406fd2029f23 644 #define BM_LLWU_PE4_WUPE13 (0x0CU) /*!< Bit mask for LLWU_PE4_WUPE13. */
mbed_official 324:406fd2029f23 645 #define BS_LLWU_PE4_WUPE13 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE13. */
mbed_official 324:406fd2029f23 646
mbed_official 324:406fd2029f23 647 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
mbed_official 324:406fd2029f23 648 #define BR_LLWU_PE4_WUPE13(x) (HW_LLWU_PE4(x).B.WUPE13)
mbed_official 324:406fd2029f23 649
mbed_official 324:406fd2029f23 650 /*! @brief Format value for bitfield LLWU_PE4_WUPE13. */
mbed_official 324:406fd2029f23 651 #define BF_LLWU_PE4_WUPE13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE13) & BM_LLWU_PE4_WUPE13)
mbed_official 324:406fd2029f23 652
mbed_official 324:406fd2029f23 653 /*! @brief Set the WUPE13 field to a new value. */
mbed_official 324:406fd2029f23 654 #define BW_LLWU_PE4_WUPE13(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE13) | BF_LLWU_PE4_WUPE13(v)))
mbed_official 324:406fd2029f23 655 /*@}*/
mbed_official 324:406fd2029f23 656
mbed_official 324:406fd2029f23 657 /*!
mbed_official 324:406fd2029f23 658 * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
mbed_official 324:406fd2029f23 659 *
mbed_official 324:406fd2029f23 660 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 661 *
mbed_official 324:406fd2029f23 662 * Values:
mbed_official 324:406fd2029f23 663 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 664 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 665 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 666 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 667 */
mbed_official 324:406fd2029f23 668 /*@{*/
mbed_official 324:406fd2029f23 669 #define BP_LLWU_PE4_WUPE14 (4U) /*!< Bit position for LLWU_PE4_WUPE14. */
mbed_official 324:406fd2029f23 670 #define BM_LLWU_PE4_WUPE14 (0x30U) /*!< Bit mask for LLWU_PE4_WUPE14. */
mbed_official 324:406fd2029f23 671 #define BS_LLWU_PE4_WUPE14 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE14. */
mbed_official 324:406fd2029f23 672
mbed_official 324:406fd2029f23 673 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
mbed_official 324:406fd2029f23 674 #define BR_LLWU_PE4_WUPE14(x) (HW_LLWU_PE4(x).B.WUPE14)
mbed_official 324:406fd2029f23 675
mbed_official 324:406fd2029f23 676 /*! @brief Format value for bitfield LLWU_PE4_WUPE14. */
mbed_official 324:406fd2029f23 677 #define BF_LLWU_PE4_WUPE14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE14) & BM_LLWU_PE4_WUPE14)
mbed_official 324:406fd2029f23 678
mbed_official 324:406fd2029f23 679 /*! @brief Set the WUPE14 field to a new value. */
mbed_official 324:406fd2029f23 680 #define BW_LLWU_PE4_WUPE14(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE14) | BF_LLWU_PE4_WUPE14(v)))
mbed_official 324:406fd2029f23 681 /*@}*/
mbed_official 324:406fd2029f23 682
mbed_official 324:406fd2029f23 683 /*!
mbed_official 324:406fd2029f23 684 * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
mbed_official 324:406fd2029f23 685 *
mbed_official 324:406fd2029f23 686 * Enables and configures the edge detection for the wakeup pin.
mbed_official 324:406fd2029f23 687 *
mbed_official 324:406fd2029f23 688 * Values:
mbed_official 324:406fd2029f23 689 * - 00 - External input pin disabled as wakeup input
mbed_official 324:406fd2029f23 690 * - 01 - External input pin enabled with rising edge detection
mbed_official 324:406fd2029f23 691 * - 10 - External input pin enabled with falling edge detection
mbed_official 324:406fd2029f23 692 * - 11 - External input pin enabled with any change detection
mbed_official 324:406fd2029f23 693 */
mbed_official 324:406fd2029f23 694 /*@{*/
mbed_official 324:406fd2029f23 695 #define BP_LLWU_PE4_WUPE15 (6U) /*!< Bit position for LLWU_PE4_WUPE15. */
mbed_official 324:406fd2029f23 696 #define BM_LLWU_PE4_WUPE15 (0xC0U) /*!< Bit mask for LLWU_PE4_WUPE15. */
mbed_official 324:406fd2029f23 697 #define BS_LLWU_PE4_WUPE15 (2U) /*!< Bit field size in bits for LLWU_PE4_WUPE15. */
mbed_official 324:406fd2029f23 698
mbed_official 324:406fd2029f23 699 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
mbed_official 324:406fd2029f23 700 #define BR_LLWU_PE4_WUPE15(x) (HW_LLWU_PE4(x).B.WUPE15)
mbed_official 324:406fd2029f23 701
mbed_official 324:406fd2029f23 702 /*! @brief Format value for bitfield LLWU_PE4_WUPE15. */
mbed_official 324:406fd2029f23 703 #define BF_LLWU_PE4_WUPE15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_PE4_WUPE15) & BM_LLWU_PE4_WUPE15)
mbed_official 324:406fd2029f23 704
mbed_official 324:406fd2029f23 705 /*! @brief Set the WUPE15 field to a new value. */
mbed_official 324:406fd2029f23 706 #define BW_LLWU_PE4_WUPE15(x, v) (HW_LLWU_PE4_WR(x, (HW_LLWU_PE4_RD(x) & ~BM_LLWU_PE4_WUPE15) | BF_LLWU_PE4_WUPE15(v)))
mbed_official 324:406fd2029f23 707 /*@}*/
mbed_official 324:406fd2029f23 708
mbed_official 324:406fd2029f23 709 /*******************************************************************************
mbed_official 324:406fd2029f23 710 * HW_LLWU_ME - LLWU Module Enable register
mbed_official 324:406fd2029f23 711 ******************************************************************************/
mbed_official 324:406fd2029f23 712
mbed_official 324:406fd2029f23 713 /*!
mbed_official 324:406fd2029f23 714 * @brief HW_LLWU_ME - LLWU Module Enable register (RW)
mbed_official 324:406fd2029f23 715 *
mbed_official 324:406fd2029f23 716 * Reset value: 0x00U
mbed_official 324:406fd2029f23 717 *
mbed_official 324:406fd2029f23 718 * LLWU_ME contains the bits to enable the internal module flag as a wakeup
mbed_official 324:406fd2029f23 719 * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
mbed_official 324:406fd2029f23 720 * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
mbed_official 324:406fd2029f23 721 * reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 722 * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
mbed_official 324:406fd2029f23 723 * RCM implements many of the reset functions for the chip. See the chip's reset
mbed_official 324:406fd2029f23 724 * chapter for more information. details for more information.
mbed_official 324:406fd2029f23 725 */
mbed_official 324:406fd2029f23 726 typedef union _hw_llwu_me
mbed_official 324:406fd2029f23 727 {
mbed_official 324:406fd2029f23 728 uint8_t U;
mbed_official 324:406fd2029f23 729 struct _hw_llwu_me_bitfields
mbed_official 324:406fd2029f23 730 {
mbed_official 324:406fd2029f23 731 uint8_t WUME0 : 1; /*!< [0] Wakeup Module Enable For Module 0 */
mbed_official 324:406fd2029f23 732 uint8_t WUME1 : 1; /*!< [1] Wakeup Module Enable for Module 1 */
mbed_official 324:406fd2029f23 733 uint8_t WUME2 : 1; /*!< [2] Wakeup Module Enable For Module 2 */
mbed_official 324:406fd2029f23 734 uint8_t WUME3 : 1; /*!< [3] Wakeup Module Enable For Module 3 */
mbed_official 324:406fd2029f23 735 uint8_t WUME4 : 1; /*!< [4] Wakeup Module Enable For Module 4 */
mbed_official 324:406fd2029f23 736 uint8_t WUME5 : 1; /*!< [5] Wakeup Module Enable For Module 5 */
mbed_official 324:406fd2029f23 737 uint8_t WUME6 : 1; /*!< [6] Wakeup Module Enable For Module 6 */
mbed_official 324:406fd2029f23 738 uint8_t WUME7 : 1; /*!< [7] Wakeup Module Enable For Module 7 */
mbed_official 324:406fd2029f23 739 } B;
mbed_official 324:406fd2029f23 740 } hw_llwu_me_t;
mbed_official 324:406fd2029f23 741
mbed_official 324:406fd2029f23 742 /*!
mbed_official 324:406fd2029f23 743 * @name Constants and macros for entire LLWU_ME register
mbed_official 324:406fd2029f23 744 */
mbed_official 324:406fd2029f23 745 /*@{*/
mbed_official 324:406fd2029f23 746 #define HW_LLWU_ME_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 747
mbed_official 324:406fd2029f23 748 #define HW_LLWU_ME(x) (*(__IO hw_llwu_me_t *) HW_LLWU_ME_ADDR(x))
mbed_official 324:406fd2029f23 749 #define HW_LLWU_ME_RD(x) (HW_LLWU_ME(x).U)
mbed_official 324:406fd2029f23 750 #define HW_LLWU_ME_WR(x, v) (HW_LLWU_ME(x).U = (v))
mbed_official 324:406fd2029f23 751 #define HW_LLWU_ME_SET(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) | (v)))
mbed_official 324:406fd2029f23 752 #define HW_LLWU_ME_CLR(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 753 #define HW_LLWU_ME_TOG(x, v) (HW_LLWU_ME_WR(x, HW_LLWU_ME_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 754 /*@}*/
mbed_official 324:406fd2029f23 755
mbed_official 324:406fd2029f23 756 /*
mbed_official 324:406fd2029f23 757 * Constants & macros for individual LLWU_ME bitfields
mbed_official 324:406fd2029f23 758 */
mbed_official 324:406fd2029f23 759
mbed_official 324:406fd2029f23 760 /*!
mbed_official 324:406fd2029f23 761 * @name Register LLWU_ME, field WUME0[0] (RW)
mbed_official 324:406fd2029f23 762 *
mbed_official 324:406fd2029f23 763 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 764 *
mbed_official 324:406fd2029f23 765 * Values:
mbed_official 324:406fd2029f23 766 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 767 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 768 */
mbed_official 324:406fd2029f23 769 /*@{*/
mbed_official 324:406fd2029f23 770 #define BP_LLWU_ME_WUME0 (0U) /*!< Bit position for LLWU_ME_WUME0. */
mbed_official 324:406fd2029f23 771 #define BM_LLWU_ME_WUME0 (0x01U) /*!< Bit mask for LLWU_ME_WUME0. */
mbed_official 324:406fd2029f23 772 #define BS_LLWU_ME_WUME0 (1U) /*!< Bit field size in bits for LLWU_ME_WUME0. */
mbed_official 324:406fd2029f23 773
mbed_official 324:406fd2029f23 774 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
mbed_official 324:406fd2029f23 775 #define BR_LLWU_ME_WUME0(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0))
mbed_official 324:406fd2029f23 776
mbed_official 324:406fd2029f23 777 /*! @brief Format value for bitfield LLWU_ME_WUME0. */
mbed_official 324:406fd2029f23 778 #define BF_LLWU_ME_WUME0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME0) & BM_LLWU_ME_WUME0)
mbed_official 324:406fd2029f23 779
mbed_official 324:406fd2029f23 780 /*! @brief Set the WUME0 field to a new value. */
mbed_official 324:406fd2029f23 781 #define BW_LLWU_ME_WUME0(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME0) = (v))
mbed_official 324:406fd2029f23 782 /*@}*/
mbed_official 324:406fd2029f23 783
mbed_official 324:406fd2029f23 784 /*!
mbed_official 324:406fd2029f23 785 * @name Register LLWU_ME, field WUME1[1] (RW)
mbed_official 324:406fd2029f23 786 *
mbed_official 324:406fd2029f23 787 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 788 *
mbed_official 324:406fd2029f23 789 * Values:
mbed_official 324:406fd2029f23 790 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 791 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 792 */
mbed_official 324:406fd2029f23 793 /*@{*/
mbed_official 324:406fd2029f23 794 #define BP_LLWU_ME_WUME1 (1U) /*!< Bit position for LLWU_ME_WUME1. */
mbed_official 324:406fd2029f23 795 #define BM_LLWU_ME_WUME1 (0x02U) /*!< Bit mask for LLWU_ME_WUME1. */
mbed_official 324:406fd2029f23 796 #define BS_LLWU_ME_WUME1 (1U) /*!< Bit field size in bits for LLWU_ME_WUME1. */
mbed_official 324:406fd2029f23 797
mbed_official 324:406fd2029f23 798 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
mbed_official 324:406fd2029f23 799 #define BR_LLWU_ME_WUME1(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1))
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 /*! @brief Format value for bitfield LLWU_ME_WUME1. */
mbed_official 324:406fd2029f23 802 #define BF_LLWU_ME_WUME1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME1) & BM_LLWU_ME_WUME1)
mbed_official 324:406fd2029f23 803
mbed_official 324:406fd2029f23 804 /*! @brief Set the WUME1 field to a new value. */
mbed_official 324:406fd2029f23 805 #define BW_LLWU_ME_WUME1(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME1) = (v))
mbed_official 324:406fd2029f23 806 /*@}*/
mbed_official 324:406fd2029f23 807
mbed_official 324:406fd2029f23 808 /*!
mbed_official 324:406fd2029f23 809 * @name Register LLWU_ME, field WUME2[2] (RW)
mbed_official 324:406fd2029f23 810 *
mbed_official 324:406fd2029f23 811 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 812 *
mbed_official 324:406fd2029f23 813 * Values:
mbed_official 324:406fd2029f23 814 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 815 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 816 */
mbed_official 324:406fd2029f23 817 /*@{*/
mbed_official 324:406fd2029f23 818 #define BP_LLWU_ME_WUME2 (2U) /*!< Bit position for LLWU_ME_WUME2. */
mbed_official 324:406fd2029f23 819 #define BM_LLWU_ME_WUME2 (0x04U) /*!< Bit mask for LLWU_ME_WUME2. */
mbed_official 324:406fd2029f23 820 #define BS_LLWU_ME_WUME2 (1U) /*!< Bit field size in bits for LLWU_ME_WUME2. */
mbed_official 324:406fd2029f23 821
mbed_official 324:406fd2029f23 822 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
mbed_official 324:406fd2029f23 823 #define BR_LLWU_ME_WUME2(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2))
mbed_official 324:406fd2029f23 824
mbed_official 324:406fd2029f23 825 /*! @brief Format value for bitfield LLWU_ME_WUME2. */
mbed_official 324:406fd2029f23 826 #define BF_LLWU_ME_WUME2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME2) & BM_LLWU_ME_WUME2)
mbed_official 324:406fd2029f23 827
mbed_official 324:406fd2029f23 828 /*! @brief Set the WUME2 field to a new value. */
mbed_official 324:406fd2029f23 829 #define BW_LLWU_ME_WUME2(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME2) = (v))
mbed_official 324:406fd2029f23 830 /*@}*/
mbed_official 324:406fd2029f23 831
mbed_official 324:406fd2029f23 832 /*!
mbed_official 324:406fd2029f23 833 * @name Register LLWU_ME, field WUME3[3] (RW)
mbed_official 324:406fd2029f23 834 *
mbed_official 324:406fd2029f23 835 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 836 *
mbed_official 324:406fd2029f23 837 * Values:
mbed_official 324:406fd2029f23 838 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 839 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 840 */
mbed_official 324:406fd2029f23 841 /*@{*/
mbed_official 324:406fd2029f23 842 #define BP_LLWU_ME_WUME3 (3U) /*!< Bit position for LLWU_ME_WUME3. */
mbed_official 324:406fd2029f23 843 #define BM_LLWU_ME_WUME3 (0x08U) /*!< Bit mask for LLWU_ME_WUME3. */
mbed_official 324:406fd2029f23 844 #define BS_LLWU_ME_WUME3 (1U) /*!< Bit field size in bits for LLWU_ME_WUME3. */
mbed_official 324:406fd2029f23 845
mbed_official 324:406fd2029f23 846 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
mbed_official 324:406fd2029f23 847 #define BR_LLWU_ME_WUME3(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3))
mbed_official 324:406fd2029f23 848
mbed_official 324:406fd2029f23 849 /*! @brief Format value for bitfield LLWU_ME_WUME3. */
mbed_official 324:406fd2029f23 850 #define BF_LLWU_ME_WUME3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME3) & BM_LLWU_ME_WUME3)
mbed_official 324:406fd2029f23 851
mbed_official 324:406fd2029f23 852 /*! @brief Set the WUME3 field to a new value. */
mbed_official 324:406fd2029f23 853 #define BW_LLWU_ME_WUME3(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME3) = (v))
mbed_official 324:406fd2029f23 854 /*@}*/
mbed_official 324:406fd2029f23 855
mbed_official 324:406fd2029f23 856 /*!
mbed_official 324:406fd2029f23 857 * @name Register LLWU_ME, field WUME4[4] (RW)
mbed_official 324:406fd2029f23 858 *
mbed_official 324:406fd2029f23 859 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 860 *
mbed_official 324:406fd2029f23 861 * Values:
mbed_official 324:406fd2029f23 862 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 863 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 864 */
mbed_official 324:406fd2029f23 865 /*@{*/
mbed_official 324:406fd2029f23 866 #define BP_LLWU_ME_WUME4 (4U) /*!< Bit position for LLWU_ME_WUME4. */
mbed_official 324:406fd2029f23 867 #define BM_LLWU_ME_WUME4 (0x10U) /*!< Bit mask for LLWU_ME_WUME4. */
mbed_official 324:406fd2029f23 868 #define BS_LLWU_ME_WUME4 (1U) /*!< Bit field size in bits for LLWU_ME_WUME4. */
mbed_official 324:406fd2029f23 869
mbed_official 324:406fd2029f23 870 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
mbed_official 324:406fd2029f23 871 #define BR_LLWU_ME_WUME4(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4))
mbed_official 324:406fd2029f23 872
mbed_official 324:406fd2029f23 873 /*! @brief Format value for bitfield LLWU_ME_WUME4. */
mbed_official 324:406fd2029f23 874 #define BF_LLWU_ME_WUME4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME4) & BM_LLWU_ME_WUME4)
mbed_official 324:406fd2029f23 875
mbed_official 324:406fd2029f23 876 /*! @brief Set the WUME4 field to a new value. */
mbed_official 324:406fd2029f23 877 #define BW_LLWU_ME_WUME4(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME4) = (v))
mbed_official 324:406fd2029f23 878 /*@}*/
mbed_official 324:406fd2029f23 879
mbed_official 324:406fd2029f23 880 /*!
mbed_official 324:406fd2029f23 881 * @name Register LLWU_ME, field WUME5[5] (RW)
mbed_official 324:406fd2029f23 882 *
mbed_official 324:406fd2029f23 883 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 884 *
mbed_official 324:406fd2029f23 885 * Values:
mbed_official 324:406fd2029f23 886 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 887 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 888 */
mbed_official 324:406fd2029f23 889 /*@{*/
mbed_official 324:406fd2029f23 890 #define BP_LLWU_ME_WUME5 (5U) /*!< Bit position for LLWU_ME_WUME5. */
mbed_official 324:406fd2029f23 891 #define BM_LLWU_ME_WUME5 (0x20U) /*!< Bit mask for LLWU_ME_WUME5. */
mbed_official 324:406fd2029f23 892 #define BS_LLWU_ME_WUME5 (1U) /*!< Bit field size in bits for LLWU_ME_WUME5. */
mbed_official 324:406fd2029f23 893
mbed_official 324:406fd2029f23 894 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
mbed_official 324:406fd2029f23 895 #define BR_LLWU_ME_WUME5(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5))
mbed_official 324:406fd2029f23 896
mbed_official 324:406fd2029f23 897 /*! @brief Format value for bitfield LLWU_ME_WUME5. */
mbed_official 324:406fd2029f23 898 #define BF_LLWU_ME_WUME5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME5) & BM_LLWU_ME_WUME5)
mbed_official 324:406fd2029f23 899
mbed_official 324:406fd2029f23 900 /*! @brief Set the WUME5 field to a new value. */
mbed_official 324:406fd2029f23 901 #define BW_LLWU_ME_WUME5(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME5) = (v))
mbed_official 324:406fd2029f23 902 /*@}*/
mbed_official 324:406fd2029f23 903
mbed_official 324:406fd2029f23 904 /*!
mbed_official 324:406fd2029f23 905 * @name Register LLWU_ME, field WUME6[6] (RW)
mbed_official 324:406fd2029f23 906 *
mbed_official 324:406fd2029f23 907 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 908 *
mbed_official 324:406fd2029f23 909 * Values:
mbed_official 324:406fd2029f23 910 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 911 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 912 */
mbed_official 324:406fd2029f23 913 /*@{*/
mbed_official 324:406fd2029f23 914 #define BP_LLWU_ME_WUME6 (6U) /*!< Bit position for LLWU_ME_WUME6. */
mbed_official 324:406fd2029f23 915 #define BM_LLWU_ME_WUME6 (0x40U) /*!< Bit mask for LLWU_ME_WUME6. */
mbed_official 324:406fd2029f23 916 #define BS_LLWU_ME_WUME6 (1U) /*!< Bit field size in bits for LLWU_ME_WUME6. */
mbed_official 324:406fd2029f23 917
mbed_official 324:406fd2029f23 918 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
mbed_official 324:406fd2029f23 919 #define BR_LLWU_ME_WUME6(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6))
mbed_official 324:406fd2029f23 920
mbed_official 324:406fd2029f23 921 /*! @brief Format value for bitfield LLWU_ME_WUME6. */
mbed_official 324:406fd2029f23 922 #define BF_LLWU_ME_WUME6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME6) & BM_LLWU_ME_WUME6)
mbed_official 324:406fd2029f23 923
mbed_official 324:406fd2029f23 924 /*! @brief Set the WUME6 field to a new value. */
mbed_official 324:406fd2029f23 925 #define BW_LLWU_ME_WUME6(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME6) = (v))
mbed_official 324:406fd2029f23 926 /*@}*/
mbed_official 324:406fd2029f23 927
mbed_official 324:406fd2029f23 928 /*!
mbed_official 324:406fd2029f23 929 * @name Register LLWU_ME, field WUME7[7] (RW)
mbed_official 324:406fd2029f23 930 *
mbed_official 324:406fd2029f23 931 * Enables an internal module as a wakeup source input.
mbed_official 324:406fd2029f23 932 *
mbed_official 324:406fd2029f23 933 * Values:
mbed_official 324:406fd2029f23 934 * - 0 - Internal module flag not used as wakeup source
mbed_official 324:406fd2029f23 935 * - 1 - Internal module flag used as wakeup source
mbed_official 324:406fd2029f23 936 */
mbed_official 324:406fd2029f23 937 /*@{*/
mbed_official 324:406fd2029f23 938 #define BP_LLWU_ME_WUME7 (7U) /*!< Bit position for LLWU_ME_WUME7. */
mbed_official 324:406fd2029f23 939 #define BM_LLWU_ME_WUME7 (0x80U) /*!< Bit mask for LLWU_ME_WUME7. */
mbed_official 324:406fd2029f23 940 #define BS_LLWU_ME_WUME7 (1U) /*!< Bit field size in bits for LLWU_ME_WUME7. */
mbed_official 324:406fd2029f23 941
mbed_official 324:406fd2029f23 942 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
mbed_official 324:406fd2029f23 943 #define BR_LLWU_ME_WUME7(x) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7))
mbed_official 324:406fd2029f23 944
mbed_official 324:406fd2029f23 945 /*! @brief Format value for bitfield LLWU_ME_WUME7. */
mbed_official 324:406fd2029f23 946 #define BF_LLWU_ME_WUME7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_ME_WUME7) & BM_LLWU_ME_WUME7)
mbed_official 324:406fd2029f23 947
mbed_official 324:406fd2029f23 948 /*! @brief Set the WUME7 field to a new value. */
mbed_official 324:406fd2029f23 949 #define BW_LLWU_ME_WUME7(x, v) (BITBAND_ACCESS8(HW_LLWU_ME_ADDR(x), BP_LLWU_ME_WUME7) = (v))
mbed_official 324:406fd2029f23 950 /*@}*/
mbed_official 324:406fd2029f23 951
mbed_official 324:406fd2029f23 952 /*******************************************************************************
mbed_official 324:406fd2029f23 953 * HW_LLWU_F1 - LLWU Flag 1 register
mbed_official 324:406fd2029f23 954 ******************************************************************************/
mbed_official 324:406fd2029f23 955
mbed_official 324:406fd2029f23 956 /*!
mbed_official 324:406fd2029f23 957 * @brief HW_LLWU_F1 - LLWU Flag 1 register (W1C)
mbed_official 324:406fd2029f23 958 *
mbed_official 324:406fd2029f23 959 * Reset value: 0x00U
mbed_official 324:406fd2029f23 960 *
mbed_official 324:406fd2029f23 961 * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
mbed_official 324:406fd2029f23 962 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
mbed_official 324:406fd2029f23 963 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
mbed_official 324:406fd2029f23 964 * external wakeup flags are read-only and clearing a flag is accomplished by a write
mbed_official 324:406fd2029f23 965 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
mbed_official 324:406fd2029f23 966 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
mbed_official 324:406fd2029f23 967 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 968 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 969 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 324:406fd2029f23 970 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 971 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 972 */
mbed_official 324:406fd2029f23 973 typedef union _hw_llwu_f1
mbed_official 324:406fd2029f23 974 {
mbed_official 324:406fd2029f23 975 uint8_t U;
mbed_official 324:406fd2029f23 976 struct _hw_llwu_f1_bitfields
mbed_official 324:406fd2029f23 977 {
mbed_official 324:406fd2029f23 978 uint8_t WUF0 : 1; /*!< [0] Wakeup Flag For LLWU_P0 */
mbed_official 324:406fd2029f23 979 uint8_t WUF1 : 1; /*!< [1] Wakeup Flag For LLWU_P1 */
mbed_official 324:406fd2029f23 980 uint8_t WUF2 : 1; /*!< [2] Wakeup Flag For LLWU_P2 */
mbed_official 324:406fd2029f23 981 uint8_t WUF3 : 1; /*!< [3] Wakeup Flag For LLWU_P3 */
mbed_official 324:406fd2029f23 982 uint8_t WUF4 : 1; /*!< [4] Wakeup Flag For LLWU_P4 */
mbed_official 324:406fd2029f23 983 uint8_t WUF5 : 1; /*!< [5] Wakeup Flag For LLWU_P5 */
mbed_official 324:406fd2029f23 984 uint8_t WUF6 : 1; /*!< [6] Wakeup Flag For LLWU_P6 */
mbed_official 324:406fd2029f23 985 uint8_t WUF7 : 1; /*!< [7] Wakeup Flag For LLWU_P7 */
mbed_official 324:406fd2029f23 986 } B;
mbed_official 324:406fd2029f23 987 } hw_llwu_f1_t;
mbed_official 324:406fd2029f23 988
mbed_official 324:406fd2029f23 989 /*!
mbed_official 324:406fd2029f23 990 * @name Constants and macros for entire LLWU_F1 register
mbed_official 324:406fd2029f23 991 */
mbed_official 324:406fd2029f23 992 /*@{*/
mbed_official 324:406fd2029f23 993 #define HW_LLWU_F1_ADDR(x) ((x) + 0x5U)
mbed_official 324:406fd2029f23 994
mbed_official 324:406fd2029f23 995 #define HW_LLWU_F1(x) (*(__IO hw_llwu_f1_t *) HW_LLWU_F1_ADDR(x))
mbed_official 324:406fd2029f23 996 #define HW_LLWU_F1_RD(x) (HW_LLWU_F1(x).U)
mbed_official 324:406fd2029f23 997 #define HW_LLWU_F1_WR(x, v) (HW_LLWU_F1(x).U = (v))
mbed_official 324:406fd2029f23 998 #define HW_LLWU_F1_SET(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) | (v)))
mbed_official 324:406fd2029f23 999 #define HW_LLWU_F1_CLR(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1000 #define HW_LLWU_F1_TOG(x, v) (HW_LLWU_F1_WR(x, HW_LLWU_F1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1001 /*@}*/
mbed_official 324:406fd2029f23 1002
mbed_official 324:406fd2029f23 1003 /*
mbed_official 324:406fd2029f23 1004 * Constants & macros for individual LLWU_F1 bitfields
mbed_official 324:406fd2029f23 1005 */
mbed_official 324:406fd2029f23 1006
mbed_official 324:406fd2029f23 1007 /*!
mbed_official 324:406fd2029f23 1008 * @name Register LLWU_F1, field WUF0[0] (W1C)
mbed_official 324:406fd2029f23 1009 *
mbed_official 324:406fd2029f23 1010 * Indicates that an enabled external wake-up pin was a source of exiting a
mbed_official 324:406fd2029f23 1011 * low-leakage power mode. To clear the flag, write a 1 to WUF0.
mbed_official 324:406fd2029f23 1012 *
mbed_official 324:406fd2029f23 1013 * Values:
mbed_official 324:406fd2029f23 1014 * - 0 - LLWU_P0 input was not a wakeup source
mbed_official 324:406fd2029f23 1015 * - 1 - LLWU_P0 input was a wakeup source
mbed_official 324:406fd2029f23 1016 */
mbed_official 324:406fd2029f23 1017 /*@{*/
mbed_official 324:406fd2029f23 1018 #define BP_LLWU_F1_WUF0 (0U) /*!< Bit position for LLWU_F1_WUF0. */
mbed_official 324:406fd2029f23 1019 #define BM_LLWU_F1_WUF0 (0x01U) /*!< Bit mask for LLWU_F1_WUF0. */
mbed_official 324:406fd2029f23 1020 #define BS_LLWU_F1_WUF0 (1U) /*!< Bit field size in bits for LLWU_F1_WUF0. */
mbed_official 324:406fd2029f23 1021
mbed_official 324:406fd2029f23 1022 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
mbed_official 324:406fd2029f23 1023 #define BR_LLWU_F1_WUF0(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0))
mbed_official 324:406fd2029f23 1024
mbed_official 324:406fd2029f23 1025 /*! @brief Format value for bitfield LLWU_F1_WUF0. */
mbed_official 324:406fd2029f23 1026 #define BF_LLWU_F1_WUF0(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF0) & BM_LLWU_F1_WUF0)
mbed_official 324:406fd2029f23 1027
mbed_official 324:406fd2029f23 1028 /*! @brief Set the WUF0 field to a new value. */
mbed_official 324:406fd2029f23 1029 #define BW_LLWU_F1_WUF0(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF0) = (v))
mbed_official 324:406fd2029f23 1030 /*@}*/
mbed_official 324:406fd2029f23 1031
mbed_official 324:406fd2029f23 1032 /*!
mbed_official 324:406fd2029f23 1033 * @name Register LLWU_F1, field WUF1[1] (W1C)
mbed_official 324:406fd2029f23 1034 *
mbed_official 324:406fd2029f23 1035 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1036 * low-leakage power mode. To clear the flag, write a 1 to WUF1.
mbed_official 324:406fd2029f23 1037 *
mbed_official 324:406fd2029f23 1038 * Values:
mbed_official 324:406fd2029f23 1039 * - 0 - LLWU_P1 input was not a wakeup source
mbed_official 324:406fd2029f23 1040 * - 1 - LLWU_P1 input was a wakeup source
mbed_official 324:406fd2029f23 1041 */
mbed_official 324:406fd2029f23 1042 /*@{*/
mbed_official 324:406fd2029f23 1043 #define BP_LLWU_F1_WUF1 (1U) /*!< Bit position for LLWU_F1_WUF1. */
mbed_official 324:406fd2029f23 1044 #define BM_LLWU_F1_WUF1 (0x02U) /*!< Bit mask for LLWU_F1_WUF1. */
mbed_official 324:406fd2029f23 1045 #define BS_LLWU_F1_WUF1 (1U) /*!< Bit field size in bits for LLWU_F1_WUF1. */
mbed_official 324:406fd2029f23 1046
mbed_official 324:406fd2029f23 1047 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
mbed_official 324:406fd2029f23 1048 #define BR_LLWU_F1_WUF1(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1))
mbed_official 324:406fd2029f23 1049
mbed_official 324:406fd2029f23 1050 /*! @brief Format value for bitfield LLWU_F1_WUF1. */
mbed_official 324:406fd2029f23 1051 #define BF_LLWU_F1_WUF1(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF1) & BM_LLWU_F1_WUF1)
mbed_official 324:406fd2029f23 1052
mbed_official 324:406fd2029f23 1053 /*! @brief Set the WUF1 field to a new value. */
mbed_official 324:406fd2029f23 1054 #define BW_LLWU_F1_WUF1(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF1) = (v))
mbed_official 324:406fd2029f23 1055 /*@}*/
mbed_official 324:406fd2029f23 1056
mbed_official 324:406fd2029f23 1057 /*!
mbed_official 324:406fd2029f23 1058 * @name Register LLWU_F1, field WUF2[2] (W1C)
mbed_official 324:406fd2029f23 1059 *
mbed_official 324:406fd2029f23 1060 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1061 * low-leakage power mode. To clear the flag, write a 1 to WUF2.
mbed_official 324:406fd2029f23 1062 *
mbed_official 324:406fd2029f23 1063 * Values:
mbed_official 324:406fd2029f23 1064 * - 0 - LLWU_P2 input was not a wakeup source
mbed_official 324:406fd2029f23 1065 * - 1 - LLWU_P2 input was a wakeup source
mbed_official 324:406fd2029f23 1066 */
mbed_official 324:406fd2029f23 1067 /*@{*/
mbed_official 324:406fd2029f23 1068 #define BP_LLWU_F1_WUF2 (2U) /*!< Bit position for LLWU_F1_WUF2. */
mbed_official 324:406fd2029f23 1069 #define BM_LLWU_F1_WUF2 (0x04U) /*!< Bit mask for LLWU_F1_WUF2. */
mbed_official 324:406fd2029f23 1070 #define BS_LLWU_F1_WUF2 (1U) /*!< Bit field size in bits for LLWU_F1_WUF2. */
mbed_official 324:406fd2029f23 1071
mbed_official 324:406fd2029f23 1072 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
mbed_official 324:406fd2029f23 1073 #define BR_LLWU_F1_WUF2(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2))
mbed_official 324:406fd2029f23 1074
mbed_official 324:406fd2029f23 1075 /*! @brief Format value for bitfield LLWU_F1_WUF2. */
mbed_official 324:406fd2029f23 1076 #define BF_LLWU_F1_WUF2(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF2) & BM_LLWU_F1_WUF2)
mbed_official 324:406fd2029f23 1077
mbed_official 324:406fd2029f23 1078 /*! @brief Set the WUF2 field to a new value. */
mbed_official 324:406fd2029f23 1079 #define BW_LLWU_F1_WUF2(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF2) = (v))
mbed_official 324:406fd2029f23 1080 /*@}*/
mbed_official 324:406fd2029f23 1081
mbed_official 324:406fd2029f23 1082 /*!
mbed_official 324:406fd2029f23 1083 * @name Register LLWU_F1, field WUF3[3] (W1C)
mbed_official 324:406fd2029f23 1084 *
mbed_official 324:406fd2029f23 1085 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1086 * low-leakage power mode. To clear the flag, write a 1 to WUF3.
mbed_official 324:406fd2029f23 1087 *
mbed_official 324:406fd2029f23 1088 * Values:
mbed_official 324:406fd2029f23 1089 * - 0 - LLWU_P3 input was not a wake-up source
mbed_official 324:406fd2029f23 1090 * - 1 - LLWU_P3 input was a wake-up source
mbed_official 324:406fd2029f23 1091 */
mbed_official 324:406fd2029f23 1092 /*@{*/
mbed_official 324:406fd2029f23 1093 #define BP_LLWU_F1_WUF3 (3U) /*!< Bit position for LLWU_F1_WUF3. */
mbed_official 324:406fd2029f23 1094 #define BM_LLWU_F1_WUF3 (0x08U) /*!< Bit mask for LLWU_F1_WUF3. */
mbed_official 324:406fd2029f23 1095 #define BS_LLWU_F1_WUF3 (1U) /*!< Bit field size in bits for LLWU_F1_WUF3. */
mbed_official 324:406fd2029f23 1096
mbed_official 324:406fd2029f23 1097 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
mbed_official 324:406fd2029f23 1098 #define BR_LLWU_F1_WUF3(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3))
mbed_official 324:406fd2029f23 1099
mbed_official 324:406fd2029f23 1100 /*! @brief Format value for bitfield LLWU_F1_WUF3. */
mbed_official 324:406fd2029f23 1101 #define BF_LLWU_F1_WUF3(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF3) & BM_LLWU_F1_WUF3)
mbed_official 324:406fd2029f23 1102
mbed_official 324:406fd2029f23 1103 /*! @brief Set the WUF3 field to a new value. */
mbed_official 324:406fd2029f23 1104 #define BW_LLWU_F1_WUF3(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF3) = (v))
mbed_official 324:406fd2029f23 1105 /*@}*/
mbed_official 324:406fd2029f23 1106
mbed_official 324:406fd2029f23 1107 /*!
mbed_official 324:406fd2029f23 1108 * @name Register LLWU_F1, field WUF4[4] (W1C)
mbed_official 324:406fd2029f23 1109 *
mbed_official 324:406fd2029f23 1110 * Indicates that an enabled external wake-up pin was a source of exiting a
mbed_official 324:406fd2029f23 1111 * low-leakage power mode. To clear the flag, write a 1 to WUF4.
mbed_official 324:406fd2029f23 1112 *
mbed_official 324:406fd2029f23 1113 * Values:
mbed_official 324:406fd2029f23 1114 * - 0 - LLWU_P4 input was not a wakeup source
mbed_official 324:406fd2029f23 1115 * - 1 - LLWU_P4 input was a wakeup source
mbed_official 324:406fd2029f23 1116 */
mbed_official 324:406fd2029f23 1117 /*@{*/
mbed_official 324:406fd2029f23 1118 #define BP_LLWU_F1_WUF4 (4U) /*!< Bit position for LLWU_F1_WUF4. */
mbed_official 324:406fd2029f23 1119 #define BM_LLWU_F1_WUF4 (0x10U) /*!< Bit mask for LLWU_F1_WUF4. */
mbed_official 324:406fd2029f23 1120 #define BS_LLWU_F1_WUF4 (1U) /*!< Bit field size in bits for LLWU_F1_WUF4. */
mbed_official 324:406fd2029f23 1121
mbed_official 324:406fd2029f23 1122 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
mbed_official 324:406fd2029f23 1123 #define BR_LLWU_F1_WUF4(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4))
mbed_official 324:406fd2029f23 1124
mbed_official 324:406fd2029f23 1125 /*! @brief Format value for bitfield LLWU_F1_WUF4. */
mbed_official 324:406fd2029f23 1126 #define BF_LLWU_F1_WUF4(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF4) & BM_LLWU_F1_WUF4)
mbed_official 324:406fd2029f23 1127
mbed_official 324:406fd2029f23 1128 /*! @brief Set the WUF4 field to a new value. */
mbed_official 324:406fd2029f23 1129 #define BW_LLWU_F1_WUF4(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF4) = (v))
mbed_official 324:406fd2029f23 1130 /*@}*/
mbed_official 324:406fd2029f23 1131
mbed_official 324:406fd2029f23 1132 /*!
mbed_official 324:406fd2029f23 1133 * @name Register LLWU_F1, field WUF5[5] (W1C)
mbed_official 324:406fd2029f23 1134 *
mbed_official 324:406fd2029f23 1135 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1136 * low-leakage power mode. To clear the flag, write a 1 to WUF5.
mbed_official 324:406fd2029f23 1137 *
mbed_official 324:406fd2029f23 1138 * Values:
mbed_official 324:406fd2029f23 1139 * - 0 - LLWU_P5 input was not a wakeup source
mbed_official 324:406fd2029f23 1140 * - 1 - LLWU_P5 input was a wakeup source
mbed_official 324:406fd2029f23 1141 */
mbed_official 324:406fd2029f23 1142 /*@{*/
mbed_official 324:406fd2029f23 1143 #define BP_LLWU_F1_WUF5 (5U) /*!< Bit position for LLWU_F1_WUF5. */
mbed_official 324:406fd2029f23 1144 #define BM_LLWU_F1_WUF5 (0x20U) /*!< Bit mask for LLWU_F1_WUF5. */
mbed_official 324:406fd2029f23 1145 #define BS_LLWU_F1_WUF5 (1U) /*!< Bit field size in bits for LLWU_F1_WUF5. */
mbed_official 324:406fd2029f23 1146
mbed_official 324:406fd2029f23 1147 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
mbed_official 324:406fd2029f23 1148 #define BR_LLWU_F1_WUF5(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5))
mbed_official 324:406fd2029f23 1149
mbed_official 324:406fd2029f23 1150 /*! @brief Format value for bitfield LLWU_F1_WUF5. */
mbed_official 324:406fd2029f23 1151 #define BF_LLWU_F1_WUF5(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF5) & BM_LLWU_F1_WUF5)
mbed_official 324:406fd2029f23 1152
mbed_official 324:406fd2029f23 1153 /*! @brief Set the WUF5 field to a new value. */
mbed_official 324:406fd2029f23 1154 #define BW_LLWU_F1_WUF5(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF5) = (v))
mbed_official 324:406fd2029f23 1155 /*@}*/
mbed_official 324:406fd2029f23 1156
mbed_official 324:406fd2029f23 1157 /*!
mbed_official 324:406fd2029f23 1158 * @name Register LLWU_F1, field WUF6[6] (W1C)
mbed_official 324:406fd2029f23 1159 *
mbed_official 324:406fd2029f23 1160 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1161 * low-leakage power mode. To clear the flag, write a 1 to WUF6.
mbed_official 324:406fd2029f23 1162 *
mbed_official 324:406fd2029f23 1163 * Values:
mbed_official 324:406fd2029f23 1164 * - 0 - LLWU_P6 input was not a wakeup source
mbed_official 324:406fd2029f23 1165 * - 1 - LLWU_P6 input was a wakeup source
mbed_official 324:406fd2029f23 1166 */
mbed_official 324:406fd2029f23 1167 /*@{*/
mbed_official 324:406fd2029f23 1168 #define BP_LLWU_F1_WUF6 (6U) /*!< Bit position for LLWU_F1_WUF6. */
mbed_official 324:406fd2029f23 1169 #define BM_LLWU_F1_WUF6 (0x40U) /*!< Bit mask for LLWU_F1_WUF6. */
mbed_official 324:406fd2029f23 1170 #define BS_LLWU_F1_WUF6 (1U) /*!< Bit field size in bits for LLWU_F1_WUF6. */
mbed_official 324:406fd2029f23 1171
mbed_official 324:406fd2029f23 1172 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
mbed_official 324:406fd2029f23 1173 #define BR_LLWU_F1_WUF6(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6))
mbed_official 324:406fd2029f23 1174
mbed_official 324:406fd2029f23 1175 /*! @brief Format value for bitfield LLWU_F1_WUF6. */
mbed_official 324:406fd2029f23 1176 #define BF_LLWU_F1_WUF6(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF6) & BM_LLWU_F1_WUF6)
mbed_official 324:406fd2029f23 1177
mbed_official 324:406fd2029f23 1178 /*! @brief Set the WUF6 field to a new value. */
mbed_official 324:406fd2029f23 1179 #define BW_LLWU_F1_WUF6(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF6) = (v))
mbed_official 324:406fd2029f23 1180 /*@}*/
mbed_official 324:406fd2029f23 1181
mbed_official 324:406fd2029f23 1182 /*!
mbed_official 324:406fd2029f23 1183 * @name Register LLWU_F1, field WUF7[7] (W1C)
mbed_official 324:406fd2029f23 1184 *
mbed_official 324:406fd2029f23 1185 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1186 * low-leakage power mode. To clear the flag, write a 1 to WUF7.
mbed_official 324:406fd2029f23 1187 *
mbed_official 324:406fd2029f23 1188 * Values:
mbed_official 324:406fd2029f23 1189 * - 0 - LLWU_P7 input was not a wakeup source
mbed_official 324:406fd2029f23 1190 * - 1 - LLWU_P7 input was a wakeup source
mbed_official 324:406fd2029f23 1191 */
mbed_official 324:406fd2029f23 1192 /*@{*/
mbed_official 324:406fd2029f23 1193 #define BP_LLWU_F1_WUF7 (7U) /*!< Bit position for LLWU_F1_WUF7. */
mbed_official 324:406fd2029f23 1194 #define BM_LLWU_F1_WUF7 (0x80U) /*!< Bit mask for LLWU_F1_WUF7. */
mbed_official 324:406fd2029f23 1195 #define BS_LLWU_F1_WUF7 (1U) /*!< Bit field size in bits for LLWU_F1_WUF7. */
mbed_official 324:406fd2029f23 1196
mbed_official 324:406fd2029f23 1197 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
mbed_official 324:406fd2029f23 1198 #define BR_LLWU_F1_WUF7(x) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7))
mbed_official 324:406fd2029f23 1199
mbed_official 324:406fd2029f23 1200 /*! @brief Format value for bitfield LLWU_F1_WUF7. */
mbed_official 324:406fd2029f23 1201 #define BF_LLWU_F1_WUF7(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F1_WUF7) & BM_LLWU_F1_WUF7)
mbed_official 324:406fd2029f23 1202
mbed_official 324:406fd2029f23 1203 /*! @brief Set the WUF7 field to a new value. */
mbed_official 324:406fd2029f23 1204 #define BW_LLWU_F1_WUF7(x, v) (BITBAND_ACCESS8(HW_LLWU_F1_ADDR(x), BP_LLWU_F1_WUF7) = (v))
mbed_official 324:406fd2029f23 1205 /*@}*/
mbed_official 324:406fd2029f23 1206
mbed_official 324:406fd2029f23 1207 /*******************************************************************************
mbed_official 324:406fd2029f23 1208 * HW_LLWU_F2 - LLWU Flag 2 register
mbed_official 324:406fd2029f23 1209 ******************************************************************************/
mbed_official 324:406fd2029f23 1210
mbed_official 324:406fd2029f23 1211 /*!
mbed_official 324:406fd2029f23 1212 * @brief HW_LLWU_F2 - LLWU Flag 2 register (W1C)
mbed_official 324:406fd2029f23 1213 *
mbed_official 324:406fd2029f23 1214 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1215 *
mbed_official 324:406fd2029f23 1216 * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
mbed_official 324:406fd2029f23 1217 * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
mbed_official 324:406fd2029f23 1218 * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
mbed_official 324:406fd2029f23 1219 * external wakeup flags are read-only and clearing a flag is accomplished by a write
mbed_official 324:406fd2029f23 1220 * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
mbed_official 324:406fd2029f23 1221 * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
mbed_official 324:406fd2029f23 1222 * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 1223 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 1224 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 324:406fd2029f23 1225 * Module (RCM). The RCM implements many of the reset functions for the chip. See the
mbed_official 324:406fd2029f23 1226 * chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 1227 */
mbed_official 324:406fd2029f23 1228 typedef union _hw_llwu_f2
mbed_official 324:406fd2029f23 1229 {
mbed_official 324:406fd2029f23 1230 uint8_t U;
mbed_official 324:406fd2029f23 1231 struct _hw_llwu_f2_bitfields
mbed_official 324:406fd2029f23 1232 {
mbed_official 324:406fd2029f23 1233 uint8_t WUF8 : 1; /*!< [0] Wakeup Flag For LLWU_P8 */
mbed_official 324:406fd2029f23 1234 uint8_t WUF9 : 1; /*!< [1] Wakeup Flag For LLWU_P9 */
mbed_official 324:406fd2029f23 1235 uint8_t WUF10 : 1; /*!< [2] Wakeup Flag For LLWU_P10 */
mbed_official 324:406fd2029f23 1236 uint8_t WUF11 : 1; /*!< [3] Wakeup Flag For LLWU_P11 */
mbed_official 324:406fd2029f23 1237 uint8_t WUF12 : 1; /*!< [4] Wakeup Flag For LLWU_P12 */
mbed_official 324:406fd2029f23 1238 uint8_t WUF13 : 1; /*!< [5] Wakeup Flag For LLWU_P13 */
mbed_official 324:406fd2029f23 1239 uint8_t WUF14 : 1; /*!< [6] Wakeup Flag For LLWU_P14 */
mbed_official 324:406fd2029f23 1240 uint8_t WUF15 : 1; /*!< [7] Wakeup Flag For LLWU_P15 */
mbed_official 324:406fd2029f23 1241 } B;
mbed_official 324:406fd2029f23 1242 } hw_llwu_f2_t;
mbed_official 324:406fd2029f23 1243
mbed_official 324:406fd2029f23 1244 /*!
mbed_official 324:406fd2029f23 1245 * @name Constants and macros for entire LLWU_F2 register
mbed_official 324:406fd2029f23 1246 */
mbed_official 324:406fd2029f23 1247 /*@{*/
mbed_official 324:406fd2029f23 1248 #define HW_LLWU_F2_ADDR(x) ((x) + 0x6U)
mbed_official 324:406fd2029f23 1249
mbed_official 324:406fd2029f23 1250 #define HW_LLWU_F2(x) (*(__IO hw_llwu_f2_t *) HW_LLWU_F2_ADDR(x))
mbed_official 324:406fd2029f23 1251 #define HW_LLWU_F2_RD(x) (HW_LLWU_F2(x).U)
mbed_official 324:406fd2029f23 1252 #define HW_LLWU_F2_WR(x, v) (HW_LLWU_F2(x).U = (v))
mbed_official 324:406fd2029f23 1253 #define HW_LLWU_F2_SET(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) | (v)))
mbed_official 324:406fd2029f23 1254 #define HW_LLWU_F2_CLR(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1255 #define HW_LLWU_F2_TOG(x, v) (HW_LLWU_F2_WR(x, HW_LLWU_F2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1256 /*@}*/
mbed_official 324:406fd2029f23 1257
mbed_official 324:406fd2029f23 1258 /*
mbed_official 324:406fd2029f23 1259 * Constants & macros for individual LLWU_F2 bitfields
mbed_official 324:406fd2029f23 1260 */
mbed_official 324:406fd2029f23 1261
mbed_official 324:406fd2029f23 1262 /*!
mbed_official 324:406fd2029f23 1263 * @name Register LLWU_F2, field WUF8[0] (W1C)
mbed_official 324:406fd2029f23 1264 *
mbed_official 324:406fd2029f23 1265 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1266 * low-leakage power mode. To clear the flag, write a 1 to WUF8.
mbed_official 324:406fd2029f23 1267 *
mbed_official 324:406fd2029f23 1268 * Values:
mbed_official 324:406fd2029f23 1269 * - 0 - LLWU_P8 input was not a wakeup source
mbed_official 324:406fd2029f23 1270 * - 1 - LLWU_P8 input was a wakeup source
mbed_official 324:406fd2029f23 1271 */
mbed_official 324:406fd2029f23 1272 /*@{*/
mbed_official 324:406fd2029f23 1273 #define BP_LLWU_F2_WUF8 (0U) /*!< Bit position for LLWU_F2_WUF8. */
mbed_official 324:406fd2029f23 1274 #define BM_LLWU_F2_WUF8 (0x01U) /*!< Bit mask for LLWU_F2_WUF8. */
mbed_official 324:406fd2029f23 1275 #define BS_LLWU_F2_WUF8 (1U) /*!< Bit field size in bits for LLWU_F2_WUF8. */
mbed_official 324:406fd2029f23 1276
mbed_official 324:406fd2029f23 1277 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
mbed_official 324:406fd2029f23 1278 #define BR_LLWU_F2_WUF8(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8))
mbed_official 324:406fd2029f23 1279
mbed_official 324:406fd2029f23 1280 /*! @brief Format value for bitfield LLWU_F2_WUF8. */
mbed_official 324:406fd2029f23 1281 #define BF_LLWU_F2_WUF8(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF8) & BM_LLWU_F2_WUF8)
mbed_official 324:406fd2029f23 1282
mbed_official 324:406fd2029f23 1283 /*! @brief Set the WUF8 field to a new value. */
mbed_official 324:406fd2029f23 1284 #define BW_LLWU_F2_WUF8(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF8) = (v))
mbed_official 324:406fd2029f23 1285 /*@}*/
mbed_official 324:406fd2029f23 1286
mbed_official 324:406fd2029f23 1287 /*!
mbed_official 324:406fd2029f23 1288 * @name Register LLWU_F2, field WUF9[1] (W1C)
mbed_official 324:406fd2029f23 1289 *
mbed_official 324:406fd2029f23 1290 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1291 * low-leakage power mode. To clear the flag, write a 1 to WUF9.
mbed_official 324:406fd2029f23 1292 *
mbed_official 324:406fd2029f23 1293 * Values:
mbed_official 324:406fd2029f23 1294 * - 0 - LLWU_P9 input was not a wakeup source
mbed_official 324:406fd2029f23 1295 * - 1 - LLWU_P9 input was a wakeup source
mbed_official 324:406fd2029f23 1296 */
mbed_official 324:406fd2029f23 1297 /*@{*/
mbed_official 324:406fd2029f23 1298 #define BP_LLWU_F2_WUF9 (1U) /*!< Bit position for LLWU_F2_WUF9. */
mbed_official 324:406fd2029f23 1299 #define BM_LLWU_F2_WUF9 (0x02U) /*!< Bit mask for LLWU_F2_WUF9. */
mbed_official 324:406fd2029f23 1300 #define BS_LLWU_F2_WUF9 (1U) /*!< Bit field size in bits for LLWU_F2_WUF9. */
mbed_official 324:406fd2029f23 1301
mbed_official 324:406fd2029f23 1302 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
mbed_official 324:406fd2029f23 1303 #define BR_LLWU_F2_WUF9(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9))
mbed_official 324:406fd2029f23 1304
mbed_official 324:406fd2029f23 1305 /*! @brief Format value for bitfield LLWU_F2_WUF9. */
mbed_official 324:406fd2029f23 1306 #define BF_LLWU_F2_WUF9(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF9) & BM_LLWU_F2_WUF9)
mbed_official 324:406fd2029f23 1307
mbed_official 324:406fd2029f23 1308 /*! @brief Set the WUF9 field to a new value. */
mbed_official 324:406fd2029f23 1309 #define BW_LLWU_F2_WUF9(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF9) = (v))
mbed_official 324:406fd2029f23 1310 /*@}*/
mbed_official 324:406fd2029f23 1311
mbed_official 324:406fd2029f23 1312 /*!
mbed_official 324:406fd2029f23 1313 * @name Register LLWU_F2, field WUF10[2] (W1C)
mbed_official 324:406fd2029f23 1314 *
mbed_official 324:406fd2029f23 1315 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1316 * low-leakage power mode. To clear the flag, write a 1 to WUF10.
mbed_official 324:406fd2029f23 1317 *
mbed_official 324:406fd2029f23 1318 * Values:
mbed_official 324:406fd2029f23 1319 * - 0 - LLWU_P10 input was not a wakeup source
mbed_official 324:406fd2029f23 1320 * - 1 - LLWU_P10 input was a wakeup source
mbed_official 324:406fd2029f23 1321 */
mbed_official 324:406fd2029f23 1322 /*@{*/
mbed_official 324:406fd2029f23 1323 #define BP_LLWU_F2_WUF10 (2U) /*!< Bit position for LLWU_F2_WUF10. */
mbed_official 324:406fd2029f23 1324 #define BM_LLWU_F2_WUF10 (0x04U) /*!< Bit mask for LLWU_F2_WUF10. */
mbed_official 324:406fd2029f23 1325 #define BS_LLWU_F2_WUF10 (1U) /*!< Bit field size in bits for LLWU_F2_WUF10. */
mbed_official 324:406fd2029f23 1326
mbed_official 324:406fd2029f23 1327 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
mbed_official 324:406fd2029f23 1328 #define BR_LLWU_F2_WUF10(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10))
mbed_official 324:406fd2029f23 1329
mbed_official 324:406fd2029f23 1330 /*! @brief Format value for bitfield LLWU_F2_WUF10. */
mbed_official 324:406fd2029f23 1331 #define BF_LLWU_F2_WUF10(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF10) & BM_LLWU_F2_WUF10)
mbed_official 324:406fd2029f23 1332
mbed_official 324:406fd2029f23 1333 /*! @brief Set the WUF10 field to a new value. */
mbed_official 324:406fd2029f23 1334 #define BW_LLWU_F2_WUF10(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF10) = (v))
mbed_official 324:406fd2029f23 1335 /*@}*/
mbed_official 324:406fd2029f23 1336
mbed_official 324:406fd2029f23 1337 /*!
mbed_official 324:406fd2029f23 1338 * @name Register LLWU_F2, field WUF11[3] (W1C)
mbed_official 324:406fd2029f23 1339 *
mbed_official 324:406fd2029f23 1340 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1341 * low-leakage power mode. To clear the flag, write a 1 to WUF11.
mbed_official 324:406fd2029f23 1342 *
mbed_official 324:406fd2029f23 1343 * Values:
mbed_official 324:406fd2029f23 1344 * - 0 - LLWU_P11 input was not a wakeup source
mbed_official 324:406fd2029f23 1345 * - 1 - LLWU_P11 input was a wakeup source
mbed_official 324:406fd2029f23 1346 */
mbed_official 324:406fd2029f23 1347 /*@{*/
mbed_official 324:406fd2029f23 1348 #define BP_LLWU_F2_WUF11 (3U) /*!< Bit position for LLWU_F2_WUF11. */
mbed_official 324:406fd2029f23 1349 #define BM_LLWU_F2_WUF11 (0x08U) /*!< Bit mask for LLWU_F2_WUF11. */
mbed_official 324:406fd2029f23 1350 #define BS_LLWU_F2_WUF11 (1U) /*!< Bit field size in bits for LLWU_F2_WUF11. */
mbed_official 324:406fd2029f23 1351
mbed_official 324:406fd2029f23 1352 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
mbed_official 324:406fd2029f23 1353 #define BR_LLWU_F2_WUF11(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11))
mbed_official 324:406fd2029f23 1354
mbed_official 324:406fd2029f23 1355 /*! @brief Format value for bitfield LLWU_F2_WUF11. */
mbed_official 324:406fd2029f23 1356 #define BF_LLWU_F2_WUF11(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF11) & BM_LLWU_F2_WUF11)
mbed_official 324:406fd2029f23 1357
mbed_official 324:406fd2029f23 1358 /*! @brief Set the WUF11 field to a new value. */
mbed_official 324:406fd2029f23 1359 #define BW_LLWU_F2_WUF11(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF11) = (v))
mbed_official 324:406fd2029f23 1360 /*@}*/
mbed_official 324:406fd2029f23 1361
mbed_official 324:406fd2029f23 1362 /*!
mbed_official 324:406fd2029f23 1363 * @name Register LLWU_F2, field WUF12[4] (W1C)
mbed_official 324:406fd2029f23 1364 *
mbed_official 324:406fd2029f23 1365 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1366 * low-leakage power mode. To clear the flag, write a 1 to WUF12.
mbed_official 324:406fd2029f23 1367 *
mbed_official 324:406fd2029f23 1368 * Values:
mbed_official 324:406fd2029f23 1369 * - 0 - LLWU_P12 input was not a wakeup source
mbed_official 324:406fd2029f23 1370 * - 1 - LLWU_P12 input was a wakeup source
mbed_official 324:406fd2029f23 1371 */
mbed_official 324:406fd2029f23 1372 /*@{*/
mbed_official 324:406fd2029f23 1373 #define BP_LLWU_F2_WUF12 (4U) /*!< Bit position for LLWU_F2_WUF12. */
mbed_official 324:406fd2029f23 1374 #define BM_LLWU_F2_WUF12 (0x10U) /*!< Bit mask for LLWU_F2_WUF12. */
mbed_official 324:406fd2029f23 1375 #define BS_LLWU_F2_WUF12 (1U) /*!< Bit field size in bits for LLWU_F2_WUF12. */
mbed_official 324:406fd2029f23 1376
mbed_official 324:406fd2029f23 1377 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
mbed_official 324:406fd2029f23 1378 #define BR_LLWU_F2_WUF12(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12))
mbed_official 324:406fd2029f23 1379
mbed_official 324:406fd2029f23 1380 /*! @brief Format value for bitfield LLWU_F2_WUF12. */
mbed_official 324:406fd2029f23 1381 #define BF_LLWU_F2_WUF12(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF12) & BM_LLWU_F2_WUF12)
mbed_official 324:406fd2029f23 1382
mbed_official 324:406fd2029f23 1383 /*! @brief Set the WUF12 field to a new value. */
mbed_official 324:406fd2029f23 1384 #define BW_LLWU_F2_WUF12(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF12) = (v))
mbed_official 324:406fd2029f23 1385 /*@}*/
mbed_official 324:406fd2029f23 1386
mbed_official 324:406fd2029f23 1387 /*!
mbed_official 324:406fd2029f23 1388 * @name Register LLWU_F2, field WUF13[5] (W1C)
mbed_official 324:406fd2029f23 1389 *
mbed_official 324:406fd2029f23 1390 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1391 * low-leakage power mode. To clear the flag, write a 1 to WUF13.
mbed_official 324:406fd2029f23 1392 *
mbed_official 324:406fd2029f23 1393 * Values:
mbed_official 324:406fd2029f23 1394 * - 0 - LLWU_P13 input was not a wakeup source
mbed_official 324:406fd2029f23 1395 * - 1 - LLWU_P13 input was a wakeup source
mbed_official 324:406fd2029f23 1396 */
mbed_official 324:406fd2029f23 1397 /*@{*/
mbed_official 324:406fd2029f23 1398 #define BP_LLWU_F2_WUF13 (5U) /*!< Bit position for LLWU_F2_WUF13. */
mbed_official 324:406fd2029f23 1399 #define BM_LLWU_F2_WUF13 (0x20U) /*!< Bit mask for LLWU_F2_WUF13. */
mbed_official 324:406fd2029f23 1400 #define BS_LLWU_F2_WUF13 (1U) /*!< Bit field size in bits for LLWU_F2_WUF13. */
mbed_official 324:406fd2029f23 1401
mbed_official 324:406fd2029f23 1402 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
mbed_official 324:406fd2029f23 1403 #define BR_LLWU_F2_WUF13(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13))
mbed_official 324:406fd2029f23 1404
mbed_official 324:406fd2029f23 1405 /*! @brief Format value for bitfield LLWU_F2_WUF13. */
mbed_official 324:406fd2029f23 1406 #define BF_LLWU_F2_WUF13(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF13) & BM_LLWU_F2_WUF13)
mbed_official 324:406fd2029f23 1407
mbed_official 324:406fd2029f23 1408 /*! @brief Set the WUF13 field to a new value. */
mbed_official 324:406fd2029f23 1409 #define BW_LLWU_F2_WUF13(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF13) = (v))
mbed_official 324:406fd2029f23 1410 /*@}*/
mbed_official 324:406fd2029f23 1411
mbed_official 324:406fd2029f23 1412 /*!
mbed_official 324:406fd2029f23 1413 * @name Register LLWU_F2, field WUF14[6] (W1C)
mbed_official 324:406fd2029f23 1414 *
mbed_official 324:406fd2029f23 1415 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1416 * low-leakage power mode. To clear the flag, write a 1 to WUF14.
mbed_official 324:406fd2029f23 1417 *
mbed_official 324:406fd2029f23 1418 * Values:
mbed_official 324:406fd2029f23 1419 * - 0 - LLWU_P14 input was not a wakeup source
mbed_official 324:406fd2029f23 1420 * - 1 - LLWU_P14 input was a wakeup source
mbed_official 324:406fd2029f23 1421 */
mbed_official 324:406fd2029f23 1422 /*@{*/
mbed_official 324:406fd2029f23 1423 #define BP_LLWU_F2_WUF14 (6U) /*!< Bit position for LLWU_F2_WUF14. */
mbed_official 324:406fd2029f23 1424 #define BM_LLWU_F2_WUF14 (0x40U) /*!< Bit mask for LLWU_F2_WUF14. */
mbed_official 324:406fd2029f23 1425 #define BS_LLWU_F2_WUF14 (1U) /*!< Bit field size in bits for LLWU_F2_WUF14. */
mbed_official 324:406fd2029f23 1426
mbed_official 324:406fd2029f23 1427 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
mbed_official 324:406fd2029f23 1428 #define BR_LLWU_F2_WUF14(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14))
mbed_official 324:406fd2029f23 1429
mbed_official 324:406fd2029f23 1430 /*! @brief Format value for bitfield LLWU_F2_WUF14. */
mbed_official 324:406fd2029f23 1431 #define BF_LLWU_F2_WUF14(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF14) & BM_LLWU_F2_WUF14)
mbed_official 324:406fd2029f23 1432
mbed_official 324:406fd2029f23 1433 /*! @brief Set the WUF14 field to a new value. */
mbed_official 324:406fd2029f23 1434 #define BW_LLWU_F2_WUF14(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF14) = (v))
mbed_official 324:406fd2029f23 1435 /*@}*/
mbed_official 324:406fd2029f23 1436
mbed_official 324:406fd2029f23 1437 /*!
mbed_official 324:406fd2029f23 1438 * @name Register LLWU_F2, field WUF15[7] (W1C)
mbed_official 324:406fd2029f23 1439 *
mbed_official 324:406fd2029f23 1440 * Indicates that an enabled external wakeup pin was a source of exiting a
mbed_official 324:406fd2029f23 1441 * low-leakage power mode. To clear the flag, write a 1 to WUF15.
mbed_official 324:406fd2029f23 1442 *
mbed_official 324:406fd2029f23 1443 * Values:
mbed_official 324:406fd2029f23 1444 * - 0 - LLWU_P15 input was not a wakeup source
mbed_official 324:406fd2029f23 1445 * - 1 - LLWU_P15 input was a wakeup source
mbed_official 324:406fd2029f23 1446 */
mbed_official 324:406fd2029f23 1447 /*@{*/
mbed_official 324:406fd2029f23 1448 #define BP_LLWU_F2_WUF15 (7U) /*!< Bit position for LLWU_F2_WUF15. */
mbed_official 324:406fd2029f23 1449 #define BM_LLWU_F2_WUF15 (0x80U) /*!< Bit mask for LLWU_F2_WUF15. */
mbed_official 324:406fd2029f23 1450 #define BS_LLWU_F2_WUF15 (1U) /*!< Bit field size in bits for LLWU_F2_WUF15. */
mbed_official 324:406fd2029f23 1451
mbed_official 324:406fd2029f23 1452 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
mbed_official 324:406fd2029f23 1453 #define BR_LLWU_F2_WUF15(x) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15))
mbed_official 324:406fd2029f23 1454
mbed_official 324:406fd2029f23 1455 /*! @brief Format value for bitfield LLWU_F2_WUF15. */
mbed_official 324:406fd2029f23 1456 #define BF_LLWU_F2_WUF15(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_F2_WUF15) & BM_LLWU_F2_WUF15)
mbed_official 324:406fd2029f23 1457
mbed_official 324:406fd2029f23 1458 /*! @brief Set the WUF15 field to a new value. */
mbed_official 324:406fd2029f23 1459 #define BW_LLWU_F2_WUF15(x, v) (BITBAND_ACCESS8(HW_LLWU_F2_ADDR(x), BP_LLWU_F2_WUF15) = (v))
mbed_official 324:406fd2029f23 1460 /*@}*/
mbed_official 324:406fd2029f23 1461
mbed_official 324:406fd2029f23 1462 /*******************************************************************************
mbed_official 324:406fd2029f23 1463 * HW_LLWU_F3 - LLWU Flag 3 register
mbed_official 324:406fd2029f23 1464 ******************************************************************************/
mbed_official 324:406fd2029f23 1465
mbed_official 324:406fd2029f23 1466 /*!
mbed_official 324:406fd2029f23 1467 * @brief HW_LLWU_F3 - LLWU Flag 3 register (RO)
mbed_official 324:406fd2029f23 1468 *
mbed_official 324:406fd2029f23 1469 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1470 *
mbed_official 324:406fd2029f23 1471 * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
mbed_official 324:406fd2029f23 1472 * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
mbed_official 324:406fd2029f23 1473 * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
mbed_official 324:406fd2029f23 1474 * For internal peripherals that are capable of running in a low-leakage power
mbed_official 324:406fd2029f23 1475 * mode, such as a real time clock module or CMP module, the flag from the
mbed_official 324:406fd2029f23 1476 * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
mbed_official 324:406fd2029f23 1477 * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
mbed_official 324:406fd2029f23 1478 * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
mbed_official 324:406fd2029f23 1479 * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
mbed_official 324:406fd2029f23 1480 * the IntroductionInformation found here describes the registers of the Reset
mbed_official 324:406fd2029f23 1481 * Control Module (RCM). The RCM implements many of the reset functions for the
mbed_official 324:406fd2029f23 1482 * chip. See the chip's reset chapter for more information. details for more
mbed_official 324:406fd2029f23 1483 * information.
mbed_official 324:406fd2029f23 1484 */
mbed_official 324:406fd2029f23 1485 typedef union _hw_llwu_f3
mbed_official 324:406fd2029f23 1486 {
mbed_official 324:406fd2029f23 1487 uint8_t U;
mbed_official 324:406fd2029f23 1488 struct _hw_llwu_f3_bitfields
mbed_official 324:406fd2029f23 1489 {
mbed_official 324:406fd2029f23 1490 uint8_t MWUF0 : 1; /*!< [0] Wakeup flag For module 0 */
mbed_official 324:406fd2029f23 1491 uint8_t MWUF1 : 1; /*!< [1] Wakeup flag For module 1 */
mbed_official 324:406fd2029f23 1492 uint8_t MWUF2 : 1; /*!< [2] Wakeup flag For module 2 */
mbed_official 324:406fd2029f23 1493 uint8_t MWUF3 : 1; /*!< [3] Wakeup flag For module 3 */
mbed_official 324:406fd2029f23 1494 uint8_t MWUF4 : 1; /*!< [4] Wakeup flag For module 4 */
mbed_official 324:406fd2029f23 1495 uint8_t MWUF5 : 1; /*!< [5] Wakeup flag For module 5 */
mbed_official 324:406fd2029f23 1496 uint8_t MWUF6 : 1; /*!< [6] Wakeup flag For module 6 */
mbed_official 324:406fd2029f23 1497 uint8_t MWUF7 : 1; /*!< [7] Wakeup flag For module 7 */
mbed_official 324:406fd2029f23 1498 } B;
mbed_official 324:406fd2029f23 1499 } hw_llwu_f3_t;
mbed_official 324:406fd2029f23 1500
mbed_official 324:406fd2029f23 1501 /*!
mbed_official 324:406fd2029f23 1502 * @name Constants and macros for entire LLWU_F3 register
mbed_official 324:406fd2029f23 1503 */
mbed_official 324:406fd2029f23 1504 /*@{*/
mbed_official 324:406fd2029f23 1505 #define HW_LLWU_F3_ADDR(x) ((x) + 0x7U)
mbed_official 324:406fd2029f23 1506
mbed_official 324:406fd2029f23 1507 #define HW_LLWU_F3(x) (*(__I hw_llwu_f3_t *) HW_LLWU_F3_ADDR(x))
mbed_official 324:406fd2029f23 1508 #define HW_LLWU_F3_RD(x) (HW_LLWU_F3(x).U)
mbed_official 324:406fd2029f23 1509 /*@}*/
mbed_official 324:406fd2029f23 1510
mbed_official 324:406fd2029f23 1511 /*
mbed_official 324:406fd2029f23 1512 * Constants & macros for individual LLWU_F3 bitfields
mbed_official 324:406fd2029f23 1513 */
mbed_official 324:406fd2029f23 1514
mbed_official 324:406fd2029f23 1515 /*!
mbed_official 324:406fd2029f23 1516 * @name Register LLWU_F3, field MWUF0[0] (RO)
mbed_official 324:406fd2029f23 1517 *
mbed_official 324:406fd2029f23 1518 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1519 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1520 * clearing mechanism.
mbed_official 324:406fd2029f23 1521 *
mbed_official 324:406fd2029f23 1522 * Values:
mbed_official 324:406fd2029f23 1523 * - 0 - Module 0 input was not a wakeup source
mbed_official 324:406fd2029f23 1524 * - 1 - Module 0 input was a wakeup source
mbed_official 324:406fd2029f23 1525 */
mbed_official 324:406fd2029f23 1526 /*@{*/
mbed_official 324:406fd2029f23 1527 #define BP_LLWU_F3_MWUF0 (0U) /*!< Bit position for LLWU_F3_MWUF0. */
mbed_official 324:406fd2029f23 1528 #define BM_LLWU_F3_MWUF0 (0x01U) /*!< Bit mask for LLWU_F3_MWUF0. */
mbed_official 324:406fd2029f23 1529 #define BS_LLWU_F3_MWUF0 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF0. */
mbed_official 324:406fd2029f23 1530
mbed_official 324:406fd2029f23 1531 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
mbed_official 324:406fd2029f23 1532 #define BR_LLWU_F3_MWUF0(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF0))
mbed_official 324:406fd2029f23 1533 /*@}*/
mbed_official 324:406fd2029f23 1534
mbed_official 324:406fd2029f23 1535 /*!
mbed_official 324:406fd2029f23 1536 * @name Register LLWU_F3, field MWUF1[1] (RO)
mbed_official 324:406fd2029f23 1537 *
mbed_official 324:406fd2029f23 1538 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1539 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1540 * clearing mechanism.
mbed_official 324:406fd2029f23 1541 *
mbed_official 324:406fd2029f23 1542 * Values:
mbed_official 324:406fd2029f23 1543 * - 0 - Module 1 input was not a wakeup source
mbed_official 324:406fd2029f23 1544 * - 1 - Module 1 input was a wakeup source
mbed_official 324:406fd2029f23 1545 */
mbed_official 324:406fd2029f23 1546 /*@{*/
mbed_official 324:406fd2029f23 1547 #define BP_LLWU_F3_MWUF1 (1U) /*!< Bit position for LLWU_F3_MWUF1. */
mbed_official 324:406fd2029f23 1548 #define BM_LLWU_F3_MWUF1 (0x02U) /*!< Bit mask for LLWU_F3_MWUF1. */
mbed_official 324:406fd2029f23 1549 #define BS_LLWU_F3_MWUF1 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF1. */
mbed_official 324:406fd2029f23 1550
mbed_official 324:406fd2029f23 1551 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
mbed_official 324:406fd2029f23 1552 #define BR_LLWU_F3_MWUF1(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF1))
mbed_official 324:406fd2029f23 1553 /*@}*/
mbed_official 324:406fd2029f23 1554
mbed_official 324:406fd2029f23 1555 /*!
mbed_official 324:406fd2029f23 1556 * @name Register LLWU_F3, field MWUF2[2] (RO)
mbed_official 324:406fd2029f23 1557 *
mbed_official 324:406fd2029f23 1558 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1559 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1560 * clearing mechanism.
mbed_official 324:406fd2029f23 1561 *
mbed_official 324:406fd2029f23 1562 * Values:
mbed_official 324:406fd2029f23 1563 * - 0 - Module 2 input was not a wakeup source
mbed_official 324:406fd2029f23 1564 * - 1 - Module 2 input was a wakeup source
mbed_official 324:406fd2029f23 1565 */
mbed_official 324:406fd2029f23 1566 /*@{*/
mbed_official 324:406fd2029f23 1567 #define BP_LLWU_F3_MWUF2 (2U) /*!< Bit position for LLWU_F3_MWUF2. */
mbed_official 324:406fd2029f23 1568 #define BM_LLWU_F3_MWUF2 (0x04U) /*!< Bit mask for LLWU_F3_MWUF2. */
mbed_official 324:406fd2029f23 1569 #define BS_LLWU_F3_MWUF2 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF2. */
mbed_official 324:406fd2029f23 1570
mbed_official 324:406fd2029f23 1571 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
mbed_official 324:406fd2029f23 1572 #define BR_LLWU_F3_MWUF2(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF2))
mbed_official 324:406fd2029f23 1573 /*@}*/
mbed_official 324:406fd2029f23 1574
mbed_official 324:406fd2029f23 1575 /*!
mbed_official 324:406fd2029f23 1576 * @name Register LLWU_F3, field MWUF3[3] (RO)
mbed_official 324:406fd2029f23 1577 *
mbed_official 324:406fd2029f23 1578 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1579 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1580 * clearing mechanism.
mbed_official 324:406fd2029f23 1581 *
mbed_official 324:406fd2029f23 1582 * Values:
mbed_official 324:406fd2029f23 1583 * - 0 - Module 3 input was not a wakeup source
mbed_official 324:406fd2029f23 1584 * - 1 - Module 3 input was a wakeup source
mbed_official 324:406fd2029f23 1585 */
mbed_official 324:406fd2029f23 1586 /*@{*/
mbed_official 324:406fd2029f23 1587 #define BP_LLWU_F3_MWUF3 (3U) /*!< Bit position for LLWU_F3_MWUF3. */
mbed_official 324:406fd2029f23 1588 #define BM_LLWU_F3_MWUF3 (0x08U) /*!< Bit mask for LLWU_F3_MWUF3. */
mbed_official 324:406fd2029f23 1589 #define BS_LLWU_F3_MWUF3 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF3. */
mbed_official 324:406fd2029f23 1590
mbed_official 324:406fd2029f23 1591 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
mbed_official 324:406fd2029f23 1592 #define BR_LLWU_F3_MWUF3(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF3))
mbed_official 324:406fd2029f23 1593 /*@}*/
mbed_official 324:406fd2029f23 1594
mbed_official 324:406fd2029f23 1595 /*!
mbed_official 324:406fd2029f23 1596 * @name Register LLWU_F3, field MWUF4[4] (RO)
mbed_official 324:406fd2029f23 1597 *
mbed_official 324:406fd2029f23 1598 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1599 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1600 * clearing mechanism.
mbed_official 324:406fd2029f23 1601 *
mbed_official 324:406fd2029f23 1602 * Values:
mbed_official 324:406fd2029f23 1603 * - 0 - Module 4 input was not a wakeup source
mbed_official 324:406fd2029f23 1604 * - 1 - Module 4 input was a wakeup source
mbed_official 324:406fd2029f23 1605 */
mbed_official 324:406fd2029f23 1606 /*@{*/
mbed_official 324:406fd2029f23 1607 #define BP_LLWU_F3_MWUF4 (4U) /*!< Bit position for LLWU_F3_MWUF4. */
mbed_official 324:406fd2029f23 1608 #define BM_LLWU_F3_MWUF4 (0x10U) /*!< Bit mask for LLWU_F3_MWUF4. */
mbed_official 324:406fd2029f23 1609 #define BS_LLWU_F3_MWUF4 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF4. */
mbed_official 324:406fd2029f23 1610
mbed_official 324:406fd2029f23 1611 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
mbed_official 324:406fd2029f23 1612 #define BR_LLWU_F3_MWUF4(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF4))
mbed_official 324:406fd2029f23 1613 /*@}*/
mbed_official 324:406fd2029f23 1614
mbed_official 324:406fd2029f23 1615 /*!
mbed_official 324:406fd2029f23 1616 * @name Register LLWU_F3, field MWUF5[5] (RO)
mbed_official 324:406fd2029f23 1617 *
mbed_official 324:406fd2029f23 1618 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1619 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1620 * clearing mechanism.
mbed_official 324:406fd2029f23 1621 *
mbed_official 324:406fd2029f23 1622 * Values:
mbed_official 324:406fd2029f23 1623 * - 0 - Module 5 input was not a wakeup source
mbed_official 324:406fd2029f23 1624 * - 1 - Module 5 input was a wakeup source
mbed_official 324:406fd2029f23 1625 */
mbed_official 324:406fd2029f23 1626 /*@{*/
mbed_official 324:406fd2029f23 1627 #define BP_LLWU_F3_MWUF5 (5U) /*!< Bit position for LLWU_F3_MWUF5. */
mbed_official 324:406fd2029f23 1628 #define BM_LLWU_F3_MWUF5 (0x20U) /*!< Bit mask for LLWU_F3_MWUF5. */
mbed_official 324:406fd2029f23 1629 #define BS_LLWU_F3_MWUF5 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF5. */
mbed_official 324:406fd2029f23 1630
mbed_official 324:406fd2029f23 1631 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
mbed_official 324:406fd2029f23 1632 #define BR_LLWU_F3_MWUF5(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF5))
mbed_official 324:406fd2029f23 1633 /*@}*/
mbed_official 324:406fd2029f23 1634
mbed_official 324:406fd2029f23 1635 /*!
mbed_official 324:406fd2029f23 1636 * @name Register LLWU_F3, field MWUF6[6] (RO)
mbed_official 324:406fd2029f23 1637 *
mbed_official 324:406fd2029f23 1638 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1639 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1640 * clearing mechanism.
mbed_official 324:406fd2029f23 1641 *
mbed_official 324:406fd2029f23 1642 * Values:
mbed_official 324:406fd2029f23 1643 * - 0 - Module 6 input was not a wakeup source
mbed_official 324:406fd2029f23 1644 * - 1 - Module 6 input was a wakeup source
mbed_official 324:406fd2029f23 1645 */
mbed_official 324:406fd2029f23 1646 /*@{*/
mbed_official 324:406fd2029f23 1647 #define BP_LLWU_F3_MWUF6 (6U) /*!< Bit position for LLWU_F3_MWUF6. */
mbed_official 324:406fd2029f23 1648 #define BM_LLWU_F3_MWUF6 (0x40U) /*!< Bit mask for LLWU_F3_MWUF6. */
mbed_official 324:406fd2029f23 1649 #define BS_LLWU_F3_MWUF6 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF6. */
mbed_official 324:406fd2029f23 1650
mbed_official 324:406fd2029f23 1651 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
mbed_official 324:406fd2029f23 1652 #define BR_LLWU_F3_MWUF6(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF6))
mbed_official 324:406fd2029f23 1653 /*@}*/
mbed_official 324:406fd2029f23 1654
mbed_official 324:406fd2029f23 1655 /*!
mbed_official 324:406fd2029f23 1656 * @name Register LLWU_F3, field MWUF7[7] (RO)
mbed_official 324:406fd2029f23 1657 *
mbed_official 324:406fd2029f23 1658 * Indicates that an enabled internal peripheral was a source of exiting a
mbed_official 324:406fd2029f23 1659 * low-leakage power mode. To clear the flag, follow the internal peripheral flag
mbed_official 324:406fd2029f23 1660 * clearing mechanism.
mbed_official 324:406fd2029f23 1661 *
mbed_official 324:406fd2029f23 1662 * Values:
mbed_official 324:406fd2029f23 1663 * - 0 - Module 7 input was not a wakeup source
mbed_official 324:406fd2029f23 1664 * - 1 - Module 7 input was a wakeup source
mbed_official 324:406fd2029f23 1665 */
mbed_official 324:406fd2029f23 1666 /*@{*/
mbed_official 324:406fd2029f23 1667 #define BP_LLWU_F3_MWUF7 (7U) /*!< Bit position for LLWU_F3_MWUF7. */
mbed_official 324:406fd2029f23 1668 #define BM_LLWU_F3_MWUF7 (0x80U) /*!< Bit mask for LLWU_F3_MWUF7. */
mbed_official 324:406fd2029f23 1669 #define BS_LLWU_F3_MWUF7 (1U) /*!< Bit field size in bits for LLWU_F3_MWUF7. */
mbed_official 324:406fd2029f23 1670
mbed_official 324:406fd2029f23 1671 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
mbed_official 324:406fd2029f23 1672 #define BR_LLWU_F3_MWUF7(x) (BITBAND_ACCESS8(HW_LLWU_F3_ADDR(x), BP_LLWU_F3_MWUF7))
mbed_official 324:406fd2029f23 1673 /*@}*/
mbed_official 324:406fd2029f23 1674
mbed_official 324:406fd2029f23 1675 /*******************************************************************************
mbed_official 324:406fd2029f23 1676 * HW_LLWU_FILT1 - LLWU Pin Filter 1 register
mbed_official 324:406fd2029f23 1677 ******************************************************************************/
mbed_official 324:406fd2029f23 1678
mbed_official 324:406fd2029f23 1679 /*!
mbed_official 324:406fd2029f23 1680 * @brief HW_LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
mbed_official 324:406fd2029f23 1681 *
mbed_official 324:406fd2029f23 1682 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1683 *
mbed_official 324:406fd2029f23 1684 * LLWU_FILT1 is a control and status register that is used to enable/disable
mbed_official 324:406fd2029f23 1685 * the digital filter 1 features for an external pin. This register is reset on
mbed_official 324:406fd2029f23 1686 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 1687 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 1688 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 324:406fd2029f23 1689 * Module (RCM). The RCM implements many of the reset functions for the chip. See
mbed_official 324:406fd2029f23 1690 * the chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 1691 */
mbed_official 324:406fd2029f23 1692 typedef union _hw_llwu_filt1
mbed_official 324:406fd2029f23 1693 {
mbed_official 324:406fd2029f23 1694 uint8_t U;
mbed_official 324:406fd2029f23 1695 struct _hw_llwu_filt1_bitfields
mbed_official 324:406fd2029f23 1696 {
mbed_official 324:406fd2029f23 1697 uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */
mbed_official 324:406fd2029f23 1698 uint8_t RESERVED0 : 1; /*!< [4] */
mbed_official 324:406fd2029f23 1699 uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */
mbed_official 324:406fd2029f23 1700 uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */
mbed_official 324:406fd2029f23 1701 } B;
mbed_official 324:406fd2029f23 1702 } hw_llwu_filt1_t;
mbed_official 324:406fd2029f23 1703
mbed_official 324:406fd2029f23 1704 /*!
mbed_official 324:406fd2029f23 1705 * @name Constants and macros for entire LLWU_FILT1 register
mbed_official 324:406fd2029f23 1706 */
mbed_official 324:406fd2029f23 1707 /*@{*/
mbed_official 324:406fd2029f23 1708 #define HW_LLWU_FILT1_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 1709
mbed_official 324:406fd2029f23 1710 #define HW_LLWU_FILT1(x) (*(__IO hw_llwu_filt1_t *) HW_LLWU_FILT1_ADDR(x))
mbed_official 324:406fd2029f23 1711 #define HW_LLWU_FILT1_RD(x) (HW_LLWU_FILT1(x).U)
mbed_official 324:406fd2029f23 1712 #define HW_LLWU_FILT1_WR(x, v) (HW_LLWU_FILT1(x).U = (v))
mbed_official 324:406fd2029f23 1713 #define HW_LLWU_FILT1_SET(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) | (v)))
mbed_official 324:406fd2029f23 1714 #define HW_LLWU_FILT1_CLR(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1715 #define HW_LLWU_FILT1_TOG(x, v) (HW_LLWU_FILT1_WR(x, HW_LLWU_FILT1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1716 /*@}*/
mbed_official 324:406fd2029f23 1717
mbed_official 324:406fd2029f23 1718 /*
mbed_official 324:406fd2029f23 1719 * Constants & macros for individual LLWU_FILT1 bitfields
mbed_official 324:406fd2029f23 1720 */
mbed_official 324:406fd2029f23 1721
mbed_official 324:406fd2029f23 1722 /*!
mbed_official 324:406fd2029f23 1723 * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
mbed_official 324:406fd2029f23 1724 *
mbed_official 324:406fd2029f23 1725 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
mbed_official 324:406fd2029f23 1726 *
mbed_official 324:406fd2029f23 1727 * Values:
mbed_official 324:406fd2029f23 1728 * - 0000 - Select LLWU_P0 for filter
mbed_official 324:406fd2029f23 1729 * - 1111 - Select LLWU_P15 for filter
mbed_official 324:406fd2029f23 1730 */
mbed_official 324:406fd2029f23 1731 /*@{*/
mbed_official 324:406fd2029f23 1732 #define BP_LLWU_FILT1_FILTSEL (0U) /*!< Bit position for LLWU_FILT1_FILTSEL. */
mbed_official 324:406fd2029f23 1733 #define BM_LLWU_FILT1_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT1_FILTSEL. */
mbed_official 324:406fd2029f23 1734 #define BS_LLWU_FILT1_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT1_FILTSEL. */
mbed_official 324:406fd2029f23 1735
mbed_official 324:406fd2029f23 1736 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
mbed_official 324:406fd2029f23 1737 #define BR_LLWU_FILT1_FILTSEL(x) (HW_LLWU_FILT1(x).B.FILTSEL)
mbed_official 324:406fd2029f23 1738
mbed_official 324:406fd2029f23 1739 /*! @brief Format value for bitfield LLWU_FILT1_FILTSEL. */
mbed_official 324:406fd2029f23 1740 #define BF_LLWU_FILT1_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTSEL) & BM_LLWU_FILT1_FILTSEL)
mbed_official 324:406fd2029f23 1741
mbed_official 324:406fd2029f23 1742 /*! @brief Set the FILTSEL field to a new value. */
mbed_official 324:406fd2029f23 1743 #define BW_LLWU_FILT1_FILTSEL(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTSEL) | BF_LLWU_FILT1_FILTSEL(v)))
mbed_official 324:406fd2029f23 1744 /*@}*/
mbed_official 324:406fd2029f23 1745
mbed_official 324:406fd2029f23 1746 /*!
mbed_official 324:406fd2029f23 1747 * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
mbed_official 324:406fd2029f23 1748 *
mbed_official 324:406fd2029f23 1749 * Controls the digital filter options for the external pin detect.
mbed_official 324:406fd2029f23 1750 *
mbed_official 324:406fd2029f23 1751 * Values:
mbed_official 324:406fd2029f23 1752 * - 00 - Filter disabled
mbed_official 324:406fd2029f23 1753 * - 01 - Filter posedge detect enabled
mbed_official 324:406fd2029f23 1754 * - 10 - Filter negedge detect enabled
mbed_official 324:406fd2029f23 1755 * - 11 - Filter any edge detect enabled
mbed_official 324:406fd2029f23 1756 */
mbed_official 324:406fd2029f23 1757 /*@{*/
mbed_official 324:406fd2029f23 1758 #define BP_LLWU_FILT1_FILTE (5U) /*!< Bit position for LLWU_FILT1_FILTE. */
mbed_official 324:406fd2029f23 1759 #define BM_LLWU_FILT1_FILTE (0x60U) /*!< Bit mask for LLWU_FILT1_FILTE. */
mbed_official 324:406fd2029f23 1760 #define BS_LLWU_FILT1_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT1_FILTE. */
mbed_official 324:406fd2029f23 1761
mbed_official 324:406fd2029f23 1762 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
mbed_official 324:406fd2029f23 1763 #define BR_LLWU_FILT1_FILTE(x) (HW_LLWU_FILT1(x).B.FILTE)
mbed_official 324:406fd2029f23 1764
mbed_official 324:406fd2029f23 1765 /*! @brief Format value for bitfield LLWU_FILT1_FILTE. */
mbed_official 324:406fd2029f23 1766 #define BF_LLWU_FILT1_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTE) & BM_LLWU_FILT1_FILTE)
mbed_official 324:406fd2029f23 1767
mbed_official 324:406fd2029f23 1768 /*! @brief Set the FILTE field to a new value. */
mbed_official 324:406fd2029f23 1769 #define BW_LLWU_FILT1_FILTE(x, v) (HW_LLWU_FILT1_WR(x, (HW_LLWU_FILT1_RD(x) & ~BM_LLWU_FILT1_FILTE) | BF_LLWU_FILT1_FILTE(v)))
mbed_official 324:406fd2029f23 1770 /*@}*/
mbed_official 324:406fd2029f23 1771
mbed_official 324:406fd2029f23 1772 /*!
mbed_official 324:406fd2029f23 1773 * @name Register LLWU_FILT1, field FILTF[7] (W1C)
mbed_official 324:406fd2029f23 1774 *
mbed_official 324:406fd2029f23 1775 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
mbed_official 324:406fd2029f23 1776 * source of exiting a low-leakage power mode. To clear the flag write a one to
mbed_official 324:406fd2029f23 1777 * FILTF.
mbed_official 324:406fd2029f23 1778 *
mbed_official 324:406fd2029f23 1779 * Values:
mbed_official 324:406fd2029f23 1780 * - 0 - Pin Filter 1 was not a wakeup source
mbed_official 324:406fd2029f23 1781 * - 1 - Pin Filter 1 was a wakeup source
mbed_official 324:406fd2029f23 1782 */
mbed_official 324:406fd2029f23 1783 /*@{*/
mbed_official 324:406fd2029f23 1784 #define BP_LLWU_FILT1_FILTF (7U) /*!< Bit position for LLWU_FILT1_FILTF. */
mbed_official 324:406fd2029f23 1785 #define BM_LLWU_FILT1_FILTF (0x80U) /*!< Bit mask for LLWU_FILT1_FILTF. */
mbed_official 324:406fd2029f23 1786 #define BS_LLWU_FILT1_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT1_FILTF. */
mbed_official 324:406fd2029f23 1787
mbed_official 324:406fd2029f23 1788 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
mbed_official 324:406fd2029f23 1789 #define BR_LLWU_FILT1_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF))
mbed_official 324:406fd2029f23 1790
mbed_official 324:406fd2029f23 1791 /*! @brief Format value for bitfield LLWU_FILT1_FILTF. */
mbed_official 324:406fd2029f23 1792 #define BF_LLWU_FILT1_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT1_FILTF) & BM_LLWU_FILT1_FILTF)
mbed_official 324:406fd2029f23 1793
mbed_official 324:406fd2029f23 1794 /*! @brief Set the FILTF field to a new value. */
mbed_official 324:406fd2029f23 1795 #define BW_LLWU_FILT1_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT1_ADDR(x), BP_LLWU_FILT1_FILTF) = (v))
mbed_official 324:406fd2029f23 1796 /*@}*/
mbed_official 324:406fd2029f23 1797
mbed_official 324:406fd2029f23 1798 /*******************************************************************************
mbed_official 324:406fd2029f23 1799 * HW_LLWU_FILT2 - LLWU Pin Filter 2 register
mbed_official 324:406fd2029f23 1800 ******************************************************************************/
mbed_official 324:406fd2029f23 1801
mbed_official 324:406fd2029f23 1802 /*!
mbed_official 324:406fd2029f23 1803 * @brief HW_LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
mbed_official 324:406fd2029f23 1804 *
mbed_official 324:406fd2029f23 1805 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1806 *
mbed_official 324:406fd2029f23 1807 * LLWU_FILT2 is a control and status register that is used to enable/disable
mbed_official 324:406fd2029f23 1808 * the digital filter 2 features for an external pin. This register is reset on
mbed_official 324:406fd2029f23 1809 * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
mbed_official 324:406fd2029f23 1810 * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
mbed_official 324:406fd2029f23 1811 * IntroductionInformation found here describes the registers of the Reset Control
mbed_official 324:406fd2029f23 1812 * Module (RCM). The RCM implements many of the reset functions for the chip. See
mbed_official 324:406fd2029f23 1813 * the chip's reset chapter for more information. details for more information.
mbed_official 324:406fd2029f23 1814 */
mbed_official 324:406fd2029f23 1815 typedef union _hw_llwu_filt2
mbed_official 324:406fd2029f23 1816 {
mbed_official 324:406fd2029f23 1817 uint8_t U;
mbed_official 324:406fd2029f23 1818 struct _hw_llwu_filt2_bitfields
mbed_official 324:406fd2029f23 1819 {
mbed_official 324:406fd2029f23 1820 uint8_t FILTSEL : 4; /*!< [3:0] Filter Pin Select */
mbed_official 324:406fd2029f23 1821 uint8_t RESERVED0 : 1; /*!< [4] */
mbed_official 324:406fd2029f23 1822 uint8_t FILTE : 2; /*!< [6:5] Digital Filter On External Pin */
mbed_official 324:406fd2029f23 1823 uint8_t FILTF : 1; /*!< [7] Filter Detect Flag */
mbed_official 324:406fd2029f23 1824 } B;
mbed_official 324:406fd2029f23 1825 } hw_llwu_filt2_t;
mbed_official 324:406fd2029f23 1826
mbed_official 324:406fd2029f23 1827 /*!
mbed_official 324:406fd2029f23 1828 * @name Constants and macros for entire LLWU_FILT2 register
mbed_official 324:406fd2029f23 1829 */
mbed_official 324:406fd2029f23 1830 /*@{*/
mbed_official 324:406fd2029f23 1831 #define HW_LLWU_FILT2_ADDR(x) ((x) + 0x9U)
mbed_official 324:406fd2029f23 1832
mbed_official 324:406fd2029f23 1833 #define HW_LLWU_FILT2(x) (*(__IO hw_llwu_filt2_t *) HW_LLWU_FILT2_ADDR(x))
mbed_official 324:406fd2029f23 1834 #define HW_LLWU_FILT2_RD(x) (HW_LLWU_FILT2(x).U)
mbed_official 324:406fd2029f23 1835 #define HW_LLWU_FILT2_WR(x, v) (HW_LLWU_FILT2(x).U = (v))
mbed_official 324:406fd2029f23 1836 #define HW_LLWU_FILT2_SET(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) | (v)))
mbed_official 324:406fd2029f23 1837 #define HW_LLWU_FILT2_CLR(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1838 #define HW_LLWU_FILT2_TOG(x, v) (HW_LLWU_FILT2_WR(x, HW_LLWU_FILT2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1839 /*@}*/
mbed_official 324:406fd2029f23 1840
mbed_official 324:406fd2029f23 1841 /*
mbed_official 324:406fd2029f23 1842 * Constants & macros for individual LLWU_FILT2 bitfields
mbed_official 324:406fd2029f23 1843 */
mbed_official 324:406fd2029f23 1844
mbed_official 324:406fd2029f23 1845 /*!
mbed_official 324:406fd2029f23 1846 * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
mbed_official 324:406fd2029f23 1847 *
mbed_official 324:406fd2029f23 1848 * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
mbed_official 324:406fd2029f23 1849 *
mbed_official 324:406fd2029f23 1850 * Values:
mbed_official 324:406fd2029f23 1851 * - 0000 - Select LLWU_P0 for filter
mbed_official 324:406fd2029f23 1852 * - 1111 - Select LLWU_P15 for filter
mbed_official 324:406fd2029f23 1853 */
mbed_official 324:406fd2029f23 1854 /*@{*/
mbed_official 324:406fd2029f23 1855 #define BP_LLWU_FILT2_FILTSEL (0U) /*!< Bit position for LLWU_FILT2_FILTSEL. */
mbed_official 324:406fd2029f23 1856 #define BM_LLWU_FILT2_FILTSEL (0x0FU) /*!< Bit mask for LLWU_FILT2_FILTSEL. */
mbed_official 324:406fd2029f23 1857 #define BS_LLWU_FILT2_FILTSEL (4U) /*!< Bit field size in bits for LLWU_FILT2_FILTSEL. */
mbed_official 324:406fd2029f23 1858
mbed_official 324:406fd2029f23 1859 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
mbed_official 324:406fd2029f23 1860 #define BR_LLWU_FILT2_FILTSEL(x) (HW_LLWU_FILT2(x).B.FILTSEL)
mbed_official 324:406fd2029f23 1861
mbed_official 324:406fd2029f23 1862 /*! @brief Format value for bitfield LLWU_FILT2_FILTSEL. */
mbed_official 324:406fd2029f23 1863 #define BF_LLWU_FILT2_FILTSEL(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTSEL) & BM_LLWU_FILT2_FILTSEL)
mbed_official 324:406fd2029f23 1864
mbed_official 324:406fd2029f23 1865 /*! @brief Set the FILTSEL field to a new value. */
mbed_official 324:406fd2029f23 1866 #define BW_LLWU_FILT2_FILTSEL(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTSEL) | BF_LLWU_FILT2_FILTSEL(v)))
mbed_official 324:406fd2029f23 1867 /*@}*/
mbed_official 324:406fd2029f23 1868
mbed_official 324:406fd2029f23 1869 /*!
mbed_official 324:406fd2029f23 1870 * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
mbed_official 324:406fd2029f23 1871 *
mbed_official 324:406fd2029f23 1872 * Controls the digital filter options for the external pin detect.
mbed_official 324:406fd2029f23 1873 *
mbed_official 324:406fd2029f23 1874 * Values:
mbed_official 324:406fd2029f23 1875 * - 00 - Filter disabled
mbed_official 324:406fd2029f23 1876 * - 01 - Filter posedge detect enabled
mbed_official 324:406fd2029f23 1877 * - 10 - Filter negedge detect enabled
mbed_official 324:406fd2029f23 1878 * - 11 - Filter any edge detect enabled
mbed_official 324:406fd2029f23 1879 */
mbed_official 324:406fd2029f23 1880 /*@{*/
mbed_official 324:406fd2029f23 1881 #define BP_LLWU_FILT2_FILTE (5U) /*!< Bit position for LLWU_FILT2_FILTE. */
mbed_official 324:406fd2029f23 1882 #define BM_LLWU_FILT2_FILTE (0x60U) /*!< Bit mask for LLWU_FILT2_FILTE. */
mbed_official 324:406fd2029f23 1883 #define BS_LLWU_FILT2_FILTE (2U) /*!< Bit field size in bits for LLWU_FILT2_FILTE. */
mbed_official 324:406fd2029f23 1884
mbed_official 324:406fd2029f23 1885 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
mbed_official 324:406fd2029f23 1886 #define BR_LLWU_FILT2_FILTE(x) (HW_LLWU_FILT2(x).B.FILTE)
mbed_official 324:406fd2029f23 1887
mbed_official 324:406fd2029f23 1888 /*! @brief Format value for bitfield LLWU_FILT2_FILTE. */
mbed_official 324:406fd2029f23 1889 #define BF_LLWU_FILT2_FILTE(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTE) & BM_LLWU_FILT2_FILTE)
mbed_official 324:406fd2029f23 1890
mbed_official 324:406fd2029f23 1891 /*! @brief Set the FILTE field to a new value. */
mbed_official 324:406fd2029f23 1892 #define BW_LLWU_FILT2_FILTE(x, v) (HW_LLWU_FILT2_WR(x, (HW_LLWU_FILT2_RD(x) & ~BM_LLWU_FILT2_FILTE) | BF_LLWU_FILT2_FILTE(v)))
mbed_official 324:406fd2029f23 1893 /*@}*/
mbed_official 324:406fd2029f23 1894
mbed_official 324:406fd2029f23 1895 /*!
mbed_official 324:406fd2029f23 1896 * @name Register LLWU_FILT2, field FILTF[7] (W1C)
mbed_official 324:406fd2029f23 1897 *
mbed_official 324:406fd2029f23 1898 * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
mbed_official 324:406fd2029f23 1899 * source of exiting a low-leakage power mode. To clear the flag write a one to
mbed_official 324:406fd2029f23 1900 * FILTF.
mbed_official 324:406fd2029f23 1901 *
mbed_official 324:406fd2029f23 1902 * Values:
mbed_official 324:406fd2029f23 1903 * - 0 - Pin Filter 2 was not a wakeup source
mbed_official 324:406fd2029f23 1904 * - 1 - Pin Filter 2 was a wakeup source
mbed_official 324:406fd2029f23 1905 */
mbed_official 324:406fd2029f23 1906 /*@{*/
mbed_official 324:406fd2029f23 1907 #define BP_LLWU_FILT2_FILTF (7U) /*!< Bit position for LLWU_FILT2_FILTF. */
mbed_official 324:406fd2029f23 1908 #define BM_LLWU_FILT2_FILTF (0x80U) /*!< Bit mask for LLWU_FILT2_FILTF. */
mbed_official 324:406fd2029f23 1909 #define BS_LLWU_FILT2_FILTF (1U) /*!< Bit field size in bits for LLWU_FILT2_FILTF. */
mbed_official 324:406fd2029f23 1910
mbed_official 324:406fd2029f23 1911 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
mbed_official 324:406fd2029f23 1912 #define BR_LLWU_FILT2_FILTF(x) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF))
mbed_official 324:406fd2029f23 1913
mbed_official 324:406fd2029f23 1914 /*! @brief Format value for bitfield LLWU_FILT2_FILTF. */
mbed_official 324:406fd2029f23 1915 #define BF_LLWU_FILT2_FILTF(v) ((uint8_t)((uint8_t)(v) << BP_LLWU_FILT2_FILTF) & BM_LLWU_FILT2_FILTF)
mbed_official 324:406fd2029f23 1916
mbed_official 324:406fd2029f23 1917 /*! @brief Set the FILTF field to a new value. */
mbed_official 324:406fd2029f23 1918 #define BW_LLWU_FILT2_FILTF(x, v) (BITBAND_ACCESS8(HW_LLWU_FILT2_ADDR(x), BP_LLWU_FILT2_FILTF) = (v))
mbed_official 324:406fd2029f23 1919 /*@}*/
mbed_official 324:406fd2029f23 1920
mbed_official 324:406fd2029f23 1921 /*******************************************************************************
mbed_official 324:406fd2029f23 1922 * hw_llwu_t - module struct
mbed_official 324:406fd2029f23 1923 ******************************************************************************/
mbed_official 324:406fd2029f23 1924 /*!
mbed_official 324:406fd2029f23 1925 * @brief All LLWU module registers.
mbed_official 324:406fd2029f23 1926 */
mbed_official 324:406fd2029f23 1927 #pragma pack(1)
mbed_official 324:406fd2029f23 1928 typedef struct _hw_llwu
mbed_official 324:406fd2029f23 1929 {
mbed_official 324:406fd2029f23 1930 __IO hw_llwu_pe1_t PE1; /*!< [0x0] LLWU Pin Enable 1 register */
mbed_official 324:406fd2029f23 1931 __IO hw_llwu_pe2_t PE2; /*!< [0x1] LLWU Pin Enable 2 register */
mbed_official 324:406fd2029f23 1932 __IO hw_llwu_pe3_t PE3; /*!< [0x2] LLWU Pin Enable 3 register */
mbed_official 324:406fd2029f23 1933 __IO hw_llwu_pe4_t PE4; /*!< [0x3] LLWU Pin Enable 4 register */
mbed_official 324:406fd2029f23 1934 __IO hw_llwu_me_t ME; /*!< [0x4] LLWU Module Enable register */
mbed_official 324:406fd2029f23 1935 __IO hw_llwu_f1_t F1; /*!< [0x5] LLWU Flag 1 register */
mbed_official 324:406fd2029f23 1936 __IO hw_llwu_f2_t F2; /*!< [0x6] LLWU Flag 2 register */
mbed_official 324:406fd2029f23 1937 __I hw_llwu_f3_t F3; /*!< [0x7] LLWU Flag 3 register */
mbed_official 324:406fd2029f23 1938 __IO hw_llwu_filt1_t FILT1; /*!< [0x8] LLWU Pin Filter 1 register */
mbed_official 324:406fd2029f23 1939 __IO hw_llwu_filt2_t FILT2; /*!< [0x9] LLWU Pin Filter 2 register */
mbed_official 324:406fd2029f23 1940 } hw_llwu_t;
mbed_official 324:406fd2029f23 1941 #pragma pack()
mbed_official 324:406fd2029f23 1942
mbed_official 324:406fd2029f23 1943 /*! @brief Macro to access all LLWU registers. */
mbed_official 324:406fd2029f23 1944 /*! @param x LLWU module instance base address. */
mbed_official 324:406fd2029f23 1945 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 1946 * use the '&' operator, like <code>&HW_LLWU(LLWU_BASE)</code>. */
mbed_official 324:406fd2029f23 1947 #define HW_LLWU(x) (*(hw_llwu_t *)(x))
mbed_official 324:406fd2029f23 1948
mbed_official 324:406fd2029f23 1949 #endif /* __HW_LLWU_REGISTERS_H__ */
mbed_official 324:406fd2029f23 1950 /* EOF */