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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_i2s.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_I2S_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_I2S_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 I2S
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Inter-IC Sound / Synchronous Audio Interface
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_I2S_TCSR - SAI Transmit Control Register
mbed_official 324:406fd2029f23 90 * - HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
mbed_official 324:406fd2029f23 91 * - HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
mbed_official 324:406fd2029f23 92 * - HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
mbed_official 324:406fd2029f23 93 * - HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
mbed_official 324:406fd2029f23 94 * - HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
mbed_official 324:406fd2029f23 95 * - HW_I2S_TDRn - SAI Transmit Data Register
mbed_official 324:406fd2029f23 96 * - HW_I2S_TFRn - SAI Transmit FIFO Register
mbed_official 324:406fd2029f23 97 * - HW_I2S_TMR - SAI Transmit Mask Register
mbed_official 324:406fd2029f23 98 * - HW_I2S_RCSR - SAI Receive Control Register
mbed_official 324:406fd2029f23 99 * - HW_I2S_RCR1 - SAI Receive Configuration 1 Register
mbed_official 324:406fd2029f23 100 * - HW_I2S_RCR2 - SAI Receive Configuration 2 Register
mbed_official 324:406fd2029f23 101 * - HW_I2S_RCR3 - SAI Receive Configuration 3 Register
mbed_official 324:406fd2029f23 102 * - HW_I2S_RCR4 - SAI Receive Configuration 4 Register
mbed_official 324:406fd2029f23 103 * - HW_I2S_RCR5 - SAI Receive Configuration 5 Register
mbed_official 324:406fd2029f23 104 * - HW_I2S_RDRn - SAI Receive Data Register
mbed_official 324:406fd2029f23 105 * - HW_I2S_RFRn - SAI Receive FIFO Register
mbed_official 324:406fd2029f23 106 * - HW_I2S_RMR - SAI Receive Mask Register
mbed_official 324:406fd2029f23 107 * - HW_I2S_MCR - SAI MCLK Control Register
mbed_official 324:406fd2029f23 108 * - HW_I2S_MDR - SAI MCLK Divide Register
mbed_official 324:406fd2029f23 109 *
mbed_official 324:406fd2029f23 110 * - hw_i2s_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 111 */
mbed_official 324:406fd2029f23 112
mbed_official 324:406fd2029f23 113 #define HW_I2S_INSTANCE_COUNT (1U) /*!< Number of instances of the I2S module. */
mbed_official 324:406fd2029f23 114
mbed_official 324:406fd2029f23 115 /*******************************************************************************
mbed_official 324:406fd2029f23 116 * HW_I2S_TCSR - SAI Transmit Control Register
mbed_official 324:406fd2029f23 117 ******************************************************************************/
mbed_official 324:406fd2029f23 118
mbed_official 324:406fd2029f23 119 /*!
mbed_official 324:406fd2029f23 120 * @brief HW_I2S_TCSR - SAI Transmit Control Register (RW)
mbed_official 324:406fd2029f23 121 *
mbed_official 324:406fd2029f23 122 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 123 */
mbed_official 324:406fd2029f23 124 typedef union _hw_i2s_tcsr
mbed_official 324:406fd2029f23 125 {
mbed_official 324:406fd2029f23 126 uint32_t U;
mbed_official 324:406fd2029f23 127 struct _hw_i2s_tcsr_bitfields
mbed_official 324:406fd2029f23 128 {
mbed_official 324:406fd2029f23 129 uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */
mbed_official 324:406fd2029f23 130 uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */
mbed_official 324:406fd2029f23 131 uint32_t RESERVED0 : 6; /*!< [7:2] */
mbed_official 324:406fd2029f23 132 uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */
mbed_official 324:406fd2029f23 133 uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */
mbed_official 324:406fd2029f23 134 uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */
mbed_official 324:406fd2029f23 135 uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */
mbed_official 324:406fd2029f23 136 uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */
mbed_official 324:406fd2029f23 137 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 138 uint32_t FRF : 1; /*!< [16] FIFO Request Flag */
mbed_official 324:406fd2029f23 139 uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */
mbed_official 324:406fd2029f23 140 uint32_t FEF : 1; /*!< [18] FIFO Error Flag */
mbed_official 324:406fd2029f23 141 uint32_t SEF : 1; /*!< [19] Sync Error Flag */
mbed_official 324:406fd2029f23 142 uint32_t WSF : 1; /*!< [20] Word Start Flag */
mbed_official 324:406fd2029f23 143 uint32_t RESERVED2 : 3; /*!< [23:21] */
mbed_official 324:406fd2029f23 144 uint32_t SR : 1; /*!< [24] Software Reset */
mbed_official 324:406fd2029f23 145 uint32_t FR : 1; /*!< [25] FIFO Reset */
mbed_official 324:406fd2029f23 146 uint32_t RESERVED3 : 2; /*!< [27:26] */
mbed_official 324:406fd2029f23 147 uint32_t BCE : 1; /*!< [28] Bit Clock Enable */
mbed_official 324:406fd2029f23 148 uint32_t DBGE : 1; /*!< [29] Debug Enable */
mbed_official 324:406fd2029f23 149 uint32_t STOPE : 1; /*!< [30] Stop Enable */
mbed_official 324:406fd2029f23 150 uint32_t TE : 1; /*!< [31] Transmitter Enable */
mbed_official 324:406fd2029f23 151 } B;
mbed_official 324:406fd2029f23 152 } hw_i2s_tcsr_t;
mbed_official 324:406fd2029f23 153
mbed_official 324:406fd2029f23 154 /*!
mbed_official 324:406fd2029f23 155 * @name Constants and macros for entire I2S_TCSR register
mbed_official 324:406fd2029f23 156 */
mbed_official 324:406fd2029f23 157 /*@{*/
mbed_official 324:406fd2029f23 158 #define HW_I2S_TCSR_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 159
mbed_official 324:406fd2029f23 160 #define HW_I2S_TCSR(x) (*(__IO hw_i2s_tcsr_t *) HW_I2S_TCSR_ADDR(x))
mbed_official 324:406fd2029f23 161 #define HW_I2S_TCSR_RD(x) (HW_I2S_TCSR(x).U)
mbed_official 324:406fd2029f23 162 #define HW_I2S_TCSR_WR(x, v) (HW_I2S_TCSR(x).U = (v))
mbed_official 324:406fd2029f23 163 #define HW_I2S_TCSR_SET(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) | (v)))
mbed_official 324:406fd2029f23 164 #define HW_I2S_TCSR_CLR(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 165 #define HW_I2S_TCSR_TOG(x, v) (HW_I2S_TCSR_WR(x, HW_I2S_TCSR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 166 /*@}*/
mbed_official 324:406fd2029f23 167
mbed_official 324:406fd2029f23 168 /*
mbed_official 324:406fd2029f23 169 * Constants & macros for individual I2S_TCSR bitfields
mbed_official 324:406fd2029f23 170 */
mbed_official 324:406fd2029f23 171
mbed_official 324:406fd2029f23 172 /*!
mbed_official 324:406fd2029f23 173 * @name Register I2S_TCSR, field FRDE[0] (RW)
mbed_official 324:406fd2029f23 174 *
mbed_official 324:406fd2029f23 175 * Enables/disables DMA requests.
mbed_official 324:406fd2029f23 176 *
mbed_official 324:406fd2029f23 177 * Values:
mbed_official 324:406fd2029f23 178 * - 0 - Disables the DMA request.
mbed_official 324:406fd2029f23 179 * - 1 - Enables the DMA request.
mbed_official 324:406fd2029f23 180 */
mbed_official 324:406fd2029f23 181 /*@{*/
mbed_official 324:406fd2029f23 182 #define BP_I2S_TCSR_FRDE (0U) /*!< Bit position for I2S_TCSR_FRDE. */
mbed_official 324:406fd2029f23 183 #define BM_I2S_TCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_TCSR_FRDE. */
mbed_official 324:406fd2029f23 184 #define BS_I2S_TCSR_FRDE (1U) /*!< Bit field size in bits for I2S_TCSR_FRDE. */
mbed_official 324:406fd2029f23 185
mbed_official 324:406fd2029f23 186 /*! @brief Read current value of the I2S_TCSR_FRDE field. */
mbed_official 324:406fd2029f23 187 #define BR_I2S_TCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE))
mbed_official 324:406fd2029f23 188
mbed_official 324:406fd2029f23 189 /*! @brief Format value for bitfield I2S_TCSR_FRDE. */
mbed_official 324:406fd2029f23 190 #define BF_I2S_TCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRDE) & BM_I2S_TCSR_FRDE)
mbed_official 324:406fd2029f23 191
mbed_official 324:406fd2029f23 192 /*! @brief Set the FRDE field to a new value. */
mbed_official 324:406fd2029f23 193 #define BW_I2S_TCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRDE) = (v))
mbed_official 324:406fd2029f23 194 /*@}*/
mbed_official 324:406fd2029f23 195
mbed_official 324:406fd2029f23 196 /*!
mbed_official 324:406fd2029f23 197 * @name Register I2S_TCSR, field FWDE[1] (RW)
mbed_official 324:406fd2029f23 198 *
mbed_official 324:406fd2029f23 199 * Enables/disables DMA requests.
mbed_official 324:406fd2029f23 200 *
mbed_official 324:406fd2029f23 201 * Values:
mbed_official 324:406fd2029f23 202 * - 0 - Disables the DMA request.
mbed_official 324:406fd2029f23 203 * - 1 - Enables the DMA request.
mbed_official 324:406fd2029f23 204 */
mbed_official 324:406fd2029f23 205 /*@{*/
mbed_official 324:406fd2029f23 206 #define BP_I2S_TCSR_FWDE (1U) /*!< Bit position for I2S_TCSR_FWDE. */
mbed_official 324:406fd2029f23 207 #define BM_I2S_TCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_TCSR_FWDE. */
mbed_official 324:406fd2029f23 208 #define BS_I2S_TCSR_FWDE (1U) /*!< Bit field size in bits for I2S_TCSR_FWDE. */
mbed_official 324:406fd2029f23 209
mbed_official 324:406fd2029f23 210 /*! @brief Read current value of the I2S_TCSR_FWDE field. */
mbed_official 324:406fd2029f23 211 #define BR_I2S_TCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE))
mbed_official 324:406fd2029f23 212
mbed_official 324:406fd2029f23 213 /*! @brief Format value for bitfield I2S_TCSR_FWDE. */
mbed_official 324:406fd2029f23 214 #define BF_I2S_TCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWDE) & BM_I2S_TCSR_FWDE)
mbed_official 324:406fd2029f23 215
mbed_official 324:406fd2029f23 216 /*! @brief Set the FWDE field to a new value. */
mbed_official 324:406fd2029f23 217 #define BW_I2S_TCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWDE) = (v))
mbed_official 324:406fd2029f23 218 /*@}*/
mbed_official 324:406fd2029f23 219
mbed_official 324:406fd2029f23 220 /*!
mbed_official 324:406fd2029f23 221 * @name Register I2S_TCSR, field FRIE[8] (RW)
mbed_official 324:406fd2029f23 222 *
mbed_official 324:406fd2029f23 223 * Enables/disables FIFO request interrupts.
mbed_official 324:406fd2029f23 224 *
mbed_official 324:406fd2029f23 225 * Values:
mbed_official 324:406fd2029f23 226 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 227 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 228 */
mbed_official 324:406fd2029f23 229 /*@{*/
mbed_official 324:406fd2029f23 230 #define BP_I2S_TCSR_FRIE (8U) /*!< Bit position for I2S_TCSR_FRIE. */
mbed_official 324:406fd2029f23 231 #define BM_I2S_TCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_TCSR_FRIE. */
mbed_official 324:406fd2029f23 232 #define BS_I2S_TCSR_FRIE (1U) /*!< Bit field size in bits for I2S_TCSR_FRIE. */
mbed_official 324:406fd2029f23 233
mbed_official 324:406fd2029f23 234 /*! @brief Read current value of the I2S_TCSR_FRIE field. */
mbed_official 324:406fd2029f23 235 #define BR_I2S_TCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE))
mbed_official 324:406fd2029f23 236
mbed_official 324:406fd2029f23 237 /*! @brief Format value for bitfield I2S_TCSR_FRIE. */
mbed_official 324:406fd2029f23 238 #define BF_I2S_TCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FRIE) & BM_I2S_TCSR_FRIE)
mbed_official 324:406fd2029f23 239
mbed_official 324:406fd2029f23 240 /*! @brief Set the FRIE field to a new value. */
mbed_official 324:406fd2029f23 241 #define BW_I2S_TCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRIE) = (v))
mbed_official 324:406fd2029f23 242 /*@}*/
mbed_official 324:406fd2029f23 243
mbed_official 324:406fd2029f23 244 /*!
mbed_official 324:406fd2029f23 245 * @name Register I2S_TCSR, field FWIE[9] (RW)
mbed_official 324:406fd2029f23 246 *
mbed_official 324:406fd2029f23 247 * Enables/disables FIFO warning interrupts.
mbed_official 324:406fd2029f23 248 *
mbed_official 324:406fd2029f23 249 * Values:
mbed_official 324:406fd2029f23 250 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 251 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 252 */
mbed_official 324:406fd2029f23 253 /*@{*/
mbed_official 324:406fd2029f23 254 #define BP_I2S_TCSR_FWIE (9U) /*!< Bit position for I2S_TCSR_FWIE. */
mbed_official 324:406fd2029f23 255 #define BM_I2S_TCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_TCSR_FWIE. */
mbed_official 324:406fd2029f23 256 #define BS_I2S_TCSR_FWIE (1U) /*!< Bit field size in bits for I2S_TCSR_FWIE. */
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 /*! @brief Read current value of the I2S_TCSR_FWIE field. */
mbed_official 324:406fd2029f23 259 #define BR_I2S_TCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE))
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*! @brief Format value for bitfield I2S_TCSR_FWIE. */
mbed_official 324:406fd2029f23 262 #define BF_I2S_TCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FWIE) & BM_I2S_TCSR_FWIE)
mbed_official 324:406fd2029f23 263
mbed_official 324:406fd2029f23 264 /*! @brief Set the FWIE field to a new value. */
mbed_official 324:406fd2029f23 265 #define BW_I2S_TCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWIE) = (v))
mbed_official 324:406fd2029f23 266 /*@}*/
mbed_official 324:406fd2029f23 267
mbed_official 324:406fd2029f23 268 /*!
mbed_official 324:406fd2029f23 269 * @name Register I2S_TCSR, field FEIE[10] (RW)
mbed_official 324:406fd2029f23 270 *
mbed_official 324:406fd2029f23 271 * Enables/disables FIFO error interrupts.
mbed_official 324:406fd2029f23 272 *
mbed_official 324:406fd2029f23 273 * Values:
mbed_official 324:406fd2029f23 274 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 275 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 276 */
mbed_official 324:406fd2029f23 277 /*@{*/
mbed_official 324:406fd2029f23 278 #define BP_I2S_TCSR_FEIE (10U) /*!< Bit position for I2S_TCSR_FEIE. */
mbed_official 324:406fd2029f23 279 #define BM_I2S_TCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_TCSR_FEIE. */
mbed_official 324:406fd2029f23 280 #define BS_I2S_TCSR_FEIE (1U) /*!< Bit field size in bits for I2S_TCSR_FEIE. */
mbed_official 324:406fd2029f23 281
mbed_official 324:406fd2029f23 282 /*! @brief Read current value of the I2S_TCSR_FEIE field. */
mbed_official 324:406fd2029f23 283 #define BR_I2S_TCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE))
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*! @brief Format value for bitfield I2S_TCSR_FEIE. */
mbed_official 324:406fd2029f23 286 #define BF_I2S_TCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEIE) & BM_I2S_TCSR_FEIE)
mbed_official 324:406fd2029f23 287
mbed_official 324:406fd2029f23 288 /*! @brief Set the FEIE field to a new value. */
mbed_official 324:406fd2029f23 289 #define BW_I2S_TCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEIE) = (v))
mbed_official 324:406fd2029f23 290 /*@}*/
mbed_official 324:406fd2029f23 291
mbed_official 324:406fd2029f23 292 /*!
mbed_official 324:406fd2029f23 293 * @name Register I2S_TCSR, field SEIE[11] (RW)
mbed_official 324:406fd2029f23 294 *
mbed_official 324:406fd2029f23 295 * Enables/disables sync error interrupts.
mbed_official 324:406fd2029f23 296 *
mbed_official 324:406fd2029f23 297 * Values:
mbed_official 324:406fd2029f23 298 * - 0 - Disables interrupt.
mbed_official 324:406fd2029f23 299 * - 1 - Enables interrupt.
mbed_official 324:406fd2029f23 300 */
mbed_official 324:406fd2029f23 301 /*@{*/
mbed_official 324:406fd2029f23 302 #define BP_I2S_TCSR_SEIE (11U) /*!< Bit position for I2S_TCSR_SEIE. */
mbed_official 324:406fd2029f23 303 #define BM_I2S_TCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_TCSR_SEIE. */
mbed_official 324:406fd2029f23 304 #define BS_I2S_TCSR_SEIE (1U) /*!< Bit field size in bits for I2S_TCSR_SEIE. */
mbed_official 324:406fd2029f23 305
mbed_official 324:406fd2029f23 306 /*! @brief Read current value of the I2S_TCSR_SEIE field. */
mbed_official 324:406fd2029f23 307 #define BR_I2S_TCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE))
mbed_official 324:406fd2029f23 308
mbed_official 324:406fd2029f23 309 /*! @brief Format value for bitfield I2S_TCSR_SEIE. */
mbed_official 324:406fd2029f23 310 #define BF_I2S_TCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEIE) & BM_I2S_TCSR_SEIE)
mbed_official 324:406fd2029f23 311
mbed_official 324:406fd2029f23 312 /*! @brief Set the SEIE field to a new value. */
mbed_official 324:406fd2029f23 313 #define BW_I2S_TCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEIE) = (v))
mbed_official 324:406fd2029f23 314 /*@}*/
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 /*!
mbed_official 324:406fd2029f23 317 * @name Register I2S_TCSR, field WSIE[12] (RW)
mbed_official 324:406fd2029f23 318 *
mbed_official 324:406fd2029f23 319 * Enables/disables word start interrupts.
mbed_official 324:406fd2029f23 320 *
mbed_official 324:406fd2029f23 321 * Values:
mbed_official 324:406fd2029f23 322 * - 0 - Disables interrupt.
mbed_official 324:406fd2029f23 323 * - 1 - Enables interrupt.
mbed_official 324:406fd2029f23 324 */
mbed_official 324:406fd2029f23 325 /*@{*/
mbed_official 324:406fd2029f23 326 #define BP_I2S_TCSR_WSIE (12U) /*!< Bit position for I2S_TCSR_WSIE. */
mbed_official 324:406fd2029f23 327 #define BM_I2S_TCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_TCSR_WSIE. */
mbed_official 324:406fd2029f23 328 #define BS_I2S_TCSR_WSIE (1U) /*!< Bit field size in bits for I2S_TCSR_WSIE. */
mbed_official 324:406fd2029f23 329
mbed_official 324:406fd2029f23 330 /*! @brief Read current value of the I2S_TCSR_WSIE field. */
mbed_official 324:406fd2029f23 331 #define BR_I2S_TCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE))
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 /*! @brief Format value for bitfield I2S_TCSR_WSIE. */
mbed_official 324:406fd2029f23 334 #define BF_I2S_TCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSIE) & BM_I2S_TCSR_WSIE)
mbed_official 324:406fd2029f23 335
mbed_official 324:406fd2029f23 336 /*! @brief Set the WSIE field to a new value. */
mbed_official 324:406fd2029f23 337 #define BW_I2S_TCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSIE) = (v))
mbed_official 324:406fd2029f23 338 /*@}*/
mbed_official 324:406fd2029f23 339
mbed_official 324:406fd2029f23 340 /*!
mbed_official 324:406fd2029f23 341 * @name Register I2S_TCSR, field FRF[16] (RO)
mbed_official 324:406fd2029f23 342 *
mbed_official 324:406fd2029f23 343 * Indicates that the number of words in an enabled transmit channel FIFO is
mbed_official 324:406fd2029f23 344 * less than or equal to the transmit FIFO watermark.
mbed_official 324:406fd2029f23 345 *
mbed_official 324:406fd2029f23 346 * Values:
mbed_official 324:406fd2029f23 347 * - 0 - Transmit FIFO watermark has not been reached.
mbed_official 324:406fd2029f23 348 * - 1 - Transmit FIFO watermark has been reached.
mbed_official 324:406fd2029f23 349 */
mbed_official 324:406fd2029f23 350 /*@{*/
mbed_official 324:406fd2029f23 351 #define BP_I2S_TCSR_FRF (16U) /*!< Bit position for I2S_TCSR_FRF. */
mbed_official 324:406fd2029f23 352 #define BM_I2S_TCSR_FRF (0x00010000U) /*!< Bit mask for I2S_TCSR_FRF. */
mbed_official 324:406fd2029f23 353 #define BS_I2S_TCSR_FRF (1U) /*!< Bit field size in bits for I2S_TCSR_FRF. */
mbed_official 324:406fd2029f23 354
mbed_official 324:406fd2029f23 355 /*! @brief Read current value of the I2S_TCSR_FRF field. */
mbed_official 324:406fd2029f23 356 #define BR_I2S_TCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FRF))
mbed_official 324:406fd2029f23 357 /*@}*/
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*!
mbed_official 324:406fd2029f23 360 * @name Register I2S_TCSR, field FWF[17] (RO)
mbed_official 324:406fd2029f23 361 *
mbed_official 324:406fd2029f23 362 * Indicates that an enabled transmit FIFO is empty.
mbed_official 324:406fd2029f23 363 *
mbed_official 324:406fd2029f23 364 * Values:
mbed_official 324:406fd2029f23 365 * - 0 - No enabled transmit FIFO is empty.
mbed_official 324:406fd2029f23 366 * - 1 - Enabled transmit FIFO is empty.
mbed_official 324:406fd2029f23 367 */
mbed_official 324:406fd2029f23 368 /*@{*/
mbed_official 324:406fd2029f23 369 #define BP_I2S_TCSR_FWF (17U) /*!< Bit position for I2S_TCSR_FWF. */
mbed_official 324:406fd2029f23 370 #define BM_I2S_TCSR_FWF (0x00020000U) /*!< Bit mask for I2S_TCSR_FWF. */
mbed_official 324:406fd2029f23 371 #define BS_I2S_TCSR_FWF (1U) /*!< Bit field size in bits for I2S_TCSR_FWF. */
mbed_official 324:406fd2029f23 372
mbed_official 324:406fd2029f23 373 /*! @brief Read current value of the I2S_TCSR_FWF field. */
mbed_official 324:406fd2029f23 374 #define BR_I2S_TCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FWF))
mbed_official 324:406fd2029f23 375 /*@}*/
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*!
mbed_official 324:406fd2029f23 378 * @name Register I2S_TCSR, field FEF[18] (W1C)
mbed_official 324:406fd2029f23 379 *
mbed_official 324:406fd2029f23 380 * Indicates that an enabled transmit FIFO has underrun. Write a logic 1 to this
mbed_official 324:406fd2029f23 381 * field to clear this flag.
mbed_official 324:406fd2029f23 382 *
mbed_official 324:406fd2029f23 383 * Values:
mbed_official 324:406fd2029f23 384 * - 0 - Transmit underrun not detected.
mbed_official 324:406fd2029f23 385 * - 1 - Transmit underrun detected.
mbed_official 324:406fd2029f23 386 */
mbed_official 324:406fd2029f23 387 /*@{*/
mbed_official 324:406fd2029f23 388 #define BP_I2S_TCSR_FEF (18U) /*!< Bit position for I2S_TCSR_FEF. */
mbed_official 324:406fd2029f23 389 #define BM_I2S_TCSR_FEF (0x00040000U) /*!< Bit mask for I2S_TCSR_FEF. */
mbed_official 324:406fd2029f23 390 #define BS_I2S_TCSR_FEF (1U) /*!< Bit field size in bits for I2S_TCSR_FEF. */
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392 /*! @brief Read current value of the I2S_TCSR_FEF field. */
mbed_official 324:406fd2029f23 393 #define BR_I2S_TCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF))
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395 /*! @brief Format value for bitfield I2S_TCSR_FEF. */
mbed_official 324:406fd2029f23 396 #define BF_I2S_TCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FEF) & BM_I2S_TCSR_FEF)
mbed_official 324:406fd2029f23 397
mbed_official 324:406fd2029f23 398 /*! @brief Set the FEF field to a new value. */
mbed_official 324:406fd2029f23 399 #define BW_I2S_TCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FEF) = (v))
mbed_official 324:406fd2029f23 400 /*@}*/
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /*!
mbed_official 324:406fd2029f23 403 * @name Register I2S_TCSR, field SEF[19] (W1C)
mbed_official 324:406fd2029f23 404 *
mbed_official 324:406fd2029f23 405 * Indicates that an error in the externally-generated frame sync has been
mbed_official 324:406fd2029f23 406 * detected. Write a logic 1 to this field to clear this flag.
mbed_official 324:406fd2029f23 407 *
mbed_official 324:406fd2029f23 408 * Values:
mbed_official 324:406fd2029f23 409 * - 0 - Sync error not detected.
mbed_official 324:406fd2029f23 410 * - 1 - Frame sync error detected.
mbed_official 324:406fd2029f23 411 */
mbed_official 324:406fd2029f23 412 /*@{*/
mbed_official 324:406fd2029f23 413 #define BP_I2S_TCSR_SEF (19U) /*!< Bit position for I2S_TCSR_SEF. */
mbed_official 324:406fd2029f23 414 #define BM_I2S_TCSR_SEF (0x00080000U) /*!< Bit mask for I2S_TCSR_SEF. */
mbed_official 324:406fd2029f23 415 #define BS_I2S_TCSR_SEF (1U) /*!< Bit field size in bits for I2S_TCSR_SEF. */
mbed_official 324:406fd2029f23 416
mbed_official 324:406fd2029f23 417 /*! @brief Read current value of the I2S_TCSR_SEF field. */
mbed_official 324:406fd2029f23 418 #define BR_I2S_TCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF))
mbed_official 324:406fd2029f23 419
mbed_official 324:406fd2029f23 420 /*! @brief Format value for bitfield I2S_TCSR_SEF. */
mbed_official 324:406fd2029f23 421 #define BF_I2S_TCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SEF) & BM_I2S_TCSR_SEF)
mbed_official 324:406fd2029f23 422
mbed_official 324:406fd2029f23 423 /*! @brief Set the SEF field to a new value. */
mbed_official 324:406fd2029f23 424 #define BW_I2S_TCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SEF) = (v))
mbed_official 324:406fd2029f23 425 /*@}*/
mbed_official 324:406fd2029f23 426
mbed_official 324:406fd2029f23 427 /*!
mbed_official 324:406fd2029f23 428 * @name Register I2S_TCSR, field WSF[20] (W1C)
mbed_official 324:406fd2029f23 429 *
mbed_official 324:406fd2029f23 430 * Indicates that the start of the configured word has been detected. Write a
mbed_official 324:406fd2029f23 431 * logic 1 to this field to clear this flag.
mbed_official 324:406fd2029f23 432 *
mbed_official 324:406fd2029f23 433 * Values:
mbed_official 324:406fd2029f23 434 * - 0 - Start of word not detected.
mbed_official 324:406fd2029f23 435 * - 1 - Start of word detected.
mbed_official 324:406fd2029f23 436 */
mbed_official 324:406fd2029f23 437 /*@{*/
mbed_official 324:406fd2029f23 438 #define BP_I2S_TCSR_WSF (20U) /*!< Bit position for I2S_TCSR_WSF. */
mbed_official 324:406fd2029f23 439 #define BM_I2S_TCSR_WSF (0x00100000U) /*!< Bit mask for I2S_TCSR_WSF. */
mbed_official 324:406fd2029f23 440 #define BS_I2S_TCSR_WSF (1U) /*!< Bit field size in bits for I2S_TCSR_WSF. */
mbed_official 324:406fd2029f23 441
mbed_official 324:406fd2029f23 442 /*! @brief Read current value of the I2S_TCSR_WSF field. */
mbed_official 324:406fd2029f23 443 #define BR_I2S_TCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF))
mbed_official 324:406fd2029f23 444
mbed_official 324:406fd2029f23 445 /*! @brief Format value for bitfield I2S_TCSR_WSF. */
mbed_official 324:406fd2029f23 446 #define BF_I2S_TCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_WSF) & BM_I2S_TCSR_WSF)
mbed_official 324:406fd2029f23 447
mbed_official 324:406fd2029f23 448 /*! @brief Set the WSF field to a new value. */
mbed_official 324:406fd2029f23 449 #define BW_I2S_TCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_WSF) = (v))
mbed_official 324:406fd2029f23 450 /*@}*/
mbed_official 324:406fd2029f23 451
mbed_official 324:406fd2029f23 452 /*!
mbed_official 324:406fd2029f23 453 * @name Register I2S_TCSR, field SR[24] (RW)
mbed_official 324:406fd2029f23 454 *
mbed_official 324:406fd2029f23 455 * When set, resets the internal transmitter logic including the FIFO pointers.
mbed_official 324:406fd2029f23 456 * Software-visible registers are not affected, except for the status registers.
mbed_official 324:406fd2029f23 457 *
mbed_official 324:406fd2029f23 458 * Values:
mbed_official 324:406fd2029f23 459 * - 0 - No effect.
mbed_official 324:406fd2029f23 460 * - 1 - Software reset.
mbed_official 324:406fd2029f23 461 */
mbed_official 324:406fd2029f23 462 /*@{*/
mbed_official 324:406fd2029f23 463 #define BP_I2S_TCSR_SR (24U) /*!< Bit position for I2S_TCSR_SR. */
mbed_official 324:406fd2029f23 464 #define BM_I2S_TCSR_SR (0x01000000U) /*!< Bit mask for I2S_TCSR_SR. */
mbed_official 324:406fd2029f23 465 #define BS_I2S_TCSR_SR (1U) /*!< Bit field size in bits for I2S_TCSR_SR. */
mbed_official 324:406fd2029f23 466
mbed_official 324:406fd2029f23 467 /*! @brief Read current value of the I2S_TCSR_SR field. */
mbed_official 324:406fd2029f23 468 #define BR_I2S_TCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR))
mbed_official 324:406fd2029f23 469
mbed_official 324:406fd2029f23 470 /*! @brief Format value for bitfield I2S_TCSR_SR. */
mbed_official 324:406fd2029f23 471 #define BF_I2S_TCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_SR) & BM_I2S_TCSR_SR)
mbed_official 324:406fd2029f23 472
mbed_official 324:406fd2029f23 473 /*! @brief Set the SR field to a new value. */
mbed_official 324:406fd2029f23 474 #define BW_I2S_TCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_SR) = (v))
mbed_official 324:406fd2029f23 475 /*@}*/
mbed_official 324:406fd2029f23 476
mbed_official 324:406fd2029f23 477 /*!
mbed_official 324:406fd2029f23 478 * @name Register I2S_TCSR, field FR[25] (WORZ)
mbed_official 324:406fd2029f23 479 *
mbed_official 324:406fd2029f23 480 * Resets the FIFO pointers. Reading this field will always return zero. FIFO
mbed_official 324:406fd2029f23 481 * pointers should only be reset when the transmitter is disabled or the FIFO error
mbed_official 324:406fd2029f23 482 * flag is set.
mbed_official 324:406fd2029f23 483 *
mbed_official 324:406fd2029f23 484 * Values:
mbed_official 324:406fd2029f23 485 * - 0 - No effect.
mbed_official 324:406fd2029f23 486 * - 1 - FIFO reset.
mbed_official 324:406fd2029f23 487 */
mbed_official 324:406fd2029f23 488 /*@{*/
mbed_official 324:406fd2029f23 489 #define BP_I2S_TCSR_FR (25U) /*!< Bit position for I2S_TCSR_FR. */
mbed_official 324:406fd2029f23 490 #define BM_I2S_TCSR_FR (0x02000000U) /*!< Bit mask for I2S_TCSR_FR. */
mbed_official 324:406fd2029f23 491 #define BS_I2S_TCSR_FR (1U) /*!< Bit field size in bits for I2S_TCSR_FR. */
mbed_official 324:406fd2029f23 492
mbed_official 324:406fd2029f23 493 /*! @brief Format value for bitfield I2S_TCSR_FR. */
mbed_official 324:406fd2029f23 494 #define BF_I2S_TCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_FR) & BM_I2S_TCSR_FR)
mbed_official 324:406fd2029f23 495
mbed_official 324:406fd2029f23 496 /*! @brief Set the FR field to a new value. */
mbed_official 324:406fd2029f23 497 #define BW_I2S_TCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_FR) = (v))
mbed_official 324:406fd2029f23 498 /*@}*/
mbed_official 324:406fd2029f23 499
mbed_official 324:406fd2029f23 500 /*!
mbed_official 324:406fd2029f23 501 * @name Register I2S_TCSR, field BCE[28] (RW)
mbed_official 324:406fd2029f23 502 *
mbed_official 324:406fd2029f23 503 * Enables the transmit bit clock, separately from the TE. This field is
mbed_official 324:406fd2029f23 504 * automatically set whenever TE is set. When software clears this field, the transmit
mbed_official 324:406fd2029f23 505 * bit clock remains enabled, and this bit remains set, until the end of the
mbed_official 324:406fd2029f23 506 * current frame.
mbed_official 324:406fd2029f23 507 *
mbed_official 324:406fd2029f23 508 * Values:
mbed_official 324:406fd2029f23 509 * - 0 - Transmit bit clock is disabled.
mbed_official 324:406fd2029f23 510 * - 1 - Transmit bit clock is enabled.
mbed_official 324:406fd2029f23 511 */
mbed_official 324:406fd2029f23 512 /*@{*/
mbed_official 324:406fd2029f23 513 #define BP_I2S_TCSR_BCE (28U) /*!< Bit position for I2S_TCSR_BCE. */
mbed_official 324:406fd2029f23 514 #define BM_I2S_TCSR_BCE (0x10000000U) /*!< Bit mask for I2S_TCSR_BCE. */
mbed_official 324:406fd2029f23 515 #define BS_I2S_TCSR_BCE (1U) /*!< Bit field size in bits for I2S_TCSR_BCE. */
mbed_official 324:406fd2029f23 516
mbed_official 324:406fd2029f23 517 /*! @brief Read current value of the I2S_TCSR_BCE field. */
mbed_official 324:406fd2029f23 518 #define BR_I2S_TCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE))
mbed_official 324:406fd2029f23 519
mbed_official 324:406fd2029f23 520 /*! @brief Format value for bitfield I2S_TCSR_BCE. */
mbed_official 324:406fd2029f23 521 #define BF_I2S_TCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_BCE) & BM_I2S_TCSR_BCE)
mbed_official 324:406fd2029f23 522
mbed_official 324:406fd2029f23 523 /*! @brief Set the BCE field to a new value. */
mbed_official 324:406fd2029f23 524 #define BW_I2S_TCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_BCE) = (v))
mbed_official 324:406fd2029f23 525 /*@}*/
mbed_official 324:406fd2029f23 526
mbed_official 324:406fd2029f23 527 /*!
mbed_official 324:406fd2029f23 528 * @name Register I2S_TCSR, field DBGE[29] (RW)
mbed_official 324:406fd2029f23 529 *
mbed_official 324:406fd2029f23 530 * Enables/disables transmitter operation in Debug mode. The transmit bit clock
mbed_official 324:406fd2029f23 531 * is not affected by debug mode.
mbed_official 324:406fd2029f23 532 *
mbed_official 324:406fd2029f23 533 * Values:
mbed_official 324:406fd2029f23 534 * - 0 - Transmitter is disabled in Debug mode, after completing the current
mbed_official 324:406fd2029f23 535 * frame.
mbed_official 324:406fd2029f23 536 * - 1 - Transmitter is enabled in Debug mode.
mbed_official 324:406fd2029f23 537 */
mbed_official 324:406fd2029f23 538 /*@{*/
mbed_official 324:406fd2029f23 539 #define BP_I2S_TCSR_DBGE (29U) /*!< Bit position for I2S_TCSR_DBGE. */
mbed_official 324:406fd2029f23 540 #define BM_I2S_TCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_TCSR_DBGE. */
mbed_official 324:406fd2029f23 541 #define BS_I2S_TCSR_DBGE (1U) /*!< Bit field size in bits for I2S_TCSR_DBGE. */
mbed_official 324:406fd2029f23 542
mbed_official 324:406fd2029f23 543 /*! @brief Read current value of the I2S_TCSR_DBGE field. */
mbed_official 324:406fd2029f23 544 #define BR_I2S_TCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE))
mbed_official 324:406fd2029f23 545
mbed_official 324:406fd2029f23 546 /*! @brief Format value for bitfield I2S_TCSR_DBGE. */
mbed_official 324:406fd2029f23 547 #define BF_I2S_TCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_DBGE) & BM_I2S_TCSR_DBGE)
mbed_official 324:406fd2029f23 548
mbed_official 324:406fd2029f23 549 /*! @brief Set the DBGE field to a new value. */
mbed_official 324:406fd2029f23 550 #define BW_I2S_TCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_DBGE) = (v))
mbed_official 324:406fd2029f23 551 /*@}*/
mbed_official 324:406fd2029f23 552
mbed_official 324:406fd2029f23 553 /*!
mbed_official 324:406fd2029f23 554 * @name Register I2S_TCSR, field STOPE[30] (RW)
mbed_official 324:406fd2029f23 555 *
mbed_official 324:406fd2029f23 556 * Configures transmitter operation in Stop mode. This field is ignored and the
mbed_official 324:406fd2029f23 557 * transmitter is disabled in all low-leakage stop modes.
mbed_official 324:406fd2029f23 558 *
mbed_official 324:406fd2029f23 559 * Values:
mbed_official 324:406fd2029f23 560 * - 0 - Transmitter disabled in Stop mode.
mbed_official 324:406fd2029f23 561 * - 1 - Transmitter enabled in Stop mode.
mbed_official 324:406fd2029f23 562 */
mbed_official 324:406fd2029f23 563 /*@{*/
mbed_official 324:406fd2029f23 564 #define BP_I2S_TCSR_STOPE (30U) /*!< Bit position for I2S_TCSR_STOPE. */
mbed_official 324:406fd2029f23 565 #define BM_I2S_TCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_TCSR_STOPE. */
mbed_official 324:406fd2029f23 566 #define BS_I2S_TCSR_STOPE (1U) /*!< Bit field size in bits for I2S_TCSR_STOPE. */
mbed_official 324:406fd2029f23 567
mbed_official 324:406fd2029f23 568 /*! @brief Read current value of the I2S_TCSR_STOPE field. */
mbed_official 324:406fd2029f23 569 #define BR_I2S_TCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE))
mbed_official 324:406fd2029f23 570
mbed_official 324:406fd2029f23 571 /*! @brief Format value for bitfield I2S_TCSR_STOPE. */
mbed_official 324:406fd2029f23 572 #define BF_I2S_TCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_STOPE) & BM_I2S_TCSR_STOPE)
mbed_official 324:406fd2029f23 573
mbed_official 324:406fd2029f23 574 /*! @brief Set the STOPE field to a new value. */
mbed_official 324:406fd2029f23 575 #define BW_I2S_TCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_STOPE) = (v))
mbed_official 324:406fd2029f23 576 /*@}*/
mbed_official 324:406fd2029f23 577
mbed_official 324:406fd2029f23 578 /*!
mbed_official 324:406fd2029f23 579 * @name Register I2S_TCSR, field TE[31] (RW)
mbed_official 324:406fd2029f23 580 *
mbed_official 324:406fd2029f23 581 * Enables/disables the transmitter. When software clears this field, the
mbed_official 324:406fd2029f23 582 * transmitter remains enabled, and this bit remains set, until the end of the current
mbed_official 324:406fd2029f23 583 * frame.
mbed_official 324:406fd2029f23 584 *
mbed_official 324:406fd2029f23 585 * Values:
mbed_official 324:406fd2029f23 586 * - 0 - Transmitter is disabled.
mbed_official 324:406fd2029f23 587 * - 1 - Transmitter is enabled, or transmitter has been disabled and has not
mbed_official 324:406fd2029f23 588 * yet reached end of frame.
mbed_official 324:406fd2029f23 589 */
mbed_official 324:406fd2029f23 590 /*@{*/
mbed_official 324:406fd2029f23 591 #define BP_I2S_TCSR_TE (31U) /*!< Bit position for I2S_TCSR_TE. */
mbed_official 324:406fd2029f23 592 #define BM_I2S_TCSR_TE (0x80000000U) /*!< Bit mask for I2S_TCSR_TE. */
mbed_official 324:406fd2029f23 593 #define BS_I2S_TCSR_TE (1U) /*!< Bit field size in bits for I2S_TCSR_TE. */
mbed_official 324:406fd2029f23 594
mbed_official 324:406fd2029f23 595 /*! @brief Read current value of the I2S_TCSR_TE field. */
mbed_official 324:406fd2029f23 596 #define BR_I2S_TCSR_TE(x) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE))
mbed_official 324:406fd2029f23 597
mbed_official 324:406fd2029f23 598 /*! @brief Format value for bitfield I2S_TCSR_TE. */
mbed_official 324:406fd2029f23 599 #define BF_I2S_TCSR_TE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCSR_TE) & BM_I2S_TCSR_TE)
mbed_official 324:406fd2029f23 600
mbed_official 324:406fd2029f23 601 /*! @brief Set the TE field to a new value. */
mbed_official 324:406fd2029f23 602 #define BW_I2S_TCSR_TE(x, v) (BITBAND_ACCESS32(HW_I2S_TCSR_ADDR(x), BP_I2S_TCSR_TE) = (v))
mbed_official 324:406fd2029f23 603 /*@}*/
mbed_official 324:406fd2029f23 604
mbed_official 324:406fd2029f23 605 /*******************************************************************************
mbed_official 324:406fd2029f23 606 * HW_I2S_TCR1 - SAI Transmit Configuration 1 Register
mbed_official 324:406fd2029f23 607 ******************************************************************************/
mbed_official 324:406fd2029f23 608
mbed_official 324:406fd2029f23 609 /*!
mbed_official 324:406fd2029f23 610 * @brief HW_I2S_TCR1 - SAI Transmit Configuration 1 Register (RW)
mbed_official 324:406fd2029f23 611 *
mbed_official 324:406fd2029f23 612 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 613 */
mbed_official 324:406fd2029f23 614 typedef union _hw_i2s_tcr1
mbed_official 324:406fd2029f23 615 {
mbed_official 324:406fd2029f23 616 uint32_t U;
mbed_official 324:406fd2029f23 617 struct _hw_i2s_tcr1_bitfields
mbed_official 324:406fd2029f23 618 {
mbed_official 324:406fd2029f23 619 uint32_t TFW : 3; /*!< [2:0] Transmit FIFO Watermark */
mbed_official 324:406fd2029f23 620 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 621 } B;
mbed_official 324:406fd2029f23 622 } hw_i2s_tcr1_t;
mbed_official 324:406fd2029f23 623
mbed_official 324:406fd2029f23 624 /*!
mbed_official 324:406fd2029f23 625 * @name Constants and macros for entire I2S_TCR1 register
mbed_official 324:406fd2029f23 626 */
mbed_official 324:406fd2029f23 627 /*@{*/
mbed_official 324:406fd2029f23 628 #define HW_I2S_TCR1_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 629
mbed_official 324:406fd2029f23 630 #define HW_I2S_TCR1(x) (*(__IO hw_i2s_tcr1_t *) HW_I2S_TCR1_ADDR(x))
mbed_official 324:406fd2029f23 631 #define HW_I2S_TCR1_RD(x) (HW_I2S_TCR1(x).U)
mbed_official 324:406fd2029f23 632 #define HW_I2S_TCR1_WR(x, v) (HW_I2S_TCR1(x).U = (v))
mbed_official 324:406fd2029f23 633 #define HW_I2S_TCR1_SET(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) | (v)))
mbed_official 324:406fd2029f23 634 #define HW_I2S_TCR1_CLR(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 635 #define HW_I2S_TCR1_TOG(x, v) (HW_I2S_TCR1_WR(x, HW_I2S_TCR1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 636 /*@}*/
mbed_official 324:406fd2029f23 637
mbed_official 324:406fd2029f23 638 /*
mbed_official 324:406fd2029f23 639 * Constants & macros for individual I2S_TCR1 bitfields
mbed_official 324:406fd2029f23 640 */
mbed_official 324:406fd2029f23 641
mbed_official 324:406fd2029f23 642 /*!
mbed_official 324:406fd2029f23 643 * @name Register I2S_TCR1, field TFW[2:0] (RW)
mbed_official 324:406fd2029f23 644 *
mbed_official 324:406fd2029f23 645 * Configures the watermark level for all enabled transmit channels.
mbed_official 324:406fd2029f23 646 */
mbed_official 324:406fd2029f23 647 /*@{*/
mbed_official 324:406fd2029f23 648 #define BP_I2S_TCR1_TFW (0U) /*!< Bit position for I2S_TCR1_TFW. */
mbed_official 324:406fd2029f23 649 #define BM_I2S_TCR1_TFW (0x00000007U) /*!< Bit mask for I2S_TCR1_TFW. */
mbed_official 324:406fd2029f23 650 #define BS_I2S_TCR1_TFW (3U) /*!< Bit field size in bits for I2S_TCR1_TFW. */
mbed_official 324:406fd2029f23 651
mbed_official 324:406fd2029f23 652 /*! @brief Read current value of the I2S_TCR1_TFW field. */
mbed_official 324:406fd2029f23 653 #define BR_I2S_TCR1_TFW(x) (HW_I2S_TCR1(x).B.TFW)
mbed_official 324:406fd2029f23 654
mbed_official 324:406fd2029f23 655 /*! @brief Format value for bitfield I2S_TCR1_TFW. */
mbed_official 324:406fd2029f23 656 #define BF_I2S_TCR1_TFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR1_TFW) & BM_I2S_TCR1_TFW)
mbed_official 324:406fd2029f23 657
mbed_official 324:406fd2029f23 658 /*! @brief Set the TFW field to a new value. */
mbed_official 324:406fd2029f23 659 #define BW_I2S_TCR1_TFW(x, v) (HW_I2S_TCR1_WR(x, (HW_I2S_TCR1_RD(x) & ~BM_I2S_TCR1_TFW) | BF_I2S_TCR1_TFW(v)))
mbed_official 324:406fd2029f23 660 /*@}*/
mbed_official 324:406fd2029f23 661
mbed_official 324:406fd2029f23 662 /*******************************************************************************
mbed_official 324:406fd2029f23 663 * HW_I2S_TCR2 - SAI Transmit Configuration 2 Register
mbed_official 324:406fd2029f23 664 ******************************************************************************/
mbed_official 324:406fd2029f23 665
mbed_official 324:406fd2029f23 666 /*!
mbed_official 324:406fd2029f23 667 * @brief HW_I2S_TCR2 - SAI Transmit Configuration 2 Register (RW)
mbed_official 324:406fd2029f23 668 *
mbed_official 324:406fd2029f23 669 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 670 *
mbed_official 324:406fd2029f23 671 * This register must not be altered when TCSR[TE] is set.
mbed_official 324:406fd2029f23 672 */
mbed_official 324:406fd2029f23 673 typedef union _hw_i2s_tcr2
mbed_official 324:406fd2029f23 674 {
mbed_official 324:406fd2029f23 675 uint32_t U;
mbed_official 324:406fd2029f23 676 struct _hw_i2s_tcr2_bitfields
mbed_official 324:406fd2029f23 677 {
mbed_official 324:406fd2029f23 678 uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */
mbed_official 324:406fd2029f23 679 uint32_t RESERVED0 : 16; /*!< [23:8] */
mbed_official 324:406fd2029f23 680 uint32_t BCD : 1; /*!< [24] Bit Clock Direction */
mbed_official 324:406fd2029f23 681 uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */
mbed_official 324:406fd2029f23 682 uint32_t MSEL : 2; /*!< [27:26] MCLK Select */
mbed_official 324:406fd2029f23 683 uint32_t BCI : 1; /*!< [28] Bit Clock Input */
mbed_official 324:406fd2029f23 684 uint32_t BCS : 1; /*!< [29] Bit Clock Swap */
mbed_official 324:406fd2029f23 685 uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */
mbed_official 324:406fd2029f23 686 } B;
mbed_official 324:406fd2029f23 687 } hw_i2s_tcr2_t;
mbed_official 324:406fd2029f23 688
mbed_official 324:406fd2029f23 689 /*!
mbed_official 324:406fd2029f23 690 * @name Constants and macros for entire I2S_TCR2 register
mbed_official 324:406fd2029f23 691 */
mbed_official 324:406fd2029f23 692 /*@{*/
mbed_official 324:406fd2029f23 693 #define HW_I2S_TCR2_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 694
mbed_official 324:406fd2029f23 695 #define HW_I2S_TCR2(x) (*(__IO hw_i2s_tcr2_t *) HW_I2S_TCR2_ADDR(x))
mbed_official 324:406fd2029f23 696 #define HW_I2S_TCR2_RD(x) (HW_I2S_TCR2(x).U)
mbed_official 324:406fd2029f23 697 #define HW_I2S_TCR2_WR(x, v) (HW_I2S_TCR2(x).U = (v))
mbed_official 324:406fd2029f23 698 #define HW_I2S_TCR2_SET(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) | (v)))
mbed_official 324:406fd2029f23 699 #define HW_I2S_TCR2_CLR(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 700 #define HW_I2S_TCR2_TOG(x, v) (HW_I2S_TCR2_WR(x, HW_I2S_TCR2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 701 /*@}*/
mbed_official 324:406fd2029f23 702
mbed_official 324:406fd2029f23 703 /*
mbed_official 324:406fd2029f23 704 * Constants & macros for individual I2S_TCR2 bitfields
mbed_official 324:406fd2029f23 705 */
mbed_official 324:406fd2029f23 706
mbed_official 324:406fd2029f23 707 /*!
mbed_official 324:406fd2029f23 708 * @name Register I2S_TCR2, field DIV[7:0] (RW)
mbed_official 324:406fd2029f23 709 *
mbed_official 324:406fd2029f23 710 * Divides down the audio master clock to generate the bit clock when configured
mbed_official 324:406fd2029f23 711 * for an internal bit clock. The division value is (DIV + 1) * 2.
mbed_official 324:406fd2029f23 712 */
mbed_official 324:406fd2029f23 713 /*@{*/
mbed_official 324:406fd2029f23 714 #define BP_I2S_TCR2_DIV (0U) /*!< Bit position for I2S_TCR2_DIV. */
mbed_official 324:406fd2029f23 715 #define BM_I2S_TCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_TCR2_DIV. */
mbed_official 324:406fd2029f23 716 #define BS_I2S_TCR2_DIV (8U) /*!< Bit field size in bits for I2S_TCR2_DIV. */
mbed_official 324:406fd2029f23 717
mbed_official 324:406fd2029f23 718 /*! @brief Read current value of the I2S_TCR2_DIV field. */
mbed_official 324:406fd2029f23 719 #define BR_I2S_TCR2_DIV(x) (HW_I2S_TCR2(x).B.DIV)
mbed_official 324:406fd2029f23 720
mbed_official 324:406fd2029f23 721 /*! @brief Format value for bitfield I2S_TCR2_DIV. */
mbed_official 324:406fd2029f23 722 #define BF_I2S_TCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_DIV) & BM_I2S_TCR2_DIV)
mbed_official 324:406fd2029f23 723
mbed_official 324:406fd2029f23 724 /*! @brief Set the DIV field to a new value. */
mbed_official 324:406fd2029f23 725 #define BW_I2S_TCR2_DIV(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_DIV) | BF_I2S_TCR2_DIV(v)))
mbed_official 324:406fd2029f23 726 /*@}*/
mbed_official 324:406fd2029f23 727
mbed_official 324:406fd2029f23 728 /*!
mbed_official 324:406fd2029f23 729 * @name Register I2S_TCR2, field BCD[24] (RW)
mbed_official 324:406fd2029f23 730 *
mbed_official 324:406fd2029f23 731 * Configures the direction of the bit clock.
mbed_official 324:406fd2029f23 732 *
mbed_official 324:406fd2029f23 733 * Values:
mbed_official 324:406fd2029f23 734 * - 0 - Bit clock is generated externally in Slave mode.
mbed_official 324:406fd2029f23 735 * - 1 - Bit clock is generated internally in Master mode.
mbed_official 324:406fd2029f23 736 */
mbed_official 324:406fd2029f23 737 /*@{*/
mbed_official 324:406fd2029f23 738 #define BP_I2S_TCR2_BCD (24U) /*!< Bit position for I2S_TCR2_BCD. */
mbed_official 324:406fd2029f23 739 #define BM_I2S_TCR2_BCD (0x01000000U) /*!< Bit mask for I2S_TCR2_BCD. */
mbed_official 324:406fd2029f23 740 #define BS_I2S_TCR2_BCD (1U) /*!< Bit field size in bits for I2S_TCR2_BCD. */
mbed_official 324:406fd2029f23 741
mbed_official 324:406fd2029f23 742 /*! @brief Read current value of the I2S_TCR2_BCD field. */
mbed_official 324:406fd2029f23 743 #define BR_I2S_TCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD))
mbed_official 324:406fd2029f23 744
mbed_official 324:406fd2029f23 745 /*! @brief Format value for bitfield I2S_TCR2_BCD. */
mbed_official 324:406fd2029f23 746 #define BF_I2S_TCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCD) & BM_I2S_TCR2_BCD)
mbed_official 324:406fd2029f23 747
mbed_official 324:406fd2029f23 748 /*! @brief Set the BCD field to a new value. */
mbed_official 324:406fd2029f23 749 #define BW_I2S_TCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCD) = (v))
mbed_official 324:406fd2029f23 750 /*@}*/
mbed_official 324:406fd2029f23 751
mbed_official 324:406fd2029f23 752 /*!
mbed_official 324:406fd2029f23 753 * @name Register I2S_TCR2, field BCP[25] (RW)
mbed_official 324:406fd2029f23 754 *
mbed_official 324:406fd2029f23 755 * Configures the polarity of the bit clock.
mbed_official 324:406fd2029f23 756 *
mbed_official 324:406fd2029f23 757 * Values:
mbed_official 324:406fd2029f23 758 * - 0 - Bit clock is active high with drive outputs on rising edge and sample
mbed_official 324:406fd2029f23 759 * inputs on falling edge.
mbed_official 324:406fd2029f23 760 * - 1 - Bit clock is active low with drive outputs on falling edge and sample
mbed_official 324:406fd2029f23 761 * inputs on rising edge.
mbed_official 324:406fd2029f23 762 */
mbed_official 324:406fd2029f23 763 /*@{*/
mbed_official 324:406fd2029f23 764 #define BP_I2S_TCR2_BCP (25U) /*!< Bit position for I2S_TCR2_BCP. */
mbed_official 324:406fd2029f23 765 #define BM_I2S_TCR2_BCP (0x02000000U) /*!< Bit mask for I2S_TCR2_BCP. */
mbed_official 324:406fd2029f23 766 #define BS_I2S_TCR2_BCP (1U) /*!< Bit field size in bits for I2S_TCR2_BCP. */
mbed_official 324:406fd2029f23 767
mbed_official 324:406fd2029f23 768 /*! @brief Read current value of the I2S_TCR2_BCP field. */
mbed_official 324:406fd2029f23 769 #define BR_I2S_TCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP))
mbed_official 324:406fd2029f23 770
mbed_official 324:406fd2029f23 771 /*! @brief Format value for bitfield I2S_TCR2_BCP. */
mbed_official 324:406fd2029f23 772 #define BF_I2S_TCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCP) & BM_I2S_TCR2_BCP)
mbed_official 324:406fd2029f23 773
mbed_official 324:406fd2029f23 774 /*! @brief Set the BCP field to a new value. */
mbed_official 324:406fd2029f23 775 #define BW_I2S_TCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCP) = (v))
mbed_official 324:406fd2029f23 776 /*@}*/
mbed_official 324:406fd2029f23 777
mbed_official 324:406fd2029f23 778 /*!
mbed_official 324:406fd2029f23 779 * @name Register I2S_TCR2, field MSEL[27:26] (RW)
mbed_official 324:406fd2029f23 780 *
mbed_official 324:406fd2029f23 781 * Selects the audio Master Clock option used to generate an internally
mbed_official 324:406fd2029f23 782 * generated bit clock. This field has no effect when configured for an externally
mbed_official 324:406fd2029f23 783 * generated bit clock. Depending on the device, some Master Clock options might not be
mbed_official 324:406fd2029f23 784 * available. See the chip configuration details for the availability and
mbed_official 324:406fd2029f23 785 * chip-specific meaning of each option.
mbed_official 324:406fd2029f23 786 *
mbed_official 324:406fd2029f23 787 * Values:
mbed_official 324:406fd2029f23 788 * - 00 - Bus Clock selected.
mbed_official 324:406fd2029f23 789 * - 01 - Master Clock (MCLK) 1 option selected.
mbed_official 324:406fd2029f23 790 * - 10 - Master Clock (MCLK) 2 option selected.
mbed_official 324:406fd2029f23 791 * - 11 - Master Clock (MCLK) 3 option selected.
mbed_official 324:406fd2029f23 792 */
mbed_official 324:406fd2029f23 793 /*@{*/
mbed_official 324:406fd2029f23 794 #define BP_I2S_TCR2_MSEL (26U) /*!< Bit position for I2S_TCR2_MSEL. */
mbed_official 324:406fd2029f23 795 #define BM_I2S_TCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_TCR2_MSEL. */
mbed_official 324:406fd2029f23 796 #define BS_I2S_TCR2_MSEL (2U) /*!< Bit field size in bits for I2S_TCR2_MSEL. */
mbed_official 324:406fd2029f23 797
mbed_official 324:406fd2029f23 798 /*! @brief Read current value of the I2S_TCR2_MSEL field. */
mbed_official 324:406fd2029f23 799 #define BR_I2S_TCR2_MSEL(x) (HW_I2S_TCR2(x).B.MSEL)
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 /*! @brief Format value for bitfield I2S_TCR2_MSEL. */
mbed_official 324:406fd2029f23 802 #define BF_I2S_TCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_MSEL) & BM_I2S_TCR2_MSEL)
mbed_official 324:406fd2029f23 803
mbed_official 324:406fd2029f23 804 /*! @brief Set the MSEL field to a new value. */
mbed_official 324:406fd2029f23 805 #define BW_I2S_TCR2_MSEL(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_MSEL) | BF_I2S_TCR2_MSEL(v)))
mbed_official 324:406fd2029f23 806 /*@}*/
mbed_official 324:406fd2029f23 807
mbed_official 324:406fd2029f23 808 /*!
mbed_official 324:406fd2029f23 809 * @name Register I2S_TCR2, field BCI[28] (RW)
mbed_official 324:406fd2029f23 810 *
mbed_official 324:406fd2029f23 811 * When this field is set and using an internally generated bit clock in either
mbed_official 324:406fd2029f23 812 * synchronous or asynchronous mode, the bit clock actually used by the
mbed_official 324:406fd2029f23 813 * transmitter is delayed by the pad output delay (the transmitter is clocked by the pad
mbed_official 324:406fd2029f23 814 * input as if the clock was externally generated). This has the effect of
mbed_official 324:406fd2029f23 815 * decreasing the data input setup time, but increasing the data output valid time. The
mbed_official 324:406fd2029f23 816 * slave mode timing from the datasheet should be used for the transmitter when
mbed_official 324:406fd2029f23 817 * this bit is set. In synchronous mode, this bit allows the transmitter to use
mbed_official 324:406fd2029f23 818 * the slave mode timing from the datasheet, while the receiver uses the master
mbed_official 324:406fd2029f23 819 * mode timing. This field has no effect when configured for an externally generated
mbed_official 324:406fd2029f23 820 * bit clock .
mbed_official 324:406fd2029f23 821 *
mbed_official 324:406fd2029f23 822 * Values:
mbed_official 324:406fd2029f23 823 * - 0 - No effect.
mbed_official 324:406fd2029f23 824 * - 1 - Internal logic is clocked as if bit clock was externally generated.
mbed_official 324:406fd2029f23 825 */
mbed_official 324:406fd2029f23 826 /*@{*/
mbed_official 324:406fd2029f23 827 #define BP_I2S_TCR2_BCI (28U) /*!< Bit position for I2S_TCR2_BCI. */
mbed_official 324:406fd2029f23 828 #define BM_I2S_TCR2_BCI (0x10000000U) /*!< Bit mask for I2S_TCR2_BCI. */
mbed_official 324:406fd2029f23 829 #define BS_I2S_TCR2_BCI (1U) /*!< Bit field size in bits for I2S_TCR2_BCI. */
mbed_official 324:406fd2029f23 830
mbed_official 324:406fd2029f23 831 /*! @brief Read current value of the I2S_TCR2_BCI field. */
mbed_official 324:406fd2029f23 832 #define BR_I2S_TCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI))
mbed_official 324:406fd2029f23 833
mbed_official 324:406fd2029f23 834 /*! @brief Format value for bitfield I2S_TCR2_BCI. */
mbed_official 324:406fd2029f23 835 #define BF_I2S_TCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCI) & BM_I2S_TCR2_BCI)
mbed_official 324:406fd2029f23 836
mbed_official 324:406fd2029f23 837 /*! @brief Set the BCI field to a new value. */
mbed_official 324:406fd2029f23 838 #define BW_I2S_TCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCI) = (v))
mbed_official 324:406fd2029f23 839 /*@}*/
mbed_official 324:406fd2029f23 840
mbed_official 324:406fd2029f23 841 /*!
mbed_official 324:406fd2029f23 842 * @name Register I2S_TCR2, field BCS[29] (RW)
mbed_official 324:406fd2029f23 843 *
mbed_official 324:406fd2029f23 844 * This field swaps the bit clock used by the transmitter. When the transmitter
mbed_official 324:406fd2029f23 845 * is configured in asynchronous mode and this bit is set, the transmitter is
mbed_official 324:406fd2029f23 846 * clocked by the receiver bit clock (SAI_RX_BCLK). This allows the transmitter and
mbed_official 324:406fd2029f23 847 * receiver to share the same bit clock, but the transmitter continues to use the
mbed_official 324:406fd2029f23 848 * transmit frame sync (SAI_TX_SYNC). When the transmitter is configured in
mbed_official 324:406fd2029f23 849 * synchronous mode, the transmitter BCS field and receiver BCS field must be set to
mbed_official 324:406fd2029f23 850 * the same value. When both are set, the transmitter and receiver are both
mbed_official 324:406fd2029f23 851 * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync
mbed_official 324:406fd2029f23 852 * (SAI_RX_SYNC).
mbed_official 324:406fd2029f23 853 *
mbed_official 324:406fd2029f23 854 * Values:
mbed_official 324:406fd2029f23 855 * - 0 - Use the normal bit clock source.
mbed_official 324:406fd2029f23 856 * - 1 - Swap the bit clock source.
mbed_official 324:406fd2029f23 857 */
mbed_official 324:406fd2029f23 858 /*@{*/
mbed_official 324:406fd2029f23 859 #define BP_I2S_TCR2_BCS (29U) /*!< Bit position for I2S_TCR2_BCS. */
mbed_official 324:406fd2029f23 860 #define BM_I2S_TCR2_BCS (0x20000000U) /*!< Bit mask for I2S_TCR2_BCS. */
mbed_official 324:406fd2029f23 861 #define BS_I2S_TCR2_BCS (1U) /*!< Bit field size in bits for I2S_TCR2_BCS. */
mbed_official 324:406fd2029f23 862
mbed_official 324:406fd2029f23 863 /*! @brief Read current value of the I2S_TCR2_BCS field. */
mbed_official 324:406fd2029f23 864 #define BR_I2S_TCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS))
mbed_official 324:406fd2029f23 865
mbed_official 324:406fd2029f23 866 /*! @brief Format value for bitfield I2S_TCR2_BCS. */
mbed_official 324:406fd2029f23 867 #define BF_I2S_TCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_BCS) & BM_I2S_TCR2_BCS)
mbed_official 324:406fd2029f23 868
mbed_official 324:406fd2029f23 869 /*! @brief Set the BCS field to a new value. */
mbed_official 324:406fd2029f23 870 #define BW_I2S_TCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_TCR2_ADDR(x), BP_I2S_TCR2_BCS) = (v))
mbed_official 324:406fd2029f23 871 /*@}*/
mbed_official 324:406fd2029f23 872
mbed_official 324:406fd2029f23 873 /*!
mbed_official 324:406fd2029f23 874 * @name Register I2S_TCR2, field SYNC[31:30] (RW)
mbed_official 324:406fd2029f23 875 *
mbed_official 324:406fd2029f23 876 * Configures between asynchronous and synchronous modes of operation. When
mbed_official 324:406fd2029f23 877 * configured for a synchronous mode of operation, the receiver must be configured
mbed_official 324:406fd2029f23 878 * for asynchronous operation.
mbed_official 324:406fd2029f23 879 *
mbed_official 324:406fd2029f23 880 * Values:
mbed_official 324:406fd2029f23 881 * - 00 - Asynchronous mode.
mbed_official 324:406fd2029f23 882 * - 01 - Synchronous with receiver.
mbed_official 324:406fd2029f23 883 * - 10 - Synchronous with another SAI transmitter.
mbed_official 324:406fd2029f23 884 * - 11 - Synchronous with another SAI receiver.
mbed_official 324:406fd2029f23 885 */
mbed_official 324:406fd2029f23 886 /*@{*/
mbed_official 324:406fd2029f23 887 #define BP_I2S_TCR2_SYNC (30U) /*!< Bit position for I2S_TCR2_SYNC. */
mbed_official 324:406fd2029f23 888 #define BM_I2S_TCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_TCR2_SYNC. */
mbed_official 324:406fd2029f23 889 #define BS_I2S_TCR2_SYNC (2U) /*!< Bit field size in bits for I2S_TCR2_SYNC. */
mbed_official 324:406fd2029f23 890
mbed_official 324:406fd2029f23 891 /*! @brief Read current value of the I2S_TCR2_SYNC field. */
mbed_official 324:406fd2029f23 892 #define BR_I2S_TCR2_SYNC(x) (HW_I2S_TCR2(x).B.SYNC)
mbed_official 324:406fd2029f23 893
mbed_official 324:406fd2029f23 894 /*! @brief Format value for bitfield I2S_TCR2_SYNC. */
mbed_official 324:406fd2029f23 895 #define BF_I2S_TCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR2_SYNC) & BM_I2S_TCR2_SYNC)
mbed_official 324:406fd2029f23 896
mbed_official 324:406fd2029f23 897 /*! @brief Set the SYNC field to a new value. */
mbed_official 324:406fd2029f23 898 #define BW_I2S_TCR2_SYNC(x, v) (HW_I2S_TCR2_WR(x, (HW_I2S_TCR2_RD(x) & ~BM_I2S_TCR2_SYNC) | BF_I2S_TCR2_SYNC(v)))
mbed_official 324:406fd2029f23 899 /*@}*/
mbed_official 324:406fd2029f23 900
mbed_official 324:406fd2029f23 901 /*******************************************************************************
mbed_official 324:406fd2029f23 902 * HW_I2S_TCR3 - SAI Transmit Configuration 3 Register
mbed_official 324:406fd2029f23 903 ******************************************************************************/
mbed_official 324:406fd2029f23 904
mbed_official 324:406fd2029f23 905 /*!
mbed_official 324:406fd2029f23 906 * @brief HW_I2S_TCR3 - SAI Transmit Configuration 3 Register (RW)
mbed_official 324:406fd2029f23 907 *
mbed_official 324:406fd2029f23 908 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 909 */
mbed_official 324:406fd2029f23 910 typedef union _hw_i2s_tcr3
mbed_official 324:406fd2029f23 911 {
mbed_official 324:406fd2029f23 912 uint32_t U;
mbed_official 324:406fd2029f23 913 struct _hw_i2s_tcr3_bitfields
mbed_official 324:406fd2029f23 914 {
mbed_official 324:406fd2029f23 915 uint32_t WDFL : 4; /*!< [3:0] Word Flag Configuration */
mbed_official 324:406fd2029f23 916 uint32_t RESERVED0 : 12; /*!< [15:4] */
mbed_official 324:406fd2029f23 917 uint32_t TCE : 1; /*!< [16] Transmit Channel Enable */
mbed_official 324:406fd2029f23 918 uint32_t RESERVED1 : 15; /*!< [31:17] */
mbed_official 324:406fd2029f23 919 } B;
mbed_official 324:406fd2029f23 920 } hw_i2s_tcr3_t;
mbed_official 324:406fd2029f23 921
mbed_official 324:406fd2029f23 922 /*!
mbed_official 324:406fd2029f23 923 * @name Constants and macros for entire I2S_TCR3 register
mbed_official 324:406fd2029f23 924 */
mbed_official 324:406fd2029f23 925 /*@{*/
mbed_official 324:406fd2029f23 926 #define HW_I2S_TCR3_ADDR(x) ((x) + 0xCU)
mbed_official 324:406fd2029f23 927
mbed_official 324:406fd2029f23 928 #define HW_I2S_TCR3(x) (*(__IO hw_i2s_tcr3_t *) HW_I2S_TCR3_ADDR(x))
mbed_official 324:406fd2029f23 929 #define HW_I2S_TCR3_RD(x) (HW_I2S_TCR3(x).U)
mbed_official 324:406fd2029f23 930 #define HW_I2S_TCR3_WR(x, v) (HW_I2S_TCR3(x).U = (v))
mbed_official 324:406fd2029f23 931 #define HW_I2S_TCR3_SET(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) | (v)))
mbed_official 324:406fd2029f23 932 #define HW_I2S_TCR3_CLR(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 933 #define HW_I2S_TCR3_TOG(x, v) (HW_I2S_TCR3_WR(x, HW_I2S_TCR3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 934 /*@}*/
mbed_official 324:406fd2029f23 935
mbed_official 324:406fd2029f23 936 /*
mbed_official 324:406fd2029f23 937 * Constants & macros for individual I2S_TCR3 bitfields
mbed_official 324:406fd2029f23 938 */
mbed_official 324:406fd2029f23 939
mbed_official 324:406fd2029f23 940 /*!
mbed_official 324:406fd2029f23 941 * @name Register I2S_TCR3, field WDFL[3:0] (RW)
mbed_official 324:406fd2029f23 942 *
mbed_official 324:406fd2029f23 943 * Configures which word sets the start of word flag. The value written must be
mbed_official 324:406fd2029f23 944 * one less than the word number. For example, writing 0 configures the first
mbed_official 324:406fd2029f23 945 * word in the frame. When configured to a value greater than TCR4[FRSZ], then the
mbed_official 324:406fd2029f23 946 * start of word flag is never set.
mbed_official 324:406fd2029f23 947 */
mbed_official 324:406fd2029f23 948 /*@{*/
mbed_official 324:406fd2029f23 949 #define BP_I2S_TCR3_WDFL (0U) /*!< Bit position for I2S_TCR3_WDFL. */
mbed_official 324:406fd2029f23 950 #define BM_I2S_TCR3_WDFL (0x0000000FU) /*!< Bit mask for I2S_TCR3_WDFL. */
mbed_official 324:406fd2029f23 951 #define BS_I2S_TCR3_WDFL (4U) /*!< Bit field size in bits for I2S_TCR3_WDFL. */
mbed_official 324:406fd2029f23 952
mbed_official 324:406fd2029f23 953 /*! @brief Read current value of the I2S_TCR3_WDFL field. */
mbed_official 324:406fd2029f23 954 #define BR_I2S_TCR3_WDFL(x) (HW_I2S_TCR3(x).B.WDFL)
mbed_official 324:406fd2029f23 955
mbed_official 324:406fd2029f23 956 /*! @brief Format value for bitfield I2S_TCR3_WDFL. */
mbed_official 324:406fd2029f23 957 #define BF_I2S_TCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_WDFL) & BM_I2S_TCR3_WDFL)
mbed_official 324:406fd2029f23 958
mbed_official 324:406fd2029f23 959 /*! @brief Set the WDFL field to a new value. */
mbed_official 324:406fd2029f23 960 #define BW_I2S_TCR3_WDFL(x, v) (HW_I2S_TCR3_WR(x, (HW_I2S_TCR3_RD(x) & ~BM_I2S_TCR3_WDFL) | BF_I2S_TCR3_WDFL(v)))
mbed_official 324:406fd2029f23 961 /*@}*/
mbed_official 324:406fd2029f23 962
mbed_official 324:406fd2029f23 963 /*!
mbed_official 324:406fd2029f23 964 * @name Register I2S_TCR3, field TCE[16] (RW)
mbed_official 324:406fd2029f23 965 *
mbed_official 324:406fd2029f23 966 * Enables the corresponding data channel for transmit operation. A channel must
mbed_official 324:406fd2029f23 967 * be enabled before its FIFO is accessed. Changing this field will take effect
mbed_official 324:406fd2029f23 968 * immediately for generating the FIFO request and warning flags, but at the end
mbed_official 324:406fd2029f23 969 * of each frame for transmit operation.
mbed_official 324:406fd2029f23 970 *
mbed_official 324:406fd2029f23 971 * Values:
mbed_official 324:406fd2029f23 972 * - 0 - Transmit data channel N is disabled.
mbed_official 324:406fd2029f23 973 * - 1 - Transmit data channel N is enabled.
mbed_official 324:406fd2029f23 974 */
mbed_official 324:406fd2029f23 975 /*@{*/
mbed_official 324:406fd2029f23 976 #define BP_I2S_TCR3_TCE (16U) /*!< Bit position for I2S_TCR3_TCE. */
mbed_official 324:406fd2029f23 977 #define BM_I2S_TCR3_TCE (0x00010000U) /*!< Bit mask for I2S_TCR3_TCE. */
mbed_official 324:406fd2029f23 978 #define BS_I2S_TCR3_TCE (1U) /*!< Bit field size in bits for I2S_TCR3_TCE. */
mbed_official 324:406fd2029f23 979
mbed_official 324:406fd2029f23 980 /*! @brief Read current value of the I2S_TCR3_TCE field. */
mbed_official 324:406fd2029f23 981 #define BR_I2S_TCR3_TCE(x) (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE))
mbed_official 324:406fd2029f23 982
mbed_official 324:406fd2029f23 983 /*! @brief Format value for bitfield I2S_TCR3_TCE. */
mbed_official 324:406fd2029f23 984 #define BF_I2S_TCR3_TCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR3_TCE) & BM_I2S_TCR3_TCE)
mbed_official 324:406fd2029f23 985
mbed_official 324:406fd2029f23 986 /*! @brief Set the TCE field to a new value. */
mbed_official 324:406fd2029f23 987 #define BW_I2S_TCR3_TCE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR3_ADDR(x), BP_I2S_TCR3_TCE) = (v))
mbed_official 324:406fd2029f23 988 /*@}*/
mbed_official 324:406fd2029f23 989
mbed_official 324:406fd2029f23 990 /*******************************************************************************
mbed_official 324:406fd2029f23 991 * HW_I2S_TCR4 - SAI Transmit Configuration 4 Register
mbed_official 324:406fd2029f23 992 ******************************************************************************/
mbed_official 324:406fd2029f23 993
mbed_official 324:406fd2029f23 994 /*!
mbed_official 324:406fd2029f23 995 * @brief HW_I2S_TCR4 - SAI Transmit Configuration 4 Register (RW)
mbed_official 324:406fd2029f23 996 *
mbed_official 324:406fd2029f23 997 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 998 *
mbed_official 324:406fd2029f23 999 * This register must not be altered when TCSR[TE] is set.
mbed_official 324:406fd2029f23 1000 */
mbed_official 324:406fd2029f23 1001 typedef union _hw_i2s_tcr4
mbed_official 324:406fd2029f23 1002 {
mbed_official 324:406fd2029f23 1003 uint32_t U;
mbed_official 324:406fd2029f23 1004 struct _hw_i2s_tcr4_bitfields
mbed_official 324:406fd2029f23 1005 {
mbed_official 324:406fd2029f23 1006 uint32_t FSD : 1; /*!< [0] Frame Sync Direction */
mbed_official 324:406fd2029f23 1007 uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */
mbed_official 324:406fd2029f23 1008 uint32_t ONDEM : 1; /*!< [2] On Demand Mode */
mbed_official 324:406fd2029f23 1009 uint32_t FSE : 1; /*!< [3] Frame Sync Early */
mbed_official 324:406fd2029f23 1010 uint32_t MF : 1; /*!< [4] MSB First */
mbed_official 324:406fd2029f23 1011 uint32_t RESERVED0 : 3; /*!< [7:5] */
mbed_official 324:406fd2029f23 1012 uint32_t SYWD : 5; /*!< [12:8] Sync Width */
mbed_official 324:406fd2029f23 1013 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 1014 uint32_t FRSZ : 4; /*!< [19:16] Frame size */
mbed_official 324:406fd2029f23 1015 uint32_t RESERVED2 : 4; /*!< [23:20] */
mbed_official 324:406fd2029f23 1016 uint32_t FPACK : 2; /*!< [25:24] FIFO Packing Mode */
mbed_official 324:406fd2029f23 1017 uint32_t RESERVED3 : 2; /*!< [27:26] */
mbed_official 324:406fd2029f23 1018 uint32_t FCONT : 1; /*!< [28] FIFO Continue on Error */
mbed_official 324:406fd2029f23 1019 uint32_t RESERVED4 : 3; /*!< [31:29] */
mbed_official 324:406fd2029f23 1020 } B;
mbed_official 324:406fd2029f23 1021 } hw_i2s_tcr4_t;
mbed_official 324:406fd2029f23 1022
mbed_official 324:406fd2029f23 1023 /*!
mbed_official 324:406fd2029f23 1024 * @name Constants and macros for entire I2S_TCR4 register
mbed_official 324:406fd2029f23 1025 */
mbed_official 324:406fd2029f23 1026 /*@{*/
mbed_official 324:406fd2029f23 1027 #define HW_I2S_TCR4_ADDR(x) ((x) + 0x10U)
mbed_official 324:406fd2029f23 1028
mbed_official 324:406fd2029f23 1029 #define HW_I2S_TCR4(x) (*(__IO hw_i2s_tcr4_t *) HW_I2S_TCR4_ADDR(x))
mbed_official 324:406fd2029f23 1030 #define HW_I2S_TCR4_RD(x) (HW_I2S_TCR4(x).U)
mbed_official 324:406fd2029f23 1031 #define HW_I2S_TCR4_WR(x, v) (HW_I2S_TCR4(x).U = (v))
mbed_official 324:406fd2029f23 1032 #define HW_I2S_TCR4_SET(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) | (v)))
mbed_official 324:406fd2029f23 1033 #define HW_I2S_TCR4_CLR(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1034 #define HW_I2S_TCR4_TOG(x, v) (HW_I2S_TCR4_WR(x, HW_I2S_TCR4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1035 /*@}*/
mbed_official 324:406fd2029f23 1036
mbed_official 324:406fd2029f23 1037 /*
mbed_official 324:406fd2029f23 1038 * Constants & macros for individual I2S_TCR4 bitfields
mbed_official 324:406fd2029f23 1039 */
mbed_official 324:406fd2029f23 1040
mbed_official 324:406fd2029f23 1041 /*!
mbed_official 324:406fd2029f23 1042 * @name Register I2S_TCR4, field FSD[0] (RW)
mbed_official 324:406fd2029f23 1043 *
mbed_official 324:406fd2029f23 1044 * Configures the direction of the frame sync.
mbed_official 324:406fd2029f23 1045 *
mbed_official 324:406fd2029f23 1046 * Values:
mbed_official 324:406fd2029f23 1047 * - 0 - Frame sync is generated externally in Slave mode.
mbed_official 324:406fd2029f23 1048 * - 1 - Frame sync is generated internally in Master mode.
mbed_official 324:406fd2029f23 1049 */
mbed_official 324:406fd2029f23 1050 /*@{*/
mbed_official 324:406fd2029f23 1051 #define BP_I2S_TCR4_FSD (0U) /*!< Bit position for I2S_TCR4_FSD. */
mbed_official 324:406fd2029f23 1052 #define BM_I2S_TCR4_FSD (0x00000001U) /*!< Bit mask for I2S_TCR4_FSD. */
mbed_official 324:406fd2029f23 1053 #define BS_I2S_TCR4_FSD (1U) /*!< Bit field size in bits for I2S_TCR4_FSD. */
mbed_official 324:406fd2029f23 1054
mbed_official 324:406fd2029f23 1055 /*! @brief Read current value of the I2S_TCR4_FSD field. */
mbed_official 324:406fd2029f23 1056 #define BR_I2S_TCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD))
mbed_official 324:406fd2029f23 1057
mbed_official 324:406fd2029f23 1058 /*! @brief Format value for bitfield I2S_TCR4_FSD. */
mbed_official 324:406fd2029f23 1059 #define BF_I2S_TCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSD) & BM_I2S_TCR4_FSD)
mbed_official 324:406fd2029f23 1060
mbed_official 324:406fd2029f23 1061 /*! @brief Set the FSD field to a new value. */
mbed_official 324:406fd2029f23 1062 #define BW_I2S_TCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSD) = (v))
mbed_official 324:406fd2029f23 1063 /*@}*/
mbed_official 324:406fd2029f23 1064
mbed_official 324:406fd2029f23 1065 /*!
mbed_official 324:406fd2029f23 1066 * @name Register I2S_TCR4, field FSP[1] (RW)
mbed_official 324:406fd2029f23 1067 *
mbed_official 324:406fd2029f23 1068 * Configures the polarity of the frame sync.
mbed_official 324:406fd2029f23 1069 *
mbed_official 324:406fd2029f23 1070 * Values:
mbed_official 324:406fd2029f23 1071 * - 0 - Frame sync is active high.
mbed_official 324:406fd2029f23 1072 * - 1 - Frame sync is active low.
mbed_official 324:406fd2029f23 1073 */
mbed_official 324:406fd2029f23 1074 /*@{*/
mbed_official 324:406fd2029f23 1075 #define BP_I2S_TCR4_FSP (1U) /*!< Bit position for I2S_TCR4_FSP. */
mbed_official 324:406fd2029f23 1076 #define BM_I2S_TCR4_FSP (0x00000002U) /*!< Bit mask for I2S_TCR4_FSP. */
mbed_official 324:406fd2029f23 1077 #define BS_I2S_TCR4_FSP (1U) /*!< Bit field size in bits for I2S_TCR4_FSP. */
mbed_official 324:406fd2029f23 1078
mbed_official 324:406fd2029f23 1079 /*! @brief Read current value of the I2S_TCR4_FSP field. */
mbed_official 324:406fd2029f23 1080 #define BR_I2S_TCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP))
mbed_official 324:406fd2029f23 1081
mbed_official 324:406fd2029f23 1082 /*! @brief Format value for bitfield I2S_TCR4_FSP. */
mbed_official 324:406fd2029f23 1083 #define BF_I2S_TCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSP) & BM_I2S_TCR4_FSP)
mbed_official 324:406fd2029f23 1084
mbed_official 324:406fd2029f23 1085 /*! @brief Set the FSP field to a new value. */
mbed_official 324:406fd2029f23 1086 #define BW_I2S_TCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSP) = (v))
mbed_official 324:406fd2029f23 1087 /*@}*/
mbed_official 324:406fd2029f23 1088
mbed_official 324:406fd2029f23 1089 /*!
mbed_official 324:406fd2029f23 1090 * @name Register I2S_TCR4, field ONDEM[2] (RW)
mbed_official 324:406fd2029f23 1091 *
mbed_official 324:406fd2029f23 1092 * When set, and the frame sync is generated internally, a frame sync is only
mbed_official 324:406fd2029f23 1093 * generated when the FIFO warning flag is clear.
mbed_official 324:406fd2029f23 1094 *
mbed_official 324:406fd2029f23 1095 * Values:
mbed_official 324:406fd2029f23 1096 * - 0 - Internal frame sync is generated continuously.
mbed_official 324:406fd2029f23 1097 * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
mbed_official 324:406fd2029f23 1098 */
mbed_official 324:406fd2029f23 1099 /*@{*/
mbed_official 324:406fd2029f23 1100 #define BP_I2S_TCR4_ONDEM (2U) /*!< Bit position for I2S_TCR4_ONDEM. */
mbed_official 324:406fd2029f23 1101 #define BM_I2S_TCR4_ONDEM (0x00000004U) /*!< Bit mask for I2S_TCR4_ONDEM. */
mbed_official 324:406fd2029f23 1102 #define BS_I2S_TCR4_ONDEM (1U) /*!< Bit field size in bits for I2S_TCR4_ONDEM. */
mbed_official 324:406fd2029f23 1103
mbed_official 324:406fd2029f23 1104 /*! @brief Read current value of the I2S_TCR4_ONDEM field. */
mbed_official 324:406fd2029f23 1105 #define BR_I2S_TCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM))
mbed_official 324:406fd2029f23 1106
mbed_official 324:406fd2029f23 1107 /*! @brief Format value for bitfield I2S_TCR4_ONDEM. */
mbed_official 324:406fd2029f23 1108 #define BF_I2S_TCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_ONDEM) & BM_I2S_TCR4_ONDEM)
mbed_official 324:406fd2029f23 1109
mbed_official 324:406fd2029f23 1110 /*! @brief Set the ONDEM field to a new value. */
mbed_official 324:406fd2029f23 1111 #define BW_I2S_TCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_ONDEM) = (v))
mbed_official 324:406fd2029f23 1112 /*@}*/
mbed_official 324:406fd2029f23 1113
mbed_official 324:406fd2029f23 1114 /*!
mbed_official 324:406fd2029f23 1115 * @name Register I2S_TCR4, field FSE[3] (RW)
mbed_official 324:406fd2029f23 1116 *
mbed_official 324:406fd2029f23 1117 * Values:
mbed_official 324:406fd2029f23 1118 * - 0 - Frame sync asserts with the first bit of the frame.
mbed_official 324:406fd2029f23 1119 * - 1 - Frame sync asserts one bit before the first bit of the frame.
mbed_official 324:406fd2029f23 1120 */
mbed_official 324:406fd2029f23 1121 /*@{*/
mbed_official 324:406fd2029f23 1122 #define BP_I2S_TCR4_FSE (3U) /*!< Bit position for I2S_TCR4_FSE. */
mbed_official 324:406fd2029f23 1123 #define BM_I2S_TCR4_FSE (0x00000008U) /*!< Bit mask for I2S_TCR4_FSE. */
mbed_official 324:406fd2029f23 1124 #define BS_I2S_TCR4_FSE (1U) /*!< Bit field size in bits for I2S_TCR4_FSE. */
mbed_official 324:406fd2029f23 1125
mbed_official 324:406fd2029f23 1126 /*! @brief Read current value of the I2S_TCR4_FSE field. */
mbed_official 324:406fd2029f23 1127 #define BR_I2S_TCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE))
mbed_official 324:406fd2029f23 1128
mbed_official 324:406fd2029f23 1129 /*! @brief Format value for bitfield I2S_TCR4_FSE. */
mbed_official 324:406fd2029f23 1130 #define BF_I2S_TCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FSE) & BM_I2S_TCR4_FSE)
mbed_official 324:406fd2029f23 1131
mbed_official 324:406fd2029f23 1132 /*! @brief Set the FSE field to a new value. */
mbed_official 324:406fd2029f23 1133 #define BW_I2S_TCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FSE) = (v))
mbed_official 324:406fd2029f23 1134 /*@}*/
mbed_official 324:406fd2029f23 1135
mbed_official 324:406fd2029f23 1136 /*!
mbed_official 324:406fd2029f23 1137 * @name Register I2S_TCR4, field MF[4] (RW)
mbed_official 324:406fd2029f23 1138 *
mbed_official 324:406fd2029f23 1139 * Configures whether the LSB or the MSB is transmitted first.
mbed_official 324:406fd2029f23 1140 *
mbed_official 324:406fd2029f23 1141 * Values:
mbed_official 324:406fd2029f23 1142 * - 0 - LSB is transmitted first.
mbed_official 324:406fd2029f23 1143 * - 1 - MSB is transmitted first.
mbed_official 324:406fd2029f23 1144 */
mbed_official 324:406fd2029f23 1145 /*@{*/
mbed_official 324:406fd2029f23 1146 #define BP_I2S_TCR4_MF (4U) /*!< Bit position for I2S_TCR4_MF. */
mbed_official 324:406fd2029f23 1147 #define BM_I2S_TCR4_MF (0x00000010U) /*!< Bit mask for I2S_TCR4_MF. */
mbed_official 324:406fd2029f23 1148 #define BS_I2S_TCR4_MF (1U) /*!< Bit field size in bits for I2S_TCR4_MF. */
mbed_official 324:406fd2029f23 1149
mbed_official 324:406fd2029f23 1150 /*! @brief Read current value of the I2S_TCR4_MF field. */
mbed_official 324:406fd2029f23 1151 #define BR_I2S_TCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF))
mbed_official 324:406fd2029f23 1152
mbed_official 324:406fd2029f23 1153 /*! @brief Format value for bitfield I2S_TCR4_MF. */
mbed_official 324:406fd2029f23 1154 #define BF_I2S_TCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_MF) & BM_I2S_TCR4_MF)
mbed_official 324:406fd2029f23 1155
mbed_official 324:406fd2029f23 1156 /*! @brief Set the MF field to a new value. */
mbed_official 324:406fd2029f23 1157 #define BW_I2S_TCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_MF) = (v))
mbed_official 324:406fd2029f23 1158 /*@}*/
mbed_official 324:406fd2029f23 1159
mbed_official 324:406fd2029f23 1160 /*!
mbed_official 324:406fd2029f23 1161 * @name Register I2S_TCR4, field SYWD[12:8] (RW)
mbed_official 324:406fd2029f23 1162 *
mbed_official 324:406fd2029f23 1163 * Configures the length of the frame sync in number of bit clocks. The value
mbed_official 324:406fd2029f23 1164 * written must be one less than the number of bit clocks. For example, write 0 for
mbed_official 324:406fd2029f23 1165 * the frame sync to assert for one bit clock only. The sync width cannot be
mbed_official 324:406fd2029f23 1166 * configured longer than the first word of the frame.
mbed_official 324:406fd2029f23 1167 */
mbed_official 324:406fd2029f23 1168 /*@{*/
mbed_official 324:406fd2029f23 1169 #define BP_I2S_TCR4_SYWD (8U) /*!< Bit position for I2S_TCR4_SYWD. */
mbed_official 324:406fd2029f23 1170 #define BM_I2S_TCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_TCR4_SYWD. */
mbed_official 324:406fd2029f23 1171 #define BS_I2S_TCR4_SYWD (5U) /*!< Bit field size in bits for I2S_TCR4_SYWD. */
mbed_official 324:406fd2029f23 1172
mbed_official 324:406fd2029f23 1173 /*! @brief Read current value of the I2S_TCR4_SYWD field. */
mbed_official 324:406fd2029f23 1174 #define BR_I2S_TCR4_SYWD(x) (HW_I2S_TCR4(x).B.SYWD)
mbed_official 324:406fd2029f23 1175
mbed_official 324:406fd2029f23 1176 /*! @brief Format value for bitfield I2S_TCR4_SYWD. */
mbed_official 324:406fd2029f23 1177 #define BF_I2S_TCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_SYWD) & BM_I2S_TCR4_SYWD)
mbed_official 324:406fd2029f23 1178
mbed_official 324:406fd2029f23 1179 /*! @brief Set the SYWD field to a new value. */
mbed_official 324:406fd2029f23 1180 #define BW_I2S_TCR4_SYWD(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_SYWD) | BF_I2S_TCR4_SYWD(v)))
mbed_official 324:406fd2029f23 1181 /*@}*/
mbed_official 324:406fd2029f23 1182
mbed_official 324:406fd2029f23 1183 /*!
mbed_official 324:406fd2029f23 1184 * @name Register I2S_TCR4, field FRSZ[19:16] (RW)
mbed_official 324:406fd2029f23 1185 *
mbed_official 324:406fd2029f23 1186 * Configures the number of words in each frame. The value written must be one
mbed_official 324:406fd2029f23 1187 * less than the number of words in the frame. For example, write 0 for one word
mbed_official 324:406fd2029f23 1188 * per frame. The maximum supported frame size is 16 words.
mbed_official 324:406fd2029f23 1189 */
mbed_official 324:406fd2029f23 1190 /*@{*/
mbed_official 324:406fd2029f23 1191 #define BP_I2S_TCR4_FRSZ (16U) /*!< Bit position for I2S_TCR4_FRSZ. */
mbed_official 324:406fd2029f23 1192 #define BM_I2S_TCR4_FRSZ (0x000F0000U) /*!< Bit mask for I2S_TCR4_FRSZ. */
mbed_official 324:406fd2029f23 1193 #define BS_I2S_TCR4_FRSZ (4U) /*!< Bit field size in bits for I2S_TCR4_FRSZ. */
mbed_official 324:406fd2029f23 1194
mbed_official 324:406fd2029f23 1195 /*! @brief Read current value of the I2S_TCR4_FRSZ field. */
mbed_official 324:406fd2029f23 1196 #define BR_I2S_TCR4_FRSZ(x) (HW_I2S_TCR4(x).B.FRSZ)
mbed_official 324:406fd2029f23 1197
mbed_official 324:406fd2029f23 1198 /*! @brief Format value for bitfield I2S_TCR4_FRSZ. */
mbed_official 324:406fd2029f23 1199 #define BF_I2S_TCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FRSZ) & BM_I2S_TCR4_FRSZ)
mbed_official 324:406fd2029f23 1200
mbed_official 324:406fd2029f23 1201 /*! @brief Set the FRSZ field to a new value. */
mbed_official 324:406fd2029f23 1202 #define BW_I2S_TCR4_FRSZ(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FRSZ) | BF_I2S_TCR4_FRSZ(v)))
mbed_official 324:406fd2029f23 1203 /*@}*/
mbed_official 324:406fd2029f23 1204
mbed_official 324:406fd2029f23 1205 /*!
mbed_official 324:406fd2029f23 1206 * @name Register I2S_TCR4, field FPACK[25:24] (RW)
mbed_official 324:406fd2029f23 1207 *
mbed_official 324:406fd2029f23 1208 * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
mbed_official 324:406fd2029f23 1209 * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
mbed_official 324:406fd2029f23 1210 * 16-bits are loaded from the FIFO. The first word in each frame always starts with
mbed_official 324:406fd2029f23 1211 * a new 32-bit FIFO word and the first bit shifted must be configured within the
mbed_official 324:406fd2029f23 1212 * first packed word. When FIFO packing is enabled, the FIFO write pointer will
mbed_official 324:406fd2029f23 1213 * only increment when the full 32-bit FIFO word has been written by software.
mbed_official 324:406fd2029f23 1214 *
mbed_official 324:406fd2029f23 1215 * Values:
mbed_official 324:406fd2029f23 1216 * - 00 - FIFO packing is disabled
mbed_official 324:406fd2029f23 1217 * - 01 - Reserved
mbed_official 324:406fd2029f23 1218 * - 10 - 8-bit FIFO packing is enabled
mbed_official 324:406fd2029f23 1219 * - 11 - 16-bit FIFO packing is enabled
mbed_official 324:406fd2029f23 1220 */
mbed_official 324:406fd2029f23 1221 /*@{*/
mbed_official 324:406fd2029f23 1222 #define BP_I2S_TCR4_FPACK (24U) /*!< Bit position for I2S_TCR4_FPACK. */
mbed_official 324:406fd2029f23 1223 #define BM_I2S_TCR4_FPACK (0x03000000U) /*!< Bit mask for I2S_TCR4_FPACK. */
mbed_official 324:406fd2029f23 1224 #define BS_I2S_TCR4_FPACK (2U) /*!< Bit field size in bits for I2S_TCR4_FPACK. */
mbed_official 324:406fd2029f23 1225
mbed_official 324:406fd2029f23 1226 /*! @brief Read current value of the I2S_TCR4_FPACK field. */
mbed_official 324:406fd2029f23 1227 #define BR_I2S_TCR4_FPACK(x) (HW_I2S_TCR4(x).B.FPACK)
mbed_official 324:406fd2029f23 1228
mbed_official 324:406fd2029f23 1229 /*! @brief Format value for bitfield I2S_TCR4_FPACK. */
mbed_official 324:406fd2029f23 1230 #define BF_I2S_TCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FPACK) & BM_I2S_TCR4_FPACK)
mbed_official 324:406fd2029f23 1231
mbed_official 324:406fd2029f23 1232 /*! @brief Set the FPACK field to a new value. */
mbed_official 324:406fd2029f23 1233 #define BW_I2S_TCR4_FPACK(x, v) (HW_I2S_TCR4_WR(x, (HW_I2S_TCR4_RD(x) & ~BM_I2S_TCR4_FPACK) | BF_I2S_TCR4_FPACK(v)))
mbed_official 324:406fd2029f23 1234 /*@}*/
mbed_official 324:406fd2029f23 1235
mbed_official 324:406fd2029f23 1236 /*!
mbed_official 324:406fd2029f23 1237 * @name Register I2S_TCR4, field FCONT[28] (RW)
mbed_official 324:406fd2029f23 1238 *
mbed_official 324:406fd2029f23 1239 * Configures when the SAI will continue transmitting after a FIFO error has
mbed_official 324:406fd2029f23 1240 * been detected.
mbed_official 324:406fd2029f23 1241 *
mbed_official 324:406fd2029f23 1242 * Values:
mbed_official 324:406fd2029f23 1243 * - 0 - On FIFO error, the SAI will continue from the start of the next frame
mbed_official 324:406fd2029f23 1244 * after the FIFO error flag has been cleared.
mbed_official 324:406fd2029f23 1245 * - 1 - On FIFO error, the SAI will continue from the same word that caused the
mbed_official 324:406fd2029f23 1246 * FIFO error to set after the FIFO warning flag has been cleared.
mbed_official 324:406fd2029f23 1247 */
mbed_official 324:406fd2029f23 1248 /*@{*/
mbed_official 324:406fd2029f23 1249 #define BP_I2S_TCR4_FCONT (28U) /*!< Bit position for I2S_TCR4_FCONT. */
mbed_official 324:406fd2029f23 1250 #define BM_I2S_TCR4_FCONT (0x10000000U) /*!< Bit mask for I2S_TCR4_FCONT. */
mbed_official 324:406fd2029f23 1251 #define BS_I2S_TCR4_FCONT (1U) /*!< Bit field size in bits for I2S_TCR4_FCONT. */
mbed_official 324:406fd2029f23 1252
mbed_official 324:406fd2029f23 1253 /*! @brief Read current value of the I2S_TCR4_FCONT field. */
mbed_official 324:406fd2029f23 1254 #define BR_I2S_TCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT))
mbed_official 324:406fd2029f23 1255
mbed_official 324:406fd2029f23 1256 /*! @brief Format value for bitfield I2S_TCR4_FCONT. */
mbed_official 324:406fd2029f23 1257 #define BF_I2S_TCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR4_FCONT) & BM_I2S_TCR4_FCONT)
mbed_official 324:406fd2029f23 1258
mbed_official 324:406fd2029f23 1259 /*! @brief Set the FCONT field to a new value. */
mbed_official 324:406fd2029f23 1260 #define BW_I2S_TCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_TCR4_ADDR(x), BP_I2S_TCR4_FCONT) = (v))
mbed_official 324:406fd2029f23 1261 /*@}*/
mbed_official 324:406fd2029f23 1262
mbed_official 324:406fd2029f23 1263 /*******************************************************************************
mbed_official 324:406fd2029f23 1264 * HW_I2S_TCR5 - SAI Transmit Configuration 5 Register
mbed_official 324:406fd2029f23 1265 ******************************************************************************/
mbed_official 324:406fd2029f23 1266
mbed_official 324:406fd2029f23 1267 /*!
mbed_official 324:406fd2029f23 1268 * @brief HW_I2S_TCR5 - SAI Transmit Configuration 5 Register (RW)
mbed_official 324:406fd2029f23 1269 *
mbed_official 324:406fd2029f23 1270 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1271 *
mbed_official 324:406fd2029f23 1272 * This register must not be altered when TCSR[TE] is set.
mbed_official 324:406fd2029f23 1273 */
mbed_official 324:406fd2029f23 1274 typedef union _hw_i2s_tcr5
mbed_official 324:406fd2029f23 1275 {
mbed_official 324:406fd2029f23 1276 uint32_t U;
mbed_official 324:406fd2029f23 1277 struct _hw_i2s_tcr5_bitfields
mbed_official 324:406fd2029f23 1278 {
mbed_official 324:406fd2029f23 1279 uint32_t RESERVED0 : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1280 uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */
mbed_official 324:406fd2029f23 1281 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 1282 uint32_t W0W : 5; /*!< [20:16] Word 0 Width */
mbed_official 324:406fd2029f23 1283 uint32_t RESERVED2 : 3; /*!< [23:21] */
mbed_official 324:406fd2029f23 1284 uint32_t WNW : 5; /*!< [28:24] Word N Width */
mbed_official 324:406fd2029f23 1285 uint32_t RESERVED3 : 3; /*!< [31:29] */
mbed_official 324:406fd2029f23 1286 } B;
mbed_official 324:406fd2029f23 1287 } hw_i2s_tcr5_t;
mbed_official 324:406fd2029f23 1288
mbed_official 324:406fd2029f23 1289 /*!
mbed_official 324:406fd2029f23 1290 * @name Constants and macros for entire I2S_TCR5 register
mbed_official 324:406fd2029f23 1291 */
mbed_official 324:406fd2029f23 1292 /*@{*/
mbed_official 324:406fd2029f23 1293 #define HW_I2S_TCR5_ADDR(x) ((x) + 0x14U)
mbed_official 324:406fd2029f23 1294
mbed_official 324:406fd2029f23 1295 #define HW_I2S_TCR5(x) (*(__IO hw_i2s_tcr5_t *) HW_I2S_TCR5_ADDR(x))
mbed_official 324:406fd2029f23 1296 #define HW_I2S_TCR5_RD(x) (HW_I2S_TCR5(x).U)
mbed_official 324:406fd2029f23 1297 #define HW_I2S_TCR5_WR(x, v) (HW_I2S_TCR5(x).U = (v))
mbed_official 324:406fd2029f23 1298 #define HW_I2S_TCR5_SET(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) | (v)))
mbed_official 324:406fd2029f23 1299 #define HW_I2S_TCR5_CLR(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1300 #define HW_I2S_TCR5_TOG(x, v) (HW_I2S_TCR5_WR(x, HW_I2S_TCR5_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1301 /*@}*/
mbed_official 324:406fd2029f23 1302
mbed_official 324:406fd2029f23 1303 /*
mbed_official 324:406fd2029f23 1304 * Constants & macros for individual I2S_TCR5 bitfields
mbed_official 324:406fd2029f23 1305 */
mbed_official 324:406fd2029f23 1306
mbed_official 324:406fd2029f23 1307 /*!
mbed_official 324:406fd2029f23 1308 * @name Register I2S_TCR5, field FBT[12:8] (RW)
mbed_official 324:406fd2029f23 1309 *
mbed_official 324:406fd2029f23 1310 * Configures the bit index for the first bit transmitted for each word in the
mbed_official 324:406fd2029f23 1311 * frame. If configured for MSB First, the index of the next bit transmitted is
mbed_official 324:406fd2029f23 1312 * one less than the current bit transmitted. If configured for LSB First, the
mbed_official 324:406fd2029f23 1313 * index of the next bit transmitted is one more than the current bit transmitted.
mbed_official 324:406fd2029f23 1314 * The value written must be greater than or equal to the word width when
mbed_official 324:406fd2029f23 1315 * configured for MSB First. The value written must be less than or equal to 31-word width
mbed_official 324:406fd2029f23 1316 * when configured for LSB First.
mbed_official 324:406fd2029f23 1317 */
mbed_official 324:406fd2029f23 1318 /*@{*/
mbed_official 324:406fd2029f23 1319 #define BP_I2S_TCR5_FBT (8U) /*!< Bit position for I2S_TCR5_FBT. */
mbed_official 324:406fd2029f23 1320 #define BM_I2S_TCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_TCR5_FBT. */
mbed_official 324:406fd2029f23 1321 #define BS_I2S_TCR5_FBT (5U) /*!< Bit field size in bits for I2S_TCR5_FBT. */
mbed_official 324:406fd2029f23 1322
mbed_official 324:406fd2029f23 1323 /*! @brief Read current value of the I2S_TCR5_FBT field. */
mbed_official 324:406fd2029f23 1324 #define BR_I2S_TCR5_FBT(x) (HW_I2S_TCR5(x).B.FBT)
mbed_official 324:406fd2029f23 1325
mbed_official 324:406fd2029f23 1326 /*! @brief Format value for bitfield I2S_TCR5_FBT. */
mbed_official 324:406fd2029f23 1327 #define BF_I2S_TCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_FBT) & BM_I2S_TCR5_FBT)
mbed_official 324:406fd2029f23 1328
mbed_official 324:406fd2029f23 1329 /*! @brief Set the FBT field to a new value. */
mbed_official 324:406fd2029f23 1330 #define BW_I2S_TCR5_FBT(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_FBT) | BF_I2S_TCR5_FBT(v)))
mbed_official 324:406fd2029f23 1331 /*@}*/
mbed_official 324:406fd2029f23 1332
mbed_official 324:406fd2029f23 1333 /*!
mbed_official 324:406fd2029f23 1334 * @name Register I2S_TCR5, field W0W[20:16] (RW)
mbed_official 324:406fd2029f23 1335 *
mbed_official 324:406fd2029f23 1336 * Configures the number of bits in the first word in each frame. The value
mbed_official 324:406fd2029f23 1337 * written must be one less than the number of bits in the first word. Word width of
mbed_official 324:406fd2029f23 1338 * less than 8 bits is not supported if there is only one word per frame.
mbed_official 324:406fd2029f23 1339 */
mbed_official 324:406fd2029f23 1340 /*@{*/
mbed_official 324:406fd2029f23 1341 #define BP_I2S_TCR5_W0W (16U) /*!< Bit position for I2S_TCR5_W0W. */
mbed_official 324:406fd2029f23 1342 #define BM_I2S_TCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_TCR5_W0W. */
mbed_official 324:406fd2029f23 1343 #define BS_I2S_TCR5_W0W (5U) /*!< Bit field size in bits for I2S_TCR5_W0W. */
mbed_official 324:406fd2029f23 1344
mbed_official 324:406fd2029f23 1345 /*! @brief Read current value of the I2S_TCR5_W0W field. */
mbed_official 324:406fd2029f23 1346 #define BR_I2S_TCR5_W0W(x) (HW_I2S_TCR5(x).B.W0W)
mbed_official 324:406fd2029f23 1347
mbed_official 324:406fd2029f23 1348 /*! @brief Format value for bitfield I2S_TCR5_W0W. */
mbed_official 324:406fd2029f23 1349 #define BF_I2S_TCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_W0W) & BM_I2S_TCR5_W0W)
mbed_official 324:406fd2029f23 1350
mbed_official 324:406fd2029f23 1351 /*! @brief Set the W0W field to a new value. */
mbed_official 324:406fd2029f23 1352 #define BW_I2S_TCR5_W0W(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_W0W) | BF_I2S_TCR5_W0W(v)))
mbed_official 324:406fd2029f23 1353 /*@}*/
mbed_official 324:406fd2029f23 1354
mbed_official 324:406fd2029f23 1355 /*!
mbed_official 324:406fd2029f23 1356 * @name Register I2S_TCR5, field WNW[28:24] (RW)
mbed_official 324:406fd2029f23 1357 *
mbed_official 324:406fd2029f23 1358 * Configures the number of bits in each word, for each word except the first in
mbed_official 324:406fd2029f23 1359 * the frame. The value written must be one less than the number of bits per
mbed_official 324:406fd2029f23 1360 * word. Word width of less than 8 bits is not supported.
mbed_official 324:406fd2029f23 1361 */
mbed_official 324:406fd2029f23 1362 /*@{*/
mbed_official 324:406fd2029f23 1363 #define BP_I2S_TCR5_WNW (24U) /*!< Bit position for I2S_TCR5_WNW. */
mbed_official 324:406fd2029f23 1364 #define BM_I2S_TCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_TCR5_WNW. */
mbed_official 324:406fd2029f23 1365 #define BS_I2S_TCR5_WNW (5U) /*!< Bit field size in bits for I2S_TCR5_WNW. */
mbed_official 324:406fd2029f23 1366
mbed_official 324:406fd2029f23 1367 /*! @brief Read current value of the I2S_TCR5_WNW field. */
mbed_official 324:406fd2029f23 1368 #define BR_I2S_TCR5_WNW(x) (HW_I2S_TCR5(x).B.WNW)
mbed_official 324:406fd2029f23 1369
mbed_official 324:406fd2029f23 1370 /*! @brief Format value for bitfield I2S_TCR5_WNW. */
mbed_official 324:406fd2029f23 1371 #define BF_I2S_TCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TCR5_WNW) & BM_I2S_TCR5_WNW)
mbed_official 324:406fd2029f23 1372
mbed_official 324:406fd2029f23 1373 /*! @brief Set the WNW field to a new value. */
mbed_official 324:406fd2029f23 1374 #define BW_I2S_TCR5_WNW(x, v) (HW_I2S_TCR5_WR(x, (HW_I2S_TCR5_RD(x) & ~BM_I2S_TCR5_WNW) | BF_I2S_TCR5_WNW(v)))
mbed_official 324:406fd2029f23 1375 /*@}*/
mbed_official 324:406fd2029f23 1376
mbed_official 324:406fd2029f23 1377 /*******************************************************************************
mbed_official 324:406fd2029f23 1378 * HW_I2S_TDRn - SAI Transmit Data Register
mbed_official 324:406fd2029f23 1379 ******************************************************************************/
mbed_official 324:406fd2029f23 1380
mbed_official 324:406fd2029f23 1381 /*!
mbed_official 324:406fd2029f23 1382 * @brief HW_I2S_TDRn - SAI Transmit Data Register (WORZ)
mbed_official 324:406fd2029f23 1383 *
mbed_official 324:406fd2029f23 1384 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1385 */
mbed_official 324:406fd2029f23 1386 typedef union _hw_i2s_tdrn
mbed_official 324:406fd2029f23 1387 {
mbed_official 324:406fd2029f23 1388 uint32_t U;
mbed_official 324:406fd2029f23 1389 struct _hw_i2s_tdrn_bitfields
mbed_official 324:406fd2029f23 1390 {
mbed_official 324:406fd2029f23 1391 uint32_t TDR : 32; /*!< [31:0] Transmit Data Register */
mbed_official 324:406fd2029f23 1392 } B;
mbed_official 324:406fd2029f23 1393 } hw_i2s_tdrn_t;
mbed_official 324:406fd2029f23 1394
mbed_official 324:406fd2029f23 1395 /*!
mbed_official 324:406fd2029f23 1396 * @name Constants and macros for entire I2S_TDRn register
mbed_official 324:406fd2029f23 1397 */
mbed_official 324:406fd2029f23 1398 /*@{*/
mbed_official 324:406fd2029f23 1399 #define HW_I2S_TDRn_COUNT (1U)
mbed_official 324:406fd2029f23 1400
mbed_official 324:406fd2029f23 1401 #define HW_I2S_TDRn_ADDR(x, n) ((x) + 0x20U + (0x4U * (n)))
mbed_official 324:406fd2029f23 1402
mbed_official 324:406fd2029f23 1403 #define HW_I2S_TDRn(x, n) (*(__O hw_i2s_tdrn_t *) HW_I2S_TDRn_ADDR(x, n))
mbed_official 324:406fd2029f23 1404 #define HW_I2S_TDRn_RD(x, n) (HW_I2S_TDRn(x, n).U)
mbed_official 324:406fd2029f23 1405 #define HW_I2S_TDRn_WR(x, n, v) (HW_I2S_TDRn(x, n).U = (v))
mbed_official 324:406fd2029f23 1406 /*@}*/
mbed_official 324:406fd2029f23 1407
mbed_official 324:406fd2029f23 1408 /*
mbed_official 324:406fd2029f23 1409 * Constants & macros for individual I2S_TDRn bitfields
mbed_official 324:406fd2029f23 1410 */
mbed_official 324:406fd2029f23 1411
mbed_official 324:406fd2029f23 1412 /*!
mbed_official 324:406fd2029f23 1413 * @name Register I2S_TDRn, field TDR[31:0] (WORZ)
mbed_official 324:406fd2029f23 1414 *
mbed_official 324:406fd2029f23 1415 * The corresponding TCR3[TCE] bit must be set before accessing the channel's
mbed_official 324:406fd2029f23 1416 * transmit data register. Writes to this register when the transmit FIFO is not
mbed_official 324:406fd2029f23 1417 * full will push the data written into the transmit data FIFO. Writes to this
mbed_official 324:406fd2029f23 1418 * register when the transmit FIFO is full are ignored.
mbed_official 324:406fd2029f23 1419 */
mbed_official 324:406fd2029f23 1420 /*@{*/
mbed_official 324:406fd2029f23 1421 #define BP_I2S_TDRn_TDR (0U) /*!< Bit position for I2S_TDRn_TDR. */
mbed_official 324:406fd2029f23 1422 #define BM_I2S_TDRn_TDR (0xFFFFFFFFU) /*!< Bit mask for I2S_TDRn_TDR. */
mbed_official 324:406fd2029f23 1423 #define BS_I2S_TDRn_TDR (32U) /*!< Bit field size in bits for I2S_TDRn_TDR. */
mbed_official 324:406fd2029f23 1424
mbed_official 324:406fd2029f23 1425 /*! @brief Format value for bitfield I2S_TDRn_TDR. */
mbed_official 324:406fd2029f23 1426 #define BF_I2S_TDRn_TDR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TDRn_TDR) & BM_I2S_TDRn_TDR)
mbed_official 324:406fd2029f23 1427
mbed_official 324:406fd2029f23 1428 /*! @brief Set the TDR field to a new value. */
mbed_official 324:406fd2029f23 1429 #define BW_I2S_TDRn_TDR(x, n, v) (HW_I2S_TDRn_WR(x, n, v))
mbed_official 324:406fd2029f23 1430 /*@}*/
mbed_official 324:406fd2029f23 1431
mbed_official 324:406fd2029f23 1432 /*******************************************************************************
mbed_official 324:406fd2029f23 1433 * HW_I2S_TFRn - SAI Transmit FIFO Register
mbed_official 324:406fd2029f23 1434 ******************************************************************************/
mbed_official 324:406fd2029f23 1435
mbed_official 324:406fd2029f23 1436 /*!
mbed_official 324:406fd2029f23 1437 * @brief HW_I2S_TFRn - SAI Transmit FIFO Register (RO)
mbed_official 324:406fd2029f23 1438 *
mbed_official 324:406fd2029f23 1439 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1440 *
mbed_official 324:406fd2029f23 1441 * The MSB of the read and write pointers is used to distinguish between FIFO
mbed_official 324:406fd2029f23 1442 * full and empty conditions. If the read and write pointers are identical, then
mbed_official 324:406fd2029f23 1443 * the FIFO is empty. If the read and write pointers are identical except for the
mbed_official 324:406fd2029f23 1444 * MSB, then the FIFO is full.
mbed_official 324:406fd2029f23 1445 */
mbed_official 324:406fd2029f23 1446 typedef union _hw_i2s_tfrn
mbed_official 324:406fd2029f23 1447 {
mbed_official 324:406fd2029f23 1448 uint32_t U;
mbed_official 324:406fd2029f23 1449 struct _hw_i2s_tfrn_bitfields
mbed_official 324:406fd2029f23 1450 {
mbed_official 324:406fd2029f23 1451 uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */
mbed_official 324:406fd2029f23 1452 uint32_t RESERVED0 : 12; /*!< [15:4] */
mbed_official 324:406fd2029f23 1453 uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */
mbed_official 324:406fd2029f23 1454 uint32_t RESERVED1 : 12; /*!< [31:20] */
mbed_official 324:406fd2029f23 1455 } B;
mbed_official 324:406fd2029f23 1456 } hw_i2s_tfrn_t;
mbed_official 324:406fd2029f23 1457
mbed_official 324:406fd2029f23 1458 /*!
mbed_official 324:406fd2029f23 1459 * @name Constants and macros for entire I2S_TFRn register
mbed_official 324:406fd2029f23 1460 */
mbed_official 324:406fd2029f23 1461 /*@{*/
mbed_official 324:406fd2029f23 1462 #define HW_I2S_TFRn_COUNT (1U)
mbed_official 324:406fd2029f23 1463
mbed_official 324:406fd2029f23 1464 #define HW_I2S_TFRn_ADDR(x, n) ((x) + 0x40U + (0x4U * (n)))
mbed_official 324:406fd2029f23 1465
mbed_official 324:406fd2029f23 1466 #define HW_I2S_TFRn(x, n) (*(__I hw_i2s_tfrn_t *) HW_I2S_TFRn_ADDR(x, n))
mbed_official 324:406fd2029f23 1467 #define HW_I2S_TFRn_RD(x, n) (HW_I2S_TFRn(x, n).U)
mbed_official 324:406fd2029f23 1468 /*@}*/
mbed_official 324:406fd2029f23 1469
mbed_official 324:406fd2029f23 1470 /*
mbed_official 324:406fd2029f23 1471 * Constants & macros for individual I2S_TFRn bitfields
mbed_official 324:406fd2029f23 1472 */
mbed_official 324:406fd2029f23 1473
mbed_official 324:406fd2029f23 1474 /*!
mbed_official 324:406fd2029f23 1475 * @name Register I2S_TFRn, field RFP[3:0] (RO)
mbed_official 324:406fd2029f23 1476 *
mbed_official 324:406fd2029f23 1477 * FIFO read pointer for transmit data channel.
mbed_official 324:406fd2029f23 1478 */
mbed_official 324:406fd2029f23 1479 /*@{*/
mbed_official 324:406fd2029f23 1480 #define BP_I2S_TFRn_RFP (0U) /*!< Bit position for I2S_TFRn_RFP. */
mbed_official 324:406fd2029f23 1481 #define BM_I2S_TFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_TFRn_RFP. */
mbed_official 324:406fd2029f23 1482 #define BS_I2S_TFRn_RFP (4U) /*!< Bit field size in bits for I2S_TFRn_RFP. */
mbed_official 324:406fd2029f23 1483
mbed_official 324:406fd2029f23 1484 /*! @brief Read current value of the I2S_TFRn_RFP field. */
mbed_official 324:406fd2029f23 1485 #define BR_I2S_TFRn_RFP(x, n) (HW_I2S_TFRn(x, n).B.RFP)
mbed_official 324:406fd2029f23 1486 /*@}*/
mbed_official 324:406fd2029f23 1487
mbed_official 324:406fd2029f23 1488 /*!
mbed_official 324:406fd2029f23 1489 * @name Register I2S_TFRn, field WFP[19:16] (RO)
mbed_official 324:406fd2029f23 1490 *
mbed_official 324:406fd2029f23 1491 * FIFO write pointer for transmit data channel.
mbed_official 324:406fd2029f23 1492 */
mbed_official 324:406fd2029f23 1493 /*@{*/
mbed_official 324:406fd2029f23 1494 #define BP_I2S_TFRn_WFP (16U) /*!< Bit position for I2S_TFRn_WFP. */
mbed_official 324:406fd2029f23 1495 #define BM_I2S_TFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_TFRn_WFP. */
mbed_official 324:406fd2029f23 1496 #define BS_I2S_TFRn_WFP (4U) /*!< Bit field size in bits for I2S_TFRn_WFP. */
mbed_official 324:406fd2029f23 1497
mbed_official 324:406fd2029f23 1498 /*! @brief Read current value of the I2S_TFRn_WFP field. */
mbed_official 324:406fd2029f23 1499 #define BR_I2S_TFRn_WFP(x, n) (HW_I2S_TFRn(x, n).B.WFP)
mbed_official 324:406fd2029f23 1500 /*@}*/
mbed_official 324:406fd2029f23 1501
mbed_official 324:406fd2029f23 1502 /*******************************************************************************
mbed_official 324:406fd2029f23 1503 * HW_I2S_TMR - SAI Transmit Mask Register
mbed_official 324:406fd2029f23 1504 ******************************************************************************/
mbed_official 324:406fd2029f23 1505
mbed_official 324:406fd2029f23 1506 /*!
mbed_official 324:406fd2029f23 1507 * @brief HW_I2S_TMR - SAI Transmit Mask Register (RW)
mbed_official 324:406fd2029f23 1508 *
mbed_official 324:406fd2029f23 1509 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1510 *
mbed_official 324:406fd2029f23 1511 * This register is double-buffered and updates: When TCSR[TE] is first set At
mbed_official 324:406fd2029f23 1512 * the end of each frame. This allows the masked words in each frame to change
mbed_official 324:406fd2029f23 1513 * from frame to frame.
mbed_official 324:406fd2029f23 1514 */
mbed_official 324:406fd2029f23 1515 typedef union _hw_i2s_tmr
mbed_official 324:406fd2029f23 1516 {
mbed_official 324:406fd2029f23 1517 uint32_t U;
mbed_official 324:406fd2029f23 1518 struct _hw_i2s_tmr_bitfields
mbed_official 324:406fd2029f23 1519 {
mbed_official 324:406fd2029f23 1520 uint32_t TWM : 16; /*!< [15:0] Transmit Word Mask */
mbed_official 324:406fd2029f23 1521 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 1522 } B;
mbed_official 324:406fd2029f23 1523 } hw_i2s_tmr_t;
mbed_official 324:406fd2029f23 1524
mbed_official 324:406fd2029f23 1525 /*!
mbed_official 324:406fd2029f23 1526 * @name Constants and macros for entire I2S_TMR register
mbed_official 324:406fd2029f23 1527 */
mbed_official 324:406fd2029f23 1528 /*@{*/
mbed_official 324:406fd2029f23 1529 #define HW_I2S_TMR_ADDR(x) ((x) + 0x60U)
mbed_official 324:406fd2029f23 1530
mbed_official 324:406fd2029f23 1531 #define HW_I2S_TMR(x) (*(__IO hw_i2s_tmr_t *) HW_I2S_TMR_ADDR(x))
mbed_official 324:406fd2029f23 1532 #define HW_I2S_TMR_RD(x) (HW_I2S_TMR(x).U)
mbed_official 324:406fd2029f23 1533 #define HW_I2S_TMR_WR(x, v) (HW_I2S_TMR(x).U = (v))
mbed_official 324:406fd2029f23 1534 #define HW_I2S_TMR_SET(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) | (v)))
mbed_official 324:406fd2029f23 1535 #define HW_I2S_TMR_CLR(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1536 #define HW_I2S_TMR_TOG(x, v) (HW_I2S_TMR_WR(x, HW_I2S_TMR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1537 /*@}*/
mbed_official 324:406fd2029f23 1538
mbed_official 324:406fd2029f23 1539 /*
mbed_official 324:406fd2029f23 1540 * Constants & macros for individual I2S_TMR bitfields
mbed_official 324:406fd2029f23 1541 */
mbed_official 324:406fd2029f23 1542
mbed_official 324:406fd2029f23 1543 /*!
mbed_official 324:406fd2029f23 1544 * @name Register I2S_TMR, field TWM[15:0] (RW)
mbed_official 324:406fd2029f23 1545 *
mbed_official 324:406fd2029f23 1546 * Configures whether the transmit word is masked (transmit data pin tristated
mbed_official 324:406fd2029f23 1547 * and transmit data not read from FIFO) for the corresponding word in the frame.
mbed_official 324:406fd2029f23 1548 *
mbed_official 324:406fd2029f23 1549 * Values:
mbed_official 324:406fd2029f23 1550 * - 0 - Word N is enabled.
mbed_official 324:406fd2029f23 1551 * - 1 - Word N is masked. The transmit data pins are tri-stated when masked.
mbed_official 324:406fd2029f23 1552 */
mbed_official 324:406fd2029f23 1553 /*@{*/
mbed_official 324:406fd2029f23 1554 #define BP_I2S_TMR_TWM (0U) /*!< Bit position for I2S_TMR_TWM. */
mbed_official 324:406fd2029f23 1555 #define BM_I2S_TMR_TWM (0x0000FFFFU) /*!< Bit mask for I2S_TMR_TWM. */
mbed_official 324:406fd2029f23 1556 #define BS_I2S_TMR_TWM (16U) /*!< Bit field size in bits for I2S_TMR_TWM. */
mbed_official 324:406fd2029f23 1557
mbed_official 324:406fd2029f23 1558 /*! @brief Read current value of the I2S_TMR_TWM field. */
mbed_official 324:406fd2029f23 1559 #define BR_I2S_TMR_TWM(x) (HW_I2S_TMR(x).B.TWM)
mbed_official 324:406fd2029f23 1560
mbed_official 324:406fd2029f23 1561 /*! @brief Format value for bitfield I2S_TMR_TWM. */
mbed_official 324:406fd2029f23 1562 #define BF_I2S_TMR_TWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_TMR_TWM) & BM_I2S_TMR_TWM)
mbed_official 324:406fd2029f23 1563
mbed_official 324:406fd2029f23 1564 /*! @brief Set the TWM field to a new value. */
mbed_official 324:406fd2029f23 1565 #define BW_I2S_TMR_TWM(x, v) (HW_I2S_TMR_WR(x, (HW_I2S_TMR_RD(x) & ~BM_I2S_TMR_TWM) | BF_I2S_TMR_TWM(v)))
mbed_official 324:406fd2029f23 1566 /*@}*/
mbed_official 324:406fd2029f23 1567
mbed_official 324:406fd2029f23 1568 /*******************************************************************************
mbed_official 324:406fd2029f23 1569 * HW_I2S_RCSR - SAI Receive Control Register
mbed_official 324:406fd2029f23 1570 ******************************************************************************/
mbed_official 324:406fd2029f23 1571
mbed_official 324:406fd2029f23 1572 /*!
mbed_official 324:406fd2029f23 1573 * @brief HW_I2S_RCSR - SAI Receive Control Register (RW)
mbed_official 324:406fd2029f23 1574 *
mbed_official 324:406fd2029f23 1575 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1576 */
mbed_official 324:406fd2029f23 1577 typedef union _hw_i2s_rcsr
mbed_official 324:406fd2029f23 1578 {
mbed_official 324:406fd2029f23 1579 uint32_t U;
mbed_official 324:406fd2029f23 1580 struct _hw_i2s_rcsr_bitfields
mbed_official 324:406fd2029f23 1581 {
mbed_official 324:406fd2029f23 1582 uint32_t FRDE : 1; /*!< [0] FIFO Request DMA Enable */
mbed_official 324:406fd2029f23 1583 uint32_t FWDE : 1; /*!< [1] FIFO Warning DMA Enable */
mbed_official 324:406fd2029f23 1584 uint32_t RESERVED0 : 6; /*!< [7:2] */
mbed_official 324:406fd2029f23 1585 uint32_t FRIE : 1; /*!< [8] FIFO Request Interrupt Enable */
mbed_official 324:406fd2029f23 1586 uint32_t FWIE : 1; /*!< [9] FIFO Warning Interrupt Enable */
mbed_official 324:406fd2029f23 1587 uint32_t FEIE : 1; /*!< [10] FIFO Error Interrupt Enable */
mbed_official 324:406fd2029f23 1588 uint32_t SEIE : 1; /*!< [11] Sync Error Interrupt Enable */
mbed_official 324:406fd2029f23 1589 uint32_t WSIE : 1; /*!< [12] Word Start Interrupt Enable */
mbed_official 324:406fd2029f23 1590 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 1591 uint32_t FRF : 1; /*!< [16] FIFO Request Flag */
mbed_official 324:406fd2029f23 1592 uint32_t FWF : 1; /*!< [17] FIFO Warning Flag */
mbed_official 324:406fd2029f23 1593 uint32_t FEF : 1; /*!< [18] FIFO Error Flag */
mbed_official 324:406fd2029f23 1594 uint32_t SEF : 1; /*!< [19] Sync Error Flag */
mbed_official 324:406fd2029f23 1595 uint32_t WSF : 1; /*!< [20] Word Start Flag */
mbed_official 324:406fd2029f23 1596 uint32_t RESERVED2 : 3; /*!< [23:21] */
mbed_official 324:406fd2029f23 1597 uint32_t SR : 1; /*!< [24] Software Reset */
mbed_official 324:406fd2029f23 1598 uint32_t FR : 1; /*!< [25] FIFO Reset */
mbed_official 324:406fd2029f23 1599 uint32_t RESERVED3 : 2; /*!< [27:26] */
mbed_official 324:406fd2029f23 1600 uint32_t BCE : 1; /*!< [28] Bit Clock Enable */
mbed_official 324:406fd2029f23 1601 uint32_t DBGE : 1; /*!< [29] Debug Enable */
mbed_official 324:406fd2029f23 1602 uint32_t STOPE : 1; /*!< [30] Stop Enable */
mbed_official 324:406fd2029f23 1603 uint32_t RE : 1; /*!< [31] Receiver Enable */
mbed_official 324:406fd2029f23 1604 } B;
mbed_official 324:406fd2029f23 1605 } hw_i2s_rcsr_t;
mbed_official 324:406fd2029f23 1606
mbed_official 324:406fd2029f23 1607 /*!
mbed_official 324:406fd2029f23 1608 * @name Constants and macros for entire I2S_RCSR register
mbed_official 324:406fd2029f23 1609 */
mbed_official 324:406fd2029f23 1610 /*@{*/
mbed_official 324:406fd2029f23 1611 #define HW_I2S_RCSR_ADDR(x) ((x) + 0x80U)
mbed_official 324:406fd2029f23 1612
mbed_official 324:406fd2029f23 1613 #define HW_I2S_RCSR(x) (*(__IO hw_i2s_rcsr_t *) HW_I2S_RCSR_ADDR(x))
mbed_official 324:406fd2029f23 1614 #define HW_I2S_RCSR_RD(x) (HW_I2S_RCSR(x).U)
mbed_official 324:406fd2029f23 1615 #define HW_I2S_RCSR_WR(x, v) (HW_I2S_RCSR(x).U = (v))
mbed_official 324:406fd2029f23 1616 #define HW_I2S_RCSR_SET(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) | (v)))
mbed_official 324:406fd2029f23 1617 #define HW_I2S_RCSR_CLR(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1618 #define HW_I2S_RCSR_TOG(x, v) (HW_I2S_RCSR_WR(x, HW_I2S_RCSR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1619 /*@}*/
mbed_official 324:406fd2029f23 1620
mbed_official 324:406fd2029f23 1621 /*
mbed_official 324:406fd2029f23 1622 * Constants & macros for individual I2S_RCSR bitfields
mbed_official 324:406fd2029f23 1623 */
mbed_official 324:406fd2029f23 1624
mbed_official 324:406fd2029f23 1625 /*!
mbed_official 324:406fd2029f23 1626 * @name Register I2S_RCSR, field FRDE[0] (RW)
mbed_official 324:406fd2029f23 1627 *
mbed_official 324:406fd2029f23 1628 * Enables/disables DMA requests.
mbed_official 324:406fd2029f23 1629 *
mbed_official 324:406fd2029f23 1630 * Values:
mbed_official 324:406fd2029f23 1631 * - 0 - Disables the DMA request.
mbed_official 324:406fd2029f23 1632 * - 1 - Enables the DMA request.
mbed_official 324:406fd2029f23 1633 */
mbed_official 324:406fd2029f23 1634 /*@{*/
mbed_official 324:406fd2029f23 1635 #define BP_I2S_RCSR_FRDE (0U) /*!< Bit position for I2S_RCSR_FRDE. */
mbed_official 324:406fd2029f23 1636 #define BM_I2S_RCSR_FRDE (0x00000001U) /*!< Bit mask for I2S_RCSR_FRDE. */
mbed_official 324:406fd2029f23 1637 #define BS_I2S_RCSR_FRDE (1U) /*!< Bit field size in bits for I2S_RCSR_FRDE. */
mbed_official 324:406fd2029f23 1638
mbed_official 324:406fd2029f23 1639 /*! @brief Read current value of the I2S_RCSR_FRDE field. */
mbed_official 324:406fd2029f23 1640 #define BR_I2S_RCSR_FRDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE))
mbed_official 324:406fd2029f23 1641
mbed_official 324:406fd2029f23 1642 /*! @brief Format value for bitfield I2S_RCSR_FRDE. */
mbed_official 324:406fd2029f23 1643 #define BF_I2S_RCSR_FRDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRDE) & BM_I2S_RCSR_FRDE)
mbed_official 324:406fd2029f23 1644
mbed_official 324:406fd2029f23 1645 /*! @brief Set the FRDE field to a new value. */
mbed_official 324:406fd2029f23 1646 #define BW_I2S_RCSR_FRDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRDE) = (v))
mbed_official 324:406fd2029f23 1647 /*@}*/
mbed_official 324:406fd2029f23 1648
mbed_official 324:406fd2029f23 1649 /*!
mbed_official 324:406fd2029f23 1650 * @name Register I2S_RCSR, field FWDE[1] (RW)
mbed_official 324:406fd2029f23 1651 *
mbed_official 324:406fd2029f23 1652 * Enables/disables DMA requests.
mbed_official 324:406fd2029f23 1653 *
mbed_official 324:406fd2029f23 1654 * Values:
mbed_official 324:406fd2029f23 1655 * - 0 - Disables the DMA request.
mbed_official 324:406fd2029f23 1656 * - 1 - Enables the DMA request.
mbed_official 324:406fd2029f23 1657 */
mbed_official 324:406fd2029f23 1658 /*@{*/
mbed_official 324:406fd2029f23 1659 #define BP_I2S_RCSR_FWDE (1U) /*!< Bit position for I2S_RCSR_FWDE. */
mbed_official 324:406fd2029f23 1660 #define BM_I2S_RCSR_FWDE (0x00000002U) /*!< Bit mask for I2S_RCSR_FWDE. */
mbed_official 324:406fd2029f23 1661 #define BS_I2S_RCSR_FWDE (1U) /*!< Bit field size in bits for I2S_RCSR_FWDE. */
mbed_official 324:406fd2029f23 1662
mbed_official 324:406fd2029f23 1663 /*! @brief Read current value of the I2S_RCSR_FWDE field. */
mbed_official 324:406fd2029f23 1664 #define BR_I2S_RCSR_FWDE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE))
mbed_official 324:406fd2029f23 1665
mbed_official 324:406fd2029f23 1666 /*! @brief Format value for bitfield I2S_RCSR_FWDE. */
mbed_official 324:406fd2029f23 1667 #define BF_I2S_RCSR_FWDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWDE) & BM_I2S_RCSR_FWDE)
mbed_official 324:406fd2029f23 1668
mbed_official 324:406fd2029f23 1669 /*! @brief Set the FWDE field to a new value. */
mbed_official 324:406fd2029f23 1670 #define BW_I2S_RCSR_FWDE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWDE) = (v))
mbed_official 324:406fd2029f23 1671 /*@}*/
mbed_official 324:406fd2029f23 1672
mbed_official 324:406fd2029f23 1673 /*!
mbed_official 324:406fd2029f23 1674 * @name Register I2S_RCSR, field FRIE[8] (RW)
mbed_official 324:406fd2029f23 1675 *
mbed_official 324:406fd2029f23 1676 * Enables/disables FIFO request interrupts.
mbed_official 324:406fd2029f23 1677 *
mbed_official 324:406fd2029f23 1678 * Values:
mbed_official 324:406fd2029f23 1679 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 1680 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 1681 */
mbed_official 324:406fd2029f23 1682 /*@{*/
mbed_official 324:406fd2029f23 1683 #define BP_I2S_RCSR_FRIE (8U) /*!< Bit position for I2S_RCSR_FRIE. */
mbed_official 324:406fd2029f23 1684 #define BM_I2S_RCSR_FRIE (0x00000100U) /*!< Bit mask for I2S_RCSR_FRIE. */
mbed_official 324:406fd2029f23 1685 #define BS_I2S_RCSR_FRIE (1U) /*!< Bit field size in bits for I2S_RCSR_FRIE. */
mbed_official 324:406fd2029f23 1686
mbed_official 324:406fd2029f23 1687 /*! @brief Read current value of the I2S_RCSR_FRIE field. */
mbed_official 324:406fd2029f23 1688 #define BR_I2S_RCSR_FRIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE))
mbed_official 324:406fd2029f23 1689
mbed_official 324:406fd2029f23 1690 /*! @brief Format value for bitfield I2S_RCSR_FRIE. */
mbed_official 324:406fd2029f23 1691 #define BF_I2S_RCSR_FRIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FRIE) & BM_I2S_RCSR_FRIE)
mbed_official 324:406fd2029f23 1692
mbed_official 324:406fd2029f23 1693 /*! @brief Set the FRIE field to a new value. */
mbed_official 324:406fd2029f23 1694 #define BW_I2S_RCSR_FRIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRIE) = (v))
mbed_official 324:406fd2029f23 1695 /*@}*/
mbed_official 324:406fd2029f23 1696
mbed_official 324:406fd2029f23 1697 /*!
mbed_official 324:406fd2029f23 1698 * @name Register I2S_RCSR, field FWIE[9] (RW)
mbed_official 324:406fd2029f23 1699 *
mbed_official 324:406fd2029f23 1700 * Enables/disables FIFO warning interrupts.
mbed_official 324:406fd2029f23 1701 *
mbed_official 324:406fd2029f23 1702 * Values:
mbed_official 324:406fd2029f23 1703 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 1704 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 1705 */
mbed_official 324:406fd2029f23 1706 /*@{*/
mbed_official 324:406fd2029f23 1707 #define BP_I2S_RCSR_FWIE (9U) /*!< Bit position for I2S_RCSR_FWIE. */
mbed_official 324:406fd2029f23 1708 #define BM_I2S_RCSR_FWIE (0x00000200U) /*!< Bit mask for I2S_RCSR_FWIE. */
mbed_official 324:406fd2029f23 1709 #define BS_I2S_RCSR_FWIE (1U) /*!< Bit field size in bits for I2S_RCSR_FWIE. */
mbed_official 324:406fd2029f23 1710
mbed_official 324:406fd2029f23 1711 /*! @brief Read current value of the I2S_RCSR_FWIE field. */
mbed_official 324:406fd2029f23 1712 #define BR_I2S_RCSR_FWIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE))
mbed_official 324:406fd2029f23 1713
mbed_official 324:406fd2029f23 1714 /*! @brief Format value for bitfield I2S_RCSR_FWIE. */
mbed_official 324:406fd2029f23 1715 #define BF_I2S_RCSR_FWIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FWIE) & BM_I2S_RCSR_FWIE)
mbed_official 324:406fd2029f23 1716
mbed_official 324:406fd2029f23 1717 /*! @brief Set the FWIE field to a new value. */
mbed_official 324:406fd2029f23 1718 #define BW_I2S_RCSR_FWIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWIE) = (v))
mbed_official 324:406fd2029f23 1719 /*@}*/
mbed_official 324:406fd2029f23 1720
mbed_official 324:406fd2029f23 1721 /*!
mbed_official 324:406fd2029f23 1722 * @name Register I2S_RCSR, field FEIE[10] (RW)
mbed_official 324:406fd2029f23 1723 *
mbed_official 324:406fd2029f23 1724 * Enables/disables FIFO error interrupts.
mbed_official 324:406fd2029f23 1725 *
mbed_official 324:406fd2029f23 1726 * Values:
mbed_official 324:406fd2029f23 1727 * - 0 - Disables the interrupt.
mbed_official 324:406fd2029f23 1728 * - 1 - Enables the interrupt.
mbed_official 324:406fd2029f23 1729 */
mbed_official 324:406fd2029f23 1730 /*@{*/
mbed_official 324:406fd2029f23 1731 #define BP_I2S_RCSR_FEIE (10U) /*!< Bit position for I2S_RCSR_FEIE. */
mbed_official 324:406fd2029f23 1732 #define BM_I2S_RCSR_FEIE (0x00000400U) /*!< Bit mask for I2S_RCSR_FEIE. */
mbed_official 324:406fd2029f23 1733 #define BS_I2S_RCSR_FEIE (1U) /*!< Bit field size in bits for I2S_RCSR_FEIE. */
mbed_official 324:406fd2029f23 1734
mbed_official 324:406fd2029f23 1735 /*! @brief Read current value of the I2S_RCSR_FEIE field. */
mbed_official 324:406fd2029f23 1736 #define BR_I2S_RCSR_FEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE))
mbed_official 324:406fd2029f23 1737
mbed_official 324:406fd2029f23 1738 /*! @brief Format value for bitfield I2S_RCSR_FEIE. */
mbed_official 324:406fd2029f23 1739 #define BF_I2S_RCSR_FEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEIE) & BM_I2S_RCSR_FEIE)
mbed_official 324:406fd2029f23 1740
mbed_official 324:406fd2029f23 1741 /*! @brief Set the FEIE field to a new value. */
mbed_official 324:406fd2029f23 1742 #define BW_I2S_RCSR_FEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEIE) = (v))
mbed_official 324:406fd2029f23 1743 /*@}*/
mbed_official 324:406fd2029f23 1744
mbed_official 324:406fd2029f23 1745 /*!
mbed_official 324:406fd2029f23 1746 * @name Register I2S_RCSR, field SEIE[11] (RW)
mbed_official 324:406fd2029f23 1747 *
mbed_official 324:406fd2029f23 1748 * Enables/disables sync error interrupts.
mbed_official 324:406fd2029f23 1749 *
mbed_official 324:406fd2029f23 1750 * Values:
mbed_official 324:406fd2029f23 1751 * - 0 - Disables interrupt.
mbed_official 324:406fd2029f23 1752 * - 1 - Enables interrupt.
mbed_official 324:406fd2029f23 1753 */
mbed_official 324:406fd2029f23 1754 /*@{*/
mbed_official 324:406fd2029f23 1755 #define BP_I2S_RCSR_SEIE (11U) /*!< Bit position for I2S_RCSR_SEIE. */
mbed_official 324:406fd2029f23 1756 #define BM_I2S_RCSR_SEIE (0x00000800U) /*!< Bit mask for I2S_RCSR_SEIE. */
mbed_official 324:406fd2029f23 1757 #define BS_I2S_RCSR_SEIE (1U) /*!< Bit field size in bits for I2S_RCSR_SEIE. */
mbed_official 324:406fd2029f23 1758
mbed_official 324:406fd2029f23 1759 /*! @brief Read current value of the I2S_RCSR_SEIE field. */
mbed_official 324:406fd2029f23 1760 #define BR_I2S_RCSR_SEIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE))
mbed_official 324:406fd2029f23 1761
mbed_official 324:406fd2029f23 1762 /*! @brief Format value for bitfield I2S_RCSR_SEIE. */
mbed_official 324:406fd2029f23 1763 #define BF_I2S_RCSR_SEIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEIE) & BM_I2S_RCSR_SEIE)
mbed_official 324:406fd2029f23 1764
mbed_official 324:406fd2029f23 1765 /*! @brief Set the SEIE field to a new value. */
mbed_official 324:406fd2029f23 1766 #define BW_I2S_RCSR_SEIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEIE) = (v))
mbed_official 324:406fd2029f23 1767 /*@}*/
mbed_official 324:406fd2029f23 1768
mbed_official 324:406fd2029f23 1769 /*!
mbed_official 324:406fd2029f23 1770 * @name Register I2S_RCSR, field WSIE[12] (RW)
mbed_official 324:406fd2029f23 1771 *
mbed_official 324:406fd2029f23 1772 * Enables/disables word start interrupts.
mbed_official 324:406fd2029f23 1773 *
mbed_official 324:406fd2029f23 1774 * Values:
mbed_official 324:406fd2029f23 1775 * - 0 - Disables interrupt.
mbed_official 324:406fd2029f23 1776 * - 1 - Enables interrupt.
mbed_official 324:406fd2029f23 1777 */
mbed_official 324:406fd2029f23 1778 /*@{*/
mbed_official 324:406fd2029f23 1779 #define BP_I2S_RCSR_WSIE (12U) /*!< Bit position for I2S_RCSR_WSIE. */
mbed_official 324:406fd2029f23 1780 #define BM_I2S_RCSR_WSIE (0x00001000U) /*!< Bit mask for I2S_RCSR_WSIE. */
mbed_official 324:406fd2029f23 1781 #define BS_I2S_RCSR_WSIE (1U) /*!< Bit field size in bits for I2S_RCSR_WSIE. */
mbed_official 324:406fd2029f23 1782
mbed_official 324:406fd2029f23 1783 /*! @brief Read current value of the I2S_RCSR_WSIE field. */
mbed_official 324:406fd2029f23 1784 #define BR_I2S_RCSR_WSIE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE))
mbed_official 324:406fd2029f23 1785
mbed_official 324:406fd2029f23 1786 /*! @brief Format value for bitfield I2S_RCSR_WSIE. */
mbed_official 324:406fd2029f23 1787 #define BF_I2S_RCSR_WSIE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSIE) & BM_I2S_RCSR_WSIE)
mbed_official 324:406fd2029f23 1788
mbed_official 324:406fd2029f23 1789 /*! @brief Set the WSIE field to a new value. */
mbed_official 324:406fd2029f23 1790 #define BW_I2S_RCSR_WSIE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSIE) = (v))
mbed_official 324:406fd2029f23 1791 /*@}*/
mbed_official 324:406fd2029f23 1792
mbed_official 324:406fd2029f23 1793 /*!
mbed_official 324:406fd2029f23 1794 * @name Register I2S_RCSR, field FRF[16] (RO)
mbed_official 324:406fd2029f23 1795 *
mbed_official 324:406fd2029f23 1796 * Indicates that the number of words in an enabled receive channel FIFO is
mbed_official 324:406fd2029f23 1797 * greater than the receive FIFO watermark.
mbed_official 324:406fd2029f23 1798 *
mbed_official 324:406fd2029f23 1799 * Values:
mbed_official 324:406fd2029f23 1800 * - 0 - Receive FIFO watermark not reached.
mbed_official 324:406fd2029f23 1801 * - 1 - Receive FIFO watermark has been reached.
mbed_official 324:406fd2029f23 1802 */
mbed_official 324:406fd2029f23 1803 /*@{*/
mbed_official 324:406fd2029f23 1804 #define BP_I2S_RCSR_FRF (16U) /*!< Bit position for I2S_RCSR_FRF. */
mbed_official 324:406fd2029f23 1805 #define BM_I2S_RCSR_FRF (0x00010000U) /*!< Bit mask for I2S_RCSR_FRF. */
mbed_official 324:406fd2029f23 1806 #define BS_I2S_RCSR_FRF (1U) /*!< Bit field size in bits for I2S_RCSR_FRF. */
mbed_official 324:406fd2029f23 1807
mbed_official 324:406fd2029f23 1808 /*! @brief Read current value of the I2S_RCSR_FRF field. */
mbed_official 324:406fd2029f23 1809 #define BR_I2S_RCSR_FRF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FRF))
mbed_official 324:406fd2029f23 1810 /*@}*/
mbed_official 324:406fd2029f23 1811
mbed_official 324:406fd2029f23 1812 /*!
mbed_official 324:406fd2029f23 1813 * @name Register I2S_RCSR, field FWF[17] (RO)
mbed_official 324:406fd2029f23 1814 *
mbed_official 324:406fd2029f23 1815 * Indicates that an enabled receive FIFO is full.
mbed_official 324:406fd2029f23 1816 *
mbed_official 324:406fd2029f23 1817 * Values:
mbed_official 324:406fd2029f23 1818 * - 0 - No enabled receive FIFO is full.
mbed_official 324:406fd2029f23 1819 * - 1 - Enabled receive FIFO is full.
mbed_official 324:406fd2029f23 1820 */
mbed_official 324:406fd2029f23 1821 /*@{*/
mbed_official 324:406fd2029f23 1822 #define BP_I2S_RCSR_FWF (17U) /*!< Bit position for I2S_RCSR_FWF. */
mbed_official 324:406fd2029f23 1823 #define BM_I2S_RCSR_FWF (0x00020000U) /*!< Bit mask for I2S_RCSR_FWF. */
mbed_official 324:406fd2029f23 1824 #define BS_I2S_RCSR_FWF (1U) /*!< Bit field size in bits for I2S_RCSR_FWF. */
mbed_official 324:406fd2029f23 1825
mbed_official 324:406fd2029f23 1826 /*! @brief Read current value of the I2S_RCSR_FWF field. */
mbed_official 324:406fd2029f23 1827 #define BR_I2S_RCSR_FWF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FWF))
mbed_official 324:406fd2029f23 1828 /*@}*/
mbed_official 324:406fd2029f23 1829
mbed_official 324:406fd2029f23 1830 /*!
mbed_official 324:406fd2029f23 1831 * @name Register I2S_RCSR, field FEF[18] (W1C)
mbed_official 324:406fd2029f23 1832 *
mbed_official 324:406fd2029f23 1833 * Indicates that an enabled receive FIFO has overflowed. Write a logic 1 to
mbed_official 324:406fd2029f23 1834 * this field to clear this flag.
mbed_official 324:406fd2029f23 1835 *
mbed_official 324:406fd2029f23 1836 * Values:
mbed_official 324:406fd2029f23 1837 * - 0 - Receive overflow not detected.
mbed_official 324:406fd2029f23 1838 * - 1 - Receive overflow detected.
mbed_official 324:406fd2029f23 1839 */
mbed_official 324:406fd2029f23 1840 /*@{*/
mbed_official 324:406fd2029f23 1841 #define BP_I2S_RCSR_FEF (18U) /*!< Bit position for I2S_RCSR_FEF. */
mbed_official 324:406fd2029f23 1842 #define BM_I2S_RCSR_FEF (0x00040000U) /*!< Bit mask for I2S_RCSR_FEF. */
mbed_official 324:406fd2029f23 1843 #define BS_I2S_RCSR_FEF (1U) /*!< Bit field size in bits for I2S_RCSR_FEF. */
mbed_official 324:406fd2029f23 1844
mbed_official 324:406fd2029f23 1845 /*! @brief Read current value of the I2S_RCSR_FEF field. */
mbed_official 324:406fd2029f23 1846 #define BR_I2S_RCSR_FEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF))
mbed_official 324:406fd2029f23 1847
mbed_official 324:406fd2029f23 1848 /*! @brief Format value for bitfield I2S_RCSR_FEF. */
mbed_official 324:406fd2029f23 1849 #define BF_I2S_RCSR_FEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FEF) & BM_I2S_RCSR_FEF)
mbed_official 324:406fd2029f23 1850
mbed_official 324:406fd2029f23 1851 /*! @brief Set the FEF field to a new value. */
mbed_official 324:406fd2029f23 1852 #define BW_I2S_RCSR_FEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FEF) = (v))
mbed_official 324:406fd2029f23 1853 /*@}*/
mbed_official 324:406fd2029f23 1854
mbed_official 324:406fd2029f23 1855 /*!
mbed_official 324:406fd2029f23 1856 * @name Register I2S_RCSR, field SEF[19] (W1C)
mbed_official 324:406fd2029f23 1857 *
mbed_official 324:406fd2029f23 1858 * Indicates that an error in the externally-generated frame sync has been
mbed_official 324:406fd2029f23 1859 * detected. Write a logic 1 to this field to clear this flag.
mbed_official 324:406fd2029f23 1860 *
mbed_official 324:406fd2029f23 1861 * Values:
mbed_official 324:406fd2029f23 1862 * - 0 - Sync error not detected.
mbed_official 324:406fd2029f23 1863 * - 1 - Frame sync error detected.
mbed_official 324:406fd2029f23 1864 */
mbed_official 324:406fd2029f23 1865 /*@{*/
mbed_official 324:406fd2029f23 1866 #define BP_I2S_RCSR_SEF (19U) /*!< Bit position for I2S_RCSR_SEF. */
mbed_official 324:406fd2029f23 1867 #define BM_I2S_RCSR_SEF (0x00080000U) /*!< Bit mask for I2S_RCSR_SEF. */
mbed_official 324:406fd2029f23 1868 #define BS_I2S_RCSR_SEF (1U) /*!< Bit field size in bits for I2S_RCSR_SEF. */
mbed_official 324:406fd2029f23 1869
mbed_official 324:406fd2029f23 1870 /*! @brief Read current value of the I2S_RCSR_SEF field. */
mbed_official 324:406fd2029f23 1871 #define BR_I2S_RCSR_SEF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF))
mbed_official 324:406fd2029f23 1872
mbed_official 324:406fd2029f23 1873 /*! @brief Format value for bitfield I2S_RCSR_SEF. */
mbed_official 324:406fd2029f23 1874 #define BF_I2S_RCSR_SEF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SEF) & BM_I2S_RCSR_SEF)
mbed_official 324:406fd2029f23 1875
mbed_official 324:406fd2029f23 1876 /*! @brief Set the SEF field to a new value. */
mbed_official 324:406fd2029f23 1877 #define BW_I2S_RCSR_SEF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SEF) = (v))
mbed_official 324:406fd2029f23 1878 /*@}*/
mbed_official 324:406fd2029f23 1879
mbed_official 324:406fd2029f23 1880 /*!
mbed_official 324:406fd2029f23 1881 * @name Register I2S_RCSR, field WSF[20] (W1C)
mbed_official 324:406fd2029f23 1882 *
mbed_official 324:406fd2029f23 1883 * Indicates that the start of the configured word has been detected. Write a
mbed_official 324:406fd2029f23 1884 * logic 1 to this field to clear this flag.
mbed_official 324:406fd2029f23 1885 *
mbed_official 324:406fd2029f23 1886 * Values:
mbed_official 324:406fd2029f23 1887 * - 0 - Start of word not detected.
mbed_official 324:406fd2029f23 1888 * - 1 - Start of word detected.
mbed_official 324:406fd2029f23 1889 */
mbed_official 324:406fd2029f23 1890 /*@{*/
mbed_official 324:406fd2029f23 1891 #define BP_I2S_RCSR_WSF (20U) /*!< Bit position for I2S_RCSR_WSF. */
mbed_official 324:406fd2029f23 1892 #define BM_I2S_RCSR_WSF (0x00100000U) /*!< Bit mask for I2S_RCSR_WSF. */
mbed_official 324:406fd2029f23 1893 #define BS_I2S_RCSR_WSF (1U) /*!< Bit field size in bits for I2S_RCSR_WSF. */
mbed_official 324:406fd2029f23 1894
mbed_official 324:406fd2029f23 1895 /*! @brief Read current value of the I2S_RCSR_WSF field. */
mbed_official 324:406fd2029f23 1896 #define BR_I2S_RCSR_WSF(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF))
mbed_official 324:406fd2029f23 1897
mbed_official 324:406fd2029f23 1898 /*! @brief Format value for bitfield I2S_RCSR_WSF. */
mbed_official 324:406fd2029f23 1899 #define BF_I2S_RCSR_WSF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_WSF) & BM_I2S_RCSR_WSF)
mbed_official 324:406fd2029f23 1900
mbed_official 324:406fd2029f23 1901 /*! @brief Set the WSF field to a new value. */
mbed_official 324:406fd2029f23 1902 #define BW_I2S_RCSR_WSF(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_WSF) = (v))
mbed_official 324:406fd2029f23 1903 /*@}*/
mbed_official 324:406fd2029f23 1904
mbed_official 324:406fd2029f23 1905 /*!
mbed_official 324:406fd2029f23 1906 * @name Register I2S_RCSR, field SR[24] (RW)
mbed_official 324:406fd2029f23 1907 *
mbed_official 324:406fd2029f23 1908 * Resets the internal receiver logic including the FIFO pointers.
mbed_official 324:406fd2029f23 1909 * Software-visible registers are not affected, except for the status registers.
mbed_official 324:406fd2029f23 1910 *
mbed_official 324:406fd2029f23 1911 * Values:
mbed_official 324:406fd2029f23 1912 * - 0 - No effect.
mbed_official 324:406fd2029f23 1913 * - 1 - Software reset.
mbed_official 324:406fd2029f23 1914 */
mbed_official 324:406fd2029f23 1915 /*@{*/
mbed_official 324:406fd2029f23 1916 #define BP_I2S_RCSR_SR (24U) /*!< Bit position for I2S_RCSR_SR. */
mbed_official 324:406fd2029f23 1917 #define BM_I2S_RCSR_SR (0x01000000U) /*!< Bit mask for I2S_RCSR_SR. */
mbed_official 324:406fd2029f23 1918 #define BS_I2S_RCSR_SR (1U) /*!< Bit field size in bits for I2S_RCSR_SR. */
mbed_official 324:406fd2029f23 1919
mbed_official 324:406fd2029f23 1920 /*! @brief Read current value of the I2S_RCSR_SR field. */
mbed_official 324:406fd2029f23 1921 #define BR_I2S_RCSR_SR(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR))
mbed_official 324:406fd2029f23 1922
mbed_official 324:406fd2029f23 1923 /*! @brief Format value for bitfield I2S_RCSR_SR. */
mbed_official 324:406fd2029f23 1924 #define BF_I2S_RCSR_SR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_SR) & BM_I2S_RCSR_SR)
mbed_official 324:406fd2029f23 1925
mbed_official 324:406fd2029f23 1926 /*! @brief Set the SR field to a new value. */
mbed_official 324:406fd2029f23 1927 #define BW_I2S_RCSR_SR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_SR) = (v))
mbed_official 324:406fd2029f23 1928 /*@}*/
mbed_official 324:406fd2029f23 1929
mbed_official 324:406fd2029f23 1930 /*!
mbed_official 324:406fd2029f23 1931 * @name Register I2S_RCSR, field FR[25] (WORZ)
mbed_official 324:406fd2029f23 1932 *
mbed_official 324:406fd2029f23 1933 * Resets the FIFO pointers. Reading this field will always return zero. FIFO
mbed_official 324:406fd2029f23 1934 * pointers should only be reset when the receiver is disabled or the FIFO error
mbed_official 324:406fd2029f23 1935 * flag is set.
mbed_official 324:406fd2029f23 1936 *
mbed_official 324:406fd2029f23 1937 * Values:
mbed_official 324:406fd2029f23 1938 * - 0 - No effect.
mbed_official 324:406fd2029f23 1939 * - 1 - FIFO reset.
mbed_official 324:406fd2029f23 1940 */
mbed_official 324:406fd2029f23 1941 /*@{*/
mbed_official 324:406fd2029f23 1942 #define BP_I2S_RCSR_FR (25U) /*!< Bit position for I2S_RCSR_FR. */
mbed_official 324:406fd2029f23 1943 #define BM_I2S_RCSR_FR (0x02000000U) /*!< Bit mask for I2S_RCSR_FR. */
mbed_official 324:406fd2029f23 1944 #define BS_I2S_RCSR_FR (1U) /*!< Bit field size in bits for I2S_RCSR_FR. */
mbed_official 324:406fd2029f23 1945
mbed_official 324:406fd2029f23 1946 /*! @brief Format value for bitfield I2S_RCSR_FR. */
mbed_official 324:406fd2029f23 1947 #define BF_I2S_RCSR_FR(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_FR) & BM_I2S_RCSR_FR)
mbed_official 324:406fd2029f23 1948
mbed_official 324:406fd2029f23 1949 /*! @brief Set the FR field to a new value. */
mbed_official 324:406fd2029f23 1950 #define BW_I2S_RCSR_FR(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_FR) = (v))
mbed_official 324:406fd2029f23 1951 /*@}*/
mbed_official 324:406fd2029f23 1952
mbed_official 324:406fd2029f23 1953 /*!
mbed_official 324:406fd2029f23 1954 * @name Register I2S_RCSR, field BCE[28] (RW)
mbed_official 324:406fd2029f23 1955 *
mbed_official 324:406fd2029f23 1956 * Enables the receive bit clock, separately from RE. This field is
mbed_official 324:406fd2029f23 1957 * automatically set whenever RE is set. When software clears this field, the receive bit
mbed_official 324:406fd2029f23 1958 * clock remains enabled, and this field remains set, until the end of the current
mbed_official 324:406fd2029f23 1959 * frame.
mbed_official 324:406fd2029f23 1960 *
mbed_official 324:406fd2029f23 1961 * Values:
mbed_official 324:406fd2029f23 1962 * - 0 - Receive bit clock is disabled.
mbed_official 324:406fd2029f23 1963 * - 1 - Receive bit clock is enabled.
mbed_official 324:406fd2029f23 1964 */
mbed_official 324:406fd2029f23 1965 /*@{*/
mbed_official 324:406fd2029f23 1966 #define BP_I2S_RCSR_BCE (28U) /*!< Bit position for I2S_RCSR_BCE. */
mbed_official 324:406fd2029f23 1967 #define BM_I2S_RCSR_BCE (0x10000000U) /*!< Bit mask for I2S_RCSR_BCE. */
mbed_official 324:406fd2029f23 1968 #define BS_I2S_RCSR_BCE (1U) /*!< Bit field size in bits for I2S_RCSR_BCE. */
mbed_official 324:406fd2029f23 1969
mbed_official 324:406fd2029f23 1970 /*! @brief Read current value of the I2S_RCSR_BCE field. */
mbed_official 324:406fd2029f23 1971 #define BR_I2S_RCSR_BCE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE))
mbed_official 324:406fd2029f23 1972
mbed_official 324:406fd2029f23 1973 /*! @brief Format value for bitfield I2S_RCSR_BCE. */
mbed_official 324:406fd2029f23 1974 #define BF_I2S_RCSR_BCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_BCE) & BM_I2S_RCSR_BCE)
mbed_official 324:406fd2029f23 1975
mbed_official 324:406fd2029f23 1976 /*! @brief Set the BCE field to a new value. */
mbed_official 324:406fd2029f23 1977 #define BW_I2S_RCSR_BCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_BCE) = (v))
mbed_official 324:406fd2029f23 1978 /*@}*/
mbed_official 324:406fd2029f23 1979
mbed_official 324:406fd2029f23 1980 /*!
mbed_official 324:406fd2029f23 1981 * @name Register I2S_RCSR, field DBGE[29] (RW)
mbed_official 324:406fd2029f23 1982 *
mbed_official 324:406fd2029f23 1983 * Enables/disables receiver operation in Debug mode. The receive bit clock is
mbed_official 324:406fd2029f23 1984 * not affected by Debug mode.
mbed_official 324:406fd2029f23 1985 *
mbed_official 324:406fd2029f23 1986 * Values:
mbed_official 324:406fd2029f23 1987 * - 0 - Receiver is disabled in Debug mode, after completing the current frame.
mbed_official 324:406fd2029f23 1988 * - 1 - Receiver is enabled in Debug mode.
mbed_official 324:406fd2029f23 1989 */
mbed_official 324:406fd2029f23 1990 /*@{*/
mbed_official 324:406fd2029f23 1991 #define BP_I2S_RCSR_DBGE (29U) /*!< Bit position for I2S_RCSR_DBGE. */
mbed_official 324:406fd2029f23 1992 #define BM_I2S_RCSR_DBGE (0x20000000U) /*!< Bit mask for I2S_RCSR_DBGE. */
mbed_official 324:406fd2029f23 1993 #define BS_I2S_RCSR_DBGE (1U) /*!< Bit field size in bits for I2S_RCSR_DBGE. */
mbed_official 324:406fd2029f23 1994
mbed_official 324:406fd2029f23 1995 /*! @brief Read current value of the I2S_RCSR_DBGE field. */
mbed_official 324:406fd2029f23 1996 #define BR_I2S_RCSR_DBGE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE))
mbed_official 324:406fd2029f23 1997
mbed_official 324:406fd2029f23 1998 /*! @brief Format value for bitfield I2S_RCSR_DBGE. */
mbed_official 324:406fd2029f23 1999 #define BF_I2S_RCSR_DBGE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_DBGE) & BM_I2S_RCSR_DBGE)
mbed_official 324:406fd2029f23 2000
mbed_official 324:406fd2029f23 2001 /*! @brief Set the DBGE field to a new value. */
mbed_official 324:406fd2029f23 2002 #define BW_I2S_RCSR_DBGE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_DBGE) = (v))
mbed_official 324:406fd2029f23 2003 /*@}*/
mbed_official 324:406fd2029f23 2004
mbed_official 324:406fd2029f23 2005 /*!
mbed_official 324:406fd2029f23 2006 * @name Register I2S_RCSR, field STOPE[30] (RW)
mbed_official 324:406fd2029f23 2007 *
mbed_official 324:406fd2029f23 2008 * Configures receiver operation in Stop mode. This bit is ignored and the
mbed_official 324:406fd2029f23 2009 * receiver is disabled in all low-leakage stop modes.
mbed_official 324:406fd2029f23 2010 *
mbed_official 324:406fd2029f23 2011 * Values:
mbed_official 324:406fd2029f23 2012 * - 0 - Receiver disabled in Stop mode.
mbed_official 324:406fd2029f23 2013 * - 1 - Receiver enabled in Stop mode.
mbed_official 324:406fd2029f23 2014 */
mbed_official 324:406fd2029f23 2015 /*@{*/
mbed_official 324:406fd2029f23 2016 #define BP_I2S_RCSR_STOPE (30U) /*!< Bit position for I2S_RCSR_STOPE. */
mbed_official 324:406fd2029f23 2017 #define BM_I2S_RCSR_STOPE (0x40000000U) /*!< Bit mask for I2S_RCSR_STOPE. */
mbed_official 324:406fd2029f23 2018 #define BS_I2S_RCSR_STOPE (1U) /*!< Bit field size in bits for I2S_RCSR_STOPE. */
mbed_official 324:406fd2029f23 2019
mbed_official 324:406fd2029f23 2020 /*! @brief Read current value of the I2S_RCSR_STOPE field. */
mbed_official 324:406fd2029f23 2021 #define BR_I2S_RCSR_STOPE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE))
mbed_official 324:406fd2029f23 2022
mbed_official 324:406fd2029f23 2023 /*! @brief Format value for bitfield I2S_RCSR_STOPE. */
mbed_official 324:406fd2029f23 2024 #define BF_I2S_RCSR_STOPE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_STOPE) & BM_I2S_RCSR_STOPE)
mbed_official 324:406fd2029f23 2025
mbed_official 324:406fd2029f23 2026 /*! @brief Set the STOPE field to a new value. */
mbed_official 324:406fd2029f23 2027 #define BW_I2S_RCSR_STOPE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_STOPE) = (v))
mbed_official 324:406fd2029f23 2028 /*@}*/
mbed_official 324:406fd2029f23 2029
mbed_official 324:406fd2029f23 2030 /*!
mbed_official 324:406fd2029f23 2031 * @name Register I2S_RCSR, field RE[31] (RW)
mbed_official 324:406fd2029f23 2032 *
mbed_official 324:406fd2029f23 2033 * Enables/disables the receiver. When software clears this field, the receiver
mbed_official 324:406fd2029f23 2034 * remains enabled, and this bit remains set, until the end of the current frame.
mbed_official 324:406fd2029f23 2035 *
mbed_official 324:406fd2029f23 2036 * Values:
mbed_official 324:406fd2029f23 2037 * - 0 - Receiver is disabled.
mbed_official 324:406fd2029f23 2038 * - 1 - Receiver is enabled, or receiver has been disabled and has not yet
mbed_official 324:406fd2029f23 2039 * reached end of frame.
mbed_official 324:406fd2029f23 2040 */
mbed_official 324:406fd2029f23 2041 /*@{*/
mbed_official 324:406fd2029f23 2042 #define BP_I2S_RCSR_RE (31U) /*!< Bit position for I2S_RCSR_RE. */
mbed_official 324:406fd2029f23 2043 #define BM_I2S_RCSR_RE (0x80000000U) /*!< Bit mask for I2S_RCSR_RE. */
mbed_official 324:406fd2029f23 2044 #define BS_I2S_RCSR_RE (1U) /*!< Bit field size in bits for I2S_RCSR_RE. */
mbed_official 324:406fd2029f23 2045
mbed_official 324:406fd2029f23 2046 /*! @brief Read current value of the I2S_RCSR_RE field. */
mbed_official 324:406fd2029f23 2047 #define BR_I2S_RCSR_RE(x) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE))
mbed_official 324:406fd2029f23 2048
mbed_official 324:406fd2029f23 2049 /*! @brief Format value for bitfield I2S_RCSR_RE. */
mbed_official 324:406fd2029f23 2050 #define BF_I2S_RCSR_RE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCSR_RE) & BM_I2S_RCSR_RE)
mbed_official 324:406fd2029f23 2051
mbed_official 324:406fd2029f23 2052 /*! @brief Set the RE field to a new value. */
mbed_official 324:406fd2029f23 2053 #define BW_I2S_RCSR_RE(x, v) (BITBAND_ACCESS32(HW_I2S_RCSR_ADDR(x), BP_I2S_RCSR_RE) = (v))
mbed_official 324:406fd2029f23 2054 /*@}*/
mbed_official 324:406fd2029f23 2055
mbed_official 324:406fd2029f23 2056 /*******************************************************************************
mbed_official 324:406fd2029f23 2057 * HW_I2S_RCR1 - SAI Receive Configuration 1 Register
mbed_official 324:406fd2029f23 2058 ******************************************************************************/
mbed_official 324:406fd2029f23 2059
mbed_official 324:406fd2029f23 2060 /*!
mbed_official 324:406fd2029f23 2061 * @brief HW_I2S_RCR1 - SAI Receive Configuration 1 Register (RW)
mbed_official 324:406fd2029f23 2062 *
mbed_official 324:406fd2029f23 2063 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2064 */
mbed_official 324:406fd2029f23 2065 typedef union _hw_i2s_rcr1
mbed_official 324:406fd2029f23 2066 {
mbed_official 324:406fd2029f23 2067 uint32_t U;
mbed_official 324:406fd2029f23 2068 struct _hw_i2s_rcr1_bitfields
mbed_official 324:406fd2029f23 2069 {
mbed_official 324:406fd2029f23 2070 uint32_t RFW : 3; /*!< [2:0] Receive FIFO Watermark */
mbed_official 324:406fd2029f23 2071 uint32_t RESERVED0 : 29; /*!< [31:3] */
mbed_official 324:406fd2029f23 2072 } B;
mbed_official 324:406fd2029f23 2073 } hw_i2s_rcr1_t;
mbed_official 324:406fd2029f23 2074
mbed_official 324:406fd2029f23 2075 /*!
mbed_official 324:406fd2029f23 2076 * @name Constants and macros for entire I2S_RCR1 register
mbed_official 324:406fd2029f23 2077 */
mbed_official 324:406fd2029f23 2078 /*@{*/
mbed_official 324:406fd2029f23 2079 #define HW_I2S_RCR1_ADDR(x) ((x) + 0x84U)
mbed_official 324:406fd2029f23 2080
mbed_official 324:406fd2029f23 2081 #define HW_I2S_RCR1(x) (*(__IO hw_i2s_rcr1_t *) HW_I2S_RCR1_ADDR(x))
mbed_official 324:406fd2029f23 2082 #define HW_I2S_RCR1_RD(x) (HW_I2S_RCR1(x).U)
mbed_official 324:406fd2029f23 2083 #define HW_I2S_RCR1_WR(x, v) (HW_I2S_RCR1(x).U = (v))
mbed_official 324:406fd2029f23 2084 #define HW_I2S_RCR1_SET(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) | (v)))
mbed_official 324:406fd2029f23 2085 #define HW_I2S_RCR1_CLR(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2086 #define HW_I2S_RCR1_TOG(x, v) (HW_I2S_RCR1_WR(x, HW_I2S_RCR1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2087 /*@}*/
mbed_official 324:406fd2029f23 2088
mbed_official 324:406fd2029f23 2089 /*
mbed_official 324:406fd2029f23 2090 * Constants & macros for individual I2S_RCR1 bitfields
mbed_official 324:406fd2029f23 2091 */
mbed_official 324:406fd2029f23 2092
mbed_official 324:406fd2029f23 2093 /*!
mbed_official 324:406fd2029f23 2094 * @name Register I2S_RCR1, field RFW[2:0] (RW)
mbed_official 324:406fd2029f23 2095 *
mbed_official 324:406fd2029f23 2096 * Configures the watermark level for all enabled receiver channels.
mbed_official 324:406fd2029f23 2097 */
mbed_official 324:406fd2029f23 2098 /*@{*/
mbed_official 324:406fd2029f23 2099 #define BP_I2S_RCR1_RFW (0U) /*!< Bit position for I2S_RCR1_RFW. */
mbed_official 324:406fd2029f23 2100 #define BM_I2S_RCR1_RFW (0x00000007U) /*!< Bit mask for I2S_RCR1_RFW. */
mbed_official 324:406fd2029f23 2101 #define BS_I2S_RCR1_RFW (3U) /*!< Bit field size in bits for I2S_RCR1_RFW. */
mbed_official 324:406fd2029f23 2102
mbed_official 324:406fd2029f23 2103 /*! @brief Read current value of the I2S_RCR1_RFW field. */
mbed_official 324:406fd2029f23 2104 #define BR_I2S_RCR1_RFW(x) (HW_I2S_RCR1(x).B.RFW)
mbed_official 324:406fd2029f23 2105
mbed_official 324:406fd2029f23 2106 /*! @brief Format value for bitfield I2S_RCR1_RFW. */
mbed_official 324:406fd2029f23 2107 #define BF_I2S_RCR1_RFW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR1_RFW) & BM_I2S_RCR1_RFW)
mbed_official 324:406fd2029f23 2108
mbed_official 324:406fd2029f23 2109 /*! @brief Set the RFW field to a new value. */
mbed_official 324:406fd2029f23 2110 #define BW_I2S_RCR1_RFW(x, v) (HW_I2S_RCR1_WR(x, (HW_I2S_RCR1_RD(x) & ~BM_I2S_RCR1_RFW) | BF_I2S_RCR1_RFW(v)))
mbed_official 324:406fd2029f23 2111 /*@}*/
mbed_official 324:406fd2029f23 2112
mbed_official 324:406fd2029f23 2113 /*******************************************************************************
mbed_official 324:406fd2029f23 2114 * HW_I2S_RCR2 - SAI Receive Configuration 2 Register
mbed_official 324:406fd2029f23 2115 ******************************************************************************/
mbed_official 324:406fd2029f23 2116
mbed_official 324:406fd2029f23 2117 /*!
mbed_official 324:406fd2029f23 2118 * @brief HW_I2S_RCR2 - SAI Receive Configuration 2 Register (RW)
mbed_official 324:406fd2029f23 2119 *
mbed_official 324:406fd2029f23 2120 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2121 *
mbed_official 324:406fd2029f23 2122 * This register must not be altered when RCSR[RE] is set.
mbed_official 324:406fd2029f23 2123 */
mbed_official 324:406fd2029f23 2124 typedef union _hw_i2s_rcr2
mbed_official 324:406fd2029f23 2125 {
mbed_official 324:406fd2029f23 2126 uint32_t U;
mbed_official 324:406fd2029f23 2127 struct _hw_i2s_rcr2_bitfields
mbed_official 324:406fd2029f23 2128 {
mbed_official 324:406fd2029f23 2129 uint32_t DIV : 8; /*!< [7:0] Bit Clock Divide */
mbed_official 324:406fd2029f23 2130 uint32_t RESERVED0 : 16; /*!< [23:8] */
mbed_official 324:406fd2029f23 2131 uint32_t BCD : 1; /*!< [24] Bit Clock Direction */
mbed_official 324:406fd2029f23 2132 uint32_t BCP : 1; /*!< [25] Bit Clock Polarity */
mbed_official 324:406fd2029f23 2133 uint32_t MSEL : 2; /*!< [27:26] MCLK Select */
mbed_official 324:406fd2029f23 2134 uint32_t BCI : 1; /*!< [28] Bit Clock Input */
mbed_official 324:406fd2029f23 2135 uint32_t BCS : 1; /*!< [29] Bit Clock Swap */
mbed_official 324:406fd2029f23 2136 uint32_t SYNC : 2; /*!< [31:30] Synchronous Mode */
mbed_official 324:406fd2029f23 2137 } B;
mbed_official 324:406fd2029f23 2138 } hw_i2s_rcr2_t;
mbed_official 324:406fd2029f23 2139
mbed_official 324:406fd2029f23 2140 /*!
mbed_official 324:406fd2029f23 2141 * @name Constants and macros for entire I2S_RCR2 register
mbed_official 324:406fd2029f23 2142 */
mbed_official 324:406fd2029f23 2143 /*@{*/
mbed_official 324:406fd2029f23 2144 #define HW_I2S_RCR2_ADDR(x) ((x) + 0x88U)
mbed_official 324:406fd2029f23 2145
mbed_official 324:406fd2029f23 2146 #define HW_I2S_RCR2(x) (*(__IO hw_i2s_rcr2_t *) HW_I2S_RCR2_ADDR(x))
mbed_official 324:406fd2029f23 2147 #define HW_I2S_RCR2_RD(x) (HW_I2S_RCR2(x).U)
mbed_official 324:406fd2029f23 2148 #define HW_I2S_RCR2_WR(x, v) (HW_I2S_RCR2(x).U = (v))
mbed_official 324:406fd2029f23 2149 #define HW_I2S_RCR2_SET(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) | (v)))
mbed_official 324:406fd2029f23 2150 #define HW_I2S_RCR2_CLR(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2151 #define HW_I2S_RCR2_TOG(x, v) (HW_I2S_RCR2_WR(x, HW_I2S_RCR2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2152 /*@}*/
mbed_official 324:406fd2029f23 2153
mbed_official 324:406fd2029f23 2154 /*
mbed_official 324:406fd2029f23 2155 * Constants & macros for individual I2S_RCR2 bitfields
mbed_official 324:406fd2029f23 2156 */
mbed_official 324:406fd2029f23 2157
mbed_official 324:406fd2029f23 2158 /*!
mbed_official 324:406fd2029f23 2159 * @name Register I2S_RCR2, field DIV[7:0] (RW)
mbed_official 324:406fd2029f23 2160 *
mbed_official 324:406fd2029f23 2161 * Divides down the audio master clock to generate the bit clock when configured
mbed_official 324:406fd2029f23 2162 * for an internal bit clock. The division value is (DIV + 1) * 2.
mbed_official 324:406fd2029f23 2163 */
mbed_official 324:406fd2029f23 2164 /*@{*/
mbed_official 324:406fd2029f23 2165 #define BP_I2S_RCR2_DIV (0U) /*!< Bit position for I2S_RCR2_DIV. */
mbed_official 324:406fd2029f23 2166 #define BM_I2S_RCR2_DIV (0x000000FFU) /*!< Bit mask for I2S_RCR2_DIV. */
mbed_official 324:406fd2029f23 2167 #define BS_I2S_RCR2_DIV (8U) /*!< Bit field size in bits for I2S_RCR2_DIV. */
mbed_official 324:406fd2029f23 2168
mbed_official 324:406fd2029f23 2169 /*! @brief Read current value of the I2S_RCR2_DIV field. */
mbed_official 324:406fd2029f23 2170 #define BR_I2S_RCR2_DIV(x) (HW_I2S_RCR2(x).B.DIV)
mbed_official 324:406fd2029f23 2171
mbed_official 324:406fd2029f23 2172 /*! @brief Format value for bitfield I2S_RCR2_DIV. */
mbed_official 324:406fd2029f23 2173 #define BF_I2S_RCR2_DIV(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_DIV) & BM_I2S_RCR2_DIV)
mbed_official 324:406fd2029f23 2174
mbed_official 324:406fd2029f23 2175 /*! @brief Set the DIV field to a new value. */
mbed_official 324:406fd2029f23 2176 #define BW_I2S_RCR2_DIV(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_DIV) | BF_I2S_RCR2_DIV(v)))
mbed_official 324:406fd2029f23 2177 /*@}*/
mbed_official 324:406fd2029f23 2178
mbed_official 324:406fd2029f23 2179 /*!
mbed_official 324:406fd2029f23 2180 * @name Register I2S_RCR2, field BCD[24] (RW)
mbed_official 324:406fd2029f23 2181 *
mbed_official 324:406fd2029f23 2182 * Configures the direction of the bit clock.
mbed_official 324:406fd2029f23 2183 *
mbed_official 324:406fd2029f23 2184 * Values:
mbed_official 324:406fd2029f23 2185 * - 0 - Bit clock is generated externally in Slave mode.
mbed_official 324:406fd2029f23 2186 * - 1 - Bit clock is generated internally in Master mode.
mbed_official 324:406fd2029f23 2187 */
mbed_official 324:406fd2029f23 2188 /*@{*/
mbed_official 324:406fd2029f23 2189 #define BP_I2S_RCR2_BCD (24U) /*!< Bit position for I2S_RCR2_BCD. */
mbed_official 324:406fd2029f23 2190 #define BM_I2S_RCR2_BCD (0x01000000U) /*!< Bit mask for I2S_RCR2_BCD. */
mbed_official 324:406fd2029f23 2191 #define BS_I2S_RCR2_BCD (1U) /*!< Bit field size in bits for I2S_RCR2_BCD. */
mbed_official 324:406fd2029f23 2192
mbed_official 324:406fd2029f23 2193 /*! @brief Read current value of the I2S_RCR2_BCD field. */
mbed_official 324:406fd2029f23 2194 #define BR_I2S_RCR2_BCD(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD))
mbed_official 324:406fd2029f23 2195
mbed_official 324:406fd2029f23 2196 /*! @brief Format value for bitfield I2S_RCR2_BCD. */
mbed_official 324:406fd2029f23 2197 #define BF_I2S_RCR2_BCD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCD) & BM_I2S_RCR2_BCD)
mbed_official 324:406fd2029f23 2198
mbed_official 324:406fd2029f23 2199 /*! @brief Set the BCD field to a new value. */
mbed_official 324:406fd2029f23 2200 #define BW_I2S_RCR2_BCD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCD) = (v))
mbed_official 324:406fd2029f23 2201 /*@}*/
mbed_official 324:406fd2029f23 2202
mbed_official 324:406fd2029f23 2203 /*!
mbed_official 324:406fd2029f23 2204 * @name Register I2S_RCR2, field BCP[25] (RW)
mbed_official 324:406fd2029f23 2205 *
mbed_official 324:406fd2029f23 2206 * Configures the polarity of the bit clock.
mbed_official 324:406fd2029f23 2207 *
mbed_official 324:406fd2029f23 2208 * Values:
mbed_official 324:406fd2029f23 2209 * - 0 - Bit Clock is active high with drive outputs on rising edge and sample
mbed_official 324:406fd2029f23 2210 * inputs on falling edge.
mbed_official 324:406fd2029f23 2211 * - 1 - Bit Clock is active low with drive outputs on falling edge and sample
mbed_official 324:406fd2029f23 2212 * inputs on rising edge.
mbed_official 324:406fd2029f23 2213 */
mbed_official 324:406fd2029f23 2214 /*@{*/
mbed_official 324:406fd2029f23 2215 #define BP_I2S_RCR2_BCP (25U) /*!< Bit position for I2S_RCR2_BCP. */
mbed_official 324:406fd2029f23 2216 #define BM_I2S_RCR2_BCP (0x02000000U) /*!< Bit mask for I2S_RCR2_BCP. */
mbed_official 324:406fd2029f23 2217 #define BS_I2S_RCR2_BCP (1U) /*!< Bit field size in bits for I2S_RCR2_BCP. */
mbed_official 324:406fd2029f23 2218
mbed_official 324:406fd2029f23 2219 /*! @brief Read current value of the I2S_RCR2_BCP field. */
mbed_official 324:406fd2029f23 2220 #define BR_I2S_RCR2_BCP(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP))
mbed_official 324:406fd2029f23 2221
mbed_official 324:406fd2029f23 2222 /*! @brief Format value for bitfield I2S_RCR2_BCP. */
mbed_official 324:406fd2029f23 2223 #define BF_I2S_RCR2_BCP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCP) & BM_I2S_RCR2_BCP)
mbed_official 324:406fd2029f23 2224
mbed_official 324:406fd2029f23 2225 /*! @brief Set the BCP field to a new value. */
mbed_official 324:406fd2029f23 2226 #define BW_I2S_RCR2_BCP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCP) = (v))
mbed_official 324:406fd2029f23 2227 /*@}*/
mbed_official 324:406fd2029f23 2228
mbed_official 324:406fd2029f23 2229 /*!
mbed_official 324:406fd2029f23 2230 * @name Register I2S_RCR2, field MSEL[27:26] (RW)
mbed_official 324:406fd2029f23 2231 *
mbed_official 324:406fd2029f23 2232 * Selects the audio Master Clock option used to generate an internally
mbed_official 324:406fd2029f23 2233 * generated bit clock. This field has no effect when configured for an externally
mbed_official 324:406fd2029f23 2234 * generated bit clock. Depending on the device, some Master Clock options might not be
mbed_official 324:406fd2029f23 2235 * available. See the chip configuration details for the availability and
mbed_official 324:406fd2029f23 2236 * chip-specific meaning of each option.
mbed_official 324:406fd2029f23 2237 *
mbed_official 324:406fd2029f23 2238 * Values:
mbed_official 324:406fd2029f23 2239 * - 00 - Bus Clock selected.
mbed_official 324:406fd2029f23 2240 * - 01 - Master Clock (MCLK) 1 option selected.
mbed_official 324:406fd2029f23 2241 * - 10 - Master Clock (MCLK) 2 option selected.
mbed_official 324:406fd2029f23 2242 * - 11 - Master Clock (MCLK) 3 option selected.
mbed_official 324:406fd2029f23 2243 */
mbed_official 324:406fd2029f23 2244 /*@{*/
mbed_official 324:406fd2029f23 2245 #define BP_I2S_RCR2_MSEL (26U) /*!< Bit position for I2S_RCR2_MSEL. */
mbed_official 324:406fd2029f23 2246 #define BM_I2S_RCR2_MSEL (0x0C000000U) /*!< Bit mask for I2S_RCR2_MSEL. */
mbed_official 324:406fd2029f23 2247 #define BS_I2S_RCR2_MSEL (2U) /*!< Bit field size in bits for I2S_RCR2_MSEL. */
mbed_official 324:406fd2029f23 2248
mbed_official 324:406fd2029f23 2249 /*! @brief Read current value of the I2S_RCR2_MSEL field. */
mbed_official 324:406fd2029f23 2250 #define BR_I2S_RCR2_MSEL(x) (HW_I2S_RCR2(x).B.MSEL)
mbed_official 324:406fd2029f23 2251
mbed_official 324:406fd2029f23 2252 /*! @brief Format value for bitfield I2S_RCR2_MSEL. */
mbed_official 324:406fd2029f23 2253 #define BF_I2S_RCR2_MSEL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_MSEL) & BM_I2S_RCR2_MSEL)
mbed_official 324:406fd2029f23 2254
mbed_official 324:406fd2029f23 2255 /*! @brief Set the MSEL field to a new value. */
mbed_official 324:406fd2029f23 2256 #define BW_I2S_RCR2_MSEL(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_MSEL) | BF_I2S_RCR2_MSEL(v)))
mbed_official 324:406fd2029f23 2257 /*@}*/
mbed_official 324:406fd2029f23 2258
mbed_official 324:406fd2029f23 2259 /*!
mbed_official 324:406fd2029f23 2260 * @name Register I2S_RCR2, field BCI[28] (RW)
mbed_official 324:406fd2029f23 2261 *
mbed_official 324:406fd2029f23 2262 * When this field is set and using an internally generated bit clock in either
mbed_official 324:406fd2029f23 2263 * synchronous or asynchronous mode, the bit clock actually used by the receiver
mbed_official 324:406fd2029f23 2264 * is delayed by the pad output delay (the receiver is clocked by the pad input
mbed_official 324:406fd2029f23 2265 * as if the clock was externally generated). This has the effect of decreasing
mbed_official 324:406fd2029f23 2266 * the data input setup time, but increasing the data output valid time. The slave
mbed_official 324:406fd2029f23 2267 * mode timing from the datasheet should be used for the receiver when this bit
mbed_official 324:406fd2029f23 2268 * is set. In synchronous mode, this bit allows the receiver to use the slave mode
mbed_official 324:406fd2029f23 2269 * timing from the datasheet, while the transmitter uses the master mode timing.
mbed_official 324:406fd2029f23 2270 * This field has no effect when configured for an externally generated bit
mbed_official 324:406fd2029f23 2271 * clock .
mbed_official 324:406fd2029f23 2272 *
mbed_official 324:406fd2029f23 2273 * Values:
mbed_official 324:406fd2029f23 2274 * - 0 - No effect.
mbed_official 324:406fd2029f23 2275 * - 1 - Internal logic is clocked as if bit clock was externally generated.
mbed_official 324:406fd2029f23 2276 */
mbed_official 324:406fd2029f23 2277 /*@{*/
mbed_official 324:406fd2029f23 2278 #define BP_I2S_RCR2_BCI (28U) /*!< Bit position for I2S_RCR2_BCI. */
mbed_official 324:406fd2029f23 2279 #define BM_I2S_RCR2_BCI (0x10000000U) /*!< Bit mask for I2S_RCR2_BCI. */
mbed_official 324:406fd2029f23 2280 #define BS_I2S_RCR2_BCI (1U) /*!< Bit field size in bits for I2S_RCR2_BCI. */
mbed_official 324:406fd2029f23 2281
mbed_official 324:406fd2029f23 2282 /*! @brief Read current value of the I2S_RCR2_BCI field. */
mbed_official 324:406fd2029f23 2283 #define BR_I2S_RCR2_BCI(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI))
mbed_official 324:406fd2029f23 2284
mbed_official 324:406fd2029f23 2285 /*! @brief Format value for bitfield I2S_RCR2_BCI. */
mbed_official 324:406fd2029f23 2286 #define BF_I2S_RCR2_BCI(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCI) & BM_I2S_RCR2_BCI)
mbed_official 324:406fd2029f23 2287
mbed_official 324:406fd2029f23 2288 /*! @brief Set the BCI field to a new value. */
mbed_official 324:406fd2029f23 2289 #define BW_I2S_RCR2_BCI(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCI) = (v))
mbed_official 324:406fd2029f23 2290 /*@}*/
mbed_official 324:406fd2029f23 2291
mbed_official 324:406fd2029f23 2292 /*!
mbed_official 324:406fd2029f23 2293 * @name Register I2S_RCR2, field BCS[29] (RW)
mbed_official 324:406fd2029f23 2294 *
mbed_official 324:406fd2029f23 2295 * This field swaps the bit clock used by the receiver. When the receiver is
mbed_official 324:406fd2029f23 2296 * configured in asynchronous mode and this bit is set, the receiver is clocked by
mbed_official 324:406fd2029f23 2297 * the transmitter bit clock (SAI_TX_BCLK). This allows the transmitter and
mbed_official 324:406fd2029f23 2298 * receiver to share the same bit clock, but the receiver continues to use the receiver
mbed_official 324:406fd2029f23 2299 * frame sync (SAI_RX_SYNC). When the receiver is configured in synchronous
mbed_official 324:406fd2029f23 2300 * mode, the transmitter BCS field and receiver BCS field must be set to the same
mbed_official 324:406fd2029f23 2301 * value. When both are set, the transmitter and receiver are both clocked by the
mbed_official 324:406fd2029f23 2302 * receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync
mbed_official 324:406fd2029f23 2303 * (SAI_TX_SYNC).
mbed_official 324:406fd2029f23 2304 *
mbed_official 324:406fd2029f23 2305 * Values:
mbed_official 324:406fd2029f23 2306 * - 0 - Use the normal bit clock source.
mbed_official 324:406fd2029f23 2307 * - 1 - Swap the bit clock source.
mbed_official 324:406fd2029f23 2308 */
mbed_official 324:406fd2029f23 2309 /*@{*/
mbed_official 324:406fd2029f23 2310 #define BP_I2S_RCR2_BCS (29U) /*!< Bit position for I2S_RCR2_BCS. */
mbed_official 324:406fd2029f23 2311 #define BM_I2S_RCR2_BCS (0x20000000U) /*!< Bit mask for I2S_RCR2_BCS. */
mbed_official 324:406fd2029f23 2312 #define BS_I2S_RCR2_BCS (1U) /*!< Bit field size in bits for I2S_RCR2_BCS. */
mbed_official 324:406fd2029f23 2313
mbed_official 324:406fd2029f23 2314 /*! @brief Read current value of the I2S_RCR2_BCS field. */
mbed_official 324:406fd2029f23 2315 #define BR_I2S_RCR2_BCS(x) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS))
mbed_official 324:406fd2029f23 2316
mbed_official 324:406fd2029f23 2317 /*! @brief Format value for bitfield I2S_RCR2_BCS. */
mbed_official 324:406fd2029f23 2318 #define BF_I2S_RCR2_BCS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_BCS) & BM_I2S_RCR2_BCS)
mbed_official 324:406fd2029f23 2319
mbed_official 324:406fd2029f23 2320 /*! @brief Set the BCS field to a new value. */
mbed_official 324:406fd2029f23 2321 #define BW_I2S_RCR2_BCS(x, v) (BITBAND_ACCESS32(HW_I2S_RCR2_ADDR(x), BP_I2S_RCR2_BCS) = (v))
mbed_official 324:406fd2029f23 2322 /*@}*/
mbed_official 324:406fd2029f23 2323
mbed_official 324:406fd2029f23 2324 /*!
mbed_official 324:406fd2029f23 2325 * @name Register I2S_RCR2, field SYNC[31:30] (RW)
mbed_official 324:406fd2029f23 2326 *
mbed_official 324:406fd2029f23 2327 * Configures between asynchronous and synchronous modes of operation. When
mbed_official 324:406fd2029f23 2328 * configured for a synchronous mode of operation, the transmitter must be configured
mbed_official 324:406fd2029f23 2329 * for asynchronous operation.
mbed_official 324:406fd2029f23 2330 *
mbed_official 324:406fd2029f23 2331 * Values:
mbed_official 324:406fd2029f23 2332 * - 00 - Asynchronous mode.
mbed_official 324:406fd2029f23 2333 * - 01 - Synchronous with transmitter.
mbed_official 324:406fd2029f23 2334 * - 10 - Synchronous with another SAI receiver.
mbed_official 324:406fd2029f23 2335 * - 11 - Synchronous with another SAI transmitter.
mbed_official 324:406fd2029f23 2336 */
mbed_official 324:406fd2029f23 2337 /*@{*/
mbed_official 324:406fd2029f23 2338 #define BP_I2S_RCR2_SYNC (30U) /*!< Bit position for I2S_RCR2_SYNC. */
mbed_official 324:406fd2029f23 2339 #define BM_I2S_RCR2_SYNC (0xC0000000U) /*!< Bit mask for I2S_RCR2_SYNC. */
mbed_official 324:406fd2029f23 2340 #define BS_I2S_RCR2_SYNC (2U) /*!< Bit field size in bits for I2S_RCR2_SYNC. */
mbed_official 324:406fd2029f23 2341
mbed_official 324:406fd2029f23 2342 /*! @brief Read current value of the I2S_RCR2_SYNC field. */
mbed_official 324:406fd2029f23 2343 #define BR_I2S_RCR2_SYNC(x) (HW_I2S_RCR2(x).B.SYNC)
mbed_official 324:406fd2029f23 2344
mbed_official 324:406fd2029f23 2345 /*! @brief Format value for bitfield I2S_RCR2_SYNC. */
mbed_official 324:406fd2029f23 2346 #define BF_I2S_RCR2_SYNC(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR2_SYNC) & BM_I2S_RCR2_SYNC)
mbed_official 324:406fd2029f23 2347
mbed_official 324:406fd2029f23 2348 /*! @brief Set the SYNC field to a new value. */
mbed_official 324:406fd2029f23 2349 #define BW_I2S_RCR2_SYNC(x, v) (HW_I2S_RCR2_WR(x, (HW_I2S_RCR2_RD(x) & ~BM_I2S_RCR2_SYNC) | BF_I2S_RCR2_SYNC(v)))
mbed_official 324:406fd2029f23 2350 /*@}*/
mbed_official 324:406fd2029f23 2351
mbed_official 324:406fd2029f23 2352 /*******************************************************************************
mbed_official 324:406fd2029f23 2353 * HW_I2S_RCR3 - SAI Receive Configuration 3 Register
mbed_official 324:406fd2029f23 2354 ******************************************************************************/
mbed_official 324:406fd2029f23 2355
mbed_official 324:406fd2029f23 2356 /*!
mbed_official 324:406fd2029f23 2357 * @brief HW_I2S_RCR3 - SAI Receive Configuration 3 Register (RW)
mbed_official 324:406fd2029f23 2358 *
mbed_official 324:406fd2029f23 2359 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2360 */
mbed_official 324:406fd2029f23 2361 typedef union _hw_i2s_rcr3
mbed_official 324:406fd2029f23 2362 {
mbed_official 324:406fd2029f23 2363 uint32_t U;
mbed_official 324:406fd2029f23 2364 struct _hw_i2s_rcr3_bitfields
mbed_official 324:406fd2029f23 2365 {
mbed_official 324:406fd2029f23 2366 uint32_t WDFL : 4; /*!< [3:0] Word Flag Configuration */
mbed_official 324:406fd2029f23 2367 uint32_t RESERVED0 : 12; /*!< [15:4] */
mbed_official 324:406fd2029f23 2368 uint32_t RCE : 1; /*!< [16] Receive Channel Enable */
mbed_official 324:406fd2029f23 2369 uint32_t RESERVED1 : 15; /*!< [31:17] */
mbed_official 324:406fd2029f23 2370 } B;
mbed_official 324:406fd2029f23 2371 } hw_i2s_rcr3_t;
mbed_official 324:406fd2029f23 2372
mbed_official 324:406fd2029f23 2373 /*!
mbed_official 324:406fd2029f23 2374 * @name Constants and macros for entire I2S_RCR3 register
mbed_official 324:406fd2029f23 2375 */
mbed_official 324:406fd2029f23 2376 /*@{*/
mbed_official 324:406fd2029f23 2377 #define HW_I2S_RCR3_ADDR(x) ((x) + 0x8CU)
mbed_official 324:406fd2029f23 2378
mbed_official 324:406fd2029f23 2379 #define HW_I2S_RCR3(x) (*(__IO hw_i2s_rcr3_t *) HW_I2S_RCR3_ADDR(x))
mbed_official 324:406fd2029f23 2380 #define HW_I2S_RCR3_RD(x) (HW_I2S_RCR3(x).U)
mbed_official 324:406fd2029f23 2381 #define HW_I2S_RCR3_WR(x, v) (HW_I2S_RCR3(x).U = (v))
mbed_official 324:406fd2029f23 2382 #define HW_I2S_RCR3_SET(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) | (v)))
mbed_official 324:406fd2029f23 2383 #define HW_I2S_RCR3_CLR(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2384 #define HW_I2S_RCR3_TOG(x, v) (HW_I2S_RCR3_WR(x, HW_I2S_RCR3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2385 /*@}*/
mbed_official 324:406fd2029f23 2386
mbed_official 324:406fd2029f23 2387 /*
mbed_official 324:406fd2029f23 2388 * Constants & macros for individual I2S_RCR3 bitfields
mbed_official 324:406fd2029f23 2389 */
mbed_official 324:406fd2029f23 2390
mbed_official 324:406fd2029f23 2391 /*!
mbed_official 324:406fd2029f23 2392 * @name Register I2S_RCR3, field WDFL[3:0] (RW)
mbed_official 324:406fd2029f23 2393 *
mbed_official 324:406fd2029f23 2394 * Configures which word the start of word flag is set. The value written should
mbed_official 324:406fd2029f23 2395 * be one less than the word number (for example, write zero to configure for
mbed_official 324:406fd2029f23 2396 * the first word in the frame). When configured to a value greater than the Frame
mbed_official 324:406fd2029f23 2397 * Size field, then the start of word flag is never set.
mbed_official 324:406fd2029f23 2398 */
mbed_official 324:406fd2029f23 2399 /*@{*/
mbed_official 324:406fd2029f23 2400 #define BP_I2S_RCR3_WDFL (0U) /*!< Bit position for I2S_RCR3_WDFL. */
mbed_official 324:406fd2029f23 2401 #define BM_I2S_RCR3_WDFL (0x0000000FU) /*!< Bit mask for I2S_RCR3_WDFL. */
mbed_official 324:406fd2029f23 2402 #define BS_I2S_RCR3_WDFL (4U) /*!< Bit field size in bits for I2S_RCR3_WDFL. */
mbed_official 324:406fd2029f23 2403
mbed_official 324:406fd2029f23 2404 /*! @brief Read current value of the I2S_RCR3_WDFL field. */
mbed_official 324:406fd2029f23 2405 #define BR_I2S_RCR3_WDFL(x) (HW_I2S_RCR3(x).B.WDFL)
mbed_official 324:406fd2029f23 2406
mbed_official 324:406fd2029f23 2407 /*! @brief Format value for bitfield I2S_RCR3_WDFL. */
mbed_official 324:406fd2029f23 2408 #define BF_I2S_RCR3_WDFL(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_WDFL) & BM_I2S_RCR3_WDFL)
mbed_official 324:406fd2029f23 2409
mbed_official 324:406fd2029f23 2410 /*! @brief Set the WDFL field to a new value. */
mbed_official 324:406fd2029f23 2411 #define BW_I2S_RCR3_WDFL(x, v) (HW_I2S_RCR3_WR(x, (HW_I2S_RCR3_RD(x) & ~BM_I2S_RCR3_WDFL) | BF_I2S_RCR3_WDFL(v)))
mbed_official 324:406fd2029f23 2412 /*@}*/
mbed_official 324:406fd2029f23 2413
mbed_official 324:406fd2029f23 2414 /*!
mbed_official 324:406fd2029f23 2415 * @name Register I2S_RCR3, field RCE[16] (RW)
mbed_official 324:406fd2029f23 2416 *
mbed_official 324:406fd2029f23 2417 * Enables the corresponding data channel for receive operation. A channel must
mbed_official 324:406fd2029f23 2418 * be enabled before its FIFO is accessed. Changing this field will take effect
mbed_official 324:406fd2029f23 2419 * immediately for generating the FIFO request and warning flags, but at the end
mbed_official 324:406fd2029f23 2420 * of each frame for receive operation.
mbed_official 324:406fd2029f23 2421 *
mbed_official 324:406fd2029f23 2422 * Values:
mbed_official 324:406fd2029f23 2423 * - 0 - Receive data channel N is disabled.
mbed_official 324:406fd2029f23 2424 * - 1 - Receive data channel N is enabled.
mbed_official 324:406fd2029f23 2425 */
mbed_official 324:406fd2029f23 2426 /*@{*/
mbed_official 324:406fd2029f23 2427 #define BP_I2S_RCR3_RCE (16U) /*!< Bit position for I2S_RCR3_RCE. */
mbed_official 324:406fd2029f23 2428 #define BM_I2S_RCR3_RCE (0x00010000U) /*!< Bit mask for I2S_RCR3_RCE. */
mbed_official 324:406fd2029f23 2429 #define BS_I2S_RCR3_RCE (1U) /*!< Bit field size in bits for I2S_RCR3_RCE. */
mbed_official 324:406fd2029f23 2430
mbed_official 324:406fd2029f23 2431 /*! @brief Read current value of the I2S_RCR3_RCE field. */
mbed_official 324:406fd2029f23 2432 #define BR_I2S_RCR3_RCE(x) (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE))
mbed_official 324:406fd2029f23 2433
mbed_official 324:406fd2029f23 2434 /*! @brief Format value for bitfield I2S_RCR3_RCE. */
mbed_official 324:406fd2029f23 2435 #define BF_I2S_RCR3_RCE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR3_RCE) & BM_I2S_RCR3_RCE)
mbed_official 324:406fd2029f23 2436
mbed_official 324:406fd2029f23 2437 /*! @brief Set the RCE field to a new value. */
mbed_official 324:406fd2029f23 2438 #define BW_I2S_RCR3_RCE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR3_ADDR(x), BP_I2S_RCR3_RCE) = (v))
mbed_official 324:406fd2029f23 2439 /*@}*/
mbed_official 324:406fd2029f23 2440
mbed_official 324:406fd2029f23 2441 /*******************************************************************************
mbed_official 324:406fd2029f23 2442 * HW_I2S_RCR4 - SAI Receive Configuration 4 Register
mbed_official 324:406fd2029f23 2443 ******************************************************************************/
mbed_official 324:406fd2029f23 2444
mbed_official 324:406fd2029f23 2445 /*!
mbed_official 324:406fd2029f23 2446 * @brief HW_I2S_RCR4 - SAI Receive Configuration 4 Register (RW)
mbed_official 324:406fd2029f23 2447 *
mbed_official 324:406fd2029f23 2448 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2449 *
mbed_official 324:406fd2029f23 2450 * This register must not be altered when RCSR[RE] is set.
mbed_official 324:406fd2029f23 2451 */
mbed_official 324:406fd2029f23 2452 typedef union _hw_i2s_rcr4
mbed_official 324:406fd2029f23 2453 {
mbed_official 324:406fd2029f23 2454 uint32_t U;
mbed_official 324:406fd2029f23 2455 struct _hw_i2s_rcr4_bitfields
mbed_official 324:406fd2029f23 2456 {
mbed_official 324:406fd2029f23 2457 uint32_t FSD : 1; /*!< [0] Frame Sync Direction */
mbed_official 324:406fd2029f23 2458 uint32_t FSP : 1; /*!< [1] Frame Sync Polarity */
mbed_official 324:406fd2029f23 2459 uint32_t ONDEM : 1; /*!< [2] On Demand Mode */
mbed_official 324:406fd2029f23 2460 uint32_t FSE : 1; /*!< [3] Frame Sync Early */
mbed_official 324:406fd2029f23 2461 uint32_t MF : 1; /*!< [4] MSB First */
mbed_official 324:406fd2029f23 2462 uint32_t RESERVED0 : 3; /*!< [7:5] */
mbed_official 324:406fd2029f23 2463 uint32_t SYWD : 5; /*!< [12:8] Sync Width */
mbed_official 324:406fd2029f23 2464 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 2465 uint32_t FRSZ : 4; /*!< [19:16] Frame Size */
mbed_official 324:406fd2029f23 2466 uint32_t RESERVED2 : 4; /*!< [23:20] */
mbed_official 324:406fd2029f23 2467 uint32_t FPACK : 2; /*!< [25:24] FIFO Packing Mode */
mbed_official 324:406fd2029f23 2468 uint32_t RESERVED3 : 2; /*!< [27:26] */
mbed_official 324:406fd2029f23 2469 uint32_t FCONT : 1; /*!< [28] FIFO Continue on Error */
mbed_official 324:406fd2029f23 2470 uint32_t RESERVED4 : 3; /*!< [31:29] */
mbed_official 324:406fd2029f23 2471 } B;
mbed_official 324:406fd2029f23 2472 } hw_i2s_rcr4_t;
mbed_official 324:406fd2029f23 2473
mbed_official 324:406fd2029f23 2474 /*!
mbed_official 324:406fd2029f23 2475 * @name Constants and macros for entire I2S_RCR4 register
mbed_official 324:406fd2029f23 2476 */
mbed_official 324:406fd2029f23 2477 /*@{*/
mbed_official 324:406fd2029f23 2478 #define HW_I2S_RCR4_ADDR(x) ((x) + 0x90U)
mbed_official 324:406fd2029f23 2479
mbed_official 324:406fd2029f23 2480 #define HW_I2S_RCR4(x) (*(__IO hw_i2s_rcr4_t *) HW_I2S_RCR4_ADDR(x))
mbed_official 324:406fd2029f23 2481 #define HW_I2S_RCR4_RD(x) (HW_I2S_RCR4(x).U)
mbed_official 324:406fd2029f23 2482 #define HW_I2S_RCR4_WR(x, v) (HW_I2S_RCR4(x).U = (v))
mbed_official 324:406fd2029f23 2483 #define HW_I2S_RCR4_SET(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) | (v)))
mbed_official 324:406fd2029f23 2484 #define HW_I2S_RCR4_CLR(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2485 #define HW_I2S_RCR4_TOG(x, v) (HW_I2S_RCR4_WR(x, HW_I2S_RCR4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2486 /*@}*/
mbed_official 324:406fd2029f23 2487
mbed_official 324:406fd2029f23 2488 /*
mbed_official 324:406fd2029f23 2489 * Constants & macros for individual I2S_RCR4 bitfields
mbed_official 324:406fd2029f23 2490 */
mbed_official 324:406fd2029f23 2491
mbed_official 324:406fd2029f23 2492 /*!
mbed_official 324:406fd2029f23 2493 * @name Register I2S_RCR4, field FSD[0] (RW)
mbed_official 324:406fd2029f23 2494 *
mbed_official 324:406fd2029f23 2495 * Configures the direction of the frame sync.
mbed_official 324:406fd2029f23 2496 *
mbed_official 324:406fd2029f23 2497 * Values:
mbed_official 324:406fd2029f23 2498 * - 0 - Frame Sync is generated externally in Slave mode.
mbed_official 324:406fd2029f23 2499 * - 1 - Frame Sync is generated internally in Master mode.
mbed_official 324:406fd2029f23 2500 */
mbed_official 324:406fd2029f23 2501 /*@{*/
mbed_official 324:406fd2029f23 2502 #define BP_I2S_RCR4_FSD (0U) /*!< Bit position for I2S_RCR4_FSD. */
mbed_official 324:406fd2029f23 2503 #define BM_I2S_RCR4_FSD (0x00000001U) /*!< Bit mask for I2S_RCR4_FSD. */
mbed_official 324:406fd2029f23 2504 #define BS_I2S_RCR4_FSD (1U) /*!< Bit field size in bits for I2S_RCR4_FSD. */
mbed_official 324:406fd2029f23 2505
mbed_official 324:406fd2029f23 2506 /*! @brief Read current value of the I2S_RCR4_FSD field. */
mbed_official 324:406fd2029f23 2507 #define BR_I2S_RCR4_FSD(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD))
mbed_official 324:406fd2029f23 2508
mbed_official 324:406fd2029f23 2509 /*! @brief Format value for bitfield I2S_RCR4_FSD. */
mbed_official 324:406fd2029f23 2510 #define BF_I2S_RCR4_FSD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSD) & BM_I2S_RCR4_FSD)
mbed_official 324:406fd2029f23 2511
mbed_official 324:406fd2029f23 2512 /*! @brief Set the FSD field to a new value. */
mbed_official 324:406fd2029f23 2513 #define BW_I2S_RCR4_FSD(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSD) = (v))
mbed_official 324:406fd2029f23 2514 /*@}*/
mbed_official 324:406fd2029f23 2515
mbed_official 324:406fd2029f23 2516 /*!
mbed_official 324:406fd2029f23 2517 * @name Register I2S_RCR4, field FSP[1] (RW)
mbed_official 324:406fd2029f23 2518 *
mbed_official 324:406fd2029f23 2519 * Configures the polarity of the frame sync.
mbed_official 324:406fd2029f23 2520 *
mbed_official 324:406fd2029f23 2521 * Values:
mbed_official 324:406fd2029f23 2522 * - 0 - Frame sync is active high.
mbed_official 324:406fd2029f23 2523 * - 1 - Frame sync is active low.
mbed_official 324:406fd2029f23 2524 */
mbed_official 324:406fd2029f23 2525 /*@{*/
mbed_official 324:406fd2029f23 2526 #define BP_I2S_RCR4_FSP (1U) /*!< Bit position for I2S_RCR4_FSP. */
mbed_official 324:406fd2029f23 2527 #define BM_I2S_RCR4_FSP (0x00000002U) /*!< Bit mask for I2S_RCR4_FSP. */
mbed_official 324:406fd2029f23 2528 #define BS_I2S_RCR4_FSP (1U) /*!< Bit field size in bits for I2S_RCR4_FSP. */
mbed_official 324:406fd2029f23 2529
mbed_official 324:406fd2029f23 2530 /*! @brief Read current value of the I2S_RCR4_FSP field. */
mbed_official 324:406fd2029f23 2531 #define BR_I2S_RCR4_FSP(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP))
mbed_official 324:406fd2029f23 2532
mbed_official 324:406fd2029f23 2533 /*! @brief Format value for bitfield I2S_RCR4_FSP. */
mbed_official 324:406fd2029f23 2534 #define BF_I2S_RCR4_FSP(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSP) & BM_I2S_RCR4_FSP)
mbed_official 324:406fd2029f23 2535
mbed_official 324:406fd2029f23 2536 /*! @brief Set the FSP field to a new value. */
mbed_official 324:406fd2029f23 2537 #define BW_I2S_RCR4_FSP(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSP) = (v))
mbed_official 324:406fd2029f23 2538 /*@}*/
mbed_official 324:406fd2029f23 2539
mbed_official 324:406fd2029f23 2540 /*!
mbed_official 324:406fd2029f23 2541 * @name Register I2S_RCR4, field ONDEM[2] (RW)
mbed_official 324:406fd2029f23 2542 *
mbed_official 324:406fd2029f23 2543 * When set, and the frame sync is generated internally, a frame sync is only
mbed_official 324:406fd2029f23 2544 * generated when the FIFO warning flag is clear.
mbed_official 324:406fd2029f23 2545 *
mbed_official 324:406fd2029f23 2546 * Values:
mbed_official 324:406fd2029f23 2547 * - 0 - Internal frame sync is generated continuously.
mbed_official 324:406fd2029f23 2548 * - 1 - Internal frame sync is generated when the FIFO warning flag is clear.
mbed_official 324:406fd2029f23 2549 */
mbed_official 324:406fd2029f23 2550 /*@{*/
mbed_official 324:406fd2029f23 2551 #define BP_I2S_RCR4_ONDEM (2U) /*!< Bit position for I2S_RCR4_ONDEM. */
mbed_official 324:406fd2029f23 2552 #define BM_I2S_RCR4_ONDEM (0x00000004U) /*!< Bit mask for I2S_RCR4_ONDEM. */
mbed_official 324:406fd2029f23 2553 #define BS_I2S_RCR4_ONDEM (1U) /*!< Bit field size in bits for I2S_RCR4_ONDEM. */
mbed_official 324:406fd2029f23 2554
mbed_official 324:406fd2029f23 2555 /*! @brief Read current value of the I2S_RCR4_ONDEM field. */
mbed_official 324:406fd2029f23 2556 #define BR_I2S_RCR4_ONDEM(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM))
mbed_official 324:406fd2029f23 2557
mbed_official 324:406fd2029f23 2558 /*! @brief Format value for bitfield I2S_RCR4_ONDEM. */
mbed_official 324:406fd2029f23 2559 #define BF_I2S_RCR4_ONDEM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_ONDEM) & BM_I2S_RCR4_ONDEM)
mbed_official 324:406fd2029f23 2560
mbed_official 324:406fd2029f23 2561 /*! @brief Set the ONDEM field to a new value. */
mbed_official 324:406fd2029f23 2562 #define BW_I2S_RCR4_ONDEM(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_ONDEM) = (v))
mbed_official 324:406fd2029f23 2563 /*@}*/
mbed_official 324:406fd2029f23 2564
mbed_official 324:406fd2029f23 2565 /*!
mbed_official 324:406fd2029f23 2566 * @name Register I2S_RCR4, field FSE[3] (RW)
mbed_official 324:406fd2029f23 2567 *
mbed_official 324:406fd2029f23 2568 * Values:
mbed_official 324:406fd2029f23 2569 * - 0 - Frame sync asserts with the first bit of the frame.
mbed_official 324:406fd2029f23 2570 * - 1 - Frame sync asserts one bit before the first bit of the frame.
mbed_official 324:406fd2029f23 2571 */
mbed_official 324:406fd2029f23 2572 /*@{*/
mbed_official 324:406fd2029f23 2573 #define BP_I2S_RCR4_FSE (3U) /*!< Bit position for I2S_RCR4_FSE. */
mbed_official 324:406fd2029f23 2574 #define BM_I2S_RCR4_FSE (0x00000008U) /*!< Bit mask for I2S_RCR4_FSE. */
mbed_official 324:406fd2029f23 2575 #define BS_I2S_RCR4_FSE (1U) /*!< Bit field size in bits for I2S_RCR4_FSE. */
mbed_official 324:406fd2029f23 2576
mbed_official 324:406fd2029f23 2577 /*! @brief Read current value of the I2S_RCR4_FSE field. */
mbed_official 324:406fd2029f23 2578 #define BR_I2S_RCR4_FSE(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE))
mbed_official 324:406fd2029f23 2579
mbed_official 324:406fd2029f23 2580 /*! @brief Format value for bitfield I2S_RCR4_FSE. */
mbed_official 324:406fd2029f23 2581 #define BF_I2S_RCR4_FSE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FSE) & BM_I2S_RCR4_FSE)
mbed_official 324:406fd2029f23 2582
mbed_official 324:406fd2029f23 2583 /*! @brief Set the FSE field to a new value. */
mbed_official 324:406fd2029f23 2584 #define BW_I2S_RCR4_FSE(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FSE) = (v))
mbed_official 324:406fd2029f23 2585 /*@}*/
mbed_official 324:406fd2029f23 2586
mbed_official 324:406fd2029f23 2587 /*!
mbed_official 324:406fd2029f23 2588 * @name Register I2S_RCR4, field MF[4] (RW)
mbed_official 324:406fd2029f23 2589 *
mbed_official 324:406fd2029f23 2590 * Configures whether the LSB or the MSB is received first.
mbed_official 324:406fd2029f23 2591 *
mbed_official 324:406fd2029f23 2592 * Values:
mbed_official 324:406fd2029f23 2593 * - 0 - LSB is received first.
mbed_official 324:406fd2029f23 2594 * - 1 - MSB is received first.
mbed_official 324:406fd2029f23 2595 */
mbed_official 324:406fd2029f23 2596 /*@{*/
mbed_official 324:406fd2029f23 2597 #define BP_I2S_RCR4_MF (4U) /*!< Bit position for I2S_RCR4_MF. */
mbed_official 324:406fd2029f23 2598 #define BM_I2S_RCR4_MF (0x00000010U) /*!< Bit mask for I2S_RCR4_MF. */
mbed_official 324:406fd2029f23 2599 #define BS_I2S_RCR4_MF (1U) /*!< Bit field size in bits for I2S_RCR4_MF. */
mbed_official 324:406fd2029f23 2600
mbed_official 324:406fd2029f23 2601 /*! @brief Read current value of the I2S_RCR4_MF field. */
mbed_official 324:406fd2029f23 2602 #define BR_I2S_RCR4_MF(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF))
mbed_official 324:406fd2029f23 2603
mbed_official 324:406fd2029f23 2604 /*! @brief Format value for bitfield I2S_RCR4_MF. */
mbed_official 324:406fd2029f23 2605 #define BF_I2S_RCR4_MF(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_MF) & BM_I2S_RCR4_MF)
mbed_official 324:406fd2029f23 2606
mbed_official 324:406fd2029f23 2607 /*! @brief Set the MF field to a new value. */
mbed_official 324:406fd2029f23 2608 #define BW_I2S_RCR4_MF(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_MF) = (v))
mbed_official 324:406fd2029f23 2609 /*@}*/
mbed_official 324:406fd2029f23 2610
mbed_official 324:406fd2029f23 2611 /*!
mbed_official 324:406fd2029f23 2612 * @name Register I2S_RCR4, field SYWD[12:8] (RW)
mbed_official 324:406fd2029f23 2613 *
mbed_official 324:406fd2029f23 2614 * Configures the length of the frame sync in number of bit clocks. The value
mbed_official 324:406fd2029f23 2615 * written must be one less than the number of bit clocks. For example, write 0 for
mbed_official 324:406fd2029f23 2616 * the frame sync to assert for one bit clock only. The sync width cannot be
mbed_official 324:406fd2029f23 2617 * configured longer than the first word of the frame.
mbed_official 324:406fd2029f23 2618 */
mbed_official 324:406fd2029f23 2619 /*@{*/
mbed_official 324:406fd2029f23 2620 #define BP_I2S_RCR4_SYWD (8U) /*!< Bit position for I2S_RCR4_SYWD. */
mbed_official 324:406fd2029f23 2621 #define BM_I2S_RCR4_SYWD (0x00001F00U) /*!< Bit mask for I2S_RCR4_SYWD. */
mbed_official 324:406fd2029f23 2622 #define BS_I2S_RCR4_SYWD (5U) /*!< Bit field size in bits for I2S_RCR4_SYWD. */
mbed_official 324:406fd2029f23 2623
mbed_official 324:406fd2029f23 2624 /*! @brief Read current value of the I2S_RCR4_SYWD field. */
mbed_official 324:406fd2029f23 2625 #define BR_I2S_RCR4_SYWD(x) (HW_I2S_RCR4(x).B.SYWD)
mbed_official 324:406fd2029f23 2626
mbed_official 324:406fd2029f23 2627 /*! @brief Format value for bitfield I2S_RCR4_SYWD. */
mbed_official 324:406fd2029f23 2628 #define BF_I2S_RCR4_SYWD(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_SYWD) & BM_I2S_RCR4_SYWD)
mbed_official 324:406fd2029f23 2629
mbed_official 324:406fd2029f23 2630 /*! @brief Set the SYWD field to a new value. */
mbed_official 324:406fd2029f23 2631 #define BW_I2S_RCR4_SYWD(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_SYWD) | BF_I2S_RCR4_SYWD(v)))
mbed_official 324:406fd2029f23 2632 /*@}*/
mbed_official 324:406fd2029f23 2633
mbed_official 324:406fd2029f23 2634 /*!
mbed_official 324:406fd2029f23 2635 * @name Register I2S_RCR4, field FRSZ[19:16] (RW)
mbed_official 324:406fd2029f23 2636 *
mbed_official 324:406fd2029f23 2637 * Configures the number of words in each frame. The value written must be one
mbed_official 324:406fd2029f23 2638 * less than the number of words in the frame. For example, write 0 for one word
mbed_official 324:406fd2029f23 2639 * per frame. The maximum supported frame size is 16 words.
mbed_official 324:406fd2029f23 2640 */
mbed_official 324:406fd2029f23 2641 /*@{*/
mbed_official 324:406fd2029f23 2642 #define BP_I2S_RCR4_FRSZ (16U) /*!< Bit position for I2S_RCR4_FRSZ. */
mbed_official 324:406fd2029f23 2643 #define BM_I2S_RCR4_FRSZ (0x000F0000U) /*!< Bit mask for I2S_RCR4_FRSZ. */
mbed_official 324:406fd2029f23 2644 #define BS_I2S_RCR4_FRSZ (4U) /*!< Bit field size in bits for I2S_RCR4_FRSZ. */
mbed_official 324:406fd2029f23 2645
mbed_official 324:406fd2029f23 2646 /*! @brief Read current value of the I2S_RCR4_FRSZ field. */
mbed_official 324:406fd2029f23 2647 #define BR_I2S_RCR4_FRSZ(x) (HW_I2S_RCR4(x).B.FRSZ)
mbed_official 324:406fd2029f23 2648
mbed_official 324:406fd2029f23 2649 /*! @brief Format value for bitfield I2S_RCR4_FRSZ. */
mbed_official 324:406fd2029f23 2650 #define BF_I2S_RCR4_FRSZ(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FRSZ) & BM_I2S_RCR4_FRSZ)
mbed_official 324:406fd2029f23 2651
mbed_official 324:406fd2029f23 2652 /*! @brief Set the FRSZ field to a new value. */
mbed_official 324:406fd2029f23 2653 #define BW_I2S_RCR4_FRSZ(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FRSZ) | BF_I2S_RCR4_FRSZ(v)))
mbed_official 324:406fd2029f23 2654 /*@}*/
mbed_official 324:406fd2029f23 2655
mbed_official 324:406fd2029f23 2656 /*!
mbed_official 324:406fd2029f23 2657 * @name Register I2S_RCR4, field FPACK[25:24] (RW)
mbed_official 324:406fd2029f23 2658 *
mbed_official 324:406fd2029f23 2659 * Enables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If
mbed_official 324:406fd2029f23 2660 * the word size is greater than 8-bit or 16-bit then only the first 8-bit or
mbed_official 324:406fd2029f23 2661 * 16-bits are stored to the FIFO. The first word in each frame always starts with a
mbed_official 324:406fd2029f23 2662 * new 32-bit FIFO word and the first bit shifted must be configured within the
mbed_official 324:406fd2029f23 2663 * first packed word. When FIFO packing is enabled, the FIFO read pointer will
mbed_official 324:406fd2029f23 2664 * only increment when the full 32-bit FIFO word has been read by software.
mbed_official 324:406fd2029f23 2665 *
mbed_official 324:406fd2029f23 2666 * Values:
mbed_official 324:406fd2029f23 2667 * - 00 - FIFO packing is disabled
mbed_official 324:406fd2029f23 2668 * - 01 - Reserved.
mbed_official 324:406fd2029f23 2669 * - 10 - 8-bit FIFO packing is enabled
mbed_official 324:406fd2029f23 2670 * - 11 - 16-bit FIFO packing is enabled
mbed_official 324:406fd2029f23 2671 */
mbed_official 324:406fd2029f23 2672 /*@{*/
mbed_official 324:406fd2029f23 2673 #define BP_I2S_RCR4_FPACK (24U) /*!< Bit position for I2S_RCR4_FPACK. */
mbed_official 324:406fd2029f23 2674 #define BM_I2S_RCR4_FPACK (0x03000000U) /*!< Bit mask for I2S_RCR4_FPACK. */
mbed_official 324:406fd2029f23 2675 #define BS_I2S_RCR4_FPACK (2U) /*!< Bit field size in bits for I2S_RCR4_FPACK. */
mbed_official 324:406fd2029f23 2676
mbed_official 324:406fd2029f23 2677 /*! @brief Read current value of the I2S_RCR4_FPACK field. */
mbed_official 324:406fd2029f23 2678 #define BR_I2S_RCR4_FPACK(x) (HW_I2S_RCR4(x).B.FPACK)
mbed_official 324:406fd2029f23 2679
mbed_official 324:406fd2029f23 2680 /*! @brief Format value for bitfield I2S_RCR4_FPACK. */
mbed_official 324:406fd2029f23 2681 #define BF_I2S_RCR4_FPACK(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FPACK) & BM_I2S_RCR4_FPACK)
mbed_official 324:406fd2029f23 2682
mbed_official 324:406fd2029f23 2683 /*! @brief Set the FPACK field to a new value. */
mbed_official 324:406fd2029f23 2684 #define BW_I2S_RCR4_FPACK(x, v) (HW_I2S_RCR4_WR(x, (HW_I2S_RCR4_RD(x) & ~BM_I2S_RCR4_FPACK) | BF_I2S_RCR4_FPACK(v)))
mbed_official 324:406fd2029f23 2685 /*@}*/
mbed_official 324:406fd2029f23 2686
mbed_official 324:406fd2029f23 2687 /*!
mbed_official 324:406fd2029f23 2688 * @name Register I2S_RCR4, field FCONT[28] (RW)
mbed_official 324:406fd2029f23 2689 *
mbed_official 324:406fd2029f23 2690 * Configures when the SAI will continue receiving after a FIFO error has been
mbed_official 324:406fd2029f23 2691 * detected.
mbed_official 324:406fd2029f23 2692 *
mbed_official 324:406fd2029f23 2693 * Values:
mbed_official 324:406fd2029f23 2694 * - 0 - On FIFO error, the SAI will continue from the start of the next frame
mbed_official 324:406fd2029f23 2695 * after the FIFO error flag has been cleared.
mbed_official 324:406fd2029f23 2696 * - 1 - On FIFO error, the SAI will continue from the same word that caused the
mbed_official 324:406fd2029f23 2697 * FIFO error to set after the FIFO warning flag has been cleared.
mbed_official 324:406fd2029f23 2698 */
mbed_official 324:406fd2029f23 2699 /*@{*/
mbed_official 324:406fd2029f23 2700 #define BP_I2S_RCR4_FCONT (28U) /*!< Bit position for I2S_RCR4_FCONT. */
mbed_official 324:406fd2029f23 2701 #define BM_I2S_RCR4_FCONT (0x10000000U) /*!< Bit mask for I2S_RCR4_FCONT. */
mbed_official 324:406fd2029f23 2702 #define BS_I2S_RCR4_FCONT (1U) /*!< Bit field size in bits for I2S_RCR4_FCONT. */
mbed_official 324:406fd2029f23 2703
mbed_official 324:406fd2029f23 2704 /*! @brief Read current value of the I2S_RCR4_FCONT field. */
mbed_official 324:406fd2029f23 2705 #define BR_I2S_RCR4_FCONT(x) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT))
mbed_official 324:406fd2029f23 2706
mbed_official 324:406fd2029f23 2707 /*! @brief Format value for bitfield I2S_RCR4_FCONT. */
mbed_official 324:406fd2029f23 2708 #define BF_I2S_RCR4_FCONT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR4_FCONT) & BM_I2S_RCR4_FCONT)
mbed_official 324:406fd2029f23 2709
mbed_official 324:406fd2029f23 2710 /*! @brief Set the FCONT field to a new value. */
mbed_official 324:406fd2029f23 2711 #define BW_I2S_RCR4_FCONT(x, v) (BITBAND_ACCESS32(HW_I2S_RCR4_ADDR(x), BP_I2S_RCR4_FCONT) = (v))
mbed_official 324:406fd2029f23 2712 /*@}*/
mbed_official 324:406fd2029f23 2713
mbed_official 324:406fd2029f23 2714 /*******************************************************************************
mbed_official 324:406fd2029f23 2715 * HW_I2S_RCR5 - SAI Receive Configuration 5 Register
mbed_official 324:406fd2029f23 2716 ******************************************************************************/
mbed_official 324:406fd2029f23 2717
mbed_official 324:406fd2029f23 2718 /*!
mbed_official 324:406fd2029f23 2719 * @brief HW_I2S_RCR5 - SAI Receive Configuration 5 Register (RW)
mbed_official 324:406fd2029f23 2720 *
mbed_official 324:406fd2029f23 2721 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2722 *
mbed_official 324:406fd2029f23 2723 * This register must not be altered when RCSR[RE] is set.
mbed_official 324:406fd2029f23 2724 */
mbed_official 324:406fd2029f23 2725 typedef union _hw_i2s_rcr5
mbed_official 324:406fd2029f23 2726 {
mbed_official 324:406fd2029f23 2727 uint32_t U;
mbed_official 324:406fd2029f23 2728 struct _hw_i2s_rcr5_bitfields
mbed_official 324:406fd2029f23 2729 {
mbed_official 324:406fd2029f23 2730 uint32_t RESERVED0 : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 2731 uint32_t FBT : 5; /*!< [12:8] First Bit Shifted */
mbed_official 324:406fd2029f23 2732 uint32_t RESERVED1 : 3; /*!< [15:13] */
mbed_official 324:406fd2029f23 2733 uint32_t W0W : 5; /*!< [20:16] Word 0 Width */
mbed_official 324:406fd2029f23 2734 uint32_t RESERVED2 : 3; /*!< [23:21] */
mbed_official 324:406fd2029f23 2735 uint32_t WNW : 5; /*!< [28:24] Word N Width */
mbed_official 324:406fd2029f23 2736 uint32_t RESERVED3 : 3; /*!< [31:29] */
mbed_official 324:406fd2029f23 2737 } B;
mbed_official 324:406fd2029f23 2738 } hw_i2s_rcr5_t;
mbed_official 324:406fd2029f23 2739
mbed_official 324:406fd2029f23 2740 /*!
mbed_official 324:406fd2029f23 2741 * @name Constants and macros for entire I2S_RCR5 register
mbed_official 324:406fd2029f23 2742 */
mbed_official 324:406fd2029f23 2743 /*@{*/
mbed_official 324:406fd2029f23 2744 #define HW_I2S_RCR5_ADDR(x) ((x) + 0x94U)
mbed_official 324:406fd2029f23 2745
mbed_official 324:406fd2029f23 2746 #define HW_I2S_RCR5(x) (*(__IO hw_i2s_rcr5_t *) HW_I2S_RCR5_ADDR(x))
mbed_official 324:406fd2029f23 2747 #define HW_I2S_RCR5_RD(x) (HW_I2S_RCR5(x).U)
mbed_official 324:406fd2029f23 2748 #define HW_I2S_RCR5_WR(x, v) (HW_I2S_RCR5(x).U = (v))
mbed_official 324:406fd2029f23 2749 #define HW_I2S_RCR5_SET(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) | (v)))
mbed_official 324:406fd2029f23 2750 #define HW_I2S_RCR5_CLR(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2751 #define HW_I2S_RCR5_TOG(x, v) (HW_I2S_RCR5_WR(x, HW_I2S_RCR5_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2752 /*@}*/
mbed_official 324:406fd2029f23 2753
mbed_official 324:406fd2029f23 2754 /*
mbed_official 324:406fd2029f23 2755 * Constants & macros for individual I2S_RCR5 bitfields
mbed_official 324:406fd2029f23 2756 */
mbed_official 324:406fd2029f23 2757
mbed_official 324:406fd2029f23 2758 /*!
mbed_official 324:406fd2029f23 2759 * @name Register I2S_RCR5, field FBT[12:8] (RW)
mbed_official 324:406fd2029f23 2760 *
mbed_official 324:406fd2029f23 2761 * Configures the bit index for the first bit received for each word in the
mbed_official 324:406fd2029f23 2762 * frame. If configured for MSB First, the index of the next bit received is one less
mbed_official 324:406fd2029f23 2763 * than the current bit received. If configured for LSB First, the index of the
mbed_official 324:406fd2029f23 2764 * next bit received is one more than the current bit received. The value written
mbed_official 324:406fd2029f23 2765 * must be greater than or equal to the word width when configured for MSB
mbed_official 324:406fd2029f23 2766 * First. The value written must be less than or equal to 31-word width when
mbed_official 324:406fd2029f23 2767 * configured for LSB First.
mbed_official 324:406fd2029f23 2768 */
mbed_official 324:406fd2029f23 2769 /*@{*/
mbed_official 324:406fd2029f23 2770 #define BP_I2S_RCR5_FBT (8U) /*!< Bit position for I2S_RCR5_FBT. */
mbed_official 324:406fd2029f23 2771 #define BM_I2S_RCR5_FBT (0x00001F00U) /*!< Bit mask for I2S_RCR5_FBT. */
mbed_official 324:406fd2029f23 2772 #define BS_I2S_RCR5_FBT (5U) /*!< Bit field size in bits for I2S_RCR5_FBT. */
mbed_official 324:406fd2029f23 2773
mbed_official 324:406fd2029f23 2774 /*! @brief Read current value of the I2S_RCR5_FBT field. */
mbed_official 324:406fd2029f23 2775 #define BR_I2S_RCR5_FBT(x) (HW_I2S_RCR5(x).B.FBT)
mbed_official 324:406fd2029f23 2776
mbed_official 324:406fd2029f23 2777 /*! @brief Format value for bitfield I2S_RCR5_FBT. */
mbed_official 324:406fd2029f23 2778 #define BF_I2S_RCR5_FBT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_FBT) & BM_I2S_RCR5_FBT)
mbed_official 324:406fd2029f23 2779
mbed_official 324:406fd2029f23 2780 /*! @brief Set the FBT field to a new value. */
mbed_official 324:406fd2029f23 2781 #define BW_I2S_RCR5_FBT(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_FBT) | BF_I2S_RCR5_FBT(v)))
mbed_official 324:406fd2029f23 2782 /*@}*/
mbed_official 324:406fd2029f23 2783
mbed_official 324:406fd2029f23 2784 /*!
mbed_official 324:406fd2029f23 2785 * @name Register I2S_RCR5, field W0W[20:16] (RW)
mbed_official 324:406fd2029f23 2786 *
mbed_official 324:406fd2029f23 2787 * Configures the number of bits in the first word in each frame. The value
mbed_official 324:406fd2029f23 2788 * written must be one less than the number of bits in the first word. Word width of
mbed_official 324:406fd2029f23 2789 * less than 8 bits is not supported if there is only one word per frame.
mbed_official 324:406fd2029f23 2790 */
mbed_official 324:406fd2029f23 2791 /*@{*/
mbed_official 324:406fd2029f23 2792 #define BP_I2S_RCR5_W0W (16U) /*!< Bit position for I2S_RCR5_W0W. */
mbed_official 324:406fd2029f23 2793 #define BM_I2S_RCR5_W0W (0x001F0000U) /*!< Bit mask for I2S_RCR5_W0W. */
mbed_official 324:406fd2029f23 2794 #define BS_I2S_RCR5_W0W (5U) /*!< Bit field size in bits for I2S_RCR5_W0W. */
mbed_official 324:406fd2029f23 2795
mbed_official 324:406fd2029f23 2796 /*! @brief Read current value of the I2S_RCR5_W0W field. */
mbed_official 324:406fd2029f23 2797 #define BR_I2S_RCR5_W0W(x) (HW_I2S_RCR5(x).B.W0W)
mbed_official 324:406fd2029f23 2798
mbed_official 324:406fd2029f23 2799 /*! @brief Format value for bitfield I2S_RCR5_W0W. */
mbed_official 324:406fd2029f23 2800 #define BF_I2S_RCR5_W0W(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_W0W) & BM_I2S_RCR5_W0W)
mbed_official 324:406fd2029f23 2801
mbed_official 324:406fd2029f23 2802 /*! @brief Set the W0W field to a new value. */
mbed_official 324:406fd2029f23 2803 #define BW_I2S_RCR5_W0W(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_W0W) | BF_I2S_RCR5_W0W(v)))
mbed_official 324:406fd2029f23 2804 /*@}*/
mbed_official 324:406fd2029f23 2805
mbed_official 324:406fd2029f23 2806 /*!
mbed_official 324:406fd2029f23 2807 * @name Register I2S_RCR5, field WNW[28:24] (RW)
mbed_official 324:406fd2029f23 2808 *
mbed_official 324:406fd2029f23 2809 * Configures the number of bits in each word, for each word except the first in
mbed_official 324:406fd2029f23 2810 * the frame. The value written must be one less than the number of bits per
mbed_official 324:406fd2029f23 2811 * word. Word width of less than 8 bits is not supported.
mbed_official 324:406fd2029f23 2812 */
mbed_official 324:406fd2029f23 2813 /*@{*/
mbed_official 324:406fd2029f23 2814 #define BP_I2S_RCR5_WNW (24U) /*!< Bit position for I2S_RCR5_WNW. */
mbed_official 324:406fd2029f23 2815 #define BM_I2S_RCR5_WNW (0x1F000000U) /*!< Bit mask for I2S_RCR5_WNW. */
mbed_official 324:406fd2029f23 2816 #define BS_I2S_RCR5_WNW (5U) /*!< Bit field size in bits for I2S_RCR5_WNW. */
mbed_official 324:406fd2029f23 2817
mbed_official 324:406fd2029f23 2818 /*! @brief Read current value of the I2S_RCR5_WNW field. */
mbed_official 324:406fd2029f23 2819 #define BR_I2S_RCR5_WNW(x) (HW_I2S_RCR5(x).B.WNW)
mbed_official 324:406fd2029f23 2820
mbed_official 324:406fd2029f23 2821 /*! @brief Format value for bitfield I2S_RCR5_WNW. */
mbed_official 324:406fd2029f23 2822 #define BF_I2S_RCR5_WNW(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RCR5_WNW) & BM_I2S_RCR5_WNW)
mbed_official 324:406fd2029f23 2823
mbed_official 324:406fd2029f23 2824 /*! @brief Set the WNW field to a new value. */
mbed_official 324:406fd2029f23 2825 #define BW_I2S_RCR5_WNW(x, v) (HW_I2S_RCR5_WR(x, (HW_I2S_RCR5_RD(x) & ~BM_I2S_RCR5_WNW) | BF_I2S_RCR5_WNW(v)))
mbed_official 324:406fd2029f23 2826 /*@}*/
mbed_official 324:406fd2029f23 2827
mbed_official 324:406fd2029f23 2828 /*******************************************************************************
mbed_official 324:406fd2029f23 2829 * HW_I2S_RDRn - SAI Receive Data Register
mbed_official 324:406fd2029f23 2830 ******************************************************************************/
mbed_official 324:406fd2029f23 2831
mbed_official 324:406fd2029f23 2832 /*!
mbed_official 324:406fd2029f23 2833 * @brief HW_I2S_RDRn - SAI Receive Data Register (RO)
mbed_official 324:406fd2029f23 2834 *
mbed_official 324:406fd2029f23 2835 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2836 *
mbed_official 324:406fd2029f23 2837 * Reading this register introduces one additional peripheral clock wait state
mbed_official 324:406fd2029f23 2838 * on each read.
mbed_official 324:406fd2029f23 2839 */
mbed_official 324:406fd2029f23 2840 typedef union _hw_i2s_rdrn
mbed_official 324:406fd2029f23 2841 {
mbed_official 324:406fd2029f23 2842 uint32_t U;
mbed_official 324:406fd2029f23 2843 struct _hw_i2s_rdrn_bitfields
mbed_official 324:406fd2029f23 2844 {
mbed_official 324:406fd2029f23 2845 uint32_t RDR : 32; /*!< [31:0] Receive Data Register */
mbed_official 324:406fd2029f23 2846 } B;
mbed_official 324:406fd2029f23 2847 } hw_i2s_rdrn_t;
mbed_official 324:406fd2029f23 2848
mbed_official 324:406fd2029f23 2849 /*!
mbed_official 324:406fd2029f23 2850 * @name Constants and macros for entire I2S_RDRn register
mbed_official 324:406fd2029f23 2851 */
mbed_official 324:406fd2029f23 2852 /*@{*/
mbed_official 324:406fd2029f23 2853 #define HW_I2S_RDRn_COUNT (1U)
mbed_official 324:406fd2029f23 2854
mbed_official 324:406fd2029f23 2855 #define HW_I2S_RDRn_ADDR(x, n) ((x) + 0xA0U + (0x4U * (n)))
mbed_official 324:406fd2029f23 2856
mbed_official 324:406fd2029f23 2857 #define HW_I2S_RDRn(x, n) (*(__I hw_i2s_rdrn_t *) HW_I2S_RDRn_ADDR(x, n))
mbed_official 324:406fd2029f23 2858 #define HW_I2S_RDRn_RD(x, n) (HW_I2S_RDRn(x, n).U)
mbed_official 324:406fd2029f23 2859 /*@}*/
mbed_official 324:406fd2029f23 2860
mbed_official 324:406fd2029f23 2861 /*
mbed_official 324:406fd2029f23 2862 * Constants & macros for individual I2S_RDRn bitfields
mbed_official 324:406fd2029f23 2863 */
mbed_official 324:406fd2029f23 2864
mbed_official 324:406fd2029f23 2865 /*!
mbed_official 324:406fd2029f23 2866 * @name Register I2S_RDRn, field RDR[31:0] (RO)
mbed_official 324:406fd2029f23 2867 *
mbed_official 324:406fd2029f23 2868 * The corresponding RCR3[RCE] bit must be set before accessing the channel's
mbed_official 324:406fd2029f23 2869 * receive data register. Reads from this register when the receive FIFO is not
mbed_official 324:406fd2029f23 2870 * empty will return the data from the top of the receive FIFO. Reads from this
mbed_official 324:406fd2029f23 2871 * register when the receive FIFO is empty are ignored.
mbed_official 324:406fd2029f23 2872 */
mbed_official 324:406fd2029f23 2873 /*@{*/
mbed_official 324:406fd2029f23 2874 #define BP_I2S_RDRn_RDR (0U) /*!< Bit position for I2S_RDRn_RDR. */
mbed_official 324:406fd2029f23 2875 #define BM_I2S_RDRn_RDR (0xFFFFFFFFU) /*!< Bit mask for I2S_RDRn_RDR. */
mbed_official 324:406fd2029f23 2876 #define BS_I2S_RDRn_RDR (32U) /*!< Bit field size in bits for I2S_RDRn_RDR. */
mbed_official 324:406fd2029f23 2877
mbed_official 324:406fd2029f23 2878 /*! @brief Read current value of the I2S_RDRn_RDR field. */
mbed_official 324:406fd2029f23 2879 #define BR_I2S_RDRn_RDR(x, n) (HW_I2S_RDRn(x, n).U)
mbed_official 324:406fd2029f23 2880 /*@}*/
mbed_official 324:406fd2029f23 2881
mbed_official 324:406fd2029f23 2882 /*******************************************************************************
mbed_official 324:406fd2029f23 2883 * HW_I2S_RFRn - SAI Receive FIFO Register
mbed_official 324:406fd2029f23 2884 ******************************************************************************/
mbed_official 324:406fd2029f23 2885
mbed_official 324:406fd2029f23 2886 /*!
mbed_official 324:406fd2029f23 2887 * @brief HW_I2S_RFRn - SAI Receive FIFO Register (RO)
mbed_official 324:406fd2029f23 2888 *
mbed_official 324:406fd2029f23 2889 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2890 *
mbed_official 324:406fd2029f23 2891 * The MSB of the read and write pointers is used to distinguish between FIFO
mbed_official 324:406fd2029f23 2892 * full and empty conditions. If the read and write pointers are identical, then
mbed_official 324:406fd2029f23 2893 * the FIFO is empty. If the read and write pointers are identical except for the
mbed_official 324:406fd2029f23 2894 * MSB, then the FIFO is full.
mbed_official 324:406fd2029f23 2895 */
mbed_official 324:406fd2029f23 2896 typedef union _hw_i2s_rfrn
mbed_official 324:406fd2029f23 2897 {
mbed_official 324:406fd2029f23 2898 uint32_t U;
mbed_official 324:406fd2029f23 2899 struct _hw_i2s_rfrn_bitfields
mbed_official 324:406fd2029f23 2900 {
mbed_official 324:406fd2029f23 2901 uint32_t RFP : 4; /*!< [3:0] Read FIFO Pointer */
mbed_official 324:406fd2029f23 2902 uint32_t RESERVED0 : 12; /*!< [15:4] */
mbed_official 324:406fd2029f23 2903 uint32_t WFP : 4; /*!< [19:16] Write FIFO Pointer */
mbed_official 324:406fd2029f23 2904 uint32_t RESERVED1 : 12; /*!< [31:20] */
mbed_official 324:406fd2029f23 2905 } B;
mbed_official 324:406fd2029f23 2906 } hw_i2s_rfrn_t;
mbed_official 324:406fd2029f23 2907
mbed_official 324:406fd2029f23 2908 /*!
mbed_official 324:406fd2029f23 2909 * @name Constants and macros for entire I2S_RFRn register
mbed_official 324:406fd2029f23 2910 */
mbed_official 324:406fd2029f23 2911 /*@{*/
mbed_official 324:406fd2029f23 2912 #define HW_I2S_RFRn_COUNT (1U)
mbed_official 324:406fd2029f23 2913
mbed_official 324:406fd2029f23 2914 #define HW_I2S_RFRn_ADDR(x, n) ((x) + 0xC0U + (0x4U * (n)))
mbed_official 324:406fd2029f23 2915
mbed_official 324:406fd2029f23 2916 #define HW_I2S_RFRn(x, n) (*(__I hw_i2s_rfrn_t *) HW_I2S_RFRn_ADDR(x, n))
mbed_official 324:406fd2029f23 2917 #define HW_I2S_RFRn_RD(x, n) (HW_I2S_RFRn(x, n).U)
mbed_official 324:406fd2029f23 2918 /*@}*/
mbed_official 324:406fd2029f23 2919
mbed_official 324:406fd2029f23 2920 /*
mbed_official 324:406fd2029f23 2921 * Constants & macros for individual I2S_RFRn bitfields
mbed_official 324:406fd2029f23 2922 */
mbed_official 324:406fd2029f23 2923
mbed_official 324:406fd2029f23 2924 /*!
mbed_official 324:406fd2029f23 2925 * @name Register I2S_RFRn, field RFP[3:0] (RO)
mbed_official 324:406fd2029f23 2926 *
mbed_official 324:406fd2029f23 2927 * FIFO read pointer for receive data channel.
mbed_official 324:406fd2029f23 2928 */
mbed_official 324:406fd2029f23 2929 /*@{*/
mbed_official 324:406fd2029f23 2930 #define BP_I2S_RFRn_RFP (0U) /*!< Bit position for I2S_RFRn_RFP. */
mbed_official 324:406fd2029f23 2931 #define BM_I2S_RFRn_RFP (0x0000000FU) /*!< Bit mask for I2S_RFRn_RFP. */
mbed_official 324:406fd2029f23 2932 #define BS_I2S_RFRn_RFP (4U) /*!< Bit field size in bits for I2S_RFRn_RFP. */
mbed_official 324:406fd2029f23 2933
mbed_official 324:406fd2029f23 2934 /*! @brief Read current value of the I2S_RFRn_RFP field. */
mbed_official 324:406fd2029f23 2935 #define BR_I2S_RFRn_RFP(x, n) (HW_I2S_RFRn(x, n).B.RFP)
mbed_official 324:406fd2029f23 2936 /*@}*/
mbed_official 324:406fd2029f23 2937
mbed_official 324:406fd2029f23 2938 /*!
mbed_official 324:406fd2029f23 2939 * @name Register I2S_RFRn, field WFP[19:16] (RO)
mbed_official 324:406fd2029f23 2940 *
mbed_official 324:406fd2029f23 2941 * FIFO write pointer for receive data channel.
mbed_official 324:406fd2029f23 2942 */
mbed_official 324:406fd2029f23 2943 /*@{*/
mbed_official 324:406fd2029f23 2944 #define BP_I2S_RFRn_WFP (16U) /*!< Bit position for I2S_RFRn_WFP. */
mbed_official 324:406fd2029f23 2945 #define BM_I2S_RFRn_WFP (0x000F0000U) /*!< Bit mask for I2S_RFRn_WFP. */
mbed_official 324:406fd2029f23 2946 #define BS_I2S_RFRn_WFP (4U) /*!< Bit field size in bits for I2S_RFRn_WFP. */
mbed_official 324:406fd2029f23 2947
mbed_official 324:406fd2029f23 2948 /*! @brief Read current value of the I2S_RFRn_WFP field. */
mbed_official 324:406fd2029f23 2949 #define BR_I2S_RFRn_WFP(x, n) (HW_I2S_RFRn(x, n).B.WFP)
mbed_official 324:406fd2029f23 2950 /*@}*/
mbed_official 324:406fd2029f23 2951
mbed_official 324:406fd2029f23 2952 /*******************************************************************************
mbed_official 324:406fd2029f23 2953 * HW_I2S_RMR - SAI Receive Mask Register
mbed_official 324:406fd2029f23 2954 ******************************************************************************/
mbed_official 324:406fd2029f23 2955
mbed_official 324:406fd2029f23 2956 /*!
mbed_official 324:406fd2029f23 2957 * @brief HW_I2S_RMR - SAI Receive Mask Register (RW)
mbed_official 324:406fd2029f23 2958 *
mbed_official 324:406fd2029f23 2959 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2960 *
mbed_official 324:406fd2029f23 2961 * This register is double-buffered and updates: When RCSR[RE] is first set At
mbed_official 324:406fd2029f23 2962 * the end of each frame This allows the masked words in each frame to change from
mbed_official 324:406fd2029f23 2963 * frame to frame.
mbed_official 324:406fd2029f23 2964 */
mbed_official 324:406fd2029f23 2965 typedef union _hw_i2s_rmr
mbed_official 324:406fd2029f23 2966 {
mbed_official 324:406fd2029f23 2967 uint32_t U;
mbed_official 324:406fd2029f23 2968 struct _hw_i2s_rmr_bitfields
mbed_official 324:406fd2029f23 2969 {
mbed_official 324:406fd2029f23 2970 uint32_t RWM : 16; /*!< [15:0] Receive Word Mask */
mbed_official 324:406fd2029f23 2971 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 2972 } B;
mbed_official 324:406fd2029f23 2973 } hw_i2s_rmr_t;
mbed_official 324:406fd2029f23 2974
mbed_official 324:406fd2029f23 2975 /*!
mbed_official 324:406fd2029f23 2976 * @name Constants and macros for entire I2S_RMR register
mbed_official 324:406fd2029f23 2977 */
mbed_official 324:406fd2029f23 2978 /*@{*/
mbed_official 324:406fd2029f23 2979 #define HW_I2S_RMR_ADDR(x) ((x) + 0xE0U)
mbed_official 324:406fd2029f23 2980
mbed_official 324:406fd2029f23 2981 #define HW_I2S_RMR(x) (*(__IO hw_i2s_rmr_t *) HW_I2S_RMR_ADDR(x))
mbed_official 324:406fd2029f23 2982 #define HW_I2S_RMR_RD(x) (HW_I2S_RMR(x).U)
mbed_official 324:406fd2029f23 2983 #define HW_I2S_RMR_WR(x, v) (HW_I2S_RMR(x).U = (v))
mbed_official 324:406fd2029f23 2984 #define HW_I2S_RMR_SET(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) | (v)))
mbed_official 324:406fd2029f23 2985 #define HW_I2S_RMR_CLR(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2986 #define HW_I2S_RMR_TOG(x, v) (HW_I2S_RMR_WR(x, HW_I2S_RMR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2987 /*@}*/
mbed_official 324:406fd2029f23 2988
mbed_official 324:406fd2029f23 2989 /*
mbed_official 324:406fd2029f23 2990 * Constants & macros for individual I2S_RMR bitfields
mbed_official 324:406fd2029f23 2991 */
mbed_official 324:406fd2029f23 2992
mbed_official 324:406fd2029f23 2993 /*!
mbed_official 324:406fd2029f23 2994 * @name Register I2S_RMR, field RWM[15:0] (RW)
mbed_official 324:406fd2029f23 2995 *
mbed_official 324:406fd2029f23 2996 * Configures whether the receive word is masked (received data ignored and not
mbed_official 324:406fd2029f23 2997 * written to receive FIFO) for the corresponding word in the frame.
mbed_official 324:406fd2029f23 2998 *
mbed_official 324:406fd2029f23 2999 * Values:
mbed_official 324:406fd2029f23 3000 * - 0 - Word N is enabled.
mbed_official 324:406fd2029f23 3001 * - 1 - Word N is masked.
mbed_official 324:406fd2029f23 3002 */
mbed_official 324:406fd2029f23 3003 /*@{*/
mbed_official 324:406fd2029f23 3004 #define BP_I2S_RMR_RWM (0U) /*!< Bit position for I2S_RMR_RWM. */
mbed_official 324:406fd2029f23 3005 #define BM_I2S_RMR_RWM (0x0000FFFFU) /*!< Bit mask for I2S_RMR_RWM. */
mbed_official 324:406fd2029f23 3006 #define BS_I2S_RMR_RWM (16U) /*!< Bit field size in bits for I2S_RMR_RWM. */
mbed_official 324:406fd2029f23 3007
mbed_official 324:406fd2029f23 3008 /*! @brief Read current value of the I2S_RMR_RWM field. */
mbed_official 324:406fd2029f23 3009 #define BR_I2S_RMR_RWM(x) (HW_I2S_RMR(x).B.RWM)
mbed_official 324:406fd2029f23 3010
mbed_official 324:406fd2029f23 3011 /*! @brief Format value for bitfield I2S_RMR_RWM. */
mbed_official 324:406fd2029f23 3012 #define BF_I2S_RMR_RWM(v) ((uint32_t)((uint32_t)(v) << BP_I2S_RMR_RWM) & BM_I2S_RMR_RWM)
mbed_official 324:406fd2029f23 3013
mbed_official 324:406fd2029f23 3014 /*! @brief Set the RWM field to a new value. */
mbed_official 324:406fd2029f23 3015 #define BW_I2S_RMR_RWM(x, v) (HW_I2S_RMR_WR(x, (HW_I2S_RMR_RD(x) & ~BM_I2S_RMR_RWM) | BF_I2S_RMR_RWM(v)))
mbed_official 324:406fd2029f23 3016 /*@}*/
mbed_official 324:406fd2029f23 3017
mbed_official 324:406fd2029f23 3018 /*******************************************************************************
mbed_official 324:406fd2029f23 3019 * HW_I2S_MCR - SAI MCLK Control Register
mbed_official 324:406fd2029f23 3020 ******************************************************************************/
mbed_official 324:406fd2029f23 3021
mbed_official 324:406fd2029f23 3022 /*!
mbed_official 324:406fd2029f23 3023 * @brief HW_I2S_MCR - SAI MCLK Control Register (RW)
mbed_official 324:406fd2029f23 3024 *
mbed_official 324:406fd2029f23 3025 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3026 *
mbed_official 324:406fd2029f23 3027 * The MCLK Control Register (MCR) controls the clock source and direction of
mbed_official 324:406fd2029f23 3028 * the audio master clock.
mbed_official 324:406fd2029f23 3029 */
mbed_official 324:406fd2029f23 3030 typedef union _hw_i2s_mcr
mbed_official 324:406fd2029f23 3031 {
mbed_official 324:406fd2029f23 3032 uint32_t U;
mbed_official 324:406fd2029f23 3033 struct _hw_i2s_mcr_bitfields
mbed_official 324:406fd2029f23 3034 {
mbed_official 324:406fd2029f23 3035 uint32_t RESERVED0 : 24; /*!< [23:0] */
mbed_official 324:406fd2029f23 3036 uint32_t MICS : 2; /*!< [25:24] MCLK Input Clock Select */
mbed_official 324:406fd2029f23 3037 uint32_t RESERVED1 : 4; /*!< [29:26] */
mbed_official 324:406fd2029f23 3038 uint32_t MOE : 1; /*!< [30] MCLK Output Enable */
mbed_official 324:406fd2029f23 3039 uint32_t DUF : 1; /*!< [31] Divider Update Flag */
mbed_official 324:406fd2029f23 3040 } B;
mbed_official 324:406fd2029f23 3041 } hw_i2s_mcr_t;
mbed_official 324:406fd2029f23 3042
mbed_official 324:406fd2029f23 3043 /*!
mbed_official 324:406fd2029f23 3044 * @name Constants and macros for entire I2S_MCR register
mbed_official 324:406fd2029f23 3045 */
mbed_official 324:406fd2029f23 3046 /*@{*/
mbed_official 324:406fd2029f23 3047 #define HW_I2S_MCR_ADDR(x) ((x) + 0x100U)
mbed_official 324:406fd2029f23 3048
mbed_official 324:406fd2029f23 3049 #define HW_I2S_MCR(x) (*(__IO hw_i2s_mcr_t *) HW_I2S_MCR_ADDR(x))
mbed_official 324:406fd2029f23 3050 #define HW_I2S_MCR_RD(x) (HW_I2S_MCR(x).U)
mbed_official 324:406fd2029f23 3051 #define HW_I2S_MCR_WR(x, v) (HW_I2S_MCR(x).U = (v))
mbed_official 324:406fd2029f23 3052 #define HW_I2S_MCR_SET(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) | (v)))
mbed_official 324:406fd2029f23 3053 #define HW_I2S_MCR_CLR(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3054 #define HW_I2S_MCR_TOG(x, v) (HW_I2S_MCR_WR(x, HW_I2S_MCR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3055 /*@}*/
mbed_official 324:406fd2029f23 3056
mbed_official 324:406fd2029f23 3057 /*
mbed_official 324:406fd2029f23 3058 * Constants & macros for individual I2S_MCR bitfields
mbed_official 324:406fd2029f23 3059 */
mbed_official 324:406fd2029f23 3060
mbed_official 324:406fd2029f23 3061 /*!
mbed_official 324:406fd2029f23 3062 * @name Register I2S_MCR, field MICS[25:24] (RW)
mbed_official 324:406fd2029f23 3063 *
mbed_official 324:406fd2029f23 3064 * Selects the clock input to the MCLK divider. This field cannot be changed
mbed_official 324:406fd2029f23 3065 * while the MCLK divider is enabled. See the chip configuration details for
mbed_official 324:406fd2029f23 3066 * information about the connections to these inputs.
mbed_official 324:406fd2029f23 3067 *
mbed_official 324:406fd2029f23 3068 * Values:
mbed_official 324:406fd2029f23 3069 * - 00 - MCLK divider input clock 0 selected.
mbed_official 324:406fd2029f23 3070 * - 01 - MCLK divider input clock 1 selected.
mbed_official 324:406fd2029f23 3071 * - 10 - MCLK divider input clock 2 selected.
mbed_official 324:406fd2029f23 3072 * - 11 - MCLK divider input clock 3 selected.
mbed_official 324:406fd2029f23 3073 */
mbed_official 324:406fd2029f23 3074 /*@{*/
mbed_official 324:406fd2029f23 3075 #define BP_I2S_MCR_MICS (24U) /*!< Bit position for I2S_MCR_MICS. */
mbed_official 324:406fd2029f23 3076 #define BM_I2S_MCR_MICS (0x03000000U) /*!< Bit mask for I2S_MCR_MICS. */
mbed_official 324:406fd2029f23 3077 #define BS_I2S_MCR_MICS (2U) /*!< Bit field size in bits for I2S_MCR_MICS. */
mbed_official 324:406fd2029f23 3078
mbed_official 324:406fd2029f23 3079 /*! @brief Read current value of the I2S_MCR_MICS field. */
mbed_official 324:406fd2029f23 3080 #define BR_I2S_MCR_MICS(x) (HW_I2S_MCR(x).B.MICS)
mbed_official 324:406fd2029f23 3081
mbed_official 324:406fd2029f23 3082 /*! @brief Format value for bitfield I2S_MCR_MICS. */
mbed_official 324:406fd2029f23 3083 #define BF_I2S_MCR_MICS(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MICS) & BM_I2S_MCR_MICS)
mbed_official 324:406fd2029f23 3084
mbed_official 324:406fd2029f23 3085 /*! @brief Set the MICS field to a new value. */
mbed_official 324:406fd2029f23 3086 #define BW_I2S_MCR_MICS(x, v) (HW_I2S_MCR_WR(x, (HW_I2S_MCR_RD(x) & ~BM_I2S_MCR_MICS) | BF_I2S_MCR_MICS(v)))
mbed_official 324:406fd2029f23 3087 /*@}*/
mbed_official 324:406fd2029f23 3088
mbed_official 324:406fd2029f23 3089 /*!
mbed_official 324:406fd2029f23 3090 * @name Register I2S_MCR, field MOE[30] (RW)
mbed_official 324:406fd2029f23 3091 *
mbed_official 324:406fd2029f23 3092 * Enables the MCLK divider and configures the MCLK signal pin as an output.
mbed_official 324:406fd2029f23 3093 * When software clears this field, it remains set until the MCLK divider is fully
mbed_official 324:406fd2029f23 3094 * disabled.
mbed_official 324:406fd2029f23 3095 *
mbed_official 324:406fd2029f23 3096 * Values:
mbed_official 324:406fd2029f23 3097 * - 0 - MCLK signal pin is configured as an input that bypasses the MCLK
mbed_official 324:406fd2029f23 3098 * divider.
mbed_official 324:406fd2029f23 3099 * - 1 - MCLK signal pin is configured as an output from the MCLK divider and
mbed_official 324:406fd2029f23 3100 * the MCLK divider is enabled.
mbed_official 324:406fd2029f23 3101 */
mbed_official 324:406fd2029f23 3102 /*@{*/
mbed_official 324:406fd2029f23 3103 #define BP_I2S_MCR_MOE (30U) /*!< Bit position for I2S_MCR_MOE. */
mbed_official 324:406fd2029f23 3104 #define BM_I2S_MCR_MOE (0x40000000U) /*!< Bit mask for I2S_MCR_MOE. */
mbed_official 324:406fd2029f23 3105 #define BS_I2S_MCR_MOE (1U) /*!< Bit field size in bits for I2S_MCR_MOE. */
mbed_official 324:406fd2029f23 3106
mbed_official 324:406fd2029f23 3107 /*! @brief Read current value of the I2S_MCR_MOE field. */
mbed_official 324:406fd2029f23 3108 #define BR_I2S_MCR_MOE(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE))
mbed_official 324:406fd2029f23 3109
mbed_official 324:406fd2029f23 3110 /*! @brief Format value for bitfield I2S_MCR_MOE. */
mbed_official 324:406fd2029f23 3111 #define BF_I2S_MCR_MOE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MCR_MOE) & BM_I2S_MCR_MOE)
mbed_official 324:406fd2029f23 3112
mbed_official 324:406fd2029f23 3113 /*! @brief Set the MOE field to a new value. */
mbed_official 324:406fd2029f23 3114 #define BW_I2S_MCR_MOE(x, v) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_MOE) = (v))
mbed_official 324:406fd2029f23 3115 /*@}*/
mbed_official 324:406fd2029f23 3116
mbed_official 324:406fd2029f23 3117 /*!
mbed_official 324:406fd2029f23 3118 * @name Register I2S_MCR, field DUF[31] (RO)
mbed_official 324:406fd2029f23 3119 *
mbed_official 324:406fd2029f23 3120 * Provides the status of on-the-fly updates to the MCLK divider ratio.
mbed_official 324:406fd2029f23 3121 *
mbed_official 324:406fd2029f23 3122 * Values:
mbed_official 324:406fd2029f23 3123 * - 0 - MCLK divider ratio is not being updated currently.
mbed_official 324:406fd2029f23 3124 * - 1 - MCLK divider ratio is updating on-the-fly. Further updates to the MCLK
mbed_official 324:406fd2029f23 3125 * divider ratio are blocked while this flag remains set.
mbed_official 324:406fd2029f23 3126 */
mbed_official 324:406fd2029f23 3127 /*@{*/
mbed_official 324:406fd2029f23 3128 #define BP_I2S_MCR_DUF (31U) /*!< Bit position for I2S_MCR_DUF. */
mbed_official 324:406fd2029f23 3129 #define BM_I2S_MCR_DUF (0x80000000U) /*!< Bit mask for I2S_MCR_DUF. */
mbed_official 324:406fd2029f23 3130 #define BS_I2S_MCR_DUF (1U) /*!< Bit field size in bits for I2S_MCR_DUF. */
mbed_official 324:406fd2029f23 3131
mbed_official 324:406fd2029f23 3132 /*! @brief Read current value of the I2S_MCR_DUF field. */
mbed_official 324:406fd2029f23 3133 #define BR_I2S_MCR_DUF(x) (BITBAND_ACCESS32(HW_I2S_MCR_ADDR(x), BP_I2S_MCR_DUF))
mbed_official 324:406fd2029f23 3134 /*@}*/
mbed_official 324:406fd2029f23 3135
mbed_official 324:406fd2029f23 3136 /*******************************************************************************
mbed_official 324:406fd2029f23 3137 * HW_I2S_MDR - SAI MCLK Divide Register
mbed_official 324:406fd2029f23 3138 ******************************************************************************/
mbed_official 324:406fd2029f23 3139
mbed_official 324:406fd2029f23 3140 /*!
mbed_official 324:406fd2029f23 3141 * @brief HW_I2S_MDR - SAI MCLK Divide Register (RW)
mbed_official 324:406fd2029f23 3142 *
mbed_official 324:406fd2029f23 3143 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3144 *
mbed_official 324:406fd2029f23 3145 * The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
mbed_official 324:406fd2029f23 3146 * MDR can be changed when the MCLK divider clock is enabled, additional writes
mbed_official 324:406fd2029f23 3147 * to the MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK
mbed_official 324:406fd2029f23 3148 * divided clock is disabled do not set MCR[DUF].
mbed_official 324:406fd2029f23 3149 */
mbed_official 324:406fd2029f23 3150 typedef union _hw_i2s_mdr
mbed_official 324:406fd2029f23 3151 {
mbed_official 324:406fd2029f23 3152 uint32_t U;
mbed_official 324:406fd2029f23 3153 struct _hw_i2s_mdr_bitfields
mbed_official 324:406fd2029f23 3154 {
mbed_official 324:406fd2029f23 3155 uint32_t DIVIDE : 12; /*!< [11:0] MCLK Divide */
mbed_official 324:406fd2029f23 3156 uint32_t FRACT : 8; /*!< [19:12] MCLK Fraction */
mbed_official 324:406fd2029f23 3157 uint32_t RESERVED0 : 12; /*!< [31:20] */
mbed_official 324:406fd2029f23 3158 } B;
mbed_official 324:406fd2029f23 3159 } hw_i2s_mdr_t;
mbed_official 324:406fd2029f23 3160
mbed_official 324:406fd2029f23 3161 /*!
mbed_official 324:406fd2029f23 3162 * @name Constants and macros for entire I2S_MDR register
mbed_official 324:406fd2029f23 3163 */
mbed_official 324:406fd2029f23 3164 /*@{*/
mbed_official 324:406fd2029f23 3165 #define HW_I2S_MDR_ADDR(x) ((x) + 0x104U)
mbed_official 324:406fd2029f23 3166
mbed_official 324:406fd2029f23 3167 #define HW_I2S_MDR(x) (*(__IO hw_i2s_mdr_t *) HW_I2S_MDR_ADDR(x))
mbed_official 324:406fd2029f23 3168 #define HW_I2S_MDR_RD(x) (HW_I2S_MDR(x).U)
mbed_official 324:406fd2029f23 3169 #define HW_I2S_MDR_WR(x, v) (HW_I2S_MDR(x).U = (v))
mbed_official 324:406fd2029f23 3170 #define HW_I2S_MDR_SET(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) | (v)))
mbed_official 324:406fd2029f23 3171 #define HW_I2S_MDR_CLR(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3172 #define HW_I2S_MDR_TOG(x, v) (HW_I2S_MDR_WR(x, HW_I2S_MDR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3173 /*@}*/
mbed_official 324:406fd2029f23 3174
mbed_official 324:406fd2029f23 3175 /*
mbed_official 324:406fd2029f23 3176 * Constants & macros for individual I2S_MDR bitfields
mbed_official 324:406fd2029f23 3177 */
mbed_official 324:406fd2029f23 3178
mbed_official 324:406fd2029f23 3179 /*!
mbed_official 324:406fd2029f23 3180 * @name Register I2S_MDR, field DIVIDE[11:0] (RW)
mbed_official 324:406fd2029f23 3181 *
mbed_official 324:406fd2029f23 3182 * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
mbed_official 324:406fd2029f23 3183 * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
mbed_official 324:406fd2029f23 3184 * DIVIDE field.
mbed_official 324:406fd2029f23 3185 */
mbed_official 324:406fd2029f23 3186 /*@{*/
mbed_official 324:406fd2029f23 3187 #define BP_I2S_MDR_DIVIDE (0U) /*!< Bit position for I2S_MDR_DIVIDE. */
mbed_official 324:406fd2029f23 3188 #define BM_I2S_MDR_DIVIDE (0x00000FFFU) /*!< Bit mask for I2S_MDR_DIVIDE. */
mbed_official 324:406fd2029f23 3189 #define BS_I2S_MDR_DIVIDE (12U) /*!< Bit field size in bits for I2S_MDR_DIVIDE. */
mbed_official 324:406fd2029f23 3190
mbed_official 324:406fd2029f23 3191 /*! @brief Read current value of the I2S_MDR_DIVIDE field. */
mbed_official 324:406fd2029f23 3192 #define BR_I2S_MDR_DIVIDE(x) (HW_I2S_MDR(x).B.DIVIDE)
mbed_official 324:406fd2029f23 3193
mbed_official 324:406fd2029f23 3194 /*! @brief Format value for bitfield I2S_MDR_DIVIDE. */
mbed_official 324:406fd2029f23 3195 #define BF_I2S_MDR_DIVIDE(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_DIVIDE) & BM_I2S_MDR_DIVIDE)
mbed_official 324:406fd2029f23 3196
mbed_official 324:406fd2029f23 3197 /*! @brief Set the DIVIDE field to a new value. */
mbed_official 324:406fd2029f23 3198 #define BW_I2S_MDR_DIVIDE(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_DIVIDE) | BF_I2S_MDR_DIVIDE(v)))
mbed_official 324:406fd2029f23 3199 /*@}*/
mbed_official 324:406fd2029f23 3200
mbed_official 324:406fd2029f23 3201 /*!
mbed_official 324:406fd2029f23 3202 * @name Register I2S_MDR, field FRACT[19:12] (RW)
mbed_official 324:406fd2029f23 3203 *
mbed_official 324:406fd2029f23 3204 * Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT +
mbed_official 324:406fd2029f23 3205 * 1) / (DIVIDE + 1) ). FRACT must be set equal or less than the value in the
mbed_official 324:406fd2029f23 3206 * DIVIDE field.
mbed_official 324:406fd2029f23 3207 */
mbed_official 324:406fd2029f23 3208 /*@{*/
mbed_official 324:406fd2029f23 3209 #define BP_I2S_MDR_FRACT (12U) /*!< Bit position for I2S_MDR_FRACT. */
mbed_official 324:406fd2029f23 3210 #define BM_I2S_MDR_FRACT (0x000FF000U) /*!< Bit mask for I2S_MDR_FRACT. */
mbed_official 324:406fd2029f23 3211 #define BS_I2S_MDR_FRACT (8U) /*!< Bit field size in bits for I2S_MDR_FRACT. */
mbed_official 324:406fd2029f23 3212
mbed_official 324:406fd2029f23 3213 /*! @brief Read current value of the I2S_MDR_FRACT field. */
mbed_official 324:406fd2029f23 3214 #define BR_I2S_MDR_FRACT(x) (HW_I2S_MDR(x).B.FRACT)
mbed_official 324:406fd2029f23 3215
mbed_official 324:406fd2029f23 3216 /*! @brief Format value for bitfield I2S_MDR_FRACT. */
mbed_official 324:406fd2029f23 3217 #define BF_I2S_MDR_FRACT(v) ((uint32_t)((uint32_t)(v) << BP_I2S_MDR_FRACT) & BM_I2S_MDR_FRACT)
mbed_official 324:406fd2029f23 3218
mbed_official 324:406fd2029f23 3219 /*! @brief Set the FRACT field to a new value. */
mbed_official 324:406fd2029f23 3220 #define BW_I2S_MDR_FRACT(x, v) (HW_I2S_MDR_WR(x, (HW_I2S_MDR_RD(x) & ~BM_I2S_MDR_FRACT) | BF_I2S_MDR_FRACT(v)))
mbed_official 324:406fd2029f23 3221 /*@}*/
mbed_official 324:406fd2029f23 3222
mbed_official 324:406fd2029f23 3223 /*******************************************************************************
mbed_official 324:406fd2029f23 3224 * hw_i2s_t - module struct
mbed_official 324:406fd2029f23 3225 ******************************************************************************/
mbed_official 324:406fd2029f23 3226 /*!
mbed_official 324:406fd2029f23 3227 * @brief All I2S module registers.
mbed_official 324:406fd2029f23 3228 */
mbed_official 324:406fd2029f23 3229 #pragma pack(1)
mbed_official 324:406fd2029f23 3230 typedef struct _hw_i2s
mbed_official 324:406fd2029f23 3231 {
mbed_official 324:406fd2029f23 3232 __IO hw_i2s_tcsr_t TCSR; /*!< [0x0] SAI Transmit Control Register */
mbed_official 324:406fd2029f23 3233 __IO hw_i2s_tcr1_t TCR1; /*!< [0x4] SAI Transmit Configuration 1 Register */
mbed_official 324:406fd2029f23 3234 __IO hw_i2s_tcr2_t TCR2; /*!< [0x8] SAI Transmit Configuration 2 Register */
mbed_official 324:406fd2029f23 3235 __IO hw_i2s_tcr3_t TCR3; /*!< [0xC] SAI Transmit Configuration 3 Register */
mbed_official 324:406fd2029f23 3236 __IO hw_i2s_tcr4_t TCR4; /*!< [0x10] SAI Transmit Configuration 4 Register */
mbed_official 324:406fd2029f23 3237 __IO hw_i2s_tcr5_t TCR5; /*!< [0x14] SAI Transmit Configuration 5 Register */
mbed_official 324:406fd2029f23 3238 uint8_t _reserved0[8];
mbed_official 324:406fd2029f23 3239 __O hw_i2s_tdrn_t TDRn[1]; /*!< [0x20] SAI Transmit Data Register */
mbed_official 324:406fd2029f23 3240 uint8_t _reserved1[28];
mbed_official 324:406fd2029f23 3241 __I hw_i2s_tfrn_t TFRn[1]; /*!< [0x40] SAI Transmit FIFO Register */
mbed_official 324:406fd2029f23 3242 uint8_t _reserved2[28];
mbed_official 324:406fd2029f23 3243 __IO hw_i2s_tmr_t TMR; /*!< [0x60] SAI Transmit Mask Register */
mbed_official 324:406fd2029f23 3244 uint8_t _reserved3[28];
mbed_official 324:406fd2029f23 3245 __IO hw_i2s_rcsr_t RCSR; /*!< [0x80] SAI Receive Control Register */
mbed_official 324:406fd2029f23 3246 __IO hw_i2s_rcr1_t RCR1; /*!< [0x84] SAI Receive Configuration 1 Register */
mbed_official 324:406fd2029f23 3247 __IO hw_i2s_rcr2_t RCR2; /*!< [0x88] SAI Receive Configuration 2 Register */
mbed_official 324:406fd2029f23 3248 __IO hw_i2s_rcr3_t RCR3; /*!< [0x8C] SAI Receive Configuration 3 Register */
mbed_official 324:406fd2029f23 3249 __IO hw_i2s_rcr4_t RCR4; /*!< [0x90] SAI Receive Configuration 4 Register */
mbed_official 324:406fd2029f23 3250 __IO hw_i2s_rcr5_t RCR5; /*!< [0x94] SAI Receive Configuration 5 Register */
mbed_official 324:406fd2029f23 3251 uint8_t _reserved4[8];
mbed_official 324:406fd2029f23 3252 __I hw_i2s_rdrn_t RDRn[1]; /*!< [0xA0] SAI Receive Data Register */
mbed_official 324:406fd2029f23 3253 uint8_t _reserved5[28];
mbed_official 324:406fd2029f23 3254 __I hw_i2s_rfrn_t RFRn[1]; /*!< [0xC0] SAI Receive FIFO Register */
mbed_official 324:406fd2029f23 3255 uint8_t _reserved6[28];
mbed_official 324:406fd2029f23 3256 __IO hw_i2s_rmr_t RMR; /*!< [0xE0] SAI Receive Mask Register */
mbed_official 324:406fd2029f23 3257 uint8_t _reserved7[28];
mbed_official 324:406fd2029f23 3258 __IO hw_i2s_mcr_t MCR; /*!< [0x100] SAI MCLK Control Register */
mbed_official 324:406fd2029f23 3259 __IO hw_i2s_mdr_t MDR; /*!< [0x104] SAI MCLK Divide Register */
mbed_official 324:406fd2029f23 3260 } hw_i2s_t;
mbed_official 324:406fd2029f23 3261 #pragma pack()
mbed_official 324:406fd2029f23 3262
mbed_official 324:406fd2029f23 3263 /*! @brief Macro to access all I2S registers. */
mbed_official 324:406fd2029f23 3264 /*! @param x I2S module instance base address. */
mbed_official 324:406fd2029f23 3265 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 3266 * use the '&' operator, like <code>&HW_I2S(I2S0_BASE)</code>. */
mbed_official 324:406fd2029f23 3267 #define HW_I2S(x) (*(hw_i2s_t *)(x))
mbed_official 324:406fd2029f23 3268
mbed_official 324:406fd2029f23 3269 #endif /* __HW_I2S_REGISTERS_H__ */
mbed_official 324:406fd2029f23 3270 /* EOF */