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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftm.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:: mbed_official
Date:: Thu Sep 18 14:00:17 2014 +0100
Revision:: 324:406fd2029f23

Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5

Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/

Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	324:406fd2029f23	1	/*
mbed_official	324:406fd2029f23	2	** ###################################################################
mbed_official	324:406fd2029f23	3	** Compilers: Keil ARM C/C++ Compiler
mbed_official	324:406fd2029f23	4	** Freescale C/C++ for Embedded ARM
mbed_official	324:406fd2029f23	5	** GNU C Compiler
mbed_official	324:406fd2029f23	6	** IAR ANSI C/C++ Compiler for ARM
mbed_official	324:406fd2029f23	7	**
mbed_official	324:406fd2029f23	8	** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official	324:406fd2029f23	9	** Version: rev. 2.5, 2014-05-06
mbed_official	324:406fd2029f23	10	** Build: b140604
mbed_official	324:406fd2029f23	11	**
mbed_official	324:406fd2029f23	12	** Abstract:
mbed_official	324:406fd2029f23	13	** Extension to the CMSIS register access layer header.
mbed_official	324:406fd2029f23	14	**
mbed_official	324:406fd2029f23	15	** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official	324:406fd2029f23	16	** All rights reserved.
mbed_official	324:406fd2029f23	17	**
mbed_official	324:406fd2029f23	18	** Redistribution and use in source and binary forms, with or without modification,
mbed_official	324:406fd2029f23	19	** are permitted provided that the following conditions are met:
mbed_official	324:406fd2029f23	20	**
mbed_official	324:406fd2029f23	21	** o Redistributions of source code must retain the above copyright notice, this list
mbed_official	324:406fd2029f23	22	** of conditions and the following disclaimer.
mbed_official	324:406fd2029f23	23	**
mbed_official	324:406fd2029f23	24	** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official	324:406fd2029f23	25	** list of conditions and the following disclaimer in the documentation and/or
mbed_official	324:406fd2029f23	26	** other materials provided with the distribution.
mbed_official	324:406fd2029f23	27	**
mbed_official	324:406fd2029f23	28	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official	324:406fd2029f23	29	** contributors may be used to endorse or promote products derived from this
mbed_official	324:406fd2029f23	30	** software without specific prior written permission.
mbed_official	324:406fd2029f23	31	**
mbed_official	324:406fd2029f23	32	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official	324:406fd2029f23	33	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official	324:406fd2029f23	34	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	324:406fd2029f23	35	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official	324:406fd2029f23	36	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official	324:406fd2029f23	37	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official	324:406fd2029f23	38	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official	324:406fd2029f23	39	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official	324:406fd2029f23	40	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official	324:406fd2029f23	41	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	324:406fd2029f23	42	**
mbed_official	324:406fd2029f23	43	** http: www.freescale.com
mbed_official	324:406fd2029f23	44	** mail: support@freescale.com
mbed_official	324:406fd2029f23	45	**
mbed_official	324:406fd2029f23	46	** Revisions:
mbed_official	324:406fd2029f23	47	** - rev. 1.0 (2013-07-23)
mbed_official	324:406fd2029f23	48	** Initial version.
mbed_official	324:406fd2029f23	49	** - rev. 1.1 (2013-09-17)
mbed_official	324:406fd2029f23	50	** RM rev. 0.4 update.
mbed_official	324:406fd2029f23	51	** - rev. 2.0 (2013-10-29)
mbed_official	324:406fd2029f23	52	** Register accessor macros added to the memory map.
mbed_official	324:406fd2029f23	53	** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official	324:406fd2029f23	54	** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official	324:406fd2029f23	55	** System initialization updated.
mbed_official	324:406fd2029f23	56	** - rev. 2.1 (2013-10-30)
mbed_official	324:406fd2029f23	57	** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official	324:406fd2029f23	58	** - rev. 2.2 (2013-12-20)
mbed_official	324:406fd2029f23	59	** Update according to reference manual rev. 0.6,
mbed_official	324:406fd2029f23	60	** - rev. 2.3 (2014-01-13)
mbed_official	324:406fd2029f23	61	** Update according to reference manual rev. 0.61,
mbed_official	324:406fd2029f23	62	** - rev. 2.4 (2014-02-10)
mbed_official	324:406fd2029f23	63	** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official	324:406fd2029f23	64	** - rev. 2.5 (2014-05-06)
mbed_official	324:406fd2029f23	65	** Update according to reference manual rev. 1.0,
mbed_official	324:406fd2029f23	66	** Update of system and startup files.
mbed_official	324:406fd2029f23	67	** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official	324:406fd2029f23	68	**
mbed_official	324:406fd2029f23	69	** ###################################################################
mbed_official	324:406fd2029f23	70	*/
mbed_official	324:406fd2029f23	71
mbed_official	324:406fd2029f23	72	/*
mbed_official	324:406fd2029f23	73	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official	324:406fd2029f23	74	*
mbed_official	324:406fd2029f23	75	* This file was generated automatically and any changes may be lost.
mbed_official	324:406fd2029f23	76	*/
mbed_official	324:406fd2029f23	77	#ifndef __HW_FTM_REGISTERS_H__
mbed_official	324:406fd2029f23	78	#define __HW_FTM_REGISTERS_H__
mbed_official	324:406fd2029f23	79
mbed_official	324:406fd2029f23	80	#include "MK22F51212.h"
mbed_official	324:406fd2029f23	81	#include "fsl_bitaccess.h"
mbed_official	324:406fd2029f23	82
mbed_official	324:406fd2029f23	83	/*
mbed_official	324:406fd2029f23	84	* MK22F51212 FTM
mbed_official	324:406fd2029f23	85	*
mbed_official	324:406fd2029f23	86	* FlexTimer Module
mbed_official	324:406fd2029f23	87	*
mbed_official	324:406fd2029f23	88	* Registers defined in this header file:
mbed_official	324:406fd2029f23	89	* - HW_FTM_SC - Status And Control
mbed_official	324:406fd2029f23	90	* - HW_FTM_CNT - Counter
mbed_official	324:406fd2029f23	91	* - HW_FTM_MOD - Modulo
mbed_official	324:406fd2029f23	92	* - HW_FTM_CnSC - Channel (n) Status And Control
mbed_official	324:406fd2029f23	93	* - HW_FTM_CnV - Channel (n) Value
mbed_official	324:406fd2029f23	94	* - HW_FTM_CNTIN - Counter Initial Value
mbed_official	324:406fd2029f23	95	* - HW_FTM_STATUS - Capture And Compare Status
mbed_official	324:406fd2029f23	96	* - HW_FTM_MODE - Features Mode Selection
mbed_official	324:406fd2029f23	97	* - HW_FTM_SYNC - Synchronization
mbed_official	324:406fd2029f23	98	* - HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official	324:406fd2029f23	99	* - HW_FTM_OUTMASK - Output Mask
mbed_official	324:406fd2029f23	100	* - HW_FTM_COMBINE - Function For Linked Channels
mbed_official	324:406fd2029f23	101	* - HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official	324:406fd2029f23	102	* - HW_FTM_EXTTRIG - FTM External Trigger
mbed_official	324:406fd2029f23	103	* - HW_FTM_POL - Channels Polarity
mbed_official	324:406fd2029f23	104	* - HW_FTM_FMS - Fault Mode Status
mbed_official	324:406fd2029f23	105	* - HW_FTM_FILTER - Input Capture Filter Control
mbed_official	324:406fd2029f23	106	* - HW_FTM_FLTCTRL - Fault Control
mbed_official	324:406fd2029f23	107	* - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official	324:406fd2029f23	108	* - HW_FTM_CONF - Configuration
mbed_official	324:406fd2029f23	109	* - HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official	324:406fd2029f23	110	* - HW_FTM_SYNCONF - Synchronization Configuration
mbed_official	324:406fd2029f23	111	* - HW_FTM_INVCTRL - FTM Inverting Control
mbed_official	324:406fd2029f23	112	* - HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official	324:406fd2029f23	113	* - HW_FTM_PWMLOAD - FTM PWM Load
mbed_official	324:406fd2029f23	114	*
mbed_official	324:406fd2029f23	115	* - hw_ftm_t - Struct containing all module registers.
mbed_official	324:406fd2029f23	116	*/
mbed_official	324:406fd2029f23	117
mbed_official	324:406fd2029f23	118	#define HW_FTM_INSTANCE_COUNT (4U) /!< Number of instances of the FTM module. /
mbed_official	324:406fd2029f23	119	#define HW_FTM0 (0U) /!< Instance number for FTM0. /
mbed_official	324:406fd2029f23	120	#define HW_FTM1 (1U) /!< Instance number for FTM1. /
mbed_official	324:406fd2029f23	121	#define HW_FTM2 (2U) /!< Instance number for FTM2. /
mbed_official	324:406fd2029f23	122	#define HW_FTM3 (3U) /!< Instance number for FTM3. /
mbed_official	324:406fd2029f23	123
mbed_official	324:406fd2029f23	124	/*******************************************************************************
mbed_official	324:406fd2029f23	125	* HW_FTM_SC - Status And Control
mbed_official	324:406fd2029f23	126	******************************************************************************/
mbed_official	324:406fd2029f23	127
mbed_official	324:406fd2029f23	128	/*!
mbed_official	324:406fd2029f23	129	* @brief HW_FTM_SC - Status And Control (RW)
mbed_official	324:406fd2029f23	130	*
mbed_official	324:406fd2029f23	131	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	132	*
mbed_official	324:406fd2029f23	133	* SC contains the overflow status flag and control bits used to configure the
mbed_official	324:406fd2029f23	134	* interrupt enable, FTM configuration, clock source, and prescaler factor. These
mbed_official	324:406fd2029f23	135	* controls relate to all channels within this module.
mbed_official	324:406fd2029f23	136	*/
mbed_official	324:406fd2029f23	137	typedef union _hw_ftm_sc
mbed_official	324:406fd2029f23	138	{
mbed_official	324:406fd2029f23	139	uint32_t U;
mbed_official	324:406fd2029f23	140	struct _hw_ftm_sc_bitfields
mbed_official	324:406fd2029f23	141	{
mbed_official	324:406fd2029f23	142	uint32_t PS : 3; /!< [2:0] Prescale Factor Selection /
mbed_official	324:406fd2029f23	143	uint32_t CLKS : 2; /!< [4:3] Clock Source Selection /
mbed_official	324:406fd2029f23	144	uint32_t CPWMS : 1; /!< [5] Center-Aligned PWM Select /
mbed_official	324:406fd2029f23	145	uint32_t TOIE : 1; /!< [6] Timer Overflow Interrupt Enable /
mbed_official	324:406fd2029f23	146	uint32_t TOF : 1; /!< [7] Timer Overflow Flag /
mbed_official	324:406fd2029f23	147	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	148	} B;
mbed_official	324:406fd2029f23	149	} hw_ftm_sc_t;
mbed_official	324:406fd2029f23	150
mbed_official	324:406fd2029f23	151	/*!
mbed_official	324:406fd2029f23	152	* @name Constants and macros for entire FTM_SC register
mbed_official	324:406fd2029f23	153	*/
mbed_official	324:406fd2029f23	154	/@{/
mbed_official	324:406fd2029f23	155	#define HW_FTM_SC_ADDR(x) ((x) + 0x0U)
mbed_official	324:406fd2029f23	156
mbed_official	324:406fd2029f23	157	#define HW_FTM_SC(x) ((__IO hw_ftm_sc_t ) HW_FTM_SC_ADDR(x))
mbed_official	324:406fd2029f23	158	#define HW_FTM_SC_RD(x) (HW_FTM_SC(x).U)
mbed_official	324:406fd2029f23	159	#define HW_FTM_SC_WR(x, v) (HW_FTM_SC(x).U = (v))
mbed_official	324:406fd2029f23	160	#define HW_FTM_SC_SET(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) \| (v)))
mbed_official	324:406fd2029f23	161	#define HW_FTM_SC_CLR(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	162	#define HW_FTM_SC_TOG(x, v) (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	163	/@}/
mbed_official	324:406fd2029f23	164
mbed_official	324:406fd2029f23	165	/*
mbed_official	324:406fd2029f23	166	* Constants & macros for individual FTM_SC bitfields
mbed_official	324:406fd2029f23	167	*/
mbed_official	324:406fd2029f23	168
mbed_official	324:406fd2029f23	169	/*!
mbed_official	324:406fd2029f23	170	* @name Register FTM_SC, field PS[2:0] (RW)
mbed_official	324:406fd2029f23	171	*
mbed_official	324:406fd2029f23	172	* Selects one of 8 division factors for the clock source selected by CLKS. The
mbed_official	324:406fd2029f23	173	* new prescaler factor affects the clock source on the next system clock cycle
mbed_official	324:406fd2029f23	174	* after the new value is updated into the register bits. This field is write
mbed_official	324:406fd2029f23	175	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	176	*
mbed_official	324:406fd2029f23	177	* Values:
mbed_official	324:406fd2029f23	178	* - 000 - Divide by 1
mbed_official	324:406fd2029f23	179	* - 001 - Divide by 2
mbed_official	324:406fd2029f23	180	* - 010 - Divide by 4
mbed_official	324:406fd2029f23	181	* - 011 - Divide by 8
mbed_official	324:406fd2029f23	182	* - 100 - Divide by 16
mbed_official	324:406fd2029f23	183	* - 101 - Divide by 32
mbed_official	324:406fd2029f23	184	* - 110 - Divide by 64
mbed_official	324:406fd2029f23	185	* - 111 - Divide by 128
mbed_official	324:406fd2029f23	186	*/
mbed_official	324:406fd2029f23	187	/@{/
mbed_official	324:406fd2029f23	188	#define BP_FTM_SC_PS (0U) /!< Bit position for FTM_SC_PS. /
mbed_official	324:406fd2029f23	189	#define BM_FTM_SC_PS (0x00000007U) /!< Bit mask for FTM_SC_PS. /
mbed_official	324:406fd2029f23	190	#define BS_FTM_SC_PS (3U) /!< Bit field size in bits for FTM_SC_PS. /
mbed_official	324:406fd2029f23	191
mbed_official	324:406fd2029f23	192	/! @brief Read current value of the FTM_SC_PS field. /
mbed_official	324:406fd2029f23	193	#define BR_FTM_SC_PS(x) (HW_FTM_SC(x).B.PS)
mbed_official	324:406fd2029f23	194
mbed_official	324:406fd2029f23	195	/! @brief Format value for bitfield FTM_SC_PS. /
mbed_official	324:406fd2029f23	196	#define BF_FTM_SC_PS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
mbed_official	324:406fd2029f23	197
mbed_official	324:406fd2029f23	198	/! @brief Set the PS field to a new value. /
mbed_official	324:406fd2029f23	199	#define BW_FTM_SC_PS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) \| BF_FTM_SC_PS(v)))
mbed_official	324:406fd2029f23	200	/@}/
mbed_official	324:406fd2029f23	201
mbed_official	324:406fd2029f23	202	/*!
mbed_official	324:406fd2029f23	203	* @name Register FTM_SC, field CLKS[4:3] (RW)
mbed_official	324:406fd2029f23	204	*
mbed_official	324:406fd2029f23	205	* Selects one of the three FTM counter clock sources. This field is write
mbed_official	324:406fd2029f23	206	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	207	*
mbed_official	324:406fd2029f23	208	* Values:
mbed_official	324:406fd2029f23	209	* - 00 - No clock selected. This in effect disables the FTM counter.
mbed_official	324:406fd2029f23	210	* - 01 - System clock
mbed_official	324:406fd2029f23	211	* - 10 - Fixed frequency clock
mbed_official	324:406fd2029f23	212	* - 11 - External clock
mbed_official	324:406fd2029f23	213	*/
mbed_official	324:406fd2029f23	214	/@{/
mbed_official	324:406fd2029f23	215	#define BP_FTM_SC_CLKS (3U) /!< Bit position for FTM_SC_CLKS. /
mbed_official	324:406fd2029f23	216	#define BM_FTM_SC_CLKS (0x00000018U) /!< Bit mask for FTM_SC_CLKS. /
mbed_official	324:406fd2029f23	217	#define BS_FTM_SC_CLKS (2U) /!< Bit field size in bits for FTM_SC_CLKS. /
mbed_official	324:406fd2029f23	218
mbed_official	324:406fd2029f23	219	/! @brief Read current value of the FTM_SC_CLKS field. /
mbed_official	324:406fd2029f23	220	#define BR_FTM_SC_CLKS(x) (HW_FTM_SC(x).B.CLKS)
mbed_official	324:406fd2029f23	221
mbed_official	324:406fd2029f23	222	/! @brief Format value for bitfield FTM_SC_CLKS. /
mbed_official	324:406fd2029f23	223	#define BF_FTM_SC_CLKS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
mbed_official	324:406fd2029f23	224
mbed_official	324:406fd2029f23	225	/! @brief Set the CLKS field to a new value. /
mbed_official	324:406fd2029f23	226	#define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) \| BF_FTM_SC_CLKS(v)))
mbed_official	324:406fd2029f23	227	/@}/
mbed_official	324:406fd2029f23	228
mbed_official	324:406fd2029f23	229	/*!
mbed_official	324:406fd2029f23	230	* @name Register FTM_SC, field CPWMS[5] (RW)
mbed_official	324:406fd2029f23	231	*
mbed_official	324:406fd2029f23	232	* Selects CPWM mode. This mode configures the FTM to operate in Up-Down
mbed_official	324:406fd2029f23	233	* Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	324:406fd2029f23	234	* = 1.
mbed_official	324:406fd2029f23	235	*
mbed_official	324:406fd2029f23	236	* Values:
mbed_official	324:406fd2029f23	237	* - 0 - FTM counter operates in Up Counting mode.
mbed_official	324:406fd2029f23	238	* - 1 - FTM counter operates in Up-Down Counting mode.
mbed_official	324:406fd2029f23	239	*/
mbed_official	324:406fd2029f23	240	/@{/
mbed_official	324:406fd2029f23	241	#define BP_FTM_SC_CPWMS (5U) /!< Bit position for FTM_SC_CPWMS. /
mbed_official	324:406fd2029f23	242	#define BM_FTM_SC_CPWMS (0x00000020U) /!< Bit mask for FTM_SC_CPWMS. /
mbed_official	324:406fd2029f23	243	#define BS_FTM_SC_CPWMS (1U) /!< Bit field size in bits for FTM_SC_CPWMS. /
mbed_official	324:406fd2029f23	244
mbed_official	324:406fd2029f23	245	/! @brief Read current value of the FTM_SC_CPWMS field. /
mbed_official	324:406fd2029f23	246	#define BR_FTM_SC_CPWMS(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS))
mbed_official	324:406fd2029f23	247
mbed_official	324:406fd2029f23	248	/! @brief Format value for bitfield FTM_SC_CPWMS. /
mbed_official	324:406fd2029f23	249	#define BF_FTM_SC_CPWMS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
mbed_official	324:406fd2029f23	250
mbed_official	324:406fd2029f23	251	/! @brief Set the CPWMS field to a new value. /
mbed_official	324:406fd2029f23	252	#define BW_FTM_SC_CPWMS(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS) = (v))
mbed_official	324:406fd2029f23	253	/@}/
mbed_official	324:406fd2029f23	254
mbed_official	324:406fd2029f23	255	/*!
mbed_official	324:406fd2029f23	256	* @name Register FTM_SC, field TOIE[6] (RW)
mbed_official	324:406fd2029f23	257	*
mbed_official	324:406fd2029f23	258	* Enables FTM overflow interrupts.
mbed_official	324:406fd2029f23	259	*
mbed_official	324:406fd2029f23	260	* Values:
mbed_official	324:406fd2029f23	261	* - 0 - Disable TOF interrupts. Use software polling.
mbed_official	324:406fd2029f23	262	* - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
mbed_official	324:406fd2029f23	263	*/
mbed_official	324:406fd2029f23	264	/@{/
mbed_official	324:406fd2029f23	265	#define BP_FTM_SC_TOIE (6U) /!< Bit position for FTM_SC_TOIE. /
mbed_official	324:406fd2029f23	266	#define BM_FTM_SC_TOIE (0x00000040U) /!< Bit mask for FTM_SC_TOIE. /
mbed_official	324:406fd2029f23	267	#define BS_FTM_SC_TOIE (1U) /!< Bit field size in bits for FTM_SC_TOIE. /
mbed_official	324:406fd2029f23	268
mbed_official	324:406fd2029f23	269	/! @brief Read current value of the FTM_SC_TOIE field. /
mbed_official	324:406fd2029f23	270	#define BR_FTM_SC_TOIE(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE))
mbed_official	324:406fd2029f23	271
mbed_official	324:406fd2029f23	272	/! @brief Format value for bitfield FTM_SC_TOIE. /
mbed_official	324:406fd2029f23	273	#define BF_FTM_SC_TOIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
mbed_official	324:406fd2029f23	274
mbed_official	324:406fd2029f23	275	/! @brief Set the TOIE field to a new value. /
mbed_official	324:406fd2029f23	276	#define BW_FTM_SC_TOIE(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE) = (v))
mbed_official	324:406fd2029f23	277	/@}/
mbed_official	324:406fd2029f23	278
mbed_official	324:406fd2029f23	279	/*!
mbed_official	324:406fd2029f23	280	* @name Register FTM_SC, field TOF[7] (ROWZ)
mbed_official	324:406fd2029f23	281	*
mbed_official	324:406fd2029f23	282	* Set by hardware when the FTM counter passes the value in the MOD register.
mbed_official	324:406fd2029f23	283	* The TOF bit is cleared by reading the SC register while TOF is set and then
mbed_official	324:406fd2029f23	284	* writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
mbed_official	324:406fd2029f23	285	* occurs between the read and write operations, the write operation has no
mbed_official	324:406fd2029f23	286	* effect; therefore, TOF remains set indicating an overflow has occurred. In this
mbed_official	324:406fd2029f23	287	* case, a TOF interrupt request is not lost due to the clearing sequence for a
mbed_official	324:406fd2029f23	288	* previous TOF.
mbed_official	324:406fd2029f23	289	*
mbed_official	324:406fd2029f23	290	* Values:
mbed_official	324:406fd2029f23	291	* - 0 - FTM counter has not overflowed.
mbed_official	324:406fd2029f23	292	* - 1 - FTM counter has overflowed.
mbed_official	324:406fd2029f23	293	*/
mbed_official	324:406fd2029f23	294	/@{/
mbed_official	324:406fd2029f23	295	#define BP_FTM_SC_TOF (7U) /!< Bit position for FTM_SC_TOF. /
mbed_official	324:406fd2029f23	296	#define BM_FTM_SC_TOF (0x00000080U) /!< Bit mask for FTM_SC_TOF. /
mbed_official	324:406fd2029f23	297	#define BS_FTM_SC_TOF (1U) /!< Bit field size in bits for FTM_SC_TOF. /
mbed_official	324:406fd2029f23	298
mbed_official	324:406fd2029f23	299	/! @brief Read current value of the FTM_SC_TOF field. /
mbed_official	324:406fd2029f23	300	#define BR_FTM_SC_TOF(x) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF))
mbed_official	324:406fd2029f23	301
mbed_official	324:406fd2029f23	302	/! @brief Format value for bitfield FTM_SC_TOF. /
mbed_official	324:406fd2029f23	303	#define BF_FTM_SC_TOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
mbed_official	324:406fd2029f23	304
mbed_official	324:406fd2029f23	305	/! @brief Set the TOF field to a new value. /
mbed_official	324:406fd2029f23	306	#define BW_FTM_SC_TOF(x, v) (BITBAND_ACCESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF) = (v))
mbed_official	324:406fd2029f23	307	/@}/
mbed_official	324:406fd2029f23	308
mbed_official	324:406fd2029f23	309	/*******************************************************************************
mbed_official	324:406fd2029f23	310	* HW_FTM_CNT - Counter
mbed_official	324:406fd2029f23	311	******************************************************************************/
mbed_official	324:406fd2029f23	312
mbed_official	324:406fd2029f23	313	/*!
mbed_official	324:406fd2029f23	314	* @brief HW_FTM_CNT - Counter (RW)
mbed_official	324:406fd2029f23	315	*
mbed_official	324:406fd2029f23	316	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	317	*
mbed_official	324:406fd2029f23	318	* The CNT register contains the FTM counter value. Reset clears the CNT
mbed_official	324:406fd2029f23	319	* register. Writing any value to COUNT updates the counter with its initial value,
mbed_official	324:406fd2029f23	320	* CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
mbed_official	324:406fd2029f23	321	* may read.
mbed_official	324:406fd2029f23	322	*/
mbed_official	324:406fd2029f23	323	typedef union _hw_ftm_cnt
mbed_official	324:406fd2029f23	324	{
mbed_official	324:406fd2029f23	325	uint32_t U;
mbed_official	324:406fd2029f23	326	struct _hw_ftm_cnt_bitfields
mbed_official	324:406fd2029f23	327	{
mbed_official	324:406fd2029f23	328	uint32_t COUNT : 16; /!< [15:0] Counter Value /
mbed_official	324:406fd2029f23	329	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	330	} B;
mbed_official	324:406fd2029f23	331	} hw_ftm_cnt_t;
mbed_official	324:406fd2029f23	332
mbed_official	324:406fd2029f23	333	/*!
mbed_official	324:406fd2029f23	334	* @name Constants and macros for entire FTM_CNT register
mbed_official	324:406fd2029f23	335	*/
mbed_official	324:406fd2029f23	336	/@{/
mbed_official	324:406fd2029f23	337	#define HW_FTM_CNT_ADDR(x) ((x) + 0x4U)
mbed_official	324:406fd2029f23	338
mbed_official	324:406fd2029f23	339	#define HW_FTM_CNT(x) ((__IO hw_ftm_cnt_t ) HW_FTM_CNT_ADDR(x))
mbed_official	324:406fd2029f23	340	#define HW_FTM_CNT_RD(x) (HW_FTM_CNT(x).U)
mbed_official	324:406fd2029f23	341	#define HW_FTM_CNT_WR(x, v) (HW_FTM_CNT(x).U = (v))
mbed_official	324:406fd2029f23	342	#define HW_FTM_CNT_SET(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	343	#define HW_FTM_CNT_CLR(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	344	#define HW_FTM_CNT_TOG(x, v) (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	345	/@}/
mbed_official	324:406fd2029f23	346
mbed_official	324:406fd2029f23	347	/*
mbed_official	324:406fd2029f23	348	* Constants & macros for individual FTM_CNT bitfields
mbed_official	324:406fd2029f23	349	*/
mbed_official	324:406fd2029f23	350
mbed_official	324:406fd2029f23	351	/*!
mbed_official	324:406fd2029f23	352	* @name Register FTM_CNT, field COUNT[15:0] (RW)
mbed_official	324:406fd2029f23	353	*/
mbed_official	324:406fd2029f23	354	/@{/
mbed_official	324:406fd2029f23	355	#define BP_FTM_CNT_COUNT (0U) /!< Bit position for FTM_CNT_COUNT. /
mbed_official	324:406fd2029f23	356	#define BM_FTM_CNT_COUNT (0x0000FFFFU) /!< Bit mask for FTM_CNT_COUNT. /
mbed_official	324:406fd2029f23	357	#define BS_FTM_CNT_COUNT (16U) /!< Bit field size in bits for FTM_CNT_COUNT. /
mbed_official	324:406fd2029f23	358
mbed_official	324:406fd2029f23	359	/! @brief Read current value of the FTM_CNT_COUNT field. /
mbed_official	324:406fd2029f23	360	#define BR_FTM_CNT_COUNT(x) (HW_FTM_CNT(x).B.COUNT)
mbed_official	324:406fd2029f23	361
mbed_official	324:406fd2029f23	362	/! @brief Format value for bitfield FTM_CNT_COUNT. /
mbed_official	324:406fd2029f23	363	#define BF_FTM_CNT_COUNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
mbed_official	324:406fd2029f23	364
mbed_official	324:406fd2029f23	365	/! @brief Set the COUNT field to a new value. /
mbed_official	324:406fd2029f23	366	#define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) \| BF_FTM_CNT_COUNT(v)))
mbed_official	324:406fd2029f23	367	/@}/
mbed_official	324:406fd2029f23	368
mbed_official	324:406fd2029f23	369	/*******************************************************************************
mbed_official	324:406fd2029f23	370	* HW_FTM_MOD - Modulo
mbed_official	324:406fd2029f23	371	******************************************************************************/
mbed_official	324:406fd2029f23	372
mbed_official	324:406fd2029f23	373	/*!
mbed_official	324:406fd2029f23	374	* @brief HW_FTM_MOD - Modulo (RW)
mbed_official	324:406fd2029f23	375	*
mbed_official	324:406fd2029f23	376	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	377	*
mbed_official	324:406fd2029f23	378	* The Modulo register contains the modulo value for the FTM counter. After the
mbed_official	324:406fd2029f23	379	* FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
mbed_official	324:406fd2029f23	380	* the next clock, and the next value of FTM counter depends on the selected
mbed_official	324:406fd2029f23	381	* counting method; see Counter. Writing to the MOD register latches the value into a
mbed_official	324:406fd2029f23	382	* buffer. The MOD register is updated with the value of its write buffer
mbed_official	324:406fd2029f23	383	* according to Registers updated from write buffers. If FTMEN = 0, this write coherency
mbed_official	324:406fd2029f23	384	* mechanism may be manually reset by writing to the SC register whether BDM is
mbed_official	324:406fd2029f23	385	* active or not. Initialize the FTM counter, by writing to CNT, before writing
mbed_official	324:406fd2029f23	386	* to the MOD register to avoid confusion about when the first counter overflow
mbed_official	324:406fd2029f23	387	* will occur.
mbed_official	324:406fd2029f23	388	*/
mbed_official	324:406fd2029f23	389	typedef union _hw_ftm_mod
mbed_official	324:406fd2029f23	390	{
mbed_official	324:406fd2029f23	391	uint32_t U;
mbed_official	324:406fd2029f23	392	struct _hw_ftm_mod_bitfields
mbed_official	324:406fd2029f23	393	{
mbed_official	324:406fd2029f23	394	uint32_t MOD : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	395	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	396	} B;
mbed_official	324:406fd2029f23	397	} hw_ftm_mod_t;
mbed_official	324:406fd2029f23	398
mbed_official	324:406fd2029f23	399	/*!
mbed_official	324:406fd2029f23	400	* @name Constants and macros for entire FTM_MOD register
mbed_official	324:406fd2029f23	401	*/
mbed_official	324:406fd2029f23	402	/@{/
mbed_official	324:406fd2029f23	403	#define HW_FTM_MOD_ADDR(x) ((x) + 0x8U)
mbed_official	324:406fd2029f23	404
mbed_official	324:406fd2029f23	405	#define HW_FTM_MOD(x) ((__IO hw_ftm_mod_t ) HW_FTM_MOD_ADDR(x))
mbed_official	324:406fd2029f23	406	#define HW_FTM_MOD_RD(x) (HW_FTM_MOD(x).U)
mbed_official	324:406fd2029f23	407	#define HW_FTM_MOD_WR(x, v) (HW_FTM_MOD(x).U = (v))
mbed_official	324:406fd2029f23	408	#define HW_FTM_MOD_SET(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) \| (v)))
mbed_official	324:406fd2029f23	409	#define HW_FTM_MOD_CLR(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	410	#define HW_FTM_MOD_TOG(x, v) (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	411	/@}/
mbed_official	324:406fd2029f23	412
mbed_official	324:406fd2029f23	413	/*
mbed_official	324:406fd2029f23	414	* Constants & macros for individual FTM_MOD bitfields
mbed_official	324:406fd2029f23	415	*/
mbed_official	324:406fd2029f23	416
mbed_official	324:406fd2029f23	417	/*!
mbed_official	324:406fd2029f23	418	* @name Register FTM_MOD, field MOD[15:0] (RW)
mbed_official	324:406fd2029f23	419	*
mbed_official	324:406fd2029f23	420	* Modulo Value
mbed_official	324:406fd2029f23	421	*/
mbed_official	324:406fd2029f23	422	/@{/
mbed_official	324:406fd2029f23	423	#define BP_FTM_MOD_MOD (0U) /!< Bit position for FTM_MOD_MOD. /
mbed_official	324:406fd2029f23	424	#define BM_FTM_MOD_MOD (0x0000FFFFU) /!< Bit mask for FTM_MOD_MOD. /
mbed_official	324:406fd2029f23	425	#define BS_FTM_MOD_MOD (16U) /!< Bit field size in bits for FTM_MOD_MOD. /
mbed_official	324:406fd2029f23	426
mbed_official	324:406fd2029f23	427	/! @brief Read current value of the FTM_MOD_MOD field. /
mbed_official	324:406fd2029f23	428	#define BR_FTM_MOD_MOD(x) (HW_FTM_MOD(x).B.MOD)
mbed_official	324:406fd2029f23	429
mbed_official	324:406fd2029f23	430	/! @brief Format value for bitfield FTM_MOD_MOD. /
mbed_official	324:406fd2029f23	431	#define BF_FTM_MOD_MOD(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
mbed_official	324:406fd2029f23	432
mbed_official	324:406fd2029f23	433	/! @brief Set the MOD field to a new value. /
mbed_official	324:406fd2029f23	434	#define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) \| BF_FTM_MOD_MOD(v)))
mbed_official	324:406fd2029f23	435	/@}/
mbed_official	324:406fd2029f23	436
mbed_official	324:406fd2029f23	437	/*******************************************************************************
mbed_official	324:406fd2029f23	438	* HW_FTM_CnSC - Channel (n) Status And Control
mbed_official	324:406fd2029f23	439	******************************************************************************/
mbed_official	324:406fd2029f23	440
mbed_official	324:406fd2029f23	441	/*!
mbed_official	324:406fd2029f23	442	* @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
mbed_official	324:406fd2029f23	443	*
mbed_official	324:406fd2029f23	444	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	445	*
mbed_official	324:406fd2029f23	446	* CnSC contains the channel-interrupt-status flag and control bits used to
mbed_official	324:406fd2029f23	447	* configure the interrupt enable, channel configuration, and pin function. Mode,
mbed_official	324:406fd2029f23	448	* edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
mbed_official	324:406fd2029f23	449	* Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
mbed_official	324:406fd2029f23	450	* purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
mbed_official	324:406fd2029f23	451	* Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
mbed_official	324:406fd2029f23	452	* 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
mbed_official	324:406fd2029f23	453	* Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
mbed_official	324:406fd2029f23	454	* X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
mbed_official	324:406fd2029f23	455	* pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
mbed_official	324:406fd2029f23	456	* 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
mbed_official	324:406fd2029f23	457	* channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
mbed_official	324:406fd2029f23	458	* on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
mbed_official	324:406fd2029f23	459	* Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
mbed_official	324:406fd2029f23	460	* Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
mbed_official	324:406fd2029f23	461	* Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
mbed_official	324:406fd2029f23	462	* Enabled Rising and falling edges
mbed_official	324:406fd2029f23	463	*/
mbed_official	324:406fd2029f23	464	typedef union _hw_ftm_cnsc
mbed_official	324:406fd2029f23	465	{
mbed_official	324:406fd2029f23	466	uint32_t U;
mbed_official	324:406fd2029f23	467	struct _hw_ftm_cnsc_bitfields
mbed_official	324:406fd2029f23	468	{
mbed_official	324:406fd2029f23	469	uint32_t DMA : 1; /!< [0] DMA Enable /
mbed_official	324:406fd2029f23	470	uint32_t ICRST : 1; /*!< [1] FTM counter reset by the selected input
mbed_official	324:406fd2029f23	471	* capture event. */
mbed_official	324:406fd2029f23	472	uint32_t ELSA : 1; /!< [2] Edge or Level Select /
mbed_official	324:406fd2029f23	473	uint32_t ELSB : 1; /!< [3] Edge or Level Select /
mbed_official	324:406fd2029f23	474	uint32_t MSA : 1; /!< [4] Channel Mode Select /
mbed_official	324:406fd2029f23	475	uint32_t MSB : 1; /!< [5] Channel Mode Select /
mbed_official	324:406fd2029f23	476	uint32_t CHIE : 1; /!< [6] Channel Interrupt Enable /
mbed_official	324:406fd2029f23	477	uint32_t CHF : 1; /!< [7] Channel Flag /
mbed_official	324:406fd2029f23	478	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	479	} B;
mbed_official	324:406fd2029f23	480	} hw_ftm_cnsc_t;
mbed_official	324:406fd2029f23	481
mbed_official	324:406fd2029f23	482	/*!
mbed_official	324:406fd2029f23	483	* @name Constants and macros for entire FTM_CnSC register
mbed_official	324:406fd2029f23	484	*/
mbed_official	324:406fd2029f23	485	/@{/
mbed_official	324:406fd2029f23	486	#define HW_FTM_CnSC_COUNT (8U)
mbed_official	324:406fd2029f23	487
mbed_official	324:406fd2029f23	488	#define HW_FTM_CnSC_ADDR(x, n) ((x) + 0xCU + (0x8U * (n)))
mbed_official	324:406fd2029f23	489
mbed_official	324:406fd2029f23	490	#define HW_FTM_CnSC(x, n) ((__IO hw_ftm_cnsc_t ) HW_FTM_CnSC_ADDR(x, n))
mbed_official	324:406fd2029f23	491	#define HW_FTM_CnSC_RD(x, n) (HW_FTM_CnSC(x, n).U)
mbed_official	324:406fd2029f23	492	#define HW_FTM_CnSC_WR(x, n, v) (HW_FTM_CnSC(x, n).U = (v))
mbed_official	324:406fd2029f23	493	#define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	494	#define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	495	#define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	496	/@}/
mbed_official	324:406fd2029f23	497
mbed_official	324:406fd2029f23	498	/*
mbed_official	324:406fd2029f23	499	* Constants & macros for individual FTM_CnSC bitfields
mbed_official	324:406fd2029f23	500	*/
mbed_official	324:406fd2029f23	501
mbed_official	324:406fd2029f23	502	/*!
mbed_official	324:406fd2029f23	503	* @name Register FTM_CnSC, field DMA[0] (RW)
mbed_official	324:406fd2029f23	504	*
mbed_official	324:406fd2029f23	505	* Enables DMA transfers for the channel.
mbed_official	324:406fd2029f23	506	*
mbed_official	324:406fd2029f23	507	* Values:
mbed_official	324:406fd2029f23	508	* - 0 - Disable DMA transfers.
mbed_official	324:406fd2029f23	509	* - 1 - Enable DMA transfers.
mbed_official	324:406fd2029f23	510	*/
mbed_official	324:406fd2029f23	511	/@{/
mbed_official	324:406fd2029f23	512	#define BP_FTM_CnSC_DMA (0U) /!< Bit position for FTM_CnSC_DMA. /
mbed_official	324:406fd2029f23	513	#define BM_FTM_CnSC_DMA (0x00000001U) /!< Bit mask for FTM_CnSC_DMA. /
mbed_official	324:406fd2029f23	514	#define BS_FTM_CnSC_DMA (1U) /!< Bit field size in bits for FTM_CnSC_DMA. /
mbed_official	324:406fd2029f23	515
mbed_official	324:406fd2029f23	516	/! @brief Read current value of the FTM_CnSC_DMA field. /
mbed_official	324:406fd2029f23	517	#define BR_FTM_CnSC_DMA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA))
mbed_official	324:406fd2029f23	518
mbed_official	324:406fd2029f23	519	/! @brief Format value for bitfield FTM_CnSC_DMA. /
mbed_official	324:406fd2029f23	520	#define BF_FTM_CnSC_DMA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
mbed_official	324:406fd2029f23	521
mbed_official	324:406fd2029f23	522	/! @brief Set the DMA field to a new value. /
mbed_official	324:406fd2029f23	523	#define BW_FTM_CnSC_DMA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA) = (v))
mbed_official	324:406fd2029f23	524	/@}/
mbed_official	324:406fd2029f23	525
mbed_official	324:406fd2029f23	526	/*!
mbed_official	324:406fd2029f23	527	* @name Register FTM_CnSC, field ICRST[1] (RW)
mbed_official	324:406fd2029f23	528	*
mbed_official	324:406fd2029f23	529	* FTM counter reset is driven by the selected event of the channel (n) in the
mbed_official	324:406fd2029f23	530	* Input Capture mode. This field is write protected. It can be written only when
mbed_official	324:406fd2029f23	531	* MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	532	*
mbed_official	324:406fd2029f23	533	* Values:
mbed_official	324:406fd2029f23	534	* - 0 - FTM counter is not reset when the selected channel (n) input event is
mbed_official	324:406fd2029f23	535	* detected.
mbed_official	324:406fd2029f23	536	* - 1 - FTM counter is reset when the selected channel (n) input event is
mbed_official	324:406fd2029f23	537	* detected.
mbed_official	324:406fd2029f23	538	*/
mbed_official	324:406fd2029f23	539	/@{/
mbed_official	324:406fd2029f23	540	#define BP_FTM_CnSC_ICRST (1U) /!< Bit position for FTM_CnSC_ICRST. /
mbed_official	324:406fd2029f23	541	#define BM_FTM_CnSC_ICRST (0x00000002U) /!< Bit mask for FTM_CnSC_ICRST. /
mbed_official	324:406fd2029f23	542	#define BS_FTM_CnSC_ICRST (1U) /!< Bit field size in bits for FTM_CnSC_ICRST. /
mbed_official	324:406fd2029f23	543
mbed_official	324:406fd2029f23	544	/! @brief Read current value of the FTM_CnSC_ICRST field. /
mbed_official	324:406fd2029f23	545	#define BR_FTM_CnSC_ICRST(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST))
mbed_official	324:406fd2029f23	546
mbed_official	324:406fd2029f23	547	/! @brief Format value for bitfield FTM_CnSC_ICRST. /
mbed_official	324:406fd2029f23	548	#define BF_FTM_CnSC_ICRST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ICRST) & BM_FTM_CnSC_ICRST)
mbed_official	324:406fd2029f23	549
mbed_official	324:406fd2029f23	550	/! @brief Set the ICRST field to a new value. /
mbed_official	324:406fd2029f23	551	#define BW_FTM_CnSC_ICRST(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ICRST) = (v))
mbed_official	324:406fd2029f23	552	/@}/
mbed_official	324:406fd2029f23	553
mbed_official	324:406fd2029f23	554	/*!
mbed_official	324:406fd2029f23	555	* @name Register FTM_CnSC, field ELSA[2] (RW)
mbed_official	324:406fd2029f23	556	*
mbed_official	324:406fd2029f23	557	* The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official	324:406fd2029f23	558	* #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	324:406fd2029f23	559	* = 1.
mbed_official	324:406fd2029f23	560	*/
mbed_official	324:406fd2029f23	561	/@{/
mbed_official	324:406fd2029f23	562	#define BP_FTM_CnSC_ELSA (2U) /!< Bit position for FTM_CnSC_ELSA. /
mbed_official	324:406fd2029f23	563	#define BM_FTM_CnSC_ELSA (0x00000004U) /!< Bit mask for FTM_CnSC_ELSA. /
mbed_official	324:406fd2029f23	564	#define BS_FTM_CnSC_ELSA (1U) /!< Bit field size in bits for FTM_CnSC_ELSA. /
mbed_official	324:406fd2029f23	565
mbed_official	324:406fd2029f23	566	/! @brief Read current value of the FTM_CnSC_ELSA field. /
mbed_official	324:406fd2029f23	567	#define BR_FTM_CnSC_ELSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA))
mbed_official	324:406fd2029f23	568
mbed_official	324:406fd2029f23	569	/! @brief Format value for bitfield FTM_CnSC_ELSA. /
mbed_official	324:406fd2029f23	570	#define BF_FTM_CnSC_ELSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
mbed_official	324:406fd2029f23	571
mbed_official	324:406fd2029f23	572	/! @brief Set the ELSA field to a new value. /
mbed_official	324:406fd2029f23	573	#define BW_FTM_CnSC_ELSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA) = (v))
mbed_official	324:406fd2029f23	574	/@}/
mbed_official	324:406fd2029f23	575
mbed_official	324:406fd2029f23	576	/*!
mbed_official	324:406fd2029f23	577	* @name Register FTM_CnSC, field ELSB[3] (RW)
mbed_official	324:406fd2029f23	578	*
mbed_official	324:406fd2029f23	579	* The functionality of ELSB and ELSA depends on the channel mode. See
mbed_official	324:406fd2029f23	580	* #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
mbed_official	324:406fd2029f23	581	* = 1.
mbed_official	324:406fd2029f23	582	*/
mbed_official	324:406fd2029f23	583	/@{/
mbed_official	324:406fd2029f23	584	#define BP_FTM_CnSC_ELSB (3U) /!< Bit position for FTM_CnSC_ELSB. /
mbed_official	324:406fd2029f23	585	#define BM_FTM_CnSC_ELSB (0x00000008U) /!< Bit mask for FTM_CnSC_ELSB. /
mbed_official	324:406fd2029f23	586	#define BS_FTM_CnSC_ELSB (1U) /!< Bit field size in bits for FTM_CnSC_ELSB. /
mbed_official	324:406fd2029f23	587
mbed_official	324:406fd2029f23	588	/! @brief Read current value of the FTM_CnSC_ELSB field. /
mbed_official	324:406fd2029f23	589	#define BR_FTM_CnSC_ELSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB))
mbed_official	324:406fd2029f23	590
mbed_official	324:406fd2029f23	591	/! @brief Format value for bitfield FTM_CnSC_ELSB. /
mbed_official	324:406fd2029f23	592	#define BF_FTM_CnSC_ELSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
mbed_official	324:406fd2029f23	593
mbed_official	324:406fd2029f23	594	/! @brief Set the ELSB field to a new value. /
mbed_official	324:406fd2029f23	595	#define BW_FTM_CnSC_ELSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB) = (v))
mbed_official	324:406fd2029f23	596	/@}/
mbed_official	324:406fd2029f23	597
mbed_official	324:406fd2029f23	598	/*!
mbed_official	324:406fd2029f23	599	* @name Register FTM_CnSC, field MSA[4] (RW)
mbed_official	324:406fd2029f23	600	*
mbed_official	324:406fd2029f23	601	* Used for further selections in the channel logic. Its functionality is
mbed_official	324:406fd2029f23	602	* dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official	324:406fd2029f23	603	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	604	*/
mbed_official	324:406fd2029f23	605	/@{/
mbed_official	324:406fd2029f23	606	#define BP_FTM_CnSC_MSA (4U) /!< Bit position for FTM_CnSC_MSA. /
mbed_official	324:406fd2029f23	607	#define BM_FTM_CnSC_MSA (0x00000010U) /!< Bit mask for FTM_CnSC_MSA. /
mbed_official	324:406fd2029f23	608	#define BS_FTM_CnSC_MSA (1U) /!< Bit field size in bits for FTM_CnSC_MSA. /
mbed_official	324:406fd2029f23	609
mbed_official	324:406fd2029f23	610	/! @brief Read current value of the FTM_CnSC_MSA field. /
mbed_official	324:406fd2029f23	611	#define BR_FTM_CnSC_MSA(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA))
mbed_official	324:406fd2029f23	612
mbed_official	324:406fd2029f23	613	/! @brief Format value for bitfield FTM_CnSC_MSA. /
mbed_official	324:406fd2029f23	614	#define BF_FTM_CnSC_MSA(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
mbed_official	324:406fd2029f23	615
mbed_official	324:406fd2029f23	616	/! @brief Set the MSA field to a new value. /
mbed_official	324:406fd2029f23	617	#define BW_FTM_CnSC_MSA(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA) = (v))
mbed_official	324:406fd2029f23	618	/@}/
mbed_official	324:406fd2029f23	619
mbed_official	324:406fd2029f23	620	/*!
mbed_official	324:406fd2029f23	621	* @name Register FTM_CnSC, field MSB[5] (RW)
mbed_official	324:406fd2029f23	622	*
mbed_official	324:406fd2029f23	623	* Used for further selections in the channel logic. Its functionality is
mbed_official	324:406fd2029f23	624	* dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
mbed_official	324:406fd2029f23	625	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	626	*/
mbed_official	324:406fd2029f23	627	/@{/
mbed_official	324:406fd2029f23	628	#define BP_FTM_CnSC_MSB (5U) /!< Bit position for FTM_CnSC_MSB. /
mbed_official	324:406fd2029f23	629	#define BM_FTM_CnSC_MSB (0x00000020U) /!< Bit mask for FTM_CnSC_MSB. /
mbed_official	324:406fd2029f23	630	#define BS_FTM_CnSC_MSB (1U) /!< Bit field size in bits for FTM_CnSC_MSB. /
mbed_official	324:406fd2029f23	631
mbed_official	324:406fd2029f23	632	/! @brief Read current value of the FTM_CnSC_MSB field. /
mbed_official	324:406fd2029f23	633	#define BR_FTM_CnSC_MSB(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB))
mbed_official	324:406fd2029f23	634
mbed_official	324:406fd2029f23	635	/! @brief Format value for bitfield FTM_CnSC_MSB. /
mbed_official	324:406fd2029f23	636	#define BF_FTM_CnSC_MSB(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
mbed_official	324:406fd2029f23	637
mbed_official	324:406fd2029f23	638	/! @brief Set the MSB field to a new value. /
mbed_official	324:406fd2029f23	639	#define BW_FTM_CnSC_MSB(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB) = (v))
mbed_official	324:406fd2029f23	640	/@}/
mbed_official	324:406fd2029f23	641
mbed_official	324:406fd2029f23	642	/*!
mbed_official	324:406fd2029f23	643	* @name Register FTM_CnSC, field CHIE[6] (RW)
mbed_official	324:406fd2029f23	644	*
mbed_official	324:406fd2029f23	645	* Enables channel interrupts.
mbed_official	324:406fd2029f23	646	*
mbed_official	324:406fd2029f23	647	* Values:
mbed_official	324:406fd2029f23	648	* - 0 - Disable channel interrupts. Use software polling.
mbed_official	324:406fd2029f23	649	* - 1 - Enable channel interrupts.
mbed_official	324:406fd2029f23	650	*/
mbed_official	324:406fd2029f23	651	/@{/
mbed_official	324:406fd2029f23	652	#define BP_FTM_CnSC_CHIE (6U) /!< Bit position for FTM_CnSC_CHIE. /
mbed_official	324:406fd2029f23	653	#define BM_FTM_CnSC_CHIE (0x00000040U) /!< Bit mask for FTM_CnSC_CHIE. /
mbed_official	324:406fd2029f23	654	#define BS_FTM_CnSC_CHIE (1U) /!< Bit field size in bits for FTM_CnSC_CHIE. /
mbed_official	324:406fd2029f23	655
mbed_official	324:406fd2029f23	656	/! @brief Read current value of the FTM_CnSC_CHIE field. /
mbed_official	324:406fd2029f23	657	#define BR_FTM_CnSC_CHIE(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE))
mbed_official	324:406fd2029f23	658
mbed_official	324:406fd2029f23	659	/! @brief Format value for bitfield FTM_CnSC_CHIE. /
mbed_official	324:406fd2029f23	660	#define BF_FTM_CnSC_CHIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
mbed_official	324:406fd2029f23	661
mbed_official	324:406fd2029f23	662	/! @brief Set the CHIE field to a new value. /
mbed_official	324:406fd2029f23	663	#define BW_FTM_CnSC_CHIE(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE) = (v))
mbed_official	324:406fd2029f23	664	/@}/
mbed_official	324:406fd2029f23	665
mbed_official	324:406fd2029f23	666	/*!
mbed_official	324:406fd2029f23	667	* @name Register FTM_CnSC, field CHF[7] (ROWZ)
mbed_official	324:406fd2029f23	668	*
mbed_official	324:406fd2029f23	669	* Set by hardware when an event occurs on the channel. CHF is cleared by
mbed_official	324:406fd2029f23	670	* reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
mbed_official	324:406fd2029f23	671	* Writing a 1 to CHF has no effect. If another event occurs between the read and
mbed_official	324:406fd2029f23	672	* write operations, the write operation has no effect; therefore, CHF remains set
mbed_official	324:406fd2029f23	673	* indicating an event has occurred. In this case a CHF interrupt request is not
mbed_official	324:406fd2029f23	674	* lost due to the clearing sequence for a previous CHF.
mbed_official	324:406fd2029f23	675	*
mbed_official	324:406fd2029f23	676	* Values:
mbed_official	324:406fd2029f23	677	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	678	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	679	*/
mbed_official	324:406fd2029f23	680	/@{/
mbed_official	324:406fd2029f23	681	#define BP_FTM_CnSC_CHF (7U) /!< Bit position for FTM_CnSC_CHF. /
mbed_official	324:406fd2029f23	682	#define BM_FTM_CnSC_CHF (0x00000080U) /!< Bit mask for FTM_CnSC_CHF. /
mbed_official	324:406fd2029f23	683	#define BS_FTM_CnSC_CHF (1U) /!< Bit field size in bits for FTM_CnSC_CHF. /
mbed_official	324:406fd2029f23	684
mbed_official	324:406fd2029f23	685	/! @brief Read current value of the FTM_CnSC_CHF field. /
mbed_official	324:406fd2029f23	686	#define BR_FTM_CnSC_CHF(x, n) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF))
mbed_official	324:406fd2029f23	687
mbed_official	324:406fd2029f23	688	/! @brief Format value for bitfield FTM_CnSC_CHF. /
mbed_official	324:406fd2029f23	689	#define BF_FTM_CnSC_CHF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
mbed_official	324:406fd2029f23	690
mbed_official	324:406fd2029f23	691	/! @brief Set the CHF field to a new value. /
mbed_official	324:406fd2029f23	692	#define BW_FTM_CnSC_CHF(x, n, v) (BITBAND_ACCESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF) = (v))
mbed_official	324:406fd2029f23	693	/@}/
mbed_official	324:406fd2029f23	694	/*******************************************************************************
mbed_official	324:406fd2029f23	695	* HW_FTM_CnV - Channel (n) Value
mbed_official	324:406fd2029f23	696	******************************************************************************/
mbed_official	324:406fd2029f23	697
mbed_official	324:406fd2029f23	698	/*!
mbed_official	324:406fd2029f23	699	* @brief HW_FTM_CnV - Channel (n) Value (RW)
mbed_official	324:406fd2029f23	700	*
mbed_official	324:406fd2029f23	701	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	702	*
mbed_official	324:406fd2029f23	703	* These registers contain the captured FTM counter value for the input modes or
mbed_official	324:406fd2029f23	704	* the match value for the output modes. In Input Capture, Capture Test, and
mbed_official	324:406fd2029f23	705	* Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
mbed_official	324:406fd2029f23	706	* writing to a CnV register latches the value into a buffer. A CnV register is
mbed_official	324:406fd2029f23	707	* updated with the value of its write buffer according to Registers updated from
mbed_official	324:406fd2029f23	708	* write buffers. If FTMEN = 0, this write coherency mechanism may be manually
mbed_official	324:406fd2029f23	709	* reset by writing to the CnSC register whether BDM mode is active or not.
mbed_official	324:406fd2029f23	710	*/
mbed_official	324:406fd2029f23	711	typedef union _hw_ftm_cnv
mbed_official	324:406fd2029f23	712	{
mbed_official	324:406fd2029f23	713	uint32_t U;
mbed_official	324:406fd2029f23	714	struct _hw_ftm_cnv_bitfields
mbed_official	324:406fd2029f23	715	{
mbed_official	324:406fd2029f23	716	uint32_t VAL : 16; /!< [15:0] Channel Value /
mbed_official	324:406fd2029f23	717	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	718	} B;
mbed_official	324:406fd2029f23	719	} hw_ftm_cnv_t;
mbed_official	324:406fd2029f23	720
mbed_official	324:406fd2029f23	721	/*!
mbed_official	324:406fd2029f23	722	* @name Constants and macros for entire FTM_CnV register
mbed_official	324:406fd2029f23	723	*/
mbed_official	324:406fd2029f23	724	/@{/
mbed_official	324:406fd2029f23	725	#define HW_FTM_CnV_COUNT (8U)
mbed_official	324:406fd2029f23	726
mbed_official	324:406fd2029f23	727	#define HW_FTM_CnV_ADDR(x, n) ((x) + 0x10U + (0x8U * (n)))
mbed_official	324:406fd2029f23	728
mbed_official	324:406fd2029f23	729	#define HW_FTM_CnV(x, n) ((__IO hw_ftm_cnv_t ) HW_FTM_CnV_ADDR(x, n))
mbed_official	324:406fd2029f23	730	#define HW_FTM_CnV_RD(x, n) (HW_FTM_CnV(x, n).U)
mbed_official	324:406fd2029f23	731	#define HW_FTM_CnV_WR(x, n, v) (HW_FTM_CnV(x, n).U = (v))
mbed_official	324:406fd2029f23	732	#define HW_FTM_CnV_SET(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) \| (v)))
mbed_official	324:406fd2029f23	733	#define HW_FTM_CnV_CLR(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
mbed_official	324:406fd2029f23	734	#define HW_FTM_CnV_TOG(x, n, v) (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^ (v)))
mbed_official	324:406fd2029f23	735	/@}/
mbed_official	324:406fd2029f23	736
mbed_official	324:406fd2029f23	737	/*
mbed_official	324:406fd2029f23	738	* Constants & macros for individual FTM_CnV bitfields
mbed_official	324:406fd2029f23	739	*/
mbed_official	324:406fd2029f23	740
mbed_official	324:406fd2029f23	741	/*!
mbed_official	324:406fd2029f23	742	* @name Register FTM_CnV, field VAL[15:0] (RW)
mbed_official	324:406fd2029f23	743	*
mbed_official	324:406fd2029f23	744	* Captured FTM counter value of the input modes or the match value for the
mbed_official	324:406fd2029f23	745	* output modes
mbed_official	324:406fd2029f23	746	*/
mbed_official	324:406fd2029f23	747	/@{/
mbed_official	324:406fd2029f23	748	#define BP_FTM_CnV_VAL (0U) /!< Bit position for FTM_CnV_VAL. /
mbed_official	324:406fd2029f23	749	#define BM_FTM_CnV_VAL (0x0000FFFFU) /!< Bit mask for FTM_CnV_VAL. /
mbed_official	324:406fd2029f23	750	#define BS_FTM_CnV_VAL (16U) /!< Bit field size in bits for FTM_CnV_VAL. /
mbed_official	324:406fd2029f23	751
mbed_official	324:406fd2029f23	752	/! @brief Read current value of the FTM_CnV_VAL field. /
mbed_official	324:406fd2029f23	753	#define BR_FTM_CnV_VAL(x, n) (HW_FTM_CnV(x, n).B.VAL)
mbed_official	324:406fd2029f23	754
mbed_official	324:406fd2029f23	755	/! @brief Format value for bitfield FTM_CnV_VAL. /
mbed_official	324:406fd2029f23	756	#define BF_FTM_CnV_VAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
mbed_official	324:406fd2029f23	757
mbed_official	324:406fd2029f23	758	/! @brief Set the VAL field to a new value. /
mbed_official	324:406fd2029f23	759	#define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) \| BF_FTM_CnV_VAL(v)))
mbed_official	324:406fd2029f23	760	/@}/
mbed_official	324:406fd2029f23	761
mbed_official	324:406fd2029f23	762	/*******************************************************************************
mbed_official	324:406fd2029f23	763	* HW_FTM_CNTIN - Counter Initial Value
mbed_official	324:406fd2029f23	764	******************************************************************************/
mbed_official	324:406fd2029f23	765
mbed_official	324:406fd2029f23	766	/*!
mbed_official	324:406fd2029f23	767	* @brief HW_FTM_CNTIN - Counter Initial Value (RW)
mbed_official	324:406fd2029f23	768	*
mbed_official	324:406fd2029f23	769	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	770	*
mbed_official	324:406fd2029f23	771	* The Counter Initial Value register contains the initial value for the FTM
mbed_official	324:406fd2029f23	772	* counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
mbed_official	324:406fd2029f23	773	* register is updated with the value of its write buffer according to Registers
mbed_official	324:406fd2029f23	774	* updated from write buffers. When the FTM clock is initially selected, by
mbed_official	324:406fd2029f23	775	* writing a non-zero value to the CLKS bits, the FTM counter starts with the value
mbed_official	324:406fd2029f23	776	* 0x0000. To avoid this behavior, before the first write to select the FTM clock,
mbed_official	324:406fd2029f23	777	* write the new value to the the CNTIN register and then initialize the FTM
mbed_official	324:406fd2029f23	778	* counter by writing any value to the CNT register.
mbed_official	324:406fd2029f23	779	*/
mbed_official	324:406fd2029f23	780	typedef union _hw_ftm_cntin
mbed_official	324:406fd2029f23	781	{
mbed_official	324:406fd2029f23	782	uint32_t U;
mbed_official	324:406fd2029f23	783	struct _hw_ftm_cntin_bitfields
mbed_official	324:406fd2029f23	784	{
mbed_official	324:406fd2029f23	785	uint32_t INIT : 16; /!< [15:0] /
mbed_official	324:406fd2029f23	786	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	787	} B;
mbed_official	324:406fd2029f23	788	} hw_ftm_cntin_t;
mbed_official	324:406fd2029f23	789
mbed_official	324:406fd2029f23	790	/*!
mbed_official	324:406fd2029f23	791	* @name Constants and macros for entire FTM_CNTIN register
mbed_official	324:406fd2029f23	792	*/
mbed_official	324:406fd2029f23	793	/@{/
mbed_official	324:406fd2029f23	794	#define HW_FTM_CNTIN_ADDR(x) ((x) + 0x4CU)
mbed_official	324:406fd2029f23	795
mbed_official	324:406fd2029f23	796	#define HW_FTM_CNTIN(x) ((__IO hw_ftm_cntin_t ) HW_FTM_CNTIN_ADDR(x))
mbed_official	324:406fd2029f23	797	#define HW_FTM_CNTIN_RD(x) (HW_FTM_CNTIN(x).U)
mbed_official	324:406fd2029f23	798	#define HW_FTM_CNTIN_WR(x, v) (HW_FTM_CNTIN(x).U = (v))
mbed_official	324:406fd2029f23	799	#define HW_FTM_CNTIN_SET(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) \| (v)))
mbed_official	324:406fd2029f23	800	#define HW_FTM_CNTIN_CLR(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	801	#define HW_FTM_CNTIN_TOG(x, v) (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	802	/@}/
mbed_official	324:406fd2029f23	803
mbed_official	324:406fd2029f23	804	/*
mbed_official	324:406fd2029f23	805	* Constants & macros for individual FTM_CNTIN bitfields
mbed_official	324:406fd2029f23	806	*/
mbed_official	324:406fd2029f23	807
mbed_official	324:406fd2029f23	808	/*!
mbed_official	324:406fd2029f23	809	* @name Register FTM_CNTIN, field INIT[15:0] (RW)
mbed_official	324:406fd2029f23	810	*
mbed_official	324:406fd2029f23	811	* Initial Value Of The FTM Counter
mbed_official	324:406fd2029f23	812	*/
mbed_official	324:406fd2029f23	813	/@{/
mbed_official	324:406fd2029f23	814	#define BP_FTM_CNTIN_INIT (0U) /!< Bit position for FTM_CNTIN_INIT. /
mbed_official	324:406fd2029f23	815	#define BM_FTM_CNTIN_INIT (0x0000FFFFU) /!< Bit mask for FTM_CNTIN_INIT. /
mbed_official	324:406fd2029f23	816	#define BS_FTM_CNTIN_INIT (16U) /!< Bit field size in bits for FTM_CNTIN_INIT. /
mbed_official	324:406fd2029f23	817
mbed_official	324:406fd2029f23	818	/! @brief Read current value of the FTM_CNTIN_INIT field. /
mbed_official	324:406fd2029f23	819	#define BR_FTM_CNTIN_INIT(x) (HW_FTM_CNTIN(x).B.INIT)
mbed_official	324:406fd2029f23	820
mbed_official	324:406fd2029f23	821	/! @brief Format value for bitfield FTM_CNTIN_INIT. /
mbed_official	324:406fd2029f23	822	#define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
mbed_official	324:406fd2029f23	823
mbed_official	324:406fd2029f23	824	/! @brief Set the INIT field to a new value. /
mbed_official	324:406fd2029f23	825	#define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) \| BF_FTM_CNTIN_INIT(v)))
mbed_official	324:406fd2029f23	826	/@}/
mbed_official	324:406fd2029f23	827
mbed_official	324:406fd2029f23	828	/*******************************************************************************
mbed_official	324:406fd2029f23	829	* HW_FTM_STATUS - Capture And Compare Status
mbed_official	324:406fd2029f23	830	******************************************************************************/
mbed_official	324:406fd2029f23	831
mbed_official	324:406fd2029f23	832	/*!
mbed_official	324:406fd2029f23	833	* @brief HW_FTM_STATUS - Capture And Compare Status (RW)
mbed_official	324:406fd2029f23	834	*
mbed_official	324:406fd2029f23	835	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	836	*
mbed_official	324:406fd2029f23	837	* The STATUS register contains a copy of the status flag CHnF bit in CnSC for
mbed_official	324:406fd2029f23	838	* each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
mbed_official	324:406fd2029f23	839	* of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
mbed_official	324:406fd2029f23	840	* STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
mbed_official	324:406fd2029f23	841	* STATUS. Hardware sets the individual channel flags when an event occurs on the
mbed_official	324:406fd2029f23	842	* channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
mbed_official	324:406fd2029f23	843	* a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
mbed_official	324:406fd2029f23	844	* occurs between the read and write operations, the write operation has no effect;
mbed_official	324:406fd2029f23	845	* therefore, CHnF remains set indicating an event has occurred. In this case, a
mbed_official	324:406fd2029f23	846	* CHnF interrupt request is not lost due to the clearing sequence for a previous
mbed_official	324:406fd2029f23	847	* CHnF. The STATUS register should be used only in Combine mode.
mbed_official	324:406fd2029f23	848	*/
mbed_official	324:406fd2029f23	849	typedef union _hw_ftm_status
mbed_official	324:406fd2029f23	850	{
mbed_official	324:406fd2029f23	851	uint32_t U;
mbed_official	324:406fd2029f23	852	struct _hw_ftm_status_bitfields
mbed_official	324:406fd2029f23	853	{
mbed_official	324:406fd2029f23	854	uint32_t CH0F : 1; /!< [0] Channel 0 Flag /
mbed_official	324:406fd2029f23	855	uint32_t CH1F : 1; /!< [1] Channel 1 Flag /
mbed_official	324:406fd2029f23	856	uint32_t CH2F : 1; /!< [2] Channel 2 Flag /
mbed_official	324:406fd2029f23	857	uint32_t CH3F : 1; /!< [3] Channel 3 Flag /
mbed_official	324:406fd2029f23	858	uint32_t CH4F : 1; /!< [4] Channel 4 Flag /
mbed_official	324:406fd2029f23	859	uint32_t CH5F : 1; /!< [5] Channel 5 Flag /
mbed_official	324:406fd2029f23	860	uint32_t CH6F : 1; /!< [6] Channel 6 Flag /
mbed_official	324:406fd2029f23	861	uint32_t CH7F : 1; /!< [7] Channel 7 Flag /
mbed_official	324:406fd2029f23	862	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	863	} B;
mbed_official	324:406fd2029f23	864	} hw_ftm_status_t;
mbed_official	324:406fd2029f23	865
mbed_official	324:406fd2029f23	866	/*!
mbed_official	324:406fd2029f23	867	* @name Constants and macros for entire FTM_STATUS register
mbed_official	324:406fd2029f23	868	*/
mbed_official	324:406fd2029f23	869	/@{/
mbed_official	324:406fd2029f23	870	#define HW_FTM_STATUS_ADDR(x) ((x) + 0x50U)
mbed_official	324:406fd2029f23	871
mbed_official	324:406fd2029f23	872	#define HW_FTM_STATUS(x) ((__IO hw_ftm_status_t ) HW_FTM_STATUS_ADDR(x))
mbed_official	324:406fd2029f23	873	#define HW_FTM_STATUS_RD(x) (HW_FTM_STATUS(x).U)
mbed_official	324:406fd2029f23	874	#define HW_FTM_STATUS_WR(x, v) (HW_FTM_STATUS(x).U = (v))
mbed_official	324:406fd2029f23	875	#define HW_FTM_STATUS_SET(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) \| (v)))
mbed_official	324:406fd2029f23	876	#define HW_FTM_STATUS_CLR(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	877	#define HW_FTM_STATUS_TOG(x, v) (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	878	/@}/
mbed_official	324:406fd2029f23	879
mbed_official	324:406fd2029f23	880	/*
mbed_official	324:406fd2029f23	881	* Constants & macros for individual FTM_STATUS bitfields
mbed_official	324:406fd2029f23	882	*/
mbed_official	324:406fd2029f23	883
mbed_official	324:406fd2029f23	884	/*!
mbed_official	324:406fd2029f23	885	* @name Register FTM_STATUS, field CH0F[0] (W1C)
mbed_official	324:406fd2029f23	886	*
mbed_official	324:406fd2029f23	887	* See the register description.
mbed_official	324:406fd2029f23	888	*
mbed_official	324:406fd2029f23	889	* Values:
mbed_official	324:406fd2029f23	890	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	891	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	892	*/
mbed_official	324:406fd2029f23	893	/@{/
mbed_official	324:406fd2029f23	894	#define BP_FTM_STATUS_CH0F (0U) /!< Bit position for FTM_STATUS_CH0F. /
mbed_official	324:406fd2029f23	895	#define BM_FTM_STATUS_CH0F (0x00000001U) /!< Bit mask for FTM_STATUS_CH0F. /
mbed_official	324:406fd2029f23	896	#define BS_FTM_STATUS_CH0F (1U) /!< Bit field size in bits for FTM_STATUS_CH0F. /
mbed_official	324:406fd2029f23	897
mbed_official	324:406fd2029f23	898	/! @brief Read current value of the FTM_STATUS_CH0F field. /
mbed_official	324:406fd2029f23	899	#define BR_FTM_STATUS_CH0F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F))
mbed_official	324:406fd2029f23	900
mbed_official	324:406fd2029f23	901	/! @brief Format value for bitfield FTM_STATUS_CH0F. /
mbed_official	324:406fd2029f23	902	#define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
mbed_official	324:406fd2029f23	903
mbed_official	324:406fd2029f23	904	/! @brief Set the CH0F field to a new value. /
mbed_official	324:406fd2029f23	905	#define BW_FTM_STATUS_CH0F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F) = (v))
mbed_official	324:406fd2029f23	906	/@}/
mbed_official	324:406fd2029f23	907
mbed_official	324:406fd2029f23	908	/*!
mbed_official	324:406fd2029f23	909	* @name Register FTM_STATUS, field CH1F[1] (W1C)
mbed_official	324:406fd2029f23	910	*
mbed_official	324:406fd2029f23	911	* See the register description.
mbed_official	324:406fd2029f23	912	*
mbed_official	324:406fd2029f23	913	* Values:
mbed_official	324:406fd2029f23	914	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	915	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	916	*/
mbed_official	324:406fd2029f23	917	/@{/
mbed_official	324:406fd2029f23	918	#define BP_FTM_STATUS_CH1F (1U) /!< Bit position for FTM_STATUS_CH1F. /
mbed_official	324:406fd2029f23	919	#define BM_FTM_STATUS_CH1F (0x00000002U) /!< Bit mask for FTM_STATUS_CH1F. /
mbed_official	324:406fd2029f23	920	#define BS_FTM_STATUS_CH1F (1U) /!< Bit field size in bits for FTM_STATUS_CH1F. /
mbed_official	324:406fd2029f23	921
mbed_official	324:406fd2029f23	922	/! @brief Read current value of the FTM_STATUS_CH1F field. /
mbed_official	324:406fd2029f23	923	#define BR_FTM_STATUS_CH1F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F))
mbed_official	324:406fd2029f23	924
mbed_official	324:406fd2029f23	925	/! @brief Format value for bitfield FTM_STATUS_CH1F. /
mbed_official	324:406fd2029f23	926	#define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
mbed_official	324:406fd2029f23	927
mbed_official	324:406fd2029f23	928	/! @brief Set the CH1F field to a new value. /
mbed_official	324:406fd2029f23	929	#define BW_FTM_STATUS_CH1F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F) = (v))
mbed_official	324:406fd2029f23	930	/@}/
mbed_official	324:406fd2029f23	931
mbed_official	324:406fd2029f23	932	/*!
mbed_official	324:406fd2029f23	933	* @name Register FTM_STATUS, field CH2F[2] (W1C)
mbed_official	324:406fd2029f23	934	*
mbed_official	324:406fd2029f23	935	* See the register description.
mbed_official	324:406fd2029f23	936	*
mbed_official	324:406fd2029f23	937	* Values:
mbed_official	324:406fd2029f23	938	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	939	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	940	*/
mbed_official	324:406fd2029f23	941	/@{/
mbed_official	324:406fd2029f23	942	#define BP_FTM_STATUS_CH2F (2U) /!< Bit position for FTM_STATUS_CH2F. /
mbed_official	324:406fd2029f23	943	#define BM_FTM_STATUS_CH2F (0x00000004U) /!< Bit mask for FTM_STATUS_CH2F. /
mbed_official	324:406fd2029f23	944	#define BS_FTM_STATUS_CH2F (1U) /!< Bit field size in bits for FTM_STATUS_CH2F. /
mbed_official	324:406fd2029f23	945
mbed_official	324:406fd2029f23	946	/! @brief Read current value of the FTM_STATUS_CH2F field. /
mbed_official	324:406fd2029f23	947	#define BR_FTM_STATUS_CH2F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F))
mbed_official	324:406fd2029f23	948
mbed_official	324:406fd2029f23	949	/! @brief Format value for bitfield FTM_STATUS_CH2F. /
mbed_official	324:406fd2029f23	950	#define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
mbed_official	324:406fd2029f23	951
mbed_official	324:406fd2029f23	952	/! @brief Set the CH2F field to a new value. /
mbed_official	324:406fd2029f23	953	#define BW_FTM_STATUS_CH2F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F) = (v))
mbed_official	324:406fd2029f23	954	/@}/
mbed_official	324:406fd2029f23	955
mbed_official	324:406fd2029f23	956	/*!
mbed_official	324:406fd2029f23	957	* @name Register FTM_STATUS, field CH3F[3] (W1C)
mbed_official	324:406fd2029f23	958	*
mbed_official	324:406fd2029f23	959	* See the register description.
mbed_official	324:406fd2029f23	960	*
mbed_official	324:406fd2029f23	961	* Values:
mbed_official	324:406fd2029f23	962	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	963	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	964	*/
mbed_official	324:406fd2029f23	965	/@{/
mbed_official	324:406fd2029f23	966	#define BP_FTM_STATUS_CH3F (3U) /!< Bit position for FTM_STATUS_CH3F. /
mbed_official	324:406fd2029f23	967	#define BM_FTM_STATUS_CH3F (0x00000008U) /!< Bit mask for FTM_STATUS_CH3F. /
mbed_official	324:406fd2029f23	968	#define BS_FTM_STATUS_CH3F (1U) /!< Bit field size in bits for FTM_STATUS_CH3F. /
mbed_official	324:406fd2029f23	969
mbed_official	324:406fd2029f23	970	/! @brief Read current value of the FTM_STATUS_CH3F field. /
mbed_official	324:406fd2029f23	971	#define BR_FTM_STATUS_CH3F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F))
mbed_official	324:406fd2029f23	972
mbed_official	324:406fd2029f23	973	/! @brief Format value for bitfield FTM_STATUS_CH3F. /
mbed_official	324:406fd2029f23	974	#define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
mbed_official	324:406fd2029f23	975
mbed_official	324:406fd2029f23	976	/! @brief Set the CH3F field to a new value. /
mbed_official	324:406fd2029f23	977	#define BW_FTM_STATUS_CH3F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F) = (v))
mbed_official	324:406fd2029f23	978	/@}/
mbed_official	324:406fd2029f23	979
mbed_official	324:406fd2029f23	980	/*!
mbed_official	324:406fd2029f23	981	* @name Register FTM_STATUS, field CH4F[4] (W1C)
mbed_official	324:406fd2029f23	982	*
mbed_official	324:406fd2029f23	983	* See the register description.
mbed_official	324:406fd2029f23	984	*
mbed_official	324:406fd2029f23	985	* Values:
mbed_official	324:406fd2029f23	986	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	987	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	988	*/
mbed_official	324:406fd2029f23	989	/@{/
mbed_official	324:406fd2029f23	990	#define BP_FTM_STATUS_CH4F (4U) /!< Bit position for FTM_STATUS_CH4F. /
mbed_official	324:406fd2029f23	991	#define BM_FTM_STATUS_CH4F (0x00000010U) /!< Bit mask for FTM_STATUS_CH4F. /
mbed_official	324:406fd2029f23	992	#define BS_FTM_STATUS_CH4F (1U) /!< Bit field size in bits for FTM_STATUS_CH4F. /
mbed_official	324:406fd2029f23	993
mbed_official	324:406fd2029f23	994	/! @brief Read current value of the FTM_STATUS_CH4F field. /
mbed_official	324:406fd2029f23	995	#define BR_FTM_STATUS_CH4F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F))
mbed_official	324:406fd2029f23	996
mbed_official	324:406fd2029f23	997	/! @brief Format value for bitfield FTM_STATUS_CH4F. /
mbed_official	324:406fd2029f23	998	#define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
mbed_official	324:406fd2029f23	999
mbed_official	324:406fd2029f23	1000	/! @brief Set the CH4F field to a new value. /
mbed_official	324:406fd2029f23	1001	#define BW_FTM_STATUS_CH4F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F) = (v))
mbed_official	324:406fd2029f23	1002	/@}/
mbed_official	324:406fd2029f23	1003
mbed_official	324:406fd2029f23	1004	/*!
mbed_official	324:406fd2029f23	1005	* @name Register FTM_STATUS, field CH5F[5] (W1C)
mbed_official	324:406fd2029f23	1006	*
mbed_official	324:406fd2029f23	1007	* See the register description.
mbed_official	324:406fd2029f23	1008	*
mbed_official	324:406fd2029f23	1009	* Values:
mbed_official	324:406fd2029f23	1010	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	1011	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	1012	*/
mbed_official	324:406fd2029f23	1013	/@{/
mbed_official	324:406fd2029f23	1014	#define BP_FTM_STATUS_CH5F (5U) /!< Bit position for FTM_STATUS_CH5F. /
mbed_official	324:406fd2029f23	1015	#define BM_FTM_STATUS_CH5F (0x00000020U) /!< Bit mask for FTM_STATUS_CH5F. /
mbed_official	324:406fd2029f23	1016	#define BS_FTM_STATUS_CH5F (1U) /!< Bit field size in bits for FTM_STATUS_CH5F. /
mbed_official	324:406fd2029f23	1017
mbed_official	324:406fd2029f23	1018	/! @brief Read current value of the FTM_STATUS_CH5F field. /
mbed_official	324:406fd2029f23	1019	#define BR_FTM_STATUS_CH5F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F))
mbed_official	324:406fd2029f23	1020
mbed_official	324:406fd2029f23	1021	/! @brief Format value for bitfield FTM_STATUS_CH5F. /
mbed_official	324:406fd2029f23	1022	#define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
mbed_official	324:406fd2029f23	1023
mbed_official	324:406fd2029f23	1024	/! @brief Set the CH5F field to a new value. /
mbed_official	324:406fd2029f23	1025	#define BW_FTM_STATUS_CH5F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F) = (v))
mbed_official	324:406fd2029f23	1026	/@}/
mbed_official	324:406fd2029f23	1027
mbed_official	324:406fd2029f23	1028	/*!
mbed_official	324:406fd2029f23	1029	* @name Register FTM_STATUS, field CH6F[6] (W1C)
mbed_official	324:406fd2029f23	1030	*
mbed_official	324:406fd2029f23	1031	* See the register description.
mbed_official	324:406fd2029f23	1032	*
mbed_official	324:406fd2029f23	1033	* Values:
mbed_official	324:406fd2029f23	1034	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	1035	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	1036	*/
mbed_official	324:406fd2029f23	1037	/@{/
mbed_official	324:406fd2029f23	1038	#define BP_FTM_STATUS_CH6F (6U) /!< Bit position for FTM_STATUS_CH6F. /
mbed_official	324:406fd2029f23	1039	#define BM_FTM_STATUS_CH6F (0x00000040U) /!< Bit mask for FTM_STATUS_CH6F. /
mbed_official	324:406fd2029f23	1040	#define BS_FTM_STATUS_CH6F (1U) /!< Bit field size in bits for FTM_STATUS_CH6F. /
mbed_official	324:406fd2029f23	1041
mbed_official	324:406fd2029f23	1042	/! @brief Read current value of the FTM_STATUS_CH6F field. /
mbed_official	324:406fd2029f23	1043	#define BR_FTM_STATUS_CH6F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F))
mbed_official	324:406fd2029f23	1044
mbed_official	324:406fd2029f23	1045	/! @brief Format value for bitfield FTM_STATUS_CH6F. /
mbed_official	324:406fd2029f23	1046	#define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
mbed_official	324:406fd2029f23	1047
mbed_official	324:406fd2029f23	1048	/! @brief Set the CH6F field to a new value. /
mbed_official	324:406fd2029f23	1049	#define BW_FTM_STATUS_CH6F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F) = (v))
mbed_official	324:406fd2029f23	1050	/@}/
mbed_official	324:406fd2029f23	1051
mbed_official	324:406fd2029f23	1052	/*!
mbed_official	324:406fd2029f23	1053	* @name Register FTM_STATUS, field CH7F[7] (W1C)
mbed_official	324:406fd2029f23	1054	*
mbed_official	324:406fd2029f23	1055	* See the register description.
mbed_official	324:406fd2029f23	1056	*
mbed_official	324:406fd2029f23	1057	* Values:
mbed_official	324:406fd2029f23	1058	* - 0 - No channel event has occurred.
mbed_official	324:406fd2029f23	1059	* - 1 - A channel event has occurred.
mbed_official	324:406fd2029f23	1060	*/
mbed_official	324:406fd2029f23	1061	/@{/
mbed_official	324:406fd2029f23	1062	#define BP_FTM_STATUS_CH7F (7U) /!< Bit position for FTM_STATUS_CH7F. /
mbed_official	324:406fd2029f23	1063	#define BM_FTM_STATUS_CH7F (0x00000080U) /!< Bit mask for FTM_STATUS_CH7F. /
mbed_official	324:406fd2029f23	1064	#define BS_FTM_STATUS_CH7F (1U) /!< Bit field size in bits for FTM_STATUS_CH7F. /
mbed_official	324:406fd2029f23	1065
mbed_official	324:406fd2029f23	1066	/! @brief Read current value of the FTM_STATUS_CH7F field. /
mbed_official	324:406fd2029f23	1067	#define BR_FTM_STATUS_CH7F(x) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F))
mbed_official	324:406fd2029f23	1068
mbed_official	324:406fd2029f23	1069	/! @brief Format value for bitfield FTM_STATUS_CH7F. /
mbed_official	324:406fd2029f23	1070	#define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
mbed_official	324:406fd2029f23	1071
mbed_official	324:406fd2029f23	1072	/! @brief Set the CH7F field to a new value. /
mbed_official	324:406fd2029f23	1073	#define BW_FTM_STATUS_CH7F(x, v) (BITBAND_ACCESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F) = (v))
mbed_official	324:406fd2029f23	1074	/@}/
mbed_official	324:406fd2029f23	1075
mbed_official	324:406fd2029f23	1076	/*******************************************************************************
mbed_official	324:406fd2029f23	1077	* HW_FTM_MODE - Features Mode Selection
mbed_official	324:406fd2029f23	1078	******************************************************************************/
mbed_official	324:406fd2029f23	1079
mbed_official	324:406fd2029f23	1080	/*!
mbed_official	324:406fd2029f23	1081	* @brief HW_FTM_MODE - Features Mode Selection (RW)
mbed_official	324:406fd2029f23	1082	*
mbed_official	324:406fd2029f23	1083	* Reset value: 0x00000004U
mbed_official	324:406fd2029f23	1084	*
mbed_official	324:406fd2029f23	1085	* This register contains the global enable bit for FTM-specific features and
mbed_official	324:406fd2029f23	1086	* the control bits used to configure: Fault control mode and interrupt Capture
mbed_official	324:406fd2029f23	1087	* Test mode PWM synchronization Write protection Channel output initialization
mbed_official	324:406fd2029f23	1088	* These controls relate to all channels within this module.
mbed_official	324:406fd2029f23	1089	*/
mbed_official	324:406fd2029f23	1090	typedef union _hw_ftm_mode
mbed_official	324:406fd2029f23	1091	{
mbed_official	324:406fd2029f23	1092	uint32_t U;
mbed_official	324:406fd2029f23	1093	struct _hw_ftm_mode_bitfields
mbed_official	324:406fd2029f23	1094	{
mbed_official	324:406fd2029f23	1095	uint32_t FTMEN : 1; /!< [0] FTM Enable /
mbed_official	324:406fd2029f23	1096	uint32_t INIT : 1; /!< [1] Initialize The Channels Output /
mbed_official	324:406fd2029f23	1097	uint32_t WPDIS : 1; /!< [2] Write Protection Disable /
mbed_official	324:406fd2029f23	1098	uint32_t PWMSYNC : 1; /!< [3] PWM Synchronization Mode /
mbed_official	324:406fd2029f23	1099	uint32_t CAPTEST : 1; /!< [4] Capture Test Mode Enable /
mbed_official	324:406fd2029f23	1100	uint32_t FAULTM : 2; /!< [6:5] Fault Control Mode /
mbed_official	324:406fd2029f23	1101	uint32_t FAULTIE : 1; /!< [7] Fault Interrupt Enable /
mbed_official	324:406fd2029f23	1102	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1103	} B;
mbed_official	324:406fd2029f23	1104	} hw_ftm_mode_t;
mbed_official	324:406fd2029f23	1105
mbed_official	324:406fd2029f23	1106	/*!
mbed_official	324:406fd2029f23	1107	* @name Constants and macros for entire FTM_MODE register
mbed_official	324:406fd2029f23	1108	*/
mbed_official	324:406fd2029f23	1109	/@{/
mbed_official	324:406fd2029f23	1110	#define HW_FTM_MODE_ADDR(x) ((x) + 0x54U)
mbed_official	324:406fd2029f23	1111
mbed_official	324:406fd2029f23	1112	#define HW_FTM_MODE(x) ((__IO hw_ftm_mode_t ) HW_FTM_MODE_ADDR(x))
mbed_official	324:406fd2029f23	1113	#define HW_FTM_MODE_RD(x) (HW_FTM_MODE(x).U)
mbed_official	324:406fd2029f23	1114	#define HW_FTM_MODE_WR(x, v) (HW_FTM_MODE(x).U = (v))
mbed_official	324:406fd2029f23	1115	#define HW_FTM_MODE_SET(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1116	#define HW_FTM_MODE_CLR(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1117	#define HW_FTM_MODE_TOG(x, v) (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1118	/@}/
mbed_official	324:406fd2029f23	1119
mbed_official	324:406fd2029f23	1120	/*
mbed_official	324:406fd2029f23	1121	* Constants & macros for individual FTM_MODE bitfields
mbed_official	324:406fd2029f23	1122	*/
mbed_official	324:406fd2029f23	1123
mbed_official	324:406fd2029f23	1124	/*!
mbed_official	324:406fd2029f23	1125	* @name Register FTM_MODE, field FTMEN[0] (RW)
mbed_official	324:406fd2029f23	1126	*
mbed_official	324:406fd2029f23	1127	* This field is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	1128	*
mbed_official	324:406fd2029f23	1129	* Values:
mbed_official	324:406fd2029f23	1130	* - 0 - Only the TPM-compatible registers (first set of registers) can be used
mbed_official	324:406fd2029f23	1131	* without any restriction. Do not use the FTM-specific registers.
mbed_official	324:406fd2029f23	1132	* - 1 - All registers including the FTM-specific registers (second set of
mbed_official	324:406fd2029f23	1133	* registers) are available for use with no restrictions.
mbed_official	324:406fd2029f23	1134	*/
mbed_official	324:406fd2029f23	1135	/@{/
mbed_official	324:406fd2029f23	1136	#define BP_FTM_MODE_FTMEN (0U) /!< Bit position for FTM_MODE_FTMEN. /
mbed_official	324:406fd2029f23	1137	#define BM_FTM_MODE_FTMEN (0x00000001U) /!< Bit mask for FTM_MODE_FTMEN. /
mbed_official	324:406fd2029f23	1138	#define BS_FTM_MODE_FTMEN (1U) /!< Bit field size in bits for FTM_MODE_FTMEN. /
mbed_official	324:406fd2029f23	1139
mbed_official	324:406fd2029f23	1140	/! @brief Read current value of the FTM_MODE_FTMEN field. /
mbed_official	324:406fd2029f23	1141	#define BR_FTM_MODE_FTMEN(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN))
mbed_official	324:406fd2029f23	1142
mbed_official	324:406fd2029f23	1143	/! @brief Format value for bitfield FTM_MODE_FTMEN. /
mbed_official	324:406fd2029f23	1144	#define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
mbed_official	324:406fd2029f23	1145
mbed_official	324:406fd2029f23	1146	/! @brief Set the FTMEN field to a new value. /
mbed_official	324:406fd2029f23	1147	#define BW_FTM_MODE_FTMEN(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN) = (v))
mbed_official	324:406fd2029f23	1148	/@}/
mbed_official	324:406fd2029f23	1149
mbed_official	324:406fd2029f23	1150	/*!
mbed_official	324:406fd2029f23	1151	* @name Register FTM_MODE, field INIT[1] (RW)
mbed_official	324:406fd2029f23	1152	*
mbed_official	324:406fd2029f23	1153	* When a 1 is written to INIT bit the channels output is initialized according
mbed_official	324:406fd2029f23	1154	* to the state of their corresponding bit in the OUTINIT register. Writing a 0
mbed_official	324:406fd2029f23	1155	* to INIT bit has no effect. The INIT bit is always read as 0.
mbed_official	324:406fd2029f23	1156	*/
mbed_official	324:406fd2029f23	1157	/@{/
mbed_official	324:406fd2029f23	1158	#define BP_FTM_MODE_INIT (1U) /!< Bit position for FTM_MODE_INIT. /
mbed_official	324:406fd2029f23	1159	#define BM_FTM_MODE_INIT (0x00000002U) /!< Bit mask for FTM_MODE_INIT. /
mbed_official	324:406fd2029f23	1160	#define BS_FTM_MODE_INIT (1U) /!< Bit field size in bits for FTM_MODE_INIT. /
mbed_official	324:406fd2029f23	1161
mbed_official	324:406fd2029f23	1162	/! @brief Read current value of the FTM_MODE_INIT field. /
mbed_official	324:406fd2029f23	1163	#define BR_FTM_MODE_INIT(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT))
mbed_official	324:406fd2029f23	1164
mbed_official	324:406fd2029f23	1165	/! @brief Format value for bitfield FTM_MODE_INIT. /
mbed_official	324:406fd2029f23	1166	#define BF_FTM_MODE_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
mbed_official	324:406fd2029f23	1167
mbed_official	324:406fd2029f23	1168	/! @brief Set the INIT field to a new value. /
mbed_official	324:406fd2029f23	1169	#define BW_FTM_MODE_INIT(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT) = (v))
mbed_official	324:406fd2029f23	1170	/@}/
mbed_official	324:406fd2029f23	1171
mbed_official	324:406fd2029f23	1172	/*!
mbed_official	324:406fd2029f23	1173	* @name Register FTM_MODE, field WPDIS[2] (RW)
mbed_official	324:406fd2029f23	1174	*
mbed_official	324:406fd2029f23	1175	* When write protection is enabled (WPDIS = 0), write protected bits cannot be
mbed_official	324:406fd2029f23	1176	* written. When write protection is disabled (WPDIS = 1), write protected bits
mbed_official	324:406fd2029f23	1177	* can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
mbed_official	324:406fd2029f23	1178	* when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
mbed_official	324:406fd2029f23	1179	* 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
mbed_official	324:406fd2029f23	1180	*
mbed_official	324:406fd2029f23	1181	* Values:
mbed_official	324:406fd2029f23	1182	* - 0 - Write protection is enabled.
mbed_official	324:406fd2029f23	1183	* - 1 - Write protection is disabled.
mbed_official	324:406fd2029f23	1184	*/
mbed_official	324:406fd2029f23	1185	/@{/
mbed_official	324:406fd2029f23	1186	#define BP_FTM_MODE_WPDIS (2U) /!< Bit position for FTM_MODE_WPDIS. /
mbed_official	324:406fd2029f23	1187	#define BM_FTM_MODE_WPDIS (0x00000004U) /!< Bit mask for FTM_MODE_WPDIS. /
mbed_official	324:406fd2029f23	1188	#define BS_FTM_MODE_WPDIS (1U) /!< Bit field size in bits for FTM_MODE_WPDIS. /
mbed_official	324:406fd2029f23	1189
mbed_official	324:406fd2029f23	1190	/! @brief Read current value of the FTM_MODE_WPDIS field. /
mbed_official	324:406fd2029f23	1191	#define BR_FTM_MODE_WPDIS(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS))
mbed_official	324:406fd2029f23	1192
mbed_official	324:406fd2029f23	1193	/! @brief Format value for bitfield FTM_MODE_WPDIS. /
mbed_official	324:406fd2029f23	1194	#define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
mbed_official	324:406fd2029f23	1195
mbed_official	324:406fd2029f23	1196	/! @brief Set the WPDIS field to a new value. /
mbed_official	324:406fd2029f23	1197	#define BW_FTM_MODE_WPDIS(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS) = (v))
mbed_official	324:406fd2029f23	1198	/@}/
mbed_official	324:406fd2029f23	1199
mbed_official	324:406fd2029f23	1200	/*!
mbed_official	324:406fd2029f23	1201	* @name Register FTM_MODE, field PWMSYNC[3] (RW)
mbed_official	324:406fd2029f23	1202	*
mbed_official	324:406fd2029f23	1203	* Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
mbed_official	324:406fd2029f23	1204	* synchronization. See PWM synchronization. The PWMSYNC bit configures the
mbed_official	324:406fd2029f23	1205	* synchronization when SYNCMODE is 0.
mbed_official	324:406fd2029f23	1206	*
mbed_official	324:406fd2029f23	1207	* Values:
mbed_official	324:406fd2029f23	1208	* - 0 - No restrictions. Software and hardware triggers can be used by MOD,
mbed_official	324:406fd2029f23	1209	* CnV, OUTMASK, and FTM counter synchronization.
mbed_official	324:406fd2029f23	1210	* - 1 - Software trigger can only be used by MOD and CnV synchronization, and
mbed_official	324:406fd2029f23	1211	* hardware triggers can only be used by OUTMASK and FTM counter
mbed_official	324:406fd2029f23	1212	* synchronization.
mbed_official	324:406fd2029f23	1213	*/
mbed_official	324:406fd2029f23	1214	/@{/
mbed_official	324:406fd2029f23	1215	#define BP_FTM_MODE_PWMSYNC (3U) /!< Bit position for FTM_MODE_PWMSYNC. /
mbed_official	324:406fd2029f23	1216	#define BM_FTM_MODE_PWMSYNC (0x00000008U) /!< Bit mask for FTM_MODE_PWMSYNC. /
mbed_official	324:406fd2029f23	1217	#define BS_FTM_MODE_PWMSYNC (1U) /!< Bit field size in bits for FTM_MODE_PWMSYNC. /
mbed_official	324:406fd2029f23	1218
mbed_official	324:406fd2029f23	1219	/! @brief Read current value of the FTM_MODE_PWMSYNC field. /
mbed_official	324:406fd2029f23	1220	#define BR_FTM_MODE_PWMSYNC(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC))
mbed_official	324:406fd2029f23	1221
mbed_official	324:406fd2029f23	1222	/! @brief Format value for bitfield FTM_MODE_PWMSYNC. /
mbed_official	324:406fd2029f23	1223	#define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
mbed_official	324:406fd2029f23	1224
mbed_official	324:406fd2029f23	1225	/! @brief Set the PWMSYNC field to a new value. /
mbed_official	324:406fd2029f23	1226	#define BW_FTM_MODE_PWMSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC) = (v))
mbed_official	324:406fd2029f23	1227	/@}/
mbed_official	324:406fd2029f23	1228
mbed_official	324:406fd2029f23	1229	/*!
mbed_official	324:406fd2029f23	1230	* @name Register FTM_MODE, field CAPTEST[4] (RW)
mbed_official	324:406fd2029f23	1231	*
mbed_official	324:406fd2029f23	1232	* Enables the capture test mode. This field is write protected. It can be
mbed_official	324:406fd2029f23	1233	* written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	1234	*
mbed_official	324:406fd2029f23	1235	* Values:
mbed_official	324:406fd2029f23	1236	* - 0 - Capture test mode is disabled.
mbed_official	324:406fd2029f23	1237	* - 1 - Capture test mode is enabled.
mbed_official	324:406fd2029f23	1238	*/
mbed_official	324:406fd2029f23	1239	/@{/
mbed_official	324:406fd2029f23	1240	#define BP_FTM_MODE_CAPTEST (4U) /!< Bit position for FTM_MODE_CAPTEST. /
mbed_official	324:406fd2029f23	1241	#define BM_FTM_MODE_CAPTEST (0x00000010U) /!< Bit mask for FTM_MODE_CAPTEST. /
mbed_official	324:406fd2029f23	1242	#define BS_FTM_MODE_CAPTEST (1U) /!< Bit field size in bits for FTM_MODE_CAPTEST. /
mbed_official	324:406fd2029f23	1243
mbed_official	324:406fd2029f23	1244	/! @brief Read current value of the FTM_MODE_CAPTEST field. /
mbed_official	324:406fd2029f23	1245	#define BR_FTM_MODE_CAPTEST(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST))
mbed_official	324:406fd2029f23	1246
mbed_official	324:406fd2029f23	1247	/! @brief Format value for bitfield FTM_MODE_CAPTEST. /
mbed_official	324:406fd2029f23	1248	#define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
mbed_official	324:406fd2029f23	1249
mbed_official	324:406fd2029f23	1250	/! @brief Set the CAPTEST field to a new value. /
mbed_official	324:406fd2029f23	1251	#define BW_FTM_MODE_CAPTEST(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST) = (v))
mbed_official	324:406fd2029f23	1252	/@}/
mbed_official	324:406fd2029f23	1253
mbed_official	324:406fd2029f23	1254	/*!
mbed_official	324:406fd2029f23	1255	* @name Register FTM_MODE, field FAULTM[6:5] (RW)
mbed_official	324:406fd2029f23	1256	*
mbed_official	324:406fd2029f23	1257	* Defines the FTM fault control mode. This field is write protected. It can be
mbed_official	324:406fd2029f23	1258	* written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	1259	*
mbed_official	324:406fd2029f23	1260	* Values:
mbed_official	324:406fd2029f23	1261	* - 00 - Fault control is disabled for all channels.
mbed_official	324:406fd2029f23	1262	* - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
mbed_official	324:406fd2029f23	1263	* 6), and the selected mode is the manual fault clearing.
mbed_official	324:406fd2029f23	1264	* - 10 - Fault control is enabled for all channels, and the selected mode is
mbed_official	324:406fd2029f23	1265	* the manual fault clearing.
mbed_official	324:406fd2029f23	1266	* - 11 - Fault control is enabled for all channels, and the selected mode is
mbed_official	324:406fd2029f23	1267	* the automatic fault clearing.
mbed_official	324:406fd2029f23	1268	*/
mbed_official	324:406fd2029f23	1269	/@{/
mbed_official	324:406fd2029f23	1270	#define BP_FTM_MODE_FAULTM (5U) /!< Bit position for FTM_MODE_FAULTM. /
mbed_official	324:406fd2029f23	1271	#define BM_FTM_MODE_FAULTM (0x00000060U) /!< Bit mask for FTM_MODE_FAULTM. /
mbed_official	324:406fd2029f23	1272	#define BS_FTM_MODE_FAULTM (2U) /!< Bit field size in bits for FTM_MODE_FAULTM. /
mbed_official	324:406fd2029f23	1273
mbed_official	324:406fd2029f23	1274	/! @brief Read current value of the FTM_MODE_FAULTM field. /
mbed_official	324:406fd2029f23	1275	#define BR_FTM_MODE_FAULTM(x) (HW_FTM_MODE(x).B.FAULTM)
mbed_official	324:406fd2029f23	1276
mbed_official	324:406fd2029f23	1277	/! @brief Format value for bitfield FTM_MODE_FAULTM. /
mbed_official	324:406fd2029f23	1278	#define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
mbed_official	324:406fd2029f23	1279
mbed_official	324:406fd2029f23	1280	/! @brief Set the FAULTM field to a new value. /
mbed_official	324:406fd2029f23	1281	#define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) \| BF_FTM_MODE_FAULTM(v)))
mbed_official	324:406fd2029f23	1282	/@}/
mbed_official	324:406fd2029f23	1283
mbed_official	324:406fd2029f23	1284	/*!
mbed_official	324:406fd2029f23	1285	* @name Register FTM_MODE, field FAULTIE[7] (RW)
mbed_official	324:406fd2029f23	1286	*
mbed_official	324:406fd2029f23	1287	* Enables the generation of an interrupt when a fault is detected by FTM and
mbed_official	324:406fd2029f23	1288	* the FTM fault control is enabled.
mbed_official	324:406fd2029f23	1289	*
mbed_official	324:406fd2029f23	1290	* Values:
mbed_official	324:406fd2029f23	1291	* - 0 - Fault control interrupt is disabled.
mbed_official	324:406fd2029f23	1292	* - 1 - Fault control interrupt is enabled.
mbed_official	324:406fd2029f23	1293	*/
mbed_official	324:406fd2029f23	1294	/@{/
mbed_official	324:406fd2029f23	1295	#define BP_FTM_MODE_FAULTIE (7U) /!< Bit position for FTM_MODE_FAULTIE. /
mbed_official	324:406fd2029f23	1296	#define BM_FTM_MODE_FAULTIE (0x00000080U) /!< Bit mask for FTM_MODE_FAULTIE. /
mbed_official	324:406fd2029f23	1297	#define BS_FTM_MODE_FAULTIE (1U) /!< Bit field size in bits for FTM_MODE_FAULTIE. /
mbed_official	324:406fd2029f23	1298
mbed_official	324:406fd2029f23	1299	/! @brief Read current value of the FTM_MODE_FAULTIE field. /
mbed_official	324:406fd2029f23	1300	#define BR_FTM_MODE_FAULTIE(x) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE))
mbed_official	324:406fd2029f23	1301
mbed_official	324:406fd2029f23	1302	/! @brief Format value for bitfield FTM_MODE_FAULTIE. /
mbed_official	324:406fd2029f23	1303	#define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
mbed_official	324:406fd2029f23	1304
mbed_official	324:406fd2029f23	1305	/! @brief Set the FAULTIE field to a new value. /
mbed_official	324:406fd2029f23	1306	#define BW_FTM_MODE_FAULTIE(x, v) (BITBAND_ACCESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE) = (v))
mbed_official	324:406fd2029f23	1307	/@}/
mbed_official	324:406fd2029f23	1308
mbed_official	324:406fd2029f23	1309	/*******************************************************************************
mbed_official	324:406fd2029f23	1310	* HW_FTM_SYNC - Synchronization
mbed_official	324:406fd2029f23	1311	******************************************************************************/
mbed_official	324:406fd2029f23	1312
mbed_official	324:406fd2029f23	1313	/*!
mbed_official	324:406fd2029f23	1314	* @brief HW_FTM_SYNC - Synchronization (RW)
mbed_official	324:406fd2029f23	1315	*
mbed_official	324:406fd2029f23	1316	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1317	*
mbed_official	324:406fd2029f23	1318	* This register configures the PWM synchronization. A synchronization event can
mbed_official	324:406fd2029f23	1319	* perform the synchronized update of MOD, CV, and OUTMASK registers with the
mbed_official	324:406fd2029f23	1320	* value of their write buffer and the FTM counter initialization. The software
mbed_official	324:406fd2029f23	1321	* trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
mbed_official	324:406fd2029f23	1322	* potential conflict if used together when SYNCMODE = 0. Use only hardware or
mbed_official	324:406fd2029f23	1323	* software triggers but not both at the same time, otherwise unpredictable behavior
mbed_official	324:406fd2029f23	1324	* is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
mbed_official	324:406fd2029f23	1325	* bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
mbed_official	324:406fd2029f23	1326	* all enabled channels simultaneously. The use of the loading point selection
mbed_official	324:406fd2029f23	1327	* together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
mbed_official	324:406fd2029f23	1328	* bits, is likely to result in unpredictable behavior. The synchronization
mbed_official	324:406fd2029f23	1329	* event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
mbed_official	324:406fd2029f23	1330	* register) bits. See PWM synchronization.
mbed_official	324:406fd2029f23	1331	*/
mbed_official	324:406fd2029f23	1332	typedef union _hw_ftm_sync
mbed_official	324:406fd2029f23	1333	{
mbed_official	324:406fd2029f23	1334	uint32_t U;
mbed_official	324:406fd2029f23	1335	struct _hw_ftm_sync_bitfields
mbed_official	324:406fd2029f23	1336	{
mbed_official	324:406fd2029f23	1337	uint32_t CNTMIN : 1; /!< [0] Minimum Loading Point Enable /
mbed_official	324:406fd2029f23	1338	uint32_t CNTMAX : 1; /!< [1] Maximum Loading Point Enable /
mbed_official	324:406fd2029f23	1339	uint32_t REINIT : 1; /*!< [2] FTM Counter Reinitialization By
mbed_official	324:406fd2029f23	1340	* Synchronization (FTM counter synchronization) */
mbed_official	324:406fd2029f23	1341	uint32_t SYNCHOM : 1; /!< [3] Output Mask Synchronization /
mbed_official	324:406fd2029f23	1342	uint32_t TRIG0 : 1; /!< [4] PWM Synchronization Hardware Trigger 0 /
mbed_official	324:406fd2029f23	1343	uint32_t TRIG1 : 1; /!< [5] PWM Synchronization Hardware Trigger 1 /
mbed_official	324:406fd2029f23	1344	uint32_t TRIG2 : 1; /!< [6] PWM Synchronization Hardware Trigger 2 /
mbed_official	324:406fd2029f23	1345	uint32_t SWSYNC : 1; /!< [7] PWM Synchronization Software Trigger /
mbed_official	324:406fd2029f23	1346	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1347	} B;
mbed_official	324:406fd2029f23	1348	} hw_ftm_sync_t;
mbed_official	324:406fd2029f23	1349
mbed_official	324:406fd2029f23	1350	/*!
mbed_official	324:406fd2029f23	1351	* @name Constants and macros for entire FTM_SYNC register
mbed_official	324:406fd2029f23	1352	*/
mbed_official	324:406fd2029f23	1353	/@{/
mbed_official	324:406fd2029f23	1354	#define HW_FTM_SYNC_ADDR(x) ((x) + 0x58U)
mbed_official	324:406fd2029f23	1355
mbed_official	324:406fd2029f23	1356	#define HW_FTM_SYNC(x) ((__IO hw_ftm_sync_t ) HW_FTM_SYNC_ADDR(x))
mbed_official	324:406fd2029f23	1357	#define HW_FTM_SYNC_RD(x) (HW_FTM_SYNC(x).U)
mbed_official	324:406fd2029f23	1358	#define HW_FTM_SYNC_WR(x, v) (HW_FTM_SYNC(x).U = (v))
mbed_official	324:406fd2029f23	1359	#define HW_FTM_SYNC_SET(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1360	#define HW_FTM_SYNC_CLR(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1361	#define HW_FTM_SYNC_TOG(x, v) (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1362	/@}/
mbed_official	324:406fd2029f23	1363
mbed_official	324:406fd2029f23	1364	/*
mbed_official	324:406fd2029f23	1365	* Constants & macros for individual FTM_SYNC bitfields
mbed_official	324:406fd2029f23	1366	*/
mbed_official	324:406fd2029f23	1367
mbed_official	324:406fd2029f23	1368	/*!
mbed_official	324:406fd2029f23	1369	* @name Register FTM_SYNC, field CNTMIN[0] (RW)
mbed_official	324:406fd2029f23	1370	*
mbed_official	324:406fd2029f23	1371	* Selects the minimum loading point to PWM synchronization. See Boundary cycle
mbed_official	324:406fd2029f23	1372	* and loading points. If CNTMIN is one, the selected loading point is when the
mbed_official	324:406fd2029f23	1373	* FTM counter reaches its minimum value (CNTIN register).
mbed_official	324:406fd2029f23	1374	*
mbed_official	324:406fd2029f23	1375	* Values:
mbed_official	324:406fd2029f23	1376	* - 0 - The minimum loading point is disabled.
mbed_official	324:406fd2029f23	1377	* - 1 - The minimum loading point is enabled.
mbed_official	324:406fd2029f23	1378	*/
mbed_official	324:406fd2029f23	1379	/@{/
mbed_official	324:406fd2029f23	1380	#define BP_FTM_SYNC_CNTMIN (0U) /!< Bit position for FTM_SYNC_CNTMIN. /
mbed_official	324:406fd2029f23	1381	#define BM_FTM_SYNC_CNTMIN (0x00000001U) /!< Bit mask for FTM_SYNC_CNTMIN. /
mbed_official	324:406fd2029f23	1382	#define BS_FTM_SYNC_CNTMIN (1U) /!< Bit field size in bits for FTM_SYNC_CNTMIN. /
mbed_official	324:406fd2029f23	1383
mbed_official	324:406fd2029f23	1384	/! @brief Read current value of the FTM_SYNC_CNTMIN field. /
mbed_official	324:406fd2029f23	1385	#define BR_FTM_SYNC_CNTMIN(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN))
mbed_official	324:406fd2029f23	1386
mbed_official	324:406fd2029f23	1387	/! @brief Format value for bitfield FTM_SYNC_CNTMIN. /
mbed_official	324:406fd2029f23	1388	#define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
mbed_official	324:406fd2029f23	1389
mbed_official	324:406fd2029f23	1390	/! @brief Set the CNTMIN field to a new value. /
mbed_official	324:406fd2029f23	1391	#define BW_FTM_SYNC_CNTMIN(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN) = (v))
mbed_official	324:406fd2029f23	1392	/@}/
mbed_official	324:406fd2029f23	1393
mbed_official	324:406fd2029f23	1394	/*!
mbed_official	324:406fd2029f23	1395	* @name Register FTM_SYNC, field CNTMAX[1] (RW)
mbed_official	324:406fd2029f23	1396	*
mbed_official	324:406fd2029f23	1397	* Selects the maximum loading point to PWM synchronization. See Boundary cycle
mbed_official	324:406fd2029f23	1398	* and loading points. If CNTMAX is 1, the selected loading point is when the FTM
mbed_official	324:406fd2029f23	1399	* counter reaches its maximum value (MOD register).
mbed_official	324:406fd2029f23	1400	*
mbed_official	324:406fd2029f23	1401	* Values:
mbed_official	324:406fd2029f23	1402	* - 0 - The maximum loading point is disabled.
mbed_official	324:406fd2029f23	1403	* - 1 - The maximum loading point is enabled.
mbed_official	324:406fd2029f23	1404	*/
mbed_official	324:406fd2029f23	1405	/@{/
mbed_official	324:406fd2029f23	1406	#define BP_FTM_SYNC_CNTMAX (1U) /!< Bit position for FTM_SYNC_CNTMAX. /
mbed_official	324:406fd2029f23	1407	#define BM_FTM_SYNC_CNTMAX (0x00000002U) /!< Bit mask for FTM_SYNC_CNTMAX. /
mbed_official	324:406fd2029f23	1408	#define BS_FTM_SYNC_CNTMAX (1U) /!< Bit field size in bits for FTM_SYNC_CNTMAX. /
mbed_official	324:406fd2029f23	1409
mbed_official	324:406fd2029f23	1410	/! @brief Read current value of the FTM_SYNC_CNTMAX field. /
mbed_official	324:406fd2029f23	1411	#define BR_FTM_SYNC_CNTMAX(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX))
mbed_official	324:406fd2029f23	1412
mbed_official	324:406fd2029f23	1413	/! @brief Format value for bitfield FTM_SYNC_CNTMAX. /
mbed_official	324:406fd2029f23	1414	#define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
mbed_official	324:406fd2029f23	1415
mbed_official	324:406fd2029f23	1416	/! @brief Set the CNTMAX field to a new value. /
mbed_official	324:406fd2029f23	1417	#define BW_FTM_SYNC_CNTMAX(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX) = (v))
mbed_official	324:406fd2029f23	1418	/@}/
mbed_official	324:406fd2029f23	1419
mbed_official	324:406fd2029f23	1420	/*!
mbed_official	324:406fd2029f23	1421	* @name Register FTM_SYNC, field REINIT[2] (RW)
mbed_official	324:406fd2029f23	1422	*
mbed_official	324:406fd2029f23	1423	* Determines if the FTM counter is reinitialized when the selected trigger for
mbed_official	324:406fd2029f23	1424	* the synchronization is detected. The REINIT bit configures the synchronization
mbed_official	324:406fd2029f23	1425	* when SYNCMODE is zero.
mbed_official	324:406fd2029f23	1426	*
mbed_official	324:406fd2029f23	1427	* Values:
mbed_official	324:406fd2029f23	1428	* - 0 - FTM counter continues to count normally.
mbed_official	324:406fd2029f23	1429	* - 1 - FTM counter is updated with its initial value when the selected trigger
mbed_official	324:406fd2029f23	1430	* is detected.
mbed_official	324:406fd2029f23	1431	*/
mbed_official	324:406fd2029f23	1432	/@{/
mbed_official	324:406fd2029f23	1433	#define BP_FTM_SYNC_REINIT (2U) /!< Bit position for FTM_SYNC_REINIT. /
mbed_official	324:406fd2029f23	1434	#define BM_FTM_SYNC_REINIT (0x00000004U) /!< Bit mask for FTM_SYNC_REINIT. /
mbed_official	324:406fd2029f23	1435	#define BS_FTM_SYNC_REINIT (1U) /!< Bit field size in bits for FTM_SYNC_REINIT. /
mbed_official	324:406fd2029f23	1436
mbed_official	324:406fd2029f23	1437	/! @brief Read current value of the FTM_SYNC_REINIT field. /
mbed_official	324:406fd2029f23	1438	#define BR_FTM_SYNC_REINIT(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT))
mbed_official	324:406fd2029f23	1439
mbed_official	324:406fd2029f23	1440	/! @brief Format value for bitfield FTM_SYNC_REINIT. /
mbed_official	324:406fd2029f23	1441	#define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
mbed_official	324:406fd2029f23	1442
mbed_official	324:406fd2029f23	1443	/! @brief Set the REINIT field to a new value. /
mbed_official	324:406fd2029f23	1444	#define BW_FTM_SYNC_REINIT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT) = (v))
mbed_official	324:406fd2029f23	1445	/@}/
mbed_official	324:406fd2029f23	1446
mbed_official	324:406fd2029f23	1447	/*!
mbed_official	324:406fd2029f23	1448	* @name Register FTM_SYNC, field SYNCHOM[3] (RW)
mbed_official	324:406fd2029f23	1449	*
mbed_official	324:406fd2029f23	1450	* Selects when the OUTMASK register is updated with the value of its buffer.
mbed_official	324:406fd2029f23	1451	*
mbed_official	324:406fd2029f23	1452	* Values:
mbed_official	324:406fd2029f23	1453	* - 0 - OUTMASK register is updated with the value of its buffer in all rising
mbed_official	324:406fd2029f23	1454	* edges of the system clock.
mbed_official	324:406fd2029f23	1455	* - 1 - OUTMASK register is updated with the value of its buffer only by the
mbed_official	324:406fd2029f23	1456	* PWM synchronization.
mbed_official	324:406fd2029f23	1457	*/
mbed_official	324:406fd2029f23	1458	/@{/
mbed_official	324:406fd2029f23	1459	#define BP_FTM_SYNC_SYNCHOM (3U) /!< Bit position for FTM_SYNC_SYNCHOM. /
mbed_official	324:406fd2029f23	1460	#define BM_FTM_SYNC_SYNCHOM (0x00000008U) /!< Bit mask for FTM_SYNC_SYNCHOM. /
mbed_official	324:406fd2029f23	1461	#define BS_FTM_SYNC_SYNCHOM (1U) /!< Bit field size in bits for FTM_SYNC_SYNCHOM. /
mbed_official	324:406fd2029f23	1462
mbed_official	324:406fd2029f23	1463	/! @brief Read current value of the FTM_SYNC_SYNCHOM field. /
mbed_official	324:406fd2029f23	1464	#define BR_FTM_SYNC_SYNCHOM(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM))
mbed_official	324:406fd2029f23	1465
mbed_official	324:406fd2029f23	1466	/! @brief Format value for bitfield FTM_SYNC_SYNCHOM. /
mbed_official	324:406fd2029f23	1467	#define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
mbed_official	324:406fd2029f23	1468
mbed_official	324:406fd2029f23	1469	/! @brief Set the SYNCHOM field to a new value. /
mbed_official	324:406fd2029f23	1470	#define BW_FTM_SYNC_SYNCHOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM) = (v))
mbed_official	324:406fd2029f23	1471	/@}/
mbed_official	324:406fd2029f23	1472
mbed_official	324:406fd2029f23	1473	/*!
mbed_official	324:406fd2029f23	1474	* @name Register FTM_SYNC, field TRIG0[4] (RW)
mbed_official	324:406fd2029f23	1475	*
mbed_official	324:406fd2029f23	1476	* Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
mbed_official	324:406fd2029f23	1477	* occurs when a rising edge is detected at the trigger 0 input signal.
mbed_official	324:406fd2029f23	1478	*
mbed_official	324:406fd2029f23	1479	* Values:
mbed_official	324:406fd2029f23	1480	* - 0 - Trigger is disabled.
mbed_official	324:406fd2029f23	1481	* - 1 - Trigger is enabled.
mbed_official	324:406fd2029f23	1482	*/
mbed_official	324:406fd2029f23	1483	/@{/
mbed_official	324:406fd2029f23	1484	#define BP_FTM_SYNC_TRIG0 (4U) /!< Bit position for FTM_SYNC_TRIG0. /
mbed_official	324:406fd2029f23	1485	#define BM_FTM_SYNC_TRIG0 (0x00000010U) /!< Bit mask for FTM_SYNC_TRIG0. /
mbed_official	324:406fd2029f23	1486	#define BS_FTM_SYNC_TRIG0 (1U) /!< Bit field size in bits for FTM_SYNC_TRIG0. /
mbed_official	324:406fd2029f23	1487
mbed_official	324:406fd2029f23	1488	/! @brief Read current value of the FTM_SYNC_TRIG0 field. /
mbed_official	324:406fd2029f23	1489	#define BR_FTM_SYNC_TRIG0(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0))
mbed_official	324:406fd2029f23	1490
mbed_official	324:406fd2029f23	1491	/! @brief Format value for bitfield FTM_SYNC_TRIG0. /
mbed_official	324:406fd2029f23	1492	#define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
mbed_official	324:406fd2029f23	1493
mbed_official	324:406fd2029f23	1494	/! @brief Set the TRIG0 field to a new value. /
mbed_official	324:406fd2029f23	1495	#define BW_FTM_SYNC_TRIG0(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0) = (v))
mbed_official	324:406fd2029f23	1496	/@}/
mbed_official	324:406fd2029f23	1497
mbed_official	324:406fd2029f23	1498	/*!
mbed_official	324:406fd2029f23	1499	* @name Register FTM_SYNC, field TRIG1[5] (RW)
mbed_official	324:406fd2029f23	1500	*
mbed_official	324:406fd2029f23	1501	* Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
mbed_official	324:406fd2029f23	1502	* happens when a rising edge is detected at the trigger 1 input signal.
mbed_official	324:406fd2029f23	1503	*
mbed_official	324:406fd2029f23	1504	* Values:
mbed_official	324:406fd2029f23	1505	* - 0 - Trigger is disabled.
mbed_official	324:406fd2029f23	1506	* - 1 - Trigger is enabled.
mbed_official	324:406fd2029f23	1507	*/
mbed_official	324:406fd2029f23	1508	/@{/
mbed_official	324:406fd2029f23	1509	#define BP_FTM_SYNC_TRIG1 (5U) /!< Bit position for FTM_SYNC_TRIG1. /
mbed_official	324:406fd2029f23	1510	#define BM_FTM_SYNC_TRIG1 (0x00000020U) /!< Bit mask for FTM_SYNC_TRIG1. /
mbed_official	324:406fd2029f23	1511	#define BS_FTM_SYNC_TRIG1 (1U) /!< Bit field size in bits for FTM_SYNC_TRIG1. /
mbed_official	324:406fd2029f23	1512
mbed_official	324:406fd2029f23	1513	/! @brief Read current value of the FTM_SYNC_TRIG1 field. /
mbed_official	324:406fd2029f23	1514	#define BR_FTM_SYNC_TRIG1(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1))
mbed_official	324:406fd2029f23	1515
mbed_official	324:406fd2029f23	1516	/! @brief Format value for bitfield FTM_SYNC_TRIG1. /
mbed_official	324:406fd2029f23	1517	#define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
mbed_official	324:406fd2029f23	1518
mbed_official	324:406fd2029f23	1519	/! @brief Set the TRIG1 field to a new value. /
mbed_official	324:406fd2029f23	1520	#define BW_FTM_SYNC_TRIG1(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1) = (v))
mbed_official	324:406fd2029f23	1521	/@}/
mbed_official	324:406fd2029f23	1522
mbed_official	324:406fd2029f23	1523	/*!
mbed_official	324:406fd2029f23	1524	* @name Register FTM_SYNC, field TRIG2[6] (RW)
mbed_official	324:406fd2029f23	1525	*
mbed_official	324:406fd2029f23	1526	* Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
mbed_official	324:406fd2029f23	1527	* happens when a rising edge is detected at the trigger 2 input signal.
mbed_official	324:406fd2029f23	1528	*
mbed_official	324:406fd2029f23	1529	* Values:
mbed_official	324:406fd2029f23	1530	* - 0 - Trigger is disabled.
mbed_official	324:406fd2029f23	1531	* - 1 - Trigger is enabled.
mbed_official	324:406fd2029f23	1532	*/
mbed_official	324:406fd2029f23	1533	/@{/
mbed_official	324:406fd2029f23	1534	#define BP_FTM_SYNC_TRIG2 (6U) /!< Bit position for FTM_SYNC_TRIG2. /
mbed_official	324:406fd2029f23	1535	#define BM_FTM_SYNC_TRIG2 (0x00000040U) /!< Bit mask for FTM_SYNC_TRIG2. /
mbed_official	324:406fd2029f23	1536	#define BS_FTM_SYNC_TRIG2 (1U) /!< Bit field size in bits for FTM_SYNC_TRIG2. /
mbed_official	324:406fd2029f23	1537
mbed_official	324:406fd2029f23	1538	/! @brief Read current value of the FTM_SYNC_TRIG2 field. /
mbed_official	324:406fd2029f23	1539	#define BR_FTM_SYNC_TRIG2(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2))
mbed_official	324:406fd2029f23	1540
mbed_official	324:406fd2029f23	1541	/! @brief Format value for bitfield FTM_SYNC_TRIG2. /
mbed_official	324:406fd2029f23	1542	#define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
mbed_official	324:406fd2029f23	1543
mbed_official	324:406fd2029f23	1544	/! @brief Set the TRIG2 field to a new value. /
mbed_official	324:406fd2029f23	1545	#define BW_FTM_SYNC_TRIG2(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2) = (v))
mbed_official	324:406fd2029f23	1546	/@}/
mbed_official	324:406fd2029f23	1547
mbed_official	324:406fd2029f23	1548	/*!
mbed_official	324:406fd2029f23	1549	* @name Register FTM_SYNC, field SWSYNC[7] (RW)
mbed_official	324:406fd2029f23	1550	*
mbed_official	324:406fd2029f23	1551	* Selects the software trigger as the PWM synchronization trigger. The software
mbed_official	324:406fd2029f23	1552	* trigger happens when a 1 is written to SWSYNC bit.
mbed_official	324:406fd2029f23	1553	*
mbed_official	324:406fd2029f23	1554	* Values:
mbed_official	324:406fd2029f23	1555	* - 0 - Software trigger is not selected.
mbed_official	324:406fd2029f23	1556	* - 1 - Software trigger is selected.
mbed_official	324:406fd2029f23	1557	*/
mbed_official	324:406fd2029f23	1558	/@{/
mbed_official	324:406fd2029f23	1559	#define BP_FTM_SYNC_SWSYNC (7U) /!< Bit position for FTM_SYNC_SWSYNC. /
mbed_official	324:406fd2029f23	1560	#define BM_FTM_SYNC_SWSYNC (0x00000080U) /!< Bit mask for FTM_SYNC_SWSYNC. /
mbed_official	324:406fd2029f23	1561	#define BS_FTM_SYNC_SWSYNC (1U) /!< Bit field size in bits for FTM_SYNC_SWSYNC. /
mbed_official	324:406fd2029f23	1562
mbed_official	324:406fd2029f23	1563	/! @brief Read current value of the FTM_SYNC_SWSYNC field. /
mbed_official	324:406fd2029f23	1564	#define BR_FTM_SYNC_SWSYNC(x) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC))
mbed_official	324:406fd2029f23	1565
mbed_official	324:406fd2029f23	1566	/! @brief Format value for bitfield FTM_SYNC_SWSYNC. /
mbed_official	324:406fd2029f23	1567	#define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
mbed_official	324:406fd2029f23	1568
mbed_official	324:406fd2029f23	1569	/! @brief Set the SWSYNC field to a new value. /
mbed_official	324:406fd2029f23	1570	#define BW_FTM_SYNC_SWSYNC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC) = (v))
mbed_official	324:406fd2029f23	1571	/@}/
mbed_official	324:406fd2029f23	1572
mbed_official	324:406fd2029f23	1573	/*******************************************************************************
mbed_official	324:406fd2029f23	1574	* HW_FTM_OUTINIT - Initial State For Channels Output
mbed_official	324:406fd2029f23	1575	******************************************************************************/
mbed_official	324:406fd2029f23	1576
mbed_official	324:406fd2029f23	1577	/*!
mbed_official	324:406fd2029f23	1578	* @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
mbed_official	324:406fd2029f23	1579	*
mbed_official	324:406fd2029f23	1580	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1581	*/
mbed_official	324:406fd2029f23	1582	typedef union _hw_ftm_outinit
mbed_official	324:406fd2029f23	1583	{
mbed_official	324:406fd2029f23	1584	uint32_t U;
mbed_official	324:406fd2029f23	1585	struct _hw_ftm_outinit_bitfields
mbed_official	324:406fd2029f23	1586	{
mbed_official	324:406fd2029f23	1587	uint32_t CH0OI : 1; /!< [0] Channel 0 Output Initialization Value /
mbed_official	324:406fd2029f23	1588	uint32_t CH1OI : 1; /!< [1] Channel 1 Output Initialization Value /
mbed_official	324:406fd2029f23	1589	uint32_t CH2OI : 1; /!< [2] Channel 2 Output Initialization Value /
mbed_official	324:406fd2029f23	1590	uint32_t CH3OI : 1; /!< [3] Channel 3 Output Initialization Value /
mbed_official	324:406fd2029f23	1591	uint32_t CH4OI : 1; /!< [4] Channel 4 Output Initialization Value /
mbed_official	324:406fd2029f23	1592	uint32_t CH5OI : 1; /!< [5] Channel 5 Output Initialization Value /
mbed_official	324:406fd2029f23	1593	uint32_t CH6OI : 1; /!< [6] Channel 6 Output Initialization Value /
mbed_official	324:406fd2029f23	1594	uint32_t CH7OI : 1; /!< [7] Channel 7 Output Initialization Value /
mbed_official	324:406fd2029f23	1595	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1596	} B;
mbed_official	324:406fd2029f23	1597	} hw_ftm_outinit_t;
mbed_official	324:406fd2029f23	1598
mbed_official	324:406fd2029f23	1599	/*!
mbed_official	324:406fd2029f23	1600	* @name Constants and macros for entire FTM_OUTINIT register
mbed_official	324:406fd2029f23	1601	*/
mbed_official	324:406fd2029f23	1602	/@{/
mbed_official	324:406fd2029f23	1603	#define HW_FTM_OUTINIT_ADDR(x) ((x) + 0x5CU)
mbed_official	324:406fd2029f23	1604
mbed_official	324:406fd2029f23	1605	#define HW_FTM_OUTINIT(x) ((__IO hw_ftm_outinit_t ) HW_FTM_OUTINIT_ADDR(x))
mbed_official	324:406fd2029f23	1606	#define HW_FTM_OUTINIT_RD(x) (HW_FTM_OUTINIT(x).U)
mbed_official	324:406fd2029f23	1607	#define HW_FTM_OUTINIT_WR(x, v) (HW_FTM_OUTINIT(x).U = (v))
mbed_official	324:406fd2029f23	1608	#define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1609	#define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1610	#define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1611	/@}/
mbed_official	324:406fd2029f23	1612
mbed_official	324:406fd2029f23	1613	/*
mbed_official	324:406fd2029f23	1614	* Constants & macros for individual FTM_OUTINIT bitfields
mbed_official	324:406fd2029f23	1615	*/
mbed_official	324:406fd2029f23	1616
mbed_official	324:406fd2029f23	1617	/*!
mbed_official	324:406fd2029f23	1618	* @name Register FTM_OUTINIT, field CH0OI[0] (RW)
mbed_official	324:406fd2029f23	1619	*
mbed_official	324:406fd2029f23	1620	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1621	* initialization occurs.
mbed_official	324:406fd2029f23	1622	*
mbed_official	324:406fd2029f23	1623	* Values:
mbed_official	324:406fd2029f23	1624	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1625	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1626	*/
mbed_official	324:406fd2029f23	1627	/@{/
mbed_official	324:406fd2029f23	1628	#define BP_FTM_OUTINIT_CH0OI (0U) /!< Bit position for FTM_OUTINIT_CH0OI. /
mbed_official	324:406fd2029f23	1629	#define BM_FTM_OUTINIT_CH0OI (0x00000001U) /!< Bit mask for FTM_OUTINIT_CH0OI. /
mbed_official	324:406fd2029f23	1630	#define BS_FTM_OUTINIT_CH0OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH0OI. /
mbed_official	324:406fd2029f23	1631
mbed_official	324:406fd2029f23	1632	/! @brief Read current value of the FTM_OUTINIT_CH0OI field. /
mbed_official	324:406fd2029f23	1633	#define BR_FTM_OUTINIT_CH0OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI))
mbed_official	324:406fd2029f23	1634
mbed_official	324:406fd2029f23	1635	/! @brief Format value for bitfield FTM_OUTINIT_CH0OI. /
mbed_official	324:406fd2029f23	1636	#define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
mbed_official	324:406fd2029f23	1637
mbed_official	324:406fd2029f23	1638	/! @brief Set the CH0OI field to a new value. /
mbed_official	324:406fd2029f23	1639	#define BW_FTM_OUTINIT_CH0OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI) = (v))
mbed_official	324:406fd2029f23	1640	/@}/
mbed_official	324:406fd2029f23	1641
mbed_official	324:406fd2029f23	1642	/*!
mbed_official	324:406fd2029f23	1643	* @name Register FTM_OUTINIT, field CH1OI[1] (RW)
mbed_official	324:406fd2029f23	1644	*
mbed_official	324:406fd2029f23	1645	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1646	* initialization occurs.
mbed_official	324:406fd2029f23	1647	*
mbed_official	324:406fd2029f23	1648	* Values:
mbed_official	324:406fd2029f23	1649	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1650	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1651	*/
mbed_official	324:406fd2029f23	1652	/@{/
mbed_official	324:406fd2029f23	1653	#define BP_FTM_OUTINIT_CH1OI (1U) /!< Bit position for FTM_OUTINIT_CH1OI. /
mbed_official	324:406fd2029f23	1654	#define BM_FTM_OUTINIT_CH1OI (0x00000002U) /!< Bit mask for FTM_OUTINIT_CH1OI. /
mbed_official	324:406fd2029f23	1655	#define BS_FTM_OUTINIT_CH1OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH1OI. /
mbed_official	324:406fd2029f23	1656
mbed_official	324:406fd2029f23	1657	/! @brief Read current value of the FTM_OUTINIT_CH1OI field. /
mbed_official	324:406fd2029f23	1658	#define BR_FTM_OUTINIT_CH1OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI))
mbed_official	324:406fd2029f23	1659
mbed_official	324:406fd2029f23	1660	/! @brief Format value for bitfield FTM_OUTINIT_CH1OI. /
mbed_official	324:406fd2029f23	1661	#define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
mbed_official	324:406fd2029f23	1662
mbed_official	324:406fd2029f23	1663	/! @brief Set the CH1OI field to a new value. /
mbed_official	324:406fd2029f23	1664	#define BW_FTM_OUTINIT_CH1OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI) = (v))
mbed_official	324:406fd2029f23	1665	/@}/
mbed_official	324:406fd2029f23	1666
mbed_official	324:406fd2029f23	1667	/*!
mbed_official	324:406fd2029f23	1668	* @name Register FTM_OUTINIT, field CH2OI[2] (RW)
mbed_official	324:406fd2029f23	1669	*
mbed_official	324:406fd2029f23	1670	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1671	* initialization occurs.
mbed_official	324:406fd2029f23	1672	*
mbed_official	324:406fd2029f23	1673	* Values:
mbed_official	324:406fd2029f23	1674	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1675	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1676	*/
mbed_official	324:406fd2029f23	1677	/@{/
mbed_official	324:406fd2029f23	1678	#define BP_FTM_OUTINIT_CH2OI (2U) /!< Bit position for FTM_OUTINIT_CH2OI. /
mbed_official	324:406fd2029f23	1679	#define BM_FTM_OUTINIT_CH2OI (0x00000004U) /!< Bit mask for FTM_OUTINIT_CH2OI. /
mbed_official	324:406fd2029f23	1680	#define BS_FTM_OUTINIT_CH2OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH2OI. /
mbed_official	324:406fd2029f23	1681
mbed_official	324:406fd2029f23	1682	/! @brief Read current value of the FTM_OUTINIT_CH2OI field. /
mbed_official	324:406fd2029f23	1683	#define BR_FTM_OUTINIT_CH2OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI))
mbed_official	324:406fd2029f23	1684
mbed_official	324:406fd2029f23	1685	/! @brief Format value for bitfield FTM_OUTINIT_CH2OI. /
mbed_official	324:406fd2029f23	1686	#define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
mbed_official	324:406fd2029f23	1687
mbed_official	324:406fd2029f23	1688	/! @brief Set the CH2OI field to a new value. /
mbed_official	324:406fd2029f23	1689	#define BW_FTM_OUTINIT_CH2OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI) = (v))
mbed_official	324:406fd2029f23	1690	/@}/
mbed_official	324:406fd2029f23	1691
mbed_official	324:406fd2029f23	1692	/*!
mbed_official	324:406fd2029f23	1693	* @name Register FTM_OUTINIT, field CH3OI[3] (RW)
mbed_official	324:406fd2029f23	1694	*
mbed_official	324:406fd2029f23	1695	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1696	* initialization occurs.
mbed_official	324:406fd2029f23	1697	*
mbed_official	324:406fd2029f23	1698	* Values:
mbed_official	324:406fd2029f23	1699	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1700	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1701	*/
mbed_official	324:406fd2029f23	1702	/@{/
mbed_official	324:406fd2029f23	1703	#define BP_FTM_OUTINIT_CH3OI (3U) /!< Bit position for FTM_OUTINIT_CH3OI. /
mbed_official	324:406fd2029f23	1704	#define BM_FTM_OUTINIT_CH3OI (0x00000008U) /!< Bit mask for FTM_OUTINIT_CH3OI. /
mbed_official	324:406fd2029f23	1705	#define BS_FTM_OUTINIT_CH3OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH3OI. /
mbed_official	324:406fd2029f23	1706
mbed_official	324:406fd2029f23	1707	/! @brief Read current value of the FTM_OUTINIT_CH3OI field. /
mbed_official	324:406fd2029f23	1708	#define BR_FTM_OUTINIT_CH3OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI))
mbed_official	324:406fd2029f23	1709
mbed_official	324:406fd2029f23	1710	/! @brief Format value for bitfield FTM_OUTINIT_CH3OI. /
mbed_official	324:406fd2029f23	1711	#define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
mbed_official	324:406fd2029f23	1712
mbed_official	324:406fd2029f23	1713	/! @brief Set the CH3OI field to a new value. /
mbed_official	324:406fd2029f23	1714	#define BW_FTM_OUTINIT_CH3OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI) = (v))
mbed_official	324:406fd2029f23	1715	/@}/
mbed_official	324:406fd2029f23	1716
mbed_official	324:406fd2029f23	1717	/*!
mbed_official	324:406fd2029f23	1718	* @name Register FTM_OUTINIT, field CH4OI[4] (RW)
mbed_official	324:406fd2029f23	1719	*
mbed_official	324:406fd2029f23	1720	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1721	* initialization occurs.
mbed_official	324:406fd2029f23	1722	*
mbed_official	324:406fd2029f23	1723	* Values:
mbed_official	324:406fd2029f23	1724	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1725	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1726	*/
mbed_official	324:406fd2029f23	1727	/@{/
mbed_official	324:406fd2029f23	1728	#define BP_FTM_OUTINIT_CH4OI (4U) /!< Bit position for FTM_OUTINIT_CH4OI. /
mbed_official	324:406fd2029f23	1729	#define BM_FTM_OUTINIT_CH4OI (0x00000010U) /!< Bit mask for FTM_OUTINIT_CH4OI. /
mbed_official	324:406fd2029f23	1730	#define BS_FTM_OUTINIT_CH4OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH4OI. /
mbed_official	324:406fd2029f23	1731
mbed_official	324:406fd2029f23	1732	/! @brief Read current value of the FTM_OUTINIT_CH4OI field. /
mbed_official	324:406fd2029f23	1733	#define BR_FTM_OUTINIT_CH4OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI))
mbed_official	324:406fd2029f23	1734
mbed_official	324:406fd2029f23	1735	/! @brief Format value for bitfield FTM_OUTINIT_CH4OI. /
mbed_official	324:406fd2029f23	1736	#define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
mbed_official	324:406fd2029f23	1737
mbed_official	324:406fd2029f23	1738	/! @brief Set the CH4OI field to a new value. /
mbed_official	324:406fd2029f23	1739	#define BW_FTM_OUTINIT_CH4OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI) = (v))
mbed_official	324:406fd2029f23	1740	/@}/
mbed_official	324:406fd2029f23	1741
mbed_official	324:406fd2029f23	1742	/*!
mbed_official	324:406fd2029f23	1743	* @name Register FTM_OUTINIT, field CH5OI[5] (RW)
mbed_official	324:406fd2029f23	1744	*
mbed_official	324:406fd2029f23	1745	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1746	* initialization occurs.
mbed_official	324:406fd2029f23	1747	*
mbed_official	324:406fd2029f23	1748	* Values:
mbed_official	324:406fd2029f23	1749	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1750	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1751	*/
mbed_official	324:406fd2029f23	1752	/@{/
mbed_official	324:406fd2029f23	1753	#define BP_FTM_OUTINIT_CH5OI (5U) /!< Bit position for FTM_OUTINIT_CH5OI. /
mbed_official	324:406fd2029f23	1754	#define BM_FTM_OUTINIT_CH5OI (0x00000020U) /!< Bit mask for FTM_OUTINIT_CH5OI. /
mbed_official	324:406fd2029f23	1755	#define BS_FTM_OUTINIT_CH5OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH5OI. /
mbed_official	324:406fd2029f23	1756
mbed_official	324:406fd2029f23	1757	/! @brief Read current value of the FTM_OUTINIT_CH5OI field. /
mbed_official	324:406fd2029f23	1758	#define BR_FTM_OUTINIT_CH5OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI))
mbed_official	324:406fd2029f23	1759
mbed_official	324:406fd2029f23	1760	/! @brief Format value for bitfield FTM_OUTINIT_CH5OI. /
mbed_official	324:406fd2029f23	1761	#define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
mbed_official	324:406fd2029f23	1762
mbed_official	324:406fd2029f23	1763	/! @brief Set the CH5OI field to a new value. /
mbed_official	324:406fd2029f23	1764	#define BW_FTM_OUTINIT_CH5OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI) = (v))
mbed_official	324:406fd2029f23	1765	/@}/
mbed_official	324:406fd2029f23	1766
mbed_official	324:406fd2029f23	1767	/*!
mbed_official	324:406fd2029f23	1768	* @name Register FTM_OUTINIT, field CH6OI[6] (RW)
mbed_official	324:406fd2029f23	1769	*
mbed_official	324:406fd2029f23	1770	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1771	* initialization occurs.
mbed_official	324:406fd2029f23	1772	*
mbed_official	324:406fd2029f23	1773	* Values:
mbed_official	324:406fd2029f23	1774	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1775	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1776	*/
mbed_official	324:406fd2029f23	1777	/@{/
mbed_official	324:406fd2029f23	1778	#define BP_FTM_OUTINIT_CH6OI (6U) /!< Bit position for FTM_OUTINIT_CH6OI. /
mbed_official	324:406fd2029f23	1779	#define BM_FTM_OUTINIT_CH6OI (0x00000040U) /!< Bit mask for FTM_OUTINIT_CH6OI. /
mbed_official	324:406fd2029f23	1780	#define BS_FTM_OUTINIT_CH6OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH6OI. /
mbed_official	324:406fd2029f23	1781
mbed_official	324:406fd2029f23	1782	/! @brief Read current value of the FTM_OUTINIT_CH6OI field. /
mbed_official	324:406fd2029f23	1783	#define BR_FTM_OUTINIT_CH6OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI))
mbed_official	324:406fd2029f23	1784
mbed_official	324:406fd2029f23	1785	/! @brief Format value for bitfield FTM_OUTINIT_CH6OI. /
mbed_official	324:406fd2029f23	1786	#define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
mbed_official	324:406fd2029f23	1787
mbed_official	324:406fd2029f23	1788	/! @brief Set the CH6OI field to a new value. /
mbed_official	324:406fd2029f23	1789	#define BW_FTM_OUTINIT_CH6OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI) = (v))
mbed_official	324:406fd2029f23	1790	/@}/
mbed_official	324:406fd2029f23	1791
mbed_official	324:406fd2029f23	1792	/*!
mbed_official	324:406fd2029f23	1793	* @name Register FTM_OUTINIT, field CH7OI[7] (RW)
mbed_official	324:406fd2029f23	1794	*
mbed_official	324:406fd2029f23	1795	* Selects the value that is forced into the channel output when the
mbed_official	324:406fd2029f23	1796	* initialization occurs.
mbed_official	324:406fd2029f23	1797	*
mbed_official	324:406fd2029f23	1798	* Values:
mbed_official	324:406fd2029f23	1799	* - 0 - The initialization value is 0.
mbed_official	324:406fd2029f23	1800	* - 1 - The initialization value is 1.
mbed_official	324:406fd2029f23	1801	*/
mbed_official	324:406fd2029f23	1802	/@{/
mbed_official	324:406fd2029f23	1803	#define BP_FTM_OUTINIT_CH7OI (7U) /!< Bit position for FTM_OUTINIT_CH7OI. /
mbed_official	324:406fd2029f23	1804	#define BM_FTM_OUTINIT_CH7OI (0x00000080U) /!< Bit mask for FTM_OUTINIT_CH7OI. /
mbed_official	324:406fd2029f23	1805	#define BS_FTM_OUTINIT_CH7OI (1U) /!< Bit field size in bits for FTM_OUTINIT_CH7OI. /
mbed_official	324:406fd2029f23	1806
mbed_official	324:406fd2029f23	1807	/! @brief Read current value of the FTM_OUTINIT_CH7OI field. /
mbed_official	324:406fd2029f23	1808	#define BR_FTM_OUTINIT_CH7OI(x) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI))
mbed_official	324:406fd2029f23	1809
mbed_official	324:406fd2029f23	1810	/! @brief Format value for bitfield FTM_OUTINIT_CH7OI. /
mbed_official	324:406fd2029f23	1811	#define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
mbed_official	324:406fd2029f23	1812
mbed_official	324:406fd2029f23	1813	/! @brief Set the CH7OI field to a new value. /
mbed_official	324:406fd2029f23	1814	#define BW_FTM_OUTINIT_CH7OI(x, v) (BITBAND_ACCESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI) = (v))
mbed_official	324:406fd2029f23	1815	/@}/
mbed_official	324:406fd2029f23	1816
mbed_official	324:406fd2029f23	1817	/*******************************************************************************
mbed_official	324:406fd2029f23	1818	* HW_FTM_OUTMASK - Output Mask
mbed_official	324:406fd2029f23	1819	******************************************************************************/
mbed_official	324:406fd2029f23	1820
mbed_official	324:406fd2029f23	1821	/*!
mbed_official	324:406fd2029f23	1822	* @brief HW_FTM_OUTMASK - Output Mask (RW)
mbed_official	324:406fd2029f23	1823	*
mbed_official	324:406fd2029f23	1824	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	1825	*
mbed_official	324:406fd2029f23	1826	* This register provides a mask for each FTM channel. The mask of a channel
mbed_official	324:406fd2029f23	1827	* determines if its output responds, that is, it is masked or not, when a match
mbed_official	324:406fd2029f23	1828	* occurs. This feature is used for BLDC control where the PWM signal is presented
mbed_official	324:406fd2029f23	1829	* to an electric motor at specific times to provide electronic commutation. Any
mbed_official	324:406fd2029f23	1830	* write to the OUTMASK register, stores the value in its write buffer. The
mbed_official	324:406fd2029f23	1831	* register is updated with the value of its write buffer according to PWM
mbed_official	324:406fd2029f23	1832	* synchronization.
mbed_official	324:406fd2029f23	1833	*/
mbed_official	324:406fd2029f23	1834	typedef union _hw_ftm_outmask
mbed_official	324:406fd2029f23	1835	{
mbed_official	324:406fd2029f23	1836	uint32_t U;
mbed_official	324:406fd2029f23	1837	struct _hw_ftm_outmask_bitfields
mbed_official	324:406fd2029f23	1838	{
mbed_official	324:406fd2029f23	1839	uint32_t CH0OM : 1; /!< [0] Channel 0 Output Mask /
mbed_official	324:406fd2029f23	1840	uint32_t CH1OM : 1; /!< [1] Channel 1 Output Mask /
mbed_official	324:406fd2029f23	1841	uint32_t CH2OM : 1; /!< [2] Channel 2 Output Mask /
mbed_official	324:406fd2029f23	1842	uint32_t CH3OM : 1; /!< [3] Channel 3 Output Mask /
mbed_official	324:406fd2029f23	1843	uint32_t CH4OM : 1; /!< [4] Channel 4 Output Mask /
mbed_official	324:406fd2029f23	1844	uint32_t CH5OM : 1; /!< [5] Channel 5 Output Mask /
mbed_official	324:406fd2029f23	1845	uint32_t CH6OM : 1; /!< [6] Channel 6 Output Mask /
mbed_official	324:406fd2029f23	1846	uint32_t CH7OM : 1; /!< [7] Channel 7 Output Mask /
mbed_official	324:406fd2029f23	1847	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	1848	} B;
mbed_official	324:406fd2029f23	1849	} hw_ftm_outmask_t;
mbed_official	324:406fd2029f23	1850
mbed_official	324:406fd2029f23	1851	/*!
mbed_official	324:406fd2029f23	1852	* @name Constants and macros for entire FTM_OUTMASK register
mbed_official	324:406fd2029f23	1853	*/
mbed_official	324:406fd2029f23	1854	/@{/
mbed_official	324:406fd2029f23	1855	#define HW_FTM_OUTMASK_ADDR(x) ((x) + 0x60U)
mbed_official	324:406fd2029f23	1856
mbed_official	324:406fd2029f23	1857	#define HW_FTM_OUTMASK(x) ((__IO hw_ftm_outmask_t ) HW_FTM_OUTMASK_ADDR(x))
mbed_official	324:406fd2029f23	1858	#define HW_FTM_OUTMASK_RD(x) (HW_FTM_OUTMASK(x).U)
mbed_official	324:406fd2029f23	1859	#define HW_FTM_OUTMASK_WR(x, v) (HW_FTM_OUTMASK(x).U = (v))
mbed_official	324:406fd2029f23	1860	#define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) \| (v)))
mbed_official	324:406fd2029f23	1861	#define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	1862	#define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	1863	/@}/
mbed_official	324:406fd2029f23	1864
mbed_official	324:406fd2029f23	1865	/*
mbed_official	324:406fd2029f23	1866	* Constants & macros for individual FTM_OUTMASK bitfields
mbed_official	324:406fd2029f23	1867	*/
mbed_official	324:406fd2029f23	1868
mbed_official	324:406fd2029f23	1869	/*!
mbed_official	324:406fd2029f23	1870	* @name Register FTM_OUTMASK, field CH0OM[0] (RW)
mbed_official	324:406fd2029f23	1871	*
mbed_official	324:406fd2029f23	1872	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1873	*
mbed_official	324:406fd2029f23	1874	* Values:
mbed_official	324:406fd2029f23	1875	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1876	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1877	*/
mbed_official	324:406fd2029f23	1878	/@{/
mbed_official	324:406fd2029f23	1879	#define BP_FTM_OUTMASK_CH0OM (0U) /!< Bit position for FTM_OUTMASK_CH0OM. /
mbed_official	324:406fd2029f23	1880	#define BM_FTM_OUTMASK_CH0OM (0x00000001U) /!< Bit mask for FTM_OUTMASK_CH0OM. /
mbed_official	324:406fd2029f23	1881	#define BS_FTM_OUTMASK_CH0OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH0OM. /
mbed_official	324:406fd2029f23	1882
mbed_official	324:406fd2029f23	1883	/! @brief Read current value of the FTM_OUTMASK_CH0OM field. /
mbed_official	324:406fd2029f23	1884	#define BR_FTM_OUTMASK_CH0OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM))
mbed_official	324:406fd2029f23	1885
mbed_official	324:406fd2029f23	1886	/! @brief Format value for bitfield FTM_OUTMASK_CH0OM. /
mbed_official	324:406fd2029f23	1887	#define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
mbed_official	324:406fd2029f23	1888
mbed_official	324:406fd2029f23	1889	/! @brief Set the CH0OM field to a new value. /
mbed_official	324:406fd2029f23	1890	#define BW_FTM_OUTMASK_CH0OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM) = (v))
mbed_official	324:406fd2029f23	1891	/@}/
mbed_official	324:406fd2029f23	1892
mbed_official	324:406fd2029f23	1893	/*!
mbed_official	324:406fd2029f23	1894	* @name Register FTM_OUTMASK, field CH1OM[1] (RW)
mbed_official	324:406fd2029f23	1895	*
mbed_official	324:406fd2029f23	1896	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1897	*
mbed_official	324:406fd2029f23	1898	* Values:
mbed_official	324:406fd2029f23	1899	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1900	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1901	*/
mbed_official	324:406fd2029f23	1902	/@{/
mbed_official	324:406fd2029f23	1903	#define BP_FTM_OUTMASK_CH1OM (1U) /!< Bit position for FTM_OUTMASK_CH1OM. /
mbed_official	324:406fd2029f23	1904	#define BM_FTM_OUTMASK_CH1OM (0x00000002U) /!< Bit mask for FTM_OUTMASK_CH1OM. /
mbed_official	324:406fd2029f23	1905	#define BS_FTM_OUTMASK_CH1OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH1OM. /
mbed_official	324:406fd2029f23	1906
mbed_official	324:406fd2029f23	1907	/! @brief Read current value of the FTM_OUTMASK_CH1OM field. /
mbed_official	324:406fd2029f23	1908	#define BR_FTM_OUTMASK_CH1OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM))
mbed_official	324:406fd2029f23	1909
mbed_official	324:406fd2029f23	1910	/! @brief Format value for bitfield FTM_OUTMASK_CH1OM. /
mbed_official	324:406fd2029f23	1911	#define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
mbed_official	324:406fd2029f23	1912
mbed_official	324:406fd2029f23	1913	/! @brief Set the CH1OM field to a new value. /
mbed_official	324:406fd2029f23	1914	#define BW_FTM_OUTMASK_CH1OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM) = (v))
mbed_official	324:406fd2029f23	1915	/@}/
mbed_official	324:406fd2029f23	1916
mbed_official	324:406fd2029f23	1917	/*!
mbed_official	324:406fd2029f23	1918	* @name Register FTM_OUTMASK, field CH2OM[2] (RW)
mbed_official	324:406fd2029f23	1919	*
mbed_official	324:406fd2029f23	1920	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1921	*
mbed_official	324:406fd2029f23	1922	* Values:
mbed_official	324:406fd2029f23	1923	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1924	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1925	*/
mbed_official	324:406fd2029f23	1926	/@{/
mbed_official	324:406fd2029f23	1927	#define BP_FTM_OUTMASK_CH2OM (2U) /!< Bit position for FTM_OUTMASK_CH2OM. /
mbed_official	324:406fd2029f23	1928	#define BM_FTM_OUTMASK_CH2OM (0x00000004U) /!< Bit mask for FTM_OUTMASK_CH2OM. /
mbed_official	324:406fd2029f23	1929	#define BS_FTM_OUTMASK_CH2OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH2OM. /
mbed_official	324:406fd2029f23	1930
mbed_official	324:406fd2029f23	1931	/! @brief Read current value of the FTM_OUTMASK_CH2OM field. /
mbed_official	324:406fd2029f23	1932	#define BR_FTM_OUTMASK_CH2OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM))
mbed_official	324:406fd2029f23	1933
mbed_official	324:406fd2029f23	1934	/! @brief Format value for bitfield FTM_OUTMASK_CH2OM. /
mbed_official	324:406fd2029f23	1935	#define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
mbed_official	324:406fd2029f23	1936
mbed_official	324:406fd2029f23	1937	/! @brief Set the CH2OM field to a new value. /
mbed_official	324:406fd2029f23	1938	#define BW_FTM_OUTMASK_CH2OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM) = (v))
mbed_official	324:406fd2029f23	1939	/@}/
mbed_official	324:406fd2029f23	1940
mbed_official	324:406fd2029f23	1941	/*!
mbed_official	324:406fd2029f23	1942	* @name Register FTM_OUTMASK, field CH3OM[3] (RW)
mbed_official	324:406fd2029f23	1943	*
mbed_official	324:406fd2029f23	1944	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1945	*
mbed_official	324:406fd2029f23	1946	* Values:
mbed_official	324:406fd2029f23	1947	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1948	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1949	*/
mbed_official	324:406fd2029f23	1950	/@{/
mbed_official	324:406fd2029f23	1951	#define BP_FTM_OUTMASK_CH3OM (3U) /!< Bit position for FTM_OUTMASK_CH3OM. /
mbed_official	324:406fd2029f23	1952	#define BM_FTM_OUTMASK_CH3OM (0x00000008U) /!< Bit mask for FTM_OUTMASK_CH3OM. /
mbed_official	324:406fd2029f23	1953	#define BS_FTM_OUTMASK_CH3OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH3OM. /
mbed_official	324:406fd2029f23	1954
mbed_official	324:406fd2029f23	1955	/! @brief Read current value of the FTM_OUTMASK_CH3OM field. /
mbed_official	324:406fd2029f23	1956	#define BR_FTM_OUTMASK_CH3OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM))
mbed_official	324:406fd2029f23	1957
mbed_official	324:406fd2029f23	1958	/! @brief Format value for bitfield FTM_OUTMASK_CH3OM. /
mbed_official	324:406fd2029f23	1959	#define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
mbed_official	324:406fd2029f23	1960
mbed_official	324:406fd2029f23	1961	/! @brief Set the CH3OM field to a new value. /
mbed_official	324:406fd2029f23	1962	#define BW_FTM_OUTMASK_CH3OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM) = (v))
mbed_official	324:406fd2029f23	1963	/@}/
mbed_official	324:406fd2029f23	1964
mbed_official	324:406fd2029f23	1965	/*!
mbed_official	324:406fd2029f23	1966	* @name Register FTM_OUTMASK, field CH4OM[4] (RW)
mbed_official	324:406fd2029f23	1967	*
mbed_official	324:406fd2029f23	1968	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1969	*
mbed_official	324:406fd2029f23	1970	* Values:
mbed_official	324:406fd2029f23	1971	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1972	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1973	*/
mbed_official	324:406fd2029f23	1974	/@{/
mbed_official	324:406fd2029f23	1975	#define BP_FTM_OUTMASK_CH4OM (4U) /!< Bit position for FTM_OUTMASK_CH4OM. /
mbed_official	324:406fd2029f23	1976	#define BM_FTM_OUTMASK_CH4OM (0x00000010U) /!< Bit mask for FTM_OUTMASK_CH4OM. /
mbed_official	324:406fd2029f23	1977	#define BS_FTM_OUTMASK_CH4OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH4OM. /
mbed_official	324:406fd2029f23	1978
mbed_official	324:406fd2029f23	1979	/! @brief Read current value of the FTM_OUTMASK_CH4OM field. /
mbed_official	324:406fd2029f23	1980	#define BR_FTM_OUTMASK_CH4OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM))
mbed_official	324:406fd2029f23	1981
mbed_official	324:406fd2029f23	1982	/! @brief Format value for bitfield FTM_OUTMASK_CH4OM. /
mbed_official	324:406fd2029f23	1983	#define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
mbed_official	324:406fd2029f23	1984
mbed_official	324:406fd2029f23	1985	/! @brief Set the CH4OM field to a new value. /
mbed_official	324:406fd2029f23	1986	#define BW_FTM_OUTMASK_CH4OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM) = (v))
mbed_official	324:406fd2029f23	1987	/@}/
mbed_official	324:406fd2029f23	1988
mbed_official	324:406fd2029f23	1989	/*!
mbed_official	324:406fd2029f23	1990	* @name Register FTM_OUTMASK, field CH5OM[5] (RW)
mbed_official	324:406fd2029f23	1991	*
mbed_official	324:406fd2029f23	1992	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	1993	*
mbed_official	324:406fd2029f23	1994	* Values:
mbed_official	324:406fd2029f23	1995	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	1996	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	1997	*/
mbed_official	324:406fd2029f23	1998	/@{/
mbed_official	324:406fd2029f23	1999	#define BP_FTM_OUTMASK_CH5OM (5U) /!< Bit position for FTM_OUTMASK_CH5OM. /
mbed_official	324:406fd2029f23	2000	#define BM_FTM_OUTMASK_CH5OM (0x00000020U) /!< Bit mask for FTM_OUTMASK_CH5OM. /
mbed_official	324:406fd2029f23	2001	#define BS_FTM_OUTMASK_CH5OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH5OM. /
mbed_official	324:406fd2029f23	2002
mbed_official	324:406fd2029f23	2003	/! @brief Read current value of the FTM_OUTMASK_CH5OM field. /
mbed_official	324:406fd2029f23	2004	#define BR_FTM_OUTMASK_CH5OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM))
mbed_official	324:406fd2029f23	2005
mbed_official	324:406fd2029f23	2006	/! @brief Format value for bitfield FTM_OUTMASK_CH5OM. /
mbed_official	324:406fd2029f23	2007	#define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
mbed_official	324:406fd2029f23	2008
mbed_official	324:406fd2029f23	2009	/! @brief Set the CH5OM field to a new value. /
mbed_official	324:406fd2029f23	2010	#define BW_FTM_OUTMASK_CH5OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM) = (v))
mbed_official	324:406fd2029f23	2011	/@}/
mbed_official	324:406fd2029f23	2012
mbed_official	324:406fd2029f23	2013	/*!
mbed_official	324:406fd2029f23	2014	* @name Register FTM_OUTMASK, field CH6OM[6] (RW)
mbed_official	324:406fd2029f23	2015	*
mbed_official	324:406fd2029f23	2016	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	2017	*
mbed_official	324:406fd2029f23	2018	* Values:
mbed_official	324:406fd2029f23	2019	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	2020	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	2021	*/
mbed_official	324:406fd2029f23	2022	/@{/
mbed_official	324:406fd2029f23	2023	#define BP_FTM_OUTMASK_CH6OM (6U) /!< Bit position for FTM_OUTMASK_CH6OM. /
mbed_official	324:406fd2029f23	2024	#define BM_FTM_OUTMASK_CH6OM (0x00000040U) /!< Bit mask for FTM_OUTMASK_CH6OM. /
mbed_official	324:406fd2029f23	2025	#define BS_FTM_OUTMASK_CH6OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH6OM. /
mbed_official	324:406fd2029f23	2026
mbed_official	324:406fd2029f23	2027	/! @brief Read current value of the FTM_OUTMASK_CH6OM field. /
mbed_official	324:406fd2029f23	2028	#define BR_FTM_OUTMASK_CH6OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM))
mbed_official	324:406fd2029f23	2029
mbed_official	324:406fd2029f23	2030	/! @brief Format value for bitfield FTM_OUTMASK_CH6OM. /
mbed_official	324:406fd2029f23	2031	#define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
mbed_official	324:406fd2029f23	2032
mbed_official	324:406fd2029f23	2033	/! @brief Set the CH6OM field to a new value. /
mbed_official	324:406fd2029f23	2034	#define BW_FTM_OUTMASK_CH6OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM) = (v))
mbed_official	324:406fd2029f23	2035	/@}/
mbed_official	324:406fd2029f23	2036
mbed_official	324:406fd2029f23	2037	/*!
mbed_official	324:406fd2029f23	2038	* @name Register FTM_OUTMASK, field CH7OM[7] (RW)
mbed_official	324:406fd2029f23	2039	*
mbed_official	324:406fd2029f23	2040	* Defines if the channel output is masked or unmasked.
mbed_official	324:406fd2029f23	2041	*
mbed_official	324:406fd2029f23	2042	* Values:
mbed_official	324:406fd2029f23	2043	* - 0 - Channel output is not masked. It continues to operate normally.
mbed_official	324:406fd2029f23	2044	* - 1 - Channel output is masked. It is forced to its inactive state.
mbed_official	324:406fd2029f23	2045	*/
mbed_official	324:406fd2029f23	2046	/@{/
mbed_official	324:406fd2029f23	2047	#define BP_FTM_OUTMASK_CH7OM (7U) /!< Bit position for FTM_OUTMASK_CH7OM. /
mbed_official	324:406fd2029f23	2048	#define BM_FTM_OUTMASK_CH7OM (0x00000080U) /!< Bit mask for FTM_OUTMASK_CH7OM. /
mbed_official	324:406fd2029f23	2049	#define BS_FTM_OUTMASK_CH7OM (1U) /!< Bit field size in bits for FTM_OUTMASK_CH7OM. /
mbed_official	324:406fd2029f23	2050
mbed_official	324:406fd2029f23	2051	/! @brief Read current value of the FTM_OUTMASK_CH7OM field. /
mbed_official	324:406fd2029f23	2052	#define BR_FTM_OUTMASK_CH7OM(x) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM))
mbed_official	324:406fd2029f23	2053
mbed_official	324:406fd2029f23	2054	/! @brief Format value for bitfield FTM_OUTMASK_CH7OM. /
mbed_official	324:406fd2029f23	2055	#define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
mbed_official	324:406fd2029f23	2056
mbed_official	324:406fd2029f23	2057	/! @brief Set the CH7OM field to a new value. /
mbed_official	324:406fd2029f23	2058	#define BW_FTM_OUTMASK_CH7OM(x, v) (BITBAND_ACCESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM) = (v))
mbed_official	324:406fd2029f23	2059	/@}/
mbed_official	324:406fd2029f23	2060
mbed_official	324:406fd2029f23	2061	/*******************************************************************************
mbed_official	324:406fd2029f23	2062	* HW_FTM_COMBINE - Function For Linked Channels
mbed_official	324:406fd2029f23	2063	******************************************************************************/
mbed_official	324:406fd2029f23	2064
mbed_official	324:406fd2029f23	2065	/*!
mbed_official	324:406fd2029f23	2066	* @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
mbed_official	324:406fd2029f23	2067	*
mbed_official	324:406fd2029f23	2068	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2069	*
mbed_official	324:406fd2029f23	2070	* This register contains the control bits used to configure the fault control,
mbed_official	324:406fd2029f23	2071	* synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
mbed_official	324:406fd2029f23	2072	* and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
mbed_official	324:406fd2029f23	2073	* 4, and 6.
mbed_official	324:406fd2029f23	2074	*/
mbed_official	324:406fd2029f23	2075	typedef union _hw_ftm_combine
mbed_official	324:406fd2029f23	2076	{
mbed_official	324:406fd2029f23	2077	uint32_t U;
mbed_official	324:406fd2029f23	2078	struct _hw_ftm_combine_bitfields
mbed_official	324:406fd2029f23	2079	{
mbed_official	324:406fd2029f23	2080	uint32_t COMBINE0 : 1; /!< [0] Combine Channels For n = 0 /
mbed_official	324:406fd2029f23	2081	uint32_t COMP0 : 1; /!< [1] Complement Of Channel (n) For n = 0 /
mbed_official	324:406fd2029f23	2082	uint32_t DECAPEN0 : 1; /*!< [2] Dual Edge Capture Mode Enable For n =
mbed_official	324:406fd2029f23	2083	* 0 */
mbed_official	324:406fd2029f23	2084	uint32_t DECAP0 : 1; /*!< [3] Dual Edge Capture Mode Captures For n =
mbed_official	324:406fd2029f23	2085	* 0 */
mbed_official	324:406fd2029f23	2086	uint32_t DTEN0 : 1; /!< [4] Deadtime Enable For n = 0 /
mbed_official	324:406fd2029f23	2087	uint32_t SYNCEN0 : 1; /!< [5] Synchronization Enable For n = 0 /
mbed_official	324:406fd2029f23	2088	uint32_t FAULTEN0 : 1; /!< [6] Fault Control Enable For n = 0 /
mbed_official	324:406fd2029f23	2089	uint32_t RESERVED0 : 1; /!< [7] /
mbed_official	324:406fd2029f23	2090	uint32_t COMBINE1 : 1; /!< [8] Combine Channels For n = 2 /
mbed_official	324:406fd2029f23	2091	uint32_t COMP1 : 1; /!< [9] Complement Of Channel (n) For n = 2 /
mbed_official	324:406fd2029f23	2092	uint32_t DECAPEN1 : 1; /*!< [10] Dual Edge Capture Mode Enable For n
mbed_official	324:406fd2029f23	2093	* = 2 */
mbed_official	324:406fd2029f23	2094	uint32_t DECAP1 : 1; /*!< [11] Dual Edge Capture Mode Captures For n
mbed_official	324:406fd2029f23	2095	* = 2 */
mbed_official	324:406fd2029f23	2096	uint32_t DTEN1 : 1; /!< [12] Deadtime Enable For n = 2 /
mbed_official	324:406fd2029f23	2097	uint32_t SYNCEN1 : 1; /!< [13] Synchronization Enable For n = 2 /
mbed_official	324:406fd2029f23	2098	uint32_t FAULTEN1 : 1; /!< [14] Fault Control Enable For n = 2 /
mbed_official	324:406fd2029f23	2099	uint32_t RESERVED1 : 1; /!< [15] /
mbed_official	324:406fd2029f23	2100	uint32_t COMBINE2 : 1; /!< [16] Combine Channels For n = 4 /
mbed_official	324:406fd2029f23	2101	uint32_t COMP2 : 1; /!< [17] Complement Of Channel (n) For n = 4 /
mbed_official	324:406fd2029f23	2102	uint32_t DECAPEN2 : 1; /*!< [18] Dual Edge Capture Mode Enable For n
mbed_official	324:406fd2029f23	2103	* = 4 */
mbed_official	324:406fd2029f23	2104	uint32_t DECAP2 : 1; /*!< [19] Dual Edge Capture Mode Captures For n
mbed_official	324:406fd2029f23	2105	* = 4 */
mbed_official	324:406fd2029f23	2106	uint32_t DTEN2 : 1; /!< [20] Deadtime Enable For n = 4 /
mbed_official	324:406fd2029f23	2107	uint32_t SYNCEN2 : 1; /!< [21] Synchronization Enable For n = 4 /
mbed_official	324:406fd2029f23	2108	uint32_t FAULTEN2 : 1; /!< [22] Fault Control Enable For n = 4 /
mbed_official	324:406fd2029f23	2109	uint32_t RESERVED2 : 1; /!< [23] /
mbed_official	324:406fd2029f23	2110	uint32_t COMBINE3 : 1; /!< [24] Combine Channels For n = 6 /
mbed_official	324:406fd2029f23	2111	uint32_t COMP3 : 1; /!< [25] Complement Of Channel (n) for n = 6 /
mbed_official	324:406fd2029f23	2112	uint32_t DECAPEN3 : 1; /*!< [26] Dual Edge Capture Mode Enable For n
mbed_official	324:406fd2029f23	2113	* = 6 */
mbed_official	324:406fd2029f23	2114	uint32_t DECAP3 : 1; /*!< [27] Dual Edge Capture Mode Captures For n
mbed_official	324:406fd2029f23	2115	* = 6 */
mbed_official	324:406fd2029f23	2116	uint32_t DTEN3 : 1; /!< [28] Deadtime Enable For n = 6 /
mbed_official	324:406fd2029f23	2117	uint32_t SYNCEN3 : 1; /!< [29] Synchronization Enable For n = 6 /
mbed_official	324:406fd2029f23	2118	uint32_t FAULTEN3 : 1; /!< [30] Fault Control Enable For n = 6 /
mbed_official	324:406fd2029f23	2119	uint32_t RESERVED3 : 1; /!< [31] /
mbed_official	324:406fd2029f23	2120	} B;
mbed_official	324:406fd2029f23	2121	} hw_ftm_combine_t;
mbed_official	324:406fd2029f23	2122
mbed_official	324:406fd2029f23	2123	/*!
mbed_official	324:406fd2029f23	2124	* @name Constants and macros for entire FTM_COMBINE register
mbed_official	324:406fd2029f23	2125	*/
mbed_official	324:406fd2029f23	2126	/@{/
mbed_official	324:406fd2029f23	2127	#define HW_FTM_COMBINE_ADDR(x) ((x) + 0x64U)
mbed_official	324:406fd2029f23	2128
mbed_official	324:406fd2029f23	2129	#define HW_FTM_COMBINE(x) ((__IO hw_ftm_combine_t ) HW_FTM_COMBINE_ADDR(x))
mbed_official	324:406fd2029f23	2130	#define HW_FTM_COMBINE_RD(x) (HW_FTM_COMBINE(x).U)
mbed_official	324:406fd2029f23	2131	#define HW_FTM_COMBINE_WR(x, v) (HW_FTM_COMBINE(x).U = (v))
mbed_official	324:406fd2029f23	2132	#define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2133	#define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2134	#define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2135	/@}/
mbed_official	324:406fd2029f23	2136
mbed_official	324:406fd2029f23	2137	/*
mbed_official	324:406fd2029f23	2138	* Constants & macros for individual FTM_COMBINE bitfields
mbed_official	324:406fd2029f23	2139	*/
mbed_official	324:406fd2029f23	2140
mbed_official	324:406fd2029f23	2141	/*!
mbed_official	324:406fd2029f23	2142	* @name Register FTM_COMBINE, field COMBINE0[0] (RW)
mbed_official	324:406fd2029f23	2143	*
mbed_official	324:406fd2029f23	2144	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2145	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2146	*
mbed_official	324:406fd2029f23	2147	* Values:
mbed_official	324:406fd2029f23	2148	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	324:406fd2029f23	2149	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	324:406fd2029f23	2150	*/
mbed_official	324:406fd2029f23	2151	/@{/
mbed_official	324:406fd2029f23	2152	#define BP_FTM_COMBINE_COMBINE0 (0U) /!< Bit position for FTM_COMBINE_COMBINE0. /
mbed_official	324:406fd2029f23	2153	#define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /!< Bit mask for FTM_COMBINE_COMBINE0. /
mbed_official	324:406fd2029f23	2154	#define BS_FTM_COMBINE_COMBINE0 (1U) /!< Bit field size in bits for FTM_COMBINE_COMBINE0. /
mbed_official	324:406fd2029f23	2155
mbed_official	324:406fd2029f23	2156	/! @brief Read current value of the FTM_COMBINE_COMBINE0 field. /
mbed_official	324:406fd2029f23	2157	#define BR_FTM_COMBINE_COMBINE0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0))
mbed_official	324:406fd2029f23	2158
mbed_official	324:406fd2029f23	2159	/! @brief Format value for bitfield FTM_COMBINE_COMBINE0. /
mbed_official	324:406fd2029f23	2160	#define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
mbed_official	324:406fd2029f23	2161
mbed_official	324:406fd2029f23	2162	/! @brief Set the COMBINE0 field to a new value. /
mbed_official	324:406fd2029f23	2163	#define BW_FTM_COMBINE_COMBINE0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0) = (v))
mbed_official	324:406fd2029f23	2164	/@}/
mbed_official	324:406fd2029f23	2165
mbed_official	324:406fd2029f23	2166	/*!
mbed_official	324:406fd2029f23	2167	* @name Register FTM_COMBINE, field COMP0[1] (RW)
mbed_official	324:406fd2029f23	2168	*
mbed_official	324:406fd2029f23	2169	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	324:406fd2029f23	2170	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	324:406fd2029f23	2171	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2172	*
mbed_official	324:406fd2029f23	2173	* Values:
mbed_official	324:406fd2029f23	2174	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	324:406fd2029f23	2175	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	324:406fd2029f23	2176	*/
mbed_official	324:406fd2029f23	2177	/@{/
mbed_official	324:406fd2029f23	2178	#define BP_FTM_COMBINE_COMP0 (1U) /!< Bit position for FTM_COMBINE_COMP0. /
mbed_official	324:406fd2029f23	2179	#define BM_FTM_COMBINE_COMP0 (0x00000002U) /!< Bit mask for FTM_COMBINE_COMP0. /
mbed_official	324:406fd2029f23	2180	#define BS_FTM_COMBINE_COMP0 (1U) /!< Bit field size in bits for FTM_COMBINE_COMP0. /
mbed_official	324:406fd2029f23	2181
mbed_official	324:406fd2029f23	2182	/! @brief Read current value of the FTM_COMBINE_COMP0 field. /
mbed_official	324:406fd2029f23	2183	#define BR_FTM_COMBINE_COMP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0))
mbed_official	324:406fd2029f23	2184
mbed_official	324:406fd2029f23	2185	/! @brief Format value for bitfield FTM_COMBINE_COMP0. /
mbed_official	324:406fd2029f23	2186	#define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
mbed_official	324:406fd2029f23	2187
mbed_official	324:406fd2029f23	2188	/! @brief Set the COMP0 field to a new value. /
mbed_official	324:406fd2029f23	2189	#define BW_FTM_COMBINE_COMP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0) = (v))
mbed_official	324:406fd2029f23	2190	/@}/
mbed_official	324:406fd2029f23	2191
mbed_official	324:406fd2029f23	2192	/*!
mbed_official	324:406fd2029f23	2193	* @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
mbed_official	324:406fd2029f23	2194	*
mbed_official	324:406fd2029f23	2195	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	324:406fd2029f23	2196	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	324:406fd2029f23	2197	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	324:406fd2029f23	2198	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	324:406fd2029f23	2199	* MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2200	*
mbed_official	324:406fd2029f23	2201	* Values:
mbed_official	324:406fd2029f23	2202	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2203	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2204	*/
mbed_official	324:406fd2029f23	2205	/@{/
mbed_official	324:406fd2029f23	2206	#define BP_FTM_COMBINE_DECAPEN0 (2U) /!< Bit position for FTM_COMBINE_DECAPEN0. /
mbed_official	324:406fd2029f23	2207	#define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /!< Bit mask for FTM_COMBINE_DECAPEN0. /
mbed_official	324:406fd2029f23	2208	#define BS_FTM_COMBINE_DECAPEN0 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAPEN0. /
mbed_official	324:406fd2029f23	2209
mbed_official	324:406fd2029f23	2210	/! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. /
mbed_official	324:406fd2029f23	2211	#define BR_FTM_COMBINE_DECAPEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0))
mbed_official	324:406fd2029f23	2212
mbed_official	324:406fd2029f23	2213	/! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. /
mbed_official	324:406fd2029f23	2214	#define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
mbed_official	324:406fd2029f23	2215
mbed_official	324:406fd2029f23	2216	/! @brief Set the DECAPEN0 field to a new value. /
mbed_official	324:406fd2029f23	2217	#define BW_FTM_COMBINE_DECAPEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0) = (v))
mbed_official	324:406fd2029f23	2218	/@}/
mbed_official	324:406fd2029f23	2219
mbed_official	324:406fd2029f23	2220	/*!
mbed_official	324:406fd2029f23	2221	* @name Register FTM_COMBINE, field DECAP0[3] (RW)
mbed_official	324:406fd2029f23	2222	*
mbed_official	324:406fd2029f23	2223	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	324:406fd2029f23	2224	* input event and the configuration of the dual edge capture bits. This field
mbed_official	324:406fd2029f23	2225	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	324:406fd2029f23	2226	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	324:406fd2029f23	2227	* of channel (n+1) event is made.
mbed_official	324:406fd2029f23	2228	*
mbed_official	324:406fd2029f23	2229	* Values:
mbed_official	324:406fd2029f23	2230	* - 0 - The dual edge captures are inactive.
mbed_official	324:406fd2029f23	2231	* - 1 - The dual edge captures are active.
mbed_official	324:406fd2029f23	2232	*/
mbed_official	324:406fd2029f23	2233	/@{/
mbed_official	324:406fd2029f23	2234	#define BP_FTM_COMBINE_DECAP0 (3U) /!< Bit position for FTM_COMBINE_DECAP0. /
mbed_official	324:406fd2029f23	2235	#define BM_FTM_COMBINE_DECAP0 (0x00000008U) /!< Bit mask for FTM_COMBINE_DECAP0. /
mbed_official	324:406fd2029f23	2236	#define BS_FTM_COMBINE_DECAP0 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAP0. /
mbed_official	324:406fd2029f23	2237
mbed_official	324:406fd2029f23	2238	/! @brief Read current value of the FTM_COMBINE_DECAP0 field. /
mbed_official	324:406fd2029f23	2239	#define BR_FTM_COMBINE_DECAP0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0))
mbed_official	324:406fd2029f23	2240
mbed_official	324:406fd2029f23	2241	/! @brief Format value for bitfield FTM_COMBINE_DECAP0. /
mbed_official	324:406fd2029f23	2242	#define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
mbed_official	324:406fd2029f23	2243
mbed_official	324:406fd2029f23	2244	/! @brief Set the DECAP0 field to a new value. /
mbed_official	324:406fd2029f23	2245	#define BW_FTM_COMBINE_DECAP0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0) = (v))
mbed_official	324:406fd2029f23	2246	/@}/
mbed_official	324:406fd2029f23	2247
mbed_official	324:406fd2029f23	2248	/*!
mbed_official	324:406fd2029f23	2249	* @name Register FTM_COMBINE, field DTEN0[4] (RW)
mbed_official	324:406fd2029f23	2250	*
mbed_official	324:406fd2029f23	2251	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	324:406fd2029f23	2252	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2253	*
mbed_official	324:406fd2029f23	2254	* Values:
mbed_official	324:406fd2029f23	2255	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2256	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2257	*/
mbed_official	324:406fd2029f23	2258	/@{/
mbed_official	324:406fd2029f23	2259	#define BP_FTM_COMBINE_DTEN0 (4U) /!< Bit position for FTM_COMBINE_DTEN0. /
mbed_official	324:406fd2029f23	2260	#define BM_FTM_COMBINE_DTEN0 (0x00000010U) /!< Bit mask for FTM_COMBINE_DTEN0. /
mbed_official	324:406fd2029f23	2261	#define BS_FTM_COMBINE_DTEN0 (1U) /!< Bit field size in bits for FTM_COMBINE_DTEN0. /
mbed_official	324:406fd2029f23	2262
mbed_official	324:406fd2029f23	2263	/! @brief Read current value of the FTM_COMBINE_DTEN0 field. /
mbed_official	324:406fd2029f23	2264	#define BR_FTM_COMBINE_DTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0))
mbed_official	324:406fd2029f23	2265
mbed_official	324:406fd2029f23	2266	/! @brief Format value for bitfield FTM_COMBINE_DTEN0. /
mbed_official	324:406fd2029f23	2267	#define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
mbed_official	324:406fd2029f23	2268
mbed_official	324:406fd2029f23	2269	/! @brief Set the DTEN0 field to a new value. /
mbed_official	324:406fd2029f23	2270	#define BW_FTM_COMBINE_DTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0) = (v))
mbed_official	324:406fd2029f23	2271	/@}/
mbed_official	324:406fd2029f23	2272
mbed_official	324:406fd2029f23	2273	/*!
mbed_official	324:406fd2029f23	2274	* @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
mbed_official	324:406fd2029f23	2275	*
mbed_official	324:406fd2029f23	2276	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	324:406fd2029f23	2277	*
mbed_official	324:406fd2029f23	2278	* Values:
mbed_official	324:406fd2029f23	2279	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2280	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2281	*/
mbed_official	324:406fd2029f23	2282	/@{/
mbed_official	324:406fd2029f23	2283	#define BP_FTM_COMBINE_SYNCEN0 (5U) /!< Bit position for FTM_COMBINE_SYNCEN0. /
mbed_official	324:406fd2029f23	2284	#define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /!< Bit mask for FTM_COMBINE_SYNCEN0. /
mbed_official	324:406fd2029f23	2285	#define BS_FTM_COMBINE_SYNCEN0 (1U) /!< Bit field size in bits for FTM_COMBINE_SYNCEN0. /
mbed_official	324:406fd2029f23	2286
mbed_official	324:406fd2029f23	2287	/! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. /
mbed_official	324:406fd2029f23	2288	#define BR_FTM_COMBINE_SYNCEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0))
mbed_official	324:406fd2029f23	2289
mbed_official	324:406fd2029f23	2290	/! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. /
mbed_official	324:406fd2029f23	2291	#define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
mbed_official	324:406fd2029f23	2292
mbed_official	324:406fd2029f23	2293	/! @brief Set the SYNCEN0 field to a new value. /
mbed_official	324:406fd2029f23	2294	#define BW_FTM_COMBINE_SYNCEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0) = (v))
mbed_official	324:406fd2029f23	2295	/@}/
mbed_official	324:406fd2029f23	2296
mbed_official	324:406fd2029f23	2297	/*!
mbed_official	324:406fd2029f23	2298	* @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
mbed_official	324:406fd2029f23	2299	*
mbed_official	324:406fd2029f23	2300	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2301	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2302	*
mbed_official	324:406fd2029f23	2303	* Values:
mbed_official	324:406fd2029f23	2304	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2305	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2306	*/
mbed_official	324:406fd2029f23	2307	/@{/
mbed_official	324:406fd2029f23	2308	#define BP_FTM_COMBINE_FAULTEN0 (6U) /!< Bit position for FTM_COMBINE_FAULTEN0. /
mbed_official	324:406fd2029f23	2309	#define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /!< Bit mask for FTM_COMBINE_FAULTEN0. /
mbed_official	324:406fd2029f23	2310	#define BS_FTM_COMBINE_FAULTEN0 (1U) /!< Bit field size in bits for FTM_COMBINE_FAULTEN0. /
mbed_official	324:406fd2029f23	2311
mbed_official	324:406fd2029f23	2312	/! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. /
mbed_official	324:406fd2029f23	2313	#define BR_FTM_COMBINE_FAULTEN0(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0))
mbed_official	324:406fd2029f23	2314
mbed_official	324:406fd2029f23	2315	/! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. /
mbed_official	324:406fd2029f23	2316	#define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
mbed_official	324:406fd2029f23	2317
mbed_official	324:406fd2029f23	2318	/! @brief Set the FAULTEN0 field to a new value. /
mbed_official	324:406fd2029f23	2319	#define BW_FTM_COMBINE_FAULTEN0(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0) = (v))
mbed_official	324:406fd2029f23	2320	/@}/
mbed_official	324:406fd2029f23	2321
mbed_official	324:406fd2029f23	2322	/*!
mbed_official	324:406fd2029f23	2323	* @name Register FTM_COMBINE, field COMBINE1[8] (RW)
mbed_official	324:406fd2029f23	2324	*
mbed_official	324:406fd2029f23	2325	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2326	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2327	*
mbed_official	324:406fd2029f23	2328	* Values:
mbed_official	324:406fd2029f23	2329	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	324:406fd2029f23	2330	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	324:406fd2029f23	2331	*/
mbed_official	324:406fd2029f23	2332	/@{/
mbed_official	324:406fd2029f23	2333	#define BP_FTM_COMBINE_COMBINE1 (8U) /!< Bit position for FTM_COMBINE_COMBINE1. /
mbed_official	324:406fd2029f23	2334	#define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /!< Bit mask for FTM_COMBINE_COMBINE1. /
mbed_official	324:406fd2029f23	2335	#define BS_FTM_COMBINE_COMBINE1 (1U) /!< Bit field size in bits for FTM_COMBINE_COMBINE1. /
mbed_official	324:406fd2029f23	2336
mbed_official	324:406fd2029f23	2337	/! @brief Read current value of the FTM_COMBINE_COMBINE1 field. /
mbed_official	324:406fd2029f23	2338	#define BR_FTM_COMBINE_COMBINE1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1))
mbed_official	324:406fd2029f23	2339
mbed_official	324:406fd2029f23	2340	/! @brief Format value for bitfield FTM_COMBINE_COMBINE1. /
mbed_official	324:406fd2029f23	2341	#define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
mbed_official	324:406fd2029f23	2342
mbed_official	324:406fd2029f23	2343	/! @brief Set the COMBINE1 field to a new value. /
mbed_official	324:406fd2029f23	2344	#define BW_FTM_COMBINE_COMBINE1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1) = (v))
mbed_official	324:406fd2029f23	2345	/@}/
mbed_official	324:406fd2029f23	2346
mbed_official	324:406fd2029f23	2347	/*!
mbed_official	324:406fd2029f23	2348	* @name Register FTM_COMBINE, field COMP1[9] (RW)
mbed_official	324:406fd2029f23	2349	*
mbed_official	324:406fd2029f23	2350	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	324:406fd2029f23	2351	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	324:406fd2029f23	2352	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2353	*
mbed_official	324:406fd2029f23	2354	* Values:
mbed_official	324:406fd2029f23	2355	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	324:406fd2029f23	2356	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	324:406fd2029f23	2357	*/
mbed_official	324:406fd2029f23	2358	/@{/
mbed_official	324:406fd2029f23	2359	#define BP_FTM_COMBINE_COMP1 (9U) /!< Bit position for FTM_COMBINE_COMP1. /
mbed_official	324:406fd2029f23	2360	#define BM_FTM_COMBINE_COMP1 (0x00000200U) /!< Bit mask for FTM_COMBINE_COMP1. /
mbed_official	324:406fd2029f23	2361	#define BS_FTM_COMBINE_COMP1 (1U) /!< Bit field size in bits for FTM_COMBINE_COMP1. /
mbed_official	324:406fd2029f23	2362
mbed_official	324:406fd2029f23	2363	/! @brief Read current value of the FTM_COMBINE_COMP1 field. /
mbed_official	324:406fd2029f23	2364	#define BR_FTM_COMBINE_COMP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1))
mbed_official	324:406fd2029f23	2365
mbed_official	324:406fd2029f23	2366	/! @brief Format value for bitfield FTM_COMBINE_COMP1. /
mbed_official	324:406fd2029f23	2367	#define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
mbed_official	324:406fd2029f23	2368
mbed_official	324:406fd2029f23	2369	/! @brief Set the COMP1 field to a new value. /
mbed_official	324:406fd2029f23	2370	#define BW_FTM_COMBINE_COMP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1) = (v))
mbed_official	324:406fd2029f23	2371	/@}/
mbed_official	324:406fd2029f23	2372
mbed_official	324:406fd2029f23	2373	/*!
mbed_official	324:406fd2029f23	2374	* @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
mbed_official	324:406fd2029f23	2375	*
mbed_official	324:406fd2029f23	2376	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	324:406fd2029f23	2377	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	324:406fd2029f23	2378	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	324:406fd2029f23	2379	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	324:406fd2029f23	2380	* MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2381	*
mbed_official	324:406fd2029f23	2382	* Values:
mbed_official	324:406fd2029f23	2383	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2384	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2385	*/
mbed_official	324:406fd2029f23	2386	/@{/
mbed_official	324:406fd2029f23	2387	#define BP_FTM_COMBINE_DECAPEN1 (10U) /!< Bit position for FTM_COMBINE_DECAPEN1. /
mbed_official	324:406fd2029f23	2388	#define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /!< Bit mask for FTM_COMBINE_DECAPEN1. /
mbed_official	324:406fd2029f23	2389	#define BS_FTM_COMBINE_DECAPEN1 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAPEN1. /
mbed_official	324:406fd2029f23	2390
mbed_official	324:406fd2029f23	2391	/! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. /
mbed_official	324:406fd2029f23	2392	#define BR_FTM_COMBINE_DECAPEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1))
mbed_official	324:406fd2029f23	2393
mbed_official	324:406fd2029f23	2394	/! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. /
mbed_official	324:406fd2029f23	2395	#define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
mbed_official	324:406fd2029f23	2396
mbed_official	324:406fd2029f23	2397	/! @brief Set the DECAPEN1 field to a new value. /
mbed_official	324:406fd2029f23	2398	#define BW_FTM_COMBINE_DECAPEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1) = (v))
mbed_official	324:406fd2029f23	2399	/@}/
mbed_official	324:406fd2029f23	2400
mbed_official	324:406fd2029f23	2401	/*!
mbed_official	324:406fd2029f23	2402	* @name Register FTM_COMBINE, field DECAP1[11] (RW)
mbed_official	324:406fd2029f23	2403	*
mbed_official	324:406fd2029f23	2404	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	324:406fd2029f23	2405	* input event and the configuration of the dual edge capture bits. This field
mbed_official	324:406fd2029f23	2406	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	324:406fd2029f23	2407	* hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
mbed_official	324:406fd2029f23	2408	* of channel (n+1) event is made.
mbed_official	324:406fd2029f23	2409	*
mbed_official	324:406fd2029f23	2410	* Values:
mbed_official	324:406fd2029f23	2411	* - 0 - The dual edge captures are inactive.
mbed_official	324:406fd2029f23	2412	* - 1 - The dual edge captures are active.
mbed_official	324:406fd2029f23	2413	*/
mbed_official	324:406fd2029f23	2414	/@{/
mbed_official	324:406fd2029f23	2415	#define BP_FTM_COMBINE_DECAP1 (11U) /!< Bit position for FTM_COMBINE_DECAP1. /
mbed_official	324:406fd2029f23	2416	#define BM_FTM_COMBINE_DECAP1 (0x00000800U) /!< Bit mask for FTM_COMBINE_DECAP1. /
mbed_official	324:406fd2029f23	2417	#define BS_FTM_COMBINE_DECAP1 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAP1. /
mbed_official	324:406fd2029f23	2418
mbed_official	324:406fd2029f23	2419	/! @brief Read current value of the FTM_COMBINE_DECAP1 field. /
mbed_official	324:406fd2029f23	2420	#define BR_FTM_COMBINE_DECAP1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1))
mbed_official	324:406fd2029f23	2421
mbed_official	324:406fd2029f23	2422	/! @brief Format value for bitfield FTM_COMBINE_DECAP1. /
mbed_official	324:406fd2029f23	2423	#define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
mbed_official	324:406fd2029f23	2424
mbed_official	324:406fd2029f23	2425	/! @brief Set the DECAP1 field to a new value. /
mbed_official	324:406fd2029f23	2426	#define BW_FTM_COMBINE_DECAP1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1) = (v))
mbed_official	324:406fd2029f23	2427	/@}/
mbed_official	324:406fd2029f23	2428
mbed_official	324:406fd2029f23	2429	/*!
mbed_official	324:406fd2029f23	2430	* @name Register FTM_COMBINE, field DTEN1[12] (RW)
mbed_official	324:406fd2029f23	2431	*
mbed_official	324:406fd2029f23	2432	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	324:406fd2029f23	2433	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2434	*
mbed_official	324:406fd2029f23	2435	* Values:
mbed_official	324:406fd2029f23	2436	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2437	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2438	*/
mbed_official	324:406fd2029f23	2439	/@{/
mbed_official	324:406fd2029f23	2440	#define BP_FTM_COMBINE_DTEN1 (12U) /!< Bit position for FTM_COMBINE_DTEN1. /
mbed_official	324:406fd2029f23	2441	#define BM_FTM_COMBINE_DTEN1 (0x00001000U) /!< Bit mask for FTM_COMBINE_DTEN1. /
mbed_official	324:406fd2029f23	2442	#define BS_FTM_COMBINE_DTEN1 (1U) /!< Bit field size in bits for FTM_COMBINE_DTEN1. /
mbed_official	324:406fd2029f23	2443
mbed_official	324:406fd2029f23	2444	/! @brief Read current value of the FTM_COMBINE_DTEN1 field. /
mbed_official	324:406fd2029f23	2445	#define BR_FTM_COMBINE_DTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1))
mbed_official	324:406fd2029f23	2446
mbed_official	324:406fd2029f23	2447	/! @brief Format value for bitfield FTM_COMBINE_DTEN1. /
mbed_official	324:406fd2029f23	2448	#define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
mbed_official	324:406fd2029f23	2449
mbed_official	324:406fd2029f23	2450	/! @brief Set the DTEN1 field to a new value. /
mbed_official	324:406fd2029f23	2451	#define BW_FTM_COMBINE_DTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1) = (v))
mbed_official	324:406fd2029f23	2452	/@}/
mbed_official	324:406fd2029f23	2453
mbed_official	324:406fd2029f23	2454	/*!
mbed_official	324:406fd2029f23	2455	* @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
mbed_official	324:406fd2029f23	2456	*
mbed_official	324:406fd2029f23	2457	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	324:406fd2029f23	2458	*
mbed_official	324:406fd2029f23	2459	* Values:
mbed_official	324:406fd2029f23	2460	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2461	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2462	*/
mbed_official	324:406fd2029f23	2463	/@{/
mbed_official	324:406fd2029f23	2464	#define BP_FTM_COMBINE_SYNCEN1 (13U) /!< Bit position for FTM_COMBINE_SYNCEN1. /
mbed_official	324:406fd2029f23	2465	#define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /!< Bit mask for FTM_COMBINE_SYNCEN1. /
mbed_official	324:406fd2029f23	2466	#define BS_FTM_COMBINE_SYNCEN1 (1U) /!< Bit field size in bits for FTM_COMBINE_SYNCEN1. /
mbed_official	324:406fd2029f23	2467
mbed_official	324:406fd2029f23	2468	/! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. /
mbed_official	324:406fd2029f23	2469	#define BR_FTM_COMBINE_SYNCEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1))
mbed_official	324:406fd2029f23	2470
mbed_official	324:406fd2029f23	2471	/! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. /
mbed_official	324:406fd2029f23	2472	#define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
mbed_official	324:406fd2029f23	2473
mbed_official	324:406fd2029f23	2474	/! @brief Set the SYNCEN1 field to a new value. /
mbed_official	324:406fd2029f23	2475	#define BW_FTM_COMBINE_SYNCEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1) = (v))
mbed_official	324:406fd2029f23	2476	/@}/
mbed_official	324:406fd2029f23	2477
mbed_official	324:406fd2029f23	2478	/*!
mbed_official	324:406fd2029f23	2479	* @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
mbed_official	324:406fd2029f23	2480	*
mbed_official	324:406fd2029f23	2481	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2482	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2483	*
mbed_official	324:406fd2029f23	2484	* Values:
mbed_official	324:406fd2029f23	2485	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2486	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2487	*/
mbed_official	324:406fd2029f23	2488	/@{/
mbed_official	324:406fd2029f23	2489	#define BP_FTM_COMBINE_FAULTEN1 (14U) /!< Bit position for FTM_COMBINE_FAULTEN1. /
mbed_official	324:406fd2029f23	2490	#define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /!< Bit mask for FTM_COMBINE_FAULTEN1. /
mbed_official	324:406fd2029f23	2491	#define BS_FTM_COMBINE_FAULTEN1 (1U) /!< Bit field size in bits for FTM_COMBINE_FAULTEN1. /
mbed_official	324:406fd2029f23	2492
mbed_official	324:406fd2029f23	2493	/! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. /
mbed_official	324:406fd2029f23	2494	#define BR_FTM_COMBINE_FAULTEN1(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1))
mbed_official	324:406fd2029f23	2495
mbed_official	324:406fd2029f23	2496	/! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. /
mbed_official	324:406fd2029f23	2497	#define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
mbed_official	324:406fd2029f23	2498
mbed_official	324:406fd2029f23	2499	/! @brief Set the FAULTEN1 field to a new value. /
mbed_official	324:406fd2029f23	2500	#define BW_FTM_COMBINE_FAULTEN1(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1) = (v))
mbed_official	324:406fd2029f23	2501	/@}/
mbed_official	324:406fd2029f23	2502
mbed_official	324:406fd2029f23	2503	/*!
mbed_official	324:406fd2029f23	2504	* @name Register FTM_COMBINE, field COMBINE2[16] (RW)
mbed_official	324:406fd2029f23	2505	*
mbed_official	324:406fd2029f23	2506	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2507	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2508	*
mbed_official	324:406fd2029f23	2509	* Values:
mbed_official	324:406fd2029f23	2510	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	324:406fd2029f23	2511	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	324:406fd2029f23	2512	*/
mbed_official	324:406fd2029f23	2513	/@{/
mbed_official	324:406fd2029f23	2514	#define BP_FTM_COMBINE_COMBINE2 (16U) /!< Bit position for FTM_COMBINE_COMBINE2. /
mbed_official	324:406fd2029f23	2515	#define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /!< Bit mask for FTM_COMBINE_COMBINE2. /
mbed_official	324:406fd2029f23	2516	#define BS_FTM_COMBINE_COMBINE2 (1U) /!< Bit field size in bits for FTM_COMBINE_COMBINE2. /
mbed_official	324:406fd2029f23	2517
mbed_official	324:406fd2029f23	2518	/! @brief Read current value of the FTM_COMBINE_COMBINE2 field. /
mbed_official	324:406fd2029f23	2519	#define BR_FTM_COMBINE_COMBINE2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2))
mbed_official	324:406fd2029f23	2520
mbed_official	324:406fd2029f23	2521	/! @brief Format value for bitfield FTM_COMBINE_COMBINE2. /
mbed_official	324:406fd2029f23	2522	#define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
mbed_official	324:406fd2029f23	2523
mbed_official	324:406fd2029f23	2524	/! @brief Set the COMBINE2 field to a new value. /
mbed_official	324:406fd2029f23	2525	#define BW_FTM_COMBINE_COMBINE2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2) = (v))
mbed_official	324:406fd2029f23	2526	/@}/
mbed_official	324:406fd2029f23	2527
mbed_official	324:406fd2029f23	2528	/*!
mbed_official	324:406fd2029f23	2529	* @name Register FTM_COMBINE, field COMP2[17] (RW)
mbed_official	324:406fd2029f23	2530	*
mbed_official	324:406fd2029f23	2531	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	324:406fd2029f23	2532	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	324:406fd2029f23	2533	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2534	*
mbed_official	324:406fd2029f23	2535	* Values:
mbed_official	324:406fd2029f23	2536	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	324:406fd2029f23	2537	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	324:406fd2029f23	2538	*/
mbed_official	324:406fd2029f23	2539	/@{/
mbed_official	324:406fd2029f23	2540	#define BP_FTM_COMBINE_COMP2 (17U) /!< Bit position for FTM_COMBINE_COMP2. /
mbed_official	324:406fd2029f23	2541	#define BM_FTM_COMBINE_COMP2 (0x00020000U) /!< Bit mask for FTM_COMBINE_COMP2. /
mbed_official	324:406fd2029f23	2542	#define BS_FTM_COMBINE_COMP2 (1U) /!< Bit field size in bits for FTM_COMBINE_COMP2. /
mbed_official	324:406fd2029f23	2543
mbed_official	324:406fd2029f23	2544	/! @brief Read current value of the FTM_COMBINE_COMP2 field. /
mbed_official	324:406fd2029f23	2545	#define BR_FTM_COMBINE_COMP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2))
mbed_official	324:406fd2029f23	2546
mbed_official	324:406fd2029f23	2547	/! @brief Format value for bitfield FTM_COMBINE_COMP2. /
mbed_official	324:406fd2029f23	2548	#define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
mbed_official	324:406fd2029f23	2549
mbed_official	324:406fd2029f23	2550	/! @brief Set the COMP2 field to a new value. /
mbed_official	324:406fd2029f23	2551	#define BW_FTM_COMBINE_COMP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2) = (v))
mbed_official	324:406fd2029f23	2552	/@}/
mbed_official	324:406fd2029f23	2553
mbed_official	324:406fd2029f23	2554	/*!
mbed_official	324:406fd2029f23	2555	* @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
mbed_official	324:406fd2029f23	2556	*
mbed_official	324:406fd2029f23	2557	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	324:406fd2029f23	2558	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	324:406fd2029f23	2559	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	324:406fd2029f23	2560	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	324:406fd2029f23	2561	* MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2562	*
mbed_official	324:406fd2029f23	2563	* Values:
mbed_official	324:406fd2029f23	2564	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2565	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2566	*/
mbed_official	324:406fd2029f23	2567	/@{/
mbed_official	324:406fd2029f23	2568	#define BP_FTM_COMBINE_DECAPEN2 (18U) /!< Bit position for FTM_COMBINE_DECAPEN2. /
mbed_official	324:406fd2029f23	2569	#define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /!< Bit mask for FTM_COMBINE_DECAPEN2. /
mbed_official	324:406fd2029f23	2570	#define BS_FTM_COMBINE_DECAPEN2 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAPEN2. /
mbed_official	324:406fd2029f23	2571
mbed_official	324:406fd2029f23	2572	/! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. /
mbed_official	324:406fd2029f23	2573	#define BR_FTM_COMBINE_DECAPEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2))
mbed_official	324:406fd2029f23	2574
mbed_official	324:406fd2029f23	2575	/! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. /
mbed_official	324:406fd2029f23	2576	#define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
mbed_official	324:406fd2029f23	2577
mbed_official	324:406fd2029f23	2578	/! @brief Set the DECAPEN2 field to a new value. /
mbed_official	324:406fd2029f23	2579	#define BW_FTM_COMBINE_DECAPEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2) = (v))
mbed_official	324:406fd2029f23	2580	/@}/
mbed_official	324:406fd2029f23	2581
mbed_official	324:406fd2029f23	2582	/*!
mbed_official	324:406fd2029f23	2583	* @name Register FTM_COMBINE, field DECAP2[19] (RW)
mbed_official	324:406fd2029f23	2584	*
mbed_official	324:406fd2029f23	2585	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	324:406fd2029f23	2586	* input event and the configuration of the dual edge capture bits. This field
mbed_official	324:406fd2029f23	2587	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	324:406fd2029f23	2588	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	324:406fd2029f23	2589	* of channel (n+1) event is made.
mbed_official	324:406fd2029f23	2590	*
mbed_official	324:406fd2029f23	2591	* Values:
mbed_official	324:406fd2029f23	2592	* - 0 - The dual edge captures are inactive.
mbed_official	324:406fd2029f23	2593	* - 1 - The dual edge captures are active.
mbed_official	324:406fd2029f23	2594	*/
mbed_official	324:406fd2029f23	2595	/@{/
mbed_official	324:406fd2029f23	2596	#define BP_FTM_COMBINE_DECAP2 (19U) /!< Bit position for FTM_COMBINE_DECAP2. /
mbed_official	324:406fd2029f23	2597	#define BM_FTM_COMBINE_DECAP2 (0x00080000U) /!< Bit mask for FTM_COMBINE_DECAP2. /
mbed_official	324:406fd2029f23	2598	#define BS_FTM_COMBINE_DECAP2 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAP2. /
mbed_official	324:406fd2029f23	2599
mbed_official	324:406fd2029f23	2600	/! @brief Read current value of the FTM_COMBINE_DECAP2 field. /
mbed_official	324:406fd2029f23	2601	#define BR_FTM_COMBINE_DECAP2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2))
mbed_official	324:406fd2029f23	2602
mbed_official	324:406fd2029f23	2603	/! @brief Format value for bitfield FTM_COMBINE_DECAP2. /
mbed_official	324:406fd2029f23	2604	#define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
mbed_official	324:406fd2029f23	2605
mbed_official	324:406fd2029f23	2606	/! @brief Set the DECAP2 field to a new value. /
mbed_official	324:406fd2029f23	2607	#define BW_FTM_COMBINE_DECAP2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2) = (v))
mbed_official	324:406fd2029f23	2608	/@}/
mbed_official	324:406fd2029f23	2609
mbed_official	324:406fd2029f23	2610	/*!
mbed_official	324:406fd2029f23	2611	* @name Register FTM_COMBINE, field DTEN2[20] (RW)
mbed_official	324:406fd2029f23	2612	*
mbed_official	324:406fd2029f23	2613	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	324:406fd2029f23	2614	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2615	*
mbed_official	324:406fd2029f23	2616	* Values:
mbed_official	324:406fd2029f23	2617	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2618	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2619	*/
mbed_official	324:406fd2029f23	2620	/@{/
mbed_official	324:406fd2029f23	2621	#define BP_FTM_COMBINE_DTEN2 (20U) /!< Bit position for FTM_COMBINE_DTEN2. /
mbed_official	324:406fd2029f23	2622	#define BM_FTM_COMBINE_DTEN2 (0x00100000U) /!< Bit mask for FTM_COMBINE_DTEN2. /
mbed_official	324:406fd2029f23	2623	#define BS_FTM_COMBINE_DTEN2 (1U) /!< Bit field size in bits for FTM_COMBINE_DTEN2. /
mbed_official	324:406fd2029f23	2624
mbed_official	324:406fd2029f23	2625	/! @brief Read current value of the FTM_COMBINE_DTEN2 field. /
mbed_official	324:406fd2029f23	2626	#define BR_FTM_COMBINE_DTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2))
mbed_official	324:406fd2029f23	2627
mbed_official	324:406fd2029f23	2628	/! @brief Format value for bitfield FTM_COMBINE_DTEN2. /
mbed_official	324:406fd2029f23	2629	#define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
mbed_official	324:406fd2029f23	2630
mbed_official	324:406fd2029f23	2631	/! @brief Set the DTEN2 field to a new value. /
mbed_official	324:406fd2029f23	2632	#define BW_FTM_COMBINE_DTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2) = (v))
mbed_official	324:406fd2029f23	2633	/@}/
mbed_official	324:406fd2029f23	2634
mbed_official	324:406fd2029f23	2635	/*!
mbed_official	324:406fd2029f23	2636	* @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
mbed_official	324:406fd2029f23	2637	*
mbed_official	324:406fd2029f23	2638	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	324:406fd2029f23	2639	*
mbed_official	324:406fd2029f23	2640	* Values:
mbed_official	324:406fd2029f23	2641	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2642	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2643	*/
mbed_official	324:406fd2029f23	2644	/@{/
mbed_official	324:406fd2029f23	2645	#define BP_FTM_COMBINE_SYNCEN2 (21U) /!< Bit position for FTM_COMBINE_SYNCEN2. /
mbed_official	324:406fd2029f23	2646	#define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /!< Bit mask for FTM_COMBINE_SYNCEN2. /
mbed_official	324:406fd2029f23	2647	#define BS_FTM_COMBINE_SYNCEN2 (1U) /!< Bit field size in bits for FTM_COMBINE_SYNCEN2. /
mbed_official	324:406fd2029f23	2648
mbed_official	324:406fd2029f23	2649	/! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. /
mbed_official	324:406fd2029f23	2650	#define BR_FTM_COMBINE_SYNCEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2))
mbed_official	324:406fd2029f23	2651
mbed_official	324:406fd2029f23	2652	/! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. /
mbed_official	324:406fd2029f23	2653	#define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
mbed_official	324:406fd2029f23	2654
mbed_official	324:406fd2029f23	2655	/! @brief Set the SYNCEN2 field to a new value. /
mbed_official	324:406fd2029f23	2656	#define BW_FTM_COMBINE_SYNCEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2) = (v))
mbed_official	324:406fd2029f23	2657	/@}/
mbed_official	324:406fd2029f23	2658
mbed_official	324:406fd2029f23	2659	/*!
mbed_official	324:406fd2029f23	2660	* @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
mbed_official	324:406fd2029f23	2661	*
mbed_official	324:406fd2029f23	2662	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2663	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2664	*
mbed_official	324:406fd2029f23	2665	* Values:
mbed_official	324:406fd2029f23	2666	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2667	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2668	*/
mbed_official	324:406fd2029f23	2669	/@{/
mbed_official	324:406fd2029f23	2670	#define BP_FTM_COMBINE_FAULTEN2 (22U) /!< Bit position for FTM_COMBINE_FAULTEN2. /
mbed_official	324:406fd2029f23	2671	#define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /!< Bit mask for FTM_COMBINE_FAULTEN2. /
mbed_official	324:406fd2029f23	2672	#define BS_FTM_COMBINE_FAULTEN2 (1U) /!< Bit field size in bits for FTM_COMBINE_FAULTEN2. /
mbed_official	324:406fd2029f23	2673
mbed_official	324:406fd2029f23	2674	/! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. /
mbed_official	324:406fd2029f23	2675	#define BR_FTM_COMBINE_FAULTEN2(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2))
mbed_official	324:406fd2029f23	2676
mbed_official	324:406fd2029f23	2677	/! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. /
mbed_official	324:406fd2029f23	2678	#define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
mbed_official	324:406fd2029f23	2679
mbed_official	324:406fd2029f23	2680	/! @brief Set the FAULTEN2 field to a new value. /
mbed_official	324:406fd2029f23	2681	#define BW_FTM_COMBINE_FAULTEN2(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2) = (v))
mbed_official	324:406fd2029f23	2682	/@}/
mbed_official	324:406fd2029f23	2683
mbed_official	324:406fd2029f23	2684	/*!
mbed_official	324:406fd2029f23	2685	* @name Register FTM_COMBINE, field COMBINE3[24] (RW)
mbed_official	324:406fd2029f23	2686	*
mbed_official	324:406fd2029f23	2687	* Enables the combine feature for channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2688	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2689	*
mbed_official	324:406fd2029f23	2690	* Values:
mbed_official	324:406fd2029f23	2691	* - 0 - Channels (n) and (n+1) are independent.
mbed_official	324:406fd2029f23	2692	* - 1 - Channels (n) and (n+1) are combined.
mbed_official	324:406fd2029f23	2693	*/
mbed_official	324:406fd2029f23	2694	/@{/
mbed_official	324:406fd2029f23	2695	#define BP_FTM_COMBINE_COMBINE3 (24U) /!< Bit position for FTM_COMBINE_COMBINE3. /
mbed_official	324:406fd2029f23	2696	#define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /!< Bit mask for FTM_COMBINE_COMBINE3. /
mbed_official	324:406fd2029f23	2697	#define BS_FTM_COMBINE_COMBINE3 (1U) /!< Bit field size in bits for FTM_COMBINE_COMBINE3. /
mbed_official	324:406fd2029f23	2698
mbed_official	324:406fd2029f23	2699	/! @brief Read current value of the FTM_COMBINE_COMBINE3 field. /
mbed_official	324:406fd2029f23	2700	#define BR_FTM_COMBINE_COMBINE3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3))
mbed_official	324:406fd2029f23	2701
mbed_official	324:406fd2029f23	2702	/! @brief Format value for bitfield FTM_COMBINE_COMBINE3. /
mbed_official	324:406fd2029f23	2703	#define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
mbed_official	324:406fd2029f23	2704
mbed_official	324:406fd2029f23	2705	/! @brief Set the COMBINE3 field to a new value. /
mbed_official	324:406fd2029f23	2706	#define BW_FTM_COMBINE_COMBINE3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3) = (v))
mbed_official	324:406fd2029f23	2707	/@}/
mbed_official	324:406fd2029f23	2708
mbed_official	324:406fd2029f23	2709	/*!
mbed_official	324:406fd2029f23	2710	* @name Register FTM_COMBINE, field COMP3[25] (RW)
mbed_official	324:406fd2029f23	2711	*
mbed_official	324:406fd2029f23	2712	* Enables Complementary mode for the combined channels. In Complementary mode
mbed_official	324:406fd2029f23	2713	* the channel (n+1) output is the inverse of the channel (n) output. This field
mbed_official	324:406fd2029f23	2714	* is write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2715	*
mbed_official	324:406fd2029f23	2716	* Values:
mbed_official	324:406fd2029f23	2717	* - 0 - The channel (n+1) output is the same as the channel (n) output.
mbed_official	324:406fd2029f23	2718	* - 1 - The channel (n+1) output is the complement of the channel (n) output.
mbed_official	324:406fd2029f23	2719	*/
mbed_official	324:406fd2029f23	2720	/@{/
mbed_official	324:406fd2029f23	2721	#define BP_FTM_COMBINE_COMP3 (25U) /!< Bit position for FTM_COMBINE_COMP3. /
mbed_official	324:406fd2029f23	2722	#define BM_FTM_COMBINE_COMP3 (0x02000000U) /!< Bit mask for FTM_COMBINE_COMP3. /
mbed_official	324:406fd2029f23	2723	#define BS_FTM_COMBINE_COMP3 (1U) /!< Bit field size in bits for FTM_COMBINE_COMP3. /
mbed_official	324:406fd2029f23	2724
mbed_official	324:406fd2029f23	2725	/! @brief Read current value of the FTM_COMBINE_COMP3 field. /
mbed_official	324:406fd2029f23	2726	#define BR_FTM_COMBINE_COMP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3))
mbed_official	324:406fd2029f23	2727
mbed_official	324:406fd2029f23	2728	/! @brief Format value for bitfield FTM_COMBINE_COMP3. /
mbed_official	324:406fd2029f23	2729	#define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
mbed_official	324:406fd2029f23	2730
mbed_official	324:406fd2029f23	2731	/! @brief Set the COMP3 field to a new value. /
mbed_official	324:406fd2029f23	2732	#define BW_FTM_COMBINE_COMP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3) = (v))
mbed_official	324:406fd2029f23	2733	/@}/
mbed_official	324:406fd2029f23	2734
mbed_official	324:406fd2029f23	2735	/*!
mbed_official	324:406fd2029f23	2736	* @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
mbed_official	324:406fd2029f23	2737	*
mbed_official	324:406fd2029f23	2738	* Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
mbed_official	324:406fd2029f23	2739	* reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
mbed_official	324:406fd2029f23	2740	* Dual Edge Capture mode according to #ModeSel1Table. This field applies only
mbed_official	324:406fd2029f23	2741	* when FTMEN = 1. This field is write protected. It can be written only when
mbed_official	324:406fd2029f23	2742	* MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2743	*
mbed_official	324:406fd2029f23	2744	* Values:
mbed_official	324:406fd2029f23	2745	* - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2746	* - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2747	*/
mbed_official	324:406fd2029f23	2748	/@{/
mbed_official	324:406fd2029f23	2749	#define BP_FTM_COMBINE_DECAPEN3 (26U) /!< Bit position for FTM_COMBINE_DECAPEN3. /
mbed_official	324:406fd2029f23	2750	#define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /!< Bit mask for FTM_COMBINE_DECAPEN3. /
mbed_official	324:406fd2029f23	2751	#define BS_FTM_COMBINE_DECAPEN3 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAPEN3. /
mbed_official	324:406fd2029f23	2752
mbed_official	324:406fd2029f23	2753	/! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. /
mbed_official	324:406fd2029f23	2754	#define BR_FTM_COMBINE_DECAPEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3))
mbed_official	324:406fd2029f23	2755
mbed_official	324:406fd2029f23	2756	/! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. /
mbed_official	324:406fd2029f23	2757	#define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
mbed_official	324:406fd2029f23	2758
mbed_official	324:406fd2029f23	2759	/! @brief Set the DECAPEN3 field to a new value. /
mbed_official	324:406fd2029f23	2760	#define BW_FTM_COMBINE_DECAPEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3) = (v))
mbed_official	324:406fd2029f23	2761	/@}/
mbed_official	324:406fd2029f23	2762
mbed_official	324:406fd2029f23	2763	/*!
mbed_official	324:406fd2029f23	2764	* @name Register FTM_COMBINE, field DECAP3[27] (RW)
mbed_official	324:406fd2029f23	2765	*
mbed_official	324:406fd2029f23	2766	* Enables the capture of the FTM counter value according to the channel (n)
mbed_official	324:406fd2029f23	2767	* input event and the configuration of the dual edge capture bits. This field
mbed_official	324:406fd2029f23	2768	* applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
mbed_official	324:406fd2029f23	2769	* hardware if dual edge capture - one-shot mode is selected and when the capture
mbed_official	324:406fd2029f23	2770	* of channel (n+1) event is made.
mbed_official	324:406fd2029f23	2771	*
mbed_official	324:406fd2029f23	2772	* Values:
mbed_official	324:406fd2029f23	2773	* - 0 - The dual edge captures are inactive.
mbed_official	324:406fd2029f23	2774	* - 1 - The dual edge captures are active.
mbed_official	324:406fd2029f23	2775	*/
mbed_official	324:406fd2029f23	2776	/@{/
mbed_official	324:406fd2029f23	2777	#define BP_FTM_COMBINE_DECAP3 (27U) /!< Bit position for FTM_COMBINE_DECAP3. /
mbed_official	324:406fd2029f23	2778	#define BM_FTM_COMBINE_DECAP3 (0x08000000U) /!< Bit mask for FTM_COMBINE_DECAP3. /
mbed_official	324:406fd2029f23	2779	#define BS_FTM_COMBINE_DECAP3 (1U) /!< Bit field size in bits for FTM_COMBINE_DECAP3. /
mbed_official	324:406fd2029f23	2780
mbed_official	324:406fd2029f23	2781	/! @brief Read current value of the FTM_COMBINE_DECAP3 field. /
mbed_official	324:406fd2029f23	2782	#define BR_FTM_COMBINE_DECAP3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3))
mbed_official	324:406fd2029f23	2783
mbed_official	324:406fd2029f23	2784	/! @brief Format value for bitfield FTM_COMBINE_DECAP3. /
mbed_official	324:406fd2029f23	2785	#define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
mbed_official	324:406fd2029f23	2786
mbed_official	324:406fd2029f23	2787	/! @brief Set the DECAP3 field to a new value. /
mbed_official	324:406fd2029f23	2788	#define BW_FTM_COMBINE_DECAP3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3) = (v))
mbed_official	324:406fd2029f23	2789	/@}/
mbed_official	324:406fd2029f23	2790
mbed_official	324:406fd2029f23	2791	/*!
mbed_official	324:406fd2029f23	2792	* @name Register FTM_COMBINE, field DTEN3[28] (RW)
mbed_official	324:406fd2029f23	2793	*
mbed_official	324:406fd2029f23	2794	* Enables the deadtime insertion in the channels (n) and (n+1). This field is
mbed_official	324:406fd2029f23	2795	* write protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2796	*
mbed_official	324:406fd2029f23	2797	* Values:
mbed_official	324:406fd2029f23	2798	* - 0 - The deadtime insertion in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2799	* - 1 - The deadtime insertion in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2800	*/
mbed_official	324:406fd2029f23	2801	/@{/
mbed_official	324:406fd2029f23	2802	#define BP_FTM_COMBINE_DTEN3 (28U) /!< Bit position for FTM_COMBINE_DTEN3. /
mbed_official	324:406fd2029f23	2803	#define BM_FTM_COMBINE_DTEN3 (0x10000000U) /!< Bit mask for FTM_COMBINE_DTEN3. /
mbed_official	324:406fd2029f23	2804	#define BS_FTM_COMBINE_DTEN3 (1U) /!< Bit field size in bits for FTM_COMBINE_DTEN3. /
mbed_official	324:406fd2029f23	2805
mbed_official	324:406fd2029f23	2806	/! @brief Read current value of the FTM_COMBINE_DTEN3 field. /
mbed_official	324:406fd2029f23	2807	#define BR_FTM_COMBINE_DTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3))
mbed_official	324:406fd2029f23	2808
mbed_official	324:406fd2029f23	2809	/! @brief Format value for bitfield FTM_COMBINE_DTEN3. /
mbed_official	324:406fd2029f23	2810	#define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
mbed_official	324:406fd2029f23	2811
mbed_official	324:406fd2029f23	2812	/! @brief Set the DTEN3 field to a new value. /
mbed_official	324:406fd2029f23	2813	#define BW_FTM_COMBINE_DTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3) = (v))
mbed_official	324:406fd2029f23	2814	/@}/
mbed_official	324:406fd2029f23	2815
mbed_official	324:406fd2029f23	2816	/*!
mbed_official	324:406fd2029f23	2817	* @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
mbed_official	324:406fd2029f23	2818	*
mbed_official	324:406fd2029f23	2819	* Enables PWM synchronization of registers C(n)V and C(n+1)V.
mbed_official	324:406fd2029f23	2820	*
mbed_official	324:406fd2029f23	2821	* Values:
mbed_official	324:406fd2029f23	2822	* - 0 - The PWM synchronization in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2823	* - 1 - The PWM synchronization in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2824	*/
mbed_official	324:406fd2029f23	2825	/@{/
mbed_official	324:406fd2029f23	2826	#define BP_FTM_COMBINE_SYNCEN3 (29U) /!< Bit position for FTM_COMBINE_SYNCEN3. /
mbed_official	324:406fd2029f23	2827	#define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /!< Bit mask for FTM_COMBINE_SYNCEN3. /
mbed_official	324:406fd2029f23	2828	#define BS_FTM_COMBINE_SYNCEN3 (1U) /!< Bit field size in bits for FTM_COMBINE_SYNCEN3. /
mbed_official	324:406fd2029f23	2829
mbed_official	324:406fd2029f23	2830	/! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. /
mbed_official	324:406fd2029f23	2831	#define BR_FTM_COMBINE_SYNCEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3))
mbed_official	324:406fd2029f23	2832
mbed_official	324:406fd2029f23	2833	/! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. /
mbed_official	324:406fd2029f23	2834	#define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
mbed_official	324:406fd2029f23	2835
mbed_official	324:406fd2029f23	2836	/! @brief Set the SYNCEN3 field to a new value. /
mbed_official	324:406fd2029f23	2837	#define BW_FTM_COMBINE_SYNCEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3) = (v))
mbed_official	324:406fd2029f23	2838	/@}/
mbed_official	324:406fd2029f23	2839
mbed_official	324:406fd2029f23	2840	/*!
mbed_official	324:406fd2029f23	2841	* @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
mbed_official	324:406fd2029f23	2842	*
mbed_official	324:406fd2029f23	2843	* Enables the fault control in channels (n) and (n+1). This field is write
mbed_official	324:406fd2029f23	2844	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2845	*
mbed_official	324:406fd2029f23	2846	* Values:
mbed_official	324:406fd2029f23	2847	* - 0 - The fault control in this pair of channels is disabled.
mbed_official	324:406fd2029f23	2848	* - 1 - The fault control in this pair of channels is enabled.
mbed_official	324:406fd2029f23	2849	*/
mbed_official	324:406fd2029f23	2850	/@{/
mbed_official	324:406fd2029f23	2851	#define BP_FTM_COMBINE_FAULTEN3 (30U) /!< Bit position for FTM_COMBINE_FAULTEN3. /
mbed_official	324:406fd2029f23	2852	#define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /!< Bit mask for FTM_COMBINE_FAULTEN3. /
mbed_official	324:406fd2029f23	2853	#define BS_FTM_COMBINE_FAULTEN3 (1U) /!< Bit field size in bits for FTM_COMBINE_FAULTEN3. /
mbed_official	324:406fd2029f23	2854
mbed_official	324:406fd2029f23	2855	/! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. /
mbed_official	324:406fd2029f23	2856	#define BR_FTM_COMBINE_FAULTEN3(x) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3))
mbed_official	324:406fd2029f23	2857
mbed_official	324:406fd2029f23	2858	/! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. /
mbed_official	324:406fd2029f23	2859	#define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
mbed_official	324:406fd2029f23	2860
mbed_official	324:406fd2029f23	2861	/! @brief Set the FAULTEN3 field to a new value. /
mbed_official	324:406fd2029f23	2862	#define BW_FTM_COMBINE_FAULTEN3(x, v) (BITBAND_ACCESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3) = (v))
mbed_official	324:406fd2029f23	2863	/@}/
mbed_official	324:406fd2029f23	2864
mbed_official	324:406fd2029f23	2865	/*******************************************************************************
mbed_official	324:406fd2029f23	2866	* HW_FTM_DEADTIME - Deadtime Insertion Control
mbed_official	324:406fd2029f23	2867	******************************************************************************/
mbed_official	324:406fd2029f23	2868
mbed_official	324:406fd2029f23	2869	/*!
mbed_official	324:406fd2029f23	2870	* @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
mbed_official	324:406fd2029f23	2871	*
mbed_official	324:406fd2029f23	2872	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2873	*
mbed_official	324:406fd2029f23	2874	* This register selects the deadtime prescaler factor and deadtime value. All
mbed_official	324:406fd2029f23	2875	* FTM channels use this clock prescaler and this deadtime value for the deadtime
mbed_official	324:406fd2029f23	2876	* insertion.
mbed_official	324:406fd2029f23	2877	*/
mbed_official	324:406fd2029f23	2878	typedef union _hw_ftm_deadtime
mbed_official	324:406fd2029f23	2879	{
mbed_official	324:406fd2029f23	2880	uint32_t U;
mbed_official	324:406fd2029f23	2881	struct _hw_ftm_deadtime_bitfields
mbed_official	324:406fd2029f23	2882	{
mbed_official	324:406fd2029f23	2883	uint32_t DTVAL : 6; /!< [5:0] Deadtime Value /
mbed_official	324:406fd2029f23	2884	uint32_t DTPS : 2; /!< [7:6] Deadtime Prescaler Value /
mbed_official	324:406fd2029f23	2885	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	2886	} B;
mbed_official	324:406fd2029f23	2887	} hw_ftm_deadtime_t;
mbed_official	324:406fd2029f23	2888
mbed_official	324:406fd2029f23	2889	/*!
mbed_official	324:406fd2029f23	2890	* @name Constants and macros for entire FTM_DEADTIME register
mbed_official	324:406fd2029f23	2891	*/
mbed_official	324:406fd2029f23	2892	/@{/
mbed_official	324:406fd2029f23	2893	#define HW_FTM_DEADTIME_ADDR(x) ((x) + 0x68U)
mbed_official	324:406fd2029f23	2894
mbed_official	324:406fd2029f23	2895	#define HW_FTM_DEADTIME(x) ((__IO hw_ftm_deadtime_t ) HW_FTM_DEADTIME_ADDR(x))
mbed_official	324:406fd2029f23	2896	#define HW_FTM_DEADTIME_RD(x) (HW_FTM_DEADTIME(x).U)
mbed_official	324:406fd2029f23	2897	#define HW_FTM_DEADTIME_WR(x, v) (HW_FTM_DEADTIME(x).U = (v))
mbed_official	324:406fd2029f23	2898	#define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) \| (v)))
mbed_official	324:406fd2029f23	2899	#define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	2900	#define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	2901	/@}/
mbed_official	324:406fd2029f23	2902
mbed_official	324:406fd2029f23	2903	/*
mbed_official	324:406fd2029f23	2904	* Constants & macros for individual FTM_DEADTIME bitfields
mbed_official	324:406fd2029f23	2905	*/
mbed_official	324:406fd2029f23	2906
mbed_official	324:406fd2029f23	2907	/*!
mbed_official	324:406fd2029f23	2908	* @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
mbed_official	324:406fd2029f23	2909	*
mbed_official	324:406fd2029f23	2910	* Selects the deadtime insertion value for the deadtime counter. The deadtime
mbed_official	324:406fd2029f23	2911	* counter is clocked by a scaled version of the system clock. See the description
mbed_official	324:406fd2029f23	2912	* of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
mbed_official	324:406fd2029f23	2913	* deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
mbed_official	324:406fd2029f23	2914	* When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
mbed_official	324:406fd2029f23	2915	* This pattern continues up to a possible 63 counts. This field is write
mbed_official	324:406fd2029f23	2916	* protected. It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2917	*/
mbed_official	324:406fd2029f23	2918	/@{/
mbed_official	324:406fd2029f23	2919	#define BP_FTM_DEADTIME_DTVAL (0U) /!< Bit position for FTM_DEADTIME_DTVAL. /
mbed_official	324:406fd2029f23	2920	#define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /!< Bit mask for FTM_DEADTIME_DTVAL. /
mbed_official	324:406fd2029f23	2921	#define BS_FTM_DEADTIME_DTVAL (6U) /!< Bit field size in bits for FTM_DEADTIME_DTVAL. /
mbed_official	324:406fd2029f23	2922
mbed_official	324:406fd2029f23	2923	/! @brief Read current value of the FTM_DEADTIME_DTVAL field. /
mbed_official	324:406fd2029f23	2924	#define BR_FTM_DEADTIME_DTVAL(x) (HW_FTM_DEADTIME(x).B.DTVAL)
mbed_official	324:406fd2029f23	2925
mbed_official	324:406fd2029f23	2926	/! @brief Format value for bitfield FTM_DEADTIME_DTVAL. /
mbed_official	324:406fd2029f23	2927	#define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
mbed_official	324:406fd2029f23	2928
mbed_official	324:406fd2029f23	2929	/! @brief Set the DTVAL field to a new value. /
mbed_official	324:406fd2029f23	2930	#define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) \| BF_FTM_DEADTIME_DTVAL(v)))
mbed_official	324:406fd2029f23	2931	/@}/
mbed_official	324:406fd2029f23	2932
mbed_official	324:406fd2029f23	2933	/*!
mbed_official	324:406fd2029f23	2934	* @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
mbed_official	324:406fd2029f23	2935	*
mbed_official	324:406fd2029f23	2936	* Selects the division factor of the system clock. This prescaled clock is used
mbed_official	324:406fd2029f23	2937	* by the deadtime counter. This field is write protected. It can be written
mbed_official	324:406fd2029f23	2938	* only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	2939	*
mbed_official	324:406fd2029f23	2940	* Values:
mbed_official	324:406fd2029f23	2941	* - 0x - Divide the system clock by 1.
mbed_official	324:406fd2029f23	2942	* - 10 - Divide the system clock by 4.
mbed_official	324:406fd2029f23	2943	* - 11 - Divide the system clock by 16.
mbed_official	324:406fd2029f23	2944	*/
mbed_official	324:406fd2029f23	2945	/@{/
mbed_official	324:406fd2029f23	2946	#define BP_FTM_DEADTIME_DTPS (6U) /!< Bit position for FTM_DEADTIME_DTPS. /
mbed_official	324:406fd2029f23	2947	#define BM_FTM_DEADTIME_DTPS (0x000000C0U) /!< Bit mask for FTM_DEADTIME_DTPS. /
mbed_official	324:406fd2029f23	2948	#define BS_FTM_DEADTIME_DTPS (2U) /!< Bit field size in bits for FTM_DEADTIME_DTPS. /
mbed_official	324:406fd2029f23	2949
mbed_official	324:406fd2029f23	2950	/! @brief Read current value of the FTM_DEADTIME_DTPS field. /
mbed_official	324:406fd2029f23	2951	#define BR_FTM_DEADTIME_DTPS(x) (HW_FTM_DEADTIME(x).B.DTPS)
mbed_official	324:406fd2029f23	2952
mbed_official	324:406fd2029f23	2953	/! @brief Format value for bitfield FTM_DEADTIME_DTPS. /
mbed_official	324:406fd2029f23	2954	#define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
mbed_official	324:406fd2029f23	2955
mbed_official	324:406fd2029f23	2956	/! @brief Set the DTPS field to a new value. /
mbed_official	324:406fd2029f23	2957	#define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) \| BF_FTM_DEADTIME_DTPS(v)))
mbed_official	324:406fd2029f23	2958	/@}/
mbed_official	324:406fd2029f23	2959
mbed_official	324:406fd2029f23	2960	/*******************************************************************************
mbed_official	324:406fd2029f23	2961	* HW_FTM_EXTTRIG - FTM External Trigger
mbed_official	324:406fd2029f23	2962	******************************************************************************/
mbed_official	324:406fd2029f23	2963
mbed_official	324:406fd2029f23	2964	/*!
mbed_official	324:406fd2029f23	2965	* @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
mbed_official	324:406fd2029f23	2966	*
mbed_official	324:406fd2029f23	2967	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	2968	*
mbed_official	324:406fd2029f23	2969	* This register: Indicates when a channel trigger was generated Enables the
mbed_official	324:406fd2029f23	2970	* generation of a trigger when the FTM counter is equal to its initial value
mbed_official	324:406fd2029f23	2971	* Selects which channels are used in the generation of the channel triggers Several
mbed_official	324:406fd2029f23	2972	* channels can be selected to generate multiple triggers in one PWM period.
mbed_official	324:406fd2029f23	2973	* Channels 6 and 7 are not used to generate channel triggers.
mbed_official	324:406fd2029f23	2974	*/
mbed_official	324:406fd2029f23	2975	typedef union _hw_ftm_exttrig
mbed_official	324:406fd2029f23	2976	{
mbed_official	324:406fd2029f23	2977	uint32_t U;
mbed_official	324:406fd2029f23	2978	struct _hw_ftm_exttrig_bitfields
mbed_official	324:406fd2029f23	2979	{
mbed_official	324:406fd2029f23	2980	uint32_t CH2TRIG : 1; /!< [0] Channel 2 Trigger Enable /
mbed_official	324:406fd2029f23	2981	uint32_t CH3TRIG : 1; /!< [1] Channel 3 Trigger Enable /
mbed_official	324:406fd2029f23	2982	uint32_t CH4TRIG : 1; /!< [2] Channel 4 Trigger Enable /
mbed_official	324:406fd2029f23	2983	uint32_t CH5TRIG : 1; /!< [3] Channel 5 Trigger Enable /
mbed_official	324:406fd2029f23	2984	uint32_t CH0TRIG : 1; /!< [4] Channel 0 Trigger Enable /
mbed_official	324:406fd2029f23	2985	uint32_t CH1TRIG : 1; /!< [5] Channel 1 Trigger Enable /
mbed_official	324:406fd2029f23	2986	uint32_t INITTRIGEN : 1; /!< [6] Initialization Trigger Enable /
mbed_official	324:406fd2029f23	2987	uint32_t TRIGF : 1; /!< [7] Channel Trigger Flag /
mbed_official	324:406fd2029f23	2988	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	2989	} B;
mbed_official	324:406fd2029f23	2990	} hw_ftm_exttrig_t;
mbed_official	324:406fd2029f23	2991
mbed_official	324:406fd2029f23	2992	/*!
mbed_official	324:406fd2029f23	2993	* @name Constants and macros for entire FTM_EXTTRIG register
mbed_official	324:406fd2029f23	2994	*/
mbed_official	324:406fd2029f23	2995	/@{/
mbed_official	324:406fd2029f23	2996	#define HW_FTM_EXTTRIG_ADDR(x) ((x) + 0x6CU)
mbed_official	324:406fd2029f23	2997
mbed_official	324:406fd2029f23	2998	#define HW_FTM_EXTTRIG(x) ((__IO hw_ftm_exttrig_t ) HW_FTM_EXTTRIG_ADDR(x))
mbed_official	324:406fd2029f23	2999	#define HW_FTM_EXTTRIG_RD(x) (HW_FTM_EXTTRIG(x).U)
mbed_official	324:406fd2029f23	3000	#define HW_FTM_EXTTRIG_WR(x, v) (HW_FTM_EXTTRIG(x).U = (v))
mbed_official	324:406fd2029f23	3001	#define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3002	#define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3003	#define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3004	/@}/
mbed_official	324:406fd2029f23	3005
mbed_official	324:406fd2029f23	3006	/*
mbed_official	324:406fd2029f23	3007	* Constants & macros for individual FTM_EXTTRIG bitfields
mbed_official	324:406fd2029f23	3008	*/
mbed_official	324:406fd2029f23	3009
mbed_official	324:406fd2029f23	3010	/*!
mbed_official	324:406fd2029f23	3011	* @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
mbed_official	324:406fd2029f23	3012	*
mbed_official	324:406fd2029f23	3013	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3014	* to the CnV register.
mbed_official	324:406fd2029f23	3015	*
mbed_official	324:406fd2029f23	3016	* Values:
mbed_official	324:406fd2029f23	3017	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3018	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3019	*/
mbed_official	324:406fd2029f23	3020	/@{/
mbed_official	324:406fd2029f23	3021	#define BP_FTM_EXTTRIG_CH2TRIG (0U) /!< Bit position for FTM_EXTTRIG_CH2TRIG. /
mbed_official	324:406fd2029f23	3022	#define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /!< Bit mask for FTM_EXTTRIG_CH2TRIG. /
mbed_official	324:406fd2029f23	3023	#define BS_FTM_EXTTRIG_CH2TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. /
mbed_official	324:406fd2029f23	3024
mbed_official	324:406fd2029f23	3025	/! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. /
mbed_official	324:406fd2029f23	3026	#define BR_FTM_EXTTRIG_CH2TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG))
mbed_official	324:406fd2029f23	3027
mbed_official	324:406fd2029f23	3028	/! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. /
mbed_official	324:406fd2029f23	3029	#define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
mbed_official	324:406fd2029f23	3030
mbed_official	324:406fd2029f23	3031	/! @brief Set the CH2TRIG field to a new value. /
mbed_official	324:406fd2029f23	3032	#define BW_FTM_EXTTRIG_CH2TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG) = (v))
mbed_official	324:406fd2029f23	3033	/@}/
mbed_official	324:406fd2029f23	3034
mbed_official	324:406fd2029f23	3035	/*!
mbed_official	324:406fd2029f23	3036	* @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
mbed_official	324:406fd2029f23	3037	*
mbed_official	324:406fd2029f23	3038	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3039	* to the CnV register.
mbed_official	324:406fd2029f23	3040	*
mbed_official	324:406fd2029f23	3041	* Values:
mbed_official	324:406fd2029f23	3042	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3043	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3044	*/
mbed_official	324:406fd2029f23	3045	/@{/
mbed_official	324:406fd2029f23	3046	#define BP_FTM_EXTTRIG_CH3TRIG (1U) /!< Bit position for FTM_EXTTRIG_CH3TRIG. /
mbed_official	324:406fd2029f23	3047	#define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /!< Bit mask for FTM_EXTTRIG_CH3TRIG. /
mbed_official	324:406fd2029f23	3048	#define BS_FTM_EXTTRIG_CH3TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. /
mbed_official	324:406fd2029f23	3049
mbed_official	324:406fd2029f23	3050	/! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. /
mbed_official	324:406fd2029f23	3051	#define BR_FTM_EXTTRIG_CH3TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG))
mbed_official	324:406fd2029f23	3052
mbed_official	324:406fd2029f23	3053	/! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. /
mbed_official	324:406fd2029f23	3054	#define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
mbed_official	324:406fd2029f23	3055
mbed_official	324:406fd2029f23	3056	/! @brief Set the CH3TRIG field to a new value. /
mbed_official	324:406fd2029f23	3057	#define BW_FTM_EXTTRIG_CH3TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG) = (v))
mbed_official	324:406fd2029f23	3058	/@}/
mbed_official	324:406fd2029f23	3059
mbed_official	324:406fd2029f23	3060	/*!
mbed_official	324:406fd2029f23	3061	* @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
mbed_official	324:406fd2029f23	3062	*
mbed_official	324:406fd2029f23	3063	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3064	* to the CnV register.
mbed_official	324:406fd2029f23	3065	*
mbed_official	324:406fd2029f23	3066	* Values:
mbed_official	324:406fd2029f23	3067	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3068	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3069	*/
mbed_official	324:406fd2029f23	3070	/@{/
mbed_official	324:406fd2029f23	3071	#define BP_FTM_EXTTRIG_CH4TRIG (2U) /!< Bit position for FTM_EXTTRIG_CH4TRIG. /
mbed_official	324:406fd2029f23	3072	#define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /!< Bit mask for FTM_EXTTRIG_CH4TRIG. /
mbed_official	324:406fd2029f23	3073	#define BS_FTM_EXTTRIG_CH4TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. /
mbed_official	324:406fd2029f23	3074
mbed_official	324:406fd2029f23	3075	/! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. /
mbed_official	324:406fd2029f23	3076	#define BR_FTM_EXTTRIG_CH4TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG))
mbed_official	324:406fd2029f23	3077
mbed_official	324:406fd2029f23	3078	/! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. /
mbed_official	324:406fd2029f23	3079	#define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
mbed_official	324:406fd2029f23	3080
mbed_official	324:406fd2029f23	3081	/! @brief Set the CH4TRIG field to a new value. /
mbed_official	324:406fd2029f23	3082	#define BW_FTM_EXTTRIG_CH4TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG) = (v))
mbed_official	324:406fd2029f23	3083	/@}/
mbed_official	324:406fd2029f23	3084
mbed_official	324:406fd2029f23	3085	/*!
mbed_official	324:406fd2029f23	3086	* @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
mbed_official	324:406fd2029f23	3087	*
mbed_official	324:406fd2029f23	3088	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3089	* to the CnV register.
mbed_official	324:406fd2029f23	3090	*
mbed_official	324:406fd2029f23	3091	* Values:
mbed_official	324:406fd2029f23	3092	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3093	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3094	*/
mbed_official	324:406fd2029f23	3095	/@{/
mbed_official	324:406fd2029f23	3096	#define BP_FTM_EXTTRIG_CH5TRIG (3U) /!< Bit position for FTM_EXTTRIG_CH5TRIG. /
mbed_official	324:406fd2029f23	3097	#define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /!< Bit mask for FTM_EXTTRIG_CH5TRIG. /
mbed_official	324:406fd2029f23	3098	#define BS_FTM_EXTTRIG_CH5TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. /
mbed_official	324:406fd2029f23	3099
mbed_official	324:406fd2029f23	3100	/! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. /
mbed_official	324:406fd2029f23	3101	#define BR_FTM_EXTTRIG_CH5TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG))
mbed_official	324:406fd2029f23	3102
mbed_official	324:406fd2029f23	3103	/! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. /
mbed_official	324:406fd2029f23	3104	#define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
mbed_official	324:406fd2029f23	3105
mbed_official	324:406fd2029f23	3106	/! @brief Set the CH5TRIG field to a new value. /
mbed_official	324:406fd2029f23	3107	#define BW_FTM_EXTTRIG_CH5TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG) = (v))
mbed_official	324:406fd2029f23	3108	/@}/
mbed_official	324:406fd2029f23	3109
mbed_official	324:406fd2029f23	3110	/*!
mbed_official	324:406fd2029f23	3111	* @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
mbed_official	324:406fd2029f23	3112	*
mbed_official	324:406fd2029f23	3113	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3114	* to the CnV register.
mbed_official	324:406fd2029f23	3115	*
mbed_official	324:406fd2029f23	3116	* Values:
mbed_official	324:406fd2029f23	3117	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3118	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3119	*/
mbed_official	324:406fd2029f23	3120	/@{/
mbed_official	324:406fd2029f23	3121	#define BP_FTM_EXTTRIG_CH0TRIG (4U) /!< Bit position for FTM_EXTTRIG_CH0TRIG. /
mbed_official	324:406fd2029f23	3122	#define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /!< Bit mask for FTM_EXTTRIG_CH0TRIG. /
mbed_official	324:406fd2029f23	3123	#define BS_FTM_EXTTRIG_CH0TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. /
mbed_official	324:406fd2029f23	3124
mbed_official	324:406fd2029f23	3125	/! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. /
mbed_official	324:406fd2029f23	3126	#define BR_FTM_EXTTRIG_CH0TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG))
mbed_official	324:406fd2029f23	3127
mbed_official	324:406fd2029f23	3128	/! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. /
mbed_official	324:406fd2029f23	3129	#define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
mbed_official	324:406fd2029f23	3130
mbed_official	324:406fd2029f23	3131	/! @brief Set the CH0TRIG field to a new value. /
mbed_official	324:406fd2029f23	3132	#define BW_FTM_EXTTRIG_CH0TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG) = (v))
mbed_official	324:406fd2029f23	3133	/@}/
mbed_official	324:406fd2029f23	3134
mbed_official	324:406fd2029f23	3135	/*!
mbed_official	324:406fd2029f23	3136	* @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
mbed_official	324:406fd2029f23	3137	*
mbed_official	324:406fd2029f23	3138	* Enables the generation of the channel trigger when the FTM counter is equal
mbed_official	324:406fd2029f23	3139	* to the CnV register.
mbed_official	324:406fd2029f23	3140	*
mbed_official	324:406fd2029f23	3141	* Values:
mbed_official	324:406fd2029f23	3142	* - 0 - The generation of the channel trigger is disabled.
mbed_official	324:406fd2029f23	3143	* - 1 - The generation of the channel trigger is enabled.
mbed_official	324:406fd2029f23	3144	*/
mbed_official	324:406fd2029f23	3145	/@{/
mbed_official	324:406fd2029f23	3146	#define BP_FTM_EXTTRIG_CH1TRIG (5U) /!< Bit position for FTM_EXTTRIG_CH1TRIG. /
mbed_official	324:406fd2029f23	3147	#define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /!< Bit mask for FTM_EXTTRIG_CH1TRIG. /
mbed_official	324:406fd2029f23	3148	#define BS_FTM_EXTTRIG_CH1TRIG (1U) /!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. /
mbed_official	324:406fd2029f23	3149
mbed_official	324:406fd2029f23	3150	/! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. /
mbed_official	324:406fd2029f23	3151	#define BR_FTM_EXTTRIG_CH1TRIG(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG))
mbed_official	324:406fd2029f23	3152
mbed_official	324:406fd2029f23	3153	/! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. /
mbed_official	324:406fd2029f23	3154	#define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
mbed_official	324:406fd2029f23	3155
mbed_official	324:406fd2029f23	3156	/! @brief Set the CH1TRIG field to a new value. /
mbed_official	324:406fd2029f23	3157	#define BW_FTM_EXTTRIG_CH1TRIG(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG) = (v))
mbed_official	324:406fd2029f23	3158	/@}/
mbed_official	324:406fd2029f23	3159
mbed_official	324:406fd2029f23	3160	/*!
mbed_official	324:406fd2029f23	3161	* @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
mbed_official	324:406fd2029f23	3162	*
mbed_official	324:406fd2029f23	3163	* Enables the generation of the trigger when the FTM counter is equal to the
mbed_official	324:406fd2029f23	3164	* CNTIN register.
mbed_official	324:406fd2029f23	3165	*
mbed_official	324:406fd2029f23	3166	* Values:
mbed_official	324:406fd2029f23	3167	* - 0 - The generation of initialization trigger is disabled.
mbed_official	324:406fd2029f23	3168	* - 1 - The generation of initialization trigger is enabled.
mbed_official	324:406fd2029f23	3169	*/
mbed_official	324:406fd2029f23	3170	/@{/
mbed_official	324:406fd2029f23	3171	#define BP_FTM_EXTTRIG_INITTRIGEN (6U) /!< Bit position for FTM_EXTTRIG_INITTRIGEN. /
mbed_official	324:406fd2029f23	3172	#define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /!< Bit mask for FTM_EXTTRIG_INITTRIGEN. /
mbed_official	324:406fd2029f23	3173	#define BS_FTM_EXTTRIG_INITTRIGEN (1U) /!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. /
mbed_official	324:406fd2029f23	3174
mbed_official	324:406fd2029f23	3175	/! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. /
mbed_official	324:406fd2029f23	3176	#define BR_FTM_EXTTRIG_INITTRIGEN(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN))
mbed_official	324:406fd2029f23	3177
mbed_official	324:406fd2029f23	3178	/! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. /
mbed_official	324:406fd2029f23	3179	#define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
mbed_official	324:406fd2029f23	3180
mbed_official	324:406fd2029f23	3181	/! @brief Set the INITTRIGEN field to a new value. /
mbed_official	324:406fd2029f23	3182	#define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN) = (v))
mbed_official	324:406fd2029f23	3183	/@}/
mbed_official	324:406fd2029f23	3184
mbed_official	324:406fd2029f23	3185	/*!
mbed_official	324:406fd2029f23	3186	* @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
mbed_official	324:406fd2029f23	3187	*
mbed_official	324:406fd2029f23	3188	* Set by hardware when a channel trigger is generated. Clear TRIGF by reading
mbed_official	324:406fd2029f23	3189	* EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
mbed_official	324:406fd2029f23	3190	* has no effect. If another channel trigger is generated before the clearing
mbed_official	324:406fd2029f23	3191	* sequence is completed, the sequence is reset so TRIGF remains set after the clear
mbed_official	324:406fd2029f23	3192	* sequence is completed for the earlier TRIGF.
mbed_official	324:406fd2029f23	3193	*
mbed_official	324:406fd2029f23	3194	* Values:
mbed_official	324:406fd2029f23	3195	* - 0 - No channel trigger was generated.
mbed_official	324:406fd2029f23	3196	* - 1 - A channel trigger was generated.
mbed_official	324:406fd2029f23	3197	*/
mbed_official	324:406fd2029f23	3198	/@{/
mbed_official	324:406fd2029f23	3199	#define BP_FTM_EXTTRIG_TRIGF (7U) /!< Bit position for FTM_EXTTRIG_TRIGF. /
mbed_official	324:406fd2029f23	3200	#define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /!< Bit mask for FTM_EXTTRIG_TRIGF. /
mbed_official	324:406fd2029f23	3201	#define BS_FTM_EXTTRIG_TRIGF (1U) /!< Bit field size in bits for FTM_EXTTRIG_TRIGF. /
mbed_official	324:406fd2029f23	3202
mbed_official	324:406fd2029f23	3203	/! @brief Read current value of the FTM_EXTTRIG_TRIGF field. /
mbed_official	324:406fd2029f23	3204	#define BR_FTM_EXTTRIG_TRIGF(x) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF))
mbed_official	324:406fd2029f23	3205
mbed_official	324:406fd2029f23	3206	/! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. /
mbed_official	324:406fd2029f23	3207	#define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
mbed_official	324:406fd2029f23	3208
mbed_official	324:406fd2029f23	3209	/! @brief Set the TRIGF field to a new value. /
mbed_official	324:406fd2029f23	3210	#define BW_FTM_EXTTRIG_TRIGF(x, v) (BITBAND_ACCESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF) = (v))
mbed_official	324:406fd2029f23	3211	/@}/
mbed_official	324:406fd2029f23	3212
mbed_official	324:406fd2029f23	3213	/*******************************************************************************
mbed_official	324:406fd2029f23	3214	* HW_FTM_POL - Channels Polarity
mbed_official	324:406fd2029f23	3215	******************************************************************************/
mbed_official	324:406fd2029f23	3216
mbed_official	324:406fd2029f23	3217	/*!
mbed_official	324:406fd2029f23	3218	* @brief HW_FTM_POL - Channels Polarity (RW)
mbed_official	324:406fd2029f23	3219	*
mbed_official	324:406fd2029f23	3220	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3221	*
mbed_official	324:406fd2029f23	3222	* This register defines the output polarity of the FTM channels. The safe value
mbed_official	324:406fd2029f23	3223	* that is driven in a channel output when the fault control is enabled and a
mbed_official	324:406fd2029f23	3224	* fault condition is detected is the inactive state of the channel. That is, the
mbed_official	324:406fd2029f23	3225	* safe value of a channel is the value of its POL bit.
mbed_official	324:406fd2029f23	3226	*/
mbed_official	324:406fd2029f23	3227	typedef union _hw_ftm_pol
mbed_official	324:406fd2029f23	3228	{
mbed_official	324:406fd2029f23	3229	uint32_t U;
mbed_official	324:406fd2029f23	3230	struct _hw_ftm_pol_bitfields
mbed_official	324:406fd2029f23	3231	{
mbed_official	324:406fd2029f23	3232	uint32_t POL0 : 1; /!< [0] Channel 0 Polarity /
mbed_official	324:406fd2029f23	3233	uint32_t POL1 : 1; /!< [1] Channel 1 Polarity /
mbed_official	324:406fd2029f23	3234	uint32_t POL2 : 1; /!< [2] Channel 2 Polarity /
mbed_official	324:406fd2029f23	3235	uint32_t POL3 : 1; /!< [3] Channel 3 Polarity /
mbed_official	324:406fd2029f23	3236	uint32_t POL4 : 1; /!< [4] Channel 4 Polarity /
mbed_official	324:406fd2029f23	3237	uint32_t POL5 : 1; /!< [5] Channel 5 Polarity /
mbed_official	324:406fd2029f23	3238	uint32_t POL6 : 1; /!< [6] Channel 6 Polarity /
mbed_official	324:406fd2029f23	3239	uint32_t POL7 : 1; /!< [7] Channel 7 Polarity /
mbed_official	324:406fd2029f23	3240	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	3241	} B;
mbed_official	324:406fd2029f23	3242	} hw_ftm_pol_t;
mbed_official	324:406fd2029f23	3243
mbed_official	324:406fd2029f23	3244	/*!
mbed_official	324:406fd2029f23	3245	* @name Constants and macros for entire FTM_POL register
mbed_official	324:406fd2029f23	3246	*/
mbed_official	324:406fd2029f23	3247	/@{/
mbed_official	324:406fd2029f23	3248	#define HW_FTM_POL_ADDR(x) ((x) + 0x70U)
mbed_official	324:406fd2029f23	3249
mbed_official	324:406fd2029f23	3250	#define HW_FTM_POL(x) ((__IO hw_ftm_pol_t ) HW_FTM_POL_ADDR(x))
mbed_official	324:406fd2029f23	3251	#define HW_FTM_POL_RD(x) (HW_FTM_POL(x).U)
mbed_official	324:406fd2029f23	3252	#define HW_FTM_POL_WR(x, v) (HW_FTM_POL(x).U = (v))
mbed_official	324:406fd2029f23	3253	#define HW_FTM_POL_SET(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3254	#define HW_FTM_POL_CLR(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3255	#define HW_FTM_POL_TOG(x, v) (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3256	/@}/
mbed_official	324:406fd2029f23	3257
mbed_official	324:406fd2029f23	3258	/*
mbed_official	324:406fd2029f23	3259	* Constants & macros for individual FTM_POL bitfields
mbed_official	324:406fd2029f23	3260	*/
mbed_official	324:406fd2029f23	3261
mbed_official	324:406fd2029f23	3262	/*!
mbed_official	324:406fd2029f23	3263	* @name Register FTM_POL, field POL0[0] (RW)
mbed_official	324:406fd2029f23	3264	*
mbed_official	324:406fd2029f23	3265	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3266	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3267	*
mbed_official	324:406fd2029f23	3268	* Values:
mbed_official	324:406fd2029f23	3269	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3270	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3271	*/
mbed_official	324:406fd2029f23	3272	/@{/
mbed_official	324:406fd2029f23	3273	#define BP_FTM_POL_POL0 (0U) /!< Bit position for FTM_POL_POL0. /
mbed_official	324:406fd2029f23	3274	#define BM_FTM_POL_POL0 (0x00000001U) /!< Bit mask for FTM_POL_POL0. /
mbed_official	324:406fd2029f23	3275	#define BS_FTM_POL_POL0 (1U) /!< Bit field size in bits for FTM_POL_POL0. /
mbed_official	324:406fd2029f23	3276
mbed_official	324:406fd2029f23	3277	/! @brief Read current value of the FTM_POL_POL0 field. /
mbed_official	324:406fd2029f23	3278	#define BR_FTM_POL_POL0(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0))
mbed_official	324:406fd2029f23	3279
mbed_official	324:406fd2029f23	3280	/! @brief Format value for bitfield FTM_POL_POL0. /
mbed_official	324:406fd2029f23	3281	#define BF_FTM_POL_POL0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
mbed_official	324:406fd2029f23	3282
mbed_official	324:406fd2029f23	3283	/! @brief Set the POL0 field to a new value. /
mbed_official	324:406fd2029f23	3284	#define BW_FTM_POL_POL0(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0) = (v))
mbed_official	324:406fd2029f23	3285	/@}/
mbed_official	324:406fd2029f23	3286
mbed_official	324:406fd2029f23	3287	/*!
mbed_official	324:406fd2029f23	3288	* @name Register FTM_POL, field POL1[1] (RW)
mbed_official	324:406fd2029f23	3289	*
mbed_official	324:406fd2029f23	3290	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3291	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3292	*
mbed_official	324:406fd2029f23	3293	* Values:
mbed_official	324:406fd2029f23	3294	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3295	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3296	*/
mbed_official	324:406fd2029f23	3297	/@{/
mbed_official	324:406fd2029f23	3298	#define BP_FTM_POL_POL1 (1U) /!< Bit position for FTM_POL_POL1. /
mbed_official	324:406fd2029f23	3299	#define BM_FTM_POL_POL1 (0x00000002U) /!< Bit mask for FTM_POL_POL1. /
mbed_official	324:406fd2029f23	3300	#define BS_FTM_POL_POL1 (1U) /!< Bit field size in bits for FTM_POL_POL1. /
mbed_official	324:406fd2029f23	3301
mbed_official	324:406fd2029f23	3302	/! @brief Read current value of the FTM_POL_POL1 field. /
mbed_official	324:406fd2029f23	3303	#define BR_FTM_POL_POL1(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1))
mbed_official	324:406fd2029f23	3304
mbed_official	324:406fd2029f23	3305	/! @brief Format value for bitfield FTM_POL_POL1. /
mbed_official	324:406fd2029f23	3306	#define BF_FTM_POL_POL1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
mbed_official	324:406fd2029f23	3307
mbed_official	324:406fd2029f23	3308	/! @brief Set the POL1 field to a new value. /
mbed_official	324:406fd2029f23	3309	#define BW_FTM_POL_POL1(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1) = (v))
mbed_official	324:406fd2029f23	3310	/@}/
mbed_official	324:406fd2029f23	3311
mbed_official	324:406fd2029f23	3312	/*!
mbed_official	324:406fd2029f23	3313	* @name Register FTM_POL, field POL2[2] (RW)
mbed_official	324:406fd2029f23	3314	*
mbed_official	324:406fd2029f23	3315	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3316	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3317	*
mbed_official	324:406fd2029f23	3318	* Values:
mbed_official	324:406fd2029f23	3319	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3320	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3321	*/
mbed_official	324:406fd2029f23	3322	/@{/
mbed_official	324:406fd2029f23	3323	#define BP_FTM_POL_POL2 (2U) /!< Bit position for FTM_POL_POL2. /
mbed_official	324:406fd2029f23	3324	#define BM_FTM_POL_POL2 (0x00000004U) /!< Bit mask for FTM_POL_POL2. /
mbed_official	324:406fd2029f23	3325	#define BS_FTM_POL_POL2 (1U) /!< Bit field size in bits for FTM_POL_POL2. /
mbed_official	324:406fd2029f23	3326
mbed_official	324:406fd2029f23	3327	/! @brief Read current value of the FTM_POL_POL2 field. /
mbed_official	324:406fd2029f23	3328	#define BR_FTM_POL_POL2(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2))
mbed_official	324:406fd2029f23	3329
mbed_official	324:406fd2029f23	3330	/! @brief Format value for bitfield FTM_POL_POL2. /
mbed_official	324:406fd2029f23	3331	#define BF_FTM_POL_POL2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
mbed_official	324:406fd2029f23	3332
mbed_official	324:406fd2029f23	3333	/! @brief Set the POL2 field to a new value. /
mbed_official	324:406fd2029f23	3334	#define BW_FTM_POL_POL2(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2) = (v))
mbed_official	324:406fd2029f23	3335	/@}/
mbed_official	324:406fd2029f23	3336
mbed_official	324:406fd2029f23	3337	/*!
mbed_official	324:406fd2029f23	3338	* @name Register FTM_POL, field POL3[3] (RW)
mbed_official	324:406fd2029f23	3339	*
mbed_official	324:406fd2029f23	3340	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3341	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3342	*
mbed_official	324:406fd2029f23	3343	* Values:
mbed_official	324:406fd2029f23	3344	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3345	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3346	*/
mbed_official	324:406fd2029f23	3347	/@{/
mbed_official	324:406fd2029f23	3348	#define BP_FTM_POL_POL3 (3U) /!< Bit position for FTM_POL_POL3. /
mbed_official	324:406fd2029f23	3349	#define BM_FTM_POL_POL3 (0x00000008U) /!< Bit mask for FTM_POL_POL3. /
mbed_official	324:406fd2029f23	3350	#define BS_FTM_POL_POL3 (1U) /!< Bit field size in bits for FTM_POL_POL3. /
mbed_official	324:406fd2029f23	3351
mbed_official	324:406fd2029f23	3352	/! @brief Read current value of the FTM_POL_POL3 field. /
mbed_official	324:406fd2029f23	3353	#define BR_FTM_POL_POL3(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3))
mbed_official	324:406fd2029f23	3354
mbed_official	324:406fd2029f23	3355	/! @brief Format value for bitfield FTM_POL_POL3. /
mbed_official	324:406fd2029f23	3356	#define BF_FTM_POL_POL3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
mbed_official	324:406fd2029f23	3357
mbed_official	324:406fd2029f23	3358	/! @brief Set the POL3 field to a new value. /
mbed_official	324:406fd2029f23	3359	#define BW_FTM_POL_POL3(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3) = (v))
mbed_official	324:406fd2029f23	3360	/@}/
mbed_official	324:406fd2029f23	3361
mbed_official	324:406fd2029f23	3362	/*!
mbed_official	324:406fd2029f23	3363	* @name Register FTM_POL, field POL4[4] (RW)
mbed_official	324:406fd2029f23	3364	*
mbed_official	324:406fd2029f23	3365	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3366	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3367	*
mbed_official	324:406fd2029f23	3368	* Values:
mbed_official	324:406fd2029f23	3369	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3370	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3371	*/
mbed_official	324:406fd2029f23	3372	/@{/
mbed_official	324:406fd2029f23	3373	#define BP_FTM_POL_POL4 (4U) /!< Bit position for FTM_POL_POL4. /
mbed_official	324:406fd2029f23	3374	#define BM_FTM_POL_POL4 (0x00000010U) /!< Bit mask for FTM_POL_POL4. /
mbed_official	324:406fd2029f23	3375	#define BS_FTM_POL_POL4 (1U) /!< Bit field size in bits for FTM_POL_POL4. /
mbed_official	324:406fd2029f23	3376
mbed_official	324:406fd2029f23	3377	/! @brief Read current value of the FTM_POL_POL4 field. /
mbed_official	324:406fd2029f23	3378	#define BR_FTM_POL_POL4(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4))
mbed_official	324:406fd2029f23	3379
mbed_official	324:406fd2029f23	3380	/! @brief Format value for bitfield FTM_POL_POL4. /
mbed_official	324:406fd2029f23	3381	#define BF_FTM_POL_POL4(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
mbed_official	324:406fd2029f23	3382
mbed_official	324:406fd2029f23	3383	/! @brief Set the POL4 field to a new value. /
mbed_official	324:406fd2029f23	3384	#define BW_FTM_POL_POL4(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4) = (v))
mbed_official	324:406fd2029f23	3385	/@}/
mbed_official	324:406fd2029f23	3386
mbed_official	324:406fd2029f23	3387	/*!
mbed_official	324:406fd2029f23	3388	* @name Register FTM_POL, field POL5[5] (RW)
mbed_official	324:406fd2029f23	3389	*
mbed_official	324:406fd2029f23	3390	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3391	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3392	*
mbed_official	324:406fd2029f23	3393	* Values:
mbed_official	324:406fd2029f23	3394	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3395	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3396	*/
mbed_official	324:406fd2029f23	3397	/@{/
mbed_official	324:406fd2029f23	3398	#define BP_FTM_POL_POL5 (5U) /!< Bit position for FTM_POL_POL5. /
mbed_official	324:406fd2029f23	3399	#define BM_FTM_POL_POL5 (0x00000020U) /!< Bit mask for FTM_POL_POL5. /
mbed_official	324:406fd2029f23	3400	#define BS_FTM_POL_POL5 (1U) /!< Bit field size in bits for FTM_POL_POL5. /
mbed_official	324:406fd2029f23	3401
mbed_official	324:406fd2029f23	3402	/! @brief Read current value of the FTM_POL_POL5 field. /
mbed_official	324:406fd2029f23	3403	#define BR_FTM_POL_POL5(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5))
mbed_official	324:406fd2029f23	3404
mbed_official	324:406fd2029f23	3405	/! @brief Format value for bitfield FTM_POL_POL5. /
mbed_official	324:406fd2029f23	3406	#define BF_FTM_POL_POL5(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
mbed_official	324:406fd2029f23	3407
mbed_official	324:406fd2029f23	3408	/! @brief Set the POL5 field to a new value. /
mbed_official	324:406fd2029f23	3409	#define BW_FTM_POL_POL5(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5) = (v))
mbed_official	324:406fd2029f23	3410	/@}/
mbed_official	324:406fd2029f23	3411
mbed_official	324:406fd2029f23	3412	/*!
mbed_official	324:406fd2029f23	3413	* @name Register FTM_POL, field POL6[6] (RW)
mbed_official	324:406fd2029f23	3414	*
mbed_official	324:406fd2029f23	3415	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3416	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3417	*
mbed_official	324:406fd2029f23	3418	* Values:
mbed_official	324:406fd2029f23	3419	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3420	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3421	*/
mbed_official	324:406fd2029f23	3422	/@{/
mbed_official	324:406fd2029f23	3423	#define BP_FTM_POL_POL6 (6U) /!< Bit position for FTM_POL_POL6. /
mbed_official	324:406fd2029f23	3424	#define BM_FTM_POL_POL6 (0x00000040U) /!< Bit mask for FTM_POL_POL6. /
mbed_official	324:406fd2029f23	3425	#define BS_FTM_POL_POL6 (1U) /!< Bit field size in bits for FTM_POL_POL6. /
mbed_official	324:406fd2029f23	3426
mbed_official	324:406fd2029f23	3427	/! @brief Read current value of the FTM_POL_POL6 field. /
mbed_official	324:406fd2029f23	3428	#define BR_FTM_POL_POL6(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6))
mbed_official	324:406fd2029f23	3429
mbed_official	324:406fd2029f23	3430	/! @brief Format value for bitfield FTM_POL_POL6. /
mbed_official	324:406fd2029f23	3431	#define BF_FTM_POL_POL6(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
mbed_official	324:406fd2029f23	3432
mbed_official	324:406fd2029f23	3433	/! @brief Set the POL6 field to a new value. /
mbed_official	324:406fd2029f23	3434	#define BW_FTM_POL_POL6(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6) = (v))
mbed_official	324:406fd2029f23	3435	/@}/
mbed_official	324:406fd2029f23	3436
mbed_official	324:406fd2029f23	3437	/*!
mbed_official	324:406fd2029f23	3438	* @name Register FTM_POL, field POL7[7] (RW)
mbed_official	324:406fd2029f23	3439	*
mbed_official	324:406fd2029f23	3440	* Defines the polarity of the channel output. This field is write protected. It
mbed_official	324:406fd2029f23	3441	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3442	*
mbed_official	324:406fd2029f23	3443	* Values:
mbed_official	324:406fd2029f23	3444	* - 0 - The channel polarity is active high.
mbed_official	324:406fd2029f23	3445	* - 1 - The channel polarity is active low.
mbed_official	324:406fd2029f23	3446	*/
mbed_official	324:406fd2029f23	3447	/@{/
mbed_official	324:406fd2029f23	3448	#define BP_FTM_POL_POL7 (7U) /!< Bit position for FTM_POL_POL7. /
mbed_official	324:406fd2029f23	3449	#define BM_FTM_POL_POL7 (0x00000080U) /!< Bit mask for FTM_POL_POL7. /
mbed_official	324:406fd2029f23	3450	#define BS_FTM_POL_POL7 (1U) /!< Bit field size in bits for FTM_POL_POL7. /
mbed_official	324:406fd2029f23	3451
mbed_official	324:406fd2029f23	3452	/! @brief Read current value of the FTM_POL_POL7 field. /
mbed_official	324:406fd2029f23	3453	#define BR_FTM_POL_POL7(x) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7))
mbed_official	324:406fd2029f23	3454
mbed_official	324:406fd2029f23	3455	/! @brief Format value for bitfield FTM_POL_POL7. /
mbed_official	324:406fd2029f23	3456	#define BF_FTM_POL_POL7(v) ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
mbed_official	324:406fd2029f23	3457
mbed_official	324:406fd2029f23	3458	/! @brief Set the POL7 field to a new value. /
mbed_official	324:406fd2029f23	3459	#define BW_FTM_POL_POL7(x, v) (BITBAND_ACCESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7) = (v))
mbed_official	324:406fd2029f23	3460	/@}/
mbed_official	324:406fd2029f23	3461
mbed_official	324:406fd2029f23	3462	/*******************************************************************************
mbed_official	324:406fd2029f23	3463	* HW_FTM_FMS - Fault Mode Status
mbed_official	324:406fd2029f23	3464	******************************************************************************/
mbed_official	324:406fd2029f23	3465
mbed_official	324:406fd2029f23	3466	/*!
mbed_official	324:406fd2029f23	3467	* @brief HW_FTM_FMS - Fault Mode Status (RW)
mbed_official	324:406fd2029f23	3468	*
mbed_official	324:406fd2029f23	3469	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3470	*
mbed_official	324:406fd2029f23	3471	* This register contains the fault detection flags, write protection enable
mbed_official	324:406fd2029f23	3472	* bit, and the logic OR of the enabled fault inputs.
mbed_official	324:406fd2029f23	3473	*/
mbed_official	324:406fd2029f23	3474	typedef union _hw_ftm_fms
mbed_official	324:406fd2029f23	3475	{
mbed_official	324:406fd2029f23	3476	uint32_t U;
mbed_official	324:406fd2029f23	3477	struct _hw_ftm_fms_bitfields
mbed_official	324:406fd2029f23	3478	{
mbed_official	324:406fd2029f23	3479	uint32_t FAULTF0 : 1; /!< [0] Fault Detection Flag 0 /
mbed_official	324:406fd2029f23	3480	uint32_t FAULTF1 : 1; /!< [1] Fault Detection Flag 1 /
mbed_official	324:406fd2029f23	3481	uint32_t FAULTF2 : 1; /!< [2] Fault Detection Flag 2 /
mbed_official	324:406fd2029f23	3482	uint32_t FAULTF3 : 1; /!< [3] Fault Detection Flag 3 /
mbed_official	324:406fd2029f23	3483	uint32_t RESERVED0 : 1; /!< [4] /
mbed_official	324:406fd2029f23	3484	uint32_t FAULTIN : 1; /!< [5] Fault Inputs /
mbed_official	324:406fd2029f23	3485	uint32_t WPEN : 1; /!< [6] Write Protection Enable /
mbed_official	324:406fd2029f23	3486	uint32_t FAULTF : 1; /!< [7] Fault Detection Flag /
mbed_official	324:406fd2029f23	3487	uint32_t RESERVED1 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	3488	} B;
mbed_official	324:406fd2029f23	3489	} hw_ftm_fms_t;
mbed_official	324:406fd2029f23	3490
mbed_official	324:406fd2029f23	3491	/*!
mbed_official	324:406fd2029f23	3492	* @name Constants and macros for entire FTM_FMS register
mbed_official	324:406fd2029f23	3493	*/
mbed_official	324:406fd2029f23	3494	/@{/
mbed_official	324:406fd2029f23	3495	#define HW_FTM_FMS_ADDR(x) ((x) + 0x74U)
mbed_official	324:406fd2029f23	3496
mbed_official	324:406fd2029f23	3497	#define HW_FTM_FMS(x) ((__IO hw_ftm_fms_t ) HW_FTM_FMS_ADDR(x))
mbed_official	324:406fd2029f23	3498	#define HW_FTM_FMS_RD(x) (HW_FTM_FMS(x).U)
mbed_official	324:406fd2029f23	3499	#define HW_FTM_FMS_WR(x, v) (HW_FTM_FMS(x).U = (v))
mbed_official	324:406fd2029f23	3500	#define HW_FTM_FMS_SET(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3501	#define HW_FTM_FMS_CLR(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3502	#define HW_FTM_FMS_TOG(x, v) (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3503	/@}/
mbed_official	324:406fd2029f23	3504
mbed_official	324:406fd2029f23	3505	/*
mbed_official	324:406fd2029f23	3506	* Constants & macros for individual FTM_FMS bitfields
mbed_official	324:406fd2029f23	3507	*/
mbed_official	324:406fd2029f23	3508
mbed_official	324:406fd2029f23	3509	/*!
mbed_official	324:406fd2029f23	3510	* @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
mbed_official	324:406fd2029f23	3511	*
mbed_official	324:406fd2029f23	3512	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	324:406fd2029f23	3513	* is enabled and a fault condition is detected at the fault input. Clear FAULTF0
mbed_official	324:406fd2029f23	3514	* by reading the FMS register while FAULTF0 is set and then writing a 0 to
mbed_official	324:406fd2029f23	3515	* FAULTF0 while there is no existing fault condition at the corresponding fault
mbed_official	324:406fd2029f23	3516	* input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
mbed_official	324:406fd2029f23	3517	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	324:406fd2029f23	3518	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	324:406fd2029f23	3519	* so FAULTF0 remains set after the clearing sequence is completed for the
mbed_official	324:406fd2029f23	3520	* earlier fault condition.
mbed_official	324:406fd2029f23	3521	*
mbed_official	324:406fd2029f23	3522	* Values:
mbed_official	324:406fd2029f23	3523	* - 0 - No fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3524	* - 1 - A fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3525	*/
mbed_official	324:406fd2029f23	3526	/@{/
mbed_official	324:406fd2029f23	3527	#define BP_FTM_FMS_FAULTF0 (0U) /!< Bit position for FTM_FMS_FAULTF0. /
mbed_official	324:406fd2029f23	3528	#define BM_FTM_FMS_FAULTF0 (0x00000001U) /!< Bit mask for FTM_FMS_FAULTF0. /
mbed_official	324:406fd2029f23	3529	#define BS_FTM_FMS_FAULTF0 (1U) /!< Bit field size in bits for FTM_FMS_FAULTF0. /
mbed_official	324:406fd2029f23	3530
mbed_official	324:406fd2029f23	3531	/! @brief Read current value of the FTM_FMS_FAULTF0 field. /
mbed_official	324:406fd2029f23	3532	#define BR_FTM_FMS_FAULTF0(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0))
mbed_official	324:406fd2029f23	3533
mbed_official	324:406fd2029f23	3534	/! @brief Format value for bitfield FTM_FMS_FAULTF0. /
mbed_official	324:406fd2029f23	3535	#define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
mbed_official	324:406fd2029f23	3536
mbed_official	324:406fd2029f23	3537	/! @brief Set the FAULTF0 field to a new value. /
mbed_official	324:406fd2029f23	3538	#define BW_FTM_FMS_FAULTF0(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0) = (v))
mbed_official	324:406fd2029f23	3539	/@}/
mbed_official	324:406fd2029f23	3540
mbed_official	324:406fd2029f23	3541	/*!
mbed_official	324:406fd2029f23	3542	* @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
mbed_official	324:406fd2029f23	3543	*
mbed_official	324:406fd2029f23	3544	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	324:406fd2029f23	3545	* is enabled and a fault condition is detected at the fault input. Clear FAULTF1
mbed_official	324:406fd2029f23	3546	* by reading the FMS register while FAULTF1 is set and then writing a 0 to
mbed_official	324:406fd2029f23	3547	* FAULTF1 while there is no existing fault condition at the corresponding fault
mbed_official	324:406fd2029f23	3548	* input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
mbed_official	324:406fd2029f23	3549	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	324:406fd2029f23	3550	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	324:406fd2029f23	3551	* so FAULTF1 remains set after the clearing sequence is completed for the
mbed_official	324:406fd2029f23	3552	* earlier fault condition.
mbed_official	324:406fd2029f23	3553	*
mbed_official	324:406fd2029f23	3554	* Values:
mbed_official	324:406fd2029f23	3555	* - 0 - No fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3556	* - 1 - A fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3557	*/
mbed_official	324:406fd2029f23	3558	/@{/
mbed_official	324:406fd2029f23	3559	#define BP_FTM_FMS_FAULTF1 (1U) /!< Bit position for FTM_FMS_FAULTF1. /
mbed_official	324:406fd2029f23	3560	#define BM_FTM_FMS_FAULTF1 (0x00000002U) /!< Bit mask for FTM_FMS_FAULTF1. /
mbed_official	324:406fd2029f23	3561	#define BS_FTM_FMS_FAULTF1 (1U) /!< Bit field size in bits for FTM_FMS_FAULTF1. /
mbed_official	324:406fd2029f23	3562
mbed_official	324:406fd2029f23	3563	/! @brief Read current value of the FTM_FMS_FAULTF1 field. /
mbed_official	324:406fd2029f23	3564	#define BR_FTM_FMS_FAULTF1(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1))
mbed_official	324:406fd2029f23	3565
mbed_official	324:406fd2029f23	3566	/! @brief Format value for bitfield FTM_FMS_FAULTF1. /
mbed_official	324:406fd2029f23	3567	#define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
mbed_official	324:406fd2029f23	3568
mbed_official	324:406fd2029f23	3569	/! @brief Set the FAULTF1 field to a new value. /
mbed_official	324:406fd2029f23	3570	#define BW_FTM_FMS_FAULTF1(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1) = (v))
mbed_official	324:406fd2029f23	3571	/@}/
mbed_official	324:406fd2029f23	3572
mbed_official	324:406fd2029f23	3573	/*!
mbed_official	324:406fd2029f23	3574	* @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
mbed_official	324:406fd2029f23	3575	*
mbed_official	324:406fd2029f23	3576	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	324:406fd2029f23	3577	* is enabled and a fault condition is detected at the fault input. Clear FAULTF2
mbed_official	324:406fd2029f23	3578	* by reading the FMS register while FAULTF2 is set and then writing a 0 to
mbed_official	324:406fd2029f23	3579	* FAULTF2 while there is no existing fault condition at the corresponding fault
mbed_official	324:406fd2029f23	3580	* input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
mbed_official	324:406fd2029f23	3581	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	324:406fd2029f23	3582	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	324:406fd2029f23	3583	* so FAULTF2 remains set after the clearing sequence is completed for the
mbed_official	324:406fd2029f23	3584	* earlier fault condition.
mbed_official	324:406fd2029f23	3585	*
mbed_official	324:406fd2029f23	3586	* Values:
mbed_official	324:406fd2029f23	3587	* - 0 - No fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3588	* - 1 - A fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3589	*/
mbed_official	324:406fd2029f23	3590	/@{/
mbed_official	324:406fd2029f23	3591	#define BP_FTM_FMS_FAULTF2 (2U) /!< Bit position for FTM_FMS_FAULTF2. /
mbed_official	324:406fd2029f23	3592	#define BM_FTM_FMS_FAULTF2 (0x00000004U) /!< Bit mask for FTM_FMS_FAULTF2. /
mbed_official	324:406fd2029f23	3593	#define BS_FTM_FMS_FAULTF2 (1U) /!< Bit field size in bits for FTM_FMS_FAULTF2. /
mbed_official	324:406fd2029f23	3594
mbed_official	324:406fd2029f23	3595	/! @brief Read current value of the FTM_FMS_FAULTF2 field. /
mbed_official	324:406fd2029f23	3596	#define BR_FTM_FMS_FAULTF2(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2))
mbed_official	324:406fd2029f23	3597
mbed_official	324:406fd2029f23	3598	/! @brief Format value for bitfield FTM_FMS_FAULTF2. /
mbed_official	324:406fd2029f23	3599	#define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
mbed_official	324:406fd2029f23	3600
mbed_official	324:406fd2029f23	3601	/! @brief Set the FAULTF2 field to a new value. /
mbed_official	324:406fd2029f23	3602	#define BW_FTM_FMS_FAULTF2(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2) = (v))
mbed_official	324:406fd2029f23	3603	/@}/
mbed_official	324:406fd2029f23	3604
mbed_official	324:406fd2029f23	3605	/*!
mbed_official	324:406fd2029f23	3606	* @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
mbed_official	324:406fd2029f23	3607	*
mbed_official	324:406fd2029f23	3608	* Set by hardware when fault control is enabled, the corresponding fault input
mbed_official	324:406fd2029f23	3609	* is enabled and a fault condition is detected at the fault input. Clear FAULTF3
mbed_official	324:406fd2029f23	3610	* by reading the FMS register while FAULTF3 is set and then writing a 0 to
mbed_official	324:406fd2029f23	3611	* FAULTF3 while there is no existing fault condition at the corresponding fault
mbed_official	324:406fd2029f23	3612	* input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
mbed_official	324:406fd2029f23	3613	* FAULTF bit is cleared. If another fault condition is detected at the corresponding
mbed_official	324:406fd2029f23	3614	* fault input before the clearing sequence is completed, the sequence is reset
mbed_official	324:406fd2029f23	3615	* so FAULTF3 remains set after the clearing sequence is completed for the
mbed_official	324:406fd2029f23	3616	* earlier fault condition.
mbed_official	324:406fd2029f23	3617	*
mbed_official	324:406fd2029f23	3618	* Values:
mbed_official	324:406fd2029f23	3619	* - 0 - No fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3620	* - 1 - A fault condition was detected at the fault input.
mbed_official	324:406fd2029f23	3621	*/
mbed_official	324:406fd2029f23	3622	/@{/
mbed_official	324:406fd2029f23	3623	#define BP_FTM_FMS_FAULTF3 (3U) /!< Bit position for FTM_FMS_FAULTF3. /
mbed_official	324:406fd2029f23	3624	#define BM_FTM_FMS_FAULTF3 (0x00000008U) /!< Bit mask for FTM_FMS_FAULTF3. /
mbed_official	324:406fd2029f23	3625	#define BS_FTM_FMS_FAULTF3 (1U) /!< Bit field size in bits for FTM_FMS_FAULTF3. /
mbed_official	324:406fd2029f23	3626
mbed_official	324:406fd2029f23	3627	/! @brief Read current value of the FTM_FMS_FAULTF3 field. /
mbed_official	324:406fd2029f23	3628	#define BR_FTM_FMS_FAULTF3(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3))
mbed_official	324:406fd2029f23	3629
mbed_official	324:406fd2029f23	3630	/! @brief Format value for bitfield FTM_FMS_FAULTF3. /
mbed_official	324:406fd2029f23	3631	#define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
mbed_official	324:406fd2029f23	3632
mbed_official	324:406fd2029f23	3633	/! @brief Set the FAULTF3 field to a new value. /
mbed_official	324:406fd2029f23	3634	#define BW_FTM_FMS_FAULTF3(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3) = (v))
mbed_official	324:406fd2029f23	3635	/@}/
mbed_official	324:406fd2029f23	3636
mbed_official	324:406fd2029f23	3637	/*!
mbed_official	324:406fd2029f23	3638	* @name Register FTM_FMS, field FAULTIN[5] (RO)
mbed_official	324:406fd2029f23	3639	*
mbed_official	324:406fd2029f23	3640	* Represents the logic OR of the enabled fault inputs after their filter (if
mbed_official	324:406fd2029f23	3641	* their filter is enabled) when fault control is enabled.
mbed_official	324:406fd2029f23	3642	*
mbed_official	324:406fd2029f23	3643	* Values:
mbed_official	324:406fd2029f23	3644	* - 0 - The logic OR of the enabled fault inputs is 0.
mbed_official	324:406fd2029f23	3645	* - 1 - The logic OR of the enabled fault inputs is 1.
mbed_official	324:406fd2029f23	3646	*/
mbed_official	324:406fd2029f23	3647	/@{/
mbed_official	324:406fd2029f23	3648	#define BP_FTM_FMS_FAULTIN (5U) /!< Bit position for FTM_FMS_FAULTIN. /
mbed_official	324:406fd2029f23	3649	#define BM_FTM_FMS_FAULTIN (0x00000020U) /!< Bit mask for FTM_FMS_FAULTIN. /
mbed_official	324:406fd2029f23	3650	#define BS_FTM_FMS_FAULTIN (1U) /!< Bit field size in bits for FTM_FMS_FAULTIN. /
mbed_official	324:406fd2029f23	3651
mbed_official	324:406fd2029f23	3652	/! @brief Read current value of the FTM_FMS_FAULTIN field. /
mbed_official	324:406fd2029f23	3653	#define BR_FTM_FMS_FAULTIN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN))
mbed_official	324:406fd2029f23	3654	/@}/
mbed_official	324:406fd2029f23	3655
mbed_official	324:406fd2029f23	3656	/*!
mbed_official	324:406fd2029f23	3657	* @name Register FTM_FMS, field WPEN[6] (RW)
mbed_official	324:406fd2029f23	3658	*
mbed_official	324:406fd2029f23	3659	* The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
mbed_official	324:406fd2029f23	3660	* to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
mbed_official	324:406fd2029f23	3661	* WPDIS. Writing 0 to WPEN has no effect.
mbed_official	324:406fd2029f23	3662	*
mbed_official	324:406fd2029f23	3663	* Values:
mbed_official	324:406fd2029f23	3664	* - 0 - Write protection is disabled. Write protected bits can be written.
mbed_official	324:406fd2029f23	3665	* - 1 - Write protection is enabled. Write protected bits cannot be written.
mbed_official	324:406fd2029f23	3666	*/
mbed_official	324:406fd2029f23	3667	/@{/
mbed_official	324:406fd2029f23	3668	#define BP_FTM_FMS_WPEN (6U) /!< Bit position for FTM_FMS_WPEN. /
mbed_official	324:406fd2029f23	3669	#define BM_FTM_FMS_WPEN (0x00000040U) /!< Bit mask for FTM_FMS_WPEN. /
mbed_official	324:406fd2029f23	3670	#define BS_FTM_FMS_WPEN (1U) /!< Bit field size in bits for FTM_FMS_WPEN. /
mbed_official	324:406fd2029f23	3671
mbed_official	324:406fd2029f23	3672	/! @brief Read current value of the FTM_FMS_WPEN field. /
mbed_official	324:406fd2029f23	3673	#define BR_FTM_FMS_WPEN(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN))
mbed_official	324:406fd2029f23	3674
mbed_official	324:406fd2029f23	3675	/! @brief Format value for bitfield FTM_FMS_WPEN. /
mbed_official	324:406fd2029f23	3676	#define BF_FTM_FMS_WPEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
mbed_official	324:406fd2029f23	3677
mbed_official	324:406fd2029f23	3678	/! @brief Set the WPEN field to a new value. /
mbed_official	324:406fd2029f23	3679	#define BW_FTM_FMS_WPEN(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN) = (v))
mbed_official	324:406fd2029f23	3680	/@}/
mbed_official	324:406fd2029f23	3681
mbed_official	324:406fd2029f23	3682	/*!
mbed_official	324:406fd2029f23	3683	* @name Register FTM_FMS, field FAULTF[7] (ROWZ)
mbed_official	324:406fd2029f23	3684	*
mbed_official	324:406fd2029f23	3685	* Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
mbed_official	324:406fd2029f23	3686	* Clear FAULTF by reading the FMS register while FAULTF is set and then writing
mbed_official	324:406fd2029f23	3687	* a 0 to FAULTF while there is no existing fault condition at the enabled fault
mbed_official	324:406fd2029f23	3688	* inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
mbed_official	324:406fd2029f23	3689	* detected in an enabled fault input before the clearing sequence is completed, the
mbed_official	324:406fd2029f23	3690	* sequence is reset so FAULTF remains set after the clearing sequence is
mbed_official	324:406fd2029f23	3691	* completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
mbed_official	324:406fd2029f23	3692	* are cleared individually.
mbed_official	324:406fd2029f23	3693	*
mbed_official	324:406fd2029f23	3694	* Values:
mbed_official	324:406fd2029f23	3695	* - 0 - No fault condition was detected.
mbed_official	324:406fd2029f23	3696	* - 1 - A fault condition was detected.
mbed_official	324:406fd2029f23	3697	*/
mbed_official	324:406fd2029f23	3698	/@{/
mbed_official	324:406fd2029f23	3699	#define BP_FTM_FMS_FAULTF (7U) /!< Bit position for FTM_FMS_FAULTF. /
mbed_official	324:406fd2029f23	3700	#define BM_FTM_FMS_FAULTF (0x00000080U) /!< Bit mask for FTM_FMS_FAULTF. /
mbed_official	324:406fd2029f23	3701	#define BS_FTM_FMS_FAULTF (1U) /!< Bit field size in bits for FTM_FMS_FAULTF. /
mbed_official	324:406fd2029f23	3702
mbed_official	324:406fd2029f23	3703	/! @brief Read current value of the FTM_FMS_FAULTF field. /
mbed_official	324:406fd2029f23	3704	#define BR_FTM_FMS_FAULTF(x) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF))
mbed_official	324:406fd2029f23	3705
mbed_official	324:406fd2029f23	3706	/! @brief Format value for bitfield FTM_FMS_FAULTF. /
mbed_official	324:406fd2029f23	3707	#define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
mbed_official	324:406fd2029f23	3708
mbed_official	324:406fd2029f23	3709	/! @brief Set the FAULTF field to a new value. /
mbed_official	324:406fd2029f23	3710	#define BW_FTM_FMS_FAULTF(x, v) (BITBAND_ACCESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF) = (v))
mbed_official	324:406fd2029f23	3711	/@}/
mbed_official	324:406fd2029f23	3712
mbed_official	324:406fd2029f23	3713	/*******************************************************************************
mbed_official	324:406fd2029f23	3714	* HW_FTM_FILTER - Input Capture Filter Control
mbed_official	324:406fd2029f23	3715	******************************************************************************/
mbed_official	324:406fd2029f23	3716
mbed_official	324:406fd2029f23	3717	/*!
mbed_official	324:406fd2029f23	3718	* @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
mbed_official	324:406fd2029f23	3719	*
mbed_official	324:406fd2029f23	3720	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3721	*
mbed_official	324:406fd2029f23	3722	* This register selects the filter value for the inputs of channels. Channels
mbed_official	324:406fd2029f23	3723	* 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
mbed_official	324:406fd2029f23	3724	* immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
mbed_official	324:406fd2029f23	3725	* in input modes. Failure to do this could result in a missing valid signal.
mbed_official	324:406fd2029f23	3726	*/
mbed_official	324:406fd2029f23	3727	typedef union _hw_ftm_filter
mbed_official	324:406fd2029f23	3728	{
mbed_official	324:406fd2029f23	3729	uint32_t U;
mbed_official	324:406fd2029f23	3730	struct _hw_ftm_filter_bitfields
mbed_official	324:406fd2029f23	3731	{
mbed_official	324:406fd2029f23	3732	uint32_t CH0FVAL : 4; /!< [3:0] Channel 0 Input Filter /
mbed_official	324:406fd2029f23	3733	uint32_t CH1FVAL : 4; /!< [7:4] Channel 1 Input Filter /
mbed_official	324:406fd2029f23	3734	uint32_t CH2FVAL : 4; /!< [11:8] Channel 2 Input Filter /
mbed_official	324:406fd2029f23	3735	uint32_t CH3FVAL : 4; /!< [15:12] Channel 3 Input Filter /
mbed_official	324:406fd2029f23	3736	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	3737	} B;
mbed_official	324:406fd2029f23	3738	} hw_ftm_filter_t;
mbed_official	324:406fd2029f23	3739
mbed_official	324:406fd2029f23	3740	/*!
mbed_official	324:406fd2029f23	3741	* @name Constants and macros for entire FTM_FILTER register
mbed_official	324:406fd2029f23	3742	*/
mbed_official	324:406fd2029f23	3743	/@{/
mbed_official	324:406fd2029f23	3744	#define HW_FTM_FILTER_ADDR(x) ((x) + 0x78U)
mbed_official	324:406fd2029f23	3745
mbed_official	324:406fd2029f23	3746	#define HW_FTM_FILTER(x) ((__IO hw_ftm_filter_t ) HW_FTM_FILTER_ADDR(x))
mbed_official	324:406fd2029f23	3747	#define HW_FTM_FILTER_RD(x) (HW_FTM_FILTER(x).U)
mbed_official	324:406fd2029f23	3748	#define HW_FTM_FILTER_WR(x, v) (HW_FTM_FILTER(x).U = (v))
mbed_official	324:406fd2029f23	3749	#define HW_FTM_FILTER_SET(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3750	#define HW_FTM_FILTER_CLR(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3751	#define HW_FTM_FILTER_TOG(x, v) (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3752	/@}/
mbed_official	324:406fd2029f23	3753
mbed_official	324:406fd2029f23	3754	/*
mbed_official	324:406fd2029f23	3755	* Constants & macros for individual FTM_FILTER bitfields
mbed_official	324:406fd2029f23	3756	*/
mbed_official	324:406fd2029f23	3757
mbed_official	324:406fd2029f23	3758	/*!
mbed_official	324:406fd2029f23	3759	* @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
mbed_official	324:406fd2029f23	3760	*
mbed_official	324:406fd2029f23	3761	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	324:406fd2029f23	3762	* the value is zero.
mbed_official	324:406fd2029f23	3763	*/
mbed_official	324:406fd2029f23	3764	/@{/
mbed_official	324:406fd2029f23	3765	#define BP_FTM_FILTER_CH0FVAL (0U) /!< Bit position for FTM_FILTER_CH0FVAL. /
mbed_official	324:406fd2029f23	3766	#define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /!< Bit mask for FTM_FILTER_CH0FVAL. /
mbed_official	324:406fd2029f23	3767	#define BS_FTM_FILTER_CH0FVAL (4U) /!< Bit field size in bits for FTM_FILTER_CH0FVAL. /
mbed_official	324:406fd2029f23	3768
mbed_official	324:406fd2029f23	3769	/! @brief Read current value of the FTM_FILTER_CH0FVAL field. /
mbed_official	324:406fd2029f23	3770	#define BR_FTM_FILTER_CH0FVAL(x) (HW_FTM_FILTER(x).B.CH0FVAL)
mbed_official	324:406fd2029f23	3771
mbed_official	324:406fd2029f23	3772	/! @brief Format value for bitfield FTM_FILTER_CH0FVAL. /
mbed_official	324:406fd2029f23	3773	#define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
mbed_official	324:406fd2029f23	3774
mbed_official	324:406fd2029f23	3775	/! @brief Set the CH0FVAL field to a new value. /
mbed_official	324:406fd2029f23	3776	#define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) \| BF_FTM_FILTER_CH0FVAL(v)))
mbed_official	324:406fd2029f23	3777	/@}/
mbed_official	324:406fd2029f23	3778
mbed_official	324:406fd2029f23	3779	/*!
mbed_official	324:406fd2029f23	3780	* @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
mbed_official	324:406fd2029f23	3781	*
mbed_official	324:406fd2029f23	3782	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	324:406fd2029f23	3783	* the value is zero.
mbed_official	324:406fd2029f23	3784	*/
mbed_official	324:406fd2029f23	3785	/@{/
mbed_official	324:406fd2029f23	3786	#define BP_FTM_FILTER_CH1FVAL (4U) /!< Bit position for FTM_FILTER_CH1FVAL. /
mbed_official	324:406fd2029f23	3787	#define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /!< Bit mask for FTM_FILTER_CH1FVAL. /
mbed_official	324:406fd2029f23	3788	#define BS_FTM_FILTER_CH1FVAL (4U) /!< Bit field size in bits for FTM_FILTER_CH1FVAL. /
mbed_official	324:406fd2029f23	3789
mbed_official	324:406fd2029f23	3790	/! @brief Read current value of the FTM_FILTER_CH1FVAL field. /
mbed_official	324:406fd2029f23	3791	#define BR_FTM_FILTER_CH1FVAL(x) (HW_FTM_FILTER(x).B.CH1FVAL)
mbed_official	324:406fd2029f23	3792
mbed_official	324:406fd2029f23	3793	/! @brief Format value for bitfield FTM_FILTER_CH1FVAL. /
mbed_official	324:406fd2029f23	3794	#define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
mbed_official	324:406fd2029f23	3795
mbed_official	324:406fd2029f23	3796	/! @brief Set the CH1FVAL field to a new value. /
mbed_official	324:406fd2029f23	3797	#define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) \| BF_FTM_FILTER_CH1FVAL(v)))
mbed_official	324:406fd2029f23	3798	/@}/
mbed_official	324:406fd2029f23	3799
mbed_official	324:406fd2029f23	3800	/*!
mbed_official	324:406fd2029f23	3801	* @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
mbed_official	324:406fd2029f23	3802	*
mbed_official	324:406fd2029f23	3803	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	324:406fd2029f23	3804	* the value is zero.
mbed_official	324:406fd2029f23	3805	*/
mbed_official	324:406fd2029f23	3806	/@{/
mbed_official	324:406fd2029f23	3807	#define BP_FTM_FILTER_CH2FVAL (8U) /!< Bit position for FTM_FILTER_CH2FVAL. /
mbed_official	324:406fd2029f23	3808	#define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /!< Bit mask for FTM_FILTER_CH2FVAL. /
mbed_official	324:406fd2029f23	3809	#define BS_FTM_FILTER_CH2FVAL (4U) /!< Bit field size in bits for FTM_FILTER_CH2FVAL. /
mbed_official	324:406fd2029f23	3810
mbed_official	324:406fd2029f23	3811	/! @brief Read current value of the FTM_FILTER_CH2FVAL field. /
mbed_official	324:406fd2029f23	3812	#define BR_FTM_FILTER_CH2FVAL(x) (HW_FTM_FILTER(x).B.CH2FVAL)
mbed_official	324:406fd2029f23	3813
mbed_official	324:406fd2029f23	3814	/! @brief Format value for bitfield FTM_FILTER_CH2FVAL. /
mbed_official	324:406fd2029f23	3815	#define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
mbed_official	324:406fd2029f23	3816
mbed_official	324:406fd2029f23	3817	/! @brief Set the CH2FVAL field to a new value. /
mbed_official	324:406fd2029f23	3818	#define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) \| BF_FTM_FILTER_CH2FVAL(v)))
mbed_official	324:406fd2029f23	3819	/@}/
mbed_official	324:406fd2029f23	3820
mbed_official	324:406fd2029f23	3821	/*!
mbed_official	324:406fd2029f23	3822	* @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
mbed_official	324:406fd2029f23	3823	*
mbed_official	324:406fd2029f23	3824	* Selects the filter value for the channel input. The filter is disabled when
mbed_official	324:406fd2029f23	3825	* the value is zero.
mbed_official	324:406fd2029f23	3826	*/
mbed_official	324:406fd2029f23	3827	/@{/
mbed_official	324:406fd2029f23	3828	#define BP_FTM_FILTER_CH3FVAL (12U) /!< Bit position for FTM_FILTER_CH3FVAL. /
mbed_official	324:406fd2029f23	3829	#define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /!< Bit mask for FTM_FILTER_CH3FVAL. /
mbed_official	324:406fd2029f23	3830	#define BS_FTM_FILTER_CH3FVAL (4U) /!< Bit field size in bits for FTM_FILTER_CH3FVAL. /
mbed_official	324:406fd2029f23	3831
mbed_official	324:406fd2029f23	3832	/! @brief Read current value of the FTM_FILTER_CH3FVAL field. /
mbed_official	324:406fd2029f23	3833	#define BR_FTM_FILTER_CH3FVAL(x) (HW_FTM_FILTER(x).B.CH3FVAL)
mbed_official	324:406fd2029f23	3834
mbed_official	324:406fd2029f23	3835	/! @brief Format value for bitfield FTM_FILTER_CH3FVAL. /
mbed_official	324:406fd2029f23	3836	#define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
mbed_official	324:406fd2029f23	3837
mbed_official	324:406fd2029f23	3838	/! @brief Set the CH3FVAL field to a new value. /
mbed_official	324:406fd2029f23	3839	#define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) \| BF_FTM_FILTER_CH3FVAL(v)))
mbed_official	324:406fd2029f23	3840	/@}/
mbed_official	324:406fd2029f23	3841
mbed_official	324:406fd2029f23	3842	/*******************************************************************************
mbed_official	324:406fd2029f23	3843	* HW_FTM_FLTCTRL - Fault Control
mbed_official	324:406fd2029f23	3844	******************************************************************************/
mbed_official	324:406fd2029f23	3845
mbed_official	324:406fd2029f23	3846	/*!
mbed_official	324:406fd2029f23	3847	* @brief HW_FTM_FLTCTRL - Fault Control (RW)
mbed_official	324:406fd2029f23	3848	*
mbed_official	324:406fd2029f23	3849	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	3850	*
mbed_official	324:406fd2029f23	3851	* This register selects the filter value for the fault inputs, enables the
mbed_official	324:406fd2029f23	3852	* fault inputs and the fault inputs filter.
mbed_official	324:406fd2029f23	3853	*/
mbed_official	324:406fd2029f23	3854	typedef union _hw_ftm_fltctrl
mbed_official	324:406fd2029f23	3855	{
mbed_official	324:406fd2029f23	3856	uint32_t U;
mbed_official	324:406fd2029f23	3857	struct _hw_ftm_fltctrl_bitfields
mbed_official	324:406fd2029f23	3858	{
mbed_official	324:406fd2029f23	3859	uint32_t FAULT0EN : 1; /!< [0] Fault Input 0 Enable /
mbed_official	324:406fd2029f23	3860	uint32_t FAULT1EN : 1; /!< [1] Fault Input 1 Enable /
mbed_official	324:406fd2029f23	3861	uint32_t FAULT2EN : 1; /!< [2] Fault Input 2 Enable /
mbed_official	324:406fd2029f23	3862	uint32_t FAULT3EN : 1; /!< [3] Fault Input 3 Enable /
mbed_official	324:406fd2029f23	3863	uint32_t FFLTR0EN : 1; /!< [4] Fault Input 0 Filter Enable /
mbed_official	324:406fd2029f23	3864	uint32_t FFLTR1EN : 1; /!< [5] Fault Input 1 Filter Enable /
mbed_official	324:406fd2029f23	3865	uint32_t FFLTR2EN : 1; /!< [6] Fault Input 2 Filter Enable /
mbed_official	324:406fd2029f23	3866	uint32_t FFLTR3EN : 1; /!< [7] Fault Input 3 Filter Enable /
mbed_official	324:406fd2029f23	3867	uint32_t FFVAL : 4; /!< [11:8] Fault Input Filter /
mbed_official	324:406fd2029f23	3868	uint32_t RESERVED0 : 20; /!< [31:12] /
mbed_official	324:406fd2029f23	3869	} B;
mbed_official	324:406fd2029f23	3870	} hw_ftm_fltctrl_t;
mbed_official	324:406fd2029f23	3871
mbed_official	324:406fd2029f23	3872	/*!
mbed_official	324:406fd2029f23	3873	* @name Constants and macros for entire FTM_FLTCTRL register
mbed_official	324:406fd2029f23	3874	*/
mbed_official	324:406fd2029f23	3875	/@{/
mbed_official	324:406fd2029f23	3876	#define HW_FTM_FLTCTRL_ADDR(x) ((x) + 0x7CU)
mbed_official	324:406fd2029f23	3877
mbed_official	324:406fd2029f23	3878	#define HW_FTM_FLTCTRL(x) ((__IO hw_ftm_fltctrl_t ) HW_FTM_FLTCTRL_ADDR(x))
mbed_official	324:406fd2029f23	3879	#define HW_FTM_FLTCTRL_RD(x) (HW_FTM_FLTCTRL(x).U)
mbed_official	324:406fd2029f23	3880	#define HW_FTM_FLTCTRL_WR(x, v) (HW_FTM_FLTCTRL(x).U = (v))
mbed_official	324:406fd2029f23	3881	#define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	3882	#define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	3883	#define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	3884	/@}/
mbed_official	324:406fd2029f23	3885
mbed_official	324:406fd2029f23	3886	/*
mbed_official	324:406fd2029f23	3887	* Constants & macros for individual FTM_FLTCTRL bitfields
mbed_official	324:406fd2029f23	3888	*/
mbed_official	324:406fd2029f23	3889
mbed_official	324:406fd2029f23	3890	/*!
mbed_official	324:406fd2029f23	3891	* @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
mbed_official	324:406fd2029f23	3892	*
mbed_official	324:406fd2029f23	3893	* Enables the fault input. This field is write protected. It can be written
mbed_official	324:406fd2029f23	3894	* only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3895	*
mbed_official	324:406fd2029f23	3896	* Values:
mbed_official	324:406fd2029f23	3897	* - 0 - Fault input is disabled.
mbed_official	324:406fd2029f23	3898	* - 1 - Fault input is enabled.
mbed_official	324:406fd2029f23	3899	*/
mbed_official	324:406fd2029f23	3900	/@{/
mbed_official	324:406fd2029f23	3901	#define BP_FTM_FLTCTRL_FAULT0EN (0U) /!< Bit position for FTM_FLTCTRL_FAULT0EN. /
mbed_official	324:406fd2029f23	3902	#define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /!< Bit mask for FTM_FLTCTRL_FAULT0EN. /
mbed_official	324:406fd2029f23	3903	#define BS_FTM_FLTCTRL_FAULT0EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. /
mbed_official	324:406fd2029f23	3904
mbed_official	324:406fd2029f23	3905	/! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. /
mbed_official	324:406fd2029f23	3906	#define BR_FTM_FLTCTRL_FAULT0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN))
mbed_official	324:406fd2029f23	3907
mbed_official	324:406fd2029f23	3908	/! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. /
mbed_official	324:406fd2029f23	3909	#define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
mbed_official	324:406fd2029f23	3910
mbed_official	324:406fd2029f23	3911	/! @brief Set the FAULT0EN field to a new value. /
mbed_official	324:406fd2029f23	3912	#define BW_FTM_FLTCTRL_FAULT0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN) = (v))
mbed_official	324:406fd2029f23	3913	/@}/
mbed_official	324:406fd2029f23	3914
mbed_official	324:406fd2029f23	3915	/*!
mbed_official	324:406fd2029f23	3916	* @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
mbed_official	324:406fd2029f23	3917	*
mbed_official	324:406fd2029f23	3918	* Enables the fault input. This field is write protected. It can be written
mbed_official	324:406fd2029f23	3919	* only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3920	*
mbed_official	324:406fd2029f23	3921	* Values:
mbed_official	324:406fd2029f23	3922	* - 0 - Fault input is disabled.
mbed_official	324:406fd2029f23	3923	* - 1 - Fault input is enabled.
mbed_official	324:406fd2029f23	3924	*/
mbed_official	324:406fd2029f23	3925	/@{/
mbed_official	324:406fd2029f23	3926	#define BP_FTM_FLTCTRL_FAULT1EN (1U) /!< Bit position for FTM_FLTCTRL_FAULT1EN. /
mbed_official	324:406fd2029f23	3927	#define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /!< Bit mask for FTM_FLTCTRL_FAULT1EN. /
mbed_official	324:406fd2029f23	3928	#define BS_FTM_FLTCTRL_FAULT1EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. /
mbed_official	324:406fd2029f23	3929
mbed_official	324:406fd2029f23	3930	/! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. /
mbed_official	324:406fd2029f23	3931	#define BR_FTM_FLTCTRL_FAULT1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN))
mbed_official	324:406fd2029f23	3932
mbed_official	324:406fd2029f23	3933	/! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. /
mbed_official	324:406fd2029f23	3934	#define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
mbed_official	324:406fd2029f23	3935
mbed_official	324:406fd2029f23	3936	/! @brief Set the FAULT1EN field to a new value. /
mbed_official	324:406fd2029f23	3937	#define BW_FTM_FLTCTRL_FAULT1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN) = (v))
mbed_official	324:406fd2029f23	3938	/@}/
mbed_official	324:406fd2029f23	3939
mbed_official	324:406fd2029f23	3940	/*!
mbed_official	324:406fd2029f23	3941	* @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
mbed_official	324:406fd2029f23	3942	*
mbed_official	324:406fd2029f23	3943	* Enables the fault input. This field is write protected. It can be written
mbed_official	324:406fd2029f23	3944	* only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3945	*
mbed_official	324:406fd2029f23	3946	* Values:
mbed_official	324:406fd2029f23	3947	* - 0 - Fault input is disabled.
mbed_official	324:406fd2029f23	3948	* - 1 - Fault input is enabled.
mbed_official	324:406fd2029f23	3949	*/
mbed_official	324:406fd2029f23	3950	/@{/
mbed_official	324:406fd2029f23	3951	#define BP_FTM_FLTCTRL_FAULT2EN (2U) /!< Bit position for FTM_FLTCTRL_FAULT2EN. /
mbed_official	324:406fd2029f23	3952	#define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /!< Bit mask for FTM_FLTCTRL_FAULT2EN. /
mbed_official	324:406fd2029f23	3953	#define BS_FTM_FLTCTRL_FAULT2EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. /
mbed_official	324:406fd2029f23	3954
mbed_official	324:406fd2029f23	3955	/! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. /
mbed_official	324:406fd2029f23	3956	#define BR_FTM_FLTCTRL_FAULT2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN))
mbed_official	324:406fd2029f23	3957
mbed_official	324:406fd2029f23	3958	/! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. /
mbed_official	324:406fd2029f23	3959	#define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
mbed_official	324:406fd2029f23	3960
mbed_official	324:406fd2029f23	3961	/! @brief Set the FAULT2EN field to a new value. /
mbed_official	324:406fd2029f23	3962	#define BW_FTM_FLTCTRL_FAULT2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN) = (v))
mbed_official	324:406fd2029f23	3963	/@}/
mbed_official	324:406fd2029f23	3964
mbed_official	324:406fd2029f23	3965	/*!
mbed_official	324:406fd2029f23	3966	* @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
mbed_official	324:406fd2029f23	3967	*
mbed_official	324:406fd2029f23	3968	* Enables the fault input. This field is write protected. It can be written
mbed_official	324:406fd2029f23	3969	* only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3970	*
mbed_official	324:406fd2029f23	3971	* Values:
mbed_official	324:406fd2029f23	3972	* - 0 - Fault input is disabled.
mbed_official	324:406fd2029f23	3973	* - 1 - Fault input is enabled.
mbed_official	324:406fd2029f23	3974	*/
mbed_official	324:406fd2029f23	3975	/@{/
mbed_official	324:406fd2029f23	3976	#define BP_FTM_FLTCTRL_FAULT3EN (3U) /!< Bit position for FTM_FLTCTRL_FAULT3EN. /
mbed_official	324:406fd2029f23	3977	#define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /!< Bit mask for FTM_FLTCTRL_FAULT3EN. /
mbed_official	324:406fd2029f23	3978	#define BS_FTM_FLTCTRL_FAULT3EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. /
mbed_official	324:406fd2029f23	3979
mbed_official	324:406fd2029f23	3980	/! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. /
mbed_official	324:406fd2029f23	3981	#define BR_FTM_FLTCTRL_FAULT3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN))
mbed_official	324:406fd2029f23	3982
mbed_official	324:406fd2029f23	3983	/! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. /
mbed_official	324:406fd2029f23	3984	#define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
mbed_official	324:406fd2029f23	3985
mbed_official	324:406fd2029f23	3986	/! @brief Set the FAULT3EN field to a new value. /
mbed_official	324:406fd2029f23	3987	#define BW_FTM_FLTCTRL_FAULT3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN) = (v))
mbed_official	324:406fd2029f23	3988	/@}/
mbed_official	324:406fd2029f23	3989
mbed_official	324:406fd2029f23	3990	/*!
mbed_official	324:406fd2029f23	3991	* @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
mbed_official	324:406fd2029f23	3992	*
mbed_official	324:406fd2029f23	3993	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	324:406fd2029f23	3994	* be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	3995	*
mbed_official	324:406fd2029f23	3996	* Values:
mbed_official	324:406fd2029f23	3997	* - 0 - Fault input filter is disabled.
mbed_official	324:406fd2029f23	3998	* - 1 - Fault input filter is enabled.
mbed_official	324:406fd2029f23	3999	*/
mbed_official	324:406fd2029f23	4000	/@{/
mbed_official	324:406fd2029f23	4001	#define BP_FTM_FLTCTRL_FFLTR0EN (4U) /!< Bit position for FTM_FLTCTRL_FFLTR0EN. /
mbed_official	324:406fd2029f23	4002	#define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /!< Bit mask for FTM_FLTCTRL_FFLTR0EN. /
mbed_official	324:406fd2029f23	4003	#define BS_FTM_FLTCTRL_FFLTR0EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. /
mbed_official	324:406fd2029f23	4004
mbed_official	324:406fd2029f23	4005	/! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. /
mbed_official	324:406fd2029f23	4006	#define BR_FTM_FLTCTRL_FFLTR0EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN))
mbed_official	324:406fd2029f23	4007
mbed_official	324:406fd2029f23	4008	/! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. /
mbed_official	324:406fd2029f23	4009	#define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
mbed_official	324:406fd2029f23	4010
mbed_official	324:406fd2029f23	4011	/! @brief Set the FFLTR0EN field to a new value. /
mbed_official	324:406fd2029f23	4012	#define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN) = (v))
mbed_official	324:406fd2029f23	4013	/@}/
mbed_official	324:406fd2029f23	4014
mbed_official	324:406fd2029f23	4015	/*!
mbed_official	324:406fd2029f23	4016	* @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
mbed_official	324:406fd2029f23	4017	*
mbed_official	324:406fd2029f23	4018	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	324:406fd2029f23	4019	* be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4020	*
mbed_official	324:406fd2029f23	4021	* Values:
mbed_official	324:406fd2029f23	4022	* - 0 - Fault input filter is disabled.
mbed_official	324:406fd2029f23	4023	* - 1 - Fault input filter is enabled.
mbed_official	324:406fd2029f23	4024	*/
mbed_official	324:406fd2029f23	4025	/@{/
mbed_official	324:406fd2029f23	4026	#define BP_FTM_FLTCTRL_FFLTR1EN (5U) /!< Bit position for FTM_FLTCTRL_FFLTR1EN. /
mbed_official	324:406fd2029f23	4027	#define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /!< Bit mask for FTM_FLTCTRL_FFLTR1EN. /
mbed_official	324:406fd2029f23	4028	#define BS_FTM_FLTCTRL_FFLTR1EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. /
mbed_official	324:406fd2029f23	4029
mbed_official	324:406fd2029f23	4030	/! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. /
mbed_official	324:406fd2029f23	4031	#define BR_FTM_FLTCTRL_FFLTR1EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN))
mbed_official	324:406fd2029f23	4032
mbed_official	324:406fd2029f23	4033	/! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. /
mbed_official	324:406fd2029f23	4034	#define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
mbed_official	324:406fd2029f23	4035
mbed_official	324:406fd2029f23	4036	/! @brief Set the FFLTR1EN field to a new value. /
mbed_official	324:406fd2029f23	4037	#define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN) = (v))
mbed_official	324:406fd2029f23	4038	/@}/
mbed_official	324:406fd2029f23	4039
mbed_official	324:406fd2029f23	4040	/*!
mbed_official	324:406fd2029f23	4041	* @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
mbed_official	324:406fd2029f23	4042	*
mbed_official	324:406fd2029f23	4043	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	324:406fd2029f23	4044	* be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4045	*
mbed_official	324:406fd2029f23	4046	* Values:
mbed_official	324:406fd2029f23	4047	* - 0 - Fault input filter is disabled.
mbed_official	324:406fd2029f23	4048	* - 1 - Fault input filter is enabled.
mbed_official	324:406fd2029f23	4049	*/
mbed_official	324:406fd2029f23	4050	/@{/
mbed_official	324:406fd2029f23	4051	#define BP_FTM_FLTCTRL_FFLTR2EN (6U) /!< Bit position for FTM_FLTCTRL_FFLTR2EN. /
mbed_official	324:406fd2029f23	4052	#define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /!< Bit mask for FTM_FLTCTRL_FFLTR2EN. /
mbed_official	324:406fd2029f23	4053	#define BS_FTM_FLTCTRL_FFLTR2EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. /
mbed_official	324:406fd2029f23	4054
mbed_official	324:406fd2029f23	4055	/! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. /
mbed_official	324:406fd2029f23	4056	#define BR_FTM_FLTCTRL_FFLTR2EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN))
mbed_official	324:406fd2029f23	4057
mbed_official	324:406fd2029f23	4058	/! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. /
mbed_official	324:406fd2029f23	4059	#define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
mbed_official	324:406fd2029f23	4060
mbed_official	324:406fd2029f23	4061	/! @brief Set the FFLTR2EN field to a new value. /
mbed_official	324:406fd2029f23	4062	#define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN) = (v))
mbed_official	324:406fd2029f23	4063	/@}/
mbed_official	324:406fd2029f23	4064
mbed_official	324:406fd2029f23	4065	/*!
mbed_official	324:406fd2029f23	4066	* @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
mbed_official	324:406fd2029f23	4067	*
mbed_official	324:406fd2029f23	4068	* Enables the filter for the fault input. This field is write protected. It can
mbed_official	324:406fd2029f23	4069	* be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4070	*
mbed_official	324:406fd2029f23	4071	* Values:
mbed_official	324:406fd2029f23	4072	* - 0 - Fault input filter is disabled.
mbed_official	324:406fd2029f23	4073	* - 1 - Fault input filter is enabled.
mbed_official	324:406fd2029f23	4074	*/
mbed_official	324:406fd2029f23	4075	/@{/
mbed_official	324:406fd2029f23	4076	#define BP_FTM_FLTCTRL_FFLTR3EN (7U) /!< Bit position for FTM_FLTCTRL_FFLTR3EN. /
mbed_official	324:406fd2029f23	4077	#define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /!< Bit mask for FTM_FLTCTRL_FFLTR3EN. /
mbed_official	324:406fd2029f23	4078	#define BS_FTM_FLTCTRL_FFLTR3EN (1U) /!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. /
mbed_official	324:406fd2029f23	4079
mbed_official	324:406fd2029f23	4080	/! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. /
mbed_official	324:406fd2029f23	4081	#define BR_FTM_FLTCTRL_FFLTR3EN(x) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN))
mbed_official	324:406fd2029f23	4082
mbed_official	324:406fd2029f23	4083	/! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. /
mbed_official	324:406fd2029f23	4084	#define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
mbed_official	324:406fd2029f23	4085
mbed_official	324:406fd2029f23	4086	/! @brief Set the FFLTR3EN field to a new value. /
mbed_official	324:406fd2029f23	4087	#define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (BITBAND_ACCESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN) = (v))
mbed_official	324:406fd2029f23	4088	/@}/
mbed_official	324:406fd2029f23	4089
mbed_official	324:406fd2029f23	4090	/*!
mbed_official	324:406fd2029f23	4091	* @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
mbed_official	324:406fd2029f23	4092	*
mbed_official	324:406fd2029f23	4093	* Selects the filter value for the fault inputs. The fault filter is disabled
mbed_official	324:406fd2029f23	4094	* when the value is zero. Writing to this field has immediate effect and must be
mbed_official	324:406fd2029f23	4095	* done only when the fault control or all fault inputs are disabled. Failure to
mbed_official	324:406fd2029f23	4096	* do this could result in a missing fault detection.
mbed_official	324:406fd2029f23	4097	*/
mbed_official	324:406fd2029f23	4098	/@{/
mbed_official	324:406fd2029f23	4099	#define BP_FTM_FLTCTRL_FFVAL (8U) /!< Bit position for FTM_FLTCTRL_FFVAL. /
mbed_official	324:406fd2029f23	4100	#define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /!< Bit mask for FTM_FLTCTRL_FFVAL. /
mbed_official	324:406fd2029f23	4101	#define BS_FTM_FLTCTRL_FFVAL (4U) /!< Bit field size in bits for FTM_FLTCTRL_FFVAL. /
mbed_official	324:406fd2029f23	4102
mbed_official	324:406fd2029f23	4103	/! @brief Read current value of the FTM_FLTCTRL_FFVAL field. /
mbed_official	324:406fd2029f23	4104	#define BR_FTM_FLTCTRL_FFVAL(x) (HW_FTM_FLTCTRL(x).B.FFVAL)
mbed_official	324:406fd2029f23	4105
mbed_official	324:406fd2029f23	4106	/! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. /
mbed_official	324:406fd2029f23	4107	#define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
mbed_official	324:406fd2029f23	4108
mbed_official	324:406fd2029f23	4109	/! @brief Set the FFVAL field to a new value. /
mbed_official	324:406fd2029f23	4110	#define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) \| BF_FTM_FLTCTRL_FFVAL(v)))
mbed_official	324:406fd2029f23	4111	/@}/
mbed_official	324:406fd2029f23	4112
mbed_official	324:406fd2029f23	4113	/*******************************************************************************
mbed_official	324:406fd2029f23	4114	* HW_FTM_QDCTRL - Quadrature Decoder Control And Status
mbed_official	324:406fd2029f23	4115	******************************************************************************/
mbed_official	324:406fd2029f23	4116
mbed_official	324:406fd2029f23	4117	/*!
mbed_official	324:406fd2029f23	4118	* @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
mbed_official	324:406fd2029f23	4119	*
mbed_official	324:406fd2029f23	4120	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	4121	*
mbed_official	324:406fd2029f23	4122	* This register has the control and status bits for the Quadrature Decoder mode.
mbed_official	324:406fd2029f23	4123	*/
mbed_official	324:406fd2029f23	4124	typedef union _hw_ftm_qdctrl
mbed_official	324:406fd2029f23	4125	{
mbed_official	324:406fd2029f23	4126	uint32_t U;
mbed_official	324:406fd2029f23	4127	struct _hw_ftm_qdctrl_bitfields
mbed_official	324:406fd2029f23	4128	{
mbed_official	324:406fd2029f23	4129	uint32_t QUADEN : 1; /!< [0] Quadrature Decoder Mode Enable /
mbed_official	324:406fd2029f23	4130	uint32_t TOFDIR : 1; /*!< [1] Timer Overflow Direction In Quadrature
mbed_official	324:406fd2029f23	4131	* Decoder Mode */
mbed_official	324:406fd2029f23	4132	uint32_t QUADIR : 1; /*!< [2] FTM Counter Direction In Quadrature
mbed_official	324:406fd2029f23	4133	* Decoder Mode */
mbed_official	324:406fd2029f23	4134	uint32_t QUADMODE : 1; /!< [3] Quadrature Decoder Mode /
mbed_official	324:406fd2029f23	4135	uint32_t PHBPOL : 1; /!< [4] Phase B Input Polarity /
mbed_official	324:406fd2029f23	4136	uint32_t PHAPOL : 1; /!< [5] Phase A Input Polarity /
mbed_official	324:406fd2029f23	4137	uint32_t PHBFLTREN : 1; /!< [6] Phase B Input Filter Enable /
mbed_official	324:406fd2029f23	4138	uint32_t PHAFLTREN : 1; /!< [7] Phase A Input Filter Enable /
mbed_official	324:406fd2029f23	4139	uint32_t RESERVED0 : 24; /!< [31:8] /
mbed_official	324:406fd2029f23	4140	} B;
mbed_official	324:406fd2029f23	4141	} hw_ftm_qdctrl_t;
mbed_official	324:406fd2029f23	4142
mbed_official	324:406fd2029f23	4143	/*!
mbed_official	324:406fd2029f23	4144	* @name Constants and macros for entire FTM_QDCTRL register
mbed_official	324:406fd2029f23	4145	*/
mbed_official	324:406fd2029f23	4146	/@{/
mbed_official	324:406fd2029f23	4147	#define HW_FTM_QDCTRL_ADDR(x) ((x) + 0x80U)
mbed_official	324:406fd2029f23	4148
mbed_official	324:406fd2029f23	4149	#define HW_FTM_QDCTRL(x) ((__IO hw_ftm_qdctrl_t ) HW_FTM_QDCTRL_ADDR(x))
mbed_official	324:406fd2029f23	4150	#define HW_FTM_QDCTRL_RD(x) (HW_FTM_QDCTRL(x).U)
mbed_official	324:406fd2029f23	4151	#define HW_FTM_QDCTRL_WR(x, v) (HW_FTM_QDCTRL(x).U = (v))
mbed_official	324:406fd2029f23	4152	#define HW_FTM_QDCTRL_SET(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4153	#define HW_FTM_QDCTRL_CLR(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4154	#define HW_FTM_QDCTRL_TOG(x, v) (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4155	/@}/
mbed_official	324:406fd2029f23	4156
mbed_official	324:406fd2029f23	4157	/*
mbed_official	324:406fd2029f23	4158	* Constants & macros for individual FTM_QDCTRL bitfields
mbed_official	324:406fd2029f23	4159	*/
mbed_official	324:406fd2029f23	4160
mbed_official	324:406fd2029f23	4161	/*!
mbed_official	324:406fd2029f23	4162	* @name Register FTM_QDCTRL, field QUADEN[0] (RW)
mbed_official	324:406fd2029f23	4163	*
mbed_official	324:406fd2029f23	4164	* Enables the Quadrature Decoder mode. In this mode, the phase A and B input
mbed_official	324:406fd2029f23	4165	* signals control the FTM counter direction. The Quadrature Decoder mode has
mbed_official	324:406fd2029f23	4166	* precedence over the other modes. See #ModeSel1Table. This field is write protected.
mbed_official	324:406fd2029f23	4167	* It can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4168	*
mbed_official	324:406fd2029f23	4169	* Values:
mbed_official	324:406fd2029f23	4170	* - 0 - Quadrature Decoder mode is disabled.
mbed_official	324:406fd2029f23	4171	* - 1 - Quadrature Decoder mode is enabled.
mbed_official	324:406fd2029f23	4172	*/
mbed_official	324:406fd2029f23	4173	/@{/
mbed_official	324:406fd2029f23	4174	#define BP_FTM_QDCTRL_QUADEN (0U) /!< Bit position for FTM_QDCTRL_QUADEN. /
mbed_official	324:406fd2029f23	4175	#define BM_FTM_QDCTRL_QUADEN (0x00000001U) /!< Bit mask for FTM_QDCTRL_QUADEN. /
mbed_official	324:406fd2029f23	4176	#define BS_FTM_QDCTRL_QUADEN (1U) /!< Bit field size in bits for FTM_QDCTRL_QUADEN. /
mbed_official	324:406fd2029f23	4177
mbed_official	324:406fd2029f23	4178	/! @brief Read current value of the FTM_QDCTRL_QUADEN field. /
mbed_official	324:406fd2029f23	4179	#define BR_FTM_QDCTRL_QUADEN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN))
mbed_official	324:406fd2029f23	4180
mbed_official	324:406fd2029f23	4181	/! @brief Format value for bitfield FTM_QDCTRL_QUADEN. /
mbed_official	324:406fd2029f23	4182	#define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
mbed_official	324:406fd2029f23	4183
mbed_official	324:406fd2029f23	4184	/! @brief Set the QUADEN field to a new value. /
mbed_official	324:406fd2029f23	4185	#define BW_FTM_QDCTRL_QUADEN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN) = (v))
mbed_official	324:406fd2029f23	4186	/@}/
mbed_official	324:406fd2029f23	4187
mbed_official	324:406fd2029f23	4188	/*!
mbed_official	324:406fd2029f23	4189	* @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
mbed_official	324:406fd2029f23	4190	*
mbed_official	324:406fd2029f23	4191	* Indicates if the TOF bit was set on the top or the bottom of counting.
mbed_official	324:406fd2029f23	4192	*
mbed_official	324:406fd2029f23	4193	* Values:
mbed_official	324:406fd2029f23	4194	* - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
mbed_official	324:406fd2029f23	4195	* decrement and FTM counter changes from its minimum value (CNTIN register) to
mbed_official	324:406fd2029f23	4196	* its maximum value (MOD register).
mbed_official	324:406fd2029f23	4197	* - 1 - TOF bit was set on the top of counting. There was an FTM counter
mbed_official	324:406fd2029f23	4198	* increment and FTM counter changes from its maximum value (MOD register) to its
mbed_official	324:406fd2029f23	4199	* minimum value (CNTIN register).
mbed_official	324:406fd2029f23	4200	*/
mbed_official	324:406fd2029f23	4201	/@{/
mbed_official	324:406fd2029f23	4202	#define BP_FTM_QDCTRL_TOFDIR (1U) /!< Bit position for FTM_QDCTRL_TOFDIR. /
mbed_official	324:406fd2029f23	4203	#define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /!< Bit mask for FTM_QDCTRL_TOFDIR. /
mbed_official	324:406fd2029f23	4204	#define BS_FTM_QDCTRL_TOFDIR (1U) /!< Bit field size in bits for FTM_QDCTRL_TOFDIR. /
mbed_official	324:406fd2029f23	4205
mbed_official	324:406fd2029f23	4206	/! @brief Read current value of the FTM_QDCTRL_TOFDIR field. /
mbed_official	324:406fd2029f23	4207	#define BR_FTM_QDCTRL_TOFDIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR))
mbed_official	324:406fd2029f23	4208	/@}/
mbed_official	324:406fd2029f23	4209
mbed_official	324:406fd2029f23	4210	/*!
mbed_official	324:406fd2029f23	4211	* @name Register FTM_QDCTRL, field QUADIR[2] (RO)
mbed_official	324:406fd2029f23	4212	*
mbed_official	324:406fd2029f23	4213	* Indicates the counting direction.
mbed_official	324:406fd2029f23	4214	*
mbed_official	324:406fd2029f23	4215	* Values:
mbed_official	324:406fd2029f23	4216	* - 0 - Counting direction is decreasing (FTM counter decrement).
mbed_official	324:406fd2029f23	4217	* - 1 - Counting direction is increasing (FTM counter increment).
mbed_official	324:406fd2029f23	4218	*/
mbed_official	324:406fd2029f23	4219	/@{/
mbed_official	324:406fd2029f23	4220	#define BP_FTM_QDCTRL_QUADIR (2U) /!< Bit position for FTM_QDCTRL_QUADIR. /
mbed_official	324:406fd2029f23	4221	#define BM_FTM_QDCTRL_QUADIR (0x00000004U) /!< Bit mask for FTM_QDCTRL_QUADIR. /
mbed_official	324:406fd2029f23	4222	#define BS_FTM_QDCTRL_QUADIR (1U) /!< Bit field size in bits for FTM_QDCTRL_QUADIR. /
mbed_official	324:406fd2029f23	4223
mbed_official	324:406fd2029f23	4224	/! @brief Read current value of the FTM_QDCTRL_QUADIR field. /
mbed_official	324:406fd2029f23	4225	#define BR_FTM_QDCTRL_QUADIR(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR))
mbed_official	324:406fd2029f23	4226	/@}/
mbed_official	324:406fd2029f23	4227
mbed_official	324:406fd2029f23	4228	/*!
mbed_official	324:406fd2029f23	4229	* @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
mbed_official	324:406fd2029f23	4230	*
mbed_official	324:406fd2029f23	4231	* Selects the encoding mode used in the Quadrature Decoder mode.
mbed_official	324:406fd2029f23	4232	*
mbed_official	324:406fd2029f23	4233	* Values:
mbed_official	324:406fd2029f23	4234	* - 0 - Phase A and phase B encoding mode.
mbed_official	324:406fd2029f23	4235	* - 1 - Count and direction encoding mode.
mbed_official	324:406fd2029f23	4236	*/
mbed_official	324:406fd2029f23	4237	/@{/
mbed_official	324:406fd2029f23	4238	#define BP_FTM_QDCTRL_QUADMODE (3U) /!< Bit position for FTM_QDCTRL_QUADMODE. /
mbed_official	324:406fd2029f23	4239	#define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /!< Bit mask for FTM_QDCTRL_QUADMODE. /
mbed_official	324:406fd2029f23	4240	#define BS_FTM_QDCTRL_QUADMODE (1U) /!< Bit field size in bits for FTM_QDCTRL_QUADMODE. /
mbed_official	324:406fd2029f23	4241
mbed_official	324:406fd2029f23	4242	/! @brief Read current value of the FTM_QDCTRL_QUADMODE field. /
mbed_official	324:406fd2029f23	4243	#define BR_FTM_QDCTRL_QUADMODE(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE))
mbed_official	324:406fd2029f23	4244
mbed_official	324:406fd2029f23	4245	/! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. /
mbed_official	324:406fd2029f23	4246	#define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
mbed_official	324:406fd2029f23	4247
mbed_official	324:406fd2029f23	4248	/! @brief Set the QUADMODE field to a new value. /
mbed_official	324:406fd2029f23	4249	#define BW_FTM_QDCTRL_QUADMODE(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE) = (v))
mbed_official	324:406fd2029f23	4250	/@}/
mbed_official	324:406fd2029f23	4251
mbed_official	324:406fd2029f23	4252	/*!
mbed_official	324:406fd2029f23	4253	* @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
mbed_official	324:406fd2029f23	4254	*
mbed_official	324:406fd2029f23	4255	* Selects the polarity for the quadrature decoder phase B input.
mbed_official	324:406fd2029f23	4256	*
mbed_official	324:406fd2029f23	4257	* Values:
mbed_official	324:406fd2029f23	4258	* - 0 - Normal polarity. Phase B input signal is not inverted before
mbed_official	324:406fd2029f23	4259	* identifying the rising and falling edges of this signal.
mbed_official	324:406fd2029f23	4260	* - 1 - Inverted polarity. Phase B input signal is inverted before identifying
mbed_official	324:406fd2029f23	4261	* the rising and falling edges of this signal.
mbed_official	324:406fd2029f23	4262	*/
mbed_official	324:406fd2029f23	4263	/@{/
mbed_official	324:406fd2029f23	4264	#define BP_FTM_QDCTRL_PHBPOL (4U) /!< Bit position for FTM_QDCTRL_PHBPOL. /
mbed_official	324:406fd2029f23	4265	#define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /!< Bit mask for FTM_QDCTRL_PHBPOL. /
mbed_official	324:406fd2029f23	4266	#define BS_FTM_QDCTRL_PHBPOL (1U) /!< Bit field size in bits for FTM_QDCTRL_PHBPOL. /
mbed_official	324:406fd2029f23	4267
mbed_official	324:406fd2029f23	4268	/! @brief Read current value of the FTM_QDCTRL_PHBPOL field. /
mbed_official	324:406fd2029f23	4269	#define BR_FTM_QDCTRL_PHBPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL))
mbed_official	324:406fd2029f23	4270
mbed_official	324:406fd2029f23	4271	/! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. /
mbed_official	324:406fd2029f23	4272	#define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
mbed_official	324:406fd2029f23	4273
mbed_official	324:406fd2029f23	4274	/! @brief Set the PHBPOL field to a new value. /
mbed_official	324:406fd2029f23	4275	#define BW_FTM_QDCTRL_PHBPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL) = (v))
mbed_official	324:406fd2029f23	4276	/@}/
mbed_official	324:406fd2029f23	4277
mbed_official	324:406fd2029f23	4278	/*!
mbed_official	324:406fd2029f23	4279	* @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
mbed_official	324:406fd2029f23	4280	*
mbed_official	324:406fd2029f23	4281	* Selects the polarity for the quadrature decoder phase A input.
mbed_official	324:406fd2029f23	4282	*
mbed_official	324:406fd2029f23	4283	* Values:
mbed_official	324:406fd2029f23	4284	* - 0 - Normal polarity. Phase A input signal is not inverted before
mbed_official	324:406fd2029f23	4285	* identifying the rising and falling edges of this signal.
mbed_official	324:406fd2029f23	4286	* - 1 - Inverted polarity. Phase A input signal is inverted before identifying
mbed_official	324:406fd2029f23	4287	* the rising and falling edges of this signal.
mbed_official	324:406fd2029f23	4288	*/
mbed_official	324:406fd2029f23	4289	/@{/
mbed_official	324:406fd2029f23	4290	#define BP_FTM_QDCTRL_PHAPOL (5U) /!< Bit position for FTM_QDCTRL_PHAPOL. /
mbed_official	324:406fd2029f23	4291	#define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /!< Bit mask for FTM_QDCTRL_PHAPOL. /
mbed_official	324:406fd2029f23	4292	#define BS_FTM_QDCTRL_PHAPOL (1U) /!< Bit field size in bits for FTM_QDCTRL_PHAPOL. /
mbed_official	324:406fd2029f23	4293
mbed_official	324:406fd2029f23	4294	/! @brief Read current value of the FTM_QDCTRL_PHAPOL field. /
mbed_official	324:406fd2029f23	4295	#define BR_FTM_QDCTRL_PHAPOL(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL))
mbed_official	324:406fd2029f23	4296
mbed_official	324:406fd2029f23	4297	/! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. /
mbed_official	324:406fd2029f23	4298	#define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
mbed_official	324:406fd2029f23	4299
mbed_official	324:406fd2029f23	4300	/! @brief Set the PHAPOL field to a new value. /
mbed_official	324:406fd2029f23	4301	#define BW_FTM_QDCTRL_PHAPOL(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL) = (v))
mbed_official	324:406fd2029f23	4302	/@}/
mbed_official	324:406fd2029f23	4303
mbed_official	324:406fd2029f23	4304	/*!
mbed_official	324:406fd2029f23	4305	* @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
mbed_official	324:406fd2029f23	4306	*
mbed_official	324:406fd2029f23	4307	* Enables the filter for the quadrature decoder phase B input. The filter value
mbed_official	324:406fd2029f23	4308	* for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
mbed_official	324:406fd2029f23	4309	* filter is also disabled when CH1FVAL is zero.
mbed_official	324:406fd2029f23	4310	*
mbed_official	324:406fd2029f23	4311	* Values:
mbed_official	324:406fd2029f23	4312	* - 0 - Phase B input filter is disabled.
mbed_official	324:406fd2029f23	4313	* - 1 - Phase B input filter is enabled.
mbed_official	324:406fd2029f23	4314	*/
mbed_official	324:406fd2029f23	4315	/@{/
mbed_official	324:406fd2029f23	4316	#define BP_FTM_QDCTRL_PHBFLTREN (6U) /!< Bit position for FTM_QDCTRL_PHBFLTREN. /
mbed_official	324:406fd2029f23	4317	#define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /!< Bit mask for FTM_QDCTRL_PHBFLTREN. /
mbed_official	324:406fd2029f23	4318	#define BS_FTM_QDCTRL_PHBFLTREN (1U) /!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. /
mbed_official	324:406fd2029f23	4319
mbed_official	324:406fd2029f23	4320	/! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. /
mbed_official	324:406fd2029f23	4321	#define BR_FTM_QDCTRL_PHBFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN))
mbed_official	324:406fd2029f23	4322
mbed_official	324:406fd2029f23	4323	/! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. /
mbed_official	324:406fd2029f23	4324	#define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
mbed_official	324:406fd2029f23	4325
mbed_official	324:406fd2029f23	4326	/! @brief Set the PHBFLTREN field to a new value. /
mbed_official	324:406fd2029f23	4327	#define BW_FTM_QDCTRL_PHBFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN) = (v))
mbed_official	324:406fd2029f23	4328	/@}/
mbed_official	324:406fd2029f23	4329
mbed_official	324:406fd2029f23	4330	/*!
mbed_official	324:406fd2029f23	4331	* @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
mbed_official	324:406fd2029f23	4332	*
mbed_official	324:406fd2029f23	4333	* Enables the filter for the quadrature decoder phase A input. The filter value
mbed_official	324:406fd2029f23	4334	* for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
mbed_official	324:406fd2029f23	4335	* filter is also disabled when CH0FVAL is zero.
mbed_official	324:406fd2029f23	4336	*
mbed_official	324:406fd2029f23	4337	* Values:
mbed_official	324:406fd2029f23	4338	* - 0 - Phase A input filter is disabled.
mbed_official	324:406fd2029f23	4339	* - 1 - Phase A input filter is enabled.
mbed_official	324:406fd2029f23	4340	*/
mbed_official	324:406fd2029f23	4341	/@{/
mbed_official	324:406fd2029f23	4342	#define BP_FTM_QDCTRL_PHAFLTREN (7U) /!< Bit position for FTM_QDCTRL_PHAFLTREN. /
mbed_official	324:406fd2029f23	4343	#define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /!< Bit mask for FTM_QDCTRL_PHAFLTREN. /
mbed_official	324:406fd2029f23	4344	#define BS_FTM_QDCTRL_PHAFLTREN (1U) /!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. /
mbed_official	324:406fd2029f23	4345
mbed_official	324:406fd2029f23	4346	/! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. /
mbed_official	324:406fd2029f23	4347	#define BR_FTM_QDCTRL_PHAFLTREN(x) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN))
mbed_official	324:406fd2029f23	4348
mbed_official	324:406fd2029f23	4349	/! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. /
mbed_official	324:406fd2029f23	4350	#define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
mbed_official	324:406fd2029f23	4351
mbed_official	324:406fd2029f23	4352	/! @brief Set the PHAFLTREN field to a new value. /
mbed_official	324:406fd2029f23	4353	#define BW_FTM_QDCTRL_PHAFLTREN(x, v) (BITBAND_ACCESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN) = (v))
mbed_official	324:406fd2029f23	4354	/@}/
mbed_official	324:406fd2029f23	4355
mbed_official	324:406fd2029f23	4356	/*******************************************************************************
mbed_official	324:406fd2029f23	4357	* HW_FTM_CONF - Configuration
mbed_official	324:406fd2029f23	4358	******************************************************************************/
mbed_official	324:406fd2029f23	4359
mbed_official	324:406fd2029f23	4360	/*!
mbed_official	324:406fd2029f23	4361	* @brief HW_FTM_CONF - Configuration (RW)
mbed_official	324:406fd2029f23	4362	*
mbed_official	324:406fd2029f23	4363	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	4364	*
mbed_official	324:406fd2029f23	4365	* This register selects the number of times that the FTM counter overflow
mbed_official	324:406fd2029f23	4366	* should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
mbed_official	324:406fd2029f23	4367	* of an external global time base, and the global time base signal generation.
mbed_official	324:406fd2029f23	4368	*/
mbed_official	324:406fd2029f23	4369	typedef union _hw_ftm_conf
mbed_official	324:406fd2029f23	4370	{
mbed_official	324:406fd2029f23	4371	uint32_t U;
mbed_official	324:406fd2029f23	4372	struct _hw_ftm_conf_bitfields
mbed_official	324:406fd2029f23	4373	{
mbed_official	324:406fd2029f23	4374	uint32_t NUMTOF : 5; /!< [4:0] TOF Frequency /
mbed_official	324:406fd2029f23	4375	uint32_t RESERVED0 : 1; /!< [5] /
mbed_official	324:406fd2029f23	4376	uint32_t BDMMODE : 2; /!< [7:6] BDM Mode /
mbed_official	324:406fd2029f23	4377	uint32_t RESERVED1 : 1; /!< [8] /
mbed_official	324:406fd2029f23	4378	uint32_t GTBEEN : 1; /!< [9] Global Time Base Enable /
mbed_official	324:406fd2029f23	4379	uint32_t GTBEOUT : 1; /!< [10] Global Time Base Output /
mbed_official	324:406fd2029f23	4380	uint32_t RESERVED2 : 21; /!< [31:11] /
mbed_official	324:406fd2029f23	4381	} B;
mbed_official	324:406fd2029f23	4382	} hw_ftm_conf_t;
mbed_official	324:406fd2029f23	4383
mbed_official	324:406fd2029f23	4384	/*!
mbed_official	324:406fd2029f23	4385	* @name Constants and macros for entire FTM_CONF register
mbed_official	324:406fd2029f23	4386	*/
mbed_official	324:406fd2029f23	4387	/@{/
mbed_official	324:406fd2029f23	4388	#define HW_FTM_CONF_ADDR(x) ((x) + 0x84U)
mbed_official	324:406fd2029f23	4389
mbed_official	324:406fd2029f23	4390	#define HW_FTM_CONF(x) ((__IO hw_ftm_conf_t ) HW_FTM_CONF_ADDR(x))
mbed_official	324:406fd2029f23	4391	#define HW_FTM_CONF_RD(x) (HW_FTM_CONF(x).U)
mbed_official	324:406fd2029f23	4392	#define HW_FTM_CONF_WR(x, v) (HW_FTM_CONF(x).U = (v))
mbed_official	324:406fd2029f23	4393	#define HW_FTM_CONF_SET(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4394	#define HW_FTM_CONF_CLR(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4395	#define HW_FTM_CONF_TOG(x, v) (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4396	/@}/
mbed_official	324:406fd2029f23	4397
mbed_official	324:406fd2029f23	4398	/*
mbed_official	324:406fd2029f23	4399	* Constants & macros for individual FTM_CONF bitfields
mbed_official	324:406fd2029f23	4400	*/
mbed_official	324:406fd2029f23	4401
mbed_official	324:406fd2029f23	4402	/*!
mbed_official	324:406fd2029f23	4403	* @name Register FTM_CONF, field NUMTOF[4:0] (RW)
mbed_official	324:406fd2029f23	4404	*
mbed_official	324:406fd2029f23	4405	* Selects the ratio between the number of counter overflows to the number of
mbed_official	324:406fd2029f23	4406	* times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
mbed_official	324:406fd2029f23	4407	* overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
mbed_official	324:406fd2029f23	4408	* the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
mbed_official	324:406fd2029f23	4409	* overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
mbed_official	324:406fd2029f23	4410	* first counter overflow but not for the next 3 overflows. This pattern continues
mbed_official	324:406fd2029f23	4411	* up to a maximum of 31.
mbed_official	324:406fd2029f23	4412	*/
mbed_official	324:406fd2029f23	4413	/@{/
mbed_official	324:406fd2029f23	4414	#define BP_FTM_CONF_NUMTOF (0U) /!< Bit position for FTM_CONF_NUMTOF. /
mbed_official	324:406fd2029f23	4415	#define BM_FTM_CONF_NUMTOF (0x0000001FU) /!< Bit mask for FTM_CONF_NUMTOF. /
mbed_official	324:406fd2029f23	4416	#define BS_FTM_CONF_NUMTOF (5U) /!< Bit field size in bits for FTM_CONF_NUMTOF. /
mbed_official	324:406fd2029f23	4417
mbed_official	324:406fd2029f23	4418	/! @brief Read current value of the FTM_CONF_NUMTOF field. /
mbed_official	324:406fd2029f23	4419	#define BR_FTM_CONF_NUMTOF(x) (HW_FTM_CONF(x).B.NUMTOF)
mbed_official	324:406fd2029f23	4420
mbed_official	324:406fd2029f23	4421	/! @brief Format value for bitfield FTM_CONF_NUMTOF. /
mbed_official	324:406fd2029f23	4422	#define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
mbed_official	324:406fd2029f23	4423
mbed_official	324:406fd2029f23	4424	/! @brief Set the NUMTOF field to a new value. /
mbed_official	324:406fd2029f23	4425	#define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) \| BF_FTM_CONF_NUMTOF(v)))
mbed_official	324:406fd2029f23	4426	/@}/
mbed_official	324:406fd2029f23	4427
mbed_official	324:406fd2029f23	4428	/*!
mbed_official	324:406fd2029f23	4429	* @name Register FTM_CONF, field BDMMODE[7:6] (RW)
mbed_official	324:406fd2029f23	4430	*
mbed_official	324:406fd2029f23	4431	* Selects the FTM behavior in BDM mode. See BDM mode.
mbed_official	324:406fd2029f23	4432	*/
mbed_official	324:406fd2029f23	4433	/@{/
mbed_official	324:406fd2029f23	4434	#define BP_FTM_CONF_BDMMODE (6U) /!< Bit position for FTM_CONF_BDMMODE. /
mbed_official	324:406fd2029f23	4435	#define BM_FTM_CONF_BDMMODE (0x000000C0U) /!< Bit mask for FTM_CONF_BDMMODE. /
mbed_official	324:406fd2029f23	4436	#define BS_FTM_CONF_BDMMODE (2U) /!< Bit field size in bits for FTM_CONF_BDMMODE. /
mbed_official	324:406fd2029f23	4437
mbed_official	324:406fd2029f23	4438	/! @brief Read current value of the FTM_CONF_BDMMODE field. /
mbed_official	324:406fd2029f23	4439	#define BR_FTM_CONF_BDMMODE(x) (HW_FTM_CONF(x).B.BDMMODE)
mbed_official	324:406fd2029f23	4440
mbed_official	324:406fd2029f23	4441	/! @brief Format value for bitfield FTM_CONF_BDMMODE. /
mbed_official	324:406fd2029f23	4442	#define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
mbed_official	324:406fd2029f23	4443
mbed_official	324:406fd2029f23	4444	/! @brief Set the BDMMODE field to a new value. /
mbed_official	324:406fd2029f23	4445	#define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) \| BF_FTM_CONF_BDMMODE(v)))
mbed_official	324:406fd2029f23	4446	/@}/
mbed_official	324:406fd2029f23	4447
mbed_official	324:406fd2029f23	4448	/*!
mbed_official	324:406fd2029f23	4449	* @name Register FTM_CONF, field GTBEEN[9] (RW)
mbed_official	324:406fd2029f23	4450	*
mbed_official	324:406fd2029f23	4451	* Configures the FTM to use an external global time base signal that is
mbed_official	324:406fd2029f23	4452	* generated by another FTM.
mbed_official	324:406fd2029f23	4453	*
mbed_official	324:406fd2029f23	4454	* Values:
mbed_official	324:406fd2029f23	4455	* - 0 - Use of an external global time base is disabled.
mbed_official	324:406fd2029f23	4456	* - 1 - Use of an external global time base is enabled.
mbed_official	324:406fd2029f23	4457	*/
mbed_official	324:406fd2029f23	4458	/@{/
mbed_official	324:406fd2029f23	4459	#define BP_FTM_CONF_GTBEEN (9U) /!< Bit position for FTM_CONF_GTBEEN. /
mbed_official	324:406fd2029f23	4460	#define BM_FTM_CONF_GTBEEN (0x00000200U) /!< Bit mask for FTM_CONF_GTBEEN. /
mbed_official	324:406fd2029f23	4461	#define BS_FTM_CONF_GTBEEN (1U) /!< Bit field size in bits for FTM_CONF_GTBEEN. /
mbed_official	324:406fd2029f23	4462
mbed_official	324:406fd2029f23	4463	/! @brief Read current value of the FTM_CONF_GTBEEN field. /
mbed_official	324:406fd2029f23	4464	#define BR_FTM_CONF_GTBEEN(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN))
mbed_official	324:406fd2029f23	4465
mbed_official	324:406fd2029f23	4466	/! @brief Format value for bitfield FTM_CONF_GTBEEN. /
mbed_official	324:406fd2029f23	4467	#define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
mbed_official	324:406fd2029f23	4468
mbed_official	324:406fd2029f23	4469	/! @brief Set the GTBEEN field to a new value. /
mbed_official	324:406fd2029f23	4470	#define BW_FTM_CONF_GTBEEN(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN) = (v))
mbed_official	324:406fd2029f23	4471	/@}/
mbed_official	324:406fd2029f23	4472
mbed_official	324:406fd2029f23	4473	/*!
mbed_official	324:406fd2029f23	4474	* @name Register FTM_CONF, field GTBEOUT[10] (RW)
mbed_official	324:406fd2029f23	4475	*
mbed_official	324:406fd2029f23	4476	* Enables the global time base signal generation to other FTMs.
mbed_official	324:406fd2029f23	4477	*
mbed_official	324:406fd2029f23	4478	* Values:
mbed_official	324:406fd2029f23	4479	* - 0 - A global time base signal generation is disabled.
mbed_official	324:406fd2029f23	4480	* - 1 - A global time base signal generation is enabled.
mbed_official	324:406fd2029f23	4481	*/
mbed_official	324:406fd2029f23	4482	/@{/
mbed_official	324:406fd2029f23	4483	#define BP_FTM_CONF_GTBEOUT (10U) /!< Bit position for FTM_CONF_GTBEOUT. /
mbed_official	324:406fd2029f23	4484	#define BM_FTM_CONF_GTBEOUT (0x00000400U) /!< Bit mask for FTM_CONF_GTBEOUT. /
mbed_official	324:406fd2029f23	4485	#define BS_FTM_CONF_GTBEOUT (1U) /!< Bit field size in bits for FTM_CONF_GTBEOUT. /
mbed_official	324:406fd2029f23	4486
mbed_official	324:406fd2029f23	4487	/! @brief Read current value of the FTM_CONF_GTBEOUT field. /
mbed_official	324:406fd2029f23	4488	#define BR_FTM_CONF_GTBEOUT(x) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT))
mbed_official	324:406fd2029f23	4489
mbed_official	324:406fd2029f23	4490	/! @brief Format value for bitfield FTM_CONF_GTBEOUT. /
mbed_official	324:406fd2029f23	4491	#define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
mbed_official	324:406fd2029f23	4492
mbed_official	324:406fd2029f23	4493	/! @brief Set the GTBEOUT field to a new value. /
mbed_official	324:406fd2029f23	4494	#define BW_FTM_CONF_GTBEOUT(x, v) (BITBAND_ACCESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT) = (v))
mbed_official	324:406fd2029f23	4495	/@}/
mbed_official	324:406fd2029f23	4496
mbed_official	324:406fd2029f23	4497	/*******************************************************************************
mbed_official	324:406fd2029f23	4498	* HW_FTM_FLTPOL - FTM Fault Input Polarity
mbed_official	324:406fd2029f23	4499	******************************************************************************/
mbed_official	324:406fd2029f23	4500
mbed_official	324:406fd2029f23	4501	/*!
mbed_official	324:406fd2029f23	4502	* @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
mbed_official	324:406fd2029f23	4503	*
mbed_official	324:406fd2029f23	4504	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	4505	*
mbed_official	324:406fd2029f23	4506	* This register defines the fault inputs polarity.
mbed_official	324:406fd2029f23	4507	*/
mbed_official	324:406fd2029f23	4508	typedef union _hw_ftm_fltpol
mbed_official	324:406fd2029f23	4509	{
mbed_official	324:406fd2029f23	4510	uint32_t U;
mbed_official	324:406fd2029f23	4511	struct _hw_ftm_fltpol_bitfields
mbed_official	324:406fd2029f23	4512	{
mbed_official	324:406fd2029f23	4513	uint32_t FLT0POL : 1; /!< [0] Fault Input 0 Polarity /
mbed_official	324:406fd2029f23	4514	uint32_t FLT1POL : 1; /!< [1] Fault Input 1 Polarity /
mbed_official	324:406fd2029f23	4515	uint32_t FLT2POL : 1; /!< [2] Fault Input 2 Polarity /
mbed_official	324:406fd2029f23	4516	uint32_t FLT3POL : 1; /!< [3] Fault Input 3 Polarity /
mbed_official	324:406fd2029f23	4517	uint32_t RESERVED0 : 28; /!< [31:4] /
mbed_official	324:406fd2029f23	4518	} B;
mbed_official	324:406fd2029f23	4519	} hw_ftm_fltpol_t;
mbed_official	324:406fd2029f23	4520
mbed_official	324:406fd2029f23	4521	/*!
mbed_official	324:406fd2029f23	4522	* @name Constants and macros for entire FTM_FLTPOL register
mbed_official	324:406fd2029f23	4523	*/
mbed_official	324:406fd2029f23	4524	/@{/
mbed_official	324:406fd2029f23	4525	#define HW_FTM_FLTPOL_ADDR(x) ((x) + 0x88U)
mbed_official	324:406fd2029f23	4526
mbed_official	324:406fd2029f23	4527	#define HW_FTM_FLTPOL(x) ((__IO hw_ftm_fltpol_t ) HW_FTM_FLTPOL_ADDR(x))
mbed_official	324:406fd2029f23	4528	#define HW_FTM_FLTPOL_RD(x) (HW_FTM_FLTPOL(x).U)
mbed_official	324:406fd2029f23	4529	#define HW_FTM_FLTPOL_WR(x, v) (HW_FTM_FLTPOL(x).U = (v))
mbed_official	324:406fd2029f23	4530	#define HW_FTM_FLTPOL_SET(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4531	#define HW_FTM_FLTPOL_CLR(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4532	#define HW_FTM_FLTPOL_TOG(x, v) (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4533	/@}/
mbed_official	324:406fd2029f23	4534
mbed_official	324:406fd2029f23	4535	/*
mbed_official	324:406fd2029f23	4536	* Constants & macros for individual FTM_FLTPOL bitfields
mbed_official	324:406fd2029f23	4537	*/
mbed_official	324:406fd2029f23	4538
mbed_official	324:406fd2029f23	4539	/*!
mbed_official	324:406fd2029f23	4540	* @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
mbed_official	324:406fd2029f23	4541	*
mbed_official	324:406fd2029f23	4542	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	324:406fd2029f23	4543	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4544	*
mbed_official	324:406fd2029f23	4545	* Values:
mbed_official	324:406fd2029f23	4546	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	324:406fd2029f23	4547	* indicates a fault.
mbed_official	324:406fd2029f23	4548	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	324:406fd2029f23	4549	* indicates a fault.
mbed_official	324:406fd2029f23	4550	*/
mbed_official	324:406fd2029f23	4551	/@{/
mbed_official	324:406fd2029f23	4552	#define BP_FTM_FLTPOL_FLT0POL (0U) /!< Bit position for FTM_FLTPOL_FLT0POL. /
mbed_official	324:406fd2029f23	4553	#define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /!< Bit mask for FTM_FLTPOL_FLT0POL. /
mbed_official	324:406fd2029f23	4554	#define BS_FTM_FLTPOL_FLT0POL (1U) /!< Bit field size in bits for FTM_FLTPOL_FLT0POL. /
mbed_official	324:406fd2029f23	4555
mbed_official	324:406fd2029f23	4556	/! @brief Read current value of the FTM_FLTPOL_FLT0POL field. /
mbed_official	324:406fd2029f23	4557	#define BR_FTM_FLTPOL_FLT0POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL))
mbed_official	324:406fd2029f23	4558
mbed_official	324:406fd2029f23	4559	/! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. /
mbed_official	324:406fd2029f23	4560	#define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
mbed_official	324:406fd2029f23	4561
mbed_official	324:406fd2029f23	4562	/! @brief Set the FLT0POL field to a new value. /
mbed_official	324:406fd2029f23	4563	#define BW_FTM_FLTPOL_FLT0POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL) = (v))
mbed_official	324:406fd2029f23	4564	/@}/
mbed_official	324:406fd2029f23	4565
mbed_official	324:406fd2029f23	4566	/*!
mbed_official	324:406fd2029f23	4567	* @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
mbed_official	324:406fd2029f23	4568	*
mbed_official	324:406fd2029f23	4569	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	324:406fd2029f23	4570	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4571	*
mbed_official	324:406fd2029f23	4572	* Values:
mbed_official	324:406fd2029f23	4573	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	324:406fd2029f23	4574	* indicates a fault.
mbed_official	324:406fd2029f23	4575	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	324:406fd2029f23	4576	* indicates a fault.
mbed_official	324:406fd2029f23	4577	*/
mbed_official	324:406fd2029f23	4578	/@{/
mbed_official	324:406fd2029f23	4579	#define BP_FTM_FLTPOL_FLT1POL (1U) /!< Bit position for FTM_FLTPOL_FLT1POL. /
mbed_official	324:406fd2029f23	4580	#define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /!< Bit mask for FTM_FLTPOL_FLT1POL. /
mbed_official	324:406fd2029f23	4581	#define BS_FTM_FLTPOL_FLT1POL (1U) /!< Bit field size in bits for FTM_FLTPOL_FLT1POL. /
mbed_official	324:406fd2029f23	4582
mbed_official	324:406fd2029f23	4583	/! @brief Read current value of the FTM_FLTPOL_FLT1POL field. /
mbed_official	324:406fd2029f23	4584	#define BR_FTM_FLTPOL_FLT1POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL))
mbed_official	324:406fd2029f23	4585
mbed_official	324:406fd2029f23	4586	/! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. /
mbed_official	324:406fd2029f23	4587	#define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
mbed_official	324:406fd2029f23	4588
mbed_official	324:406fd2029f23	4589	/! @brief Set the FLT1POL field to a new value. /
mbed_official	324:406fd2029f23	4590	#define BW_FTM_FLTPOL_FLT1POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL) = (v))
mbed_official	324:406fd2029f23	4591	/@}/
mbed_official	324:406fd2029f23	4592
mbed_official	324:406fd2029f23	4593	/*!
mbed_official	324:406fd2029f23	4594	* @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
mbed_official	324:406fd2029f23	4595	*
mbed_official	324:406fd2029f23	4596	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	324:406fd2029f23	4597	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4598	*
mbed_official	324:406fd2029f23	4599	* Values:
mbed_official	324:406fd2029f23	4600	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	324:406fd2029f23	4601	* indicates a fault.
mbed_official	324:406fd2029f23	4602	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	324:406fd2029f23	4603	* indicates a fault.
mbed_official	324:406fd2029f23	4604	*/
mbed_official	324:406fd2029f23	4605	/@{/
mbed_official	324:406fd2029f23	4606	#define BP_FTM_FLTPOL_FLT2POL (2U) /!< Bit position for FTM_FLTPOL_FLT2POL. /
mbed_official	324:406fd2029f23	4607	#define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /!< Bit mask for FTM_FLTPOL_FLT2POL. /
mbed_official	324:406fd2029f23	4608	#define BS_FTM_FLTPOL_FLT2POL (1U) /!< Bit field size in bits for FTM_FLTPOL_FLT2POL. /
mbed_official	324:406fd2029f23	4609
mbed_official	324:406fd2029f23	4610	/! @brief Read current value of the FTM_FLTPOL_FLT2POL field. /
mbed_official	324:406fd2029f23	4611	#define BR_FTM_FLTPOL_FLT2POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL))
mbed_official	324:406fd2029f23	4612
mbed_official	324:406fd2029f23	4613	/! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. /
mbed_official	324:406fd2029f23	4614	#define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
mbed_official	324:406fd2029f23	4615
mbed_official	324:406fd2029f23	4616	/! @brief Set the FLT2POL field to a new value. /
mbed_official	324:406fd2029f23	4617	#define BW_FTM_FLTPOL_FLT2POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL) = (v))
mbed_official	324:406fd2029f23	4618	/@}/
mbed_official	324:406fd2029f23	4619
mbed_official	324:406fd2029f23	4620	/*!
mbed_official	324:406fd2029f23	4621	* @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
mbed_official	324:406fd2029f23	4622	*
mbed_official	324:406fd2029f23	4623	* Defines the polarity of the fault input. This field is write protected. It
mbed_official	324:406fd2029f23	4624	* can be written only when MODE[WPDIS] = 1.
mbed_official	324:406fd2029f23	4625	*
mbed_official	324:406fd2029f23	4626	* Values:
mbed_official	324:406fd2029f23	4627	* - 0 - The fault input polarity is active high. A 1 at the fault input
mbed_official	324:406fd2029f23	4628	* indicates a fault.
mbed_official	324:406fd2029f23	4629	* - 1 - The fault input polarity is active low. A 0 at the fault input
mbed_official	324:406fd2029f23	4630	* indicates a fault.
mbed_official	324:406fd2029f23	4631	*/
mbed_official	324:406fd2029f23	4632	/@{/
mbed_official	324:406fd2029f23	4633	#define BP_FTM_FLTPOL_FLT3POL (3U) /!< Bit position for FTM_FLTPOL_FLT3POL. /
mbed_official	324:406fd2029f23	4634	#define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /!< Bit mask for FTM_FLTPOL_FLT3POL. /
mbed_official	324:406fd2029f23	4635	#define BS_FTM_FLTPOL_FLT3POL (1U) /!< Bit field size in bits for FTM_FLTPOL_FLT3POL. /
mbed_official	324:406fd2029f23	4636
mbed_official	324:406fd2029f23	4637	/! @brief Read current value of the FTM_FLTPOL_FLT3POL field. /
mbed_official	324:406fd2029f23	4638	#define BR_FTM_FLTPOL_FLT3POL(x) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL))
mbed_official	324:406fd2029f23	4639
mbed_official	324:406fd2029f23	4640	/! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. /
mbed_official	324:406fd2029f23	4641	#define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
mbed_official	324:406fd2029f23	4642
mbed_official	324:406fd2029f23	4643	/! @brief Set the FLT3POL field to a new value. /
mbed_official	324:406fd2029f23	4644	#define BW_FTM_FLTPOL_FLT3POL(x, v) (BITBAND_ACCESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL) = (v))
mbed_official	324:406fd2029f23	4645	/@}/
mbed_official	324:406fd2029f23	4646
mbed_official	324:406fd2029f23	4647	/*******************************************************************************
mbed_official	324:406fd2029f23	4648	* HW_FTM_SYNCONF - Synchronization Configuration
mbed_official	324:406fd2029f23	4649	******************************************************************************/
mbed_official	324:406fd2029f23	4650
mbed_official	324:406fd2029f23	4651	/*!
mbed_official	324:406fd2029f23	4652	* @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
mbed_official	324:406fd2029f23	4653	*
mbed_official	324:406fd2029f23	4654	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	4655	*
mbed_official	324:406fd2029f23	4656	* This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
mbed_official	324:406fd2029f23	4657	* and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
mbed_official	324:406fd2029f23	4658	* 0, 1, 2, when the hardware trigger j is detected.
mbed_official	324:406fd2029f23	4659	*/
mbed_official	324:406fd2029f23	4660	typedef union _hw_ftm_synconf
mbed_official	324:406fd2029f23	4661	{
mbed_official	324:406fd2029f23	4662	uint32_t U;
mbed_official	324:406fd2029f23	4663	struct _hw_ftm_synconf_bitfields
mbed_official	324:406fd2029f23	4664	{
mbed_official	324:406fd2029f23	4665	uint32_t HWTRIGMODE : 1; /!< [0] Hardware Trigger Mode /
mbed_official	324:406fd2029f23	4666	uint32_t RESERVED0 : 1; /!< [1] /
mbed_official	324:406fd2029f23	4667	uint32_t CNTINC : 1; /!< [2] CNTIN Register Synchronization /
mbed_official	324:406fd2029f23	4668	uint32_t RESERVED1 : 1; /!< [3] /
mbed_official	324:406fd2029f23	4669	uint32_t INVC : 1; /!< [4] INVCTRL Register Synchronization /
mbed_official	324:406fd2029f23	4670	uint32_t SWOC : 1; /!< [5] SWOCTRL Register Synchronization /
mbed_official	324:406fd2029f23	4671	uint32_t RESERVED2 : 1; /!< [6] /
mbed_official	324:406fd2029f23	4672	uint32_t SYNCMODE : 1; /!< [7] Synchronization Mode /
mbed_official	324:406fd2029f23	4673	uint32_t SWRSTCNT : 1; /!< [8] /
mbed_official	324:406fd2029f23	4674	uint32_t SWWRBUF : 1; /!< [9] /
mbed_official	324:406fd2029f23	4675	uint32_t SWOM : 1; /!< [10] /
mbed_official	324:406fd2029f23	4676	uint32_t SWINVC : 1; /!< [11] /
mbed_official	324:406fd2029f23	4677	uint32_t SWSOC : 1; /!< [12] /
mbed_official	324:406fd2029f23	4678	uint32_t RESERVED3 : 3; /!< [15:13] /
mbed_official	324:406fd2029f23	4679	uint32_t HWRSTCNT : 1; /!< [16] /
mbed_official	324:406fd2029f23	4680	uint32_t HWWRBUF : 1; /!< [17] /
mbed_official	324:406fd2029f23	4681	uint32_t HWOM : 1; /!< [18] /
mbed_official	324:406fd2029f23	4682	uint32_t HWINVC : 1; /!< [19] /
mbed_official	324:406fd2029f23	4683	uint32_t HWSOC : 1; /!< [20] /
mbed_official	324:406fd2029f23	4684	uint32_t RESERVED4 : 11; /!< [31:21] /
mbed_official	324:406fd2029f23	4685	} B;
mbed_official	324:406fd2029f23	4686	} hw_ftm_synconf_t;
mbed_official	324:406fd2029f23	4687
mbed_official	324:406fd2029f23	4688	/*!
mbed_official	324:406fd2029f23	4689	* @name Constants and macros for entire FTM_SYNCONF register
mbed_official	324:406fd2029f23	4690	*/
mbed_official	324:406fd2029f23	4691	/@{/
mbed_official	324:406fd2029f23	4692	#define HW_FTM_SYNCONF_ADDR(x) ((x) + 0x8CU)
mbed_official	324:406fd2029f23	4693
mbed_official	324:406fd2029f23	4694	#define HW_FTM_SYNCONF(x) ((__IO hw_ftm_synconf_t ) HW_FTM_SYNCONF_ADDR(x))
mbed_official	324:406fd2029f23	4695	#define HW_FTM_SYNCONF_RD(x) (HW_FTM_SYNCONF(x).U)
mbed_official	324:406fd2029f23	4696	#define HW_FTM_SYNCONF_WR(x, v) (HW_FTM_SYNCONF(x).U = (v))
mbed_official	324:406fd2029f23	4697	#define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) \| (v)))
mbed_official	324:406fd2029f23	4698	#define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	4699	#define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	4700	/@}/
mbed_official	324:406fd2029f23	4701
mbed_official	324:406fd2029f23	4702	/*
mbed_official	324:406fd2029f23	4703	* Constants & macros for individual FTM_SYNCONF bitfields
mbed_official	324:406fd2029f23	4704	*/
mbed_official	324:406fd2029f23	4705
mbed_official	324:406fd2029f23	4706	/*!
mbed_official	324:406fd2029f23	4707	* @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
mbed_official	324:406fd2029f23	4708	*
mbed_official	324:406fd2029f23	4709	* Values:
mbed_official	324:406fd2029f23	4710	* - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
mbed_official	324:406fd2029f23	4711	* j = 0, 1,2.
mbed_official	324:406fd2029f23	4712	* - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
mbed_official	324:406fd2029f23	4713	* detected, where j = 0, 1,2.
mbed_official	324:406fd2029f23	4714	*/
mbed_official	324:406fd2029f23	4715	/@{/
mbed_official	324:406fd2029f23	4716	#define BP_FTM_SYNCONF_HWTRIGMODE (0U) /!< Bit position for FTM_SYNCONF_HWTRIGMODE. /
mbed_official	324:406fd2029f23	4717	#define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /!< Bit mask for FTM_SYNCONF_HWTRIGMODE. /
mbed_official	324:406fd2029f23	4718	#define BS_FTM_SYNCONF_HWTRIGMODE (1U) /!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. /
mbed_official	324:406fd2029f23	4719
mbed_official	324:406fd2029f23	4720	/! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. /
mbed_official	324:406fd2029f23	4721	#define BR_FTM_SYNCONF_HWTRIGMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE))
mbed_official	324:406fd2029f23	4722
mbed_official	324:406fd2029f23	4723	/! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. /
mbed_official	324:406fd2029f23	4724	#define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
mbed_official	324:406fd2029f23	4725
mbed_official	324:406fd2029f23	4726	/! @brief Set the HWTRIGMODE field to a new value. /
mbed_official	324:406fd2029f23	4727	#define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE) = (v))
mbed_official	324:406fd2029f23	4728	/@}/
mbed_official	324:406fd2029f23	4729
mbed_official	324:406fd2029f23	4730	/*!
mbed_official	324:406fd2029f23	4731	* @name Register FTM_SYNCONF, field CNTINC[2] (RW)
mbed_official	324:406fd2029f23	4732	*
mbed_official	324:406fd2029f23	4733	* Values:
mbed_official	324:406fd2029f23	4734	* - 0 - CNTIN register is updated with its buffer value at all rising edges of
mbed_official	324:406fd2029f23	4735	* system clock.
mbed_official	324:406fd2029f23	4736	* - 1 - CNTIN register is updated with its buffer value by the PWM
mbed_official	324:406fd2029f23	4737	* synchronization.
mbed_official	324:406fd2029f23	4738	*/
mbed_official	324:406fd2029f23	4739	/@{/
mbed_official	324:406fd2029f23	4740	#define BP_FTM_SYNCONF_CNTINC (2U) /!< Bit position for FTM_SYNCONF_CNTINC. /
mbed_official	324:406fd2029f23	4741	#define BM_FTM_SYNCONF_CNTINC (0x00000004U) /!< Bit mask for FTM_SYNCONF_CNTINC. /
mbed_official	324:406fd2029f23	4742	#define BS_FTM_SYNCONF_CNTINC (1U) /!< Bit field size in bits for FTM_SYNCONF_CNTINC. /
mbed_official	324:406fd2029f23	4743
mbed_official	324:406fd2029f23	4744	/! @brief Read current value of the FTM_SYNCONF_CNTINC field. /
mbed_official	324:406fd2029f23	4745	#define BR_FTM_SYNCONF_CNTINC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC))
mbed_official	324:406fd2029f23	4746
mbed_official	324:406fd2029f23	4747	/! @brief Format value for bitfield FTM_SYNCONF_CNTINC. /
mbed_official	324:406fd2029f23	4748	#define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
mbed_official	324:406fd2029f23	4749
mbed_official	324:406fd2029f23	4750	/! @brief Set the CNTINC field to a new value. /
mbed_official	324:406fd2029f23	4751	#define BW_FTM_SYNCONF_CNTINC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC) = (v))
mbed_official	324:406fd2029f23	4752	/@}/
mbed_official	324:406fd2029f23	4753
mbed_official	324:406fd2029f23	4754	/*!
mbed_official	324:406fd2029f23	4755	* @name Register FTM_SYNCONF, field INVC[4] (RW)
mbed_official	324:406fd2029f23	4756	*
mbed_official	324:406fd2029f23	4757	* Values:
mbed_official	324:406fd2029f23	4758	* - 0 - INVCTRL register is updated with its buffer value at all rising edges
mbed_official	324:406fd2029f23	4759	* of system clock.
mbed_official	324:406fd2029f23	4760	* - 1 - INVCTRL register is updated with its buffer value by the PWM
mbed_official	324:406fd2029f23	4761	* synchronization.
mbed_official	324:406fd2029f23	4762	*/
mbed_official	324:406fd2029f23	4763	/@{/
mbed_official	324:406fd2029f23	4764	#define BP_FTM_SYNCONF_INVC (4U) /!< Bit position for FTM_SYNCONF_INVC. /
mbed_official	324:406fd2029f23	4765	#define BM_FTM_SYNCONF_INVC (0x00000010U) /!< Bit mask for FTM_SYNCONF_INVC. /
mbed_official	324:406fd2029f23	4766	#define BS_FTM_SYNCONF_INVC (1U) /!< Bit field size in bits for FTM_SYNCONF_INVC. /
mbed_official	324:406fd2029f23	4767
mbed_official	324:406fd2029f23	4768	/! @brief Read current value of the FTM_SYNCONF_INVC field. /
mbed_official	324:406fd2029f23	4769	#define BR_FTM_SYNCONF_INVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC))
mbed_official	324:406fd2029f23	4770
mbed_official	324:406fd2029f23	4771	/! @brief Format value for bitfield FTM_SYNCONF_INVC. /
mbed_official	324:406fd2029f23	4772	#define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
mbed_official	324:406fd2029f23	4773
mbed_official	324:406fd2029f23	4774	/! @brief Set the INVC field to a new value. /
mbed_official	324:406fd2029f23	4775	#define BW_FTM_SYNCONF_INVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC) = (v))
mbed_official	324:406fd2029f23	4776	/@}/
mbed_official	324:406fd2029f23	4777
mbed_official	324:406fd2029f23	4778	/*!
mbed_official	324:406fd2029f23	4779	* @name Register FTM_SYNCONF, field SWOC[5] (RW)
mbed_official	324:406fd2029f23	4780	*
mbed_official	324:406fd2029f23	4781	* Values:
mbed_official	324:406fd2029f23	4782	* - 0 - SWOCTRL register is updated with its buffer value at all rising edges
mbed_official	324:406fd2029f23	4783	* of system clock.
mbed_official	324:406fd2029f23	4784	* - 1 - SWOCTRL register is updated with its buffer value by the PWM
mbed_official	324:406fd2029f23	4785	* synchronization.
mbed_official	324:406fd2029f23	4786	*/
mbed_official	324:406fd2029f23	4787	/@{/
mbed_official	324:406fd2029f23	4788	#define BP_FTM_SYNCONF_SWOC (5U) /!< Bit position for FTM_SYNCONF_SWOC. /
mbed_official	324:406fd2029f23	4789	#define BM_FTM_SYNCONF_SWOC (0x00000020U) /!< Bit mask for FTM_SYNCONF_SWOC. /
mbed_official	324:406fd2029f23	4790	#define BS_FTM_SYNCONF_SWOC (1U) /!< Bit field size in bits for FTM_SYNCONF_SWOC. /
mbed_official	324:406fd2029f23	4791
mbed_official	324:406fd2029f23	4792	/! @brief Read current value of the FTM_SYNCONF_SWOC field. /
mbed_official	324:406fd2029f23	4793	#define BR_FTM_SYNCONF_SWOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC))
mbed_official	324:406fd2029f23	4794
mbed_official	324:406fd2029f23	4795	/! @brief Format value for bitfield FTM_SYNCONF_SWOC. /
mbed_official	324:406fd2029f23	4796	#define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
mbed_official	324:406fd2029f23	4797
mbed_official	324:406fd2029f23	4798	/! @brief Set the SWOC field to a new value. /
mbed_official	324:406fd2029f23	4799	#define BW_FTM_SYNCONF_SWOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC) = (v))
mbed_official	324:406fd2029f23	4800	/@}/
mbed_official	324:406fd2029f23	4801
mbed_official	324:406fd2029f23	4802	/*!
mbed_official	324:406fd2029f23	4803	* @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
mbed_official	324:406fd2029f23	4804	*
mbed_official	324:406fd2029f23	4805	* Selects the PWM Synchronization mode.
mbed_official	324:406fd2029f23	4806	*
mbed_official	324:406fd2029f23	4807	* Values:
mbed_official	324:406fd2029f23	4808	* - 0 - Legacy PWM synchronization is selected.
mbed_official	324:406fd2029f23	4809	* - 1 - Enhanced PWM synchronization is selected.
mbed_official	324:406fd2029f23	4810	*/
mbed_official	324:406fd2029f23	4811	/@{/
mbed_official	324:406fd2029f23	4812	#define BP_FTM_SYNCONF_SYNCMODE (7U) /!< Bit position for FTM_SYNCONF_SYNCMODE. /
mbed_official	324:406fd2029f23	4813	#define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /!< Bit mask for FTM_SYNCONF_SYNCMODE. /
mbed_official	324:406fd2029f23	4814	#define BS_FTM_SYNCONF_SYNCMODE (1U) /!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. /
mbed_official	324:406fd2029f23	4815
mbed_official	324:406fd2029f23	4816	/! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. /
mbed_official	324:406fd2029f23	4817	#define BR_FTM_SYNCONF_SYNCMODE(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE))
mbed_official	324:406fd2029f23	4818
mbed_official	324:406fd2029f23	4819	/! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. /
mbed_official	324:406fd2029f23	4820	#define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
mbed_official	324:406fd2029f23	4821
mbed_official	324:406fd2029f23	4822	/! @brief Set the SYNCMODE field to a new value. /
mbed_official	324:406fd2029f23	4823	#define BW_FTM_SYNCONF_SYNCMODE(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE) = (v))
mbed_official	324:406fd2029f23	4824	/@}/
mbed_official	324:406fd2029f23	4825
mbed_official	324:406fd2029f23	4826	/*!
mbed_official	324:406fd2029f23	4827	* @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
mbed_official	324:406fd2029f23	4828	*
mbed_official	324:406fd2029f23	4829	* FTM counter synchronization is activated by the software trigger.
mbed_official	324:406fd2029f23	4830	*
mbed_official	324:406fd2029f23	4831	* Values:
mbed_official	324:406fd2029f23	4832	* - 0 - The software trigger does not activate the FTM counter synchronization.
mbed_official	324:406fd2029f23	4833	* - 1 - The software trigger activates the FTM counter synchronization.
mbed_official	324:406fd2029f23	4834	*/
mbed_official	324:406fd2029f23	4835	/@{/
mbed_official	324:406fd2029f23	4836	#define BP_FTM_SYNCONF_SWRSTCNT (8U) /!< Bit position for FTM_SYNCONF_SWRSTCNT. /
mbed_official	324:406fd2029f23	4837	#define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /!< Bit mask for FTM_SYNCONF_SWRSTCNT. /
mbed_official	324:406fd2029f23	4838	#define BS_FTM_SYNCONF_SWRSTCNT (1U) /!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. /
mbed_official	324:406fd2029f23	4839
mbed_official	324:406fd2029f23	4840	/! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. /
mbed_official	324:406fd2029f23	4841	#define BR_FTM_SYNCONF_SWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT))
mbed_official	324:406fd2029f23	4842
mbed_official	324:406fd2029f23	4843	/! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. /
mbed_official	324:406fd2029f23	4844	#define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
mbed_official	324:406fd2029f23	4845
mbed_official	324:406fd2029f23	4846	/! @brief Set the SWRSTCNT field to a new value. /
mbed_official	324:406fd2029f23	4847	#define BW_FTM_SYNCONF_SWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT) = (v))
mbed_official	324:406fd2029f23	4848	/@}/
mbed_official	324:406fd2029f23	4849
mbed_official	324:406fd2029f23	4850	/*!
mbed_official	324:406fd2029f23	4851	* @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
mbed_official	324:406fd2029f23	4852	*
mbed_official	324:406fd2029f23	4853	* MOD, CNTIN, and CV registers synchronization is activated by the software
mbed_official	324:406fd2029f23	4854	* trigger.
mbed_official	324:406fd2029f23	4855	*
mbed_official	324:406fd2029f23	4856	* Values:
mbed_official	324:406fd2029f23	4857	* - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
mbed_official	324:406fd2029f23	4858	* synchronization.
mbed_official	324:406fd2029f23	4859	* - 1 - The software trigger activates MOD, CNTIN, and CV registers
mbed_official	324:406fd2029f23	4860	* synchronization.
mbed_official	324:406fd2029f23	4861	*/
mbed_official	324:406fd2029f23	4862	/@{/
mbed_official	324:406fd2029f23	4863	#define BP_FTM_SYNCONF_SWWRBUF (9U) /!< Bit position for FTM_SYNCONF_SWWRBUF. /
mbed_official	324:406fd2029f23	4864	#define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /!< Bit mask for FTM_SYNCONF_SWWRBUF. /
mbed_official	324:406fd2029f23	4865	#define BS_FTM_SYNCONF_SWWRBUF (1U) /!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. /
mbed_official	324:406fd2029f23	4866
mbed_official	324:406fd2029f23	4867	/! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. /
mbed_official	324:406fd2029f23	4868	#define BR_FTM_SYNCONF_SWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF))
mbed_official	324:406fd2029f23	4869
mbed_official	324:406fd2029f23	4870	/! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. /
mbed_official	324:406fd2029f23	4871	#define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
mbed_official	324:406fd2029f23	4872
mbed_official	324:406fd2029f23	4873	/! @brief Set the SWWRBUF field to a new value. /
mbed_official	324:406fd2029f23	4874	#define BW_FTM_SYNCONF_SWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF) = (v))
mbed_official	324:406fd2029f23	4875	/@}/
mbed_official	324:406fd2029f23	4876
mbed_official	324:406fd2029f23	4877	/*!
mbed_official	324:406fd2029f23	4878	* @name Register FTM_SYNCONF, field SWOM[10] (RW)
mbed_official	324:406fd2029f23	4879	*
mbed_official	324:406fd2029f23	4880	* Output mask synchronization is activated by the software trigger.
mbed_official	324:406fd2029f23	4881	*
mbed_official	324:406fd2029f23	4882	* Values:
mbed_official	324:406fd2029f23	4883	* - 0 - The software trigger does not activate the OUTMASK register
mbed_official	324:406fd2029f23	4884	* synchronization.
mbed_official	324:406fd2029f23	4885	* - 1 - The software trigger activates the OUTMASK register synchronization.
mbed_official	324:406fd2029f23	4886	*/
mbed_official	324:406fd2029f23	4887	/@{/
mbed_official	324:406fd2029f23	4888	#define BP_FTM_SYNCONF_SWOM (10U) /!< Bit position for FTM_SYNCONF_SWOM. /
mbed_official	324:406fd2029f23	4889	#define BM_FTM_SYNCONF_SWOM (0x00000400U) /!< Bit mask for FTM_SYNCONF_SWOM. /
mbed_official	324:406fd2029f23	4890	#define BS_FTM_SYNCONF_SWOM (1U) /!< Bit field size in bits for FTM_SYNCONF_SWOM. /
mbed_official	324:406fd2029f23	4891
mbed_official	324:406fd2029f23	4892	/! @brief Read current value of the FTM_SYNCONF_SWOM field. /
mbed_official	324:406fd2029f23	4893	#define BR_FTM_SYNCONF_SWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM))
mbed_official	324:406fd2029f23	4894
mbed_official	324:406fd2029f23	4895	/! @brief Format value for bitfield FTM_SYNCONF_SWOM. /
mbed_official	324:406fd2029f23	4896	#define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
mbed_official	324:406fd2029f23	4897
mbed_official	324:406fd2029f23	4898	/! @brief Set the SWOM field to a new value. /
mbed_official	324:406fd2029f23	4899	#define BW_FTM_SYNCONF_SWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM) = (v))
mbed_official	324:406fd2029f23	4900	/@}/
mbed_official	324:406fd2029f23	4901
mbed_official	324:406fd2029f23	4902	/*!
mbed_official	324:406fd2029f23	4903	* @name Register FTM_SYNCONF, field SWINVC[11] (RW)
mbed_official	324:406fd2029f23	4904	*
mbed_official	324:406fd2029f23	4905	* Inverting control synchronization is activated by the software trigger.
mbed_official	324:406fd2029f23	4906	*
mbed_official	324:406fd2029f23	4907	* Values:
mbed_official	324:406fd2029f23	4908	* - 0 - The software trigger does not activate the INVCTRL register
mbed_official	324:406fd2029f23	4909	* synchronization.
mbed_official	324:406fd2029f23	4910	* - 1 - The software trigger activates the INVCTRL register synchronization.
mbed_official	324:406fd2029f23	4911	*/
mbed_official	324:406fd2029f23	4912	/@{/
mbed_official	324:406fd2029f23	4913	#define BP_FTM_SYNCONF_SWINVC (11U) /!< Bit position for FTM_SYNCONF_SWINVC. /
mbed_official	324:406fd2029f23	4914	#define BM_FTM_SYNCONF_SWINVC (0x00000800U) /!< Bit mask for FTM_SYNCONF_SWINVC. /
mbed_official	324:406fd2029f23	4915	#define BS_FTM_SYNCONF_SWINVC (1U) /!< Bit field size in bits for FTM_SYNCONF_SWINVC. /
mbed_official	324:406fd2029f23	4916
mbed_official	324:406fd2029f23	4917	/! @brief Read current value of the FTM_SYNCONF_SWINVC field. /
mbed_official	324:406fd2029f23	4918	#define BR_FTM_SYNCONF_SWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC))
mbed_official	324:406fd2029f23	4919
mbed_official	324:406fd2029f23	4920	/! @brief Format value for bitfield FTM_SYNCONF_SWINVC. /
mbed_official	324:406fd2029f23	4921	#define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
mbed_official	324:406fd2029f23	4922
mbed_official	324:406fd2029f23	4923	/! @brief Set the SWINVC field to a new value. /
mbed_official	324:406fd2029f23	4924	#define BW_FTM_SYNCONF_SWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC) = (v))
mbed_official	324:406fd2029f23	4925	/@}/
mbed_official	324:406fd2029f23	4926
mbed_official	324:406fd2029f23	4927	/*!
mbed_official	324:406fd2029f23	4928	* @name Register FTM_SYNCONF, field SWSOC[12] (RW)
mbed_official	324:406fd2029f23	4929	*
mbed_official	324:406fd2029f23	4930	* Software output control synchronization is activated by the software trigger.
mbed_official	324:406fd2029f23	4931	*
mbed_official	324:406fd2029f23	4932	* Values:
mbed_official	324:406fd2029f23	4933	* - 0 - The software trigger does not activate the SWOCTRL register
mbed_official	324:406fd2029f23	4934	* synchronization.
mbed_official	324:406fd2029f23	4935	* - 1 - The software trigger activates the SWOCTRL register synchronization.
mbed_official	324:406fd2029f23	4936	*/
mbed_official	324:406fd2029f23	4937	/@{/
mbed_official	324:406fd2029f23	4938	#define BP_FTM_SYNCONF_SWSOC (12U) /!< Bit position for FTM_SYNCONF_SWSOC. /
mbed_official	324:406fd2029f23	4939	#define BM_FTM_SYNCONF_SWSOC (0x00001000U) /!< Bit mask for FTM_SYNCONF_SWSOC. /
mbed_official	324:406fd2029f23	4940	#define BS_FTM_SYNCONF_SWSOC (1U) /!< Bit field size in bits for FTM_SYNCONF_SWSOC. /
mbed_official	324:406fd2029f23	4941
mbed_official	324:406fd2029f23	4942	/! @brief Read current value of the FTM_SYNCONF_SWSOC field. /
mbed_official	324:406fd2029f23	4943	#define BR_FTM_SYNCONF_SWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC))
mbed_official	324:406fd2029f23	4944
mbed_official	324:406fd2029f23	4945	/! @brief Format value for bitfield FTM_SYNCONF_SWSOC. /
mbed_official	324:406fd2029f23	4946	#define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
mbed_official	324:406fd2029f23	4947
mbed_official	324:406fd2029f23	4948	/! @brief Set the SWSOC field to a new value. /
mbed_official	324:406fd2029f23	4949	#define BW_FTM_SYNCONF_SWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC) = (v))
mbed_official	324:406fd2029f23	4950	/@}/
mbed_official	324:406fd2029f23	4951
mbed_official	324:406fd2029f23	4952	/*!
mbed_official	324:406fd2029f23	4953	* @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
mbed_official	324:406fd2029f23	4954	*
mbed_official	324:406fd2029f23	4955	* FTM counter synchronization is activated by a hardware trigger.
mbed_official	324:406fd2029f23	4956	*
mbed_official	324:406fd2029f23	4957	* Values:
mbed_official	324:406fd2029f23	4958	* - 0 - A hardware trigger does not activate the FTM counter synchronization.
mbed_official	324:406fd2029f23	4959	* - 1 - A hardware trigger activates the FTM counter synchronization.
mbed_official	324:406fd2029f23	4960	*/
mbed_official	324:406fd2029f23	4961	/@{/
mbed_official	324:406fd2029f23	4962	#define BP_FTM_SYNCONF_HWRSTCNT (16U) /!< Bit position for FTM_SYNCONF_HWRSTCNT. /
mbed_official	324:406fd2029f23	4963	#define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /!< Bit mask for FTM_SYNCONF_HWRSTCNT. /
mbed_official	324:406fd2029f23	4964	#define BS_FTM_SYNCONF_HWRSTCNT (1U) /!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. /
mbed_official	324:406fd2029f23	4965
mbed_official	324:406fd2029f23	4966	/! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. /
mbed_official	324:406fd2029f23	4967	#define BR_FTM_SYNCONF_HWRSTCNT(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT))
mbed_official	324:406fd2029f23	4968
mbed_official	324:406fd2029f23	4969	/! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. /
mbed_official	324:406fd2029f23	4970	#define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
mbed_official	324:406fd2029f23	4971
mbed_official	324:406fd2029f23	4972	/! @brief Set the HWRSTCNT field to a new value. /
mbed_official	324:406fd2029f23	4973	#define BW_FTM_SYNCONF_HWRSTCNT(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT) = (v))
mbed_official	324:406fd2029f23	4974	/@}/
mbed_official	324:406fd2029f23	4975
mbed_official	324:406fd2029f23	4976	/*!
mbed_official	324:406fd2029f23	4977	* @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
mbed_official	324:406fd2029f23	4978	*
mbed_official	324:406fd2029f23	4979	* MOD, CNTIN, and CV registers synchronization is activated by a hardware
mbed_official	324:406fd2029f23	4980	* trigger.
mbed_official	324:406fd2029f23	4981	*
mbed_official	324:406fd2029f23	4982	* Values:
mbed_official	324:406fd2029f23	4983	* - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
mbed_official	324:406fd2029f23	4984	* synchronization.
mbed_official	324:406fd2029f23	4985	* - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
mbed_official	324:406fd2029f23	4986	* synchronization.
mbed_official	324:406fd2029f23	4987	*/
mbed_official	324:406fd2029f23	4988	/@{/
mbed_official	324:406fd2029f23	4989	#define BP_FTM_SYNCONF_HWWRBUF (17U) /!< Bit position for FTM_SYNCONF_HWWRBUF. /
mbed_official	324:406fd2029f23	4990	#define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /!< Bit mask for FTM_SYNCONF_HWWRBUF. /
mbed_official	324:406fd2029f23	4991	#define BS_FTM_SYNCONF_HWWRBUF (1U) /!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. /
mbed_official	324:406fd2029f23	4992
mbed_official	324:406fd2029f23	4993	/! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. /
mbed_official	324:406fd2029f23	4994	#define BR_FTM_SYNCONF_HWWRBUF(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF))
mbed_official	324:406fd2029f23	4995
mbed_official	324:406fd2029f23	4996	/! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. /
mbed_official	324:406fd2029f23	4997	#define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
mbed_official	324:406fd2029f23	4998
mbed_official	324:406fd2029f23	4999	/! @brief Set the HWWRBUF field to a new value. /
mbed_official	324:406fd2029f23	5000	#define BW_FTM_SYNCONF_HWWRBUF(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF) = (v))
mbed_official	324:406fd2029f23	5001	/@}/
mbed_official	324:406fd2029f23	5002
mbed_official	324:406fd2029f23	5003	/*!
mbed_official	324:406fd2029f23	5004	* @name Register FTM_SYNCONF, field HWOM[18] (RW)
mbed_official	324:406fd2029f23	5005	*
mbed_official	324:406fd2029f23	5006	* Output mask synchronization is activated by a hardware trigger.
mbed_official	324:406fd2029f23	5007	*
mbed_official	324:406fd2029f23	5008	* Values:
mbed_official	324:406fd2029f23	5009	* - 0 - A hardware trigger does not activate the OUTMASK register
mbed_official	324:406fd2029f23	5010	* synchronization.
mbed_official	324:406fd2029f23	5011	* - 1 - A hardware trigger activates the OUTMASK register synchronization.
mbed_official	324:406fd2029f23	5012	*/
mbed_official	324:406fd2029f23	5013	/@{/
mbed_official	324:406fd2029f23	5014	#define BP_FTM_SYNCONF_HWOM (18U) /!< Bit position for FTM_SYNCONF_HWOM. /
mbed_official	324:406fd2029f23	5015	#define BM_FTM_SYNCONF_HWOM (0x00040000U) /!< Bit mask for FTM_SYNCONF_HWOM. /
mbed_official	324:406fd2029f23	5016	#define BS_FTM_SYNCONF_HWOM (1U) /!< Bit field size in bits for FTM_SYNCONF_HWOM. /
mbed_official	324:406fd2029f23	5017
mbed_official	324:406fd2029f23	5018	/! @brief Read current value of the FTM_SYNCONF_HWOM field. /
mbed_official	324:406fd2029f23	5019	#define BR_FTM_SYNCONF_HWOM(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM))
mbed_official	324:406fd2029f23	5020
mbed_official	324:406fd2029f23	5021	/! @brief Format value for bitfield FTM_SYNCONF_HWOM. /
mbed_official	324:406fd2029f23	5022	#define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
mbed_official	324:406fd2029f23	5023
mbed_official	324:406fd2029f23	5024	/! @brief Set the HWOM field to a new value. /
mbed_official	324:406fd2029f23	5025	#define BW_FTM_SYNCONF_HWOM(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM) = (v))
mbed_official	324:406fd2029f23	5026	/@}/
mbed_official	324:406fd2029f23	5027
mbed_official	324:406fd2029f23	5028	/*!
mbed_official	324:406fd2029f23	5029	* @name Register FTM_SYNCONF, field HWINVC[19] (RW)
mbed_official	324:406fd2029f23	5030	*
mbed_official	324:406fd2029f23	5031	* Inverting control synchronization is activated by a hardware trigger.
mbed_official	324:406fd2029f23	5032	*
mbed_official	324:406fd2029f23	5033	* Values:
mbed_official	324:406fd2029f23	5034	* - 0 - A hardware trigger does not activate the INVCTRL register
mbed_official	324:406fd2029f23	5035	* synchronization.
mbed_official	324:406fd2029f23	5036	* - 1 - A hardware trigger activates the INVCTRL register synchronization.
mbed_official	324:406fd2029f23	5037	*/
mbed_official	324:406fd2029f23	5038	/@{/
mbed_official	324:406fd2029f23	5039	#define BP_FTM_SYNCONF_HWINVC (19U) /!< Bit position for FTM_SYNCONF_HWINVC. /
mbed_official	324:406fd2029f23	5040	#define BM_FTM_SYNCONF_HWINVC (0x00080000U) /!< Bit mask for FTM_SYNCONF_HWINVC. /
mbed_official	324:406fd2029f23	5041	#define BS_FTM_SYNCONF_HWINVC (1U) /!< Bit field size in bits for FTM_SYNCONF_HWINVC. /
mbed_official	324:406fd2029f23	5042
mbed_official	324:406fd2029f23	5043	/! @brief Read current value of the FTM_SYNCONF_HWINVC field. /
mbed_official	324:406fd2029f23	5044	#define BR_FTM_SYNCONF_HWINVC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC))
mbed_official	324:406fd2029f23	5045
mbed_official	324:406fd2029f23	5046	/! @brief Format value for bitfield FTM_SYNCONF_HWINVC. /
mbed_official	324:406fd2029f23	5047	#define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
mbed_official	324:406fd2029f23	5048
mbed_official	324:406fd2029f23	5049	/! @brief Set the HWINVC field to a new value. /
mbed_official	324:406fd2029f23	5050	#define BW_FTM_SYNCONF_HWINVC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC) = (v))
mbed_official	324:406fd2029f23	5051	/@}/
mbed_official	324:406fd2029f23	5052
mbed_official	324:406fd2029f23	5053	/*!
mbed_official	324:406fd2029f23	5054	* @name Register FTM_SYNCONF, field HWSOC[20] (RW)
mbed_official	324:406fd2029f23	5055	*
mbed_official	324:406fd2029f23	5056	* Software output control synchronization is activated by a hardware trigger.
mbed_official	324:406fd2029f23	5057	*
mbed_official	324:406fd2029f23	5058	* Values:
mbed_official	324:406fd2029f23	5059	* - 0 - A hardware trigger does not activate the SWOCTRL register
mbed_official	324:406fd2029f23	5060	* synchronization.
mbed_official	324:406fd2029f23	5061	* - 1 - A hardware trigger activates the SWOCTRL register synchronization.
mbed_official	324:406fd2029f23	5062	*/
mbed_official	324:406fd2029f23	5063	/@{/
mbed_official	324:406fd2029f23	5064	#define BP_FTM_SYNCONF_HWSOC (20U) /!< Bit position for FTM_SYNCONF_HWSOC. /
mbed_official	324:406fd2029f23	5065	#define BM_FTM_SYNCONF_HWSOC (0x00100000U) /!< Bit mask for FTM_SYNCONF_HWSOC. /
mbed_official	324:406fd2029f23	5066	#define BS_FTM_SYNCONF_HWSOC (1U) /!< Bit field size in bits for FTM_SYNCONF_HWSOC. /
mbed_official	324:406fd2029f23	5067
mbed_official	324:406fd2029f23	5068	/! @brief Read current value of the FTM_SYNCONF_HWSOC field. /
mbed_official	324:406fd2029f23	5069	#define BR_FTM_SYNCONF_HWSOC(x) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC))
mbed_official	324:406fd2029f23	5070
mbed_official	324:406fd2029f23	5071	/! @brief Format value for bitfield FTM_SYNCONF_HWSOC. /
mbed_official	324:406fd2029f23	5072	#define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
mbed_official	324:406fd2029f23	5073
mbed_official	324:406fd2029f23	5074	/! @brief Set the HWSOC field to a new value. /
mbed_official	324:406fd2029f23	5075	#define BW_FTM_SYNCONF_HWSOC(x, v) (BITBAND_ACCESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC) = (v))
mbed_official	324:406fd2029f23	5076	/@}/
mbed_official	324:406fd2029f23	5077
mbed_official	324:406fd2029f23	5078	/*******************************************************************************
mbed_official	324:406fd2029f23	5079	* HW_FTM_INVCTRL - FTM Inverting Control
mbed_official	324:406fd2029f23	5080	******************************************************************************/
mbed_official	324:406fd2029f23	5081
mbed_official	324:406fd2029f23	5082	/*!
mbed_official	324:406fd2029f23	5083	* @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
mbed_official	324:406fd2029f23	5084	*
mbed_official	324:406fd2029f23	5085	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	5086	*
mbed_official	324:406fd2029f23	5087	* This register controls when the channel (n) output becomes the channel (n+1)
mbed_official	324:406fd2029f23	5088	* output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
mbed_official	324:406fd2029f23	5089	* bit enables the inverting operation for the corresponding pair channels m. This
mbed_official	324:406fd2029f23	5090	* register has a write buffer. The INVmEN bit is updated by the INVCTRL
mbed_official	324:406fd2029f23	5091	* register synchronization.
mbed_official	324:406fd2029f23	5092	*/
mbed_official	324:406fd2029f23	5093	typedef union _hw_ftm_invctrl
mbed_official	324:406fd2029f23	5094	{
mbed_official	324:406fd2029f23	5095	uint32_t U;
mbed_official	324:406fd2029f23	5096	struct _hw_ftm_invctrl_bitfields
mbed_official	324:406fd2029f23	5097	{
mbed_official	324:406fd2029f23	5098	uint32_t INV0EN : 1; /!< [0] Pair Channels 0 Inverting Enable /
mbed_official	324:406fd2029f23	5099	uint32_t INV1EN : 1; /!< [1] Pair Channels 1 Inverting Enable /
mbed_official	324:406fd2029f23	5100	uint32_t INV2EN : 1; /!< [2] Pair Channels 2 Inverting Enable /
mbed_official	324:406fd2029f23	5101	uint32_t INV3EN : 1; /!< [3] Pair Channels 3 Inverting Enable /
mbed_official	324:406fd2029f23	5102	uint32_t RESERVED0 : 28; /!< [31:4] /
mbed_official	324:406fd2029f23	5103	} B;
mbed_official	324:406fd2029f23	5104	} hw_ftm_invctrl_t;
mbed_official	324:406fd2029f23	5105
mbed_official	324:406fd2029f23	5106	/*!
mbed_official	324:406fd2029f23	5107	* @name Constants and macros for entire FTM_INVCTRL register
mbed_official	324:406fd2029f23	5108	*/
mbed_official	324:406fd2029f23	5109	/@{/
mbed_official	324:406fd2029f23	5110	#define HW_FTM_INVCTRL_ADDR(x) ((x) + 0x90U)
mbed_official	324:406fd2029f23	5111
mbed_official	324:406fd2029f23	5112	#define HW_FTM_INVCTRL(x) ((__IO hw_ftm_invctrl_t ) HW_FTM_INVCTRL_ADDR(x))
mbed_official	324:406fd2029f23	5113	#define HW_FTM_INVCTRL_RD(x) (HW_FTM_INVCTRL(x).U)
mbed_official	324:406fd2029f23	5114	#define HW_FTM_INVCTRL_WR(x, v) (HW_FTM_INVCTRL(x).U = (v))
mbed_official	324:406fd2029f23	5115	#define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	5116	#define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	5117	#define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	5118	/@}/
mbed_official	324:406fd2029f23	5119
mbed_official	324:406fd2029f23	5120	/*
mbed_official	324:406fd2029f23	5121	* Constants & macros for individual FTM_INVCTRL bitfields
mbed_official	324:406fd2029f23	5122	*/
mbed_official	324:406fd2029f23	5123
mbed_official	324:406fd2029f23	5124	/*!
mbed_official	324:406fd2029f23	5125	* @name Register FTM_INVCTRL, field INV0EN[0] (RW)
mbed_official	324:406fd2029f23	5126	*
mbed_official	324:406fd2029f23	5127	* Values:
mbed_official	324:406fd2029f23	5128	* - 0 - Inverting is disabled.
mbed_official	324:406fd2029f23	5129	* - 1 - Inverting is enabled.
mbed_official	324:406fd2029f23	5130	*/
mbed_official	324:406fd2029f23	5131	/@{/
mbed_official	324:406fd2029f23	5132	#define BP_FTM_INVCTRL_INV0EN (0U) /!< Bit position for FTM_INVCTRL_INV0EN. /
mbed_official	324:406fd2029f23	5133	#define BM_FTM_INVCTRL_INV0EN (0x00000001U) /!< Bit mask for FTM_INVCTRL_INV0EN. /
mbed_official	324:406fd2029f23	5134	#define BS_FTM_INVCTRL_INV0EN (1U) /!< Bit field size in bits for FTM_INVCTRL_INV0EN. /
mbed_official	324:406fd2029f23	5135
mbed_official	324:406fd2029f23	5136	/! @brief Read current value of the FTM_INVCTRL_INV0EN field. /
mbed_official	324:406fd2029f23	5137	#define BR_FTM_INVCTRL_INV0EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN))
mbed_official	324:406fd2029f23	5138
mbed_official	324:406fd2029f23	5139	/! @brief Format value for bitfield FTM_INVCTRL_INV0EN. /
mbed_official	324:406fd2029f23	5140	#define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
mbed_official	324:406fd2029f23	5141
mbed_official	324:406fd2029f23	5142	/! @brief Set the INV0EN field to a new value. /
mbed_official	324:406fd2029f23	5143	#define BW_FTM_INVCTRL_INV0EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN) = (v))
mbed_official	324:406fd2029f23	5144	/@}/
mbed_official	324:406fd2029f23	5145
mbed_official	324:406fd2029f23	5146	/*!
mbed_official	324:406fd2029f23	5147	* @name Register FTM_INVCTRL, field INV1EN[1] (RW)
mbed_official	324:406fd2029f23	5148	*
mbed_official	324:406fd2029f23	5149	* Values:
mbed_official	324:406fd2029f23	5150	* - 0 - Inverting is disabled.
mbed_official	324:406fd2029f23	5151	* - 1 - Inverting is enabled.
mbed_official	324:406fd2029f23	5152	*/
mbed_official	324:406fd2029f23	5153	/@{/
mbed_official	324:406fd2029f23	5154	#define BP_FTM_INVCTRL_INV1EN (1U) /!< Bit position for FTM_INVCTRL_INV1EN. /
mbed_official	324:406fd2029f23	5155	#define BM_FTM_INVCTRL_INV1EN (0x00000002U) /!< Bit mask for FTM_INVCTRL_INV1EN. /
mbed_official	324:406fd2029f23	5156	#define BS_FTM_INVCTRL_INV1EN (1U) /!< Bit field size in bits for FTM_INVCTRL_INV1EN. /
mbed_official	324:406fd2029f23	5157
mbed_official	324:406fd2029f23	5158	/! @brief Read current value of the FTM_INVCTRL_INV1EN field. /
mbed_official	324:406fd2029f23	5159	#define BR_FTM_INVCTRL_INV1EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN))
mbed_official	324:406fd2029f23	5160
mbed_official	324:406fd2029f23	5161	/! @brief Format value for bitfield FTM_INVCTRL_INV1EN. /
mbed_official	324:406fd2029f23	5162	#define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
mbed_official	324:406fd2029f23	5163
mbed_official	324:406fd2029f23	5164	/! @brief Set the INV1EN field to a new value. /
mbed_official	324:406fd2029f23	5165	#define BW_FTM_INVCTRL_INV1EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN) = (v))
mbed_official	324:406fd2029f23	5166	/@}/
mbed_official	324:406fd2029f23	5167
mbed_official	324:406fd2029f23	5168	/*!
mbed_official	324:406fd2029f23	5169	* @name Register FTM_INVCTRL, field INV2EN[2] (RW)
mbed_official	324:406fd2029f23	5170	*
mbed_official	324:406fd2029f23	5171	* Values:
mbed_official	324:406fd2029f23	5172	* - 0 - Inverting is disabled.
mbed_official	324:406fd2029f23	5173	* - 1 - Inverting is enabled.
mbed_official	324:406fd2029f23	5174	*/
mbed_official	324:406fd2029f23	5175	/@{/
mbed_official	324:406fd2029f23	5176	#define BP_FTM_INVCTRL_INV2EN (2U) /!< Bit position for FTM_INVCTRL_INV2EN. /
mbed_official	324:406fd2029f23	5177	#define BM_FTM_INVCTRL_INV2EN (0x00000004U) /!< Bit mask for FTM_INVCTRL_INV2EN. /
mbed_official	324:406fd2029f23	5178	#define BS_FTM_INVCTRL_INV2EN (1U) /!< Bit field size in bits for FTM_INVCTRL_INV2EN. /
mbed_official	324:406fd2029f23	5179
mbed_official	324:406fd2029f23	5180	/! @brief Read current value of the FTM_INVCTRL_INV2EN field. /
mbed_official	324:406fd2029f23	5181	#define BR_FTM_INVCTRL_INV2EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN))
mbed_official	324:406fd2029f23	5182
mbed_official	324:406fd2029f23	5183	/! @brief Format value for bitfield FTM_INVCTRL_INV2EN. /
mbed_official	324:406fd2029f23	5184	#define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
mbed_official	324:406fd2029f23	5185
mbed_official	324:406fd2029f23	5186	/! @brief Set the INV2EN field to a new value. /
mbed_official	324:406fd2029f23	5187	#define BW_FTM_INVCTRL_INV2EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN) = (v))
mbed_official	324:406fd2029f23	5188	/@}/
mbed_official	324:406fd2029f23	5189
mbed_official	324:406fd2029f23	5190	/*!
mbed_official	324:406fd2029f23	5191	* @name Register FTM_INVCTRL, field INV3EN[3] (RW)
mbed_official	324:406fd2029f23	5192	*
mbed_official	324:406fd2029f23	5193	* Values:
mbed_official	324:406fd2029f23	5194	* - 0 - Inverting is disabled.
mbed_official	324:406fd2029f23	5195	* - 1 - Inverting is enabled.
mbed_official	324:406fd2029f23	5196	*/
mbed_official	324:406fd2029f23	5197	/@{/
mbed_official	324:406fd2029f23	5198	#define BP_FTM_INVCTRL_INV3EN (3U) /!< Bit position for FTM_INVCTRL_INV3EN. /
mbed_official	324:406fd2029f23	5199	#define BM_FTM_INVCTRL_INV3EN (0x00000008U) /!< Bit mask for FTM_INVCTRL_INV3EN. /
mbed_official	324:406fd2029f23	5200	#define BS_FTM_INVCTRL_INV3EN (1U) /!< Bit field size in bits for FTM_INVCTRL_INV3EN. /
mbed_official	324:406fd2029f23	5201
mbed_official	324:406fd2029f23	5202	/! @brief Read current value of the FTM_INVCTRL_INV3EN field. /
mbed_official	324:406fd2029f23	5203	#define BR_FTM_INVCTRL_INV3EN(x) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN))
mbed_official	324:406fd2029f23	5204
mbed_official	324:406fd2029f23	5205	/! @brief Format value for bitfield FTM_INVCTRL_INV3EN. /
mbed_official	324:406fd2029f23	5206	#define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
mbed_official	324:406fd2029f23	5207
mbed_official	324:406fd2029f23	5208	/! @brief Set the INV3EN field to a new value. /
mbed_official	324:406fd2029f23	5209	#define BW_FTM_INVCTRL_INV3EN(x, v) (BITBAND_ACCESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN) = (v))
mbed_official	324:406fd2029f23	5210	/@}/
mbed_official	324:406fd2029f23	5211
mbed_official	324:406fd2029f23	5212	/*******************************************************************************
mbed_official	324:406fd2029f23	5213	* HW_FTM_SWOCTRL - FTM Software Output Control
mbed_official	324:406fd2029f23	5214	******************************************************************************/
mbed_official	324:406fd2029f23	5215
mbed_official	324:406fd2029f23	5216	/*!
mbed_official	324:406fd2029f23	5217	* @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
mbed_official	324:406fd2029f23	5218	*
mbed_official	324:406fd2029f23	5219	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	5220	*
mbed_official	324:406fd2029f23	5221	* This register enables software control of channel (n) output and defines the
mbed_official	324:406fd2029f23	5222	* value forced to the channel (n) output: The CHnOC bits enable the control of
mbed_official	324:406fd2029f23	5223	* the corresponding channel (n) output by software. The CHnOCV bits select the
mbed_official	324:406fd2029f23	5224	* value that is forced at the corresponding channel (n) output. This register has
mbed_official	324:406fd2029f23	5225	* a write buffer. The fields are updated by the SWOCTRL register synchronization.
mbed_official	324:406fd2029f23	5226	*/
mbed_official	324:406fd2029f23	5227	typedef union _hw_ftm_swoctrl
mbed_official	324:406fd2029f23	5228	{
mbed_official	324:406fd2029f23	5229	uint32_t U;
mbed_official	324:406fd2029f23	5230	struct _hw_ftm_swoctrl_bitfields
mbed_official	324:406fd2029f23	5231	{
mbed_official	324:406fd2029f23	5232	uint32_t CH0OC : 1; /*!< [0] Channel 0 Software Output Control Enable
mbed_official	324:406fd2029f23	5233	* */
mbed_official	324:406fd2029f23	5234	uint32_t CH1OC : 1; /*!< [1] Channel 1 Software Output Control Enable
mbed_official	324:406fd2029f23	5235	* */
mbed_official	324:406fd2029f23	5236	uint32_t CH2OC : 1; /*!< [2] Channel 2 Software Output Control Enable
mbed_official	324:406fd2029f23	5237	* */
mbed_official	324:406fd2029f23	5238	uint32_t CH3OC : 1; /*!< [3] Channel 3 Software Output Control Enable
mbed_official	324:406fd2029f23	5239	* */
mbed_official	324:406fd2029f23	5240	uint32_t CH4OC : 1; /*!< [4] Channel 4 Software Output Control Enable
mbed_official	324:406fd2029f23	5241	* */
mbed_official	324:406fd2029f23	5242	uint32_t CH5OC : 1; /*!< [5] Channel 5 Software Output Control Enable
mbed_official	324:406fd2029f23	5243	* */
mbed_official	324:406fd2029f23	5244	uint32_t CH6OC : 1; /*!< [6] Channel 6 Software Output Control Enable
mbed_official	324:406fd2029f23	5245	* */
mbed_official	324:406fd2029f23	5246	uint32_t CH7OC : 1; /*!< [7] Channel 7 Software Output Control Enable
mbed_official	324:406fd2029f23	5247	* */
mbed_official	324:406fd2029f23	5248	uint32_t CH0OCV : 1; /*!< [8] Channel 0 Software Output Control Value
mbed_official	324:406fd2029f23	5249	* */
mbed_official	324:406fd2029f23	5250	uint32_t CH1OCV : 1; /*!< [9] Channel 1 Software Output Control Value
mbed_official	324:406fd2029f23	5251	* */
mbed_official	324:406fd2029f23	5252	uint32_t CH2OCV : 1; /*!< [10] Channel 2 Software Output Control
mbed_official	324:406fd2029f23	5253	* Value */
mbed_official	324:406fd2029f23	5254	uint32_t CH3OCV : 1; /*!< [11] Channel 3 Software Output Control
mbed_official	324:406fd2029f23	5255	* Value */
mbed_official	324:406fd2029f23	5256	uint32_t CH4OCV : 1; /*!< [12] Channel 4 Software Output Control
mbed_official	324:406fd2029f23	5257	* Value */
mbed_official	324:406fd2029f23	5258	uint32_t CH5OCV : 1; /*!< [13] Channel 5 Software Output Control
mbed_official	324:406fd2029f23	5259	* Value */
mbed_official	324:406fd2029f23	5260	uint32_t CH6OCV : 1; /*!< [14] Channel 6 Software Output Control
mbed_official	324:406fd2029f23	5261	* Value */
mbed_official	324:406fd2029f23	5262	uint32_t CH7OCV : 1; /*!< [15] Channel 7 Software Output Control
mbed_official	324:406fd2029f23	5263	* Value */
mbed_official	324:406fd2029f23	5264	uint32_t RESERVED0 : 16; /!< [31:16] /
mbed_official	324:406fd2029f23	5265	} B;
mbed_official	324:406fd2029f23	5266	} hw_ftm_swoctrl_t;
mbed_official	324:406fd2029f23	5267
mbed_official	324:406fd2029f23	5268	/*!
mbed_official	324:406fd2029f23	5269	* @name Constants and macros for entire FTM_SWOCTRL register
mbed_official	324:406fd2029f23	5270	*/
mbed_official	324:406fd2029f23	5271	/@{/
mbed_official	324:406fd2029f23	5272	#define HW_FTM_SWOCTRL_ADDR(x) ((x) + 0x94U)
mbed_official	324:406fd2029f23	5273
mbed_official	324:406fd2029f23	5274	#define HW_FTM_SWOCTRL(x) ((__IO hw_ftm_swoctrl_t ) HW_FTM_SWOCTRL_ADDR(x))
mbed_official	324:406fd2029f23	5275	#define HW_FTM_SWOCTRL_RD(x) (HW_FTM_SWOCTRL(x).U)
mbed_official	324:406fd2029f23	5276	#define HW_FTM_SWOCTRL_WR(x, v) (HW_FTM_SWOCTRL(x).U = (v))
mbed_official	324:406fd2029f23	5277	#define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) \| (v)))
mbed_official	324:406fd2029f23	5278	#define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	5279	#define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	5280	/@}/
mbed_official	324:406fd2029f23	5281
mbed_official	324:406fd2029f23	5282	/*
mbed_official	324:406fd2029f23	5283	* Constants & macros for individual FTM_SWOCTRL bitfields
mbed_official	324:406fd2029f23	5284	*/
mbed_official	324:406fd2029f23	5285
mbed_official	324:406fd2029f23	5286	/*!
mbed_official	324:406fd2029f23	5287	* @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
mbed_official	324:406fd2029f23	5288	*
mbed_official	324:406fd2029f23	5289	* Values:
mbed_official	324:406fd2029f23	5290	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5291	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5292	*/
mbed_official	324:406fd2029f23	5293	/@{/
mbed_official	324:406fd2029f23	5294	#define BP_FTM_SWOCTRL_CH0OC (0U) /!< Bit position for FTM_SWOCTRL_CH0OC. /
mbed_official	324:406fd2029f23	5295	#define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /!< Bit mask for FTM_SWOCTRL_CH0OC. /
mbed_official	324:406fd2029f23	5296	#define BS_FTM_SWOCTRL_CH0OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH0OC. /
mbed_official	324:406fd2029f23	5297
mbed_official	324:406fd2029f23	5298	/! @brief Read current value of the FTM_SWOCTRL_CH0OC field. /
mbed_official	324:406fd2029f23	5299	#define BR_FTM_SWOCTRL_CH0OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC))
mbed_official	324:406fd2029f23	5300
mbed_official	324:406fd2029f23	5301	/! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. /
mbed_official	324:406fd2029f23	5302	#define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
mbed_official	324:406fd2029f23	5303
mbed_official	324:406fd2029f23	5304	/! @brief Set the CH0OC field to a new value. /
mbed_official	324:406fd2029f23	5305	#define BW_FTM_SWOCTRL_CH0OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC) = (v))
mbed_official	324:406fd2029f23	5306	/@}/
mbed_official	324:406fd2029f23	5307
mbed_official	324:406fd2029f23	5308	/*!
mbed_official	324:406fd2029f23	5309	* @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
mbed_official	324:406fd2029f23	5310	*
mbed_official	324:406fd2029f23	5311	* Values:
mbed_official	324:406fd2029f23	5312	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5313	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5314	*/
mbed_official	324:406fd2029f23	5315	/@{/
mbed_official	324:406fd2029f23	5316	#define BP_FTM_SWOCTRL_CH1OC (1U) /!< Bit position for FTM_SWOCTRL_CH1OC. /
mbed_official	324:406fd2029f23	5317	#define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /!< Bit mask for FTM_SWOCTRL_CH1OC. /
mbed_official	324:406fd2029f23	5318	#define BS_FTM_SWOCTRL_CH1OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH1OC. /
mbed_official	324:406fd2029f23	5319
mbed_official	324:406fd2029f23	5320	/! @brief Read current value of the FTM_SWOCTRL_CH1OC field. /
mbed_official	324:406fd2029f23	5321	#define BR_FTM_SWOCTRL_CH1OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC))
mbed_official	324:406fd2029f23	5322
mbed_official	324:406fd2029f23	5323	/! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. /
mbed_official	324:406fd2029f23	5324	#define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
mbed_official	324:406fd2029f23	5325
mbed_official	324:406fd2029f23	5326	/! @brief Set the CH1OC field to a new value. /
mbed_official	324:406fd2029f23	5327	#define BW_FTM_SWOCTRL_CH1OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC) = (v))
mbed_official	324:406fd2029f23	5328	/@}/
mbed_official	324:406fd2029f23	5329
mbed_official	324:406fd2029f23	5330	/*!
mbed_official	324:406fd2029f23	5331	* @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
mbed_official	324:406fd2029f23	5332	*
mbed_official	324:406fd2029f23	5333	* Values:
mbed_official	324:406fd2029f23	5334	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5335	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5336	*/
mbed_official	324:406fd2029f23	5337	/@{/
mbed_official	324:406fd2029f23	5338	#define BP_FTM_SWOCTRL_CH2OC (2U) /!< Bit position for FTM_SWOCTRL_CH2OC. /
mbed_official	324:406fd2029f23	5339	#define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /!< Bit mask for FTM_SWOCTRL_CH2OC. /
mbed_official	324:406fd2029f23	5340	#define BS_FTM_SWOCTRL_CH2OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH2OC. /
mbed_official	324:406fd2029f23	5341
mbed_official	324:406fd2029f23	5342	/! @brief Read current value of the FTM_SWOCTRL_CH2OC field. /
mbed_official	324:406fd2029f23	5343	#define BR_FTM_SWOCTRL_CH2OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC))
mbed_official	324:406fd2029f23	5344
mbed_official	324:406fd2029f23	5345	/! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. /
mbed_official	324:406fd2029f23	5346	#define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
mbed_official	324:406fd2029f23	5347
mbed_official	324:406fd2029f23	5348	/! @brief Set the CH2OC field to a new value. /
mbed_official	324:406fd2029f23	5349	#define BW_FTM_SWOCTRL_CH2OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC) = (v))
mbed_official	324:406fd2029f23	5350	/@}/
mbed_official	324:406fd2029f23	5351
mbed_official	324:406fd2029f23	5352	/*!
mbed_official	324:406fd2029f23	5353	* @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
mbed_official	324:406fd2029f23	5354	*
mbed_official	324:406fd2029f23	5355	* Values:
mbed_official	324:406fd2029f23	5356	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5357	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5358	*/
mbed_official	324:406fd2029f23	5359	/@{/
mbed_official	324:406fd2029f23	5360	#define BP_FTM_SWOCTRL_CH3OC (3U) /!< Bit position for FTM_SWOCTRL_CH3OC. /
mbed_official	324:406fd2029f23	5361	#define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /!< Bit mask for FTM_SWOCTRL_CH3OC. /
mbed_official	324:406fd2029f23	5362	#define BS_FTM_SWOCTRL_CH3OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH3OC. /
mbed_official	324:406fd2029f23	5363
mbed_official	324:406fd2029f23	5364	/! @brief Read current value of the FTM_SWOCTRL_CH3OC field. /
mbed_official	324:406fd2029f23	5365	#define BR_FTM_SWOCTRL_CH3OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC))
mbed_official	324:406fd2029f23	5366
mbed_official	324:406fd2029f23	5367	/! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. /
mbed_official	324:406fd2029f23	5368	#define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
mbed_official	324:406fd2029f23	5369
mbed_official	324:406fd2029f23	5370	/! @brief Set the CH3OC field to a new value. /
mbed_official	324:406fd2029f23	5371	#define BW_FTM_SWOCTRL_CH3OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC) = (v))
mbed_official	324:406fd2029f23	5372	/@}/
mbed_official	324:406fd2029f23	5373
mbed_official	324:406fd2029f23	5374	/*!
mbed_official	324:406fd2029f23	5375	* @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
mbed_official	324:406fd2029f23	5376	*
mbed_official	324:406fd2029f23	5377	* Values:
mbed_official	324:406fd2029f23	5378	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5379	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5380	*/
mbed_official	324:406fd2029f23	5381	/@{/
mbed_official	324:406fd2029f23	5382	#define BP_FTM_SWOCTRL_CH4OC (4U) /!< Bit position for FTM_SWOCTRL_CH4OC. /
mbed_official	324:406fd2029f23	5383	#define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /!< Bit mask for FTM_SWOCTRL_CH4OC. /
mbed_official	324:406fd2029f23	5384	#define BS_FTM_SWOCTRL_CH4OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH4OC. /
mbed_official	324:406fd2029f23	5385
mbed_official	324:406fd2029f23	5386	/! @brief Read current value of the FTM_SWOCTRL_CH4OC field. /
mbed_official	324:406fd2029f23	5387	#define BR_FTM_SWOCTRL_CH4OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC))
mbed_official	324:406fd2029f23	5388
mbed_official	324:406fd2029f23	5389	/! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. /
mbed_official	324:406fd2029f23	5390	#define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
mbed_official	324:406fd2029f23	5391
mbed_official	324:406fd2029f23	5392	/! @brief Set the CH4OC field to a new value. /
mbed_official	324:406fd2029f23	5393	#define BW_FTM_SWOCTRL_CH4OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC) = (v))
mbed_official	324:406fd2029f23	5394	/@}/
mbed_official	324:406fd2029f23	5395
mbed_official	324:406fd2029f23	5396	/*!
mbed_official	324:406fd2029f23	5397	* @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
mbed_official	324:406fd2029f23	5398	*
mbed_official	324:406fd2029f23	5399	* Values:
mbed_official	324:406fd2029f23	5400	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5401	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5402	*/
mbed_official	324:406fd2029f23	5403	/@{/
mbed_official	324:406fd2029f23	5404	#define BP_FTM_SWOCTRL_CH5OC (5U) /!< Bit position for FTM_SWOCTRL_CH5OC. /
mbed_official	324:406fd2029f23	5405	#define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /!< Bit mask for FTM_SWOCTRL_CH5OC. /
mbed_official	324:406fd2029f23	5406	#define BS_FTM_SWOCTRL_CH5OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH5OC. /
mbed_official	324:406fd2029f23	5407
mbed_official	324:406fd2029f23	5408	/! @brief Read current value of the FTM_SWOCTRL_CH5OC field. /
mbed_official	324:406fd2029f23	5409	#define BR_FTM_SWOCTRL_CH5OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC))
mbed_official	324:406fd2029f23	5410
mbed_official	324:406fd2029f23	5411	/! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. /
mbed_official	324:406fd2029f23	5412	#define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
mbed_official	324:406fd2029f23	5413
mbed_official	324:406fd2029f23	5414	/! @brief Set the CH5OC field to a new value. /
mbed_official	324:406fd2029f23	5415	#define BW_FTM_SWOCTRL_CH5OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC) = (v))
mbed_official	324:406fd2029f23	5416	/@}/
mbed_official	324:406fd2029f23	5417
mbed_official	324:406fd2029f23	5418	/*!
mbed_official	324:406fd2029f23	5419	* @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
mbed_official	324:406fd2029f23	5420	*
mbed_official	324:406fd2029f23	5421	* Values:
mbed_official	324:406fd2029f23	5422	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5423	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5424	*/
mbed_official	324:406fd2029f23	5425	/@{/
mbed_official	324:406fd2029f23	5426	#define BP_FTM_SWOCTRL_CH6OC (6U) /!< Bit position for FTM_SWOCTRL_CH6OC. /
mbed_official	324:406fd2029f23	5427	#define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /!< Bit mask for FTM_SWOCTRL_CH6OC. /
mbed_official	324:406fd2029f23	5428	#define BS_FTM_SWOCTRL_CH6OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH6OC. /
mbed_official	324:406fd2029f23	5429
mbed_official	324:406fd2029f23	5430	/! @brief Read current value of the FTM_SWOCTRL_CH6OC field. /
mbed_official	324:406fd2029f23	5431	#define BR_FTM_SWOCTRL_CH6OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC))
mbed_official	324:406fd2029f23	5432
mbed_official	324:406fd2029f23	5433	/! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. /
mbed_official	324:406fd2029f23	5434	#define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
mbed_official	324:406fd2029f23	5435
mbed_official	324:406fd2029f23	5436	/! @brief Set the CH6OC field to a new value. /
mbed_official	324:406fd2029f23	5437	#define BW_FTM_SWOCTRL_CH6OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC) = (v))
mbed_official	324:406fd2029f23	5438	/@}/
mbed_official	324:406fd2029f23	5439
mbed_official	324:406fd2029f23	5440	/*!
mbed_official	324:406fd2029f23	5441	* @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
mbed_official	324:406fd2029f23	5442	*
mbed_official	324:406fd2029f23	5443	* Values:
mbed_official	324:406fd2029f23	5444	* - 0 - The channel output is not affected by software output control.
mbed_official	324:406fd2029f23	5445	* - 1 - The channel output is affected by software output control.
mbed_official	324:406fd2029f23	5446	*/
mbed_official	324:406fd2029f23	5447	/@{/
mbed_official	324:406fd2029f23	5448	#define BP_FTM_SWOCTRL_CH7OC (7U) /!< Bit position for FTM_SWOCTRL_CH7OC. /
mbed_official	324:406fd2029f23	5449	#define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /!< Bit mask for FTM_SWOCTRL_CH7OC. /
mbed_official	324:406fd2029f23	5450	#define BS_FTM_SWOCTRL_CH7OC (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH7OC. /
mbed_official	324:406fd2029f23	5451
mbed_official	324:406fd2029f23	5452	/! @brief Read current value of the FTM_SWOCTRL_CH7OC field. /
mbed_official	324:406fd2029f23	5453	#define BR_FTM_SWOCTRL_CH7OC(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC))
mbed_official	324:406fd2029f23	5454
mbed_official	324:406fd2029f23	5455	/! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. /
mbed_official	324:406fd2029f23	5456	#define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
mbed_official	324:406fd2029f23	5457
mbed_official	324:406fd2029f23	5458	/! @brief Set the CH7OC field to a new value. /
mbed_official	324:406fd2029f23	5459	#define BW_FTM_SWOCTRL_CH7OC(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC) = (v))
mbed_official	324:406fd2029f23	5460	/@}/
mbed_official	324:406fd2029f23	5461
mbed_official	324:406fd2029f23	5462	/*!
mbed_official	324:406fd2029f23	5463	* @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
mbed_official	324:406fd2029f23	5464	*
mbed_official	324:406fd2029f23	5465	* Values:
mbed_official	324:406fd2029f23	5466	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5467	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5468	*/
mbed_official	324:406fd2029f23	5469	/@{/
mbed_official	324:406fd2029f23	5470	#define BP_FTM_SWOCTRL_CH0OCV (8U) /!< Bit position for FTM_SWOCTRL_CH0OCV. /
mbed_official	324:406fd2029f23	5471	#define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /!< Bit mask for FTM_SWOCTRL_CH0OCV. /
mbed_official	324:406fd2029f23	5472	#define BS_FTM_SWOCTRL_CH0OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. /
mbed_official	324:406fd2029f23	5473
mbed_official	324:406fd2029f23	5474	/! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. /
mbed_official	324:406fd2029f23	5475	#define BR_FTM_SWOCTRL_CH0OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV))
mbed_official	324:406fd2029f23	5476
mbed_official	324:406fd2029f23	5477	/! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. /
mbed_official	324:406fd2029f23	5478	#define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
mbed_official	324:406fd2029f23	5479
mbed_official	324:406fd2029f23	5480	/! @brief Set the CH0OCV field to a new value. /
mbed_official	324:406fd2029f23	5481	#define BW_FTM_SWOCTRL_CH0OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV) = (v))
mbed_official	324:406fd2029f23	5482	/@}/
mbed_official	324:406fd2029f23	5483
mbed_official	324:406fd2029f23	5484	/*!
mbed_official	324:406fd2029f23	5485	* @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
mbed_official	324:406fd2029f23	5486	*
mbed_official	324:406fd2029f23	5487	* Values:
mbed_official	324:406fd2029f23	5488	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5489	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5490	*/
mbed_official	324:406fd2029f23	5491	/@{/
mbed_official	324:406fd2029f23	5492	#define BP_FTM_SWOCTRL_CH1OCV (9U) /!< Bit position for FTM_SWOCTRL_CH1OCV. /
mbed_official	324:406fd2029f23	5493	#define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /!< Bit mask for FTM_SWOCTRL_CH1OCV. /
mbed_official	324:406fd2029f23	5494	#define BS_FTM_SWOCTRL_CH1OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. /
mbed_official	324:406fd2029f23	5495
mbed_official	324:406fd2029f23	5496	/! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. /
mbed_official	324:406fd2029f23	5497	#define BR_FTM_SWOCTRL_CH1OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV))
mbed_official	324:406fd2029f23	5498
mbed_official	324:406fd2029f23	5499	/! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. /
mbed_official	324:406fd2029f23	5500	#define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
mbed_official	324:406fd2029f23	5501
mbed_official	324:406fd2029f23	5502	/! @brief Set the CH1OCV field to a new value. /
mbed_official	324:406fd2029f23	5503	#define BW_FTM_SWOCTRL_CH1OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV) = (v))
mbed_official	324:406fd2029f23	5504	/@}/
mbed_official	324:406fd2029f23	5505
mbed_official	324:406fd2029f23	5506	/*!
mbed_official	324:406fd2029f23	5507	* @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
mbed_official	324:406fd2029f23	5508	*
mbed_official	324:406fd2029f23	5509	* Values:
mbed_official	324:406fd2029f23	5510	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5511	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5512	*/
mbed_official	324:406fd2029f23	5513	/@{/
mbed_official	324:406fd2029f23	5514	#define BP_FTM_SWOCTRL_CH2OCV (10U) /!< Bit position for FTM_SWOCTRL_CH2OCV. /
mbed_official	324:406fd2029f23	5515	#define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /!< Bit mask for FTM_SWOCTRL_CH2OCV. /
mbed_official	324:406fd2029f23	5516	#define BS_FTM_SWOCTRL_CH2OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. /
mbed_official	324:406fd2029f23	5517
mbed_official	324:406fd2029f23	5518	/! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. /
mbed_official	324:406fd2029f23	5519	#define BR_FTM_SWOCTRL_CH2OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV))
mbed_official	324:406fd2029f23	5520
mbed_official	324:406fd2029f23	5521	/! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. /
mbed_official	324:406fd2029f23	5522	#define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
mbed_official	324:406fd2029f23	5523
mbed_official	324:406fd2029f23	5524	/! @brief Set the CH2OCV field to a new value. /
mbed_official	324:406fd2029f23	5525	#define BW_FTM_SWOCTRL_CH2OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV) = (v))
mbed_official	324:406fd2029f23	5526	/@}/
mbed_official	324:406fd2029f23	5527
mbed_official	324:406fd2029f23	5528	/*!
mbed_official	324:406fd2029f23	5529	* @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
mbed_official	324:406fd2029f23	5530	*
mbed_official	324:406fd2029f23	5531	* Values:
mbed_official	324:406fd2029f23	5532	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5533	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5534	*/
mbed_official	324:406fd2029f23	5535	/@{/
mbed_official	324:406fd2029f23	5536	#define BP_FTM_SWOCTRL_CH3OCV (11U) /!< Bit position for FTM_SWOCTRL_CH3OCV. /
mbed_official	324:406fd2029f23	5537	#define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /!< Bit mask for FTM_SWOCTRL_CH3OCV. /
mbed_official	324:406fd2029f23	5538	#define BS_FTM_SWOCTRL_CH3OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. /
mbed_official	324:406fd2029f23	5539
mbed_official	324:406fd2029f23	5540	/! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. /
mbed_official	324:406fd2029f23	5541	#define BR_FTM_SWOCTRL_CH3OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV))
mbed_official	324:406fd2029f23	5542
mbed_official	324:406fd2029f23	5543	/! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. /
mbed_official	324:406fd2029f23	5544	#define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
mbed_official	324:406fd2029f23	5545
mbed_official	324:406fd2029f23	5546	/! @brief Set the CH3OCV field to a new value. /
mbed_official	324:406fd2029f23	5547	#define BW_FTM_SWOCTRL_CH3OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV) = (v))
mbed_official	324:406fd2029f23	5548	/@}/
mbed_official	324:406fd2029f23	5549
mbed_official	324:406fd2029f23	5550	/*!
mbed_official	324:406fd2029f23	5551	* @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
mbed_official	324:406fd2029f23	5552	*
mbed_official	324:406fd2029f23	5553	* Values:
mbed_official	324:406fd2029f23	5554	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5555	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5556	*/
mbed_official	324:406fd2029f23	5557	/@{/
mbed_official	324:406fd2029f23	5558	#define BP_FTM_SWOCTRL_CH4OCV (12U) /!< Bit position for FTM_SWOCTRL_CH4OCV. /
mbed_official	324:406fd2029f23	5559	#define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /!< Bit mask for FTM_SWOCTRL_CH4OCV. /
mbed_official	324:406fd2029f23	5560	#define BS_FTM_SWOCTRL_CH4OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. /
mbed_official	324:406fd2029f23	5561
mbed_official	324:406fd2029f23	5562	/! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. /
mbed_official	324:406fd2029f23	5563	#define BR_FTM_SWOCTRL_CH4OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV))
mbed_official	324:406fd2029f23	5564
mbed_official	324:406fd2029f23	5565	/! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. /
mbed_official	324:406fd2029f23	5566	#define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
mbed_official	324:406fd2029f23	5567
mbed_official	324:406fd2029f23	5568	/! @brief Set the CH4OCV field to a new value. /
mbed_official	324:406fd2029f23	5569	#define BW_FTM_SWOCTRL_CH4OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV) = (v))
mbed_official	324:406fd2029f23	5570	/@}/
mbed_official	324:406fd2029f23	5571
mbed_official	324:406fd2029f23	5572	/*!
mbed_official	324:406fd2029f23	5573	* @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
mbed_official	324:406fd2029f23	5574	*
mbed_official	324:406fd2029f23	5575	* Values:
mbed_official	324:406fd2029f23	5576	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5577	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5578	*/
mbed_official	324:406fd2029f23	5579	/@{/
mbed_official	324:406fd2029f23	5580	#define BP_FTM_SWOCTRL_CH5OCV (13U) /!< Bit position for FTM_SWOCTRL_CH5OCV. /
mbed_official	324:406fd2029f23	5581	#define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /!< Bit mask for FTM_SWOCTRL_CH5OCV. /
mbed_official	324:406fd2029f23	5582	#define BS_FTM_SWOCTRL_CH5OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. /
mbed_official	324:406fd2029f23	5583
mbed_official	324:406fd2029f23	5584	/! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. /
mbed_official	324:406fd2029f23	5585	#define BR_FTM_SWOCTRL_CH5OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV))
mbed_official	324:406fd2029f23	5586
mbed_official	324:406fd2029f23	5587	/! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. /
mbed_official	324:406fd2029f23	5588	#define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
mbed_official	324:406fd2029f23	5589
mbed_official	324:406fd2029f23	5590	/! @brief Set the CH5OCV field to a new value. /
mbed_official	324:406fd2029f23	5591	#define BW_FTM_SWOCTRL_CH5OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV) = (v))
mbed_official	324:406fd2029f23	5592	/@}/
mbed_official	324:406fd2029f23	5593
mbed_official	324:406fd2029f23	5594	/*!
mbed_official	324:406fd2029f23	5595	* @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
mbed_official	324:406fd2029f23	5596	*
mbed_official	324:406fd2029f23	5597	* Values:
mbed_official	324:406fd2029f23	5598	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5599	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5600	*/
mbed_official	324:406fd2029f23	5601	/@{/
mbed_official	324:406fd2029f23	5602	#define BP_FTM_SWOCTRL_CH6OCV (14U) /!< Bit position for FTM_SWOCTRL_CH6OCV. /
mbed_official	324:406fd2029f23	5603	#define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /!< Bit mask for FTM_SWOCTRL_CH6OCV. /
mbed_official	324:406fd2029f23	5604	#define BS_FTM_SWOCTRL_CH6OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. /
mbed_official	324:406fd2029f23	5605
mbed_official	324:406fd2029f23	5606	/! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. /
mbed_official	324:406fd2029f23	5607	#define BR_FTM_SWOCTRL_CH6OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV))
mbed_official	324:406fd2029f23	5608
mbed_official	324:406fd2029f23	5609	/! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. /
mbed_official	324:406fd2029f23	5610	#define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
mbed_official	324:406fd2029f23	5611
mbed_official	324:406fd2029f23	5612	/! @brief Set the CH6OCV field to a new value. /
mbed_official	324:406fd2029f23	5613	#define BW_FTM_SWOCTRL_CH6OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV) = (v))
mbed_official	324:406fd2029f23	5614	/@}/
mbed_official	324:406fd2029f23	5615
mbed_official	324:406fd2029f23	5616	/*!
mbed_official	324:406fd2029f23	5617	* @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
mbed_official	324:406fd2029f23	5618	*
mbed_official	324:406fd2029f23	5619	* Values:
mbed_official	324:406fd2029f23	5620	* - 0 - The software output control forces 0 to the channel output.
mbed_official	324:406fd2029f23	5621	* - 1 - The software output control forces 1 to the channel output.
mbed_official	324:406fd2029f23	5622	*/
mbed_official	324:406fd2029f23	5623	/@{/
mbed_official	324:406fd2029f23	5624	#define BP_FTM_SWOCTRL_CH7OCV (15U) /!< Bit position for FTM_SWOCTRL_CH7OCV. /
mbed_official	324:406fd2029f23	5625	#define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /!< Bit mask for FTM_SWOCTRL_CH7OCV. /
mbed_official	324:406fd2029f23	5626	#define BS_FTM_SWOCTRL_CH7OCV (1U) /!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. /
mbed_official	324:406fd2029f23	5627
mbed_official	324:406fd2029f23	5628	/! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. /
mbed_official	324:406fd2029f23	5629	#define BR_FTM_SWOCTRL_CH7OCV(x) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV))
mbed_official	324:406fd2029f23	5630
mbed_official	324:406fd2029f23	5631	/! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. /
mbed_official	324:406fd2029f23	5632	#define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
mbed_official	324:406fd2029f23	5633
mbed_official	324:406fd2029f23	5634	/! @brief Set the CH7OCV field to a new value. /
mbed_official	324:406fd2029f23	5635	#define BW_FTM_SWOCTRL_CH7OCV(x, v) (BITBAND_ACCESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV) = (v))
mbed_official	324:406fd2029f23	5636	/@}/
mbed_official	324:406fd2029f23	5637
mbed_official	324:406fd2029f23	5638	/*******************************************************************************
mbed_official	324:406fd2029f23	5639	* HW_FTM_PWMLOAD - FTM PWM Load
mbed_official	324:406fd2029f23	5640	******************************************************************************/
mbed_official	324:406fd2029f23	5641
mbed_official	324:406fd2029f23	5642	/*!
mbed_official	324:406fd2029f23	5643	* @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
mbed_official	324:406fd2029f23	5644	*
mbed_official	324:406fd2029f23	5645	* Reset value: 0x00000000U
mbed_official	324:406fd2029f23	5646	*
mbed_official	324:406fd2029f23	5647	* Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
mbed_official	324:406fd2029f23	5648	* values of their write buffers when the FTM counter changes from the MOD
mbed_official	324:406fd2029f23	5649	* register value to its next value or when a channel (j) match occurs. A match occurs
mbed_official	324:406fd2029f23	5650	* for the channel (j) when FTM counter = C(j)V.
mbed_official	324:406fd2029f23	5651	*/
mbed_official	324:406fd2029f23	5652	typedef union _hw_ftm_pwmload
mbed_official	324:406fd2029f23	5653	{
mbed_official	324:406fd2029f23	5654	uint32_t U;
mbed_official	324:406fd2029f23	5655	struct _hw_ftm_pwmload_bitfields
mbed_official	324:406fd2029f23	5656	{
mbed_official	324:406fd2029f23	5657	uint32_t CH0SEL : 1; /!< [0] Channel 0 Select /
mbed_official	324:406fd2029f23	5658	uint32_t CH1SEL : 1; /!< [1] Channel 1 Select /
mbed_official	324:406fd2029f23	5659	uint32_t CH2SEL : 1; /!< [2] Channel 2 Select /
mbed_official	324:406fd2029f23	5660	uint32_t CH3SEL : 1; /!< [3] Channel 3 Select /
mbed_official	324:406fd2029f23	5661	uint32_t CH4SEL : 1; /!< [4] Channel 4 Select /
mbed_official	324:406fd2029f23	5662	uint32_t CH5SEL : 1; /!< [5] Channel 5 Select /
mbed_official	324:406fd2029f23	5663	uint32_t CH6SEL : 1; /!< [6] Channel 6 Select /
mbed_official	324:406fd2029f23	5664	uint32_t CH7SEL : 1; /!< [7] Channel 7 Select /
mbed_official	324:406fd2029f23	5665	uint32_t RESERVED0 : 1; /!< [8] /
mbed_official	324:406fd2029f23	5666	uint32_t LDOK : 1; /!< [9] Load Enable /
mbed_official	324:406fd2029f23	5667	uint32_t RESERVED1 : 22; /!< [31:10] /
mbed_official	324:406fd2029f23	5668	} B;
mbed_official	324:406fd2029f23	5669	} hw_ftm_pwmload_t;
mbed_official	324:406fd2029f23	5670
mbed_official	324:406fd2029f23	5671	/*!
mbed_official	324:406fd2029f23	5672	* @name Constants and macros for entire FTM_PWMLOAD register
mbed_official	324:406fd2029f23	5673	*/
mbed_official	324:406fd2029f23	5674	/@{/
mbed_official	324:406fd2029f23	5675	#define HW_FTM_PWMLOAD_ADDR(x) ((x) + 0x98U)
mbed_official	324:406fd2029f23	5676
mbed_official	324:406fd2029f23	5677	#define HW_FTM_PWMLOAD(x) ((__IO hw_ftm_pwmload_t ) HW_FTM_PWMLOAD_ADDR(x))
mbed_official	324:406fd2029f23	5678	#define HW_FTM_PWMLOAD_RD(x) (HW_FTM_PWMLOAD(x).U)
mbed_official	324:406fd2029f23	5679	#define HW_FTM_PWMLOAD_WR(x, v) (HW_FTM_PWMLOAD(x).U = (v))
mbed_official	324:406fd2029f23	5680	#define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) \| (v)))
mbed_official	324:406fd2029f23	5681	#define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
mbed_official	324:406fd2029f23	5682	#define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^ (v)))
mbed_official	324:406fd2029f23	5683	/@}/
mbed_official	324:406fd2029f23	5684
mbed_official	324:406fd2029f23	5685	/*
mbed_official	324:406fd2029f23	5686	* Constants & macros for individual FTM_PWMLOAD bitfields
mbed_official	324:406fd2029f23	5687	*/
mbed_official	324:406fd2029f23	5688
mbed_official	324:406fd2029f23	5689	/*!
mbed_official	324:406fd2029f23	5690	* @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
mbed_official	324:406fd2029f23	5691	*
mbed_official	324:406fd2029f23	5692	* Values:
mbed_official	324:406fd2029f23	5693	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5694	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5695	*/
mbed_official	324:406fd2029f23	5696	/@{/
mbed_official	324:406fd2029f23	5697	#define BP_FTM_PWMLOAD_CH0SEL (0U) /!< Bit position for FTM_PWMLOAD_CH0SEL. /
mbed_official	324:406fd2029f23	5698	#define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /!< Bit mask for FTM_PWMLOAD_CH0SEL. /
mbed_official	324:406fd2029f23	5699	#define BS_FTM_PWMLOAD_CH0SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. /
mbed_official	324:406fd2029f23	5700
mbed_official	324:406fd2029f23	5701	/! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. /
mbed_official	324:406fd2029f23	5702	#define BR_FTM_PWMLOAD_CH0SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL))
mbed_official	324:406fd2029f23	5703
mbed_official	324:406fd2029f23	5704	/! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. /
mbed_official	324:406fd2029f23	5705	#define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
mbed_official	324:406fd2029f23	5706
mbed_official	324:406fd2029f23	5707	/! @brief Set the CH0SEL field to a new value. /
mbed_official	324:406fd2029f23	5708	#define BW_FTM_PWMLOAD_CH0SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL) = (v))
mbed_official	324:406fd2029f23	5709	/@}/
mbed_official	324:406fd2029f23	5710
mbed_official	324:406fd2029f23	5711	/*!
mbed_official	324:406fd2029f23	5712	* @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
mbed_official	324:406fd2029f23	5713	*
mbed_official	324:406fd2029f23	5714	* Values:
mbed_official	324:406fd2029f23	5715	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5716	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5717	*/
mbed_official	324:406fd2029f23	5718	/@{/
mbed_official	324:406fd2029f23	5719	#define BP_FTM_PWMLOAD_CH1SEL (1U) /!< Bit position for FTM_PWMLOAD_CH1SEL. /
mbed_official	324:406fd2029f23	5720	#define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /!< Bit mask for FTM_PWMLOAD_CH1SEL. /
mbed_official	324:406fd2029f23	5721	#define BS_FTM_PWMLOAD_CH1SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. /
mbed_official	324:406fd2029f23	5722
mbed_official	324:406fd2029f23	5723	/! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. /
mbed_official	324:406fd2029f23	5724	#define BR_FTM_PWMLOAD_CH1SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL))
mbed_official	324:406fd2029f23	5725
mbed_official	324:406fd2029f23	5726	/! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. /
mbed_official	324:406fd2029f23	5727	#define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
mbed_official	324:406fd2029f23	5728
mbed_official	324:406fd2029f23	5729	/! @brief Set the CH1SEL field to a new value. /
mbed_official	324:406fd2029f23	5730	#define BW_FTM_PWMLOAD_CH1SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL) = (v))
mbed_official	324:406fd2029f23	5731	/@}/
mbed_official	324:406fd2029f23	5732
mbed_official	324:406fd2029f23	5733	/*!
mbed_official	324:406fd2029f23	5734	* @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
mbed_official	324:406fd2029f23	5735	*
mbed_official	324:406fd2029f23	5736	* Values:
mbed_official	324:406fd2029f23	5737	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5738	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5739	*/
mbed_official	324:406fd2029f23	5740	/@{/
mbed_official	324:406fd2029f23	5741	#define BP_FTM_PWMLOAD_CH2SEL (2U) /!< Bit position for FTM_PWMLOAD_CH2SEL. /
mbed_official	324:406fd2029f23	5742	#define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /!< Bit mask for FTM_PWMLOAD_CH2SEL. /
mbed_official	324:406fd2029f23	5743	#define BS_FTM_PWMLOAD_CH2SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. /
mbed_official	324:406fd2029f23	5744
mbed_official	324:406fd2029f23	5745	/! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. /
mbed_official	324:406fd2029f23	5746	#define BR_FTM_PWMLOAD_CH2SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL))
mbed_official	324:406fd2029f23	5747
mbed_official	324:406fd2029f23	5748	/! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. /
mbed_official	324:406fd2029f23	5749	#define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
mbed_official	324:406fd2029f23	5750
mbed_official	324:406fd2029f23	5751	/! @brief Set the CH2SEL field to a new value. /
mbed_official	324:406fd2029f23	5752	#define BW_FTM_PWMLOAD_CH2SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL) = (v))
mbed_official	324:406fd2029f23	5753	/@}/
mbed_official	324:406fd2029f23	5754
mbed_official	324:406fd2029f23	5755	/*!
mbed_official	324:406fd2029f23	5756	* @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
mbed_official	324:406fd2029f23	5757	*
mbed_official	324:406fd2029f23	5758	* Values:
mbed_official	324:406fd2029f23	5759	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5760	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5761	*/
mbed_official	324:406fd2029f23	5762	/@{/
mbed_official	324:406fd2029f23	5763	#define BP_FTM_PWMLOAD_CH3SEL (3U) /!< Bit position for FTM_PWMLOAD_CH3SEL. /
mbed_official	324:406fd2029f23	5764	#define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /!< Bit mask for FTM_PWMLOAD_CH3SEL. /
mbed_official	324:406fd2029f23	5765	#define BS_FTM_PWMLOAD_CH3SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. /
mbed_official	324:406fd2029f23	5766
mbed_official	324:406fd2029f23	5767	/! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. /
mbed_official	324:406fd2029f23	5768	#define BR_FTM_PWMLOAD_CH3SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL))
mbed_official	324:406fd2029f23	5769
mbed_official	324:406fd2029f23	5770	/! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. /
mbed_official	324:406fd2029f23	5771	#define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
mbed_official	324:406fd2029f23	5772
mbed_official	324:406fd2029f23	5773	/! @brief Set the CH3SEL field to a new value. /
mbed_official	324:406fd2029f23	5774	#define BW_FTM_PWMLOAD_CH3SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL) = (v))
mbed_official	324:406fd2029f23	5775	/@}/
mbed_official	324:406fd2029f23	5776
mbed_official	324:406fd2029f23	5777	/*!
mbed_official	324:406fd2029f23	5778	* @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
mbed_official	324:406fd2029f23	5779	*
mbed_official	324:406fd2029f23	5780	* Values:
mbed_official	324:406fd2029f23	5781	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5782	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5783	*/
mbed_official	324:406fd2029f23	5784	/@{/
mbed_official	324:406fd2029f23	5785	#define BP_FTM_PWMLOAD_CH4SEL (4U) /!< Bit position for FTM_PWMLOAD_CH4SEL. /
mbed_official	324:406fd2029f23	5786	#define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /!< Bit mask for FTM_PWMLOAD_CH4SEL. /
mbed_official	324:406fd2029f23	5787	#define BS_FTM_PWMLOAD_CH4SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. /
mbed_official	324:406fd2029f23	5788
mbed_official	324:406fd2029f23	5789	/! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. /
mbed_official	324:406fd2029f23	5790	#define BR_FTM_PWMLOAD_CH4SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL))
mbed_official	324:406fd2029f23	5791
mbed_official	324:406fd2029f23	5792	/! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. /
mbed_official	324:406fd2029f23	5793	#define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
mbed_official	324:406fd2029f23	5794
mbed_official	324:406fd2029f23	5795	/! @brief Set the CH4SEL field to a new value. /
mbed_official	324:406fd2029f23	5796	#define BW_FTM_PWMLOAD_CH4SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL) = (v))
mbed_official	324:406fd2029f23	5797	/@}/
mbed_official	324:406fd2029f23	5798
mbed_official	324:406fd2029f23	5799	/*!
mbed_official	324:406fd2029f23	5800	* @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
mbed_official	324:406fd2029f23	5801	*
mbed_official	324:406fd2029f23	5802	* Values:
mbed_official	324:406fd2029f23	5803	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5804	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5805	*/
mbed_official	324:406fd2029f23	5806	/@{/
mbed_official	324:406fd2029f23	5807	#define BP_FTM_PWMLOAD_CH5SEL (5U) /!< Bit position for FTM_PWMLOAD_CH5SEL. /
mbed_official	324:406fd2029f23	5808	#define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /!< Bit mask for FTM_PWMLOAD_CH5SEL. /
mbed_official	324:406fd2029f23	5809	#define BS_FTM_PWMLOAD_CH5SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. /
mbed_official	324:406fd2029f23	5810
mbed_official	324:406fd2029f23	5811	/! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. /
mbed_official	324:406fd2029f23	5812	#define BR_FTM_PWMLOAD_CH5SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL))
mbed_official	324:406fd2029f23	5813
mbed_official	324:406fd2029f23	5814	/! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. /
mbed_official	324:406fd2029f23	5815	#define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
mbed_official	324:406fd2029f23	5816
mbed_official	324:406fd2029f23	5817	/! @brief Set the CH5SEL field to a new value. /
mbed_official	324:406fd2029f23	5818	#define BW_FTM_PWMLOAD_CH5SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL) = (v))
mbed_official	324:406fd2029f23	5819	/@}/
mbed_official	324:406fd2029f23	5820
mbed_official	324:406fd2029f23	5821	/*!
mbed_official	324:406fd2029f23	5822	* @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
mbed_official	324:406fd2029f23	5823	*
mbed_official	324:406fd2029f23	5824	* Values:
mbed_official	324:406fd2029f23	5825	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5826	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5827	*/
mbed_official	324:406fd2029f23	5828	/@{/
mbed_official	324:406fd2029f23	5829	#define BP_FTM_PWMLOAD_CH6SEL (6U) /!< Bit position for FTM_PWMLOAD_CH6SEL. /
mbed_official	324:406fd2029f23	5830	#define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /!< Bit mask for FTM_PWMLOAD_CH6SEL. /
mbed_official	324:406fd2029f23	5831	#define BS_FTM_PWMLOAD_CH6SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. /
mbed_official	324:406fd2029f23	5832
mbed_official	324:406fd2029f23	5833	/! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. /
mbed_official	324:406fd2029f23	5834	#define BR_FTM_PWMLOAD_CH6SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL))
mbed_official	324:406fd2029f23	5835
mbed_official	324:406fd2029f23	5836	/! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. /
mbed_official	324:406fd2029f23	5837	#define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
mbed_official	324:406fd2029f23	5838
mbed_official	324:406fd2029f23	5839	/! @brief Set the CH6SEL field to a new value. /
mbed_official	324:406fd2029f23	5840	#define BW_FTM_PWMLOAD_CH6SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL) = (v))
mbed_official	324:406fd2029f23	5841	/@}/
mbed_official	324:406fd2029f23	5842
mbed_official	324:406fd2029f23	5843	/*!
mbed_official	324:406fd2029f23	5844	* @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
mbed_official	324:406fd2029f23	5845	*
mbed_official	324:406fd2029f23	5846	* Values:
mbed_official	324:406fd2029f23	5847	* - 0 - Do not include the channel in the matching process.
mbed_official	324:406fd2029f23	5848	* - 1 - Include the channel in the matching process.
mbed_official	324:406fd2029f23	5849	*/
mbed_official	324:406fd2029f23	5850	/@{/
mbed_official	324:406fd2029f23	5851	#define BP_FTM_PWMLOAD_CH7SEL (7U) /!< Bit position for FTM_PWMLOAD_CH7SEL. /
mbed_official	324:406fd2029f23	5852	#define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /!< Bit mask for FTM_PWMLOAD_CH7SEL. /
mbed_official	324:406fd2029f23	5853	#define BS_FTM_PWMLOAD_CH7SEL (1U) /!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. /
mbed_official	324:406fd2029f23	5854
mbed_official	324:406fd2029f23	5855	/! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. /
mbed_official	324:406fd2029f23	5856	#define BR_FTM_PWMLOAD_CH7SEL(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL))
mbed_official	324:406fd2029f23	5857
mbed_official	324:406fd2029f23	5858	/! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. /
mbed_official	324:406fd2029f23	5859	#define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
mbed_official	324:406fd2029f23	5860
mbed_official	324:406fd2029f23	5861	/! @brief Set the CH7SEL field to a new value. /
mbed_official	324:406fd2029f23	5862	#define BW_FTM_PWMLOAD_CH7SEL(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL) = (v))
mbed_official	324:406fd2029f23	5863	/@}/
mbed_official	324:406fd2029f23	5864
mbed_official	324:406fd2029f23	5865	/*!
mbed_official	324:406fd2029f23	5866	* @name Register FTM_PWMLOAD, field LDOK[9] (RW)
mbed_official	324:406fd2029f23	5867	*
mbed_official	324:406fd2029f23	5868	* Enables the loading of the MOD, CNTIN, and CV registers with the values of
mbed_official	324:406fd2029f23	5869	* their write buffers.
mbed_official	324:406fd2029f23	5870	*
mbed_official	324:406fd2029f23	5871	* Values:
mbed_official	324:406fd2029f23	5872	* - 0 - Loading updated values is disabled.
mbed_official	324:406fd2029f23	5873	* - 1 - Loading updated values is enabled.
mbed_official	324:406fd2029f23	5874	*/
mbed_official	324:406fd2029f23	5875	/@{/
mbed_official	324:406fd2029f23	5876	#define BP_FTM_PWMLOAD_LDOK (9U) /!< Bit position for FTM_PWMLOAD_LDOK. /
mbed_official	324:406fd2029f23	5877	#define BM_FTM_PWMLOAD_LDOK (0x00000200U) /!< Bit mask for FTM_PWMLOAD_LDOK. /
mbed_official	324:406fd2029f23	5878	#define BS_FTM_PWMLOAD_LDOK (1U) /!< Bit field size in bits for FTM_PWMLOAD_LDOK. /
mbed_official	324:406fd2029f23	5879
mbed_official	324:406fd2029f23	5880	/! @brief Read current value of the FTM_PWMLOAD_LDOK field. /
mbed_official	324:406fd2029f23	5881	#define BR_FTM_PWMLOAD_LDOK(x) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK))
mbed_official	324:406fd2029f23	5882
mbed_official	324:406fd2029f23	5883	/! @brief Format value for bitfield FTM_PWMLOAD_LDOK. /
mbed_official	324:406fd2029f23	5884	#define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
mbed_official	324:406fd2029f23	5885
mbed_official	324:406fd2029f23	5886	/! @brief Set the LDOK field to a new value. /
mbed_official	324:406fd2029f23	5887	#define BW_FTM_PWMLOAD_LDOK(x, v) (BITBAND_ACCESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK) = (v))
mbed_official	324:406fd2029f23	5888	/@}/
mbed_official	324:406fd2029f23	5889
mbed_official	324:406fd2029f23	5890	/*******************************************************************************
mbed_official	324:406fd2029f23	5891	* hw_ftm_t - module struct
mbed_official	324:406fd2029f23	5892	******************************************************************************/
mbed_official	324:406fd2029f23	5893	/*!
mbed_official	324:406fd2029f23	5894	* @brief All FTM module registers.
mbed_official	324:406fd2029f23	5895	*/
mbed_official	324:406fd2029f23	5896	#pragma pack(1)
mbed_official	324:406fd2029f23	5897	typedef struct _hw_ftm
mbed_official	324:406fd2029f23	5898	{
mbed_official	324:406fd2029f23	5899	__IO hw_ftm_sc_t SC; /!< [0x0] Status And Control /
mbed_official	324:406fd2029f23	5900	__IO hw_ftm_cnt_t CNT; /!< [0x4] Counter /
mbed_official	324:406fd2029f23	5901	__IO hw_ftm_mod_t MOD; /!< [0x8] Modulo /
mbed_official	324:406fd2029f23	5902	struct {
mbed_official	324:406fd2029f23	5903	__IO hw_ftm_cnsc_t CnSC; /!< [0xC] Channel (n) Status And Control /
mbed_official	324:406fd2029f23	5904	__IO hw_ftm_cnv_t CnV; /!< [0x10] Channel (n) Value /
mbed_official	324:406fd2029f23	5905	} CONTROLS[8];
mbed_official	324:406fd2029f23	5906	__IO hw_ftm_cntin_t CNTIN; /!< [0x4C] Counter Initial Value /
mbed_official	324:406fd2029f23	5907	__IO hw_ftm_status_t STATUS; /!< [0x50] Capture And Compare Status /
mbed_official	324:406fd2029f23	5908	__IO hw_ftm_mode_t MODE; /!< [0x54] Features Mode Selection /
mbed_official	324:406fd2029f23	5909	__IO hw_ftm_sync_t SYNC; /!< [0x58] Synchronization /
mbed_official	324:406fd2029f23	5910	__IO hw_ftm_outinit_t OUTINIT; /!< [0x5C] Initial State For Channels Output /
mbed_official	324:406fd2029f23	5911	__IO hw_ftm_outmask_t OUTMASK; /!< [0x60] Output Mask /
mbed_official	324:406fd2029f23	5912	__IO hw_ftm_combine_t COMBINE; /!< [0x64] Function For Linked Channels /
mbed_official	324:406fd2029f23	5913	__IO hw_ftm_deadtime_t DEADTIME; /!< [0x68] Deadtime Insertion Control /
mbed_official	324:406fd2029f23	5914	__IO hw_ftm_exttrig_t EXTTRIG; /!< [0x6C] FTM External Trigger /
mbed_official	324:406fd2029f23	5915	__IO hw_ftm_pol_t POL; /!< [0x70] Channels Polarity /
mbed_official	324:406fd2029f23	5916	__IO hw_ftm_fms_t FMS; /!< [0x74] Fault Mode Status /
mbed_official	324:406fd2029f23	5917	__IO hw_ftm_filter_t FILTER; /!< [0x78] Input Capture Filter Control /
mbed_official	324:406fd2029f23	5918	__IO hw_ftm_fltctrl_t FLTCTRL; /!< [0x7C] Fault Control /
mbed_official	324:406fd2029f23	5919	__IO hw_ftm_qdctrl_t QDCTRL; /!< [0x80] Quadrature Decoder Control And Status /
mbed_official	324:406fd2029f23	5920	__IO hw_ftm_conf_t CONF; /!< [0x84] Configuration /
mbed_official	324:406fd2029f23	5921	__IO hw_ftm_fltpol_t FLTPOL; /!< [0x88] FTM Fault Input Polarity /
mbed_official	324:406fd2029f23	5922	__IO hw_ftm_synconf_t SYNCONF; /!< [0x8C] Synchronization Configuration /
mbed_official	324:406fd2029f23	5923	__IO hw_ftm_invctrl_t INVCTRL; /!< [0x90] FTM Inverting Control /
mbed_official	324:406fd2029f23	5924	__IO hw_ftm_swoctrl_t SWOCTRL; /!< [0x94] FTM Software Output Control /
mbed_official	324:406fd2029f23	5925	__IO hw_ftm_pwmload_t PWMLOAD; /!< [0x98] FTM PWM Load /
mbed_official	324:406fd2029f23	5926	} hw_ftm_t;
mbed_official	324:406fd2029f23	5927	#pragma pack()
mbed_official	324:406fd2029f23	5928
mbed_official	324:406fd2029f23	5929	/! @brief Macro to access all FTM registers. /
mbed_official	324:406fd2029f23	5930	/! @param x FTM module instance base address. /
mbed_official	324:406fd2029f23	5931	/*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official	324:406fd2029f23	5932	* use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
mbed_official	324:406fd2029f23	5933	#define HW_FTM(x) ((hw_ftm_t )(x))
mbed_official	324:406fd2029f23	5934
mbed_official	324:406fd2029f23	5935	#endif /* __HW_FTM_REGISTERS_H__ */
mbed_official	324:406fd2029f23	5936	/* EOF */