mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ftfa.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_FTFA_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_FTFA_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 FTFA
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Flash Memory Interface
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_FTFA_FSTAT - Flash Status Register
mbed_official 324:406fd2029f23 90 * - HW_FTFA_FCNFG - Flash Configuration Register
mbed_official 324:406fd2029f23 91 * - HW_FTFA_FSEC - Flash Security Register
mbed_official 324:406fd2029f23 92 * - HW_FTFA_FOPT - Flash Option Register
mbed_official 324:406fd2029f23 93 * - HW_FTFA_FCCOB3 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 94 * - HW_FTFA_FCCOB2 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 95 * - HW_FTFA_FCCOB1 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 96 * - HW_FTFA_FCCOB0 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 97 * - HW_FTFA_FCCOB7 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 98 * - HW_FTFA_FCCOB6 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 99 * - HW_FTFA_FCCOB5 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 100 * - HW_FTFA_FCCOB4 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 101 * - HW_FTFA_FCCOBB - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 102 * - HW_FTFA_FCCOBA - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 103 * - HW_FTFA_FCCOB9 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 104 * - HW_FTFA_FCCOB8 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 105 * - HW_FTFA_FPROT3 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 106 * - HW_FTFA_FPROT2 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 107 * - HW_FTFA_FPROT1 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 108 * - HW_FTFA_FPROT0 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 109 * - HW_FTFA_XACCH3 - Execute-only Access Registers
mbed_official 324:406fd2029f23 110 * - HW_FTFA_XACCH2 - Execute-only Access Registers
mbed_official 324:406fd2029f23 111 * - HW_FTFA_XACCH1 - Execute-only Access Registers
mbed_official 324:406fd2029f23 112 * - HW_FTFA_XACCH0 - Execute-only Access Registers
mbed_official 324:406fd2029f23 113 * - HW_FTFA_XACCL3 - Execute-only Access Registers
mbed_official 324:406fd2029f23 114 * - HW_FTFA_XACCL2 - Execute-only Access Registers
mbed_official 324:406fd2029f23 115 * - HW_FTFA_XACCL1 - Execute-only Access Registers
mbed_official 324:406fd2029f23 116 * - HW_FTFA_XACCL0 - Execute-only Access Registers
mbed_official 324:406fd2029f23 117 * - HW_FTFA_SACCH3 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 118 * - HW_FTFA_SACCH2 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 119 * - HW_FTFA_SACCH1 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 120 * - HW_FTFA_SACCH0 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 121 * - HW_FTFA_SACCL3 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 122 * - HW_FTFA_SACCL2 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 123 * - HW_FTFA_SACCL1 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 124 * - HW_FTFA_SACCL0 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 125 * - HW_FTFA_FACSS - Flash Access Segment Size Register
mbed_official 324:406fd2029f23 126 * - HW_FTFA_FACSN - Flash Access Segment Number Register
mbed_official 324:406fd2029f23 127 *
mbed_official 324:406fd2029f23 128 * - hw_ftfa_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 129 */
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 #define HW_FTFA_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFA module. */
mbed_official 324:406fd2029f23 132
mbed_official 324:406fd2029f23 133 /*******************************************************************************
mbed_official 324:406fd2029f23 134 * HW_FTFA_FSTAT - Flash Status Register
mbed_official 324:406fd2029f23 135 ******************************************************************************/
mbed_official 324:406fd2029f23 136
mbed_official 324:406fd2029f23 137 /*!
mbed_official 324:406fd2029f23 138 * @brief HW_FTFA_FSTAT - Flash Status Register (RW)
mbed_official 324:406fd2029f23 139 *
mbed_official 324:406fd2029f23 140 * Reset value: 0x00U
mbed_official 324:406fd2029f23 141 *
mbed_official 324:406fd2029f23 142 * The FSTAT register reports the operational status of the flash memory module.
mbed_official 324:406fd2029f23 143 * The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
mbed_official 324:406fd2029f23 144 * MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. When
mbed_official 324:406fd2029f23 145 * set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in
mbed_official 324:406fd2029f23 146 * this register prevent the launch of any more commands until the flag is
mbed_official 324:406fd2029f23 147 * cleared (by writing a one to it).
mbed_official 324:406fd2029f23 148 */
mbed_official 324:406fd2029f23 149 typedef union _hw_ftfa_fstat
mbed_official 324:406fd2029f23 150 {
mbed_official 324:406fd2029f23 151 uint8_t U;
mbed_official 324:406fd2029f23 152 struct _hw_ftfa_fstat_bitfields
mbed_official 324:406fd2029f23 153 {
mbed_official 324:406fd2029f23 154 uint8_t MGSTAT0 : 1; /*!< [0] Memory Controller Command Completion
mbed_official 324:406fd2029f23 155 * Status Flag */
mbed_official 324:406fd2029f23 156 uint8_t RESERVED0 : 3; /*!< [3:1] */
mbed_official 324:406fd2029f23 157 uint8_t FPVIOL : 1; /*!< [4] Flash Protection Violation Flag */
mbed_official 324:406fd2029f23 158 uint8_t ACCERR : 1; /*!< [5] Flash Access Error Flag */
mbed_official 324:406fd2029f23 159 uint8_t RDCOLERR : 1; /*!< [6] Flash Read Collision Error Flag */
mbed_official 324:406fd2029f23 160 uint8_t CCIF : 1; /*!< [7] Command Complete Interrupt Flag */
mbed_official 324:406fd2029f23 161 } B;
mbed_official 324:406fd2029f23 162 } hw_ftfa_fstat_t;
mbed_official 324:406fd2029f23 163
mbed_official 324:406fd2029f23 164 /*!
mbed_official 324:406fd2029f23 165 * @name Constants and macros for entire FTFA_FSTAT register
mbed_official 324:406fd2029f23 166 */
mbed_official 324:406fd2029f23 167 /*@{*/
mbed_official 324:406fd2029f23 168 #define HW_FTFA_FSTAT_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 169
mbed_official 324:406fd2029f23 170 #define HW_FTFA_FSTAT(x) (*(__IO hw_ftfa_fstat_t *) HW_FTFA_FSTAT_ADDR(x))
mbed_official 324:406fd2029f23 171 #define HW_FTFA_FSTAT_RD(x) (HW_FTFA_FSTAT(x).U)
mbed_official 324:406fd2029f23 172 #define HW_FTFA_FSTAT_WR(x, v) (HW_FTFA_FSTAT(x).U = (v))
mbed_official 324:406fd2029f23 173 #define HW_FTFA_FSTAT_SET(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) | (v)))
mbed_official 324:406fd2029f23 174 #define HW_FTFA_FSTAT_CLR(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 175 #define HW_FTFA_FSTAT_TOG(x, v) (HW_FTFA_FSTAT_WR(x, HW_FTFA_FSTAT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 176 /*@}*/
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*
mbed_official 324:406fd2029f23 179 * Constants & macros for individual FTFA_FSTAT bitfields
mbed_official 324:406fd2029f23 180 */
mbed_official 324:406fd2029f23 181
mbed_official 324:406fd2029f23 182 /*!
mbed_official 324:406fd2029f23 183 * @name Register FTFA_FSTAT, field MGSTAT0[0] (RO)
mbed_official 324:406fd2029f23 184 *
mbed_official 324:406fd2029f23 185 * The MGSTAT0 status flag is set if an error is detected during execution of a
mbed_official 324:406fd2029f23 186 * flash command or during the flash reset sequence. As a status flag, this field
mbed_official 324:406fd2029f23 187 * cannot (and need not) be cleared by the user like the other error flags in
mbed_official 324:406fd2029f23 188 * this register. The value of the MGSTAT0 bit for "command-N" is valid only at the
mbed_official 324:406fd2029f23 189 * end of the "command-N" execution when CCIF=1 and before the next command has
mbed_official 324:406fd2029f23 190 * been launched. At some point during the execution of "command-N+1," the
mbed_official 324:406fd2029f23 191 * previous result is discarded and any previous error is cleared.
mbed_official 324:406fd2029f23 192 */
mbed_official 324:406fd2029f23 193 /*@{*/
mbed_official 324:406fd2029f23 194 #define BP_FTFA_FSTAT_MGSTAT0 (0U) /*!< Bit position for FTFA_FSTAT_MGSTAT0. */
mbed_official 324:406fd2029f23 195 #define BM_FTFA_FSTAT_MGSTAT0 (0x01U) /*!< Bit mask for FTFA_FSTAT_MGSTAT0. */
mbed_official 324:406fd2029f23 196 #define BS_FTFA_FSTAT_MGSTAT0 (1U) /*!< Bit field size in bits for FTFA_FSTAT_MGSTAT0. */
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*! @brief Read current value of the FTFA_FSTAT_MGSTAT0 field. */
mbed_official 324:406fd2029f23 199 #define BR_FTFA_FSTAT_MGSTAT0(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_MGSTAT0))
mbed_official 324:406fd2029f23 200 /*@}*/
mbed_official 324:406fd2029f23 201
mbed_official 324:406fd2029f23 202 /*!
mbed_official 324:406fd2029f23 203 * @name Register FTFA_FSTAT, field FPVIOL[4] (W1C)
mbed_official 324:406fd2029f23 204 *
mbed_official 324:406fd2029f23 205 * Indicates an attempt was made to program or erase an address in a protected
mbed_official 324:406fd2029f23 206 * area of program flash memory during a command write sequence . While FPVIOL is
mbed_official 324:406fd2029f23 207 * set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is
mbed_official 324:406fd2029f23 208 * cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit has no effect.
mbed_official 324:406fd2029f23 209 *
mbed_official 324:406fd2029f23 210 * Values:
mbed_official 324:406fd2029f23 211 * - 0 - No protection violation detected
mbed_official 324:406fd2029f23 212 * - 1 - Protection violation detected
mbed_official 324:406fd2029f23 213 */
mbed_official 324:406fd2029f23 214 /*@{*/
mbed_official 324:406fd2029f23 215 #define BP_FTFA_FSTAT_FPVIOL (4U) /*!< Bit position for FTFA_FSTAT_FPVIOL. */
mbed_official 324:406fd2029f23 216 #define BM_FTFA_FSTAT_FPVIOL (0x10U) /*!< Bit mask for FTFA_FSTAT_FPVIOL. */
mbed_official 324:406fd2029f23 217 #define BS_FTFA_FSTAT_FPVIOL (1U) /*!< Bit field size in bits for FTFA_FSTAT_FPVIOL. */
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*! @brief Read current value of the FTFA_FSTAT_FPVIOL field. */
mbed_official 324:406fd2029f23 220 #define BR_FTFA_FSTAT_FPVIOL(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL))
mbed_official 324:406fd2029f23 221
mbed_official 324:406fd2029f23 222 /*! @brief Format value for bitfield FTFA_FSTAT_FPVIOL. */
mbed_official 324:406fd2029f23 223 #define BF_FTFA_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_FPVIOL) & BM_FTFA_FSTAT_FPVIOL)
mbed_official 324:406fd2029f23 224
mbed_official 324:406fd2029f23 225 /*! @brief Set the FPVIOL field to a new value. */
mbed_official 324:406fd2029f23 226 #define BW_FTFA_FSTAT_FPVIOL(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_FPVIOL) = (v))
mbed_official 324:406fd2029f23 227 /*@}*/
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*!
mbed_official 324:406fd2029f23 230 * @name Register FTFA_FSTAT, field ACCERR[5] (W1C)
mbed_official 324:406fd2029f23 231 *
mbed_official 324:406fd2029f23 232 * Indicates an illegal access has occurred to a flash memory resource caused by
mbed_official 324:406fd2029f23 233 * a violation of the command write sequence or issuing an illegal flash
mbed_official 324:406fd2029f23 234 * command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command.
mbed_official 324:406fd2029f23 235 * The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the ACCERR bit
mbed_official 324:406fd2029f23 236 * has no effect.
mbed_official 324:406fd2029f23 237 *
mbed_official 324:406fd2029f23 238 * Values:
mbed_official 324:406fd2029f23 239 * - 0 - No access error detected
mbed_official 324:406fd2029f23 240 * - 1 - Access error detected
mbed_official 324:406fd2029f23 241 */
mbed_official 324:406fd2029f23 242 /*@{*/
mbed_official 324:406fd2029f23 243 #define BP_FTFA_FSTAT_ACCERR (5U) /*!< Bit position for FTFA_FSTAT_ACCERR. */
mbed_official 324:406fd2029f23 244 #define BM_FTFA_FSTAT_ACCERR (0x20U) /*!< Bit mask for FTFA_FSTAT_ACCERR. */
mbed_official 324:406fd2029f23 245 #define BS_FTFA_FSTAT_ACCERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_ACCERR. */
mbed_official 324:406fd2029f23 246
mbed_official 324:406fd2029f23 247 /*! @brief Read current value of the FTFA_FSTAT_ACCERR field. */
mbed_official 324:406fd2029f23 248 #define BR_FTFA_FSTAT_ACCERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR))
mbed_official 324:406fd2029f23 249
mbed_official 324:406fd2029f23 250 /*! @brief Format value for bitfield FTFA_FSTAT_ACCERR. */
mbed_official 324:406fd2029f23 251 #define BF_FTFA_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_ACCERR) & BM_FTFA_FSTAT_ACCERR)
mbed_official 324:406fd2029f23 252
mbed_official 324:406fd2029f23 253 /*! @brief Set the ACCERR field to a new value. */
mbed_official 324:406fd2029f23 254 #define BW_FTFA_FSTAT_ACCERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_ACCERR) = (v))
mbed_official 324:406fd2029f23 255 /*@}*/
mbed_official 324:406fd2029f23 256
mbed_official 324:406fd2029f23 257 /*!
mbed_official 324:406fd2029f23 258 * @name Register FTFA_FSTAT, field RDCOLERR[6] (W1C)
mbed_official 324:406fd2029f23 259 *
mbed_official 324:406fd2029f23 260 * Indicates that the MCU attempted a read from a flash memory resource that was
mbed_official 324:406fd2029f23 261 * being manipulated by a flash command (CCIF=0). Any simultaneous access is
mbed_official 324:406fd2029f23 262 * detected as a collision error by the block arbitration logic. The read data in
mbed_official 324:406fd2029f23 263 * this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to
mbed_official 324:406fd2029f23 264 * it. Writing a 0 to RDCOLERR has no effect.
mbed_official 324:406fd2029f23 265 *
mbed_official 324:406fd2029f23 266 * Values:
mbed_official 324:406fd2029f23 267 * - 0 - No collision error detected
mbed_official 324:406fd2029f23 268 * - 1 - Collision error detected
mbed_official 324:406fd2029f23 269 */
mbed_official 324:406fd2029f23 270 /*@{*/
mbed_official 324:406fd2029f23 271 #define BP_FTFA_FSTAT_RDCOLERR (6U) /*!< Bit position for FTFA_FSTAT_RDCOLERR. */
mbed_official 324:406fd2029f23 272 #define BM_FTFA_FSTAT_RDCOLERR (0x40U) /*!< Bit mask for FTFA_FSTAT_RDCOLERR. */
mbed_official 324:406fd2029f23 273 #define BS_FTFA_FSTAT_RDCOLERR (1U) /*!< Bit field size in bits for FTFA_FSTAT_RDCOLERR. */
mbed_official 324:406fd2029f23 274
mbed_official 324:406fd2029f23 275 /*! @brief Read current value of the FTFA_FSTAT_RDCOLERR field. */
mbed_official 324:406fd2029f23 276 #define BR_FTFA_FSTAT_RDCOLERR(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR))
mbed_official 324:406fd2029f23 277
mbed_official 324:406fd2029f23 278 /*! @brief Format value for bitfield FTFA_FSTAT_RDCOLERR. */
mbed_official 324:406fd2029f23 279 #define BF_FTFA_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_RDCOLERR) & BM_FTFA_FSTAT_RDCOLERR)
mbed_official 324:406fd2029f23 280
mbed_official 324:406fd2029f23 281 /*! @brief Set the RDCOLERR field to a new value. */
mbed_official 324:406fd2029f23 282 #define BW_FTFA_FSTAT_RDCOLERR(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_RDCOLERR) = (v))
mbed_official 324:406fd2029f23 283 /*@}*/
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*!
mbed_official 324:406fd2029f23 286 * @name Register FTFA_FSTAT, field CCIF[7] (W1C)
mbed_official 324:406fd2029f23 287 *
mbed_official 324:406fd2029f23 288 * Indicates that a flash command has completed. The CCIF flag is cleared by
mbed_official 324:406fd2029f23 289 * writing a 1 to CCIF to launch a command, and CCIF stays low until command
mbed_official 324:406fd2029f23 290 * completion or command violation. CCIF is reset to 0 but is set to 1 by the memory
mbed_official 324:406fd2029f23 291 * controller at the end of the reset initialization sequence. Depending on how
mbed_official 324:406fd2029f23 292 * quickly the read occurs after reset release, the user may or may not see the 0
mbed_official 324:406fd2029f23 293 * hardware reset value.
mbed_official 324:406fd2029f23 294 *
mbed_official 324:406fd2029f23 295 * Values:
mbed_official 324:406fd2029f23 296 * - 0 - Flash command in progress
mbed_official 324:406fd2029f23 297 * - 1 - Flash command has completed
mbed_official 324:406fd2029f23 298 */
mbed_official 324:406fd2029f23 299 /*@{*/
mbed_official 324:406fd2029f23 300 #define BP_FTFA_FSTAT_CCIF (7U) /*!< Bit position for FTFA_FSTAT_CCIF. */
mbed_official 324:406fd2029f23 301 #define BM_FTFA_FSTAT_CCIF (0x80U) /*!< Bit mask for FTFA_FSTAT_CCIF. */
mbed_official 324:406fd2029f23 302 #define BS_FTFA_FSTAT_CCIF (1U) /*!< Bit field size in bits for FTFA_FSTAT_CCIF. */
mbed_official 324:406fd2029f23 303
mbed_official 324:406fd2029f23 304 /*! @brief Read current value of the FTFA_FSTAT_CCIF field. */
mbed_official 324:406fd2029f23 305 #define BR_FTFA_FSTAT_CCIF(x) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF))
mbed_official 324:406fd2029f23 306
mbed_official 324:406fd2029f23 307 /*! @brief Format value for bitfield FTFA_FSTAT_CCIF. */
mbed_official 324:406fd2029f23 308 #define BF_FTFA_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FSTAT_CCIF) & BM_FTFA_FSTAT_CCIF)
mbed_official 324:406fd2029f23 309
mbed_official 324:406fd2029f23 310 /*! @brief Set the CCIF field to a new value. */
mbed_official 324:406fd2029f23 311 #define BW_FTFA_FSTAT_CCIF(x, v) (BITBAND_ACCESS8(HW_FTFA_FSTAT_ADDR(x), BP_FTFA_FSTAT_CCIF) = (v))
mbed_official 324:406fd2029f23 312 /*@}*/
mbed_official 324:406fd2029f23 313
mbed_official 324:406fd2029f23 314 /*******************************************************************************
mbed_official 324:406fd2029f23 315 * HW_FTFA_FCNFG - Flash Configuration Register
mbed_official 324:406fd2029f23 316 ******************************************************************************/
mbed_official 324:406fd2029f23 317
mbed_official 324:406fd2029f23 318 /*!
mbed_official 324:406fd2029f23 319 * @brief HW_FTFA_FCNFG - Flash Configuration Register (RW)
mbed_official 324:406fd2029f23 320 *
mbed_official 324:406fd2029f23 321 * Reset value: 0x00U
mbed_official 324:406fd2029f23 322 *
mbed_official 324:406fd2029f23 323 * This register provides information on the current functional state of the
mbed_official 324:406fd2029f23 324 * flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write
mbed_official 324:406fd2029f23 325 * restrictions. The unassigned bits read as noted and are not writable.
mbed_official 324:406fd2029f23 326 */
mbed_official 324:406fd2029f23 327 typedef union _hw_ftfa_fcnfg
mbed_official 324:406fd2029f23 328 {
mbed_official 324:406fd2029f23 329 uint8_t U;
mbed_official 324:406fd2029f23 330 struct _hw_ftfa_fcnfg_bitfields
mbed_official 324:406fd2029f23 331 {
mbed_official 324:406fd2029f23 332 uint8_t RESERVED0 : 4; /*!< [3:0] */
mbed_official 324:406fd2029f23 333 uint8_t ERSSUSP : 1; /*!< [4] Erase Suspend */
mbed_official 324:406fd2029f23 334 uint8_t ERSAREQ : 1; /*!< [5] Erase All Request */
mbed_official 324:406fd2029f23 335 uint8_t RDCOLLIE : 1; /*!< [6] Read Collision Error Interrupt Enable
mbed_official 324:406fd2029f23 336 * */
mbed_official 324:406fd2029f23 337 uint8_t CCIE : 1; /*!< [7] Command Complete Interrupt Enable */
mbed_official 324:406fd2029f23 338 } B;
mbed_official 324:406fd2029f23 339 } hw_ftfa_fcnfg_t;
mbed_official 324:406fd2029f23 340
mbed_official 324:406fd2029f23 341 /*!
mbed_official 324:406fd2029f23 342 * @name Constants and macros for entire FTFA_FCNFG register
mbed_official 324:406fd2029f23 343 */
mbed_official 324:406fd2029f23 344 /*@{*/
mbed_official 324:406fd2029f23 345 #define HW_FTFA_FCNFG_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 346
mbed_official 324:406fd2029f23 347 #define HW_FTFA_FCNFG(x) (*(__IO hw_ftfa_fcnfg_t *) HW_FTFA_FCNFG_ADDR(x))
mbed_official 324:406fd2029f23 348 #define HW_FTFA_FCNFG_RD(x) (HW_FTFA_FCNFG(x).U)
mbed_official 324:406fd2029f23 349 #define HW_FTFA_FCNFG_WR(x, v) (HW_FTFA_FCNFG(x).U = (v))
mbed_official 324:406fd2029f23 350 #define HW_FTFA_FCNFG_SET(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) | (v)))
mbed_official 324:406fd2029f23 351 #define HW_FTFA_FCNFG_CLR(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 352 #define HW_FTFA_FCNFG_TOG(x, v) (HW_FTFA_FCNFG_WR(x, HW_FTFA_FCNFG_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 353 /*@}*/
mbed_official 324:406fd2029f23 354
mbed_official 324:406fd2029f23 355 /*
mbed_official 324:406fd2029f23 356 * Constants & macros for individual FTFA_FCNFG bitfields
mbed_official 324:406fd2029f23 357 */
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*!
mbed_official 324:406fd2029f23 360 * @name Register FTFA_FCNFG, field ERSSUSP[4] (RW)
mbed_official 324:406fd2029f23 361 *
mbed_official 324:406fd2029f23 362 * Allows the user to suspend (interrupt) the Erase Flash Sector command while
mbed_official 324:406fd2029f23 363 * it is executing.
mbed_official 324:406fd2029f23 364 *
mbed_official 324:406fd2029f23 365 * Values:
mbed_official 324:406fd2029f23 366 * - 0 - No suspend requested
mbed_official 324:406fd2029f23 367 * - 1 - Suspend the current Erase Flash Sector command execution.
mbed_official 324:406fd2029f23 368 */
mbed_official 324:406fd2029f23 369 /*@{*/
mbed_official 324:406fd2029f23 370 #define BP_FTFA_FCNFG_ERSSUSP (4U) /*!< Bit position for FTFA_FCNFG_ERSSUSP. */
mbed_official 324:406fd2029f23 371 #define BM_FTFA_FCNFG_ERSSUSP (0x10U) /*!< Bit mask for FTFA_FCNFG_ERSSUSP. */
mbed_official 324:406fd2029f23 372 #define BS_FTFA_FCNFG_ERSSUSP (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSSUSP. */
mbed_official 324:406fd2029f23 373
mbed_official 324:406fd2029f23 374 /*! @brief Read current value of the FTFA_FCNFG_ERSSUSP field. */
mbed_official 324:406fd2029f23 375 #define BR_FTFA_FCNFG_ERSSUSP(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP))
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*! @brief Format value for bitfield FTFA_FCNFG_ERSSUSP. */
mbed_official 324:406fd2029f23 378 #define BF_FTFA_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_ERSSUSP) & BM_FTFA_FCNFG_ERSSUSP)
mbed_official 324:406fd2029f23 379
mbed_official 324:406fd2029f23 380 /*! @brief Set the ERSSUSP field to a new value. */
mbed_official 324:406fd2029f23 381 #define BW_FTFA_FCNFG_ERSSUSP(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSSUSP) = (v))
mbed_official 324:406fd2029f23 382 /*@}*/
mbed_official 324:406fd2029f23 383
mbed_official 324:406fd2029f23 384 /*!
mbed_official 324:406fd2029f23 385 * @name Register FTFA_FCNFG, field ERSAREQ[5] (RO)
mbed_official 324:406fd2029f23 386 *
mbed_official 324:406fd2029f23 387 * Issues a request to the memory controller to execute the Erase All Blocks
mbed_official 324:406fd2029f23 388 * command and release security. ERSAREQ is not directly writable but is under
mbed_official 324:406fd2029f23 389 * indirect user control. Refer to the device's Chip Configuration details on how to
mbed_official 324:406fd2029f23 390 * request this command. ERSAREQ sets when an erase all request is triggered
mbed_official 324:406fd2029f23 391 * external to the flash memory module and CCIF is set (no command is currently being
mbed_official 324:406fd2029f23 392 * executed). ERSAREQ is cleared by the flash memory module when the operation
mbed_official 324:406fd2029f23 393 * completes.
mbed_official 324:406fd2029f23 394 *
mbed_official 324:406fd2029f23 395 * Values:
mbed_official 324:406fd2029f23 396 * - 0 - No request or request complete
mbed_official 324:406fd2029f23 397 * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
mbed_official 324:406fd2029f23 398 * program the security byte in the Flash Configuration Field to the unsecure
mbed_official 324:406fd2029f23 399 * state, and release MCU security by setting the FSEC[SEC] field to the
mbed_official 324:406fd2029f23 400 * unsecure state.
mbed_official 324:406fd2029f23 401 */
mbed_official 324:406fd2029f23 402 /*@{*/
mbed_official 324:406fd2029f23 403 #define BP_FTFA_FCNFG_ERSAREQ (5U) /*!< Bit position for FTFA_FCNFG_ERSAREQ. */
mbed_official 324:406fd2029f23 404 #define BM_FTFA_FCNFG_ERSAREQ (0x20U) /*!< Bit mask for FTFA_FCNFG_ERSAREQ. */
mbed_official 324:406fd2029f23 405 #define BS_FTFA_FCNFG_ERSAREQ (1U) /*!< Bit field size in bits for FTFA_FCNFG_ERSAREQ. */
mbed_official 324:406fd2029f23 406
mbed_official 324:406fd2029f23 407 /*! @brief Read current value of the FTFA_FCNFG_ERSAREQ field. */
mbed_official 324:406fd2029f23 408 #define BR_FTFA_FCNFG_ERSAREQ(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_ERSAREQ))
mbed_official 324:406fd2029f23 409 /*@}*/
mbed_official 324:406fd2029f23 410
mbed_official 324:406fd2029f23 411 /*!
mbed_official 324:406fd2029f23 412 * @name Register FTFA_FCNFG, field RDCOLLIE[6] (RW)
mbed_official 324:406fd2029f23 413 *
mbed_official 324:406fd2029f23 414 * Controls interrupt generation when a flash memory read collision error occurs.
mbed_official 324:406fd2029f23 415 *
mbed_official 324:406fd2029f23 416 * Values:
mbed_official 324:406fd2029f23 417 * - 0 - Read collision error interrupt disabled
mbed_official 324:406fd2029f23 418 * - 1 - Read collision error interrupt enabled. An interrupt request is
mbed_official 324:406fd2029f23 419 * generated whenever a flash memory read collision error is detected (see the
mbed_official 324:406fd2029f23 420 * description of FSTAT[RDCOLERR]).
mbed_official 324:406fd2029f23 421 */
mbed_official 324:406fd2029f23 422 /*@{*/
mbed_official 324:406fd2029f23 423 #define BP_FTFA_FCNFG_RDCOLLIE (6U) /*!< Bit position for FTFA_FCNFG_RDCOLLIE. */
mbed_official 324:406fd2029f23 424 #define BM_FTFA_FCNFG_RDCOLLIE (0x40U) /*!< Bit mask for FTFA_FCNFG_RDCOLLIE. */
mbed_official 324:406fd2029f23 425 #define BS_FTFA_FCNFG_RDCOLLIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_RDCOLLIE. */
mbed_official 324:406fd2029f23 426
mbed_official 324:406fd2029f23 427 /*! @brief Read current value of the FTFA_FCNFG_RDCOLLIE field. */
mbed_official 324:406fd2029f23 428 #define BR_FTFA_FCNFG_RDCOLLIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE))
mbed_official 324:406fd2029f23 429
mbed_official 324:406fd2029f23 430 /*! @brief Format value for bitfield FTFA_FCNFG_RDCOLLIE. */
mbed_official 324:406fd2029f23 431 #define BF_FTFA_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_RDCOLLIE) & BM_FTFA_FCNFG_RDCOLLIE)
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Set the RDCOLLIE field to a new value. */
mbed_official 324:406fd2029f23 434 #define BW_FTFA_FCNFG_RDCOLLIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_RDCOLLIE) = (v))
mbed_official 324:406fd2029f23 435 /*@}*/
mbed_official 324:406fd2029f23 436
mbed_official 324:406fd2029f23 437 /*!
mbed_official 324:406fd2029f23 438 * @name Register FTFA_FCNFG, field CCIE[7] (RW)
mbed_official 324:406fd2029f23 439 *
mbed_official 324:406fd2029f23 440 * Controls interrupt generation when a flash command completes.
mbed_official 324:406fd2029f23 441 *
mbed_official 324:406fd2029f23 442 * Values:
mbed_official 324:406fd2029f23 443 * - 0 - Command complete interrupt disabled
mbed_official 324:406fd2029f23 444 * - 1 - Command complete interrupt enabled. An interrupt request is generated
mbed_official 324:406fd2029f23 445 * whenever the FSTAT[CCIF] flag is set.
mbed_official 324:406fd2029f23 446 */
mbed_official 324:406fd2029f23 447 /*@{*/
mbed_official 324:406fd2029f23 448 #define BP_FTFA_FCNFG_CCIE (7U) /*!< Bit position for FTFA_FCNFG_CCIE. */
mbed_official 324:406fd2029f23 449 #define BM_FTFA_FCNFG_CCIE (0x80U) /*!< Bit mask for FTFA_FCNFG_CCIE. */
mbed_official 324:406fd2029f23 450 #define BS_FTFA_FCNFG_CCIE (1U) /*!< Bit field size in bits for FTFA_FCNFG_CCIE. */
mbed_official 324:406fd2029f23 451
mbed_official 324:406fd2029f23 452 /*! @brief Read current value of the FTFA_FCNFG_CCIE field. */
mbed_official 324:406fd2029f23 453 #define BR_FTFA_FCNFG_CCIE(x) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE))
mbed_official 324:406fd2029f23 454
mbed_official 324:406fd2029f23 455 /*! @brief Format value for bitfield FTFA_FCNFG_CCIE. */
mbed_official 324:406fd2029f23 456 #define BF_FTFA_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCNFG_CCIE) & BM_FTFA_FCNFG_CCIE)
mbed_official 324:406fd2029f23 457
mbed_official 324:406fd2029f23 458 /*! @brief Set the CCIE field to a new value. */
mbed_official 324:406fd2029f23 459 #define BW_FTFA_FCNFG_CCIE(x, v) (BITBAND_ACCESS8(HW_FTFA_FCNFG_ADDR(x), BP_FTFA_FCNFG_CCIE) = (v))
mbed_official 324:406fd2029f23 460 /*@}*/
mbed_official 324:406fd2029f23 461
mbed_official 324:406fd2029f23 462 /*******************************************************************************
mbed_official 324:406fd2029f23 463 * HW_FTFA_FSEC - Flash Security Register
mbed_official 324:406fd2029f23 464 ******************************************************************************/
mbed_official 324:406fd2029f23 465
mbed_official 324:406fd2029f23 466 /*!
mbed_official 324:406fd2029f23 467 * @brief HW_FTFA_FSEC - Flash Security Register (RO)
mbed_official 324:406fd2029f23 468 *
mbed_official 324:406fd2029f23 469 * Reset value: 0x00U
mbed_official 324:406fd2029f23 470 *
mbed_official 324:406fd2029f23 471 * This read-only register holds all bits associated with the security of the
mbed_official 324:406fd2029f23 472 * MCU and flash memory module. During the reset sequence, the register is loaded
mbed_official 324:406fd2029f23 473 * with the contents of the flash security byte in the Flash Configuration Field
mbed_official 324:406fd2029f23 474 * located in program flash memory. The flash basis for the values is signified by
mbed_official 324:406fd2029f23 475 * X in the reset value.
mbed_official 324:406fd2029f23 476 */
mbed_official 324:406fd2029f23 477 typedef union _hw_ftfa_fsec
mbed_official 324:406fd2029f23 478 {
mbed_official 324:406fd2029f23 479 uint8_t U;
mbed_official 324:406fd2029f23 480 struct _hw_ftfa_fsec_bitfields
mbed_official 324:406fd2029f23 481 {
mbed_official 324:406fd2029f23 482 uint8_t SEC : 2; /*!< [1:0] Flash Security */
mbed_official 324:406fd2029f23 483 uint8_t FSLACC : 2; /*!< [3:2] Freescale Failure Analysis Access Code
mbed_official 324:406fd2029f23 484 * */
mbed_official 324:406fd2029f23 485 uint8_t MEEN : 2; /*!< [5:4] Mass Erase Enable Bits */
mbed_official 324:406fd2029f23 486 uint8_t KEYEN : 2; /*!< [7:6] Backdoor Key Security Enable */
mbed_official 324:406fd2029f23 487 } B;
mbed_official 324:406fd2029f23 488 } hw_ftfa_fsec_t;
mbed_official 324:406fd2029f23 489
mbed_official 324:406fd2029f23 490 /*!
mbed_official 324:406fd2029f23 491 * @name Constants and macros for entire FTFA_FSEC register
mbed_official 324:406fd2029f23 492 */
mbed_official 324:406fd2029f23 493 /*@{*/
mbed_official 324:406fd2029f23 494 #define HW_FTFA_FSEC_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 495
mbed_official 324:406fd2029f23 496 #define HW_FTFA_FSEC(x) (*(__I hw_ftfa_fsec_t *) HW_FTFA_FSEC_ADDR(x))
mbed_official 324:406fd2029f23 497 #define HW_FTFA_FSEC_RD(x) (HW_FTFA_FSEC(x).U)
mbed_official 324:406fd2029f23 498 /*@}*/
mbed_official 324:406fd2029f23 499
mbed_official 324:406fd2029f23 500 /*
mbed_official 324:406fd2029f23 501 * Constants & macros for individual FTFA_FSEC bitfields
mbed_official 324:406fd2029f23 502 */
mbed_official 324:406fd2029f23 503
mbed_official 324:406fd2029f23 504 /*!
mbed_official 324:406fd2029f23 505 * @name Register FTFA_FSEC, field SEC[1:0] (RO)
mbed_official 324:406fd2029f23 506 *
mbed_official 324:406fd2029f23 507 * Defines the security state of the MCU. In the secure state, the MCU limits
mbed_official 324:406fd2029f23 508 * access to flash memory module resources. The limitations are defined per device
mbed_official 324:406fd2029f23 509 * and are detailed in the Chip Configuration details. If the flash memory module
mbed_official 324:406fd2029f23 510 * is unsecured using backdoor key access, SEC is forced to 10b.
mbed_official 324:406fd2029f23 511 *
mbed_official 324:406fd2029f23 512 * Values:
mbed_official 324:406fd2029f23 513 * - 00 - MCU security status is secure.
mbed_official 324:406fd2029f23 514 * - 01 - MCU security status is secure.
mbed_official 324:406fd2029f23 515 * - 10 - MCU security status is unsecure. (The standard shipping condition of
mbed_official 324:406fd2029f23 516 * the flash memory module is unsecure.)
mbed_official 324:406fd2029f23 517 * - 11 - MCU security status is secure.
mbed_official 324:406fd2029f23 518 */
mbed_official 324:406fd2029f23 519 /*@{*/
mbed_official 324:406fd2029f23 520 #define BP_FTFA_FSEC_SEC (0U) /*!< Bit position for FTFA_FSEC_SEC. */
mbed_official 324:406fd2029f23 521 #define BM_FTFA_FSEC_SEC (0x03U) /*!< Bit mask for FTFA_FSEC_SEC. */
mbed_official 324:406fd2029f23 522 #define BS_FTFA_FSEC_SEC (2U) /*!< Bit field size in bits for FTFA_FSEC_SEC. */
mbed_official 324:406fd2029f23 523
mbed_official 324:406fd2029f23 524 /*! @brief Read current value of the FTFA_FSEC_SEC field. */
mbed_official 324:406fd2029f23 525 #define BR_FTFA_FSEC_SEC(x) (HW_FTFA_FSEC(x).B.SEC)
mbed_official 324:406fd2029f23 526 /*@}*/
mbed_official 324:406fd2029f23 527
mbed_official 324:406fd2029f23 528 /*!
mbed_official 324:406fd2029f23 529 * @name Register FTFA_FSEC, field FSLACC[3:2] (RO)
mbed_official 324:406fd2029f23 530 *
mbed_official 324:406fd2029f23 531 * Enables or disables access to the flash memory contents during returned part
mbed_official 324:406fd2029f23 532 * failure analysis at Freescale. When SEC is secure and FSLACC is denied, access
mbed_official 324:406fd2029f23 533 * to the program flash contents is denied and any failure analysis performed by
mbed_official 324:406fd2029f23 534 * Freescale factory test must begin with a full erase to unsecure the part.
mbed_official 324:406fd2029f23 535 * When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted),
mbed_official 324:406fd2029f23 536 * Freescale factory testing has visibility of the current flash contents. The
mbed_official 324:406fd2029f23 537 * state of the FSLACC bits is only relevant when SEC is set to secure. When SEC
mbed_official 324:406fd2029f23 538 * is set to unsecure, the FSLACC setting does not matter.
mbed_official 324:406fd2029f23 539 *
mbed_official 324:406fd2029f23 540 * Values:
mbed_official 324:406fd2029f23 541 * - 00 - Freescale factory access granted
mbed_official 324:406fd2029f23 542 * - 01 - Freescale factory access denied
mbed_official 324:406fd2029f23 543 * - 10 - Freescale factory access denied
mbed_official 324:406fd2029f23 544 * - 11 - Freescale factory access granted
mbed_official 324:406fd2029f23 545 */
mbed_official 324:406fd2029f23 546 /*@{*/
mbed_official 324:406fd2029f23 547 #define BP_FTFA_FSEC_FSLACC (2U) /*!< Bit position for FTFA_FSEC_FSLACC. */
mbed_official 324:406fd2029f23 548 #define BM_FTFA_FSEC_FSLACC (0x0CU) /*!< Bit mask for FTFA_FSEC_FSLACC. */
mbed_official 324:406fd2029f23 549 #define BS_FTFA_FSEC_FSLACC (2U) /*!< Bit field size in bits for FTFA_FSEC_FSLACC. */
mbed_official 324:406fd2029f23 550
mbed_official 324:406fd2029f23 551 /*! @brief Read current value of the FTFA_FSEC_FSLACC field. */
mbed_official 324:406fd2029f23 552 #define BR_FTFA_FSEC_FSLACC(x) (HW_FTFA_FSEC(x).B.FSLACC)
mbed_official 324:406fd2029f23 553 /*@}*/
mbed_official 324:406fd2029f23 554
mbed_official 324:406fd2029f23 555 /*!
mbed_official 324:406fd2029f23 556 * @name Register FTFA_FSEC, field MEEN[5:4] (RO)
mbed_official 324:406fd2029f23 557 *
mbed_official 324:406fd2029f23 558 * Enables and disables mass erase capability of the flash memory module. The
mbed_official 324:406fd2029f23 559 * state of this field is relevant only when SEC is set to secure outside of NVM
mbed_official 324:406fd2029f23 560 * Normal Mode. When SEC is set to unsecure, the MEEN setting does not matter.
mbed_official 324:406fd2029f23 561 *
mbed_official 324:406fd2029f23 562 * Values:
mbed_official 324:406fd2029f23 563 * - 00 - Mass erase is enabled
mbed_official 324:406fd2029f23 564 * - 01 - Mass erase is enabled
mbed_official 324:406fd2029f23 565 * - 10 - Mass erase is disabled
mbed_official 324:406fd2029f23 566 * - 11 - Mass erase is enabled
mbed_official 324:406fd2029f23 567 */
mbed_official 324:406fd2029f23 568 /*@{*/
mbed_official 324:406fd2029f23 569 #define BP_FTFA_FSEC_MEEN (4U) /*!< Bit position for FTFA_FSEC_MEEN. */
mbed_official 324:406fd2029f23 570 #define BM_FTFA_FSEC_MEEN (0x30U) /*!< Bit mask for FTFA_FSEC_MEEN. */
mbed_official 324:406fd2029f23 571 #define BS_FTFA_FSEC_MEEN (2U) /*!< Bit field size in bits for FTFA_FSEC_MEEN. */
mbed_official 324:406fd2029f23 572
mbed_official 324:406fd2029f23 573 /*! @brief Read current value of the FTFA_FSEC_MEEN field. */
mbed_official 324:406fd2029f23 574 #define BR_FTFA_FSEC_MEEN(x) (HW_FTFA_FSEC(x).B.MEEN)
mbed_official 324:406fd2029f23 575 /*@}*/
mbed_official 324:406fd2029f23 576
mbed_official 324:406fd2029f23 577 /*!
mbed_official 324:406fd2029f23 578 * @name Register FTFA_FSEC, field KEYEN[7:6] (RO)
mbed_official 324:406fd2029f23 579 *
mbed_official 324:406fd2029f23 580 * Enables or disables backdoor key access to the flash memory module.
mbed_official 324:406fd2029f23 581 *
mbed_official 324:406fd2029f23 582 * Values:
mbed_official 324:406fd2029f23 583 * - 00 - Backdoor key access disabled
mbed_official 324:406fd2029f23 584 * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
mbed_official 324:406fd2029f23 585 * backdoor key access)
mbed_official 324:406fd2029f23 586 * - 10 - Backdoor key access enabled
mbed_official 324:406fd2029f23 587 * - 11 - Backdoor key access disabled
mbed_official 324:406fd2029f23 588 */
mbed_official 324:406fd2029f23 589 /*@{*/
mbed_official 324:406fd2029f23 590 #define BP_FTFA_FSEC_KEYEN (6U) /*!< Bit position for FTFA_FSEC_KEYEN. */
mbed_official 324:406fd2029f23 591 #define BM_FTFA_FSEC_KEYEN (0xC0U) /*!< Bit mask for FTFA_FSEC_KEYEN. */
mbed_official 324:406fd2029f23 592 #define BS_FTFA_FSEC_KEYEN (2U) /*!< Bit field size in bits for FTFA_FSEC_KEYEN. */
mbed_official 324:406fd2029f23 593
mbed_official 324:406fd2029f23 594 /*! @brief Read current value of the FTFA_FSEC_KEYEN field. */
mbed_official 324:406fd2029f23 595 #define BR_FTFA_FSEC_KEYEN(x) (HW_FTFA_FSEC(x).B.KEYEN)
mbed_official 324:406fd2029f23 596 /*@}*/
mbed_official 324:406fd2029f23 597
mbed_official 324:406fd2029f23 598 /*******************************************************************************
mbed_official 324:406fd2029f23 599 * HW_FTFA_FOPT - Flash Option Register
mbed_official 324:406fd2029f23 600 ******************************************************************************/
mbed_official 324:406fd2029f23 601
mbed_official 324:406fd2029f23 602 /*!
mbed_official 324:406fd2029f23 603 * @brief HW_FTFA_FOPT - Flash Option Register (RO)
mbed_official 324:406fd2029f23 604 *
mbed_official 324:406fd2029f23 605 * Reset value: 0x00U
mbed_official 324:406fd2029f23 606 *
mbed_official 324:406fd2029f23 607 * The flash option register allows the MCU to customize its operations by
mbed_official 324:406fd2029f23 608 * examining the state of these read-only bits, which are loaded from NVM at reset.
mbed_official 324:406fd2029f23 609 * The function of the bits is defined in the device's Chip Configuration details.
mbed_official 324:406fd2029f23 610 * All bits in the register are read-only . During the reset sequence, the
mbed_official 324:406fd2029f23 611 * register is loaded from the flash nonvolatile option byte in the Flash Configuration
mbed_official 324:406fd2029f23 612 * Field located in program flash memory. The flash basis for the values is
mbed_official 324:406fd2029f23 613 * signified by X in the reset value. However, the register is written to 0xFF if the
mbed_official 324:406fd2029f23 614 * contents of the flash nonvolatile option byte are 0x00.
mbed_official 324:406fd2029f23 615 */
mbed_official 324:406fd2029f23 616 typedef union _hw_ftfa_fopt
mbed_official 324:406fd2029f23 617 {
mbed_official 324:406fd2029f23 618 uint8_t U;
mbed_official 324:406fd2029f23 619 struct _hw_ftfa_fopt_bitfields
mbed_official 324:406fd2029f23 620 {
mbed_official 324:406fd2029f23 621 uint8_t OPT : 8; /*!< [7:0] Nonvolatile Option */
mbed_official 324:406fd2029f23 622 } B;
mbed_official 324:406fd2029f23 623 } hw_ftfa_fopt_t;
mbed_official 324:406fd2029f23 624
mbed_official 324:406fd2029f23 625 /*!
mbed_official 324:406fd2029f23 626 * @name Constants and macros for entire FTFA_FOPT register
mbed_official 324:406fd2029f23 627 */
mbed_official 324:406fd2029f23 628 /*@{*/
mbed_official 324:406fd2029f23 629 #define HW_FTFA_FOPT_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 630
mbed_official 324:406fd2029f23 631 #define HW_FTFA_FOPT(x) (*(__I hw_ftfa_fopt_t *) HW_FTFA_FOPT_ADDR(x))
mbed_official 324:406fd2029f23 632 #define HW_FTFA_FOPT_RD(x) (HW_FTFA_FOPT(x).U)
mbed_official 324:406fd2029f23 633 /*@}*/
mbed_official 324:406fd2029f23 634
mbed_official 324:406fd2029f23 635 /*
mbed_official 324:406fd2029f23 636 * Constants & macros for individual FTFA_FOPT bitfields
mbed_official 324:406fd2029f23 637 */
mbed_official 324:406fd2029f23 638
mbed_official 324:406fd2029f23 639 /*!
mbed_official 324:406fd2029f23 640 * @name Register FTFA_FOPT, field OPT[7:0] (RO)
mbed_official 324:406fd2029f23 641 *
mbed_official 324:406fd2029f23 642 * These bits are loaded from flash to this register at reset. Refer to the
mbed_official 324:406fd2029f23 643 * device's Chip Configuration details for the definition and use of these bits.
mbed_official 324:406fd2029f23 644 */
mbed_official 324:406fd2029f23 645 /*@{*/
mbed_official 324:406fd2029f23 646 #define BP_FTFA_FOPT_OPT (0U) /*!< Bit position for FTFA_FOPT_OPT. */
mbed_official 324:406fd2029f23 647 #define BM_FTFA_FOPT_OPT (0xFFU) /*!< Bit mask for FTFA_FOPT_OPT. */
mbed_official 324:406fd2029f23 648 #define BS_FTFA_FOPT_OPT (8U) /*!< Bit field size in bits for FTFA_FOPT_OPT. */
mbed_official 324:406fd2029f23 649
mbed_official 324:406fd2029f23 650 /*! @brief Read current value of the FTFA_FOPT_OPT field. */
mbed_official 324:406fd2029f23 651 #define BR_FTFA_FOPT_OPT(x) (HW_FTFA_FOPT(x).U)
mbed_official 324:406fd2029f23 652 /*@}*/
mbed_official 324:406fd2029f23 653
mbed_official 324:406fd2029f23 654 /*******************************************************************************
mbed_official 324:406fd2029f23 655 * HW_FTFA_FCCOB3 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 656 ******************************************************************************/
mbed_official 324:406fd2029f23 657
mbed_official 324:406fd2029f23 658 /*!
mbed_official 324:406fd2029f23 659 * @brief HW_FTFA_FCCOB3 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 660 *
mbed_official 324:406fd2029f23 661 * Reset value: 0x00U
mbed_official 324:406fd2029f23 662 *
mbed_official 324:406fd2029f23 663 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 664 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 665 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 666 */
mbed_official 324:406fd2029f23 667 typedef union _hw_ftfa_fccob3
mbed_official 324:406fd2029f23 668 {
mbed_official 324:406fd2029f23 669 uint8_t U;
mbed_official 324:406fd2029f23 670 struct _hw_ftfa_fccob3_bitfields
mbed_official 324:406fd2029f23 671 {
mbed_official 324:406fd2029f23 672 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 673 } B;
mbed_official 324:406fd2029f23 674 } hw_ftfa_fccob3_t;
mbed_official 324:406fd2029f23 675
mbed_official 324:406fd2029f23 676 /*!
mbed_official 324:406fd2029f23 677 * @name Constants and macros for entire FTFA_FCCOB3 register
mbed_official 324:406fd2029f23 678 */
mbed_official 324:406fd2029f23 679 /*@{*/
mbed_official 324:406fd2029f23 680 #define HW_FTFA_FCCOB3_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 681
mbed_official 324:406fd2029f23 682 #define HW_FTFA_FCCOB3(x) (*(__IO hw_ftfa_fccob3_t *) HW_FTFA_FCCOB3_ADDR(x))
mbed_official 324:406fd2029f23 683 #define HW_FTFA_FCCOB3_RD(x) (HW_FTFA_FCCOB3(x).U)
mbed_official 324:406fd2029f23 684 #define HW_FTFA_FCCOB3_WR(x, v) (HW_FTFA_FCCOB3(x).U = (v))
mbed_official 324:406fd2029f23 685 #define HW_FTFA_FCCOB3_SET(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) | (v)))
mbed_official 324:406fd2029f23 686 #define HW_FTFA_FCCOB3_CLR(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 687 #define HW_FTFA_FCCOB3_TOG(x, v) (HW_FTFA_FCCOB3_WR(x, HW_FTFA_FCCOB3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 688 /*@}*/
mbed_official 324:406fd2029f23 689
mbed_official 324:406fd2029f23 690 /*
mbed_official 324:406fd2029f23 691 * Constants & macros for individual FTFA_FCCOB3 bitfields
mbed_official 324:406fd2029f23 692 */
mbed_official 324:406fd2029f23 693
mbed_official 324:406fd2029f23 694 /*!
mbed_official 324:406fd2029f23 695 * @name Register FTFA_FCCOB3, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 696 *
mbed_official 324:406fd2029f23 697 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 698 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 699 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 700 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 701 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 702 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 703 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 704 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 705 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 706 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 707 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 708 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 709 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 710 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 711 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 712 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 713 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 714 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 715 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 716 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 717 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 718 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 719 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 720 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 721 */
mbed_official 324:406fd2029f23 722 /*@{*/
mbed_official 324:406fd2029f23 723 #define BP_FTFA_FCCOB3_CCOBn (0U) /*!< Bit position for FTFA_FCCOB3_CCOBn. */
mbed_official 324:406fd2029f23 724 #define BM_FTFA_FCCOB3_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB3_CCOBn. */
mbed_official 324:406fd2029f23 725 #define BS_FTFA_FCCOB3_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB3_CCOBn. */
mbed_official 324:406fd2029f23 726
mbed_official 324:406fd2029f23 727 /*! @brief Read current value of the FTFA_FCCOB3_CCOBn field. */
mbed_official 324:406fd2029f23 728 #define BR_FTFA_FCCOB3_CCOBn(x) (HW_FTFA_FCCOB3(x).U)
mbed_official 324:406fd2029f23 729
mbed_official 324:406fd2029f23 730 /*! @brief Format value for bitfield FTFA_FCCOB3_CCOBn. */
mbed_official 324:406fd2029f23 731 #define BF_FTFA_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB3_CCOBn) & BM_FTFA_FCCOB3_CCOBn)
mbed_official 324:406fd2029f23 732
mbed_official 324:406fd2029f23 733 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 734 #define BW_FTFA_FCCOB3_CCOBn(x, v) (HW_FTFA_FCCOB3_WR(x, v))
mbed_official 324:406fd2029f23 735 /*@}*/
mbed_official 324:406fd2029f23 736
mbed_official 324:406fd2029f23 737 /*******************************************************************************
mbed_official 324:406fd2029f23 738 * HW_FTFA_FCCOB2 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 739 ******************************************************************************/
mbed_official 324:406fd2029f23 740
mbed_official 324:406fd2029f23 741 /*!
mbed_official 324:406fd2029f23 742 * @brief HW_FTFA_FCCOB2 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 743 *
mbed_official 324:406fd2029f23 744 * Reset value: 0x00U
mbed_official 324:406fd2029f23 745 *
mbed_official 324:406fd2029f23 746 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 747 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 748 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 749 */
mbed_official 324:406fd2029f23 750 typedef union _hw_ftfa_fccob2
mbed_official 324:406fd2029f23 751 {
mbed_official 324:406fd2029f23 752 uint8_t U;
mbed_official 324:406fd2029f23 753 struct _hw_ftfa_fccob2_bitfields
mbed_official 324:406fd2029f23 754 {
mbed_official 324:406fd2029f23 755 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 756 } B;
mbed_official 324:406fd2029f23 757 } hw_ftfa_fccob2_t;
mbed_official 324:406fd2029f23 758
mbed_official 324:406fd2029f23 759 /*!
mbed_official 324:406fd2029f23 760 * @name Constants and macros for entire FTFA_FCCOB2 register
mbed_official 324:406fd2029f23 761 */
mbed_official 324:406fd2029f23 762 /*@{*/
mbed_official 324:406fd2029f23 763 #define HW_FTFA_FCCOB2_ADDR(x) ((x) + 0x5U)
mbed_official 324:406fd2029f23 764
mbed_official 324:406fd2029f23 765 #define HW_FTFA_FCCOB2(x) (*(__IO hw_ftfa_fccob2_t *) HW_FTFA_FCCOB2_ADDR(x))
mbed_official 324:406fd2029f23 766 #define HW_FTFA_FCCOB2_RD(x) (HW_FTFA_FCCOB2(x).U)
mbed_official 324:406fd2029f23 767 #define HW_FTFA_FCCOB2_WR(x, v) (HW_FTFA_FCCOB2(x).U = (v))
mbed_official 324:406fd2029f23 768 #define HW_FTFA_FCCOB2_SET(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) | (v)))
mbed_official 324:406fd2029f23 769 #define HW_FTFA_FCCOB2_CLR(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 770 #define HW_FTFA_FCCOB2_TOG(x, v) (HW_FTFA_FCCOB2_WR(x, HW_FTFA_FCCOB2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 771 /*@}*/
mbed_official 324:406fd2029f23 772
mbed_official 324:406fd2029f23 773 /*
mbed_official 324:406fd2029f23 774 * Constants & macros for individual FTFA_FCCOB2 bitfields
mbed_official 324:406fd2029f23 775 */
mbed_official 324:406fd2029f23 776
mbed_official 324:406fd2029f23 777 /*!
mbed_official 324:406fd2029f23 778 * @name Register FTFA_FCCOB2, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 779 *
mbed_official 324:406fd2029f23 780 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 781 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 782 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 783 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 784 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 785 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 786 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 787 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 788 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 789 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 790 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 791 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 792 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 793 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 794 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 795 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 796 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 797 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 798 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 799 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 800 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 801 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 802 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 803 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 804 */
mbed_official 324:406fd2029f23 805 /*@{*/
mbed_official 324:406fd2029f23 806 #define BP_FTFA_FCCOB2_CCOBn (0U) /*!< Bit position for FTFA_FCCOB2_CCOBn. */
mbed_official 324:406fd2029f23 807 #define BM_FTFA_FCCOB2_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB2_CCOBn. */
mbed_official 324:406fd2029f23 808 #define BS_FTFA_FCCOB2_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB2_CCOBn. */
mbed_official 324:406fd2029f23 809
mbed_official 324:406fd2029f23 810 /*! @brief Read current value of the FTFA_FCCOB2_CCOBn field. */
mbed_official 324:406fd2029f23 811 #define BR_FTFA_FCCOB2_CCOBn(x) (HW_FTFA_FCCOB2(x).U)
mbed_official 324:406fd2029f23 812
mbed_official 324:406fd2029f23 813 /*! @brief Format value for bitfield FTFA_FCCOB2_CCOBn. */
mbed_official 324:406fd2029f23 814 #define BF_FTFA_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB2_CCOBn) & BM_FTFA_FCCOB2_CCOBn)
mbed_official 324:406fd2029f23 815
mbed_official 324:406fd2029f23 816 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 817 #define BW_FTFA_FCCOB2_CCOBn(x, v) (HW_FTFA_FCCOB2_WR(x, v))
mbed_official 324:406fd2029f23 818 /*@}*/
mbed_official 324:406fd2029f23 819
mbed_official 324:406fd2029f23 820 /*******************************************************************************
mbed_official 324:406fd2029f23 821 * HW_FTFA_FCCOB1 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 822 ******************************************************************************/
mbed_official 324:406fd2029f23 823
mbed_official 324:406fd2029f23 824 /*!
mbed_official 324:406fd2029f23 825 * @brief HW_FTFA_FCCOB1 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 826 *
mbed_official 324:406fd2029f23 827 * Reset value: 0x00U
mbed_official 324:406fd2029f23 828 *
mbed_official 324:406fd2029f23 829 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 830 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 831 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 832 */
mbed_official 324:406fd2029f23 833 typedef union _hw_ftfa_fccob1
mbed_official 324:406fd2029f23 834 {
mbed_official 324:406fd2029f23 835 uint8_t U;
mbed_official 324:406fd2029f23 836 struct _hw_ftfa_fccob1_bitfields
mbed_official 324:406fd2029f23 837 {
mbed_official 324:406fd2029f23 838 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 839 } B;
mbed_official 324:406fd2029f23 840 } hw_ftfa_fccob1_t;
mbed_official 324:406fd2029f23 841
mbed_official 324:406fd2029f23 842 /*!
mbed_official 324:406fd2029f23 843 * @name Constants and macros for entire FTFA_FCCOB1 register
mbed_official 324:406fd2029f23 844 */
mbed_official 324:406fd2029f23 845 /*@{*/
mbed_official 324:406fd2029f23 846 #define HW_FTFA_FCCOB1_ADDR(x) ((x) + 0x6U)
mbed_official 324:406fd2029f23 847
mbed_official 324:406fd2029f23 848 #define HW_FTFA_FCCOB1(x) (*(__IO hw_ftfa_fccob1_t *) HW_FTFA_FCCOB1_ADDR(x))
mbed_official 324:406fd2029f23 849 #define HW_FTFA_FCCOB1_RD(x) (HW_FTFA_FCCOB1(x).U)
mbed_official 324:406fd2029f23 850 #define HW_FTFA_FCCOB1_WR(x, v) (HW_FTFA_FCCOB1(x).U = (v))
mbed_official 324:406fd2029f23 851 #define HW_FTFA_FCCOB1_SET(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) | (v)))
mbed_official 324:406fd2029f23 852 #define HW_FTFA_FCCOB1_CLR(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 853 #define HW_FTFA_FCCOB1_TOG(x, v) (HW_FTFA_FCCOB1_WR(x, HW_FTFA_FCCOB1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 854 /*@}*/
mbed_official 324:406fd2029f23 855
mbed_official 324:406fd2029f23 856 /*
mbed_official 324:406fd2029f23 857 * Constants & macros for individual FTFA_FCCOB1 bitfields
mbed_official 324:406fd2029f23 858 */
mbed_official 324:406fd2029f23 859
mbed_official 324:406fd2029f23 860 /*!
mbed_official 324:406fd2029f23 861 * @name Register FTFA_FCCOB1, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 862 *
mbed_official 324:406fd2029f23 863 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 864 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 865 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 866 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 867 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 868 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 869 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 870 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 871 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 872 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 873 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 874 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 875 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 876 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 877 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 878 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 879 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 880 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 881 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 882 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 883 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 884 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 885 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 886 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 887 */
mbed_official 324:406fd2029f23 888 /*@{*/
mbed_official 324:406fd2029f23 889 #define BP_FTFA_FCCOB1_CCOBn (0U) /*!< Bit position for FTFA_FCCOB1_CCOBn. */
mbed_official 324:406fd2029f23 890 #define BM_FTFA_FCCOB1_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB1_CCOBn. */
mbed_official 324:406fd2029f23 891 #define BS_FTFA_FCCOB1_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB1_CCOBn. */
mbed_official 324:406fd2029f23 892
mbed_official 324:406fd2029f23 893 /*! @brief Read current value of the FTFA_FCCOB1_CCOBn field. */
mbed_official 324:406fd2029f23 894 #define BR_FTFA_FCCOB1_CCOBn(x) (HW_FTFA_FCCOB1(x).U)
mbed_official 324:406fd2029f23 895
mbed_official 324:406fd2029f23 896 /*! @brief Format value for bitfield FTFA_FCCOB1_CCOBn. */
mbed_official 324:406fd2029f23 897 #define BF_FTFA_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB1_CCOBn) & BM_FTFA_FCCOB1_CCOBn)
mbed_official 324:406fd2029f23 898
mbed_official 324:406fd2029f23 899 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 900 #define BW_FTFA_FCCOB1_CCOBn(x, v) (HW_FTFA_FCCOB1_WR(x, v))
mbed_official 324:406fd2029f23 901 /*@}*/
mbed_official 324:406fd2029f23 902
mbed_official 324:406fd2029f23 903 /*******************************************************************************
mbed_official 324:406fd2029f23 904 * HW_FTFA_FCCOB0 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 905 ******************************************************************************/
mbed_official 324:406fd2029f23 906
mbed_official 324:406fd2029f23 907 /*!
mbed_official 324:406fd2029f23 908 * @brief HW_FTFA_FCCOB0 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 909 *
mbed_official 324:406fd2029f23 910 * Reset value: 0x00U
mbed_official 324:406fd2029f23 911 *
mbed_official 324:406fd2029f23 912 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 913 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 914 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 915 */
mbed_official 324:406fd2029f23 916 typedef union _hw_ftfa_fccob0
mbed_official 324:406fd2029f23 917 {
mbed_official 324:406fd2029f23 918 uint8_t U;
mbed_official 324:406fd2029f23 919 struct _hw_ftfa_fccob0_bitfields
mbed_official 324:406fd2029f23 920 {
mbed_official 324:406fd2029f23 921 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 922 } B;
mbed_official 324:406fd2029f23 923 } hw_ftfa_fccob0_t;
mbed_official 324:406fd2029f23 924
mbed_official 324:406fd2029f23 925 /*!
mbed_official 324:406fd2029f23 926 * @name Constants and macros for entire FTFA_FCCOB0 register
mbed_official 324:406fd2029f23 927 */
mbed_official 324:406fd2029f23 928 /*@{*/
mbed_official 324:406fd2029f23 929 #define HW_FTFA_FCCOB0_ADDR(x) ((x) + 0x7U)
mbed_official 324:406fd2029f23 930
mbed_official 324:406fd2029f23 931 #define HW_FTFA_FCCOB0(x) (*(__IO hw_ftfa_fccob0_t *) HW_FTFA_FCCOB0_ADDR(x))
mbed_official 324:406fd2029f23 932 #define HW_FTFA_FCCOB0_RD(x) (HW_FTFA_FCCOB0(x).U)
mbed_official 324:406fd2029f23 933 #define HW_FTFA_FCCOB0_WR(x, v) (HW_FTFA_FCCOB0(x).U = (v))
mbed_official 324:406fd2029f23 934 #define HW_FTFA_FCCOB0_SET(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) | (v)))
mbed_official 324:406fd2029f23 935 #define HW_FTFA_FCCOB0_CLR(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 936 #define HW_FTFA_FCCOB0_TOG(x, v) (HW_FTFA_FCCOB0_WR(x, HW_FTFA_FCCOB0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 937 /*@}*/
mbed_official 324:406fd2029f23 938
mbed_official 324:406fd2029f23 939 /*
mbed_official 324:406fd2029f23 940 * Constants & macros for individual FTFA_FCCOB0 bitfields
mbed_official 324:406fd2029f23 941 */
mbed_official 324:406fd2029f23 942
mbed_official 324:406fd2029f23 943 /*!
mbed_official 324:406fd2029f23 944 * @name Register FTFA_FCCOB0, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 945 *
mbed_official 324:406fd2029f23 946 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 947 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 948 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 949 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 950 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 951 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 952 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 953 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 954 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 955 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 956 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 957 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 958 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 959 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 960 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 961 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 962 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 963 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 964 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 965 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 966 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 967 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 968 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 969 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 970 */
mbed_official 324:406fd2029f23 971 /*@{*/
mbed_official 324:406fd2029f23 972 #define BP_FTFA_FCCOB0_CCOBn (0U) /*!< Bit position for FTFA_FCCOB0_CCOBn. */
mbed_official 324:406fd2029f23 973 #define BM_FTFA_FCCOB0_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB0_CCOBn. */
mbed_official 324:406fd2029f23 974 #define BS_FTFA_FCCOB0_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB0_CCOBn. */
mbed_official 324:406fd2029f23 975
mbed_official 324:406fd2029f23 976 /*! @brief Read current value of the FTFA_FCCOB0_CCOBn field. */
mbed_official 324:406fd2029f23 977 #define BR_FTFA_FCCOB0_CCOBn(x) (HW_FTFA_FCCOB0(x).U)
mbed_official 324:406fd2029f23 978
mbed_official 324:406fd2029f23 979 /*! @brief Format value for bitfield FTFA_FCCOB0_CCOBn. */
mbed_official 324:406fd2029f23 980 #define BF_FTFA_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB0_CCOBn) & BM_FTFA_FCCOB0_CCOBn)
mbed_official 324:406fd2029f23 981
mbed_official 324:406fd2029f23 982 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 983 #define BW_FTFA_FCCOB0_CCOBn(x, v) (HW_FTFA_FCCOB0_WR(x, v))
mbed_official 324:406fd2029f23 984 /*@}*/
mbed_official 324:406fd2029f23 985
mbed_official 324:406fd2029f23 986 /*******************************************************************************
mbed_official 324:406fd2029f23 987 * HW_FTFA_FCCOB7 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 988 ******************************************************************************/
mbed_official 324:406fd2029f23 989
mbed_official 324:406fd2029f23 990 /*!
mbed_official 324:406fd2029f23 991 * @brief HW_FTFA_FCCOB7 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 992 *
mbed_official 324:406fd2029f23 993 * Reset value: 0x00U
mbed_official 324:406fd2029f23 994 *
mbed_official 324:406fd2029f23 995 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 996 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 997 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 998 */
mbed_official 324:406fd2029f23 999 typedef union _hw_ftfa_fccob7
mbed_official 324:406fd2029f23 1000 {
mbed_official 324:406fd2029f23 1001 uint8_t U;
mbed_official 324:406fd2029f23 1002 struct _hw_ftfa_fccob7_bitfields
mbed_official 324:406fd2029f23 1003 {
mbed_official 324:406fd2029f23 1004 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1005 } B;
mbed_official 324:406fd2029f23 1006 } hw_ftfa_fccob7_t;
mbed_official 324:406fd2029f23 1007
mbed_official 324:406fd2029f23 1008 /*!
mbed_official 324:406fd2029f23 1009 * @name Constants and macros for entire FTFA_FCCOB7 register
mbed_official 324:406fd2029f23 1010 */
mbed_official 324:406fd2029f23 1011 /*@{*/
mbed_official 324:406fd2029f23 1012 #define HW_FTFA_FCCOB7_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 1013
mbed_official 324:406fd2029f23 1014 #define HW_FTFA_FCCOB7(x) (*(__IO hw_ftfa_fccob7_t *) HW_FTFA_FCCOB7_ADDR(x))
mbed_official 324:406fd2029f23 1015 #define HW_FTFA_FCCOB7_RD(x) (HW_FTFA_FCCOB7(x).U)
mbed_official 324:406fd2029f23 1016 #define HW_FTFA_FCCOB7_WR(x, v) (HW_FTFA_FCCOB7(x).U = (v))
mbed_official 324:406fd2029f23 1017 #define HW_FTFA_FCCOB7_SET(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) | (v)))
mbed_official 324:406fd2029f23 1018 #define HW_FTFA_FCCOB7_CLR(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1019 #define HW_FTFA_FCCOB7_TOG(x, v) (HW_FTFA_FCCOB7_WR(x, HW_FTFA_FCCOB7_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1020 /*@}*/
mbed_official 324:406fd2029f23 1021
mbed_official 324:406fd2029f23 1022 /*
mbed_official 324:406fd2029f23 1023 * Constants & macros for individual FTFA_FCCOB7 bitfields
mbed_official 324:406fd2029f23 1024 */
mbed_official 324:406fd2029f23 1025
mbed_official 324:406fd2029f23 1026 /*!
mbed_official 324:406fd2029f23 1027 * @name Register FTFA_FCCOB7, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1028 *
mbed_official 324:406fd2029f23 1029 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1030 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1031 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1032 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1033 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1034 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1035 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1036 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1037 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1038 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1039 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1040 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1041 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1042 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1043 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1044 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1045 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1046 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1047 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1048 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1049 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1050 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1051 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1052 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1053 */
mbed_official 324:406fd2029f23 1054 /*@{*/
mbed_official 324:406fd2029f23 1055 #define BP_FTFA_FCCOB7_CCOBn (0U) /*!< Bit position for FTFA_FCCOB7_CCOBn. */
mbed_official 324:406fd2029f23 1056 #define BM_FTFA_FCCOB7_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB7_CCOBn. */
mbed_official 324:406fd2029f23 1057 #define BS_FTFA_FCCOB7_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB7_CCOBn. */
mbed_official 324:406fd2029f23 1058
mbed_official 324:406fd2029f23 1059 /*! @brief Read current value of the FTFA_FCCOB7_CCOBn field. */
mbed_official 324:406fd2029f23 1060 #define BR_FTFA_FCCOB7_CCOBn(x) (HW_FTFA_FCCOB7(x).U)
mbed_official 324:406fd2029f23 1061
mbed_official 324:406fd2029f23 1062 /*! @brief Format value for bitfield FTFA_FCCOB7_CCOBn. */
mbed_official 324:406fd2029f23 1063 #define BF_FTFA_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB7_CCOBn) & BM_FTFA_FCCOB7_CCOBn)
mbed_official 324:406fd2029f23 1064
mbed_official 324:406fd2029f23 1065 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1066 #define BW_FTFA_FCCOB7_CCOBn(x, v) (HW_FTFA_FCCOB7_WR(x, v))
mbed_official 324:406fd2029f23 1067 /*@}*/
mbed_official 324:406fd2029f23 1068
mbed_official 324:406fd2029f23 1069 /*******************************************************************************
mbed_official 324:406fd2029f23 1070 * HW_FTFA_FCCOB6 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1071 ******************************************************************************/
mbed_official 324:406fd2029f23 1072
mbed_official 324:406fd2029f23 1073 /*!
mbed_official 324:406fd2029f23 1074 * @brief HW_FTFA_FCCOB6 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1075 *
mbed_official 324:406fd2029f23 1076 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1077 *
mbed_official 324:406fd2029f23 1078 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1079 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1080 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1081 */
mbed_official 324:406fd2029f23 1082 typedef union _hw_ftfa_fccob6
mbed_official 324:406fd2029f23 1083 {
mbed_official 324:406fd2029f23 1084 uint8_t U;
mbed_official 324:406fd2029f23 1085 struct _hw_ftfa_fccob6_bitfields
mbed_official 324:406fd2029f23 1086 {
mbed_official 324:406fd2029f23 1087 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1088 } B;
mbed_official 324:406fd2029f23 1089 } hw_ftfa_fccob6_t;
mbed_official 324:406fd2029f23 1090
mbed_official 324:406fd2029f23 1091 /*!
mbed_official 324:406fd2029f23 1092 * @name Constants and macros for entire FTFA_FCCOB6 register
mbed_official 324:406fd2029f23 1093 */
mbed_official 324:406fd2029f23 1094 /*@{*/
mbed_official 324:406fd2029f23 1095 #define HW_FTFA_FCCOB6_ADDR(x) ((x) + 0x9U)
mbed_official 324:406fd2029f23 1096
mbed_official 324:406fd2029f23 1097 #define HW_FTFA_FCCOB6(x) (*(__IO hw_ftfa_fccob6_t *) HW_FTFA_FCCOB6_ADDR(x))
mbed_official 324:406fd2029f23 1098 #define HW_FTFA_FCCOB6_RD(x) (HW_FTFA_FCCOB6(x).U)
mbed_official 324:406fd2029f23 1099 #define HW_FTFA_FCCOB6_WR(x, v) (HW_FTFA_FCCOB6(x).U = (v))
mbed_official 324:406fd2029f23 1100 #define HW_FTFA_FCCOB6_SET(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) | (v)))
mbed_official 324:406fd2029f23 1101 #define HW_FTFA_FCCOB6_CLR(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1102 #define HW_FTFA_FCCOB6_TOG(x, v) (HW_FTFA_FCCOB6_WR(x, HW_FTFA_FCCOB6_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1103 /*@}*/
mbed_official 324:406fd2029f23 1104
mbed_official 324:406fd2029f23 1105 /*
mbed_official 324:406fd2029f23 1106 * Constants & macros for individual FTFA_FCCOB6 bitfields
mbed_official 324:406fd2029f23 1107 */
mbed_official 324:406fd2029f23 1108
mbed_official 324:406fd2029f23 1109 /*!
mbed_official 324:406fd2029f23 1110 * @name Register FTFA_FCCOB6, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1111 *
mbed_official 324:406fd2029f23 1112 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1113 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1114 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1115 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1116 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1117 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1118 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1119 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1120 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1121 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1122 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1123 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1124 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1125 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1126 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1127 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1128 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1129 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1130 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1131 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1132 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1133 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1134 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1135 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1136 */
mbed_official 324:406fd2029f23 1137 /*@{*/
mbed_official 324:406fd2029f23 1138 #define BP_FTFA_FCCOB6_CCOBn (0U) /*!< Bit position for FTFA_FCCOB6_CCOBn. */
mbed_official 324:406fd2029f23 1139 #define BM_FTFA_FCCOB6_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB6_CCOBn. */
mbed_official 324:406fd2029f23 1140 #define BS_FTFA_FCCOB6_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB6_CCOBn. */
mbed_official 324:406fd2029f23 1141
mbed_official 324:406fd2029f23 1142 /*! @brief Read current value of the FTFA_FCCOB6_CCOBn field. */
mbed_official 324:406fd2029f23 1143 #define BR_FTFA_FCCOB6_CCOBn(x) (HW_FTFA_FCCOB6(x).U)
mbed_official 324:406fd2029f23 1144
mbed_official 324:406fd2029f23 1145 /*! @brief Format value for bitfield FTFA_FCCOB6_CCOBn. */
mbed_official 324:406fd2029f23 1146 #define BF_FTFA_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB6_CCOBn) & BM_FTFA_FCCOB6_CCOBn)
mbed_official 324:406fd2029f23 1147
mbed_official 324:406fd2029f23 1148 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1149 #define BW_FTFA_FCCOB6_CCOBn(x, v) (HW_FTFA_FCCOB6_WR(x, v))
mbed_official 324:406fd2029f23 1150 /*@}*/
mbed_official 324:406fd2029f23 1151
mbed_official 324:406fd2029f23 1152 /*******************************************************************************
mbed_official 324:406fd2029f23 1153 * HW_FTFA_FCCOB5 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1154 ******************************************************************************/
mbed_official 324:406fd2029f23 1155
mbed_official 324:406fd2029f23 1156 /*!
mbed_official 324:406fd2029f23 1157 * @brief HW_FTFA_FCCOB5 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1158 *
mbed_official 324:406fd2029f23 1159 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1160 *
mbed_official 324:406fd2029f23 1161 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1162 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1163 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1164 */
mbed_official 324:406fd2029f23 1165 typedef union _hw_ftfa_fccob5
mbed_official 324:406fd2029f23 1166 {
mbed_official 324:406fd2029f23 1167 uint8_t U;
mbed_official 324:406fd2029f23 1168 struct _hw_ftfa_fccob5_bitfields
mbed_official 324:406fd2029f23 1169 {
mbed_official 324:406fd2029f23 1170 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1171 } B;
mbed_official 324:406fd2029f23 1172 } hw_ftfa_fccob5_t;
mbed_official 324:406fd2029f23 1173
mbed_official 324:406fd2029f23 1174 /*!
mbed_official 324:406fd2029f23 1175 * @name Constants and macros for entire FTFA_FCCOB5 register
mbed_official 324:406fd2029f23 1176 */
mbed_official 324:406fd2029f23 1177 /*@{*/
mbed_official 324:406fd2029f23 1178 #define HW_FTFA_FCCOB5_ADDR(x) ((x) + 0xAU)
mbed_official 324:406fd2029f23 1179
mbed_official 324:406fd2029f23 1180 #define HW_FTFA_FCCOB5(x) (*(__IO hw_ftfa_fccob5_t *) HW_FTFA_FCCOB5_ADDR(x))
mbed_official 324:406fd2029f23 1181 #define HW_FTFA_FCCOB5_RD(x) (HW_FTFA_FCCOB5(x).U)
mbed_official 324:406fd2029f23 1182 #define HW_FTFA_FCCOB5_WR(x, v) (HW_FTFA_FCCOB5(x).U = (v))
mbed_official 324:406fd2029f23 1183 #define HW_FTFA_FCCOB5_SET(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) | (v)))
mbed_official 324:406fd2029f23 1184 #define HW_FTFA_FCCOB5_CLR(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1185 #define HW_FTFA_FCCOB5_TOG(x, v) (HW_FTFA_FCCOB5_WR(x, HW_FTFA_FCCOB5_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1186 /*@}*/
mbed_official 324:406fd2029f23 1187
mbed_official 324:406fd2029f23 1188 /*
mbed_official 324:406fd2029f23 1189 * Constants & macros for individual FTFA_FCCOB5 bitfields
mbed_official 324:406fd2029f23 1190 */
mbed_official 324:406fd2029f23 1191
mbed_official 324:406fd2029f23 1192 /*!
mbed_official 324:406fd2029f23 1193 * @name Register FTFA_FCCOB5, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1194 *
mbed_official 324:406fd2029f23 1195 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1196 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1197 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1198 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1199 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1200 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1201 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1202 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1203 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1204 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1205 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1206 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1207 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1208 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1209 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1210 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1211 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1212 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1213 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1214 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1215 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1216 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1217 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1218 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1219 */
mbed_official 324:406fd2029f23 1220 /*@{*/
mbed_official 324:406fd2029f23 1221 #define BP_FTFA_FCCOB5_CCOBn (0U) /*!< Bit position for FTFA_FCCOB5_CCOBn. */
mbed_official 324:406fd2029f23 1222 #define BM_FTFA_FCCOB5_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB5_CCOBn. */
mbed_official 324:406fd2029f23 1223 #define BS_FTFA_FCCOB5_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB5_CCOBn. */
mbed_official 324:406fd2029f23 1224
mbed_official 324:406fd2029f23 1225 /*! @brief Read current value of the FTFA_FCCOB5_CCOBn field. */
mbed_official 324:406fd2029f23 1226 #define BR_FTFA_FCCOB5_CCOBn(x) (HW_FTFA_FCCOB5(x).U)
mbed_official 324:406fd2029f23 1227
mbed_official 324:406fd2029f23 1228 /*! @brief Format value for bitfield FTFA_FCCOB5_CCOBn. */
mbed_official 324:406fd2029f23 1229 #define BF_FTFA_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB5_CCOBn) & BM_FTFA_FCCOB5_CCOBn)
mbed_official 324:406fd2029f23 1230
mbed_official 324:406fd2029f23 1231 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1232 #define BW_FTFA_FCCOB5_CCOBn(x, v) (HW_FTFA_FCCOB5_WR(x, v))
mbed_official 324:406fd2029f23 1233 /*@}*/
mbed_official 324:406fd2029f23 1234
mbed_official 324:406fd2029f23 1235 /*******************************************************************************
mbed_official 324:406fd2029f23 1236 * HW_FTFA_FCCOB4 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1237 ******************************************************************************/
mbed_official 324:406fd2029f23 1238
mbed_official 324:406fd2029f23 1239 /*!
mbed_official 324:406fd2029f23 1240 * @brief HW_FTFA_FCCOB4 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1241 *
mbed_official 324:406fd2029f23 1242 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1243 *
mbed_official 324:406fd2029f23 1244 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1245 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1246 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1247 */
mbed_official 324:406fd2029f23 1248 typedef union _hw_ftfa_fccob4
mbed_official 324:406fd2029f23 1249 {
mbed_official 324:406fd2029f23 1250 uint8_t U;
mbed_official 324:406fd2029f23 1251 struct _hw_ftfa_fccob4_bitfields
mbed_official 324:406fd2029f23 1252 {
mbed_official 324:406fd2029f23 1253 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1254 } B;
mbed_official 324:406fd2029f23 1255 } hw_ftfa_fccob4_t;
mbed_official 324:406fd2029f23 1256
mbed_official 324:406fd2029f23 1257 /*!
mbed_official 324:406fd2029f23 1258 * @name Constants and macros for entire FTFA_FCCOB4 register
mbed_official 324:406fd2029f23 1259 */
mbed_official 324:406fd2029f23 1260 /*@{*/
mbed_official 324:406fd2029f23 1261 #define HW_FTFA_FCCOB4_ADDR(x) ((x) + 0xBU)
mbed_official 324:406fd2029f23 1262
mbed_official 324:406fd2029f23 1263 #define HW_FTFA_FCCOB4(x) (*(__IO hw_ftfa_fccob4_t *) HW_FTFA_FCCOB4_ADDR(x))
mbed_official 324:406fd2029f23 1264 #define HW_FTFA_FCCOB4_RD(x) (HW_FTFA_FCCOB4(x).U)
mbed_official 324:406fd2029f23 1265 #define HW_FTFA_FCCOB4_WR(x, v) (HW_FTFA_FCCOB4(x).U = (v))
mbed_official 324:406fd2029f23 1266 #define HW_FTFA_FCCOB4_SET(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) | (v)))
mbed_official 324:406fd2029f23 1267 #define HW_FTFA_FCCOB4_CLR(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1268 #define HW_FTFA_FCCOB4_TOG(x, v) (HW_FTFA_FCCOB4_WR(x, HW_FTFA_FCCOB4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1269 /*@}*/
mbed_official 324:406fd2029f23 1270
mbed_official 324:406fd2029f23 1271 /*
mbed_official 324:406fd2029f23 1272 * Constants & macros for individual FTFA_FCCOB4 bitfields
mbed_official 324:406fd2029f23 1273 */
mbed_official 324:406fd2029f23 1274
mbed_official 324:406fd2029f23 1275 /*!
mbed_official 324:406fd2029f23 1276 * @name Register FTFA_FCCOB4, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1277 *
mbed_official 324:406fd2029f23 1278 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1279 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1280 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1281 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1282 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1283 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1284 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1285 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1286 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1287 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1288 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1289 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1290 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1291 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1292 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1293 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1294 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1295 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1296 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1297 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1298 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1299 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1300 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1301 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1302 */
mbed_official 324:406fd2029f23 1303 /*@{*/
mbed_official 324:406fd2029f23 1304 #define BP_FTFA_FCCOB4_CCOBn (0U) /*!< Bit position for FTFA_FCCOB4_CCOBn. */
mbed_official 324:406fd2029f23 1305 #define BM_FTFA_FCCOB4_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB4_CCOBn. */
mbed_official 324:406fd2029f23 1306 #define BS_FTFA_FCCOB4_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB4_CCOBn. */
mbed_official 324:406fd2029f23 1307
mbed_official 324:406fd2029f23 1308 /*! @brief Read current value of the FTFA_FCCOB4_CCOBn field. */
mbed_official 324:406fd2029f23 1309 #define BR_FTFA_FCCOB4_CCOBn(x) (HW_FTFA_FCCOB4(x).U)
mbed_official 324:406fd2029f23 1310
mbed_official 324:406fd2029f23 1311 /*! @brief Format value for bitfield FTFA_FCCOB4_CCOBn. */
mbed_official 324:406fd2029f23 1312 #define BF_FTFA_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB4_CCOBn) & BM_FTFA_FCCOB4_CCOBn)
mbed_official 324:406fd2029f23 1313
mbed_official 324:406fd2029f23 1314 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1315 #define BW_FTFA_FCCOB4_CCOBn(x, v) (HW_FTFA_FCCOB4_WR(x, v))
mbed_official 324:406fd2029f23 1316 /*@}*/
mbed_official 324:406fd2029f23 1317
mbed_official 324:406fd2029f23 1318 /*******************************************************************************
mbed_official 324:406fd2029f23 1319 * HW_FTFA_FCCOBB - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1320 ******************************************************************************/
mbed_official 324:406fd2029f23 1321
mbed_official 324:406fd2029f23 1322 /*!
mbed_official 324:406fd2029f23 1323 * @brief HW_FTFA_FCCOBB - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1324 *
mbed_official 324:406fd2029f23 1325 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1326 *
mbed_official 324:406fd2029f23 1327 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1328 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1329 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1330 */
mbed_official 324:406fd2029f23 1331 typedef union _hw_ftfa_fccobb
mbed_official 324:406fd2029f23 1332 {
mbed_official 324:406fd2029f23 1333 uint8_t U;
mbed_official 324:406fd2029f23 1334 struct _hw_ftfa_fccobb_bitfields
mbed_official 324:406fd2029f23 1335 {
mbed_official 324:406fd2029f23 1336 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1337 } B;
mbed_official 324:406fd2029f23 1338 } hw_ftfa_fccobb_t;
mbed_official 324:406fd2029f23 1339
mbed_official 324:406fd2029f23 1340 /*!
mbed_official 324:406fd2029f23 1341 * @name Constants and macros for entire FTFA_FCCOBB register
mbed_official 324:406fd2029f23 1342 */
mbed_official 324:406fd2029f23 1343 /*@{*/
mbed_official 324:406fd2029f23 1344 #define HW_FTFA_FCCOBB_ADDR(x) ((x) + 0xCU)
mbed_official 324:406fd2029f23 1345
mbed_official 324:406fd2029f23 1346 #define HW_FTFA_FCCOBB(x) (*(__IO hw_ftfa_fccobb_t *) HW_FTFA_FCCOBB_ADDR(x))
mbed_official 324:406fd2029f23 1347 #define HW_FTFA_FCCOBB_RD(x) (HW_FTFA_FCCOBB(x).U)
mbed_official 324:406fd2029f23 1348 #define HW_FTFA_FCCOBB_WR(x, v) (HW_FTFA_FCCOBB(x).U = (v))
mbed_official 324:406fd2029f23 1349 #define HW_FTFA_FCCOBB_SET(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) | (v)))
mbed_official 324:406fd2029f23 1350 #define HW_FTFA_FCCOBB_CLR(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1351 #define HW_FTFA_FCCOBB_TOG(x, v) (HW_FTFA_FCCOBB_WR(x, HW_FTFA_FCCOBB_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1352 /*@}*/
mbed_official 324:406fd2029f23 1353
mbed_official 324:406fd2029f23 1354 /*
mbed_official 324:406fd2029f23 1355 * Constants & macros for individual FTFA_FCCOBB bitfields
mbed_official 324:406fd2029f23 1356 */
mbed_official 324:406fd2029f23 1357
mbed_official 324:406fd2029f23 1358 /*!
mbed_official 324:406fd2029f23 1359 * @name Register FTFA_FCCOBB, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1360 *
mbed_official 324:406fd2029f23 1361 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1362 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1363 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1364 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1365 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1366 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1367 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1368 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1369 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1370 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1371 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1372 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1373 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1374 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1375 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1376 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1377 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1378 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1379 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1380 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1381 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1382 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1383 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1384 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1385 */
mbed_official 324:406fd2029f23 1386 /*@{*/
mbed_official 324:406fd2029f23 1387 #define BP_FTFA_FCCOBB_CCOBn (0U) /*!< Bit position for FTFA_FCCOBB_CCOBn. */
mbed_official 324:406fd2029f23 1388 #define BM_FTFA_FCCOBB_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBB_CCOBn. */
mbed_official 324:406fd2029f23 1389 #define BS_FTFA_FCCOBB_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBB_CCOBn. */
mbed_official 324:406fd2029f23 1390
mbed_official 324:406fd2029f23 1391 /*! @brief Read current value of the FTFA_FCCOBB_CCOBn field. */
mbed_official 324:406fd2029f23 1392 #define BR_FTFA_FCCOBB_CCOBn(x) (HW_FTFA_FCCOBB(x).U)
mbed_official 324:406fd2029f23 1393
mbed_official 324:406fd2029f23 1394 /*! @brief Format value for bitfield FTFA_FCCOBB_CCOBn. */
mbed_official 324:406fd2029f23 1395 #define BF_FTFA_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBB_CCOBn) & BM_FTFA_FCCOBB_CCOBn)
mbed_official 324:406fd2029f23 1396
mbed_official 324:406fd2029f23 1397 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1398 #define BW_FTFA_FCCOBB_CCOBn(x, v) (HW_FTFA_FCCOBB_WR(x, v))
mbed_official 324:406fd2029f23 1399 /*@}*/
mbed_official 324:406fd2029f23 1400
mbed_official 324:406fd2029f23 1401 /*******************************************************************************
mbed_official 324:406fd2029f23 1402 * HW_FTFA_FCCOBA - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1403 ******************************************************************************/
mbed_official 324:406fd2029f23 1404
mbed_official 324:406fd2029f23 1405 /*!
mbed_official 324:406fd2029f23 1406 * @brief HW_FTFA_FCCOBA - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1407 *
mbed_official 324:406fd2029f23 1408 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1409 *
mbed_official 324:406fd2029f23 1410 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1411 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1412 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1413 */
mbed_official 324:406fd2029f23 1414 typedef union _hw_ftfa_fccoba
mbed_official 324:406fd2029f23 1415 {
mbed_official 324:406fd2029f23 1416 uint8_t U;
mbed_official 324:406fd2029f23 1417 struct _hw_ftfa_fccoba_bitfields
mbed_official 324:406fd2029f23 1418 {
mbed_official 324:406fd2029f23 1419 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1420 } B;
mbed_official 324:406fd2029f23 1421 } hw_ftfa_fccoba_t;
mbed_official 324:406fd2029f23 1422
mbed_official 324:406fd2029f23 1423 /*!
mbed_official 324:406fd2029f23 1424 * @name Constants and macros for entire FTFA_FCCOBA register
mbed_official 324:406fd2029f23 1425 */
mbed_official 324:406fd2029f23 1426 /*@{*/
mbed_official 324:406fd2029f23 1427 #define HW_FTFA_FCCOBA_ADDR(x) ((x) + 0xDU)
mbed_official 324:406fd2029f23 1428
mbed_official 324:406fd2029f23 1429 #define HW_FTFA_FCCOBA(x) (*(__IO hw_ftfa_fccoba_t *) HW_FTFA_FCCOBA_ADDR(x))
mbed_official 324:406fd2029f23 1430 #define HW_FTFA_FCCOBA_RD(x) (HW_FTFA_FCCOBA(x).U)
mbed_official 324:406fd2029f23 1431 #define HW_FTFA_FCCOBA_WR(x, v) (HW_FTFA_FCCOBA(x).U = (v))
mbed_official 324:406fd2029f23 1432 #define HW_FTFA_FCCOBA_SET(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) | (v)))
mbed_official 324:406fd2029f23 1433 #define HW_FTFA_FCCOBA_CLR(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1434 #define HW_FTFA_FCCOBA_TOG(x, v) (HW_FTFA_FCCOBA_WR(x, HW_FTFA_FCCOBA_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1435 /*@}*/
mbed_official 324:406fd2029f23 1436
mbed_official 324:406fd2029f23 1437 /*
mbed_official 324:406fd2029f23 1438 * Constants & macros for individual FTFA_FCCOBA bitfields
mbed_official 324:406fd2029f23 1439 */
mbed_official 324:406fd2029f23 1440
mbed_official 324:406fd2029f23 1441 /*!
mbed_official 324:406fd2029f23 1442 * @name Register FTFA_FCCOBA, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1443 *
mbed_official 324:406fd2029f23 1444 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1445 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1446 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1447 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1448 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1449 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1450 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1451 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1452 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1453 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1454 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1455 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1456 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1457 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1458 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1459 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1460 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1461 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1462 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1463 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1464 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1465 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1466 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1467 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1468 */
mbed_official 324:406fd2029f23 1469 /*@{*/
mbed_official 324:406fd2029f23 1470 #define BP_FTFA_FCCOBA_CCOBn (0U) /*!< Bit position for FTFA_FCCOBA_CCOBn. */
mbed_official 324:406fd2029f23 1471 #define BM_FTFA_FCCOBA_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOBA_CCOBn. */
mbed_official 324:406fd2029f23 1472 #define BS_FTFA_FCCOBA_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOBA_CCOBn. */
mbed_official 324:406fd2029f23 1473
mbed_official 324:406fd2029f23 1474 /*! @brief Read current value of the FTFA_FCCOBA_CCOBn field. */
mbed_official 324:406fd2029f23 1475 #define BR_FTFA_FCCOBA_CCOBn(x) (HW_FTFA_FCCOBA(x).U)
mbed_official 324:406fd2029f23 1476
mbed_official 324:406fd2029f23 1477 /*! @brief Format value for bitfield FTFA_FCCOBA_CCOBn. */
mbed_official 324:406fd2029f23 1478 #define BF_FTFA_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOBA_CCOBn) & BM_FTFA_FCCOBA_CCOBn)
mbed_official 324:406fd2029f23 1479
mbed_official 324:406fd2029f23 1480 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1481 #define BW_FTFA_FCCOBA_CCOBn(x, v) (HW_FTFA_FCCOBA_WR(x, v))
mbed_official 324:406fd2029f23 1482 /*@}*/
mbed_official 324:406fd2029f23 1483
mbed_official 324:406fd2029f23 1484 /*******************************************************************************
mbed_official 324:406fd2029f23 1485 * HW_FTFA_FCCOB9 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1486 ******************************************************************************/
mbed_official 324:406fd2029f23 1487
mbed_official 324:406fd2029f23 1488 /*!
mbed_official 324:406fd2029f23 1489 * @brief HW_FTFA_FCCOB9 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1490 *
mbed_official 324:406fd2029f23 1491 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1492 *
mbed_official 324:406fd2029f23 1493 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1494 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1495 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1496 */
mbed_official 324:406fd2029f23 1497 typedef union _hw_ftfa_fccob9
mbed_official 324:406fd2029f23 1498 {
mbed_official 324:406fd2029f23 1499 uint8_t U;
mbed_official 324:406fd2029f23 1500 struct _hw_ftfa_fccob9_bitfields
mbed_official 324:406fd2029f23 1501 {
mbed_official 324:406fd2029f23 1502 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1503 } B;
mbed_official 324:406fd2029f23 1504 } hw_ftfa_fccob9_t;
mbed_official 324:406fd2029f23 1505
mbed_official 324:406fd2029f23 1506 /*!
mbed_official 324:406fd2029f23 1507 * @name Constants and macros for entire FTFA_FCCOB9 register
mbed_official 324:406fd2029f23 1508 */
mbed_official 324:406fd2029f23 1509 /*@{*/
mbed_official 324:406fd2029f23 1510 #define HW_FTFA_FCCOB9_ADDR(x) ((x) + 0xEU)
mbed_official 324:406fd2029f23 1511
mbed_official 324:406fd2029f23 1512 #define HW_FTFA_FCCOB9(x) (*(__IO hw_ftfa_fccob9_t *) HW_FTFA_FCCOB9_ADDR(x))
mbed_official 324:406fd2029f23 1513 #define HW_FTFA_FCCOB9_RD(x) (HW_FTFA_FCCOB9(x).U)
mbed_official 324:406fd2029f23 1514 #define HW_FTFA_FCCOB9_WR(x, v) (HW_FTFA_FCCOB9(x).U = (v))
mbed_official 324:406fd2029f23 1515 #define HW_FTFA_FCCOB9_SET(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) | (v)))
mbed_official 324:406fd2029f23 1516 #define HW_FTFA_FCCOB9_CLR(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1517 #define HW_FTFA_FCCOB9_TOG(x, v) (HW_FTFA_FCCOB9_WR(x, HW_FTFA_FCCOB9_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1518 /*@}*/
mbed_official 324:406fd2029f23 1519
mbed_official 324:406fd2029f23 1520 /*
mbed_official 324:406fd2029f23 1521 * Constants & macros for individual FTFA_FCCOB9 bitfields
mbed_official 324:406fd2029f23 1522 */
mbed_official 324:406fd2029f23 1523
mbed_official 324:406fd2029f23 1524 /*!
mbed_official 324:406fd2029f23 1525 * @name Register FTFA_FCCOB9, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1526 *
mbed_official 324:406fd2029f23 1527 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1528 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1529 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1530 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1531 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1532 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1533 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1534 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1535 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1536 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1537 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1538 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1539 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1540 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1541 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1542 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1543 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1544 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1545 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1546 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1547 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1548 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1549 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1550 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1551 */
mbed_official 324:406fd2029f23 1552 /*@{*/
mbed_official 324:406fd2029f23 1553 #define BP_FTFA_FCCOB9_CCOBn (0U) /*!< Bit position for FTFA_FCCOB9_CCOBn. */
mbed_official 324:406fd2029f23 1554 #define BM_FTFA_FCCOB9_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB9_CCOBn. */
mbed_official 324:406fd2029f23 1555 #define BS_FTFA_FCCOB9_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB9_CCOBn. */
mbed_official 324:406fd2029f23 1556
mbed_official 324:406fd2029f23 1557 /*! @brief Read current value of the FTFA_FCCOB9_CCOBn field. */
mbed_official 324:406fd2029f23 1558 #define BR_FTFA_FCCOB9_CCOBn(x) (HW_FTFA_FCCOB9(x).U)
mbed_official 324:406fd2029f23 1559
mbed_official 324:406fd2029f23 1560 /*! @brief Format value for bitfield FTFA_FCCOB9_CCOBn. */
mbed_official 324:406fd2029f23 1561 #define BF_FTFA_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB9_CCOBn) & BM_FTFA_FCCOB9_CCOBn)
mbed_official 324:406fd2029f23 1562
mbed_official 324:406fd2029f23 1563 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1564 #define BW_FTFA_FCCOB9_CCOBn(x, v) (HW_FTFA_FCCOB9_WR(x, v))
mbed_official 324:406fd2029f23 1565 /*@}*/
mbed_official 324:406fd2029f23 1566
mbed_official 324:406fd2029f23 1567 /*******************************************************************************
mbed_official 324:406fd2029f23 1568 * HW_FTFA_FCCOB8 - Flash Common Command Object Registers
mbed_official 324:406fd2029f23 1569 ******************************************************************************/
mbed_official 324:406fd2029f23 1570
mbed_official 324:406fd2029f23 1571 /*!
mbed_official 324:406fd2029f23 1572 * @brief HW_FTFA_FCCOB8 - Flash Common Command Object Registers (RW)
mbed_official 324:406fd2029f23 1573 *
mbed_official 324:406fd2029f23 1574 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1575 *
mbed_official 324:406fd2029f23 1576 * The FCCOB register group provides 12 bytes for command codes and parameters.
mbed_official 324:406fd2029f23 1577 * The individual bytes within the set append a 0-B hex identifier to the FCCOB
mbed_official 324:406fd2029f23 1578 * register name: FCCOB0, FCCOB1, ..., FCCOBB.
mbed_official 324:406fd2029f23 1579 */
mbed_official 324:406fd2029f23 1580 typedef union _hw_ftfa_fccob8
mbed_official 324:406fd2029f23 1581 {
mbed_official 324:406fd2029f23 1582 uint8_t U;
mbed_official 324:406fd2029f23 1583 struct _hw_ftfa_fccob8_bitfields
mbed_official 324:406fd2029f23 1584 {
mbed_official 324:406fd2029f23 1585 uint8_t CCOBn : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1586 } B;
mbed_official 324:406fd2029f23 1587 } hw_ftfa_fccob8_t;
mbed_official 324:406fd2029f23 1588
mbed_official 324:406fd2029f23 1589 /*!
mbed_official 324:406fd2029f23 1590 * @name Constants and macros for entire FTFA_FCCOB8 register
mbed_official 324:406fd2029f23 1591 */
mbed_official 324:406fd2029f23 1592 /*@{*/
mbed_official 324:406fd2029f23 1593 #define HW_FTFA_FCCOB8_ADDR(x) ((x) + 0xFU)
mbed_official 324:406fd2029f23 1594
mbed_official 324:406fd2029f23 1595 #define HW_FTFA_FCCOB8(x) (*(__IO hw_ftfa_fccob8_t *) HW_FTFA_FCCOB8_ADDR(x))
mbed_official 324:406fd2029f23 1596 #define HW_FTFA_FCCOB8_RD(x) (HW_FTFA_FCCOB8(x).U)
mbed_official 324:406fd2029f23 1597 #define HW_FTFA_FCCOB8_WR(x, v) (HW_FTFA_FCCOB8(x).U = (v))
mbed_official 324:406fd2029f23 1598 #define HW_FTFA_FCCOB8_SET(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) | (v)))
mbed_official 324:406fd2029f23 1599 #define HW_FTFA_FCCOB8_CLR(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1600 #define HW_FTFA_FCCOB8_TOG(x, v) (HW_FTFA_FCCOB8_WR(x, HW_FTFA_FCCOB8_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1601 /*@}*/
mbed_official 324:406fd2029f23 1602
mbed_official 324:406fd2029f23 1603 /*
mbed_official 324:406fd2029f23 1604 * Constants & macros for individual FTFA_FCCOB8 bitfields
mbed_official 324:406fd2029f23 1605 */
mbed_official 324:406fd2029f23 1606
mbed_official 324:406fd2029f23 1607 /*!
mbed_official 324:406fd2029f23 1608 * @name Register FTFA_FCCOB8, field CCOBn[7:0] (RW)
mbed_official 324:406fd2029f23 1609 *
mbed_official 324:406fd2029f23 1610 * The FCCOB register provides a command code and relevant parameters to the
mbed_official 324:406fd2029f23 1611 * memory controller. The individual registers that compose the FCCOB data set can
mbed_official 324:406fd2029f23 1612 * be written in any order, but you must provide all needed values, which vary
mbed_official 324:406fd2029f23 1613 * from command to command. First, set up all required FCCOB fields and then
mbed_official 324:406fd2029f23 1614 * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
mbed_official 324:406fd2029f23 1615 * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
mbed_official 324:406fd2029f23 1616 * by the user until the command completes (CCIF returns to 1). No command
mbed_official 324:406fd2029f23 1617 * buffering or queueing is provided; the next command can be loaded only after the
mbed_official 324:406fd2029f23 1618 * current command completes. Some commands return information to the FCCOB
mbed_official 324:406fd2029f23 1619 * registers. Any values returned to FCCOB are available for reading after the
mbed_official 324:406fd2029f23 1620 * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
mbed_official 324:406fd2029f23 1621 * generic flash command format. The first FCCOB register, FCCOB0, always contains
mbed_official 324:406fd2029f23 1622 * the command code. This 8-bit value defines the command to be executed. The
mbed_official 324:406fd2029f23 1623 * command code is followed by the parameters required for this specific flash
mbed_official 324:406fd2029f23 1624 * command, typically an address and/or data values. The command parameter table is
mbed_official 324:406fd2029f23 1625 * written in terms of FCCOB Number (which is equivalent to the byte number). This
mbed_official 324:406fd2029f23 1626 * number is a reference to the FCCOB register name and is not the register
mbed_official 324:406fd2029f23 1627 * address. FCCOB Number Typical Command Parameter Contents [7:0] 0 FCMD (a code that
mbed_official 324:406fd2029f23 1628 * defines the flash command) 1 Flash address [23:16] 2 Flash address [15:8] 3
mbed_official 324:406fd2029f23 1629 * Flash address [7:0] 4 Data Byte 0 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8
mbed_official 324:406fd2029f23 1630 * Data Byte 4 9 Data Byte 5 A Data Byte 6 B Data Byte 7 FCCOB Endianness : The
mbed_official 324:406fd2029f23 1631 * FCCOB register group uses a big endian addressing convention. For all command
mbed_official 324:406fd2029f23 1632 * parameter fields larger than 1 byte, the most significant data resides in the
mbed_official 324:406fd2029f23 1633 * lowest FCCOB register number.
mbed_official 324:406fd2029f23 1634 */
mbed_official 324:406fd2029f23 1635 /*@{*/
mbed_official 324:406fd2029f23 1636 #define BP_FTFA_FCCOB8_CCOBn (0U) /*!< Bit position for FTFA_FCCOB8_CCOBn. */
mbed_official 324:406fd2029f23 1637 #define BM_FTFA_FCCOB8_CCOBn (0xFFU) /*!< Bit mask for FTFA_FCCOB8_CCOBn. */
mbed_official 324:406fd2029f23 1638 #define BS_FTFA_FCCOB8_CCOBn (8U) /*!< Bit field size in bits for FTFA_FCCOB8_CCOBn. */
mbed_official 324:406fd2029f23 1639
mbed_official 324:406fd2029f23 1640 /*! @brief Read current value of the FTFA_FCCOB8_CCOBn field. */
mbed_official 324:406fd2029f23 1641 #define BR_FTFA_FCCOB8_CCOBn(x) (HW_FTFA_FCCOB8(x).U)
mbed_official 324:406fd2029f23 1642
mbed_official 324:406fd2029f23 1643 /*! @brief Format value for bitfield FTFA_FCCOB8_CCOBn. */
mbed_official 324:406fd2029f23 1644 #define BF_FTFA_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FCCOB8_CCOBn) & BM_FTFA_FCCOB8_CCOBn)
mbed_official 324:406fd2029f23 1645
mbed_official 324:406fd2029f23 1646 /*! @brief Set the CCOBn field to a new value. */
mbed_official 324:406fd2029f23 1647 #define BW_FTFA_FCCOB8_CCOBn(x, v) (HW_FTFA_FCCOB8_WR(x, v))
mbed_official 324:406fd2029f23 1648 /*@}*/
mbed_official 324:406fd2029f23 1649
mbed_official 324:406fd2029f23 1650 /*******************************************************************************
mbed_official 324:406fd2029f23 1651 * HW_FTFA_FPROT3 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 1652 ******************************************************************************/
mbed_official 324:406fd2029f23 1653
mbed_official 324:406fd2029f23 1654 /*!
mbed_official 324:406fd2029f23 1655 * @brief HW_FTFA_FPROT3 - Program Flash Protection Registers (RW)
mbed_official 324:406fd2029f23 1656 *
mbed_official 324:406fd2029f23 1657 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1658 *
mbed_official 324:406fd2029f23 1659 * The FPROT registers define which logical program flash regions are protected
mbed_official 324:406fd2029f23 1660 * from program and erase operations. Protected flash regions cannot have their
mbed_official 324:406fd2029f23 1661 * content changed; that is, these regions cannot be programmed and cannot be
mbed_official 324:406fd2029f23 1662 * erased by any flash command. Unprotected regions can be changed by program and
mbed_official 324:406fd2029f23 1663 * erase operations. The four FPROT registers allow up to 32 protectable regions.
mbed_official 324:406fd2029f23 1664 * Each bit protects a 1/32 region of the program flash memory except for memory
mbed_official 324:406fd2029f23 1665 * configurations with less than 32 KB of program flash where each assigned bit
mbed_official 324:406fd2029f23 1666 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
mbed_official 324:406fd2029f23 1667 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
mbed_official 324:406fd2029f23 1668 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
mbed_official 324:406fd2029f23 1669 * FPROT2 is not used. The bitfields are defined in each register as follows:
mbed_official 324:406fd2029f23 1670 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
mbed_official 324:406fd2029f23 1671 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
mbed_official 324:406fd2029f23 1672 * sequence, the FPROT registers are loaded with the contents of the program flash
mbed_official 324:406fd2029f23 1673 * protection bytes in the Flash Configuration Field as indicated in the following
mbed_official 324:406fd2029f23 1674 * table. Program flash protection register Flash Configuration Field offset
mbed_official 324:406fd2029f23 1675 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
mbed_official 324:406fd2029f23 1676 * program flash protection that is loaded during the reset sequence, unprotect the
mbed_official 324:406fd2029f23 1677 * sector of program flash memory that contains the Flash Configuration Field. Then,
mbed_official 324:406fd2029f23 1678 * reprogram the program flash protection byte.
mbed_official 324:406fd2029f23 1679 */
mbed_official 324:406fd2029f23 1680 typedef union _hw_ftfa_fprot3
mbed_official 324:406fd2029f23 1681 {
mbed_official 324:406fd2029f23 1682 uint8_t U;
mbed_official 324:406fd2029f23 1683 struct _hw_ftfa_fprot3_bitfields
mbed_official 324:406fd2029f23 1684 {
mbed_official 324:406fd2029f23 1685 uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */
mbed_official 324:406fd2029f23 1686 } B;
mbed_official 324:406fd2029f23 1687 } hw_ftfa_fprot3_t;
mbed_official 324:406fd2029f23 1688
mbed_official 324:406fd2029f23 1689 /*!
mbed_official 324:406fd2029f23 1690 * @name Constants and macros for entire FTFA_FPROT3 register
mbed_official 324:406fd2029f23 1691 */
mbed_official 324:406fd2029f23 1692 /*@{*/
mbed_official 324:406fd2029f23 1693 #define HW_FTFA_FPROT3_ADDR(x) ((x) + 0x10U)
mbed_official 324:406fd2029f23 1694
mbed_official 324:406fd2029f23 1695 #define HW_FTFA_FPROT3(x) (*(__IO hw_ftfa_fprot3_t *) HW_FTFA_FPROT3_ADDR(x))
mbed_official 324:406fd2029f23 1696 #define HW_FTFA_FPROT3_RD(x) (HW_FTFA_FPROT3(x).U)
mbed_official 324:406fd2029f23 1697 #define HW_FTFA_FPROT3_WR(x, v) (HW_FTFA_FPROT3(x).U = (v))
mbed_official 324:406fd2029f23 1698 #define HW_FTFA_FPROT3_SET(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) | (v)))
mbed_official 324:406fd2029f23 1699 #define HW_FTFA_FPROT3_CLR(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1700 #define HW_FTFA_FPROT3_TOG(x, v) (HW_FTFA_FPROT3_WR(x, HW_FTFA_FPROT3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1701 /*@}*/
mbed_official 324:406fd2029f23 1702
mbed_official 324:406fd2029f23 1703 /*
mbed_official 324:406fd2029f23 1704 * Constants & macros for individual FTFA_FPROT3 bitfields
mbed_official 324:406fd2029f23 1705 */
mbed_official 324:406fd2029f23 1706
mbed_official 324:406fd2029f23 1707 /*!
mbed_official 324:406fd2029f23 1708 * @name Register FTFA_FPROT3, field PROT[7:0] (RW)
mbed_official 324:406fd2029f23 1709 *
mbed_official 324:406fd2029f23 1710 * Each program flash region can be protected from program and erase operations
mbed_official 324:406fd2029f23 1711 * by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official 324:406fd2029f23 1712 * only be increased, meaning that currently unprotected memory can be protected,
mbed_official 324:406fd2029f23 1713 * but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official 324:406fd2029f23 1714 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official 324:406fd2029f23 1715 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official 324:406fd2029f23 1716 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official 324:406fd2029f23 1717 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official 324:406fd2029f23 1718 * writable without restriction. Unprotected areas can be protected and protected
mbed_official 324:406fd2029f23 1719 * areas can be unprotected. The user must never write to any FPROT register while
mbed_official 324:406fd2029f23 1720 * a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official 324:406fd2029f23 1721 * the program flash memory results in a protection violation error and sets the
mbed_official 324:406fd2029f23 1722 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official 324:406fd2029f23 1723 * if it contains any protected region. Each bit in the 32-bit protection
mbed_official 324:406fd2029f23 1724 * register represents 1/32 of the total program flash except for configurations where
mbed_official 324:406fd2029f23 1725 * program flash memory is less than 32 KB. For configurations with less than 32
mbed_official 324:406fd2029f23 1726 * KB of program flash memory, each assigned bit represents 1 KB.
mbed_official 324:406fd2029f23 1727 *
mbed_official 324:406fd2029f23 1728 * Values:
mbed_official 324:406fd2029f23 1729 * - 0 - Program flash region is protected.
mbed_official 324:406fd2029f23 1730 * - 1 - Program flash region is not protected
mbed_official 324:406fd2029f23 1731 */
mbed_official 324:406fd2029f23 1732 /*@{*/
mbed_official 324:406fd2029f23 1733 #define BP_FTFA_FPROT3_PROT (0U) /*!< Bit position for FTFA_FPROT3_PROT. */
mbed_official 324:406fd2029f23 1734 #define BM_FTFA_FPROT3_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT3_PROT. */
mbed_official 324:406fd2029f23 1735 #define BS_FTFA_FPROT3_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT3_PROT. */
mbed_official 324:406fd2029f23 1736
mbed_official 324:406fd2029f23 1737 /*! @brief Read current value of the FTFA_FPROT3_PROT field. */
mbed_official 324:406fd2029f23 1738 #define BR_FTFA_FPROT3_PROT(x) (HW_FTFA_FPROT3(x).U)
mbed_official 324:406fd2029f23 1739
mbed_official 324:406fd2029f23 1740 /*! @brief Format value for bitfield FTFA_FPROT3_PROT. */
mbed_official 324:406fd2029f23 1741 #define BF_FTFA_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT3_PROT) & BM_FTFA_FPROT3_PROT)
mbed_official 324:406fd2029f23 1742
mbed_official 324:406fd2029f23 1743 /*! @brief Set the PROT field to a new value. */
mbed_official 324:406fd2029f23 1744 #define BW_FTFA_FPROT3_PROT(x, v) (HW_FTFA_FPROT3_WR(x, v))
mbed_official 324:406fd2029f23 1745 /*@}*/
mbed_official 324:406fd2029f23 1746
mbed_official 324:406fd2029f23 1747 /*******************************************************************************
mbed_official 324:406fd2029f23 1748 * HW_FTFA_FPROT2 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 1749 ******************************************************************************/
mbed_official 324:406fd2029f23 1750
mbed_official 324:406fd2029f23 1751 /*!
mbed_official 324:406fd2029f23 1752 * @brief HW_FTFA_FPROT2 - Program Flash Protection Registers (RW)
mbed_official 324:406fd2029f23 1753 *
mbed_official 324:406fd2029f23 1754 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1755 *
mbed_official 324:406fd2029f23 1756 * The FPROT registers define which logical program flash regions are protected
mbed_official 324:406fd2029f23 1757 * from program and erase operations. Protected flash regions cannot have their
mbed_official 324:406fd2029f23 1758 * content changed; that is, these regions cannot be programmed and cannot be
mbed_official 324:406fd2029f23 1759 * erased by any flash command. Unprotected regions can be changed by program and
mbed_official 324:406fd2029f23 1760 * erase operations. The four FPROT registers allow up to 32 protectable regions.
mbed_official 324:406fd2029f23 1761 * Each bit protects a 1/32 region of the program flash memory except for memory
mbed_official 324:406fd2029f23 1762 * configurations with less than 32 KB of program flash where each assigned bit
mbed_official 324:406fd2029f23 1763 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
mbed_official 324:406fd2029f23 1764 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
mbed_official 324:406fd2029f23 1765 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
mbed_official 324:406fd2029f23 1766 * FPROT2 is not used. The bitfields are defined in each register as follows:
mbed_official 324:406fd2029f23 1767 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
mbed_official 324:406fd2029f23 1768 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
mbed_official 324:406fd2029f23 1769 * sequence, the FPROT registers are loaded with the contents of the program flash
mbed_official 324:406fd2029f23 1770 * protection bytes in the Flash Configuration Field as indicated in the following
mbed_official 324:406fd2029f23 1771 * table. Program flash protection register Flash Configuration Field offset
mbed_official 324:406fd2029f23 1772 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
mbed_official 324:406fd2029f23 1773 * program flash protection that is loaded during the reset sequence, unprotect the
mbed_official 324:406fd2029f23 1774 * sector of program flash memory that contains the Flash Configuration Field. Then,
mbed_official 324:406fd2029f23 1775 * reprogram the program flash protection byte.
mbed_official 324:406fd2029f23 1776 */
mbed_official 324:406fd2029f23 1777 typedef union _hw_ftfa_fprot2
mbed_official 324:406fd2029f23 1778 {
mbed_official 324:406fd2029f23 1779 uint8_t U;
mbed_official 324:406fd2029f23 1780 struct _hw_ftfa_fprot2_bitfields
mbed_official 324:406fd2029f23 1781 {
mbed_official 324:406fd2029f23 1782 uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */
mbed_official 324:406fd2029f23 1783 } B;
mbed_official 324:406fd2029f23 1784 } hw_ftfa_fprot2_t;
mbed_official 324:406fd2029f23 1785
mbed_official 324:406fd2029f23 1786 /*!
mbed_official 324:406fd2029f23 1787 * @name Constants and macros for entire FTFA_FPROT2 register
mbed_official 324:406fd2029f23 1788 */
mbed_official 324:406fd2029f23 1789 /*@{*/
mbed_official 324:406fd2029f23 1790 #define HW_FTFA_FPROT2_ADDR(x) ((x) + 0x11U)
mbed_official 324:406fd2029f23 1791
mbed_official 324:406fd2029f23 1792 #define HW_FTFA_FPROT2(x) (*(__IO hw_ftfa_fprot2_t *) HW_FTFA_FPROT2_ADDR(x))
mbed_official 324:406fd2029f23 1793 #define HW_FTFA_FPROT2_RD(x) (HW_FTFA_FPROT2(x).U)
mbed_official 324:406fd2029f23 1794 #define HW_FTFA_FPROT2_WR(x, v) (HW_FTFA_FPROT2(x).U = (v))
mbed_official 324:406fd2029f23 1795 #define HW_FTFA_FPROT2_SET(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) | (v)))
mbed_official 324:406fd2029f23 1796 #define HW_FTFA_FPROT2_CLR(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1797 #define HW_FTFA_FPROT2_TOG(x, v) (HW_FTFA_FPROT2_WR(x, HW_FTFA_FPROT2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1798 /*@}*/
mbed_official 324:406fd2029f23 1799
mbed_official 324:406fd2029f23 1800 /*
mbed_official 324:406fd2029f23 1801 * Constants & macros for individual FTFA_FPROT2 bitfields
mbed_official 324:406fd2029f23 1802 */
mbed_official 324:406fd2029f23 1803
mbed_official 324:406fd2029f23 1804 /*!
mbed_official 324:406fd2029f23 1805 * @name Register FTFA_FPROT2, field PROT[7:0] (RW)
mbed_official 324:406fd2029f23 1806 *
mbed_official 324:406fd2029f23 1807 * Each program flash region can be protected from program and erase operations
mbed_official 324:406fd2029f23 1808 * by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official 324:406fd2029f23 1809 * only be increased, meaning that currently unprotected memory can be protected,
mbed_official 324:406fd2029f23 1810 * but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official 324:406fd2029f23 1811 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official 324:406fd2029f23 1812 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official 324:406fd2029f23 1813 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official 324:406fd2029f23 1814 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official 324:406fd2029f23 1815 * writable without restriction. Unprotected areas can be protected and protected
mbed_official 324:406fd2029f23 1816 * areas can be unprotected. The user must never write to any FPROT register while
mbed_official 324:406fd2029f23 1817 * a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official 324:406fd2029f23 1818 * the program flash memory results in a protection violation error and sets the
mbed_official 324:406fd2029f23 1819 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official 324:406fd2029f23 1820 * if it contains any protected region. Each bit in the 32-bit protection
mbed_official 324:406fd2029f23 1821 * register represents 1/32 of the total program flash except for configurations where
mbed_official 324:406fd2029f23 1822 * program flash memory is less than 32 KB. For configurations with less than 32
mbed_official 324:406fd2029f23 1823 * KB of program flash memory, each assigned bit represents 1 KB.
mbed_official 324:406fd2029f23 1824 *
mbed_official 324:406fd2029f23 1825 * Values:
mbed_official 324:406fd2029f23 1826 * - 0 - Program flash region is protected.
mbed_official 324:406fd2029f23 1827 * - 1 - Program flash region is not protected
mbed_official 324:406fd2029f23 1828 */
mbed_official 324:406fd2029f23 1829 /*@{*/
mbed_official 324:406fd2029f23 1830 #define BP_FTFA_FPROT2_PROT (0U) /*!< Bit position for FTFA_FPROT2_PROT. */
mbed_official 324:406fd2029f23 1831 #define BM_FTFA_FPROT2_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT2_PROT. */
mbed_official 324:406fd2029f23 1832 #define BS_FTFA_FPROT2_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT2_PROT. */
mbed_official 324:406fd2029f23 1833
mbed_official 324:406fd2029f23 1834 /*! @brief Read current value of the FTFA_FPROT2_PROT field. */
mbed_official 324:406fd2029f23 1835 #define BR_FTFA_FPROT2_PROT(x) (HW_FTFA_FPROT2(x).U)
mbed_official 324:406fd2029f23 1836
mbed_official 324:406fd2029f23 1837 /*! @brief Format value for bitfield FTFA_FPROT2_PROT. */
mbed_official 324:406fd2029f23 1838 #define BF_FTFA_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT2_PROT) & BM_FTFA_FPROT2_PROT)
mbed_official 324:406fd2029f23 1839
mbed_official 324:406fd2029f23 1840 /*! @brief Set the PROT field to a new value. */
mbed_official 324:406fd2029f23 1841 #define BW_FTFA_FPROT2_PROT(x, v) (HW_FTFA_FPROT2_WR(x, v))
mbed_official 324:406fd2029f23 1842 /*@}*/
mbed_official 324:406fd2029f23 1843
mbed_official 324:406fd2029f23 1844 /*******************************************************************************
mbed_official 324:406fd2029f23 1845 * HW_FTFA_FPROT1 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 1846 ******************************************************************************/
mbed_official 324:406fd2029f23 1847
mbed_official 324:406fd2029f23 1848 /*!
mbed_official 324:406fd2029f23 1849 * @brief HW_FTFA_FPROT1 - Program Flash Protection Registers (RW)
mbed_official 324:406fd2029f23 1850 *
mbed_official 324:406fd2029f23 1851 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1852 *
mbed_official 324:406fd2029f23 1853 * The FPROT registers define which logical program flash regions are protected
mbed_official 324:406fd2029f23 1854 * from program and erase operations. Protected flash regions cannot have their
mbed_official 324:406fd2029f23 1855 * content changed; that is, these regions cannot be programmed and cannot be
mbed_official 324:406fd2029f23 1856 * erased by any flash command. Unprotected regions can be changed by program and
mbed_official 324:406fd2029f23 1857 * erase operations. The four FPROT registers allow up to 32 protectable regions.
mbed_official 324:406fd2029f23 1858 * Each bit protects a 1/32 region of the program flash memory except for memory
mbed_official 324:406fd2029f23 1859 * configurations with less than 32 KB of program flash where each assigned bit
mbed_official 324:406fd2029f23 1860 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
mbed_official 324:406fd2029f23 1861 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
mbed_official 324:406fd2029f23 1862 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
mbed_official 324:406fd2029f23 1863 * FPROT2 is not used. The bitfields are defined in each register as follows:
mbed_official 324:406fd2029f23 1864 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
mbed_official 324:406fd2029f23 1865 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
mbed_official 324:406fd2029f23 1866 * sequence, the FPROT registers are loaded with the contents of the program flash
mbed_official 324:406fd2029f23 1867 * protection bytes in the Flash Configuration Field as indicated in the following
mbed_official 324:406fd2029f23 1868 * table. Program flash protection register Flash Configuration Field offset
mbed_official 324:406fd2029f23 1869 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
mbed_official 324:406fd2029f23 1870 * program flash protection that is loaded during the reset sequence, unprotect the
mbed_official 324:406fd2029f23 1871 * sector of program flash memory that contains the Flash Configuration Field. Then,
mbed_official 324:406fd2029f23 1872 * reprogram the program flash protection byte.
mbed_official 324:406fd2029f23 1873 */
mbed_official 324:406fd2029f23 1874 typedef union _hw_ftfa_fprot1
mbed_official 324:406fd2029f23 1875 {
mbed_official 324:406fd2029f23 1876 uint8_t U;
mbed_official 324:406fd2029f23 1877 struct _hw_ftfa_fprot1_bitfields
mbed_official 324:406fd2029f23 1878 {
mbed_official 324:406fd2029f23 1879 uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */
mbed_official 324:406fd2029f23 1880 } B;
mbed_official 324:406fd2029f23 1881 } hw_ftfa_fprot1_t;
mbed_official 324:406fd2029f23 1882
mbed_official 324:406fd2029f23 1883 /*!
mbed_official 324:406fd2029f23 1884 * @name Constants and macros for entire FTFA_FPROT1 register
mbed_official 324:406fd2029f23 1885 */
mbed_official 324:406fd2029f23 1886 /*@{*/
mbed_official 324:406fd2029f23 1887 #define HW_FTFA_FPROT1_ADDR(x) ((x) + 0x12U)
mbed_official 324:406fd2029f23 1888
mbed_official 324:406fd2029f23 1889 #define HW_FTFA_FPROT1(x) (*(__IO hw_ftfa_fprot1_t *) HW_FTFA_FPROT1_ADDR(x))
mbed_official 324:406fd2029f23 1890 #define HW_FTFA_FPROT1_RD(x) (HW_FTFA_FPROT1(x).U)
mbed_official 324:406fd2029f23 1891 #define HW_FTFA_FPROT1_WR(x, v) (HW_FTFA_FPROT1(x).U = (v))
mbed_official 324:406fd2029f23 1892 #define HW_FTFA_FPROT1_SET(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) | (v)))
mbed_official 324:406fd2029f23 1893 #define HW_FTFA_FPROT1_CLR(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1894 #define HW_FTFA_FPROT1_TOG(x, v) (HW_FTFA_FPROT1_WR(x, HW_FTFA_FPROT1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1895 /*@}*/
mbed_official 324:406fd2029f23 1896
mbed_official 324:406fd2029f23 1897 /*
mbed_official 324:406fd2029f23 1898 * Constants & macros for individual FTFA_FPROT1 bitfields
mbed_official 324:406fd2029f23 1899 */
mbed_official 324:406fd2029f23 1900
mbed_official 324:406fd2029f23 1901 /*!
mbed_official 324:406fd2029f23 1902 * @name Register FTFA_FPROT1, field PROT[7:0] (RW)
mbed_official 324:406fd2029f23 1903 *
mbed_official 324:406fd2029f23 1904 * Each program flash region can be protected from program and erase operations
mbed_official 324:406fd2029f23 1905 * by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official 324:406fd2029f23 1906 * only be increased, meaning that currently unprotected memory can be protected,
mbed_official 324:406fd2029f23 1907 * but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official 324:406fd2029f23 1908 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official 324:406fd2029f23 1909 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official 324:406fd2029f23 1910 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official 324:406fd2029f23 1911 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official 324:406fd2029f23 1912 * writable without restriction. Unprotected areas can be protected and protected
mbed_official 324:406fd2029f23 1913 * areas can be unprotected. The user must never write to any FPROT register while
mbed_official 324:406fd2029f23 1914 * a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official 324:406fd2029f23 1915 * the program flash memory results in a protection violation error and sets the
mbed_official 324:406fd2029f23 1916 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official 324:406fd2029f23 1917 * if it contains any protected region. Each bit in the 32-bit protection
mbed_official 324:406fd2029f23 1918 * register represents 1/32 of the total program flash except for configurations where
mbed_official 324:406fd2029f23 1919 * program flash memory is less than 32 KB. For configurations with less than 32
mbed_official 324:406fd2029f23 1920 * KB of program flash memory, each assigned bit represents 1 KB.
mbed_official 324:406fd2029f23 1921 *
mbed_official 324:406fd2029f23 1922 * Values:
mbed_official 324:406fd2029f23 1923 * - 0 - Program flash region is protected.
mbed_official 324:406fd2029f23 1924 * - 1 - Program flash region is not protected
mbed_official 324:406fd2029f23 1925 */
mbed_official 324:406fd2029f23 1926 /*@{*/
mbed_official 324:406fd2029f23 1927 #define BP_FTFA_FPROT1_PROT (0U) /*!< Bit position for FTFA_FPROT1_PROT. */
mbed_official 324:406fd2029f23 1928 #define BM_FTFA_FPROT1_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT1_PROT. */
mbed_official 324:406fd2029f23 1929 #define BS_FTFA_FPROT1_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT1_PROT. */
mbed_official 324:406fd2029f23 1930
mbed_official 324:406fd2029f23 1931 /*! @brief Read current value of the FTFA_FPROT1_PROT field. */
mbed_official 324:406fd2029f23 1932 #define BR_FTFA_FPROT1_PROT(x) (HW_FTFA_FPROT1(x).U)
mbed_official 324:406fd2029f23 1933
mbed_official 324:406fd2029f23 1934 /*! @brief Format value for bitfield FTFA_FPROT1_PROT. */
mbed_official 324:406fd2029f23 1935 #define BF_FTFA_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT1_PROT) & BM_FTFA_FPROT1_PROT)
mbed_official 324:406fd2029f23 1936
mbed_official 324:406fd2029f23 1937 /*! @brief Set the PROT field to a new value. */
mbed_official 324:406fd2029f23 1938 #define BW_FTFA_FPROT1_PROT(x, v) (HW_FTFA_FPROT1_WR(x, v))
mbed_official 324:406fd2029f23 1939 /*@}*/
mbed_official 324:406fd2029f23 1940
mbed_official 324:406fd2029f23 1941 /*******************************************************************************
mbed_official 324:406fd2029f23 1942 * HW_FTFA_FPROT0 - Program Flash Protection Registers
mbed_official 324:406fd2029f23 1943 ******************************************************************************/
mbed_official 324:406fd2029f23 1944
mbed_official 324:406fd2029f23 1945 /*!
mbed_official 324:406fd2029f23 1946 * @brief HW_FTFA_FPROT0 - Program Flash Protection Registers (RW)
mbed_official 324:406fd2029f23 1947 *
mbed_official 324:406fd2029f23 1948 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1949 *
mbed_official 324:406fd2029f23 1950 * The FPROT registers define which logical program flash regions are protected
mbed_official 324:406fd2029f23 1951 * from program and erase operations. Protected flash regions cannot have their
mbed_official 324:406fd2029f23 1952 * content changed; that is, these regions cannot be programmed and cannot be
mbed_official 324:406fd2029f23 1953 * erased by any flash command. Unprotected regions can be changed by program and
mbed_official 324:406fd2029f23 1954 * erase operations. The four FPROT registers allow up to 32 protectable regions.
mbed_official 324:406fd2029f23 1955 * Each bit protects a 1/32 region of the program flash memory except for memory
mbed_official 324:406fd2029f23 1956 * configurations with less than 32 KB of program flash where each assigned bit
mbed_official 324:406fd2029f23 1957 * protects 1 KB . For configurations with 24 KB of program flash memory or less,
mbed_official 324:406fd2029f23 1958 * FPROT0 is not used. For configurations with 16 KB of program flash memory or
mbed_official 324:406fd2029f23 1959 * less, FPROT1 is not used. For configurations with 8 KB of program flash memory,
mbed_official 324:406fd2029f23 1960 * FPROT2 is not used. The bitfields are defined in each register as follows:
mbed_official 324:406fd2029f23 1961 * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
mbed_official 324:406fd2029f23 1962 * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
mbed_official 324:406fd2029f23 1963 * sequence, the FPROT registers are loaded with the contents of the program flash
mbed_official 324:406fd2029f23 1964 * protection bytes in the Flash Configuration Field as indicated in the following
mbed_official 324:406fd2029f23 1965 * table. Program flash protection register Flash Configuration Field offset
mbed_official 324:406fd2029f23 1966 * address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the
mbed_official 324:406fd2029f23 1967 * program flash protection that is loaded during the reset sequence, unprotect the
mbed_official 324:406fd2029f23 1968 * sector of program flash memory that contains the Flash Configuration Field. Then,
mbed_official 324:406fd2029f23 1969 * reprogram the program flash protection byte.
mbed_official 324:406fd2029f23 1970 */
mbed_official 324:406fd2029f23 1971 typedef union _hw_ftfa_fprot0
mbed_official 324:406fd2029f23 1972 {
mbed_official 324:406fd2029f23 1973 uint8_t U;
mbed_official 324:406fd2029f23 1974 struct _hw_ftfa_fprot0_bitfields
mbed_official 324:406fd2029f23 1975 {
mbed_official 324:406fd2029f23 1976 uint8_t PROT : 8; /*!< [7:0] Program Flash Region Protect */
mbed_official 324:406fd2029f23 1977 } B;
mbed_official 324:406fd2029f23 1978 } hw_ftfa_fprot0_t;
mbed_official 324:406fd2029f23 1979
mbed_official 324:406fd2029f23 1980 /*!
mbed_official 324:406fd2029f23 1981 * @name Constants and macros for entire FTFA_FPROT0 register
mbed_official 324:406fd2029f23 1982 */
mbed_official 324:406fd2029f23 1983 /*@{*/
mbed_official 324:406fd2029f23 1984 #define HW_FTFA_FPROT0_ADDR(x) ((x) + 0x13U)
mbed_official 324:406fd2029f23 1985
mbed_official 324:406fd2029f23 1986 #define HW_FTFA_FPROT0(x) (*(__IO hw_ftfa_fprot0_t *) HW_FTFA_FPROT0_ADDR(x))
mbed_official 324:406fd2029f23 1987 #define HW_FTFA_FPROT0_RD(x) (HW_FTFA_FPROT0(x).U)
mbed_official 324:406fd2029f23 1988 #define HW_FTFA_FPROT0_WR(x, v) (HW_FTFA_FPROT0(x).U = (v))
mbed_official 324:406fd2029f23 1989 #define HW_FTFA_FPROT0_SET(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) | (v)))
mbed_official 324:406fd2029f23 1990 #define HW_FTFA_FPROT0_CLR(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1991 #define HW_FTFA_FPROT0_TOG(x, v) (HW_FTFA_FPROT0_WR(x, HW_FTFA_FPROT0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1992 /*@}*/
mbed_official 324:406fd2029f23 1993
mbed_official 324:406fd2029f23 1994 /*
mbed_official 324:406fd2029f23 1995 * Constants & macros for individual FTFA_FPROT0 bitfields
mbed_official 324:406fd2029f23 1996 */
mbed_official 324:406fd2029f23 1997
mbed_official 324:406fd2029f23 1998 /*!
mbed_official 324:406fd2029f23 1999 * @name Register FTFA_FPROT0, field PROT[7:0] (RW)
mbed_official 324:406fd2029f23 2000 *
mbed_official 324:406fd2029f23 2001 * Each program flash region can be protected from program and erase operations
mbed_official 324:406fd2029f23 2002 * by setting the associated PROT bit. In NVM Normal mode: The protection can
mbed_official 324:406fd2029f23 2003 * only be increased, meaning that currently unprotected memory can be protected,
mbed_official 324:406fd2029f23 2004 * but currently protected memory cannot be unprotected. Since unprotected regions
mbed_official 324:406fd2029f23 2005 * are marked with a 1 and protected regions use a 0, only writes changing 1s to
mbed_official 324:406fd2029f23 2006 * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
mbed_official 324:406fd2029f23 2007 * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
mbed_official 324:406fd2029f23 2008 * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
mbed_official 324:406fd2029f23 2009 * writable without restriction. Unprotected areas can be protected and protected
mbed_official 324:406fd2029f23 2010 * areas can be unprotected. The user must never write to any FPROT register while
mbed_official 324:406fd2029f23 2011 * a command is running (CCIF=0). Trying to alter data in any protected area in
mbed_official 324:406fd2029f23 2012 * the program flash memory results in a protection violation error and sets the
mbed_official 324:406fd2029f23 2013 * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
mbed_official 324:406fd2029f23 2014 * if it contains any protected region. Each bit in the 32-bit protection
mbed_official 324:406fd2029f23 2015 * register represents 1/32 of the total program flash except for configurations where
mbed_official 324:406fd2029f23 2016 * program flash memory is less than 32 KB. For configurations with less than 32
mbed_official 324:406fd2029f23 2017 * KB of program flash memory, each assigned bit represents 1 KB.
mbed_official 324:406fd2029f23 2018 *
mbed_official 324:406fd2029f23 2019 * Values:
mbed_official 324:406fd2029f23 2020 * - 0 - Program flash region is protected.
mbed_official 324:406fd2029f23 2021 * - 1 - Program flash region is not protected
mbed_official 324:406fd2029f23 2022 */
mbed_official 324:406fd2029f23 2023 /*@{*/
mbed_official 324:406fd2029f23 2024 #define BP_FTFA_FPROT0_PROT (0U) /*!< Bit position for FTFA_FPROT0_PROT. */
mbed_official 324:406fd2029f23 2025 #define BM_FTFA_FPROT0_PROT (0xFFU) /*!< Bit mask for FTFA_FPROT0_PROT. */
mbed_official 324:406fd2029f23 2026 #define BS_FTFA_FPROT0_PROT (8U) /*!< Bit field size in bits for FTFA_FPROT0_PROT. */
mbed_official 324:406fd2029f23 2027
mbed_official 324:406fd2029f23 2028 /*! @brief Read current value of the FTFA_FPROT0_PROT field. */
mbed_official 324:406fd2029f23 2029 #define BR_FTFA_FPROT0_PROT(x) (HW_FTFA_FPROT0(x).U)
mbed_official 324:406fd2029f23 2030
mbed_official 324:406fd2029f23 2031 /*! @brief Format value for bitfield FTFA_FPROT0_PROT. */
mbed_official 324:406fd2029f23 2032 #define BF_FTFA_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFA_FPROT0_PROT) & BM_FTFA_FPROT0_PROT)
mbed_official 324:406fd2029f23 2033
mbed_official 324:406fd2029f23 2034 /*! @brief Set the PROT field to a new value. */
mbed_official 324:406fd2029f23 2035 #define BW_FTFA_FPROT0_PROT(x, v) (HW_FTFA_FPROT0_WR(x, v))
mbed_official 324:406fd2029f23 2036 /*@}*/
mbed_official 324:406fd2029f23 2037
mbed_official 324:406fd2029f23 2038 /*******************************************************************************
mbed_official 324:406fd2029f23 2039 * HW_FTFA_XACCH3 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2040 ******************************************************************************/
mbed_official 324:406fd2029f23 2041
mbed_official 324:406fd2029f23 2042 /*!
mbed_official 324:406fd2029f23 2043 * @brief HW_FTFA_XACCH3 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2044 *
mbed_official 324:406fd2029f23 2045 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2046 *
mbed_official 324:406fd2029f23 2047 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2048 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2049 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2050 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2051 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2052 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2053 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2054 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2055 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2056 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2057 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2058 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2059 */
mbed_official 324:406fd2029f23 2060 typedef union _hw_ftfa_xacch3
mbed_official 324:406fd2029f23 2061 {
mbed_official 324:406fd2029f23 2062 uint8_t U;
mbed_official 324:406fd2029f23 2063 struct _hw_ftfa_xacch3_bitfields
mbed_official 324:406fd2029f23 2064 {
mbed_official 324:406fd2029f23 2065 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2066 } B;
mbed_official 324:406fd2029f23 2067 } hw_ftfa_xacch3_t;
mbed_official 324:406fd2029f23 2068
mbed_official 324:406fd2029f23 2069 /*!
mbed_official 324:406fd2029f23 2070 * @name Constants and macros for entire FTFA_XACCH3 register
mbed_official 324:406fd2029f23 2071 */
mbed_official 324:406fd2029f23 2072 /*@{*/
mbed_official 324:406fd2029f23 2073 #define HW_FTFA_XACCH3_ADDR(x) ((x) + 0x18U)
mbed_official 324:406fd2029f23 2074
mbed_official 324:406fd2029f23 2075 #define HW_FTFA_XACCH3(x) (*(__I hw_ftfa_xacch3_t *) HW_FTFA_XACCH3_ADDR(x))
mbed_official 324:406fd2029f23 2076 #define HW_FTFA_XACCH3_RD(x) (HW_FTFA_XACCH3(x).U)
mbed_official 324:406fd2029f23 2077 /*@}*/
mbed_official 324:406fd2029f23 2078
mbed_official 324:406fd2029f23 2079 /*
mbed_official 324:406fd2029f23 2080 * Constants & macros for individual FTFA_XACCH3 bitfields
mbed_official 324:406fd2029f23 2081 */
mbed_official 324:406fd2029f23 2082
mbed_official 324:406fd2029f23 2083 /*!
mbed_official 324:406fd2029f23 2084 * @name Register FTFA_XACCH3, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2085 *
mbed_official 324:406fd2029f23 2086 * Values:
mbed_official 324:406fd2029f23 2087 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2088 * instruction fetch)
mbed_official 324:406fd2029f23 2089 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2090 */
mbed_official 324:406fd2029f23 2091 /*@{*/
mbed_official 324:406fd2029f23 2092 #define BP_FTFA_XACCH3_XA (0U) /*!< Bit position for FTFA_XACCH3_XA. */
mbed_official 324:406fd2029f23 2093 #define BM_FTFA_XACCH3_XA (0xFFU) /*!< Bit mask for FTFA_XACCH3_XA. */
mbed_official 324:406fd2029f23 2094 #define BS_FTFA_XACCH3_XA (8U) /*!< Bit field size in bits for FTFA_XACCH3_XA. */
mbed_official 324:406fd2029f23 2095
mbed_official 324:406fd2029f23 2096 /*! @brief Read current value of the FTFA_XACCH3_XA field. */
mbed_official 324:406fd2029f23 2097 #define BR_FTFA_XACCH3_XA(x) (HW_FTFA_XACCH3(x).U)
mbed_official 324:406fd2029f23 2098 /*@}*/
mbed_official 324:406fd2029f23 2099
mbed_official 324:406fd2029f23 2100 /*******************************************************************************
mbed_official 324:406fd2029f23 2101 * HW_FTFA_XACCH2 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2102 ******************************************************************************/
mbed_official 324:406fd2029f23 2103
mbed_official 324:406fd2029f23 2104 /*!
mbed_official 324:406fd2029f23 2105 * @brief HW_FTFA_XACCH2 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2106 *
mbed_official 324:406fd2029f23 2107 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2108 *
mbed_official 324:406fd2029f23 2109 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2110 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2111 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2112 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2113 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2114 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2115 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2116 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2117 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2118 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2119 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2120 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2121 */
mbed_official 324:406fd2029f23 2122 typedef union _hw_ftfa_xacch2
mbed_official 324:406fd2029f23 2123 {
mbed_official 324:406fd2029f23 2124 uint8_t U;
mbed_official 324:406fd2029f23 2125 struct _hw_ftfa_xacch2_bitfields
mbed_official 324:406fd2029f23 2126 {
mbed_official 324:406fd2029f23 2127 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2128 } B;
mbed_official 324:406fd2029f23 2129 } hw_ftfa_xacch2_t;
mbed_official 324:406fd2029f23 2130
mbed_official 324:406fd2029f23 2131 /*!
mbed_official 324:406fd2029f23 2132 * @name Constants and macros for entire FTFA_XACCH2 register
mbed_official 324:406fd2029f23 2133 */
mbed_official 324:406fd2029f23 2134 /*@{*/
mbed_official 324:406fd2029f23 2135 #define HW_FTFA_XACCH2_ADDR(x) ((x) + 0x19U)
mbed_official 324:406fd2029f23 2136
mbed_official 324:406fd2029f23 2137 #define HW_FTFA_XACCH2(x) (*(__I hw_ftfa_xacch2_t *) HW_FTFA_XACCH2_ADDR(x))
mbed_official 324:406fd2029f23 2138 #define HW_FTFA_XACCH2_RD(x) (HW_FTFA_XACCH2(x).U)
mbed_official 324:406fd2029f23 2139 /*@}*/
mbed_official 324:406fd2029f23 2140
mbed_official 324:406fd2029f23 2141 /*
mbed_official 324:406fd2029f23 2142 * Constants & macros for individual FTFA_XACCH2 bitfields
mbed_official 324:406fd2029f23 2143 */
mbed_official 324:406fd2029f23 2144
mbed_official 324:406fd2029f23 2145 /*!
mbed_official 324:406fd2029f23 2146 * @name Register FTFA_XACCH2, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2147 *
mbed_official 324:406fd2029f23 2148 * Values:
mbed_official 324:406fd2029f23 2149 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2150 * instruction fetch)
mbed_official 324:406fd2029f23 2151 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2152 */
mbed_official 324:406fd2029f23 2153 /*@{*/
mbed_official 324:406fd2029f23 2154 #define BP_FTFA_XACCH2_XA (0U) /*!< Bit position for FTFA_XACCH2_XA. */
mbed_official 324:406fd2029f23 2155 #define BM_FTFA_XACCH2_XA (0xFFU) /*!< Bit mask for FTFA_XACCH2_XA. */
mbed_official 324:406fd2029f23 2156 #define BS_FTFA_XACCH2_XA (8U) /*!< Bit field size in bits for FTFA_XACCH2_XA. */
mbed_official 324:406fd2029f23 2157
mbed_official 324:406fd2029f23 2158 /*! @brief Read current value of the FTFA_XACCH2_XA field. */
mbed_official 324:406fd2029f23 2159 #define BR_FTFA_XACCH2_XA(x) (HW_FTFA_XACCH2(x).U)
mbed_official 324:406fd2029f23 2160 /*@}*/
mbed_official 324:406fd2029f23 2161
mbed_official 324:406fd2029f23 2162 /*******************************************************************************
mbed_official 324:406fd2029f23 2163 * HW_FTFA_XACCH1 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2164 ******************************************************************************/
mbed_official 324:406fd2029f23 2165
mbed_official 324:406fd2029f23 2166 /*!
mbed_official 324:406fd2029f23 2167 * @brief HW_FTFA_XACCH1 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2168 *
mbed_official 324:406fd2029f23 2169 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2170 *
mbed_official 324:406fd2029f23 2171 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2172 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2173 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2174 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2175 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2176 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2177 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2178 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2179 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2180 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2181 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2182 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2183 */
mbed_official 324:406fd2029f23 2184 typedef union _hw_ftfa_xacch1
mbed_official 324:406fd2029f23 2185 {
mbed_official 324:406fd2029f23 2186 uint8_t U;
mbed_official 324:406fd2029f23 2187 struct _hw_ftfa_xacch1_bitfields
mbed_official 324:406fd2029f23 2188 {
mbed_official 324:406fd2029f23 2189 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2190 } B;
mbed_official 324:406fd2029f23 2191 } hw_ftfa_xacch1_t;
mbed_official 324:406fd2029f23 2192
mbed_official 324:406fd2029f23 2193 /*!
mbed_official 324:406fd2029f23 2194 * @name Constants and macros for entire FTFA_XACCH1 register
mbed_official 324:406fd2029f23 2195 */
mbed_official 324:406fd2029f23 2196 /*@{*/
mbed_official 324:406fd2029f23 2197 #define HW_FTFA_XACCH1_ADDR(x) ((x) + 0x1AU)
mbed_official 324:406fd2029f23 2198
mbed_official 324:406fd2029f23 2199 #define HW_FTFA_XACCH1(x) (*(__I hw_ftfa_xacch1_t *) HW_FTFA_XACCH1_ADDR(x))
mbed_official 324:406fd2029f23 2200 #define HW_FTFA_XACCH1_RD(x) (HW_FTFA_XACCH1(x).U)
mbed_official 324:406fd2029f23 2201 /*@}*/
mbed_official 324:406fd2029f23 2202
mbed_official 324:406fd2029f23 2203 /*
mbed_official 324:406fd2029f23 2204 * Constants & macros for individual FTFA_XACCH1 bitfields
mbed_official 324:406fd2029f23 2205 */
mbed_official 324:406fd2029f23 2206
mbed_official 324:406fd2029f23 2207 /*!
mbed_official 324:406fd2029f23 2208 * @name Register FTFA_XACCH1, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2209 *
mbed_official 324:406fd2029f23 2210 * Values:
mbed_official 324:406fd2029f23 2211 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2212 * instruction fetch)
mbed_official 324:406fd2029f23 2213 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2214 */
mbed_official 324:406fd2029f23 2215 /*@{*/
mbed_official 324:406fd2029f23 2216 #define BP_FTFA_XACCH1_XA (0U) /*!< Bit position for FTFA_XACCH1_XA. */
mbed_official 324:406fd2029f23 2217 #define BM_FTFA_XACCH1_XA (0xFFU) /*!< Bit mask for FTFA_XACCH1_XA. */
mbed_official 324:406fd2029f23 2218 #define BS_FTFA_XACCH1_XA (8U) /*!< Bit field size in bits for FTFA_XACCH1_XA. */
mbed_official 324:406fd2029f23 2219
mbed_official 324:406fd2029f23 2220 /*! @brief Read current value of the FTFA_XACCH1_XA field. */
mbed_official 324:406fd2029f23 2221 #define BR_FTFA_XACCH1_XA(x) (HW_FTFA_XACCH1(x).U)
mbed_official 324:406fd2029f23 2222 /*@}*/
mbed_official 324:406fd2029f23 2223
mbed_official 324:406fd2029f23 2224 /*******************************************************************************
mbed_official 324:406fd2029f23 2225 * HW_FTFA_XACCH0 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2226 ******************************************************************************/
mbed_official 324:406fd2029f23 2227
mbed_official 324:406fd2029f23 2228 /*!
mbed_official 324:406fd2029f23 2229 * @brief HW_FTFA_XACCH0 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2230 *
mbed_official 324:406fd2029f23 2231 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2232 *
mbed_official 324:406fd2029f23 2233 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2234 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2235 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2236 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2237 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2238 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2239 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2240 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2241 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2242 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2243 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2244 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2245 */
mbed_official 324:406fd2029f23 2246 typedef union _hw_ftfa_xacch0
mbed_official 324:406fd2029f23 2247 {
mbed_official 324:406fd2029f23 2248 uint8_t U;
mbed_official 324:406fd2029f23 2249 struct _hw_ftfa_xacch0_bitfields
mbed_official 324:406fd2029f23 2250 {
mbed_official 324:406fd2029f23 2251 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2252 } B;
mbed_official 324:406fd2029f23 2253 } hw_ftfa_xacch0_t;
mbed_official 324:406fd2029f23 2254
mbed_official 324:406fd2029f23 2255 /*!
mbed_official 324:406fd2029f23 2256 * @name Constants and macros for entire FTFA_XACCH0 register
mbed_official 324:406fd2029f23 2257 */
mbed_official 324:406fd2029f23 2258 /*@{*/
mbed_official 324:406fd2029f23 2259 #define HW_FTFA_XACCH0_ADDR(x) ((x) + 0x1BU)
mbed_official 324:406fd2029f23 2260
mbed_official 324:406fd2029f23 2261 #define HW_FTFA_XACCH0(x) (*(__I hw_ftfa_xacch0_t *) HW_FTFA_XACCH0_ADDR(x))
mbed_official 324:406fd2029f23 2262 #define HW_FTFA_XACCH0_RD(x) (HW_FTFA_XACCH0(x).U)
mbed_official 324:406fd2029f23 2263 /*@}*/
mbed_official 324:406fd2029f23 2264
mbed_official 324:406fd2029f23 2265 /*
mbed_official 324:406fd2029f23 2266 * Constants & macros for individual FTFA_XACCH0 bitfields
mbed_official 324:406fd2029f23 2267 */
mbed_official 324:406fd2029f23 2268
mbed_official 324:406fd2029f23 2269 /*!
mbed_official 324:406fd2029f23 2270 * @name Register FTFA_XACCH0, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2271 *
mbed_official 324:406fd2029f23 2272 * Values:
mbed_official 324:406fd2029f23 2273 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2274 * instruction fetch)
mbed_official 324:406fd2029f23 2275 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2276 */
mbed_official 324:406fd2029f23 2277 /*@{*/
mbed_official 324:406fd2029f23 2278 #define BP_FTFA_XACCH0_XA (0U) /*!< Bit position for FTFA_XACCH0_XA. */
mbed_official 324:406fd2029f23 2279 #define BM_FTFA_XACCH0_XA (0xFFU) /*!< Bit mask for FTFA_XACCH0_XA. */
mbed_official 324:406fd2029f23 2280 #define BS_FTFA_XACCH0_XA (8U) /*!< Bit field size in bits for FTFA_XACCH0_XA. */
mbed_official 324:406fd2029f23 2281
mbed_official 324:406fd2029f23 2282 /*! @brief Read current value of the FTFA_XACCH0_XA field. */
mbed_official 324:406fd2029f23 2283 #define BR_FTFA_XACCH0_XA(x) (HW_FTFA_XACCH0(x).U)
mbed_official 324:406fd2029f23 2284 /*@}*/
mbed_official 324:406fd2029f23 2285
mbed_official 324:406fd2029f23 2286 /*******************************************************************************
mbed_official 324:406fd2029f23 2287 * HW_FTFA_XACCL3 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2288 ******************************************************************************/
mbed_official 324:406fd2029f23 2289
mbed_official 324:406fd2029f23 2290 /*!
mbed_official 324:406fd2029f23 2291 * @brief HW_FTFA_XACCL3 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2292 *
mbed_official 324:406fd2029f23 2293 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2294 *
mbed_official 324:406fd2029f23 2295 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2296 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2297 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2298 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2299 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2300 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2301 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2302 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2303 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2304 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2305 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2306 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2307 */
mbed_official 324:406fd2029f23 2308 typedef union _hw_ftfa_xaccl3
mbed_official 324:406fd2029f23 2309 {
mbed_official 324:406fd2029f23 2310 uint8_t U;
mbed_official 324:406fd2029f23 2311 struct _hw_ftfa_xaccl3_bitfields
mbed_official 324:406fd2029f23 2312 {
mbed_official 324:406fd2029f23 2313 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2314 } B;
mbed_official 324:406fd2029f23 2315 } hw_ftfa_xaccl3_t;
mbed_official 324:406fd2029f23 2316
mbed_official 324:406fd2029f23 2317 /*!
mbed_official 324:406fd2029f23 2318 * @name Constants and macros for entire FTFA_XACCL3 register
mbed_official 324:406fd2029f23 2319 */
mbed_official 324:406fd2029f23 2320 /*@{*/
mbed_official 324:406fd2029f23 2321 #define HW_FTFA_XACCL3_ADDR(x) ((x) + 0x1CU)
mbed_official 324:406fd2029f23 2322
mbed_official 324:406fd2029f23 2323 #define HW_FTFA_XACCL3(x) (*(__I hw_ftfa_xaccl3_t *) HW_FTFA_XACCL3_ADDR(x))
mbed_official 324:406fd2029f23 2324 #define HW_FTFA_XACCL3_RD(x) (HW_FTFA_XACCL3(x).U)
mbed_official 324:406fd2029f23 2325 /*@}*/
mbed_official 324:406fd2029f23 2326
mbed_official 324:406fd2029f23 2327 /*
mbed_official 324:406fd2029f23 2328 * Constants & macros for individual FTFA_XACCL3 bitfields
mbed_official 324:406fd2029f23 2329 */
mbed_official 324:406fd2029f23 2330
mbed_official 324:406fd2029f23 2331 /*!
mbed_official 324:406fd2029f23 2332 * @name Register FTFA_XACCL3, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2333 *
mbed_official 324:406fd2029f23 2334 * Values:
mbed_official 324:406fd2029f23 2335 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2336 * instruction fetch)
mbed_official 324:406fd2029f23 2337 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2338 */
mbed_official 324:406fd2029f23 2339 /*@{*/
mbed_official 324:406fd2029f23 2340 #define BP_FTFA_XACCL3_XA (0U) /*!< Bit position for FTFA_XACCL3_XA. */
mbed_official 324:406fd2029f23 2341 #define BM_FTFA_XACCL3_XA (0xFFU) /*!< Bit mask for FTFA_XACCL3_XA. */
mbed_official 324:406fd2029f23 2342 #define BS_FTFA_XACCL3_XA (8U) /*!< Bit field size in bits for FTFA_XACCL3_XA. */
mbed_official 324:406fd2029f23 2343
mbed_official 324:406fd2029f23 2344 /*! @brief Read current value of the FTFA_XACCL3_XA field. */
mbed_official 324:406fd2029f23 2345 #define BR_FTFA_XACCL3_XA(x) (HW_FTFA_XACCL3(x).U)
mbed_official 324:406fd2029f23 2346 /*@}*/
mbed_official 324:406fd2029f23 2347
mbed_official 324:406fd2029f23 2348 /*******************************************************************************
mbed_official 324:406fd2029f23 2349 * HW_FTFA_XACCL2 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2350 ******************************************************************************/
mbed_official 324:406fd2029f23 2351
mbed_official 324:406fd2029f23 2352 /*!
mbed_official 324:406fd2029f23 2353 * @brief HW_FTFA_XACCL2 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2354 *
mbed_official 324:406fd2029f23 2355 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2356 *
mbed_official 324:406fd2029f23 2357 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2358 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2359 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2360 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2361 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2362 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2363 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2364 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2365 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2366 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2367 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2368 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2369 */
mbed_official 324:406fd2029f23 2370 typedef union _hw_ftfa_xaccl2
mbed_official 324:406fd2029f23 2371 {
mbed_official 324:406fd2029f23 2372 uint8_t U;
mbed_official 324:406fd2029f23 2373 struct _hw_ftfa_xaccl2_bitfields
mbed_official 324:406fd2029f23 2374 {
mbed_official 324:406fd2029f23 2375 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2376 } B;
mbed_official 324:406fd2029f23 2377 } hw_ftfa_xaccl2_t;
mbed_official 324:406fd2029f23 2378
mbed_official 324:406fd2029f23 2379 /*!
mbed_official 324:406fd2029f23 2380 * @name Constants and macros for entire FTFA_XACCL2 register
mbed_official 324:406fd2029f23 2381 */
mbed_official 324:406fd2029f23 2382 /*@{*/
mbed_official 324:406fd2029f23 2383 #define HW_FTFA_XACCL2_ADDR(x) ((x) + 0x1DU)
mbed_official 324:406fd2029f23 2384
mbed_official 324:406fd2029f23 2385 #define HW_FTFA_XACCL2(x) (*(__I hw_ftfa_xaccl2_t *) HW_FTFA_XACCL2_ADDR(x))
mbed_official 324:406fd2029f23 2386 #define HW_FTFA_XACCL2_RD(x) (HW_FTFA_XACCL2(x).U)
mbed_official 324:406fd2029f23 2387 /*@}*/
mbed_official 324:406fd2029f23 2388
mbed_official 324:406fd2029f23 2389 /*
mbed_official 324:406fd2029f23 2390 * Constants & macros for individual FTFA_XACCL2 bitfields
mbed_official 324:406fd2029f23 2391 */
mbed_official 324:406fd2029f23 2392
mbed_official 324:406fd2029f23 2393 /*!
mbed_official 324:406fd2029f23 2394 * @name Register FTFA_XACCL2, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2395 *
mbed_official 324:406fd2029f23 2396 * Values:
mbed_official 324:406fd2029f23 2397 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2398 * instruction fetch)
mbed_official 324:406fd2029f23 2399 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2400 */
mbed_official 324:406fd2029f23 2401 /*@{*/
mbed_official 324:406fd2029f23 2402 #define BP_FTFA_XACCL2_XA (0U) /*!< Bit position for FTFA_XACCL2_XA. */
mbed_official 324:406fd2029f23 2403 #define BM_FTFA_XACCL2_XA (0xFFU) /*!< Bit mask for FTFA_XACCL2_XA. */
mbed_official 324:406fd2029f23 2404 #define BS_FTFA_XACCL2_XA (8U) /*!< Bit field size in bits for FTFA_XACCL2_XA. */
mbed_official 324:406fd2029f23 2405
mbed_official 324:406fd2029f23 2406 /*! @brief Read current value of the FTFA_XACCL2_XA field. */
mbed_official 324:406fd2029f23 2407 #define BR_FTFA_XACCL2_XA(x) (HW_FTFA_XACCL2(x).U)
mbed_official 324:406fd2029f23 2408 /*@}*/
mbed_official 324:406fd2029f23 2409
mbed_official 324:406fd2029f23 2410 /*******************************************************************************
mbed_official 324:406fd2029f23 2411 * HW_FTFA_XACCL1 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2412 ******************************************************************************/
mbed_official 324:406fd2029f23 2413
mbed_official 324:406fd2029f23 2414 /*!
mbed_official 324:406fd2029f23 2415 * @brief HW_FTFA_XACCL1 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2416 *
mbed_official 324:406fd2029f23 2417 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2418 *
mbed_official 324:406fd2029f23 2419 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2420 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2421 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2422 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2423 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2424 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2425 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2426 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2427 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2428 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2429 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2430 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2431 */
mbed_official 324:406fd2029f23 2432 typedef union _hw_ftfa_xaccl1
mbed_official 324:406fd2029f23 2433 {
mbed_official 324:406fd2029f23 2434 uint8_t U;
mbed_official 324:406fd2029f23 2435 struct _hw_ftfa_xaccl1_bitfields
mbed_official 324:406fd2029f23 2436 {
mbed_official 324:406fd2029f23 2437 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2438 } B;
mbed_official 324:406fd2029f23 2439 } hw_ftfa_xaccl1_t;
mbed_official 324:406fd2029f23 2440
mbed_official 324:406fd2029f23 2441 /*!
mbed_official 324:406fd2029f23 2442 * @name Constants and macros for entire FTFA_XACCL1 register
mbed_official 324:406fd2029f23 2443 */
mbed_official 324:406fd2029f23 2444 /*@{*/
mbed_official 324:406fd2029f23 2445 #define HW_FTFA_XACCL1_ADDR(x) ((x) + 0x1EU)
mbed_official 324:406fd2029f23 2446
mbed_official 324:406fd2029f23 2447 #define HW_FTFA_XACCL1(x) (*(__I hw_ftfa_xaccl1_t *) HW_FTFA_XACCL1_ADDR(x))
mbed_official 324:406fd2029f23 2448 #define HW_FTFA_XACCL1_RD(x) (HW_FTFA_XACCL1(x).U)
mbed_official 324:406fd2029f23 2449 /*@}*/
mbed_official 324:406fd2029f23 2450
mbed_official 324:406fd2029f23 2451 /*
mbed_official 324:406fd2029f23 2452 * Constants & macros for individual FTFA_XACCL1 bitfields
mbed_official 324:406fd2029f23 2453 */
mbed_official 324:406fd2029f23 2454
mbed_official 324:406fd2029f23 2455 /*!
mbed_official 324:406fd2029f23 2456 * @name Register FTFA_XACCL1, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2457 *
mbed_official 324:406fd2029f23 2458 * Values:
mbed_official 324:406fd2029f23 2459 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2460 * instruction fetch)
mbed_official 324:406fd2029f23 2461 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2462 */
mbed_official 324:406fd2029f23 2463 /*@{*/
mbed_official 324:406fd2029f23 2464 #define BP_FTFA_XACCL1_XA (0U) /*!< Bit position for FTFA_XACCL1_XA. */
mbed_official 324:406fd2029f23 2465 #define BM_FTFA_XACCL1_XA (0xFFU) /*!< Bit mask for FTFA_XACCL1_XA. */
mbed_official 324:406fd2029f23 2466 #define BS_FTFA_XACCL1_XA (8U) /*!< Bit field size in bits for FTFA_XACCL1_XA. */
mbed_official 324:406fd2029f23 2467
mbed_official 324:406fd2029f23 2468 /*! @brief Read current value of the FTFA_XACCL1_XA field. */
mbed_official 324:406fd2029f23 2469 #define BR_FTFA_XACCL1_XA(x) (HW_FTFA_XACCL1(x).U)
mbed_official 324:406fd2029f23 2470 /*@}*/
mbed_official 324:406fd2029f23 2471
mbed_official 324:406fd2029f23 2472 /*******************************************************************************
mbed_official 324:406fd2029f23 2473 * HW_FTFA_XACCL0 - Execute-only Access Registers
mbed_official 324:406fd2029f23 2474 ******************************************************************************/
mbed_official 324:406fd2029f23 2475
mbed_official 324:406fd2029f23 2476 /*!
mbed_official 324:406fd2029f23 2477 * @brief HW_FTFA_XACCL0 - Execute-only Access Registers (RO)
mbed_official 324:406fd2029f23 2478 *
mbed_official 324:406fd2029f23 2479 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2480 *
mbed_official 324:406fd2029f23 2481 * The XACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2482 * to data read or execute only or both data and instruction fetches. The eight
mbed_official 324:406fd2029f23 2483 * XACC registers allow up to 64 restricted segments of equal memory size.
mbed_official 324:406fd2029f23 2484 * Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56]
mbed_official 324:406fd2029f23 2485 * XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1
mbed_official 324:406fd2029f23 2486 * XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC
mbed_official 324:406fd2029f23 2487 * registers are loaded with the logical AND of Program Flash IFR addresses A and B
mbed_official 324:406fd2029f23 2488 * as indicated in the following table. Execute-only access register Program
mbed_official 324:406fd2029f23 2489 * Flash IFR address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA
mbed_official 324:406fd2029f23 2490 * XACCH2 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2
mbed_official 324:406fd2029f23 2491 * 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the
mbed_official 324:406fd2029f23 2492 * execute-only access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2493 */
mbed_official 324:406fd2029f23 2494 typedef union _hw_ftfa_xaccl0
mbed_official 324:406fd2029f23 2495 {
mbed_official 324:406fd2029f23 2496 uint8_t U;
mbed_official 324:406fd2029f23 2497 struct _hw_ftfa_xaccl0_bitfields
mbed_official 324:406fd2029f23 2498 {
mbed_official 324:406fd2029f23 2499 uint8_t XA : 8; /*!< [7:0] Execute-only access control */
mbed_official 324:406fd2029f23 2500 } B;
mbed_official 324:406fd2029f23 2501 } hw_ftfa_xaccl0_t;
mbed_official 324:406fd2029f23 2502
mbed_official 324:406fd2029f23 2503 /*!
mbed_official 324:406fd2029f23 2504 * @name Constants and macros for entire FTFA_XACCL0 register
mbed_official 324:406fd2029f23 2505 */
mbed_official 324:406fd2029f23 2506 /*@{*/
mbed_official 324:406fd2029f23 2507 #define HW_FTFA_XACCL0_ADDR(x) ((x) + 0x1FU)
mbed_official 324:406fd2029f23 2508
mbed_official 324:406fd2029f23 2509 #define HW_FTFA_XACCL0(x) (*(__I hw_ftfa_xaccl0_t *) HW_FTFA_XACCL0_ADDR(x))
mbed_official 324:406fd2029f23 2510 #define HW_FTFA_XACCL0_RD(x) (HW_FTFA_XACCL0(x).U)
mbed_official 324:406fd2029f23 2511 /*@}*/
mbed_official 324:406fd2029f23 2512
mbed_official 324:406fd2029f23 2513 /*
mbed_official 324:406fd2029f23 2514 * Constants & macros for individual FTFA_XACCL0 bitfields
mbed_official 324:406fd2029f23 2515 */
mbed_official 324:406fd2029f23 2516
mbed_official 324:406fd2029f23 2517 /*!
mbed_official 324:406fd2029f23 2518 * @name Register FTFA_XACCL0, field XA[7:0] (RO)
mbed_official 324:406fd2029f23 2519 *
mbed_official 324:406fd2029f23 2520 * Values:
mbed_official 324:406fd2029f23 2521 * - 0 - Associated segment is accessible in execute mode only (as an
mbed_official 324:406fd2029f23 2522 * instruction fetch)
mbed_official 324:406fd2029f23 2523 * - 1 - Associated segment is accessible as data or in execute mode
mbed_official 324:406fd2029f23 2524 */
mbed_official 324:406fd2029f23 2525 /*@{*/
mbed_official 324:406fd2029f23 2526 #define BP_FTFA_XACCL0_XA (0U) /*!< Bit position for FTFA_XACCL0_XA. */
mbed_official 324:406fd2029f23 2527 #define BM_FTFA_XACCL0_XA (0xFFU) /*!< Bit mask for FTFA_XACCL0_XA. */
mbed_official 324:406fd2029f23 2528 #define BS_FTFA_XACCL0_XA (8U) /*!< Bit field size in bits for FTFA_XACCL0_XA. */
mbed_official 324:406fd2029f23 2529
mbed_official 324:406fd2029f23 2530 /*! @brief Read current value of the FTFA_XACCL0_XA field. */
mbed_official 324:406fd2029f23 2531 #define BR_FTFA_XACCL0_XA(x) (HW_FTFA_XACCL0(x).U)
mbed_official 324:406fd2029f23 2532 /*@}*/
mbed_official 324:406fd2029f23 2533
mbed_official 324:406fd2029f23 2534 /*******************************************************************************
mbed_official 324:406fd2029f23 2535 * HW_FTFA_SACCH3 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2536 ******************************************************************************/
mbed_official 324:406fd2029f23 2537
mbed_official 324:406fd2029f23 2538 /*!
mbed_official 324:406fd2029f23 2539 * @brief HW_FTFA_SACCH3 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2540 *
mbed_official 324:406fd2029f23 2541 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2542 *
mbed_official 324:406fd2029f23 2543 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2544 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2545 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2546 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2547 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2548 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2549 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2550 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2551 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2552 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2553 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2554 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2555 */
mbed_official 324:406fd2029f23 2556 typedef union _hw_ftfa_sacch3
mbed_official 324:406fd2029f23 2557 {
mbed_official 324:406fd2029f23 2558 uint8_t U;
mbed_official 324:406fd2029f23 2559 struct _hw_ftfa_sacch3_bitfields
mbed_official 324:406fd2029f23 2560 {
mbed_official 324:406fd2029f23 2561 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2562 } B;
mbed_official 324:406fd2029f23 2563 } hw_ftfa_sacch3_t;
mbed_official 324:406fd2029f23 2564
mbed_official 324:406fd2029f23 2565 /*!
mbed_official 324:406fd2029f23 2566 * @name Constants and macros for entire FTFA_SACCH3 register
mbed_official 324:406fd2029f23 2567 */
mbed_official 324:406fd2029f23 2568 /*@{*/
mbed_official 324:406fd2029f23 2569 #define HW_FTFA_SACCH3_ADDR(x) ((x) + 0x20U)
mbed_official 324:406fd2029f23 2570
mbed_official 324:406fd2029f23 2571 #define HW_FTFA_SACCH3(x) (*(__I hw_ftfa_sacch3_t *) HW_FTFA_SACCH3_ADDR(x))
mbed_official 324:406fd2029f23 2572 #define HW_FTFA_SACCH3_RD(x) (HW_FTFA_SACCH3(x).U)
mbed_official 324:406fd2029f23 2573 /*@}*/
mbed_official 324:406fd2029f23 2574
mbed_official 324:406fd2029f23 2575 /*
mbed_official 324:406fd2029f23 2576 * Constants & macros for individual FTFA_SACCH3 bitfields
mbed_official 324:406fd2029f23 2577 */
mbed_official 324:406fd2029f23 2578
mbed_official 324:406fd2029f23 2579 /*!
mbed_official 324:406fd2029f23 2580 * @name Register FTFA_SACCH3, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2581 *
mbed_official 324:406fd2029f23 2582 * Values:
mbed_official 324:406fd2029f23 2583 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2584 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2585 */
mbed_official 324:406fd2029f23 2586 /*@{*/
mbed_official 324:406fd2029f23 2587 #define BP_FTFA_SACCH3_SA (0U) /*!< Bit position for FTFA_SACCH3_SA. */
mbed_official 324:406fd2029f23 2588 #define BM_FTFA_SACCH3_SA (0xFFU) /*!< Bit mask for FTFA_SACCH3_SA. */
mbed_official 324:406fd2029f23 2589 #define BS_FTFA_SACCH3_SA (8U) /*!< Bit field size in bits for FTFA_SACCH3_SA. */
mbed_official 324:406fd2029f23 2590
mbed_official 324:406fd2029f23 2591 /*! @brief Read current value of the FTFA_SACCH3_SA field. */
mbed_official 324:406fd2029f23 2592 #define BR_FTFA_SACCH3_SA(x) (HW_FTFA_SACCH3(x).U)
mbed_official 324:406fd2029f23 2593 /*@}*/
mbed_official 324:406fd2029f23 2594
mbed_official 324:406fd2029f23 2595 /*******************************************************************************
mbed_official 324:406fd2029f23 2596 * HW_FTFA_SACCH2 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2597 ******************************************************************************/
mbed_official 324:406fd2029f23 2598
mbed_official 324:406fd2029f23 2599 /*!
mbed_official 324:406fd2029f23 2600 * @brief HW_FTFA_SACCH2 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2601 *
mbed_official 324:406fd2029f23 2602 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2603 *
mbed_official 324:406fd2029f23 2604 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2605 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2606 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2607 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2608 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2609 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2610 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2611 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2612 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2613 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2614 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2615 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2616 */
mbed_official 324:406fd2029f23 2617 typedef union _hw_ftfa_sacch2
mbed_official 324:406fd2029f23 2618 {
mbed_official 324:406fd2029f23 2619 uint8_t U;
mbed_official 324:406fd2029f23 2620 struct _hw_ftfa_sacch2_bitfields
mbed_official 324:406fd2029f23 2621 {
mbed_official 324:406fd2029f23 2622 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2623 } B;
mbed_official 324:406fd2029f23 2624 } hw_ftfa_sacch2_t;
mbed_official 324:406fd2029f23 2625
mbed_official 324:406fd2029f23 2626 /*!
mbed_official 324:406fd2029f23 2627 * @name Constants and macros for entire FTFA_SACCH2 register
mbed_official 324:406fd2029f23 2628 */
mbed_official 324:406fd2029f23 2629 /*@{*/
mbed_official 324:406fd2029f23 2630 #define HW_FTFA_SACCH2_ADDR(x) ((x) + 0x21U)
mbed_official 324:406fd2029f23 2631
mbed_official 324:406fd2029f23 2632 #define HW_FTFA_SACCH2(x) (*(__I hw_ftfa_sacch2_t *) HW_FTFA_SACCH2_ADDR(x))
mbed_official 324:406fd2029f23 2633 #define HW_FTFA_SACCH2_RD(x) (HW_FTFA_SACCH2(x).U)
mbed_official 324:406fd2029f23 2634 /*@}*/
mbed_official 324:406fd2029f23 2635
mbed_official 324:406fd2029f23 2636 /*
mbed_official 324:406fd2029f23 2637 * Constants & macros for individual FTFA_SACCH2 bitfields
mbed_official 324:406fd2029f23 2638 */
mbed_official 324:406fd2029f23 2639
mbed_official 324:406fd2029f23 2640 /*!
mbed_official 324:406fd2029f23 2641 * @name Register FTFA_SACCH2, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2642 *
mbed_official 324:406fd2029f23 2643 * Values:
mbed_official 324:406fd2029f23 2644 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2645 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2646 */
mbed_official 324:406fd2029f23 2647 /*@{*/
mbed_official 324:406fd2029f23 2648 #define BP_FTFA_SACCH2_SA (0U) /*!< Bit position for FTFA_SACCH2_SA. */
mbed_official 324:406fd2029f23 2649 #define BM_FTFA_SACCH2_SA (0xFFU) /*!< Bit mask for FTFA_SACCH2_SA. */
mbed_official 324:406fd2029f23 2650 #define BS_FTFA_SACCH2_SA (8U) /*!< Bit field size in bits for FTFA_SACCH2_SA. */
mbed_official 324:406fd2029f23 2651
mbed_official 324:406fd2029f23 2652 /*! @brief Read current value of the FTFA_SACCH2_SA field. */
mbed_official 324:406fd2029f23 2653 #define BR_FTFA_SACCH2_SA(x) (HW_FTFA_SACCH2(x).U)
mbed_official 324:406fd2029f23 2654 /*@}*/
mbed_official 324:406fd2029f23 2655
mbed_official 324:406fd2029f23 2656 /*******************************************************************************
mbed_official 324:406fd2029f23 2657 * HW_FTFA_SACCH1 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2658 ******************************************************************************/
mbed_official 324:406fd2029f23 2659
mbed_official 324:406fd2029f23 2660 /*!
mbed_official 324:406fd2029f23 2661 * @brief HW_FTFA_SACCH1 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2662 *
mbed_official 324:406fd2029f23 2663 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2664 *
mbed_official 324:406fd2029f23 2665 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2666 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2667 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2668 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2669 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2670 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2671 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2672 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2673 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2674 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2675 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2676 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2677 */
mbed_official 324:406fd2029f23 2678 typedef union _hw_ftfa_sacch1
mbed_official 324:406fd2029f23 2679 {
mbed_official 324:406fd2029f23 2680 uint8_t U;
mbed_official 324:406fd2029f23 2681 struct _hw_ftfa_sacch1_bitfields
mbed_official 324:406fd2029f23 2682 {
mbed_official 324:406fd2029f23 2683 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2684 } B;
mbed_official 324:406fd2029f23 2685 } hw_ftfa_sacch1_t;
mbed_official 324:406fd2029f23 2686
mbed_official 324:406fd2029f23 2687 /*!
mbed_official 324:406fd2029f23 2688 * @name Constants and macros for entire FTFA_SACCH1 register
mbed_official 324:406fd2029f23 2689 */
mbed_official 324:406fd2029f23 2690 /*@{*/
mbed_official 324:406fd2029f23 2691 #define HW_FTFA_SACCH1_ADDR(x) ((x) + 0x22U)
mbed_official 324:406fd2029f23 2692
mbed_official 324:406fd2029f23 2693 #define HW_FTFA_SACCH1(x) (*(__I hw_ftfa_sacch1_t *) HW_FTFA_SACCH1_ADDR(x))
mbed_official 324:406fd2029f23 2694 #define HW_FTFA_SACCH1_RD(x) (HW_FTFA_SACCH1(x).U)
mbed_official 324:406fd2029f23 2695 /*@}*/
mbed_official 324:406fd2029f23 2696
mbed_official 324:406fd2029f23 2697 /*
mbed_official 324:406fd2029f23 2698 * Constants & macros for individual FTFA_SACCH1 bitfields
mbed_official 324:406fd2029f23 2699 */
mbed_official 324:406fd2029f23 2700
mbed_official 324:406fd2029f23 2701 /*!
mbed_official 324:406fd2029f23 2702 * @name Register FTFA_SACCH1, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2703 *
mbed_official 324:406fd2029f23 2704 * Values:
mbed_official 324:406fd2029f23 2705 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2706 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2707 */
mbed_official 324:406fd2029f23 2708 /*@{*/
mbed_official 324:406fd2029f23 2709 #define BP_FTFA_SACCH1_SA (0U) /*!< Bit position for FTFA_SACCH1_SA. */
mbed_official 324:406fd2029f23 2710 #define BM_FTFA_SACCH1_SA (0xFFU) /*!< Bit mask for FTFA_SACCH1_SA. */
mbed_official 324:406fd2029f23 2711 #define BS_FTFA_SACCH1_SA (8U) /*!< Bit field size in bits for FTFA_SACCH1_SA. */
mbed_official 324:406fd2029f23 2712
mbed_official 324:406fd2029f23 2713 /*! @brief Read current value of the FTFA_SACCH1_SA field. */
mbed_official 324:406fd2029f23 2714 #define BR_FTFA_SACCH1_SA(x) (HW_FTFA_SACCH1(x).U)
mbed_official 324:406fd2029f23 2715 /*@}*/
mbed_official 324:406fd2029f23 2716
mbed_official 324:406fd2029f23 2717 /*******************************************************************************
mbed_official 324:406fd2029f23 2718 * HW_FTFA_SACCH0 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2719 ******************************************************************************/
mbed_official 324:406fd2029f23 2720
mbed_official 324:406fd2029f23 2721 /*!
mbed_official 324:406fd2029f23 2722 * @brief HW_FTFA_SACCH0 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2723 *
mbed_official 324:406fd2029f23 2724 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2725 *
mbed_official 324:406fd2029f23 2726 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2727 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2728 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2729 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2730 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2731 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2732 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2733 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2734 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2735 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2736 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2737 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2738 */
mbed_official 324:406fd2029f23 2739 typedef union _hw_ftfa_sacch0
mbed_official 324:406fd2029f23 2740 {
mbed_official 324:406fd2029f23 2741 uint8_t U;
mbed_official 324:406fd2029f23 2742 struct _hw_ftfa_sacch0_bitfields
mbed_official 324:406fd2029f23 2743 {
mbed_official 324:406fd2029f23 2744 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2745 } B;
mbed_official 324:406fd2029f23 2746 } hw_ftfa_sacch0_t;
mbed_official 324:406fd2029f23 2747
mbed_official 324:406fd2029f23 2748 /*!
mbed_official 324:406fd2029f23 2749 * @name Constants and macros for entire FTFA_SACCH0 register
mbed_official 324:406fd2029f23 2750 */
mbed_official 324:406fd2029f23 2751 /*@{*/
mbed_official 324:406fd2029f23 2752 #define HW_FTFA_SACCH0_ADDR(x) ((x) + 0x23U)
mbed_official 324:406fd2029f23 2753
mbed_official 324:406fd2029f23 2754 #define HW_FTFA_SACCH0(x) (*(__I hw_ftfa_sacch0_t *) HW_FTFA_SACCH0_ADDR(x))
mbed_official 324:406fd2029f23 2755 #define HW_FTFA_SACCH0_RD(x) (HW_FTFA_SACCH0(x).U)
mbed_official 324:406fd2029f23 2756 /*@}*/
mbed_official 324:406fd2029f23 2757
mbed_official 324:406fd2029f23 2758 /*
mbed_official 324:406fd2029f23 2759 * Constants & macros for individual FTFA_SACCH0 bitfields
mbed_official 324:406fd2029f23 2760 */
mbed_official 324:406fd2029f23 2761
mbed_official 324:406fd2029f23 2762 /*!
mbed_official 324:406fd2029f23 2763 * @name Register FTFA_SACCH0, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2764 *
mbed_official 324:406fd2029f23 2765 * Values:
mbed_official 324:406fd2029f23 2766 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2767 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2768 */
mbed_official 324:406fd2029f23 2769 /*@{*/
mbed_official 324:406fd2029f23 2770 #define BP_FTFA_SACCH0_SA (0U) /*!< Bit position for FTFA_SACCH0_SA. */
mbed_official 324:406fd2029f23 2771 #define BM_FTFA_SACCH0_SA (0xFFU) /*!< Bit mask for FTFA_SACCH0_SA. */
mbed_official 324:406fd2029f23 2772 #define BS_FTFA_SACCH0_SA (8U) /*!< Bit field size in bits for FTFA_SACCH0_SA. */
mbed_official 324:406fd2029f23 2773
mbed_official 324:406fd2029f23 2774 /*! @brief Read current value of the FTFA_SACCH0_SA field. */
mbed_official 324:406fd2029f23 2775 #define BR_FTFA_SACCH0_SA(x) (HW_FTFA_SACCH0(x).U)
mbed_official 324:406fd2029f23 2776 /*@}*/
mbed_official 324:406fd2029f23 2777
mbed_official 324:406fd2029f23 2778 /*******************************************************************************
mbed_official 324:406fd2029f23 2779 * HW_FTFA_SACCL3 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2780 ******************************************************************************/
mbed_official 324:406fd2029f23 2781
mbed_official 324:406fd2029f23 2782 /*!
mbed_official 324:406fd2029f23 2783 * @brief HW_FTFA_SACCL3 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2784 *
mbed_official 324:406fd2029f23 2785 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2786 *
mbed_official 324:406fd2029f23 2787 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2788 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2789 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2790 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2791 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2792 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2793 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2794 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2795 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2796 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2797 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2798 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2799 */
mbed_official 324:406fd2029f23 2800 typedef union _hw_ftfa_saccl3
mbed_official 324:406fd2029f23 2801 {
mbed_official 324:406fd2029f23 2802 uint8_t U;
mbed_official 324:406fd2029f23 2803 struct _hw_ftfa_saccl3_bitfields
mbed_official 324:406fd2029f23 2804 {
mbed_official 324:406fd2029f23 2805 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2806 } B;
mbed_official 324:406fd2029f23 2807 } hw_ftfa_saccl3_t;
mbed_official 324:406fd2029f23 2808
mbed_official 324:406fd2029f23 2809 /*!
mbed_official 324:406fd2029f23 2810 * @name Constants and macros for entire FTFA_SACCL3 register
mbed_official 324:406fd2029f23 2811 */
mbed_official 324:406fd2029f23 2812 /*@{*/
mbed_official 324:406fd2029f23 2813 #define HW_FTFA_SACCL3_ADDR(x) ((x) + 0x24U)
mbed_official 324:406fd2029f23 2814
mbed_official 324:406fd2029f23 2815 #define HW_FTFA_SACCL3(x) (*(__I hw_ftfa_saccl3_t *) HW_FTFA_SACCL3_ADDR(x))
mbed_official 324:406fd2029f23 2816 #define HW_FTFA_SACCL3_RD(x) (HW_FTFA_SACCL3(x).U)
mbed_official 324:406fd2029f23 2817 /*@}*/
mbed_official 324:406fd2029f23 2818
mbed_official 324:406fd2029f23 2819 /*
mbed_official 324:406fd2029f23 2820 * Constants & macros for individual FTFA_SACCL3 bitfields
mbed_official 324:406fd2029f23 2821 */
mbed_official 324:406fd2029f23 2822
mbed_official 324:406fd2029f23 2823 /*!
mbed_official 324:406fd2029f23 2824 * @name Register FTFA_SACCL3, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2825 *
mbed_official 324:406fd2029f23 2826 * Values:
mbed_official 324:406fd2029f23 2827 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2828 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2829 */
mbed_official 324:406fd2029f23 2830 /*@{*/
mbed_official 324:406fd2029f23 2831 #define BP_FTFA_SACCL3_SA (0U) /*!< Bit position for FTFA_SACCL3_SA. */
mbed_official 324:406fd2029f23 2832 #define BM_FTFA_SACCL3_SA (0xFFU) /*!< Bit mask for FTFA_SACCL3_SA. */
mbed_official 324:406fd2029f23 2833 #define BS_FTFA_SACCL3_SA (8U) /*!< Bit field size in bits for FTFA_SACCL3_SA. */
mbed_official 324:406fd2029f23 2834
mbed_official 324:406fd2029f23 2835 /*! @brief Read current value of the FTFA_SACCL3_SA field. */
mbed_official 324:406fd2029f23 2836 #define BR_FTFA_SACCL3_SA(x) (HW_FTFA_SACCL3(x).U)
mbed_official 324:406fd2029f23 2837 /*@}*/
mbed_official 324:406fd2029f23 2838
mbed_official 324:406fd2029f23 2839 /*******************************************************************************
mbed_official 324:406fd2029f23 2840 * HW_FTFA_SACCL2 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2841 ******************************************************************************/
mbed_official 324:406fd2029f23 2842
mbed_official 324:406fd2029f23 2843 /*!
mbed_official 324:406fd2029f23 2844 * @brief HW_FTFA_SACCL2 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2845 *
mbed_official 324:406fd2029f23 2846 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2847 *
mbed_official 324:406fd2029f23 2848 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2849 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2850 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2851 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2852 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2853 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2854 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2855 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2856 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2857 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2858 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2859 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2860 */
mbed_official 324:406fd2029f23 2861 typedef union _hw_ftfa_saccl2
mbed_official 324:406fd2029f23 2862 {
mbed_official 324:406fd2029f23 2863 uint8_t U;
mbed_official 324:406fd2029f23 2864 struct _hw_ftfa_saccl2_bitfields
mbed_official 324:406fd2029f23 2865 {
mbed_official 324:406fd2029f23 2866 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2867 } B;
mbed_official 324:406fd2029f23 2868 } hw_ftfa_saccl2_t;
mbed_official 324:406fd2029f23 2869
mbed_official 324:406fd2029f23 2870 /*!
mbed_official 324:406fd2029f23 2871 * @name Constants and macros for entire FTFA_SACCL2 register
mbed_official 324:406fd2029f23 2872 */
mbed_official 324:406fd2029f23 2873 /*@{*/
mbed_official 324:406fd2029f23 2874 #define HW_FTFA_SACCL2_ADDR(x) ((x) + 0x25U)
mbed_official 324:406fd2029f23 2875
mbed_official 324:406fd2029f23 2876 #define HW_FTFA_SACCL2(x) (*(__I hw_ftfa_saccl2_t *) HW_FTFA_SACCL2_ADDR(x))
mbed_official 324:406fd2029f23 2877 #define HW_FTFA_SACCL2_RD(x) (HW_FTFA_SACCL2(x).U)
mbed_official 324:406fd2029f23 2878 /*@}*/
mbed_official 324:406fd2029f23 2879
mbed_official 324:406fd2029f23 2880 /*
mbed_official 324:406fd2029f23 2881 * Constants & macros for individual FTFA_SACCL2 bitfields
mbed_official 324:406fd2029f23 2882 */
mbed_official 324:406fd2029f23 2883
mbed_official 324:406fd2029f23 2884 /*!
mbed_official 324:406fd2029f23 2885 * @name Register FTFA_SACCL2, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2886 *
mbed_official 324:406fd2029f23 2887 * Values:
mbed_official 324:406fd2029f23 2888 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2889 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2890 */
mbed_official 324:406fd2029f23 2891 /*@{*/
mbed_official 324:406fd2029f23 2892 #define BP_FTFA_SACCL2_SA (0U) /*!< Bit position for FTFA_SACCL2_SA. */
mbed_official 324:406fd2029f23 2893 #define BM_FTFA_SACCL2_SA (0xFFU) /*!< Bit mask for FTFA_SACCL2_SA. */
mbed_official 324:406fd2029f23 2894 #define BS_FTFA_SACCL2_SA (8U) /*!< Bit field size in bits for FTFA_SACCL2_SA. */
mbed_official 324:406fd2029f23 2895
mbed_official 324:406fd2029f23 2896 /*! @brief Read current value of the FTFA_SACCL2_SA field. */
mbed_official 324:406fd2029f23 2897 #define BR_FTFA_SACCL2_SA(x) (HW_FTFA_SACCL2(x).U)
mbed_official 324:406fd2029f23 2898 /*@}*/
mbed_official 324:406fd2029f23 2899
mbed_official 324:406fd2029f23 2900 /*******************************************************************************
mbed_official 324:406fd2029f23 2901 * HW_FTFA_SACCL1 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2902 ******************************************************************************/
mbed_official 324:406fd2029f23 2903
mbed_official 324:406fd2029f23 2904 /*!
mbed_official 324:406fd2029f23 2905 * @brief HW_FTFA_SACCL1 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2906 *
mbed_official 324:406fd2029f23 2907 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2908 *
mbed_official 324:406fd2029f23 2909 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2910 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2911 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2912 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2913 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2914 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2915 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2916 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2917 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2918 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2919 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2920 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2921 */
mbed_official 324:406fd2029f23 2922 typedef union _hw_ftfa_saccl1
mbed_official 324:406fd2029f23 2923 {
mbed_official 324:406fd2029f23 2924 uint8_t U;
mbed_official 324:406fd2029f23 2925 struct _hw_ftfa_saccl1_bitfields
mbed_official 324:406fd2029f23 2926 {
mbed_official 324:406fd2029f23 2927 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2928 } B;
mbed_official 324:406fd2029f23 2929 } hw_ftfa_saccl1_t;
mbed_official 324:406fd2029f23 2930
mbed_official 324:406fd2029f23 2931 /*!
mbed_official 324:406fd2029f23 2932 * @name Constants and macros for entire FTFA_SACCL1 register
mbed_official 324:406fd2029f23 2933 */
mbed_official 324:406fd2029f23 2934 /*@{*/
mbed_official 324:406fd2029f23 2935 #define HW_FTFA_SACCL1_ADDR(x) ((x) + 0x26U)
mbed_official 324:406fd2029f23 2936
mbed_official 324:406fd2029f23 2937 #define HW_FTFA_SACCL1(x) (*(__I hw_ftfa_saccl1_t *) HW_FTFA_SACCL1_ADDR(x))
mbed_official 324:406fd2029f23 2938 #define HW_FTFA_SACCL1_RD(x) (HW_FTFA_SACCL1(x).U)
mbed_official 324:406fd2029f23 2939 /*@}*/
mbed_official 324:406fd2029f23 2940
mbed_official 324:406fd2029f23 2941 /*
mbed_official 324:406fd2029f23 2942 * Constants & macros for individual FTFA_SACCL1 bitfields
mbed_official 324:406fd2029f23 2943 */
mbed_official 324:406fd2029f23 2944
mbed_official 324:406fd2029f23 2945 /*!
mbed_official 324:406fd2029f23 2946 * @name Register FTFA_SACCL1, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 2947 *
mbed_official 324:406fd2029f23 2948 * Values:
mbed_official 324:406fd2029f23 2949 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 2950 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 2951 */
mbed_official 324:406fd2029f23 2952 /*@{*/
mbed_official 324:406fd2029f23 2953 #define BP_FTFA_SACCL1_SA (0U) /*!< Bit position for FTFA_SACCL1_SA. */
mbed_official 324:406fd2029f23 2954 #define BM_FTFA_SACCL1_SA (0xFFU) /*!< Bit mask for FTFA_SACCL1_SA. */
mbed_official 324:406fd2029f23 2955 #define BS_FTFA_SACCL1_SA (8U) /*!< Bit field size in bits for FTFA_SACCL1_SA. */
mbed_official 324:406fd2029f23 2956
mbed_official 324:406fd2029f23 2957 /*! @brief Read current value of the FTFA_SACCL1_SA field. */
mbed_official 324:406fd2029f23 2958 #define BR_FTFA_SACCL1_SA(x) (HW_FTFA_SACCL1(x).U)
mbed_official 324:406fd2029f23 2959 /*@}*/
mbed_official 324:406fd2029f23 2960
mbed_official 324:406fd2029f23 2961 /*******************************************************************************
mbed_official 324:406fd2029f23 2962 * HW_FTFA_SACCL0 - Supervisor-only Access Registers
mbed_official 324:406fd2029f23 2963 ******************************************************************************/
mbed_official 324:406fd2029f23 2964
mbed_official 324:406fd2029f23 2965 /*!
mbed_official 324:406fd2029f23 2966 * @brief HW_FTFA_SACCL0 - Supervisor-only Access Registers (RO)
mbed_official 324:406fd2029f23 2967 *
mbed_official 324:406fd2029f23 2968 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2969 *
mbed_official 324:406fd2029f23 2970 * The SACC registers define which logical program flash segments are restricted
mbed_official 324:406fd2029f23 2971 * to supervisor only or user and supervisor access. The eight SACC registers
mbed_official 324:406fd2029f23 2972 * allow up to 64 restricted segments of equal memory size. Supervisor-only access
mbed_official 324:406fd2029f23 2973 * register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1
mbed_official 324:406fd2029f23 2974 * SA[55:48] SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16]
mbed_official 324:406fd2029f23 2975 * SACCL2 SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are
mbed_official 324:406fd2029f23 2976 * loaded with the logical AND of Program Flash IFR addresses A and B as
mbed_official 324:406fd2029f23 2977 * indicated in the following table. Supervisor-only access register Program Flash IFR
mbed_official 324:406fd2029f23 2978 * address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2
mbed_official 324:406fd2029f23 2979 * 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD
mbed_official 324:406fd2029f23 2980 * SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only
mbed_official 324:406fd2029f23 2981 * access control fields that are loaded during the reset sequence.
mbed_official 324:406fd2029f23 2982 */
mbed_official 324:406fd2029f23 2983 typedef union _hw_ftfa_saccl0
mbed_official 324:406fd2029f23 2984 {
mbed_official 324:406fd2029f23 2985 uint8_t U;
mbed_official 324:406fd2029f23 2986 struct _hw_ftfa_saccl0_bitfields
mbed_official 324:406fd2029f23 2987 {
mbed_official 324:406fd2029f23 2988 uint8_t SA : 8; /*!< [7:0] Supervisor-only access control */
mbed_official 324:406fd2029f23 2989 } B;
mbed_official 324:406fd2029f23 2990 } hw_ftfa_saccl0_t;
mbed_official 324:406fd2029f23 2991
mbed_official 324:406fd2029f23 2992 /*!
mbed_official 324:406fd2029f23 2993 * @name Constants and macros for entire FTFA_SACCL0 register
mbed_official 324:406fd2029f23 2994 */
mbed_official 324:406fd2029f23 2995 /*@{*/
mbed_official 324:406fd2029f23 2996 #define HW_FTFA_SACCL0_ADDR(x) ((x) + 0x27U)
mbed_official 324:406fd2029f23 2997
mbed_official 324:406fd2029f23 2998 #define HW_FTFA_SACCL0(x) (*(__I hw_ftfa_saccl0_t *) HW_FTFA_SACCL0_ADDR(x))
mbed_official 324:406fd2029f23 2999 #define HW_FTFA_SACCL0_RD(x) (HW_FTFA_SACCL0(x).U)
mbed_official 324:406fd2029f23 3000 /*@}*/
mbed_official 324:406fd2029f23 3001
mbed_official 324:406fd2029f23 3002 /*
mbed_official 324:406fd2029f23 3003 * Constants & macros for individual FTFA_SACCL0 bitfields
mbed_official 324:406fd2029f23 3004 */
mbed_official 324:406fd2029f23 3005
mbed_official 324:406fd2029f23 3006 /*!
mbed_official 324:406fd2029f23 3007 * @name Register FTFA_SACCL0, field SA[7:0] (RO)
mbed_official 324:406fd2029f23 3008 *
mbed_official 324:406fd2029f23 3009 * Values:
mbed_official 324:406fd2029f23 3010 * - 0 - Associated segment is accessible in supervisor mode only
mbed_official 324:406fd2029f23 3011 * - 1 - Associated segment is accessible in user or supervisor mode
mbed_official 324:406fd2029f23 3012 */
mbed_official 324:406fd2029f23 3013 /*@{*/
mbed_official 324:406fd2029f23 3014 #define BP_FTFA_SACCL0_SA (0U) /*!< Bit position for FTFA_SACCL0_SA. */
mbed_official 324:406fd2029f23 3015 #define BM_FTFA_SACCL0_SA (0xFFU) /*!< Bit mask for FTFA_SACCL0_SA. */
mbed_official 324:406fd2029f23 3016 #define BS_FTFA_SACCL0_SA (8U) /*!< Bit field size in bits for FTFA_SACCL0_SA. */
mbed_official 324:406fd2029f23 3017
mbed_official 324:406fd2029f23 3018 /*! @brief Read current value of the FTFA_SACCL0_SA field. */
mbed_official 324:406fd2029f23 3019 #define BR_FTFA_SACCL0_SA(x) (HW_FTFA_SACCL0(x).U)
mbed_official 324:406fd2029f23 3020 /*@}*/
mbed_official 324:406fd2029f23 3021
mbed_official 324:406fd2029f23 3022 /*******************************************************************************
mbed_official 324:406fd2029f23 3023 * HW_FTFA_FACSS - Flash Access Segment Size Register
mbed_official 324:406fd2029f23 3024 ******************************************************************************/
mbed_official 324:406fd2029f23 3025
mbed_official 324:406fd2029f23 3026 /*!
mbed_official 324:406fd2029f23 3027 * @brief HW_FTFA_FACSS - Flash Access Segment Size Register (RO)
mbed_official 324:406fd2029f23 3028 *
mbed_official 324:406fd2029f23 3029 * Reset value: 0x00U
mbed_official 324:406fd2029f23 3030 *
mbed_official 324:406fd2029f23 3031 * The flash access segment size register determines which bits in the address
mbed_official 324:406fd2029f23 3032 * are used to index into the SACC and XACC bitmaps to get the appropriate
mbed_official 324:406fd2029f23 3033 * permission flags. All bits in the register are read-only. The contents of this
mbed_official 324:406fd2029f23 3034 * register are loaded during the reset sequence.
mbed_official 324:406fd2029f23 3035 */
mbed_official 324:406fd2029f23 3036 typedef union _hw_ftfa_facss
mbed_official 324:406fd2029f23 3037 {
mbed_official 324:406fd2029f23 3038 uint8_t U;
mbed_official 324:406fd2029f23 3039 struct _hw_ftfa_facss_bitfields
mbed_official 324:406fd2029f23 3040 {
mbed_official 324:406fd2029f23 3041 uint8_t SGSIZE : 8; /*!< [7:0] Segment Size */
mbed_official 324:406fd2029f23 3042 } B;
mbed_official 324:406fd2029f23 3043 } hw_ftfa_facss_t;
mbed_official 324:406fd2029f23 3044
mbed_official 324:406fd2029f23 3045 /*!
mbed_official 324:406fd2029f23 3046 * @name Constants and macros for entire FTFA_FACSS register
mbed_official 324:406fd2029f23 3047 */
mbed_official 324:406fd2029f23 3048 /*@{*/
mbed_official 324:406fd2029f23 3049 #define HW_FTFA_FACSS_ADDR(x) ((x) + 0x28U)
mbed_official 324:406fd2029f23 3050
mbed_official 324:406fd2029f23 3051 #define HW_FTFA_FACSS(x) (*(__I hw_ftfa_facss_t *) HW_FTFA_FACSS_ADDR(x))
mbed_official 324:406fd2029f23 3052 #define HW_FTFA_FACSS_RD(x) (HW_FTFA_FACSS(x).U)
mbed_official 324:406fd2029f23 3053 /*@}*/
mbed_official 324:406fd2029f23 3054
mbed_official 324:406fd2029f23 3055 /*
mbed_official 324:406fd2029f23 3056 * Constants & macros for individual FTFA_FACSS bitfields
mbed_official 324:406fd2029f23 3057 */
mbed_official 324:406fd2029f23 3058
mbed_official 324:406fd2029f23 3059 /*!
mbed_official 324:406fd2029f23 3060 * @name Register FTFA_FACSS, field SGSIZE[7:0] (RO)
mbed_official 324:406fd2029f23 3061 *
mbed_official 324:406fd2029f23 3062 * The segment size is a fixed value based on the available program flash size
mbed_official 324:406fd2029f23 3063 * divided by NUMSG. Program Flash Size Segment Size Segment Size Encoding 64
mbed_official 324:406fd2029f23 3064 * KBytes 2 KBytes 0x3 128 KBytes 4 KBytes 0x4 160 KBytes 4 KBytes 0x4 256 KBytes 4
mbed_official 324:406fd2029f23 3065 * KBytes 0x4 512 KBytes 8 KBytes 0x5
mbed_official 324:406fd2029f23 3066 */
mbed_official 324:406fd2029f23 3067 /*@{*/
mbed_official 324:406fd2029f23 3068 #define BP_FTFA_FACSS_SGSIZE (0U) /*!< Bit position for FTFA_FACSS_SGSIZE. */
mbed_official 324:406fd2029f23 3069 #define BM_FTFA_FACSS_SGSIZE (0xFFU) /*!< Bit mask for FTFA_FACSS_SGSIZE. */
mbed_official 324:406fd2029f23 3070 #define BS_FTFA_FACSS_SGSIZE (8U) /*!< Bit field size in bits for FTFA_FACSS_SGSIZE. */
mbed_official 324:406fd2029f23 3071
mbed_official 324:406fd2029f23 3072 /*! @brief Read current value of the FTFA_FACSS_SGSIZE field. */
mbed_official 324:406fd2029f23 3073 #define BR_FTFA_FACSS_SGSIZE(x) (HW_FTFA_FACSS(x).U)
mbed_official 324:406fd2029f23 3074 /*@}*/
mbed_official 324:406fd2029f23 3075
mbed_official 324:406fd2029f23 3076 /*******************************************************************************
mbed_official 324:406fd2029f23 3077 * HW_FTFA_FACSN - Flash Access Segment Number Register
mbed_official 324:406fd2029f23 3078 ******************************************************************************/
mbed_official 324:406fd2029f23 3079
mbed_official 324:406fd2029f23 3080 /*!
mbed_official 324:406fd2029f23 3081 * @brief HW_FTFA_FACSN - Flash Access Segment Number Register (RO)
mbed_official 324:406fd2029f23 3082 *
mbed_official 324:406fd2029f23 3083 * Reset value: 0x00U
mbed_official 324:406fd2029f23 3084 *
mbed_official 324:406fd2029f23 3085 * The flash access segment number register provides the number of program flash
mbed_official 324:406fd2029f23 3086 * segments that are available for XACC and SACC permissions. All bits in the
mbed_official 324:406fd2029f23 3087 * register are read-only. The contents of this register are loaded during the
mbed_official 324:406fd2029f23 3088 * reset sequence.
mbed_official 324:406fd2029f23 3089 */
mbed_official 324:406fd2029f23 3090 typedef union _hw_ftfa_facsn
mbed_official 324:406fd2029f23 3091 {
mbed_official 324:406fd2029f23 3092 uint8_t U;
mbed_official 324:406fd2029f23 3093 struct _hw_ftfa_facsn_bitfields
mbed_official 324:406fd2029f23 3094 {
mbed_official 324:406fd2029f23 3095 uint8_t NUMSG : 8; /*!< [7:0] Number of Segments Indicator */
mbed_official 324:406fd2029f23 3096 } B;
mbed_official 324:406fd2029f23 3097 } hw_ftfa_facsn_t;
mbed_official 324:406fd2029f23 3098
mbed_official 324:406fd2029f23 3099 /*!
mbed_official 324:406fd2029f23 3100 * @name Constants and macros for entire FTFA_FACSN register
mbed_official 324:406fd2029f23 3101 */
mbed_official 324:406fd2029f23 3102 /*@{*/
mbed_official 324:406fd2029f23 3103 #define HW_FTFA_FACSN_ADDR(x) ((x) + 0x2BU)
mbed_official 324:406fd2029f23 3104
mbed_official 324:406fd2029f23 3105 #define HW_FTFA_FACSN(x) (*(__I hw_ftfa_facsn_t *) HW_FTFA_FACSN_ADDR(x))
mbed_official 324:406fd2029f23 3106 #define HW_FTFA_FACSN_RD(x) (HW_FTFA_FACSN(x).U)
mbed_official 324:406fd2029f23 3107 /*@}*/
mbed_official 324:406fd2029f23 3108
mbed_official 324:406fd2029f23 3109 /*
mbed_official 324:406fd2029f23 3110 * Constants & macros for individual FTFA_FACSN bitfields
mbed_official 324:406fd2029f23 3111 */
mbed_official 324:406fd2029f23 3112
mbed_official 324:406fd2029f23 3113 /*!
mbed_official 324:406fd2029f23 3114 * @name Register FTFA_FACSN, field NUMSG[7:0] (RO)
mbed_official 324:406fd2029f23 3115 *
mbed_official 324:406fd2029f23 3116 * The NUMSG field indicates the number of equal-sized segments in the program
mbed_official 324:406fd2029f23 3117 * flash.
mbed_official 324:406fd2029f23 3118 *
mbed_official 324:406fd2029f23 3119 * Values:
mbed_official 324:406fd2029f23 3120 * - 100000 - Program flash memory is divided into 32 segments (64 Kbytes, 128
mbed_official 324:406fd2029f23 3121 * Kbytes)
mbed_official 324:406fd2029f23 3122 * - 101000 - Program flash memory is divided into 40 segments (160 Kbytes)
mbed_official 324:406fd2029f23 3123 * - 1000000 - Program flash memory is divided into 64 segments (256 Kbytes, 512
mbed_official 324:406fd2029f23 3124 * Kbytes)
mbed_official 324:406fd2029f23 3125 */
mbed_official 324:406fd2029f23 3126 /*@{*/
mbed_official 324:406fd2029f23 3127 #define BP_FTFA_FACSN_NUMSG (0U) /*!< Bit position for FTFA_FACSN_NUMSG. */
mbed_official 324:406fd2029f23 3128 #define BM_FTFA_FACSN_NUMSG (0xFFU) /*!< Bit mask for FTFA_FACSN_NUMSG. */
mbed_official 324:406fd2029f23 3129 #define BS_FTFA_FACSN_NUMSG (8U) /*!< Bit field size in bits for FTFA_FACSN_NUMSG. */
mbed_official 324:406fd2029f23 3130
mbed_official 324:406fd2029f23 3131 /*! @brief Read current value of the FTFA_FACSN_NUMSG field. */
mbed_official 324:406fd2029f23 3132 #define BR_FTFA_FACSN_NUMSG(x) (HW_FTFA_FACSN(x).U)
mbed_official 324:406fd2029f23 3133 /*@}*/
mbed_official 324:406fd2029f23 3134
mbed_official 324:406fd2029f23 3135 /*******************************************************************************
mbed_official 324:406fd2029f23 3136 * hw_ftfa_t - module struct
mbed_official 324:406fd2029f23 3137 ******************************************************************************/
mbed_official 324:406fd2029f23 3138 /*!
mbed_official 324:406fd2029f23 3139 * @brief All FTFA module registers.
mbed_official 324:406fd2029f23 3140 */
mbed_official 324:406fd2029f23 3141 #pragma pack(1)
mbed_official 324:406fd2029f23 3142 typedef struct _hw_ftfa
mbed_official 324:406fd2029f23 3143 {
mbed_official 324:406fd2029f23 3144 __IO hw_ftfa_fstat_t FSTAT; /*!< [0x0] Flash Status Register */
mbed_official 324:406fd2029f23 3145 __IO hw_ftfa_fcnfg_t FCNFG; /*!< [0x1] Flash Configuration Register */
mbed_official 324:406fd2029f23 3146 __I hw_ftfa_fsec_t FSEC; /*!< [0x2] Flash Security Register */
mbed_official 324:406fd2029f23 3147 __I hw_ftfa_fopt_t FOPT; /*!< [0x3] Flash Option Register */
mbed_official 324:406fd2029f23 3148 __IO hw_ftfa_fccob3_t FCCOB3; /*!< [0x4] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3149 __IO hw_ftfa_fccob2_t FCCOB2; /*!< [0x5] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3150 __IO hw_ftfa_fccob1_t FCCOB1; /*!< [0x6] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3151 __IO hw_ftfa_fccob0_t FCCOB0; /*!< [0x7] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3152 __IO hw_ftfa_fccob7_t FCCOB7; /*!< [0x8] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3153 __IO hw_ftfa_fccob6_t FCCOB6; /*!< [0x9] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3154 __IO hw_ftfa_fccob5_t FCCOB5; /*!< [0xA] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3155 __IO hw_ftfa_fccob4_t FCCOB4; /*!< [0xB] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3156 __IO hw_ftfa_fccobb_t FCCOBB; /*!< [0xC] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3157 __IO hw_ftfa_fccoba_t FCCOBA; /*!< [0xD] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3158 __IO hw_ftfa_fccob9_t FCCOB9; /*!< [0xE] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3159 __IO hw_ftfa_fccob8_t FCCOB8; /*!< [0xF] Flash Common Command Object Registers */
mbed_official 324:406fd2029f23 3160 __IO hw_ftfa_fprot3_t FPROT3; /*!< [0x10] Program Flash Protection Registers */
mbed_official 324:406fd2029f23 3161 __IO hw_ftfa_fprot2_t FPROT2; /*!< [0x11] Program Flash Protection Registers */
mbed_official 324:406fd2029f23 3162 __IO hw_ftfa_fprot1_t FPROT1; /*!< [0x12] Program Flash Protection Registers */
mbed_official 324:406fd2029f23 3163 __IO hw_ftfa_fprot0_t FPROT0; /*!< [0x13] Program Flash Protection Registers */
mbed_official 324:406fd2029f23 3164 uint8_t _reserved0[4];
mbed_official 324:406fd2029f23 3165 __I hw_ftfa_xacch3_t XACCH3; /*!< [0x18] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3166 __I hw_ftfa_xacch2_t XACCH2; /*!< [0x19] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3167 __I hw_ftfa_xacch1_t XACCH1; /*!< [0x1A] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3168 __I hw_ftfa_xacch0_t XACCH0; /*!< [0x1B] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3169 __I hw_ftfa_xaccl3_t XACCL3; /*!< [0x1C] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3170 __I hw_ftfa_xaccl2_t XACCL2; /*!< [0x1D] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3171 __I hw_ftfa_xaccl1_t XACCL1; /*!< [0x1E] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3172 __I hw_ftfa_xaccl0_t XACCL0; /*!< [0x1F] Execute-only Access Registers */
mbed_official 324:406fd2029f23 3173 __I hw_ftfa_sacch3_t SACCH3; /*!< [0x20] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3174 __I hw_ftfa_sacch2_t SACCH2; /*!< [0x21] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3175 __I hw_ftfa_sacch1_t SACCH1; /*!< [0x22] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3176 __I hw_ftfa_sacch0_t SACCH0; /*!< [0x23] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3177 __I hw_ftfa_saccl3_t SACCL3; /*!< [0x24] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3178 __I hw_ftfa_saccl2_t SACCL2; /*!< [0x25] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3179 __I hw_ftfa_saccl1_t SACCL1; /*!< [0x26] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3180 __I hw_ftfa_saccl0_t SACCL0; /*!< [0x27] Supervisor-only Access Registers */
mbed_official 324:406fd2029f23 3181 __I hw_ftfa_facss_t FACSS; /*!< [0x28] Flash Access Segment Size Register */
mbed_official 324:406fd2029f23 3182 uint8_t _reserved1[2];
mbed_official 324:406fd2029f23 3183 __I hw_ftfa_facsn_t FACSN; /*!< [0x2B] Flash Access Segment Number Register */
mbed_official 324:406fd2029f23 3184 } hw_ftfa_t;
mbed_official 324:406fd2029f23 3185 #pragma pack()
mbed_official 324:406fd2029f23 3186
mbed_official 324:406fd2029f23 3187 /*! @brief Macro to access all FTFA registers. */
mbed_official 324:406fd2029f23 3188 /*! @param x FTFA module instance base address. */
mbed_official 324:406fd2029f23 3189 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 3190 * use the '&' operator, like <code>&HW_FTFA(FTFA_BASE)</code>. */
mbed_official 324:406fd2029f23 3191 #define HW_FTFA(x) (*(hw_ftfa_t *)(x))
mbed_official 324:406fd2029f23 3192
mbed_official 324:406fd2029f23 3193 #endif /* __HW_FTFA_REGISTERS_H__ */
mbed_official 324:406fd2029f23 3194 /* EOF */