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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_fb.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_FB_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_FB_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 FB
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * FlexBus external bus interface
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_FB_CSARn - Chip Select Address Register
mbed_official 324:406fd2029f23 90 * - HW_FB_CSMRn - Chip Select Mask Register
mbed_official 324:406fd2029f23 91 * - HW_FB_CSCRn - Chip Select Control Register
mbed_official 324:406fd2029f23 92 * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
mbed_official 324:406fd2029f23 93 *
mbed_official 324:406fd2029f23 94 * - hw_fb_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 95 */
mbed_official 324:406fd2029f23 96
mbed_official 324:406fd2029f23 97 #define HW_FB_INSTANCE_COUNT (1U) /*!< Number of instances of the FB module. */
mbed_official 324:406fd2029f23 98
mbed_official 324:406fd2029f23 99 /*******************************************************************************
mbed_official 324:406fd2029f23 100 * HW_FB_CSARn - Chip Select Address Register
mbed_official 324:406fd2029f23 101 ******************************************************************************/
mbed_official 324:406fd2029f23 102
mbed_official 324:406fd2029f23 103 /*!
mbed_official 324:406fd2029f23 104 * @brief HW_FB_CSARn - Chip Select Address Register (RW)
mbed_official 324:406fd2029f23 105 *
mbed_official 324:406fd2029f23 106 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 107 *
mbed_official 324:406fd2029f23 108 * Specifies the associated chip-select's base address.
mbed_official 324:406fd2029f23 109 */
mbed_official 324:406fd2029f23 110 typedef union _hw_fb_csarn
mbed_official 324:406fd2029f23 111 {
mbed_official 324:406fd2029f23 112 uint32_t U;
mbed_official 324:406fd2029f23 113 struct _hw_fb_csarn_bitfields
mbed_official 324:406fd2029f23 114 {
mbed_official 324:406fd2029f23 115 uint32_t RESERVED0 : 16; /*!< [15:0] */
mbed_official 324:406fd2029f23 116 uint32_t BA : 16; /*!< [31:16] Base Address */
mbed_official 324:406fd2029f23 117 } B;
mbed_official 324:406fd2029f23 118 } hw_fb_csarn_t;
mbed_official 324:406fd2029f23 119
mbed_official 324:406fd2029f23 120 /*!
mbed_official 324:406fd2029f23 121 * @name Constants and macros for entire FB_CSARn register
mbed_official 324:406fd2029f23 122 */
mbed_official 324:406fd2029f23 123 /*@{*/
mbed_official 324:406fd2029f23 124 #define HW_FB_CSARn_COUNT (6U)
mbed_official 324:406fd2029f23 125
mbed_official 324:406fd2029f23 126 #define HW_FB_CSARn_ADDR(x, n) ((x) + 0x0U + (0xCU * (n)))
mbed_official 324:406fd2029f23 127
mbed_official 324:406fd2029f23 128 #define HW_FB_CSARn(x, n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(x, n))
mbed_official 324:406fd2029f23 129 #define HW_FB_CSARn_RD(x, n) (HW_FB_CSARn(x, n).U)
mbed_official 324:406fd2029f23 130 #define HW_FB_CSARn_WR(x, n, v) (HW_FB_CSARn(x, n).U = (v))
mbed_official 324:406fd2029f23 131 #define HW_FB_CSARn_SET(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 132 #define HW_FB_CSARn_CLR(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 133 #define HW_FB_CSARn_TOG(x, n, v) (HW_FB_CSARn_WR(x, n, HW_FB_CSARn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 134 /*@}*/
mbed_official 324:406fd2029f23 135
mbed_official 324:406fd2029f23 136 /*
mbed_official 324:406fd2029f23 137 * Constants & macros for individual FB_CSARn bitfields
mbed_official 324:406fd2029f23 138 */
mbed_official 324:406fd2029f23 139
mbed_official 324:406fd2029f23 140 /*!
mbed_official 324:406fd2029f23 141 * @name Register FB_CSARn, field BA[31:16] (RW)
mbed_official 324:406fd2029f23 142 *
mbed_official 324:406fd2029f23 143 * Defines the base address for memory dedicated to the associated chip-select.
mbed_official 324:406fd2029f23 144 * BA is compared to bits 31-16 on the internal address bus to determine if the
mbed_official 324:406fd2029f23 145 * associated chip-select's memory is being accessed. Because the FlexBus module
mbed_official 324:406fd2029f23 146 * is one of the slaves connected to the crossbar switch, it is only accessible
mbed_official 324:406fd2029f23 147 * within a certain memory range. See the chip memory map for the applicable
mbed_official 324:406fd2029f23 148 * FlexBus "expansion" address range for which the chip-selects can be active. Set the
mbed_official 324:406fd2029f23 149 * CSARn and CSMRn registers appropriately before accessing this region.
mbed_official 324:406fd2029f23 150 */
mbed_official 324:406fd2029f23 151 /*@{*/
mbed_official 324:406fd2029f23 152 #define BP_FB_CSARn_BA (16U) /*!< Bit position for FB_CSARn_BA. */
mbed_official 324:406fd2029f23 153 #define BM_FB_CSARn_BA (0xFFFF0000U) /*!< Bit mask for FB_CSARn_BA. */
mbed_official 324:406fd2029f23 154 #define BS_FB_CSARn_BA (16U) /*!< Bit field size in bits for FB_CSARn_BA. */
mbed_official 324:406fd2029f23 155
mbed_official 324:406fd2029f23 156 /*! @brief Read current value of the FB_CSARn_BA field. */
mbed_official 324:406fd2029f23 157 #define BR_FB_CSARn_BA(x, n) (HW_FB_CSARn(x, n).B.BA)
mbed_official 324:406fd2029f23 158
mbed_official 324:406fd2029f23 159 /*! @brief Format value for bitfield FB_CSARn_BA. */
mbed_official 324:406fd2029f23 160 #define BF_FB_CSARn_BA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSARn_BA) & BM_FB_CSARn_BA)
mbed_official 324:406fd2029f23 161
mbed_official 324:406fd2029f23 162 /*! @brief Set the BA field to a new value. */
mbed_official 324:406fd2029f23 163 #define BW_FB_CSARn_BA(x, n, v) (HW_FB_CSARn_WR(x, n, (HW_FB_CSARn_RD(x, n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
mbed_official 324:406fd2029f23 164 /*@}*/
mbed_official 324:406fd2029f23 165 /*******************************************************************************
mbed_official 324:406fd2029f23 166 * HW_FB_CSMRn - Chip Select Mask Register
mbed_official 324:406fd2029f23 167 ******************************************************************************/
mbed_official 324:406fd2029f23 168
mbed_official 324:406fd2029f23 169 /*!
mbed_official 324:406fd2029f23 170 * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
mbed_official 324:406fd2029f23 171 *
mbed_official 324:406fd2029f23 172 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 173 *
mbed_official 324:406fd2029f23 174 * Specifies the address mask and allowable access types for the associated
mbed_official 324:406fd2029f23 175 * chip-select.
mbed_official 324:406fd2029f23 176 */
mbed_official 324:406fd2029f23 177 typedef union _hw_fb_csmrn
mbed_official 324:406fd2029f23 178 {
mbed_official 324:406fd2029f23 179 uint32_t U;
mbed_official 324:406fd2029f23 180 struct _hw_fb_csmrn_bitfields
mbed_official 324:406fd2029f23 181 {
mbed_official 324:406fd2029f23 182 uint32_t V : 1; /*!< [0] Valid */
mbed_official 324:406fd2029f23 183 uint32_t RESERVED0 : 7; /*!< [7:1] */
mbed_official 324:406fd2029f23 184 uint32_t WP : 1; /*!< [8] Write Protect */
mbed_official 324:406fd2029f23 185 uint32_t RESERVED1 : 7; /*!< [15:9] */
mbed_official 324:406fd2029f23 186 uint32_t BAM : 16; /*!< [31:16] Base Address Mask */
mbed_official 324:406fd2029f23 187 } B;
mbed_official 324:406fd2029f23 188 } hw_fb_csmrn_t;
mbed_official 324:406fd2029f23 189
mbed_official 324:406fd2029f23 190 /*!
mbed_official 324:406fd2029f23 191 * @name Constants and macros for entire FB_CSMRn register
mbed_official 324:406fd2029f23 192 */
mbed_official 324:406fd2029f23 193 /*@{*/
mbed_official 324:406fd2029f23 194 #define HW_FB_CSMRn_COUNT (6U)
mbed_official 324:406fd2029f23 195
mbed_official 324:406fd2029f23 196 #define HW_FB_CSMRn_ADDR(x, n) ((x) + 0x4U + (0xCU * (n)))
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 #define HW_FB_CSMRn(x, n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(x, n))
mbed_official 324:406fd2029f23 199 #define HW_FB_CSMRn_RD(x, n) (HW_FB_CSMRn(x, n).U)
mbed_official 324:406fd2029f23 200 #define HW_FB_CSMRn_WR(x, n, v) (HW_FB_CSMRn(x, n).U = (v))
mbed_official 324:406fd2029f23 201 #define HW_FB_CSMRn_SET(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 202 #define HW_FB_CSMRn_CLR(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 203 #define HW_FB_CSMRn_TOG(x, n, v) (HW_FB_CSMRn_WR(x, n, HW_FB_CSMRn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 204 /*@}*/
mbed_official 324:406fd2029f23 205
mbed_official 324:406fd2029f23 206 /*
mbed_official 324:406fd2029f23 207 * Constants & macros for individual FB_CSMRn bitfields
mbed_official 324:406fd2029f23 208 */
mbed_official 324:406fd2029f23 209
mbed_official 324:406fd2029f23 210 /*!
mbed_official 324:406fd2029f23 211 * @name Register FB_CSMRn, field V[0] (RW)
mbed_official 324:406fd2029f23 212 *
mbed_official 324:406fd2029f23 213 * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
mbed_official 324:406fd2029f23 214 * Programmed chip-selects do not assert until the V bit is 1b (except for
mbed_official 324:406fd2029f23 215 * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
mbed_official 324:406fd2029f23 216 * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
mbed_official 324:406fd2029f23 217 * select initialization sequence to allow other chip selects to function as
mbed_official 324:406fd2029f23 218 * programmed.
mbed_official 324:406fd2029f23 219 *
mbed_official 324:406fd2029f23 220 * Values:
mbed_official 324:406fd2029f23 221 * - 0 - Chip-select is invalid.
mbed_official 324:406fd2029f23 222 * - 1 - Chip-select is valid.
mbed_official 324:406fd2029f23 223 */
mbed_official 324:406fd2029f23 224 /*@{*/
mbed_official 324:406fd2029f23 225 #define BP_FB_CSMRn_V (0U) /*!< Bit position for FB_CSMRn_V. */
mbed_official 324:406fd2029f23 226 #define BM_FB_CSMRn_V (0x00000001U) /*!< Bit mask for FB_CSMRn_V. */
mbed_official 324:406fd2029f23 227 #define BS_FB_CSMRn_V (1U) /*!< Bit field size in bits for FB_CSMRn_V. */
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*! @brief Read current value of the FB_CSMRn_V field. */
mbed_official 324:406fd2029f23 230 #define BR_FB_CSMRn_V(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V))
mbed_official 324:406fd2029f23 231
mbed_official 324:406fd2029f23 232 /*! @brief Format value for bitfield FB_CSMRn_V. */
mbed_official 324:406fd2029f23 233 #define BF_FB_CSMRn_V(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_V) & BM_FB_CSMRn_V)
mbed_official 324:406fd2029f23 234
mbed_official 324:406fd2029f23 235 /*! @brief Set the V field to a new value. */
mbed_official 324:406fd2029f23 236 #define BW_FB_CSMRn_V(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_V) = (v))
mbed_official 324:406fd2029f23 237 /*@}*/
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*!
mbed_official 324:406fd2029f23 240 * @name Register FB_CSMRn, field WP[8] (RW)
mbed_official 324:406fd2029f23 241 *
mbed_official 324:406fd2029f23 242 * Controls write accesses to the address range in the corresponding CSAR.
mbed_official 324:406fd2029f23 243 *
mbed_official 324:406fd2029f23 244 * Values:
mbed_official 324:406fd2029f23 245 * - 0 - Write accesses are allowed.
mbed_official 324:406fd2029f23 246 * - 1 - Write accesses are not allowed. Attempting to write to the range of
mbed_official 324:406fd2029f23 247 * addresses for which the WP bit is set results in a bus error termination of
mbed_official 324:406fd2029f23 248 * the internal cycle and no external cycle.
mbed_official 324:406fd2029f23 249 */
mbed_official 324:406fd2029f23 250 /*@{*/
mbed_official 324:406fd2029f23 251 #define BP_FB_CSMRn_WP (8U) /*!< Bit position for FB_CSMRn_WP. */
mbed_official 324:406fd2029f23 252 #define BM_FB_CSMRn_WP (0x00000100U) /*!< Bit mask for FB_CSMRn_WP. */
mbed_official 324:406fd2029f23 253 #define BS_FB_CSMRn_WP (1U) /*!< Bit field size in bits for FB_CSMRn_WP. */
mbed_official 324:406fd2029f23 254
mbed_official 324:406fd2029f23 255 /*! @brief Read current value of the FB_CSMRn_WP field. */
mbed_official 324:406fd2029f23 256 #define BR_FB_CSMRn_WP(x, n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP))
mbed_official 324:406fd2029f23 257
mbed_official 324:406fd2029f23 258 /*! @brief Format value for bitfield FB_CSMRn_WP. */
mbed_official 324:406fd2029f23 259 #define BF_FB_CSMRn_WP(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_WP) & BM_FB_CSMRn_WP)
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*! @brief Set the WP field to a new value. */
mbed_official 324:406fd2029f23 262 #define BW_FB_CSMRn_WP(x, n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(x, n), BP_FB_CSMRn_WP) = (v))
mbed_official 324:406fd2029f23 263 /*@}*/
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*!
mbed_official 324:406fd2029f23 266 * @name Register FB_CSMRn, field BAM[31:16] (RW)
mbed_official 324:406fd2029f23 267 *
mbed_official 324:406fd2029f23 268 * Defines the associated chip-select's block size by masking address bits.
mbed_official 324:406fd2029f23 269 *
mbed_official 324:406fd2029f23 270 * Values:
mbed_official 324:406fd2029f23 271 * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
mbed_official 324:406fd2029f23 272 * - 1 - The corresponding address bit in CSAR is a don't care in the
mbed_official 324:406fd2029f23 273 * chip-select decode.
mbed_official 324:406fd2029f23 274 */
mbed_official 324:406fd2029f23 275 /*@{*/
mbed_official 324:406fd2029f23 276 #define BP_FB_CSMRn_BAM (16U) /*!< Bit position for FB_CSMRn_BAM. */
mbed_official 324:406fd2029f23 277 #define BM_FB_CSMRn_BAM (0xFFFF0000U) /*!< Bit mask for FB_CSMRn_BAM. */
mbed_official 324:406fd2029f23 278 #define BS_FB_CSMRn_BAM (16U) /*!< Bit field size in bits for FB_CSMRn_BAM. */
mbed_official 324:406fd2029f23 279
mbed_official 324:406fd2029f23 280 /*! @brief Read current value of the FB_CSMRn_BAM field. */
mbed_official 324:406fd2029f23 281 #define BR_FB_CSMRn_BAM(x, n) (HW_FB_CSMRn(x, n).B.BAM)
mbed_official 324:406fd2029f23 282
mbed_official 324:406fd2029f23 283 /*! @brief Format value for bitfield FB_CSMRn_BAM. */
mbed_official 324:406fd2029f23 284 #define BF_FB_CSMRn_BAM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSMRn_BAM) & BM_FB_CSMRn_BAM)
mbed_official 324:406fd2029f23 285
mbed_official 324:406fd2029f23 286 /*! @brief Set the BAM field to a new value. */
mbed_official 324:406fd2029f23 287 #define BW_FB_CSMRn_BAM(x, n, v) (HW_FB_CSMRn_WR(x, n, (HW_FB_CSMRn_RD(x, n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
mbed_official 324:406fd2029f23 288 /*@}*/
mbed_official 324:406fd2029f23 289 /*******************************************************************************
mbed_official 324:406fd2029f23 290 * HW_FB_CSCRn - Chip Select Control Register
mbed_official 324:406fd2029f23 291 ******************************************************************************/
mbed_official 324:406fd2029f23 292
mbed_official 324:406fd2029f23 293 /*!
mbed_official 324:406fd2029f23 294 * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
mbed_official 324:406fd2029f23 295 *
mbed_official 324:406fd2029f23 296 * Reset value: 0x003FFC00U
mbed_official 324:406fd2029f23 297 *
mbed_official 324:406fd2029f23 298 * Controls the auto-acknowledge, address setup and hold times, port size, burst
mbed_official 324:406fd2029f23 299 * capability, and number of wait states for the associated chip select. To
mbed_official 324:406fd2029f23 300 * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
mbed_official 324:406fd2029f23 301 * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
mbed_official 324:406fd2029f23 302 * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
mbed_official 324:406fd2029f23 303 * particular chip for information on the exact CSCR0 reset value.
mbed_official 324:406fd2029f23 304 */
mbed_official 324:406fd2029f23 305 typedef union _hw_fb_cscrn
mbed_official 324:406fd2029f23 306 {
mbed_official 324:406fd2029f23 307 uint32_t U;
mbed_official 324:406fd2029f23 308 struct _hw_fb_cscrn_bitfields
mbed_official 324:406fd2029f23 309 {
mbed_official 324:406fd2029f23 310 uint32_t RESERVED0 : 3; /*!< [2:0] */
mbed_official 324:406fd2029f23 311 uint32_t BSTW : 1; /*!< [3] Burst-Write Enable */
mbed_official 324:406fd2029f23 312 uint32_t BSTR : 1; /*!< [4] Burst-Read Enable */
mbed_official 324:406fd2029f23 313 uint32_t BEM : 1; /*!< [5] Byte-Enable Mode */
mbed_official 324:406fd2029f23 314 uint32_t PS : 2; /*!< [7:6] Port Size */
mbed_official 324:406fd2029f23 315 uint32_t AA : 1; /*!< [8] Auto-Acknowledge Enable */
mbed_official 324:406fd2029f23 316 uint32_t BLS : 1; /*!< [9] Byte-Lane Shift */
mbed_official 324:406fd2029f23 317 uint32_t WS : 6; /*!< [15:10] Wait States */
mbed_official 324:406fd2029f23 318 uint32_t WRAH : 2; /*!< [17:16] Write Address Hold or Deselect */
mbed_official 324:406fd2029f23 319 uint32_t RDAH : 2; /*!< [19:18] Read Address Hold or Deselect */
mbed_official 324:406fd2029f23 320 uint32_t ASET : 2; /*!< [21:20] Address Setup */
mbed_official 324:406fd2029f23 321 uint32_t EXTS : 1; /*!< [22] */
mbed_official 324:406fd2029f23 322 uint32_t SWSEN : 1; /*!< [23] Secondary Wait State Enable */
mbed_official 324:406fd2029f23 323 uint32_t RESERVED1 : 2; /*!< [25:24] */
mbed_official 324:406fd2029f23 324 uint32_t SWS : 6; /*!< [31:26] Secondary Wait States */
mbed_official 324:406fd2029f23 325 } B;
mbed_official 324:406fd2029f23 326 } hw_fb_cscrn_t;
mbed_official 324:406fd2029f23 327
mbed_official 324:406fd2029f23 328 /*!
mbed_official 324:406fd2029f23 329 * @name Constants and macros for entire FB_CSCRn register
mbed_official 324:406fd2029f23 330 */
mbed_official 324:406fd2029f23 331 /*@{*/
mbed_official 324:406fd2029f23 332 #define HW_FB_CSCRn_COUNT (6U)
mbed_official 324:406fd2029f23 333
mbed_official 324:406fd2029f23 334 #define HW_FB_CSCRn_ADDR(x, n) ((x) + 0x8U + (0xCU * (n)))
mbed_official 324:406fd2029f23 335
mbed_official 324:406fd2029f23 336 #define HW_FB_CSCRn(x, n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(x, n))
mbed_official 324:406fd2029f23 337 #define HW_FB_CSCRn_RD(x, n) (HW_FB_CSCRn(x, n).U)
mbed_official 324:406fd2029f23 338 #define HW_FB_CSCRn_WR(x, n, v) (HW_FB_CSCRn(x, n).U = (v))
mbed_official 324:406fd2029f23 339 #define HW_FB_CSCRn_SET(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 340 #define HW_FB_CSCRn_CLR(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 341 #define HW_FB_CSCRn_TOG(x, n, v) (HW_FB_CSCRn_WR(x, n, HW_FB_CSCRn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 342 /*@}*/
mbed_official 324:406fd2029f23 343
mbed_official 324:406fd2029f23 344 /*
mbed_official 324:406fd2029f23 345 * Constants & macros for individual FB_CSCRn bitfields
mbed_official 324:406fd2029f23 346 */
mbed_official 324:406fd2029f23 347
mbed_official 324:406fd2029f23 348 /*!
mbed_official 324:406fd2029f23 349 * @name Register FB_CSCRn, field BSTW[3] (RW)
mbed_official 324:406fd2029f23 350 *
mbed_official 324:406fd2029f23 351 * Specifies whether burst writes are enabled for memory associated with each
mbed_official 324:406fd2029f23 352 * chip select.
mbed_official 324:406fd2029f23 353 *
mbed_official 324:406fd2029f23 354 * Values:
mbed_official 324:406fd2029f23 355 * - 0 - Disabled. Data exceeding the specified port size is broken into
mbed_official 324:406fd2029f23 356 * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
mbed_official 324:406fd2029f23 357 * port takes four byte writes.
mbed_official 324:406fd2029f23 358 * - 1 - Enabled. Enables burst write of data larger than the specified port
mbed_official 324:406fd2029f23 359 * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
mbed_official 324:406fd2029f23 360 * ports, and line writes to 8-, 16-, and 32-bit ports.
mbed_official 324:406fd2029f23 361 */
mbed_official 324:406fd2029f23 362 /*@{*/
mbed_official 324:406fd2029f23 363 #define BP_FB_CSCRn_BSTW (3U) /*!< Bit position for FB_CSCRn_BSTW. */
mbed_official 324:406fd2029f23 364 #define BM_FB_CSCRn_BSTW (0x00000008U) /*!< Bit mask for FB_CSCRn_BSTW. */
mbed_official 324:406fd2029f23 365 #define BS_FB_CSCRn_BSTW (1U) /*!< Bit field size in bits for FB_CSCRn_BSTW. */
mbed_official 324:406fd2029f23 366
mbed_official 324:406fd2029f23 367 /*! @brief Read current value of the FB_CSCRn_BSTW field. */
mbed_official 324:406fd2029f23 368 #define BR_FB_CSCRn_BSTW(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW))
mbed_official 324:406fd2029f23 369
mbed_official 324:406fd2029f23 370 /*! @brief Format value for bitfield FB_CSCRn_BSTW. */
mbed_official 324:406fd2029f23 371 #define BF_FB_CSCRn_BSTW(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTW) & BM_FB_CSCRn_BSTW)
mbed_official 324:406fd2029f23 372
mbed_official 324:406fd2029f23 373 /*! @brief Set the BSTW field to a new value. */
mbed_official 324:406fd2029f23 374 #define BW_FB_CSCRn_BSTW(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTW) = (v))
mbed_official 324:406fd2029f23 375 /*@}*/
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*!
mbed_official 324:406fd2029f23 378 * @name Register FB_CSCRn, field BSTR[4] (RW)
mbed_official 324:406fd2029f23 379 *
mbed_official 324:406fd2029f23 380 * Specifies whether burst reads are enabled for memory associated with each
mbed_official 324:406fd2029f23 381 * chip select.
mbed_official 324:406fd2029f23 382 *
mbed_official 324:406fd2029f23 383 * Values:
mbed_official 324:406fd2029f23 384 * - 0 - Disabled. Data exceeding the specified port size is broken into
mbed_official 324:406fd2029f23 385 * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
mbed_official 324:406fd2029f23 386 * port is broken into four 8-bit reads.
mbed_official 324:406fd2029f23 387 * - 1 - Enabled. Enables data burst reads larger than the specified port size,
mbed_official 324:406fd2029f23 388 * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
mbed_official 324:406fd2029f23 389 * ports, and line reads from 8-, 16-, and 32-bit ports.
mbed_official 324:406fd2029f23 390 */
mbed_official 324:406fd2029f23 391 /*@{*/
mbed_official 324:406fd2029f23 392 #define BP_FB_CSCRn_BSTR (4U) /*!< Bit position for FB_CSCRn_BSTR. */
mbed_official 324:406fd2029f23 393 #define BM_FB_CSCRn_BSTR (0x00000010U) /*!< Bit mask for FB_CSCRn_BSTR. */
mbed_official 324:406fd2029f23 394 #define BS_FB_CSCRn_BSTR (1U) /*!< Bit field size in bits for FB_CSCRn_BSTR. */
mbed_official 324:406fd2029f23 395
mbed_official 324:406fd2029f23 396 /*! @brief Read current value of the FB_CSCRn_BSTR field. */
mbed_official 324:406fd2029f23 397 #define BR_FB_CSCRn_BSTR(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR))
mbed_official 324:406fd2029f23 398
mbed_official 324:406fd2029f23 399 /*! @brief Format value for bitfield FB_CSCRn_BSTR. */
mbed_official 324:406fd2029f23 400 #define BF_FB_CSCRn_BSTR(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BSTR) & BM_FB_CSCRn_BSTR)
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /*! @brief Set the BSTR field to a new value. */
mbed_official 324:406fd2029f23 403 #define BW_FB_CSCRn_BSTR(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BSTR) = (v))
mbed_official 324:406fd2029f23 404 /*@}*/
mbed_official 324:406fd2029f23 405
mbed_official 324:406fd2029f23 406 /*!
mbed_official 324:406fd2029f23 407 * @name Register FB_CSCRn, field BEM[5] (RW)
mbed_official 324:406fd2029f23 408 *
mbed_official 324:406fd2029f23 409 * Specifies whether the corresponding FB_BE is asserted for read accesses.
mbed_official 324:406fd2029f23 410 * Certain memories have byte enables that must be asserted during reads and writes.
mbed_official 324:406fd2029f23 411 * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
mbed_official 324:406fd2029f23 412 * of byte enable support for these SRAMs.
mbed_official 324:406fd2029f23 413 *
mbed_official 324:406fd2029f23 414 * Values:
mbed_official 324:406fd2029f23 415 * - 0 - FB_BE is asserted for data write only.
mbed_official 324:406fd2029f23 416 * - 1 - FB_BE is asserted for data read and write accesses.
mbed_official 324:406fd2029f23 417 */
mbed_official 324:406fd2029f23 418 /*@{*/
mbed_official 324:406fd2029f23 419 #define BP_FB_CSCRn_BEM (5U) /*!< Bit position for FB_CSCRn_BEM. */
mbed_official 324:406fd2029f23 420 #define BM_FB_CSCRn_BEM (0x00000020U) /*!< Bit mask for FB_CSCRn_BEM. */
mbed_official 324:406fd2029f23 421 #define BS_FB_CSCRn_BEM (1U) /*!< Bit field size in bits for FB_CSCRn_BEM. */
mbed_official 324:406fd2029f23 422
mbed_official 324:406fd2029f23 423 /*! @brief Read current value of the FB_CSCRn_BEM field. */
mbed_official 324:406fd2029f23 424 #define BR_FB_CSCRn_BEM(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM))
mbed_official 324:406fd2029f23 425
mbed_official 324:406fd2029f23 426 /*! @brief Format value for bitfield FB_CSCRn_BEM. */
mbed_official 324:406fd2029f23 427 #define BF_FB_CSCRn_BEM(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BEM) & BM_FB_CSCRn_BEM)
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429 /*! @brief Set the BEM field to a new value. */
mbed_official 324:406fd2029f23 430 #define BW_FB_CSCRn_BEM(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BEM) = (v))
mbed_official 324:406fd2029f23 431 /*@}*/
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*!
mbed_official 324:406fd2029f23 434 * @name Register FB_CSCRn, field PS[7:6] (RW)
mbed_official 324:406fd2029f23 435 *
mbed_official 324:406fd2029f23 436 * Specifies the data port width of the associated chip-select, and determines
mbed_official 324:406fd2029f23 437 * where data is driven during write cycles and where data is sampled during read
mbed_official 324:406fd2029f23 438 * cycles.
mbed_official 324:406fd2029f23 439 *
mbed_official 324:406fd2029f23 440 * Values:
mbed_official 324:406fd2029f23 441 * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
mbed_official 324:406fd2029f23 442 * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
mbed_official 324:406fd2029f23 443 * BLS is 0b, or FB_D[7:0] when BLS is 1b.
mbed_official 324:406fd2029f23 444 */
mbed_official 324:406fd2029f23 445 /*@{*/
mbed_official 324:406fd2029f23 446 #define BP_FB_CSCRn_PS (6U) /*!< Bit position for FB_CSCRn_PS. */
mbed_official 324:406fd2029f23 447 #define BM_FB_CSCRn_PS (0x000000C0U) /*!< Bit mask for FB_CSCRn_PS. */
mbed_official 324:406fd2029f23 448 #define BS_FB_CSCRn_PS (2U) /*!< Bit field size in bits for FB_CSCRn_PS. */
mbed_official 324:406fd2029f23 449
mbed_official 324:406fd2029f23 450 /*! @brief Read current value of the FB_CSCRn_PS field. */
mbed_official 324:406fd2029f23 451 #define BR_FB_CSCRn_PS(x, n) (HW_FB_CSCRn(x, n).B.PS)
mbed_official 324:406fd2029f23 452
mbed_official 324:406fd2029f23 453 /*! @brief Format value for bitfield FB_CSCRn_PS. */
mbed_official 324:406fd2029f23 454 #define BF_FB_CSCRn_PS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_PS) & BM_FB_CSCRn_PS)
mbed_official 324:406fd2029f23 455
mbed_official 324:406fd2029f23 456 /*! @brief Set the PS field to a new value. */
mbed_official 324:406fd2029f23 457 #define BW_FB_CSCRn_PS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
mbed_official 324:406fd2029f23 458 /*@}*/
mbed_official 324:406fd2029f23 459
mbed_official 324:406fd2029f23 460 /*!
mbed_official 324:406fd2029f23 461 * @name Register FB_CSCRn, field AA[8] (RW)
mbed_official 324:406fd2029f23 462 *
mbed_official 324:406fd2029f23 463 * Asserts the internal transfer acknowledge for accesses specified by the
mbed_official 324:406fd2029f23 464 * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
mbed_official 324:406fd2029f23 465 * asserts an external FB_TA before the wait-state countdown asserts the
mbed_official 324:406fd2029f23 466 * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
mbed_official 324:406fd2029f23 467 * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
mbed_official 324:406fd2029f23 468 *
mbed_official 324:406fd2029f23 469 * Values:
mbed_official 324:406fd2029f23 470 * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
mbed_official 324:406fd2029f23 471 * terminated externally.
mbed_official 324:406fd2029f23 472 * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
mbed_official 324:406fd2029f23 473 */
mbed_official 324:406fd2029f23 474 /*@{*/
mbed_official 324:406fd2029f23 475 #define BP_FB_CSCRn_AA (8U) /*!< Bit position for FB_CSCRn_AA. */
mbed_official 324:406fd2029f23 476 #define BM_FB_CSCRn_AA (0x00000100U) /*!< Bit mask for FB_CSCRn_AA. */
mbed_official 324:406fd2029f23 477 #define BS_FB_CSCRn_AA (1U) /*!< Bit field size in bits for FB_CSCRn_AA. */
mbed_official 324:406fd2029f23 478
mbed_official 324:406fd2029f23 479 /*! @brief Read current value of the FB_CSCRn_AA field. */
mbed_official 324:406fd2029f23 480 #define BR_FB_CSCRn_AA(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA))
mbed_official 324:406fd2029f23 481
mbed_official 324:406fd2029f23 482 /*! @brief Format value for bitfield FB_CSCRn_AA. */
mbed_official 324:406fd2029f23 483 #define BF_FB_CSCRn_AA(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_AA) & BM_FB_CSCRn_AA)
mbed_official 324:406fd2029f23 484
mbed_official 324:406fd2029f23 485 /*! @brief Set the AA field to a new value. */
mbed_official 324:406fd2029f23 486 #define BW_FB_CSCRn_AA(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_AA) = (v))
mbed_official 324:406fd2029f23 487 /*@}*/
mbed_official 324:406fd2029f23 488
mbed_official 324:406fd2029f23 489 /*!
mbed_official 324:406fd2029f23 490 * @name Register FB_CSCRn, field BLS[9] (RW)
mbed_official 324:406fd2029f23 491 *
mbed_official 324:406fd2029f23 492 * Specifies if data on FB_AD appears left-aligned or right-aligned during the
mbed_official 324:406fd2029f23 493 * data phase of a FlexBus access.
mbed_official 324:406fd2029f23 494 *
mbed_official 324:406fd2029f23 495 * Values:
mbed_official 324:406fd2029f23 496 * - 0 - Not shifted. Data is left-aligned on FB_AD.
mbed_official 324:406fd2029f23 497 * - 1 - Shifted. Data is right-aligned on FB_AD.
mbed_official 324:406fd2029f23 498 */
mbed_official 324:406fd2029f23 499 /*@{*/
mbed_official 324:406fd2029f23 500 #define BP_FB_CSCRn_BLS (9U) /*!< Bit position for FB_CSCRn_BLS. */
mbed_official 324:406fd2029f23 501 #define BM_FB_CSCRn_BLS (0x00000200U) /*!< Bit mask for FB_CSCRn_BLS. */
mbed_official 324:406fd2029f23 502 #define BS_FB_CSCRn_BLS (1U) /*!< Bit field size in bits for FB_CSCRn_BLS. */
mbed_official 324:406fd2029f23 503
mbed_official 324:406fd2029f23 504 /*! @brief Read current value of the FB_CSCRn_BLS field. */
mbed_official 324:406fd2029f23 505 #define BR_FB_CSCRn_BLS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS))
mbed_official 324:406fd2029f23 506
mbed_official 324:406fd2029f23 507 /*! @brief Format value for bitfield FB_CSCRn_BLS. */
mbed_official 324:406fd2029f23 508 #define BF_FB_CSCRn_BLS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_BLS) & BM_FB_CSCRn_BLS)
mbed_official 324:406fd2029f23 509
mbed_official 324:406fd2029f23 510 /*! @brief Set the BLS field to a new value. */
mbed_official 324:406fd2029f23 511 #define BW_FB_CSCRn_BLS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_BLS) = (v))
mbed_official 324:406fd2029f23 512 /*@}*/
mbed_official 324:406fd2029f23 513
mbed_official 324:406fd2029f23 514 /*!
mbed_official 324:406fd2029f23 515 * @name Register FB_CSCRn, field WS[15:10] (RW)
mbed_official 324:406fd2029f23 516 *
mbed_official 324:406fd2029f23 517 * Specifies the number of wait states inserted after FlexBus asserts the
mbed_official 324:406fd2029f23 518 * associated chip-select and before an internal transfer acknowledge is generated (WS
mbed_official 324:406fd2029f23 519 * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
mbed_official 324:406fd2029f23 520 */
mbed_official 324:406fd2029f23 521 /*@{*/
mbed_official 324:406fd2029f23 522 #define BP_FB_CSCRn_WS (10U) /*!< Bit position for FB_CSCRn_WS. */
mbed_official 324:406fd2029f23 523 #define BM_FB_CSCRn_WS (0x0000FC00U) /*!< Bit mask for FB_CSCRn_WS. */
mbed_official 324:406fd2029f23 524 #define BS_FB_CSCRn_WS (6U) /*!< Bit field size in bits for FB_CSCRn_WS. */
mbed_official 324:406fd2029f23 525
mbed_official 324:406fd2029f23 526 /*! @brief Read current value of the FB_CSCRn_WS field. */
mbed_official 324:406fd2029f23 527 #define BR_FB_CSCRn_WS(x, n) (HW_FB_CSCRn(x, n).B.WS)
mbed_official 324:406fd2029f23 528
mbed_official 324:406fd2029f23 529 /*! @brief Format value for bitfield FB_CSCRn_WS. */
mbed_official 324:406fd2029f23 530 #define BF_FB_CSCRn_WS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WS) & BM_FB_CSCRn_WS)
mbed_official 324:406fd2029f23 531
mbed_official 324:406fd2029f23 532 /*! @brief Set the WS field to a new value. */
mbed_official 324:406fd2029f23 533 #define BW_FB_CSCRn_WS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
mbed_official 324:406fd2029f23 534 /*@}*/
mbed_official 324:406fd2029f23 535
mbed_official 324:406fd2029f23 536 /*!
mbed_official 324:406fd2029f23 537 * @name Register FB_CSCRn, field WRAH[17:16] (RW)
mbed_official 324:406fd2029f23 538 *
mbed_official 324:406fd2029f23 539 * Controls the address, data, and attribute hold time after the termination of
mbed_official 324:406fd2029f23 540 * a write cycle that hits in the associated chip-select's address space. The
mbed_official 324:406fd2029f23 541 * hold time applies only at the end of a transfer. Therefore, during a burst
mbed_official 324:406fd2029f23 542 * transfer or a transfer to a port size smaller than the transfer size, the hold time
mbed_official 324:406fd2029f23 543 * is only added after the last bus cycle.
mbed_official 324:406fd2029f23 544 *
mbed_official 324:406fd2029f23 545 * Values:
mbed_official 324:406fd2029f23 546 * - 00 - 1 cycle (default for all but FB_CS0 )
mbed_official 324:406fd2029f23 547 * - 01 - 2 cycles
mbed_official 324:406fd2029f23 548 * - 10 - 3 cycles
mbed_official 324:406fd2029f23 549 * - 11 - 4 cycles (default for FB_CS0 )
mbed_official 324:406fd2029f23 550 */
mbed_official 324:406fd2029f23 551 /*@{*/
mbed_official 324:406fd2029f23 552 #define BP_FB_CSCRn_WRAH (16U) /*!< Bit position for FB_CSCRn_WRAH. */
mbed_official 324:406fd2029f23 553 #define BM_FB_CSCRn_WRAH (0x00030000U) /*!< Bit mask for FB_CSCRn_WRAH. */
mbed_official 324:406fd2029f23 554 #define BS_FB_CSCRn_WRAH (2U) /*!< Bit field size in bits for FB_CSCRn_WRAH. */
mbed_official 324:406fd2029f23 555
mbed_official 324:406fd2029f23 556 /*! @brief Read current value of the FB_CSCRn_WRAH field. */
mbed_official 324:406fd2029f23 557 #define BR_FB_CSCRn_WRAH(x, n) (HW_FB_CSCRn(x, n).B.WRAH)
mbed_official 324:406fd2029f23 558
mbed_official 324:406fd2029f23 559 /*! @brief Format value for bitfield FB_CSCRn_WRAH. */
mbed_official 324:406fd2029f23 560 #define BF_FB_CSCRn_WRAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_WRAH) & BM_FB_CSCRn_WRAH)
mbed_official 324:406fd2029f23 561
mbed_official 324:406fd2029f23 562 /*! @brief Set the WRAH field to a new value. */
mbed_official 324:406fd2029f23 563 #define BW_FB_CSCRn_WRAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
mbed_official 324:406fd2029f23 564 /*@}*/
mbed_official 324:406fd2029f23 565
mbed_official 324:406fd2029f23 566 /*!
mbed_official 324:406fd2029f23 567 * @name Register FB_CSCRn, field RDAH[19:18] (RW)
mbed_official 324:406fd2029f23 568 *
mbed_official 324:406fd2029f23 569 * Controls the address and attribute hold time after the termination during a
mbed_official 324:406fd2029f23 570 * read cycle that hits in the associated chip-select's address space. The hold
mbed_official 324:406fd2029f23 571 * time applies only at the end of a transfer. Therefore, during a burst transfer
mbed_official 324:406fd2029f23 572 * or a transfer to a port size smaller than the transfer size, the hold time is
mbed_official 324:406fd2029f23 573 * only added after the last bus cycle. The number of cycles the address and
mbed_official 324:406fd2029f23 574 * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
mbed_official 324:406fd2029f23 575 *
mbed_official 324:406fd2029f23 576 * Values:
mbed_official 324:406fd2029f23 577 * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
mbed_official 324:406fd2029f23 578 * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
mbed_official 324:406fd2029f23 579 * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
mbed_official 324:406fd2029f23 580 * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
mbed_official 324:406fd2029f23 581 */
mbed_official 324:406fd2029f23 582 /*@{*/
mbed_official 324:406fd2029f23 583 #define BP_FB_CSCRn_RDAH (18U) /*!< Bit position for FB_CSCRn_RDAH. */
mbed_official 324:406fd2029f23 584 #define BM_FB_CSCRn_RDAH (0x000C0000U) /*!< Bit mask for FB_CSCRn_RDAH. */
mbed_official 324:406fd2029f23 585 #define BS_FB_CSCRn_RDAH (2U) /*!< Bit field size in bits for FB_CSCRn_RDAH. */
mbed_official 324:406fd2029f23 586
mbed_official 324:406fd2029f23 587 /*! @brief Read current value of the FB_CSCRn_RDAH field. */
mbed_official 324:406fd2029f23 588 #define BR_FB_CSCRn_RDAH(x, n) (HW_FB_CSCRn(x, n).B.RDAH)
mbed_official 324:406fd2029f23 589
mbed_official 324:406fd2029f23 590 /*! @brief Format value for bitfield FB_CSCRn_RDAH. */
mbed_official 324:406fd2029f23 591 #define BF_FB_CSCRn_RDAH(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_RDAH) & BM_FB_CSCRn_RDAH)
mbed_official 324:406fd2029f23 592
mbed_official 324:406fd2029f23 593 /*! @brief Set the RDAH field to a new value. */
mbed_official 324:406fd2029f23 594 #define BW_FB_CSCRn_RDAH(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
mbed_official 324:406fd2029f23 595 /*@}*/
mbed_official 324:406fd2029f23 596
mbed_official 324:406fd2029f23 597 /*!
mbed_official 324:406fd2029f23 598 * @name Register FB_CSCRn, field ASET[21:20] (RW)
mbed_official 324:406fd2029f23 599 *
mbed_official 324:406fd2029f23 600 * Controls when the chip-select is asserted with respect to assertion of a
mbed_official 324:406fd2029f23 601 * valid address and attributes.
mbed_official 324:406fd2029f23 602 *
mbed_official 324:406fd2029f23 603 * Values:
mbed_official 324:406fd2029f23 604 * - 00 - Assert FB_CSn on the first rising clock edge after the address is
mbed_official 324:406fd2029f23 605 * asserted (default for all but FB_CS0 ).
mbed_official 324:406fd2029f23 606 * - 01 - Assert FB_CSn on the second rising clock edge after the address is
mbed_official 324:406fd2029f23 607 * asserted.
mbed_official 324:406fd2029f23 608 * - 10 - Assert FB_CSn on the third rising clock edge after the address is
mbed_official 324:406fd2029f23 609 * asserted.
mbed_official 324:406fd2029f23 610 * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
mbed_official 324:406fd2029f23 611 * asserted (default for FB_CS0 ).
mbed_official 324:406fd2029f23 612 */
mbed_official 324:406fd2029f23 613 /*@{*/
mbed_official 324:406fd2029f23 614 #define BP_FB_CSCRn_ASET (20U) /*!< Bit position for FB_CSCRn_ASET. */
mbed_official 324:406fd2029f23 615 #define BM_FB_CSCRn_ASET (0x00300000U) /*!< Bit mask for FB_CSCRn_ASET. */
mbed_official 324:406fd2029f23 616 #define BS_FB_CSCRn_ASET (2U) /*!< Bit field size in bits for FB_CSCRn_ASET. */
mbed_official 324:406fd2029f23 617
mbed_official 324:406fd2029f23 618 /*! @brief Read current value of the FB_CSCRn_ASET field. */
mbed_official 324:406fd2029f23 619 #define BR_FB_CSCRn_ASET(x, n) (HW_FB_CSCRn(x, n).B.ASET)
mbed_official 324:406fd2029f23 620
mbed_official 324:406fd2029f23 621 /*! @brief Format value for bitfield FB_CSCRn_ASET. */
mbed_official 324:406fd2029f23 622 #define BF_FB_CSCRn_ASET(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_ASET) & BM_FB_CSCRn_ASET)
mbed_official 324:406fd2029f23 623
mbed_official 324:406fd2029f23 624 /*! @brief Set the ASET field to a new value. */
mbed_official 324:406fd2029f23 625 #define BW_FB_CSCRn_ASET(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
mbed_official 324:406fd2029f23 626 /*@}*/
mbed_official 324:406fd2029f23 627
mbed_official 324:406fd2029f23 628 /*!
mbed_official 324:406fd2029f23 629 * @name Register FB_CSCRn, field EXTS[22] (RW)
mbed_official 324:406fd2029f23 630 *
mbed_official 324:406fd2029f23 631 * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
mbed_official 324:406fd2029f23 632 * /FB_ALE is asserted.
mbed_official 324:406fd2029f23 633 *
mbed_official 324:406fd2029f23 634 * Values:
mbed_official 324:406fd2029f23 635 * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
mbed_official 324:406fd2029f23 636 * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
mbed_official 324:406fd2029f23 637 * edge after FB_CSn asserts.
mbed_official 324:406fd2029f23 638 */
mbed_official 324:406fd2029f23 639 /*@{*/
mbed_official 324:406fd2029f23 640 #define BP_FB_CSCRn_EXTS (22U) /*!< Bit position for FB_CSCRn_EXTS. */
mbed_official 324:406fd2029f23 641 #define BM_FB_CSCRn_EXTS (0x00400000U) /*!< Bit mask for FB_CSCRn_EXTS. */
mbed_official 324:406fd2029f23 642 #define BS_FB_CSCRn_EXTS (1U) /*!< Bit field size in bits for FB_CSCRn_EXTS. */
mbed_official 324:406fd2029f23 643
mbed_official 324:406fd2029f23 644 /*! @brief Read current value of the FB_CSCRn_EXTS field. */
mbed_official 324:406fd2029f23 645 #define BR_FB_CSCRn_EXTS(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS))
mbed_official 324:406fd2029f23 646
mbed_official 324:406fd2029f23 647 /*! @brief Format value for bitfield FB_CSCRn_EXTS. */
mbed_official 324:406fd2029f23 648 #define BF_FB_CSCRn_EXTS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_EXTS) & BM_FB_CSCRn_EXTS)
mbed_official 324:406fd2029f23 649
mbed_official 324:406fd2029f23 650 /*! @brief Set the EXTS field to a new value. */
mbed_official 324:406fd2029f23 651 #define BW_FB_CSCRn_EXTS(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_EXTS) = (v))
mbed_official 324:406fd2029f23 652 /*@}*/
mbed_official 324:406fd2029f23 653
mbed_official 324:406fd2029f23 654 /*!
mbed_official 324:406fd2029f23 655 * @name Register FB_CSCRn, field SWSEN[23] (RW)
mbed_official 324:406fd2029f23 656 *
mbed_official 324:406fd2029f23 657 * Values:
mbed_official 324:406fd2029f23 658 * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
mbed_official 324:406fd2029f23 659 * an internal transfer acknowledge is generated for all transfers.
mbed_official 324:406fd2029f23 660 * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
mbed_official 324:406fd2029f23 661 * an internal transfer acknowledge is generated for burst transfer
mbed_official 324:406fd2029f23 662 * secondary terminations.
mbed_official 324:406fd2029f23 663 */
mbed_official 324:406fd2029f23 664 /*@{*/
mbed_official 324:406fd2029f23 665 #define BP_FB_CSCRn_SWSEN (23U) /*!< Bit position for FB_CSCRn_SWSEN. */
mbed_official 324:406fd2029f23 666 #define BM_FB_CSCRn_SWSEN (0x00800000U) /*!< Bit mask for FB_CSCRn_SWSEN. */
mbed_official 324:406fd2029f23 667 #define BS_FB_CSCRn_SWSEN (1U) /*!< Bit field size in bits for FB_CSCRn_SWSEN. */
mbed_official 324:406fd2029f23 668
mbed_official 324:406fd2029f23 669 /*! @brief Read current value of the FB_CSCRn_SWSEN field. */
mbed_official 324:406fd2029f23 670 #define BR_FB_CSCRn_SWSEN(x, n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN))
mbed_official 324:406fd2029f23 671
mbed_official 324:406fd2029f23 672 /*! @brief Format value for bitfield FB_CSCRn_SWSEN. */
mbed_official 324:406fd2029f23 673 #define BF_FB_CSCRn_SWSEN(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWSEN) & BM_FB_CSCRn_SWSEN)
mbed_official 324:406fd2029f23 674
mbed_official 324:406fd2029f23 675 /*! @brief Set the SWSEN field to a new value. */
mbed_official 324:406fd2029f23 676 #define BW_FB_CSCRn_SWSEN(x, n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(x, n), BP_FB_CSCRn_SWSEN) = (v))
mbed_official 324:406fd2029f23 677 /*@}*/
mbed_official 324:406fd2029f23 678
mbed_official 324:406fd2029f23 679 /*!
mbed_official 324:406fd2029f23 680 * @name Register FB_CSCRn, field SWS[31:26] (RW)
mbed_official 324:406fd2029f23 681 *
mbed_official 324:406fd2029f23 682 * Used only when the SWSEN bit is 1b. Specifies the number of wait states
mbed_official 324:406fd2029f23 683 * inserted before an internal transfer acknowledge is generated for a burst transfer
mbed_official 324:406fd2029f23 684 * (except for the first termination, which is controlled by WS).
mbed_official 324:406fd2029f23 685 */
mbed_official 324:406fd2029f23 686 /*@{*/
mbed_official 324:406fd2029f23 687 #define BP_FB_CSCRn_SWS (26U) /*!< Bit position for FB_CSCRn_SWS. */
mbed_official 324:406fd2029f23 688 #define BM_FB_CSCRn_SWS (0xFC000000U) /*!< Bit mask for FB_CSCRn_SWS. */
mbed_official 324:406fd2029f23 689 #define BS_FB_CSCRn_SWS (6U) /*!< Bit field size in bits for FB_CSCRn_SWS. */
mbed_official 324:406fd2029f23 690
mbed_official 324:406fd2029f23 691 /*! @brief Read current value of the FB_CSCRn_SWS field. */
mbed_official 324:406fd2029f23 692 #define BR_FB_CSCRn_SWS(x, n) (HW_FB_CSCRn(x, n).B.SWS)
mbed_official 324:406fd2029f23 693
mbed_official 324:406fd2029f23 694 /*! @brief Format value for bitfield FB_CSCRn_SWS. */
mbed_official 324:406fd2029f23 695 #define BF_FB_CSCRn_SWS(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSCRn_SWS) & BM_FB_CSCRn_SWS)
mbed_official 324:406fd2029f23 696
mbed_official 324:406fd2029f23 697 /*! @brief Set the SWS field to a new value. */
mbed_official 324:406fd2029f23 698 #define BW_FB_CSCRn_SWS(x, n, v) (HW_FB_CSCRn_WR(x, n, (HW_FB_CSCRn_RD(x, n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
mbed_official 324:406fd2029f23 699 /*@}*/
mbed_official 324:406fd2029f23 700
mbed_official 324:406fd2029f23 701 /*******************************************************************************
mbed_official 324:406fd2029f23 702 * HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
mbed_official 324:406fd2029f23 703 ******************************************************************************/
mbed_official 324:406fd2029f23 704
mbed_official 324:406fd2029f23 705 /*!
mbed_official 324:406fd2029f23 706 * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
mbed_official 324:406fd2029f23 707 *
mbed_official 324:406fd2029f23 708 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 709 *
mbed_official 324:406fd2029f23 710 * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
mbed_official 324:406fd2029f23 711 * do any of the following: Write to a reserved address Write to a reserved
mbed_official 324:406fd2029f23 712 * field in this register, or Access this register using a size other than 32 bits.
mbed_official 324:406fd2029f23 713 */
mbed_official 324:406fd2029f23 714 typedef union _hw_fb_cspmcr
mbed_official 324:406fd2029f23 715 {
mbed_official 324:406fd2029f23 716 uint32_t U;
mbed_official 324:406fd2029f23 717 struct _hw_fb_cspmcr_bitfields
mbed_official 324:406fd2029f23 718 {
mbed_official 324:406fd2029f23 719 uint32_t RESERVED0 : 12; /*!< [11:0] */
mbed_official 324:406fd2029f23 720 uint32_t GROUP5 : 4; /*!< [15:12] FlexBus Signal Group 5 Multiplex
mbed_official 324:406fd2029f23 721 * control */
mbed_official 324:406fd2029f23 722 uint32_t GROUP4 : 4; /*!< [19:16] FlexBus Signal Group 4 Multiplex
mbed_official 324:406fd2029f23 723 * control */
mbed_official 324:406fd2029f23 724 uint32_t GROUP3 : 4; /*!< [23:20] FlexBus Signal Group 3 Multiplex
mbed_official 324:406fd2029f23 725 * control */
mbed_official 324:406fd2029f23 726 uint32_t GROUP2 : 4; /*!< [27:24] FlexBus Signal Group 2 Multiplex
mbed_official 324:406fd2029f23 727 * control */
mbed_official 324:406fd2029f23 728 uint32_t GROUP1 : 4; /*!< [31:28] FlexBus Signal Group 1 Multiplex
mbed_official 324:406fd2029f23 729 * control */
mbed_official 324:406fd2029f23 730 } B;
mbed_official 324:406fd2029f23 731 } hw_fb_cspmcr_t;
mbed_official 324:406fd2029f23 732
mbed_official 324:406fd2029f23 733 /*!
mbed_official 324:406fd2029f23 734 * @name Constants and macros for entire FB_CSPMCR register
mbed_official 324:406fd2029f23 735 */
mbed_official 324:406fd2029f23 736 /*@{*/
mbed_official 324:406fd2029f23 737 #define HW_FB_CSPMCR_ADDR(x) ((x) + 0x60U)
mbed_official 324:406fd2029f23 738
mbed_official 324:406fd2029f23 739 #define HW_FB_CSPMCR(x) (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR(x))
mbed_official 324:406fd2029f23 740 #define HW_FB_CSPMCR_RD(x) (HW_FB_CSPMCR(x).U)
mbed_official 324:406fd2029f23 741 #define HW_FB_CSPMCR_WR(x, v) (HW_FB_CSPMCR(x).U = (v))
mbed_official 324:406fd2029f23 742 #define HW_FB_CSPMCR_SET(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) | (v)))
mbed_official 324:406fd2029f23 743 #define HW_FB_CSPMCR_CLR(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 744 #define HW_FB_CSPMCR_TOG(x, v) (HW_FB_CSPMCR_WR(x, HW_FB_CSPMCR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 745 /*@}*/
mbed_official 324:406fd2029f23 746
mbed_official 324:406fd2029f23 747 /*
mbed_official 324:406fd2029f23 748 * Constants & macros for individual FB_CSPMCR bitfields
mbed_official 324:406fd2029f23 749 */
mbed_official 324:406fd2029f23 750
mbed_official 324:406fd2029f23 751 /*!
mbed_official 324:406fd2029f23 752 * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
mbed_official 324:406fd2029f23 753 *
mbed_official 324:406fd2029f23 754 * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
mbed_official 324:406fd2029f23 755 * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
mbed_official 324:406fd2029f23 756 * bus hangs during a transfer.
mbed_official 324:406fd2029f23 757 *
mbed_official 324:406fd2029f23 758 * Values:
mbed_official 324:406fd2029f23 759 * - 0000 - FB_TA
mbed_official 324:406fd2029f23 760 * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
mbed_official 324:406fd2029f23 761 * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
mbed_official 324:406fd2029f23 762 */
mbed_official 324:406fd2029f23 763 /*@{*/
mbed_official 324:406fd2029f23 764 #define BP_FB_CSPMCR_GROUP5 (12U) /*!< Bit position for FB_CSPMCR_GROUP5. */
mbed_official 324:406fd2029f23 765 #define BM_FB_CSPMCR_GROUP5 (0x0000F000U) /*!< Bit mask for FB_CSPMCR_GROUP5. */
mbed_official 324:406fd2029f23 766 #define BS_FB_CSPMCR_GROUP5 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP5. */
mbed_official 324:406fd2029f23 767
mbed_official 324:406fd2029f23 768 /*! @brief Read current value of the FB_CSPMCR_GROUP5 field. */
mbed_official 324:406fd2029f23 769 #define BR_FB_CSPMCR_GROUP5(x) (HW_FB_CSPMCR(x).B.GROUP5)
mbed_official 324:406fd2029f23 770
mbed_official 324:406fd2029f23 771 /*! @brief Format value for bitfield FB_CSPMCR_GROUP5. */
mbed_official 324:406fd2029f23 772 #define BF_FB_CSPMCR_GROUP5(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP5) & BM_FB_CSPMCR_GROUP5)
mbed_official 324:406fd2029f23 773
mbed_official 324:406fd2029f23 774 /*! @brief Set the GROUP5 field to a new value. */
mbed_official 324:406fd2029f23 775 #define BW_FB_CSPMCR_GROUP5(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
mbed_official 324:406fd2029f23 776 /*@}*/
mbed_official 324:406fd2029f23 777
mbed_official 324:406fd2029f23 778 /*!
mbed_official 324:406fd2029f23 779 * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
mbed_official 324:406fd2029f23 780 *
mbed_official 324:406fd2029f23 781 * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
mbed_official 324:406fd2029f23 782 *
mbed_official 324:406fd2029f23 783 * Values:
mbed_official 324:406fd2029f23 784 * - 0000 - FB_TBST
mbed_official 324:406fd2029f23 785 * - 0001 - FB_CS2
mbed_official 324:406fd2029f23 786 * - 0010 - FB_BE_15_8
mbed_official 324:406fd2029f23 787 */
mbed_official 324:406fd2029f23 788 /*@{*/
mbed_official 324:406fd2029f23 789 #define BP_FB_CSPMCR_GROUP4 (16U) /*!< Bit position for FB_CSPMCR_GROUP4. */
mbed_official 324:406fd2029f23 790 #define BM_FB_CSPMCR_GROUP4 (0x000F0000U) /*!< Bit mask for FB_CSPMCR_GROUP4. */
mbed_official 324:406fd2029f23 791 #define BS_FB_CSPMCR_GROUP4 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP4. */
mbed_official 324:406fd2029f23 792
mbed_official 324:406fd2029f23 793 /*! @brief Read current value of the FB_CSPMCR_GROUP4 field. */
mbed_official 324:406fd2029f23 794 #define BR_FB_CSPMCR_GROUP4(x) (HW_FB_CSPMCR(x).B.GROUP4)
mbed_official 324:406fd2029f23 795
mbed_official 324:406fd2029f23 796 /*! @brief Format value for bitfield FB_CSPMCR_GROUP4. */
mbed_official 324:406fd2029f23 797 #define BF_FB_CSPMCR_GROUP4(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP4) & BM_FB_CSPMCR_GROUP4)
mbed_official 324:406fd2029f23 798
mbed_official 324:406fd2029f23 799 /*! @brief Set the GROUP4 field to a new value. */
mbed_official 324:406fd2029f23 800 #define BW_FB_CSPMCR_GROUP4(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
mbed_official 324:406fd2029f23 801 /*@}*/
mbed_official 324:406fd2029f23 802
mbed_official 324:406fd2029f23 803 /*!
mbed_official 324:406fd2029f23 804 * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
mbed_official 324:406fd2029f23 805 *
mbed_official 324:406fd2029f23 806 * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
mbed_official 324:406fd2029f23 807 *
mbed_official 324:406fd2029f23 808 * Values:
mbed_official 324:406fd2029f23 809 * - 0000 - FB_CS5
mbed_official 324:406fd2029f23 810 * - 0001 - FB_TSIZ1
mbed_official 324:406fd2029f23 811 * - 0010 - FB_BE_23_16
mbed_official 324:406fd2029f23 812 */
mbed_official 324:406fd2029f23 813 /*@{*/
mbed_official 324:406fd2029f23 814 #define BP_FB_CSPMCR_GROUP3 (20U) /*!< Bit position for FB_CSPMCR_GROUP3. */
mbed_official 324:406fd2029f23 815 #define BM_FB_CSPMCR_GROUP3 (0x00F00000U) /*!< Bit mask for FB_CSPMCR_GROUP3. */
mbed_official 324:406fd2029f23 816 #define BS_FB_CSPMCR_GROUP3 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP3. */
mbed_official 324:406fd2029f23 817
mbed_official 324:406fd2029f23 818 /*! @brief Read current value of the FB_CSPMCR_GROUP3 field. */
mbed_official 324:406fd2029f23 819 #define BR_FB_CSPMCR_GROUP3(x) (HW_FB_CSPMCR(x).B.GROUP3)
mbed_official 324:406fd2029f23 820
mbed_official 324:406fd2029f23 821 /*! @brief Format value for bitfield FB_CSPMCR_GROUP3. */
mbed_official 324:406fd2029f23 822 #define BF_FB_CSPMCR_GROUP3(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP3) & BM_FB_CSPMCR_GROUP3)
mbed_official 324:406fd2029f23 823
mbed_official 324:406fd2029f23 824 /*! @brief Set the GROUP3 field to a new value. */
mbed_official 324:406fd2029f23 825 #define BW_FB_CSPMCR_GROUP3(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
mbed_official 324:406fd2029f23 826 /*@}*/
mbed_official 324:406fd2029f23 827
mbed_official 324:406fd2029f23 828 /*!
mbed_official 324:406fd2029f23 829 * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
mbed_official 324:406fd2029f23 830 *
mbed_official 324:406fd2029f23 831 * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
mbed_official 324:406fd2029f23 832 *
mbed_official 324:406fd2029f23 833 * Values:
mbed_official 324:406fd2029f23 834 * - 0000 - FB_CS4
mbed_official 324:406fd2029f23 835 * - 0001 - FB_TSIZ0
mbed_official 324:406fd2029f23 836 * - 0010 - FB_BE_31_24
mbed_official 324:406fd2029f23 837 */
mbed_official 324:406fd2029f23 838 /*@{*/
mbed_official 324:406fd2029f23 839 #define BP_FB_CSPMCR_GROUP2 (24U) /*!< Bit position for FB_CSPMCR_GROUP2. */
mbed_official 324:406fd2029f23 840 #define BM_FB_CSPMCR_GROUP2 (0x0F000000U) /*!< Bit mask for FB_CSPMCR_GROUP2. */
mbed_official 324:406fd2029f23 841 #define BS_FB_CSPMCR_GROUP2 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP2. */
mbed_official 324:406fd2029f23 842
mbed_official 324:406fd2029f23 843 /*! @brief Read current value of the FB_CSPMCR_GROUP2 field. */
mbed_official 324:406fd2029f23 844 #define BR_FB_CSPMCR_GROUP2(x) (HW_FB_CSPMCR(x).B.GROUP2)
mbed_official 324:406fd2029f23 845
mbed_official 324:406fd2029f23 846 /*! @brief Format value for bitfield FB_CSPMCR_GROUP2. */
mbed_official 324:406fd2029f23 847 #define BF_FB_CSPMCR_GROUP2(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP2) & BM_FB_CSPMCR_GROUP2)
mbed_official 324:406fd2029f23 848
mbed_official 324:406fd2029f23 849 /*! @brief Set the GROUP2 field to a new value. */
mbed_official 324:406fd2029f23 850 #define BW_FB_CSPMCR_GROUP2(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
mbed_official 324:406fd2029f23 851 /*@}*/
mbed_official 324:406fd2029f23 852
mbed_official 324:406fd2029f23 853 /*!
mbed_official 324:406fd2029f23 854 * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
mbed_official 324:406fd2029f23 855 *
mbed_official 324:406fd2029f23 856 * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
mbed_official 324:406fd2029f23 857 *
mbed_official 324:406fd2029f23 858 * Values:
mbed_official 324:406fd2029f23 859 * - 0000 - FB_ALE
mbed_official 324:406fd2029f23 860 * - 0001 - FB_CS1
mbed_official 324:406fd2029f23 861 * - 0010 - FB_TS
mbed_official 324:406fd2029f23 862 */
mbed_official 324:406fd2029f23 863 /*@{*/
mbed_official 324:406fd2029f23 864 #define BP_FB_CSPMCR_GROUP1 (28U) /*!< Bit position for FB_CSPMCR_GROUP1. */
mbed_official 324:406fd2029f23 865 #define BM_FB_CSPMCR_GROUP1 (0xF0000000U) /*!< Bit mask for FB_CSPMCR_GROUP1. */
mbed_official 324:406fd2029f23 866 #define BS_FB_CSPMCR_GROUP1 (4U) /*!< Bit field size in bits for FB_CSPMCR_GROUP1. */
mbed_official 324:406fd2029f23 867
mbed_official 324:406fd2029f23 868 /*! @brief Read current value of the FB_CSPMCR_GROUP1 field. */
mbed_official 324:406fd2029f23 869 #define BR_FB_CSPMCR_GROUP1(x) (HW_FB_CSPMCR(x).B.GROUP1)
mbed_official 324:406fd2029f23 870
mbed_official 324:406fd2029f23 871 /*! @brief Format value for bitfield FB_CSPMCR_GROUP1. */
mbed_official 324:406fd2029f23 872 #define BF_FB_CSPMCR_GROUP1(v) ((uint32_t)((uint32_t)(v) << BP_FB_CSPMCR_GROUP1) & BM_FB_CSPMCR_GROUP1)
mbed_official 324:406fd2029f23 873
mbed_official 324:406fd2029f23 874 /*! @brief Set the GROUP1 field to a new value. */
mbed_official 324:406fd2029f23 875 #define BW_FB_CSPMCR_GROUP1(x, v) (HW_FB_CSPMCR_WR(x, (HW_FB_CSPMCR_RD(x) & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
mbed_official 324:406fd2029f23 876 /*@}*/
mbed_official 324:406fd2029f23 877
mbed_official 324:406fd2029f23 878 /*******************************************************************************
mbed_official 324:406fd2029f23 879 * hw_fb_t - module struct
mbed_official 324:406fd2029f23 880 ******************************************************************************/
mbed_official 324:406fd2029f23 881 /*!
mbed_official 324:406fd2029f23 882 * @brief All FB module registers.
mbed_official 324:406fd2029f23 883 */
mbed_official 324:406fd2029f23 884 #pragma pack(1)
mbed_official 324:406fd2029f23 885 typedef struct _hw_fb
mbed_official 324:406fd2029f23 886 {
mbed_official 324:406fd2029f23 887 struct {
mbed_official 324:406fd2029f23 888 __IO hw_fb_csarn_t CSARn; /*!< [0x0] Chip Select Address Register */
mbed_official 324:406fd2029f23 889 __IO hw_fb_csmrn_t CSMRn; /*!< [0x4] Chip Select Mask Register */
mbed_official 324:406fd2029f23 890 __IO hw_fb_cscrn_t CSCRn; /*!< [0x8] Chip Select Control Register */
mbed_official 324:406fd2029f23 891 } CS[6];
mbed_official 324:406fd2029f23 892 uint8_t _reserved0[24];
mbed_official 324:406fd2029f23 893 __IO hw_fb_cspmcr_t CSPMCR; /*!< [0x60] Chip Select port Multiplexing Control Register */
mbed_official 324:406fd2029f23 894 } hw_fb_t;
mbed_official 324:406fd2029f23 895 #pragma pack()
mbed_official 324:406fd2029f23 896
mbed_official 324:406fd2029f23 897 /*! @brief Macro to access all FB registers. */
mbed_official 324:406fd2029f23 898 /*! @param x FB module instance base address. */
mbed_official 324:406fd2029f23 899 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 900 * use the '&' operator, like <code>&HW_FB(FB_BASE)</code>. */
mbed_official 324:406fd2029f23 901 #define HW_FB(x) (*(hw_fb_t *)(x))
mbed_official 324:406fd2029f23 902
mbed_official 324:406fd2029f23 903 #endif /* __HW_FB_REGISTERS_H__ */
mbed_official 324:406fd2029f23 904 /* EOF */