mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_ewm.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_EWM_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_EWM_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 EWM
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * External Watchdog Monitor
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_EWM_CTRL - Control Register
mbed_official 324:406fd2029f23 90 * - HW_EWM_SERV - Service Register
mbed_official 324:406fd2029f23 91 * - HW_EWM_CMPL - Compare Low Register
mbed_official 324:406fd2029f23 92 * - HW_EWM_CMPH - Compare High Register
mbed_official 324:406fd2029f23 93 * - HW_EWM_CLKPRESCALER - Clock Prescaler Register
mbed_official 324:406fd2029f23 94 *
mbed_official 324:406fd2029f23 95 * - hw_ewm_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 96 */
mbed_official 324:406fd2029f23 97
mbed_official 324:406fd2029f23 98 #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 /*******************************************************************************
mbed_official 324:406fd2029f23 101 * HW_EWM_CTRL - Control Register
mbed_official 324:406fd2029f23 102 ******************************************************************************/
mbed_official 324:406fd2029f23 103
mbed_official 324:406fd2029f23 104 /*!
mbed_official 324:406fd2029f23 105 * @brief HW_EWM_CTRL - Control Register (RW)
mbed_official 324:406fd2029f23 106 *
mbed_official 324:406fd2029f23 107 * Reset value: 0x00U
mbed_official 324:406fd2029f23 108 *
mbed_official 324:406fd2029f23 109 * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
mbed_official 324:406fd2029f23 110 * written once after a CPU reset. Modifying these bits more than once, generates
mbed_official 324:406fd2029f23 111 * a bus transfer error.
mbed_official 324:406fd2029f23 112 */
mbed_official 324:406fd2029f23 113 typedef union _hw_ewm_ctrl
mbed_official 324:406fd2029f23 114 {
mbed_official 324:406fd2029f23 115 uint8_t U;
mbed_official 324:406fd2029f23 116 struct _hw_ewm_ctrl_bitfields
mbed_official 324:406fd2029f23 117 {
mbed_official 324:406fd2029f23 118 uint8_t EWMEN : 1; /*!< [0] EWM enable. */
mbed_official 324:406fd2029f23 119 uint8_t ASSIN : 1; /*!< [1] EWM_in's Assertion State Select. */
mbed_official 324:406fd2029f23 120 uint8_t INEN : 1; /*!< [2] Input Enable. */
mbed_official 324:406fd2029f23 121 uint8_t INTEN : 1; /*!< [3] Interrupt Enable. */
mbed_official 324:406fd2029f23 122 uint8_t RESERVED0 : 4; /*!< [7:4] */
mbed_official 324:406fd2029f23 123 } B;
mbed_official 324:406fd2029f23 124 } hw_ewm_ctrl_t;
mbed_official 324:406fd2029f23 125
mbed_official 324:406fd2029f23 126 /*!
mbed_official 324:406fd2029f23 127 * @name Constants and macros for entire EWM_CTRL register
mbed_official 324:406fd2029f23 128 */
mbed_official 324:406fd2029f23 129 /*@{*/
mbed_official 324:406fd2029f23 130 #define HW_EWM_CTRL_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 131
mbed_official 324:406fd2029f23 132 #define HW_EWM_CTRL(x) (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
mbed_official 324:406fd2029f23 133 #define HW_EWM_CTRL_RD(x) (HW_EWM_CTRL(x).U)
mbed_official 324:406fd2029f23 134 #define HW_EWM_CTRL_WR(x, v) (HW_EWM_CTRL(x).U = (v))
mbed_official 324:406fd2029f23 135 #define HW_EWM_CTRL_SET(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) | (v)))
mbed_official 324:406fd2029f23 136 #define HW_EWM_CTRL_CLR(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 137 #define HW_EWM_CTRL_TOG(x, v) (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 138 /*@}*/
mbed_official 324:406fd2029f23 139
mbed_official 324:406fd2029f23 140 /*
mbed_official 324:406fd2029f23 141 * Constants & macros for individual EWM_CTRL bitfields
mbed_official 324:406fd2029f23 142 */
mbed_official 324:406fd2029f23 143
mbed_official 324:406fd2029f23 144 /*!
mbed_official 324:406fd2029f23 145 * @name Register EWM_CTRL, field EWMEN[0] (RW)
mbed_official 324:406fd2029f23 146 *
mbed_official 324:406fd2029f23 147 * This bit when set, enables the EWM module. This resets the EWM counter to
mbed_official 324:406fd2029f23 148 * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
mbed_official 324:406fd2029f23 149 * therefore it cannot be enabled until a reset occurs, due to the write-once
mbed_official 324:406fd2029f23 150 * nature of this bit.
mbed_official 324:406fd2029f23 151 */
mbed_official 324:406fd2029f23 152 /*@{*/
mbed_official 324:406fd2029f23 153 #define BP_EWM_CTRL_EWMEN (0U) /*!< Bit position for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 154 #define BM_EWM_CTRL_EWMEN (0x01U) /*!< Bit mask for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 155 #define BS_EWM_CTRL_EWMEN (1U) /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 156
mbed_official 324:406fd2029f23 157 /*! @brief Read current value of the EWM_CTRL_EWMEN field. */
mbed_official 324:406fd2029f23 158 #define BR_EWM_CTRL_EWMEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN))
mbed_official 324:406fd2029f23 159
mbed_official 324:406fd2029f23 160 /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
mbed_official 324:406fd2029f23 161 #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
mbed_official 324:406fd2029f23 162
mbed_official 324:406fd2029f23 163 /*! @brief Set the EWMEN field to a new value. */
mbed_official 324:406fd2029f23 164 #define BW_EWM_CTRL_EWMEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN) = (v))
mbed_official 324:406fd2029f23 165 /*@}*/
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 /*!
mbed_official 324:406fd2029f23 168 * @name Register EWM_CTRL, field ASSIN[1] (RW)
mbed_official 324:406fd2029f23 169 *
mbed_official 324:406fd2029f23 170 * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
mbed_official 324:406fd2029f23 171 * inverts the assert state to a logic one.
mbed_official 324:406fd2029f23 172 */
mbed_official 324:406fd2029f23 173 /*@{*/
mbed_official 324:406fd2029f23 174 #define BP_EWM_CTRL_ASSIN (1U) /*!< Bit position for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 175 #define BM_EWM_CTRL_ASSIN (0x02U) /*!< Bit mask for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 176 #define BS_EWM_CTRL_ASSIN (1U) /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*! @brief Read current value of the EWM_CTRL_ASSIN field. */
mbed_official 324:406fd2029f23 179 #define BR_EWM_CTRL_ASSIN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN))
mbed_official 324:406fd2029f23 180
mbed_official 324:406fd2029f23 181 /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
mbed_official 324:406fd2029f23 182 #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
mbed_official 324:406fd2029f23 183
mbed_official 324:406fd2029f23 184 /*! @brief Set the ASSIN field to a new value. */
mbed_official 324:406fd2029f23 185 #define BW_EWM_CTRL_ASSIN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN) = (v))
mbed_official 324:406fd2029f23 186 /*@}*/
mbed_official 324:406fd2029f23 187
mbed_official 324:406fd2029f23 188 /*!
mbed_official 324:406fd2029f23 189 * @name Register EWM_CTRL, field INEN[2] (RW)
mbed_official 324:406fd2029f23 190 *
mbed_official 324:406fd2029f23 191 * This bit when set, enables the EWM_in port.
mbed_official 324:406fd2029f23 192 */
mbed_official 324:406fd2029f23 193 /*@{*/
mbed_official 324:406fd2029f23 194 #define BP_EWM_CTRL_INEN (2U) /*!< Bit position for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 195 #define BM_EWM_CTRL_INEN (0x04U) /*!< Bit mask for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 196 #define BS_EWM_CTRL_INEN (1U) /*!< Bit field size in bits for EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 /*! @brief Read current value of the EWM_CTRL_INEN field. */
mbed_official 324:406fd2029f23 199 #define BR_EWM_CTRL_INEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN))
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 /*! @brief Format value for bitfield EWM_CTRL_INEN. */
mbed_official 324:406fd2029f23 202 #define BF_EWM_CTRL_INEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
mbed_official 324:406fd2029f23 203
mbed_official 324:406fd2029f23 204 /*! @brief Set the INEN field to a new value. */
mbed_official 324:406fd2029f23 205 #define BW_EWM_CTRL_INEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN) = (v))
mbed_official 324:406fd2029f23 206 /*@}*/
mbed_official 324:406fd2029f23 207
mbed_official 324:406fd2029f23 208 /*!
mbed_official 324:406fd2029f23 209 * @name Register EWM_CTRL, field INTEN[3] (RW)
mbed_official 324:406fd2029f23 210 *
mbed_official 324:406fd2029f23 211 * This bit when set and EWM_out is asserted, an interrupt request is generated.
mbed_official 324:406fd2029f23 212 * To de-assert interrupt request, user should clear this bit by writing 0.
mbed_official 324:406fd2029f23 213 */
mbed_official 324:406fd2029f23 214 /*@{*/
mbed_official 324:406fd2029f23 215 #define BP_EWM_CTRL_INTEN (3U) /*!< Bit position for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 216 #define BM_EWM_CTRL_INTEN (0x08U) /*!< Bit mask for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 217 #define BS_EWM_CTRL_INTEN (1U) /*!< Bit field size in bits for EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*! @brief Read current value of the EWM_CTRL_INTEN field. */
mbed_official 324:406fd2029f23 220 #define BR_EWM_CTRL_INTEN(x) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN))
mbed_official 324:406fd2029f23 221
mbed_official 324:406fd2029f23 222 /*! @brief Format value for bitfield EWM_CTRL_INTEN. */
mbed_official 324:406fd2029f23 223 #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
mbed_official 324:406fd2029f23 224
mbed_official 324:406fd2029f23 225 /*! @brief Set the INTEN field to a new value. */
mbed_official 324:406fd2029f23 226 #define BW_EWM_CTRL_INTEN(x, v) (BITBAND_ACCESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN) = (v))
mbed_official 324:406fd2029f23 227 /*@}*/
mbed_official 324:406fd2029f23 228
mbed_official 324:406fd2029f23 229 /*******************************************************************************
mbed_official 324:406fd2029f23 230 * HW_EWM_SERV - Service Register
mbed_official 324:406fd2029f23 231 ******************************************************************************/
mbed_official 324:406fd2029f23 232
mbed_official 324:406fd2029f23 233 /*!
mbed_official 324:406fd2029f23 234 * @brief HW_EWM_SERV - Service Register (WORZ)
mbed_official 324:406fd2029f23 235 *
mbed_official 324:406fd2029f23 236 * Reset value: 0x00U
mbed_official 324:406fd2029f23 237 *
mbed_official 324:406fd2029f23 238 * The SERV register provides the interface from the CPU to the EWM module. It
mbed_official 324:406fd2029f23 239 * is write-only and reads of this register return zero.
mbed_official 324:406fd2029f23 240 */
mbed_official 324:406fd2029f23 241 typedef union _hw_ewm_serv
mbed_official 324:406fd2029f23 242 {
mbed_official 324:406fd2029f23 243 uint8_t U;
mbed_official 324:406fd2029f23 244 struct _hw_ewm_serv_bitfields
mbed_official 324:406fd2029f23 245 {
mbed_official 324:406fd2029f23 246 uint8_t SERVICE : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 247 } B;
mbed_official 324:406fd2029f23 248 } hw_ewm_serv_t;
mbed_official 324:406fd2029f23 249
mbed_official 324:406fd2029f23 250 /*!
mbed_official 324:406fd2029f23 251 * @name Constants and macros for entire EWM_SERV register
mbed_official 324:406fd2029f23 252 */
mbed_official 324:406fd2029f23 253 /*@{*/
mbed_official 324:406fd2029f23 254 #define HW_EWM_SERV_ADDR(x) ((x) + 0x1U)
mbed_official 324:406fd2029f23 255
mbed_official 324:406fd2029f23 256 #define HW_EWM_SERV(x) (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
mbed_official 324:406fd2029f23 257 #define HW_EWM_SERV_RD(x) (HW_EWM_SERV(x).U)
mbed_official 324:406fd2029f23 258 #define HW_EWM_SERV_WR(x, v) (HW_EWM_SERV(x).U = (v))
mbed_official 324:406fd2029f23 259 /*@}*/
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261 /*
mbed_official 324:406fd2029f23 262 * Constants & macros for individual EWM_SERV bitfields
mbed_official 324:406fd2029f23 263 */
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*!
mbed_official 324:406fd2029f23 266 * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
mbed_official 324:406fd2029f23 267 *
mbed_official 324:406fd2029f23 268 * The EWM service mechanism requires the CPU to write two values to the SERV
mbed_official 324:406fd2029f23 269 * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
mbed_official 324:406fd2029f23 270 * EWM service is illegal if either of the following conditions is true. The
mbed_official 324:406fd2029f23 271 * first or second data byte is not written correctly. The second data byte is not
mbed_official 324:406fd2029f23 272 * written within a fixed number of peripheral bus cycles of the first data byte.
mbed_official 324:406fd2029f23 273 * This fixed number of cycles is called EWM_service_time.
mbed_official 324:406fd2029f23 274 */
mbed_official 324:406fd2029f23 275 /*@{*/
mbed_official 324:406fd2029f23 276 #define BP_EWM_SERV_SERVICE (0U) /*!< Bit position for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 277 #define BM_EWM_SERV_SERVICE (0xFFU) /*!< Bit mask for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 278 #define BS_EWM_SERV_SERVICE (8U) /*!< Bit field size in bits for EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 279
mbed_official 324:406fd2029f23 280 /*! @brief Format value for bitfield EWM_SERV_SERVICE. */
mbed_official 324:406fd2029f23 281 #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
mbed_official 324:406fd2029f23 282
mbed_official 324:406fd2029f23 283 /*! @brief Set the SERVICE field to a new value. */
mbed_official 324:406fd2029f23 284 #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
mbed_official 324:406fd2029f23 285 /*@}*/
mbed_official 324:406fd2029f23 286
mbed_official 324:406fd2029f23 287 /*******************************************************************************
mbed_official 324:406fd2029f23 288 * HW_EWM_CMPL - Compare Low Register
mbed_official 324:406fd2029f23 289 ******************************************************************************/
mbed_official 324:406fd2029f23 290
mbed_official 324:406fd2029f23 291 /*!
mbed_official 324:406fd2029f23 292 * @brief HW_EWM_CMPL - Compare Low Register (RW)
mbed_official 324:406fd2029f23 293 *
mbed_official 324:406fd2029f23 294 * Reset value: 0x00U
mbed_official 324:406fd2029f23 295 *
mbed_official 324:406fd2029f23 296 * The CMPL register is reset to zero after a CPU reset. This provides no
mbed_official 324:406fd2029f23 297 * minimum time for the CPU to service the EWM counter. This register can be written
mbed_official 324:406fd2029f23 298 * only once after a CPU reset. Writing this register more than once generates a
mbed_official 324:406fd2029f23 299 * bus transfer error.
mbed_official 324:406fd2029f23 300 */
mbed_official 324:406fd2029f23 301 typedef union _hw_ewm_cmpl
mbed_official 324:406fd2029f23 302 {
mbed_official 324:406fd2029f23 303 uint8_t U;
mbed_official 324:406fd2029f23 304 struct _hw_ewm_cmpl_bitfields
mbed_official 324:406fd2029f23 305 {
mbed_official 324:406fd2029f23 306 uint8_t COMPAREL : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 307 } B;
mbed_official 324:406fd2029f23 308 } hw_ewm_cmpl_t;
mbed_official 324:406fd2029f23 309
mbed_official 324:406fd2029f23 310 /*!
mbed_official 324:406fd2029f23 311 * @name Constants and macros for entire EWM_CMPL register
mbed_official 324:406fd2029f23 312 */
mbed_official 324:406fd2029f23 313 /*@{*/
mbed_official 324:406fd2029f23 314 #define HW_EWM_CMPL_ADDR(x) ((x) + 0x2U)
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 #define HW_EWM_CMPL(x) (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
mbed_official 324:406fd2029f23 317 #define HW_EWM_CMPL_RD(x) (HW_EWM_CMPL(x).U)
mbed_official 324:406fd2029f23 318 #define HW_EWM_CMPL_WR(x, v) (HW_EWM_CMPL(x).U = (v))
mbed_official 324:406fd2029f23 319 #define HW_EWM_CMPL_SET(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) | (v)))
mbed_official 324:406fd2029f23 320 #define HW_EWM_CMPL_CLR(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 321 #define HW_EWM_CMPL_TOG(x, v) (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 322 /*@}*/
mbed_official 324:406fd2029f23 323
mbed_official 324:406fd2029f23 324 /*
mbed_official 324:406fd2029f23 325 * Constants & macros for individual EWM_CMPL bitfields
mbed_official 324:406fd2029f23 326 */
mbed_official 324:406fd2029f23 327
mbed_official 324:406fd2029f23 328 /*!
mbed_official 324:406fd2029f23 329 * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
mbed_official 324:406fd2029f23 330 *
mbed_official 324:406fd2029f23 331 * To prevent runaway code from changing this field, software should write to
mbed_official 324:406fd2029f23 332 * this field after a CPU reset even if the (default) minimum service time is
mbed_official 324:406fd2029f23 333 * required.
mbed_official 324:406fd2029f23 334 */
mbed_official 324:406fd2029f23 335 /*@{*/
mbed_official 324:406fd2029f23 336 #define BP_EWM_CMPL_COMPAREL (0U) /*!< Bit position for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 337 #define BM_EWM_CMPL_COMPAREL (0xFFU) /*!< Bit mask for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 338 #define BS_EWM_CMPL_COMPAREL (8U) /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 339
mbed_official 324:406fd2029f23 340 /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
mbed_official 324:406fd2029f23 341 #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
mbed_official 324:406fd2029f23 342
mbed_official 324:406fd2029f23 343 /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
mbed_official 324:406fd2029f23 344 #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
mbed_official 324:406fd2029f23 345
mbed_official 324:406fd2029f23 346 /*! @brief Set the COMPAREL field to a new value. */
mbed_official 324:406fd2029f23 347 #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
mbed_official 324:406fd2029f23 348 /*@}*/
mbed_official 324:406fd2029f23 349
mbed_official 324:406fd2029f23 350 /*******************************************************************************
mbed_official 324:406fd2029f23 351 * HW_EWM_CMPH - Compare High Register
mbed_official 324:406fd2029f23 352 ******************************************************************************/
mbed_official 324:406fd2029f23 353
mbed_official 324:406fd2029f23 354 /*!
mbed_official 324:406fd2029f23 355 * @brief HW_EWM_CMPH - Compare High Register (RW)
mbed_official 324:406fd2029f23 356 *
mbed_official 324:406fd2029f23 357 * Reset value: 0xFFU
mbed_official 324:406fd2029f23 358 *
mbed_official 324:406fd2029f23 359 * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
mbed_official 324:406fd2029f23 360 * of 256 clocks time, for the CPU to service the EWM counter. This register can
mbed_official 324:406fd2029f23 361 * be written only once after a CPU reset. Writing this register more than once
mbed_official 324:406fd2029f23 362 * generates a bus transfer error. The valid values for CMPH are up to 0xFE
mbed_official 324:406fd2029f23 363 * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
mbed_official 324:406fd2029f23 364 * if EWM counter is greater than CMPH.
mbed_official 324:406fd2029f23 365 */
mbed_official 324:406fd2029f23 366 typedef union _hw_ewm_cmph
mbed_official 324:406fd2029f23 367 {
mbed_official 324:406fd2029f23 368 uint8_t U;
mbed_official 324:406fd2029f23 369 struct _hw_ewm_cmph_bitfields
mbed_official 324:406fd2029f23 370 {
mbed_official 324:406fd2029f23 371 uint8_t COMPAREH : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 372 } B;
mbed_official 324:406fd2029f23 373 } hw_ewm_cmph_t;
mbed_official 324:406fd2029f23 374
mbed_official 324:406fd2029f23 375 /*!
mbed_official 324:406fd2029f23 376 * @name Constants and macros for entire EWM_CMPH register
mbed_official 324:406fd2029f23 377 */
mbed_official 324:406fd2029f23 378 /*@{*/
mbed_official 324:406fd2029f23 379 #define HW_EWM_CMPH_ADDR(x) ((x) + 0x3U)
mbed_official 324:406fd2029f23 380
mbed_official 324:406fd2029f23 381 #define HW_EWM_CMPH(x) (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
mbed_official 324:406fd2029f23 382 #define HW_EWM_CMPH_RD(x) (HW_EWM_CMPH(x).U)
mbed_official 324:406fd2029f23 383 #define HW_EWM_CMPH_WR(x, v) (HW_EWM_CMPH(x).U = (v))
mbed_official 324:406fd2029f23 384 #define HW_EWM_CMPH_SET(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) | (v)))
mbed_official 324:406fd2029f23 385 #define HW_EWM_CMPH_CLR(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 386 #define HW_EWM_CMPH_TOG(x, v) (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 387 /*@}*/
mbed_official 324:406fd2029f23 388
mbed_official 324:406fd2029f23 389 /*
mbed_official 324:406fd2029f23 390 * Constants & macros for individual EWM_CMPH bitfields
mbed_official 324:406fd2029f23 391 */
mbed_official 324:406fd2029f23 392
mbed_official 324:406fd2029f23 393 /*!
mbed_official 324:406fd2029f23 394 * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
mbed_official 324:406fd2029f23 395 *
mbed_official 324:406fd2029f23 396 * To prevent runaway code from changing this field, software should write to
mbed_official 324:406fd2029f23 397 * this field after a CPU reset even if the (default) maximum service time is
mbed_official 324:406fd2029f23 398 * required.
mbed_official 324:406fd2029f23 399 */
mbed_official 324:406fd2029f23 400 /*@{*/
mbed_official 324:406fd2029f23 401 #define BP_EWM_CMPH_COMPAREH (0U) /*!< Bit position for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 402 #define BM_EWM_CMPH_COMPAREH (0xFFU) /*!< Bit mask for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 403 #define BS_EWM_CMPH_COMPAREH (8U) /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 404
mbed_official 324:406fd2029f23 405 /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
mbed_official 324:406fd2029f23 406 #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
mbed_official 324:406fd2029f23 407
mbed_official 324:406fd2029f23 408 /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
mbed_official 324:406fd2029f23 409 #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
mbed_official 324:406fd2029f23 410
mbed_official 324:406fd2029f23 411 /*! @brief Set the COMPAREH field to a new value. */
mbed_official 324:406fd2029f23 412 #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
mbed_official 324:406fd2029f23 413 /*@}*/
mbed_official 324:406fd2029f23 414
mbed_official 324:406fd2029f23 415 /*******************************************************************************
mbed_official 324:406fd2029f23 416 * HW_EWM_CLKPRESCALER - Clock Prescaler Register
mbed_official 324:406fd2029f23 417 ******************************************************************************/
mbed_official 324:406fd2029f23 418
mbed_official 324:406fd2029f23 419 /*!
mbed_official 324:406fd2029f23 420 * @brief HW_EWM_CLKPRESCALER - Clock Prescaler Register (RW)
mbed_official 324:406fd2029f23 421 *
mbed_official 324:406fd2029f23 422 * Reset value: 0x00U
mbed_official 324:406fd2029f23 423 *
mbed_official 324:406fd2029f23 424 * This CLKPRESCALER register is reset to 0x00 after a CPU reset. This register
mbed_official 324:406fd2029f23 425 * can be written only once after a CPU reset. Writing this register more than
mbed_official 324:406fd2029f23 426 * once generates a bus transfer error. Write the required prescaler value before
mbed_official 324:406fd2029f23 427 * enabling the EWM. The implementation of this register is chip-specific. See the
mbed_official 324:406fd2029f23 428 * Chip Configuration details.
mbed_official 324:406fd2029f23 429 */
mbed_official 324:406fd2029f23 430 typedef union _hw_ewm_clkprescaler
mbed_official 324:406fd2029f23 431 {
mbed_official 324:406fd2029f23 432 uint8_t U;
mbed_official 324:406fd2029f23 433 struct _hw_ewm_clkprescaler_bitfields
mbed_official 324:406fd2029f23 434 {
mbed_official 324:406fd2029f23 435 uint8_t CLK_DIV : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 436 } B;
mbed_official 324:406fd2029f23 437 } hw_ewm_clkprescaler_t;
mbed_official 324:406fd2029f23 438
mbed_official 324:406fd2029f23 439 /*!
mbed_official 324:406fd2029f23 440 * @name Constants and macros for entire EWM_CLKPRESCALER register
mbed_official 324:406fd2029f23 441 */
mbed_official 324:406fd2029f23 442 /*@{*/
mbed_official 324:406fd2029f23 443 #define HW_EWM_CLKPRESCALER_ADDR(x) ((x) + 0x5U)
mbed_official 324:406fd2029f23 444
mbed_official 324:406fd2029f23 445 #define HW_EWM_CLKPRESCALER(x) (*(__IO hw_ewm_clkprescaler_t *) HW_EWM_CLKPRESCALER_ADDR(x))
mbed_official 324:406fd2029f23 446 #define HW_EWM_CLKPRESCALER_RD(x) (HW_EWM_CLKPRESCALER(x).U)
mbed_official 324:406fd2029f23 447 #define HW_EWM_CLKPRESCALER_WR(x, v) (HW_EWM_CLKPRESCALER(x).U = (v))
mbed_official 324:406fd2029f23 448 #define HW_EWM_CLKPRESCALER_SET(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) | (v)))
mbed_official 324:406fd2029f23 449 #define HW_EWM_CLKPRESCALER_CLR(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 450 #define HW_EWM_CLKPRESCALER_TOG(x, v) (HW_EWM_CLKPRESCALER_WR(x, HW_EWM_CLKPRESCALER_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 451 /*@}*/
mbed_official 324:406fd2029f23 452
mbed_official 324:406fd2029f23 453 /*
mbed_official 324:406fd2029f23 454 * Constants & macros for individual EWM_CLKPRESCALER bitfields
mbed_official 324:406fd2029f23 455 */
mbed_official 324:406fd2029f23 456
mbed_official 324:406fd2029f23 457 /*!
mbed_official 324:406fd2029f23 458 * @name Register EWM_CLKPRESCALER, field CLK_DIV[7:0] (RW)
mbed_official 324:406fd2029f23 459 *
mbed_official 324:406fd2029f23 460 * Selected low power source for running the EWM counter can be prescaled as
mbed_official 324:406fd2029f23 461 * below. Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK_DIV
mbed_official 324:406fd2029f23 462 * )
mbed_official 324:406fd2029f23 463 */
mbed_official 324:406fd2029f23 464 /*@{*/
mbed_official 324:406fd2029f23 465 #define BP_EWM_CLKPRESCALER_CLK_DIV (0U) /*!< Bit position for EWM_CLKPRESCALER_CLK_DIV. */
mbed_official 324:406fd2029f23 466 #define BM_EWM_CLKPRESCALER_CLK_DIV (0xFFU) /*!< Bit mask for EWM_CLKPRESCALER_CLK_DIV. */
mbed_official 324:406fd2029f23 467 #define BS_EWM_CLKPRESCALER_CLK_DIV (8U) /*!< Bit field size in bits for EWM_CLKPRESCALER_CLK_DIV. */
mbed_official 324:406fd2029f23 468
mbed_official 324:406fd2029f23 469 /*! @brief Read current value of the EWM_CLKPRESCALER_CLK_DIV field. */
mbed_official 324:406fd2029f23 470 #define BR_EWM_CLKPRESCALER_CLK_DIV(x) (HW_EWM_CLKPRESCALER(x).U)
mbed_official 324:406fd2029f23 471
mbed_official 324:406fd2029f23 472 /*! @brief Format value for bitfield EWM_CLKPRESCALER_CLK_DIV. */
mbed_official 324:406fd2029f23 473 #define BF_EWM_CLKPRESCALER_CLK_DIV(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CLKPRESCALER_CLK_DIV) & BM_EWM_CLKPRESCALER_CLK_DIV)
mbed_official 324:406fd2029f23 474
mbed_official 324:406fd2029f23 475 /*! @brief Set the CLK_DIV field to a new value. */
mbed_official 324:406fd2029f23 476 #define BW_EWM_CLKPRESCALER_CLK_DIV(x, v) (HW_EWM_CLKPRESCALER_WR(x, v))
mbed_official 324:406fd2029f23 477 /*@}*/
mbed_official 324:406fd2029f23 478
mbed_official 324:406fd2029f23 479 /*******************************************************************************
mbed_official 324:406fd2029f23 480 * hw_ewm_t - module struct
mbed_official 324:406fd2029f23 481 ******************************************************************************/
mbed_official 324:406fd2029f23 482 /*!
mbed_official 324:406fd2029f23 483 * @brief All EWM module registers.
mbed_official 324:406fd2029f23 484 */
mbed_official 324:406fd2029f23 485 #pragma pack(1)
mbed_official 324:406fd2029f23 486 typedef struct _hw_ewm
mbed_official 324:406fd2029f23 487 {
mbed_official 324:406fd2029f23 488 __IO hw_ewm_ctrl_t CTRL; /*!< [0x0] Control Register */
mbed_official 324:406fd2029f23 489 __O hw_ewm_serv_t SERV; /*!< [0x1] Service Register */
mbed_official 324:406fd2029f23 490 __IO hw_ewm_cmpl_t CMPL; /*!< [0x2] Compare Low Register */
mbed_official 324:406fd2029f23 491 __IO hw_ewm_cmph_t CMPH; /*!< [0x3] Compare High Register */
mbed_official 324:406fd2029f23 492 uint8_t _reserved0[1];
mbed_official 324:406fd2029f23 493 __IO hw_ewm_clkprescaler_t CLKPRESCALER; /*!< [0x5] Clock Prescaler Register */
mbed_official 324:406fd2029f23 494 } hw_ewm_t;
mbed_official 324:406fd2029f23 495 #pragma pack()
mbed_official 324:406fd2029f23 496
mbed_official 324:406fd2029f23 497 /*! @brief Macro to access all EWM registers. */
mbed_official 324:406fd2029f23 498 /*! @param x EWM module instance base address. */
mbed_official 324:406fd2029f23 499 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 500 * use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
mbed_official 324:406fd2029f23 501 #define HW_EWM(x) (*(hw_ewm_t *)(x))
mbed_official 324:406fd2029f23 502
mbed_official 324:406fd2029f23 503 #endif /* __HW_EWM_REGISTERS_H__ */
mbed_official 324:406fd2029f23 504 /* EOF */