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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dma.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_DMA_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_DMA_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 DMA
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Enhanced direct memory access controller
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_DMA_CR - Control Register
mbed_official 324:406fd2029f23 90 * - HW_DMA_ES - Error Status Register
mbed_official 324:406fd2029f23 91 * - HW_DMA_ERQ - Enable Request Register
mbed_official 324:406fd2029f23 92 * - HW_DMA_EEI - Enable Error Interrupt Register
mbed_official 324:406fd2029f23 93 * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
mbed_official 324:406fd2029f23 94 * - HW_DMA_SEEI - Set Enable Error Interrupt Register
mbed_official 324:406fd2029f23 95 * - HW_DMA_CERQ - Clear Enable Request Register
mbed_official 324:406fd2029f23 96 * - HW_DMA_SERQ - Set Enable Request Register
mbed_official 324:406fd2029f23 97 * - HW_DMA_CDNE - Clear DONE Status Bit Register
mbed_official 324:406fd2029f23 98 * - HW_DMA_SSRT - Set START Bit Register
mbed_official 324:406fd2029f23 99 * - HW_DMA_CERR - Clear Error Register
mbed_official 324:406fd2029f23 100 * - HW_DMA_CINT - Clear Interrupt Request Register
mbed_official 324:406fd2029f23 101 * - HW_DMA_INT - Interrupt Request Register
mbed_official 324:406fd2029f23 102 * - HW_DMA_ERR - Error Register
mbed_official 324:406fd2029f23 103 * - HW_DMA_HRS - Hardware Request Status Register
mbed_official 324:406fd2029f23 104 * - HW_DMA_EARS - Enable Asynchronous Request in Stop Register
mbed_official 324:406fd2029f23 105 * - HW_DMA_DCHPRIn - Channel n Priority Register
mbed_official 324:406fd2029f23 106 * - HW_DMA_TCDn_SADDR - TCD Source Address
mbed_official 324:406fd2029f23 107 * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
mbed_official 324:406fd2029f23 108 * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
mbed_official 324:406fd2029f23 109 * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
mbed_official 324:406fd2029f23 110 * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
mbed_official 324:406fd2029f23 111 * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
mbed_official 324:406fd2029f23 112 * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
mbed_official 324:406fd2029f23 113 * - HW_DMA_TCDn_DADDR - TCD Destination Address
mbed_official 324:406fd2029f23 114 * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
mbed_official 324:406fd2029f23 115 * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official 324:406fd2029f23 116 * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official 324:406fd2029f23 117 * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
mbed_official 324:406fd2029f23 118 * - HW_DMA_TCDn_CSR - TCD Control and Status
mbed_official 324:406fd2029f23 119 * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official 324:406fd2029f23 120 * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official 324:406fd2029f23 121 *
mbed_official 324:406fd2029f23 122 * - hw_dma_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 123 */
mbed_official 324:406fd2029f23 124
mbed_official 324:406fd2029f23 125 #define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
mbed_official 324:406fd2029f23 126
mbed_official 324:406fd2029f23 127 /*******************************************************************************
mbed_official 324:406fd2029f23 128 * HW_DMA_CR - Control Register
mbed_official 324:406fd2029f23 129 ******************************************************************************/
mbed_official 324:406fd2029f23 130
mbed_official 324:406fd2029f23 131 /*!
mbed_official 324:406fd2029f23 132 * @brief HW_DMA_CR - Control Register (RW)
mbed_official 324:406fd2029f23 133 *
mbed_official 324:406fd2029f23 134 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 135 *
mbed_official 324:406fd2029f23 136 * The CR defines the basic operating configuration of the DMA. Arbitration can
mbed_official 324:406fd2029f23 137 * be configured to use either a fixed-priority or a round-robin scheme. For
mbed_official 324:406fd2029f23 138 * fixed-priority arbitration, the highest priority channel requesting service is
mbed_official 324:406fd2029f23 139 * selected to execute. The channel priority registers assign the priorities; see
mbed_official 324:406fd2029f23 140 * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
mbed_official 324:406fd2029f23 141 * ignored and channels are cycled through (from high to low channel number)
mbed_official 324:406fd2029f23 142 * without regard to priority. For proper operation, writes to the CR register must be
mbed_official 324:406fd2029f23 143 * performed only when the DMA channels are inactive; that is, when
mbed_official 324:406fd2029f23 144 * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
mbed_official 324:406fd2029f23 145 * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
mbed_official 324:406fd2029f23 146 * minor loop completion. When minor loop offsets are enabled, the minor loop
mbed_official 324:406fd2029f23 147 * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
mbed_official 324:406fd2029f23 148 * destination address (TCDn_DADDR), or to both prior to the addresses being
mbed_official 324:406fd2029f23 149 * written back into the TCD. If the major loop is complete, the minor loop offset is
mbed_official 324:406fd2029f23 150 * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
mbed_official 324:406fd2029f23 151 * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
mbed_official 324:406fd2029f23 152 * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
mbed_official 324:406fd2029f23 153 * is used to specify multiple fields: a source enable bit (SMLOE) to specify the
mbed_official 324:406fd2029f23 154 * minor loop offset should be applied to the source address (TCDn_SADDR) upon
mbed_official 324:406fd2029f23 155 * minor loop completion, a destination enable bit (DMLOE) to specify the minor
mbed_official 324:406fd2029f23 156 * loop offset should be applied to the destination address (TCDn_DADDR) upon minor
mbed_official 324:406fd2029f23 157 * loop completion, and the sign extended minor loop offset value (MLOFF). The
mbed_official 324:406fd2029f23 158 * same offset value (MLOFF) is used for both source and destination minor loop
mbed_official 324:406fd2029f23 159 * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
mbed_official 324:406fd2029f23 160 * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
mbed_official 324:406fd2029f23 161 * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
mbed_official 324:406fd2029f23 162 * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
mbed_official 324:406fd2029f23 163 * assigned to the NBYTES field.
mbed_official 324:406fd2029f23 164 */
mbed_official 324:406fd2029f23 165 typedef union _hw_dma_cr
mbed_official 324:406fd2029f23 166 {
mbed_official 324:406fd2029f23 167 uint32_t U;
mbed_official 324:406fd2029f23 168 struct _hw_dma_cr_bitfields
mbed_official 324:406fd2029f23 169 {
mbed_official 324:406fd2029f23 170 uint32_t RESERVED0 : 1; /*!< [0] Reserved. */
mbed_official 324:406fd2029f23 171 uint32_t EDBG : 1; /*!< [1] Enable Debug */
mbed_official 324:406fd2029f23 172 uint32_t ERCA : 1; /*!< [2] Enable Round Robin Channel Arbitration */
mbed_official 324:406fd2029f23 173 uint32_t RESERVED1 : 1; /*!< [3] Reserved. */
mbed_official 324:406fd2029f23 174 uint32_t HOE : 1; /*!< [4] Halt On Error */
mbed_official 324:406fd2029f23 175 uint32_t HALT : 1; /*!< [5] Halt DMA Operations */
mbed_official 324:406fd2029f23 176 uint32_t CLM : 1; /*!< [6] Continuous Link Mode */
mbed_official 324:406fd2029f23 177 uint32_t EMLM : 1; /*!< [7] Enable Minor Loop Mapping */
mbed_official 324:406fd2029f23 178 uint32_t RESERVED2 : 8; /*!< [15:8] */
mbed_official 324:406fd2029f23 179 uint32_t ECX : 1; /*!< [16] Error Cancel Transfer */
mbed_official 324:406fd2029f23 180 uint32_t CX : 1; /*!< [17] Cancel Transfer */
mbed_official 324:406fd2029f23 181 uint32_t RESERVED3 : 14; /*!< [31:18] */
mbed_official 324:406fd2029f23 182 } B;
mbed_official 324:406fd2029f23 183 } hw_dma_cr_t;
mbed_official 324:406fd2029f23 184
mbed_official 324:406fd2029f23 185 /*!
mbed_official 324:406fd2029f23 186 * @name Constants and macros for entire DMA_CR register
mbed_official 324:406fd2029f23 187 */
mbed_official 324:406fd2029f23 188 /*@{*/
mbed_official 324:406fd2029f23 189 #define HW_DMA_CR_ADDR(x) ((x) + 0x0U)
mbed_official 324:406fd2029f23 190
mbed_official 324:406fd2029f23 191 #define HW_DMA_CR(x) (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
mbed_official 324:406fd2029f23 192 #define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
mbed_official 324:406fd2029f23 193 #define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
mbed_official 324:406fd2029f23 194 #define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) | (v)))
mbed_official 324:406fd2029f23 195 #define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 196 #define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 197 /*@}*/
mbed_official 324:406fd2029f23 198
mbed_official 324:406fd2029f23 199 /*
mbed_official 324:406fd2029f23 200 * Constants & macros for individual DMA_CR bitfields
mbed_official 324:406fd2029f23 201 */
mbed_official 324:406fd2029f23 202
mbed_official 324:406fd2029f23 203 /*!
mbed_official 324:406fd2029f23 204 * @name Register DMA_CR, field EDBG[1] (RW)
mbed_official 324:406fd2029f23 205 *
mbed_official 324:406fd2029f23 206 * Values:
mbed_official 324:406fd2029f23 207 * - 0 - When in debug mode, the DMA continues to operate.
mbed_official 324:406fd2029f23 208 * - 1 - When in debug mode, the DMA stalls the start of a new channel.
mbed_official 324:406fd2029f23 209 * Executing channels are allowed to complete. Channel execution resumes when the
mbed_official 324:406fd2029f23 210 * system exits debug mode or the EDBG bit is cleared.
mbed_official 324:406fd2029f23 211 */
mbed_official 324:406fd2029f23 212 /*@{*/
mbed_official 324:406fd2029f23 213 #define BP_DMA_CR_EDBG (1U) /*!< Bit position for DMA_CR_EDBG. */
mbed_official 324:406fd2029f23 214 #define BM_DMA_CR_EDBG (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */
mbed_official 324:406fd2029f23 215 #define BS_DMA_CR_EDBG (1U) /*!< Bit field size in bits for DMA_CR_EDBG. */
mbed_official 324:406fd2029f23 216
mbed_official 324:406fd2029f23 217 /*! @brief Read current value of the DMA_CR_EDBG field. */
mbed_official 324:406fd2029f23 218 #define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
mbed_official 324:406fd2029f23 219
mbed_official 324:406fd2029f23 220 /*! @brief Format value for bitfield DMA_CR_EDBG. */
mbed_official 324:406fd2029f23 221 #define BF_DMA_CR_EDBG(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG)
mbed_official 324:406fd2029f23 222
mbed_official 324:406fd2029f23 223 /*! @brief Set the EDBG field to a new value. */
mbed_official 324:406fd2029f23 224 #define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
mbed_official 324:406fd2029f23 225 /*@}*/
mbed_official 324:406fd2029f23 226
mbed_official 324:406fd2029f23 227 /*!
mbed_official 324:406fd2029f23 228 * @name Register DMA_CR, field ERCA[2] (RW)
mbed_official 324:406fd2029f23 229 *
mbed_official 324:406fd2029f23 230 * Values:
mbed_official 324:406fd2029f23 231 * - 0 - Fixed priority arbitration is used for channel selection .
mbed_official 324:406fd2029f23 232 * - 1 - Round robin arbitration is used for channel selection .
mbed_official 324:406fd2029f23 233 */
mbed_official 324:406fd2029f23 234 /*@{*/
mbed_official 324:406fd2029f23 235 #define BP_DMA_CR_ERCA (2U) /*!< Bit position for DMA_CR_ERCA. */
mbed_official 324:406fd2029f23 236 #define BM_DMA_CR_ERCA (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */
mbed_official 324:406fd2029f23 237 #define BS_DMA_CR_ERCA (1U) /*!< Bit field size in bits for DMA_CR_ERCA. */
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /*! @brief Read current value of the DMA_CR_ERCA field. */
mbed_official 324:406fd2029f23 240 #define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
mbed_official 324:406fd2029f23 241
mbed_official 324:406fd2029f23 242 /*! @brief Format value for bitfield DMA_CR_ERCA. */
mbed_official 324:406fd2029f23 243 #define BF_DMA_CR_ERCA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA)
mbed_official 324:406fd2029f23 244
mbed_official 324:406fd2029f23 245 /*! @brief Set the ERCA field to a new value. */
mbed_official 324:406fd2029f23 246 #define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
mbed_official 324:406fd2029f23 247 /*@}*/
mbed_official 324:406fd2029f23 248
mbed_official 324:406fd2029f23 249 /*!
mbed_official 324:406fd2029f23 250 * @name Register DMA_CR, field HOE[4] (RW)
mbed_official 324:406fd2029f23 251 *
mbed_official 324:406fd2029f23 252 * Values:
mbed_official 324:406fd2029f23 253 * - 0 - Normal operation
mbed_official 324:406fd2029f23 254 * - 1 - Any error causes the HALT bit to set. Subsequently, all service
mbed_official 324:406fd2029f23 255 * requests are ignored until the HALT bit is cleared.
mbed_official 324:406fd2029f23 256 */
mbed_official 324:406fd2029f23 257 /*@{*/
mbed_official 324:406fd2029f23 258 #define BP_DMA_CR_HOE (4U) /*!< Bit position for DMA_CR_HOE. */
mbed_official 324:406fd2029f23 259 #define BM_DMA_CR_HOE (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */
mbed_official 324:406fd2029f23 260 #define BS_DMA_CR_HOE (1U) /*!< Bit field size in bits for DMA_CR_HOE. */
mbed_official 324:406fd2029f23 261
mbed_official 324:406fd2029f23 262 /*! @brief Read current value of the DMA_CR_HOE field. */
mbed_official 324:406fd2029f23 263 #define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*! @brief Format value for bitfield DMA_CR_HOE. */
mbed_official 324:406fd2029f23 266 #define BF_DMA_CR_HOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE)
mbed_official 324:406fd2029f23 267
mbed_official 324:406fd2029f23 268 /*! @brief Set the HOE field to a new value. */
mbed_official 324:406fd2029f23 269 #define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
mbed_official 324:406fd2029f23 270 /*@}*/
mbed_official 324:406fd2029f23 271
mbed_official 324:406fd2029f23 272 /*!
mbed_official 324:406fd2029f23 273 * @name Register DMA_CR, field HALT[5] (RW)
mbed_official 324:406fd2029f23 274 *
mbed_official 324:406fd2029f23 275 * Values:
mbed_official 324:406fd2029f23 276 * - 0 - Normal operation
mbed_official 324:406fd2029f23 277 * - 1 - Stall the start of any new channels. Executing channels are allowed to
mbed_official 324:406fd2029f23 278 * complete. Channel execution resumes when this bit is cleared.
mbed_official 324:406fd2029f23 279 */
mbed_official 324:406fd2029f23 280 /*@{*/
mbed_official 324:406fd2029f23 281 #define BP_DMA_CR_HALT (5U) /*!< Bit position for DMA_CR_HALT. */
mbed_official 324:406fd2029f23 282 #define BM_DMA_CR_HALT (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */
mbed_official 324:406fd2029f23 283 #define BS_DMA_CR_HALT (1U) /*!< Bit field size in bits for DMA_CR_HALT. */
mbed_official 324:406fd2029f23 284
mbed_official 324:406fd2029f23 285 /*! @brief Read current value of the DMA_CR_HALT field. */
mbed_official 324:406fd2029f23 286 #define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
mbed_official 324:406fd2029f23 287
mbed_official 324:406fd2029f23 288 /*! @brief Format value for bitfield DMA_CR_HALT. */
mbed_official 324:406fd2029f23 289 #define BF_DMA_CR_HALT(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT)
mbed_official 324:406fd2029f23 290
mbed_official 324:406fd2029f23 291 /*! @brief Set the HALT field to a new value. */
mbed_official 324:406fd2029f23 292 #define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
mbed_official 324:406fd2029f23 293 /*@}*/
mbed_official 324:406fd2029f23 294
mbed_official 324:406fd2029f23 295 /*!
mbed_official 324:406fd2029f23 296 * @name Register DMA_CR, field CLM[6] (RW)
mbed_official 324:406fd2029f23 297 *
mbed_official 324:406fd2029f23 298 * Values:
mbed_official 324:406fd2029f23 299 * - 0 - A minor loop channel link made to itself goes through channel
mbed_official 324:406fd2029f23 300 * arbitration before being activated again.
mbed_official 324:406fd2029f23 301 * - 1 - A minor loop channel link made to itself does not go through channel
mbed_official 324:406fd2029f23 302 * arbitration before being activated again. Upon minor loop completion, the
mbed_official 324:406fd2029f23 303 * channel activates again if that channel has a minor loop channel link
mbed_official 324:406fd2029f23 304 * enabled and the link channel is itself. This effectively applies the minor loop
mbed_official 324:406fd2029f23 305 * offsets and restarts the next minor loop.
mbed_official 324:406fd2029f23 306 */
mbed_official 324:406fd2029f23 307 /*@{*/
mbed_official 324:406fd2029f23 308 #define BP_DMA_CR_CLM (6U) /*!< Bit position for DMA_CR_CLM. */
mbed_official 324:406fd2029f23 309 #define BM_DMA_CR_CLM (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */
mbed_official 324:406fd2029f23 310 #define BS_DMA_CR_CLM (1U) /*!< Bit field size in bits for DMA_CR_CLM. */
mbed_official 324:406fd2029f23 311
mbed_official 324:406fd2029f23 312 /*! @brief Read current value of the DMA_CR_CLM field. */
mbed_official 324:406fd2029f23 313 #define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
mbed_official 324:406fd2029f23 314
mbed_official 324:406fd2029f23 315 /*! @brief Format value for bitfield DMA_CR_CLM. */
mbed_official 324:406fd2029f23 316 #define BF_DMA_CR_CLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM)
mbed_official 324:406fd2029f23 317
mbed_official 324:406fd2029f23 318 /*! @brief Set the CLM field to a new value. */
mbed_official 324:406fd2029f23 319 #define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
mbed_official 324:406fd2029f23 320 /*@}*/
mbed_official 324:406fd2029f23 321
mbed_official 324:406fd2029f23 322 /*!
mbed_official 324:406fd2029f23 323 * @name Register DMA_CR, field EMLM[7] (RW)
mbed_official 324:406fd2029f23 324 *
mbed_official 324:406fd2029f23 325 * Values:
mbed_official 324:406fd2029f23 326 * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
mbed_official 324:406fd2029f23 327 * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
mbed_official 324:406fd2029f23 328 * an offset field, and the NBYTES field. The individual enable fields allow
mbed_official 324:406fd2029f23 329 * the minor loop offset to be applied to the source address, the destination
mbed_official 324:406fd2029f23 330 * address, or both. The NBYTES field is reduced when either offset is
mbed_official 324:406fd2029f23 331 * enabled.
mbed_official 324:406fd2029f23 332 */
mbed_official 324:406fd2029f23 333 /*@{*/
mbed_official 324:406fd2029f23 334 #define BP_DMA_CR_EMLM (7U) /*!< Bit position for DMA_CR_EMLM. */
mbed_official 324:406fd2029f23 335 #define BM_DMA_CR_EMLM (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */
mbed_official 324:406fd2029f23 336 #define BS_DMA_CR_EMLM (1U) /*!< Bit field size in bits for DMA_CR_EMLM. */
mbed_official 324:406fd2029f23 337
mbed_official 324:406fd2029f23 338 /*! @brief Read current value of the DMA_CR_EMLM field. */
mbed_official 324:406fd2029f23 339 #define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
mbed_official 324:406fd2029f23 340
mbed_official 324:406fd2029f23 341 /*! @brief Format value for bitfield DMA_CR_EMLM. */
mbed_official 324:406fd2029f23 342 #define BF_DMA_CR_EMLM(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM)
mbed_official 324:406fd2029f23 343
mbed_official 324:406fd2029f23 344 /*! @brief Set the EMLM field to a new value. */
mbed_official 324:406fd2029f23 345 #define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
mbed_official 324:406fd2029f23 346 /*@}*/
mbed_official 324:406fd2029f23 347
mbed_official 324:406fd2029f23 348 /*!
mbed_official 324:406fd2029f23 349 * @name Register DMA_CR, field ECX[16] (RW)
mbed_official 324:406fd2029f23 350 *
mbed_official 324:406fd2029f23 351 * Values:
mbed_official 324:406fd2029f23 352 * - 0 - Normal operation
mbed_official 324:406fd2029f23 353 * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
mbed_official 324:406fd2029f23 354 * Stop the executing channel and force the minor loop to finish. The cancel
mbed_official 324:406fd2029f23 355 * takes effect after the last write of the current read/write sequence. The
mbed_official 324:406fd2029f23 356 * ECX bit clears itself after the cancel is honored. In addition to
mbed_official 324:406fd2029f23 357 * cancelling the transfer, ECX treats the cancel as an error condition, thus updating
mbed_official 324:406fd2029f23 358 * the Error Status register (DMAx_ES) and generating an optional error
mbed_official 324:406fd2029f23 359 * interrupt.
mbed_official 324:406fd2029f23 360 */
mbed_official 324:406fd2029f23 361 /*@{*/
mbed_official 324:406fd2029f23 362 #define BP_DMA_CR_ECX (16U) /*!< Bit position for DMA_CR_ECX. */
mbed_official 324:406fd2029f23 363 #define BM_DMA_CR_ECX (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */
mbed_official 324:406fd2029f23 364 #define BS_DMA_CR_ECX (1U) /*!< Bit field size in bits for DMA_CR_ECX. */
mbed_official 324:406fd2029f23 365
mbed_official 324:406fd2029f23 366 /*! @brief Read current value of the DMA_CR_ECX field. */
mbed_official 324:406fd2029f23 367 #define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
mbed_official 324:406fd2029f23 368
mbed_official 324:406fd2029f23 369 /*! @brief Format value for bitfield DMA_CR_ECX. */
mbed_official 324:406fd2029f23 370 #define BF_DMA_CR_ECX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX)
mbed_official 324:406fd2029f23 371
mbed_official 324:406fd2029f23 372 /*! @brief Set the ECX field to a new value. */
mbed_official 324:406fd2029f23 373 #define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
mbed_official 324:406fd2029f23 374 /*@}*/
mbed_official 324:406fd2029f23 375
mbed_official 324:406fd2029f23 376 /*!
mbed_official 324:406fd2029f23 377 * @name Register DMA_CR, field CX[17] (RW)
mbed_official 324:406fd2029f23 378 *
mbed_official 324:406fd2029f23 379 * Values:
mbed_official 324:406fd2029f23 380 * - 0 - Normal operation
mbed_official 324:406fd2029f23 381 * - 1 - Cancel the remaining data transfer. Stop the executing channel and
mbed_official 324:406fd2029f23 382 * force the minor loop to finish. The cancel takes effect after the last write
mbed_official 324:406fd2029f23 383 * of the current read/write sequence. The CX bit clears itself after the
mbed_official 324:406fd2029f23 384 * cancel has been honored. This cancel retires the channel normally as if the
mbed_official 324:406fd2029f23 385 * minor loop was completed.
mbed_official 324:406fd2029f23 386 */
mbed_official 324:406fd2029f23 387 /*@{*/
mbed_official 324:406fd2029f23 388 #define BP_DMA_CR_CX (17U) /*!< Bit position for DMA_CR_CX. */
mbed_official 324:406fd2029f23 389 #define BM_DMA_CR_CX (0x00020000U) /*!< Bit mask for DMA_CR_CX. */
mbed_official 324:406fd2029f23 390 #define BS_DMA_CR_CX (1U) /*!< Bit field size in bits for DMA_CR_CX. */
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392 /*! @brief Read current value of the DMA_CR_CX field. */
mbed_official 324:406fd2029f23 393 #define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
mbed_official 324:406fd2029f23 394
mbed_official 324:406fd2029f23 395 /*! @brief Format value for bitfield DMA_CR_CX. */
mbed_official 324:406fd2029f23 396 #define BF_DMA_CR_CX(v) ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX)
mbed_official 324:406fd2029f23 397
mbed_official 324:406fd2029f23 398 /*! @brief Set the CX field to a new value. */
mbed_official 324:406fd2029f23 399 #define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
mbed_official 324:406fd2029f23 400 /*@}*/
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /*******************************************************************************
mbed_official 324:406fd2029f23 403 * HW_DMA_ES - Error Status Register
mbed_official 324:406fd2029f23 404 ******************************************************************************/
mbed_official 324:406fd2029f23 405
mbed_official 324:406fd2029f23 406 /*!
mbed_official 324:406fd2029f23 407 * @brief HW_DMA_ES - Error Status Register (RO)
mbed_official 324:406fd2029f23 408 *
mbed_official 324:406fd2029f23 409 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 410 *
mbed_official 324:406fd2029f23 411 * The ES provides information concerning the last recorded channel error.
mbed_official 324:406fd2029f23 412 * Channel errors can be caused by: A configuration error, that is: An illegal setting
mbed_official 324:406fd2029f23 413 * in the transfer-control descriptor, or An illegal priority register setting
mbed_official 324:406fd2029f23 414 * in fixed-arbitration An error termination to a bus master read or write cycle
mbed_official 324:406fd2029f23 415 * See the Error Reporting and Handling section for more details.
mbed_official 324:406fd2029f23 416 */
mbed_official 324:406fd2029f23 417 typedef union _hw_dma_es
mbed_official 324:406fd2029f23 418 {
mbed_official 324:406fd2029f23 419 uint32_t U;
mbed_official 324:406fd2029f23 420 struct _hw_dma_es_bitfields
mbed_official 324:406fd2029f23 421 {
mbed_official 324:406fd2029f23 422 uint32_t DBE : 1; /*!< [0] Destination Bus Error */
mbed_official 324:406fd2029f23 423 uint32_t SBE : 1; /*!< [1] Source Bus Error */
mbed_official 324:406fd2029f23 424 uint32_t SGE : 1; /*!< [2] Scatter/Gather Configuration Error */
mbed_official 324:406fd2029f23 425 uint32_t NCE : 1; /*!< [3] NBYTES/CITER Configuration Error */
mbed_official 324:406fd2029f23 426 uint32_t DOE : 1; /*!< [4] Destination Offset Error */
mbed_official 324:406fd2029f23 427 uint32_t DAE : 1; /*!< [5] Destination Address Error */
mbed_official 324:406fd2029f23 428 uint32_t SOE : 1; /*!< [6] Source Offset Error */
mbed_official 324:406fd2029f23 429 uint32_t SAE : 1; /*!< [7] Source Address Error */
mbed_official 324:406fd2029f23 430 uint32_t ERRCHN : 4; /*!< [11:8] Error Channel Number or Canceled
mbed_official 324:406fd2029f23 431 * Channel Number */
mbed_official 324:406fd2029f23 432 uint32_t RESERVED0 : 2; /*!< [13:12] */
mbed_official 324:406fd2029f23 433 uint32_t CPE : 1; /*!< [14] Channel Priority Error */
mbed_official 324:406fd2029f23 434 uint32_t RESERVED1 : 1; /*!< [15] */
mbed_official 324:406fd2029f23 435 uint32_t ECX : 1; /*!< [16] Transfer Canceled */
mbed_official 324:406fd2029f23 436 uint32_t RESERVED2 : 14; /*!< [30:17] */
mbed_official 324:406fd2029f23 437 uint32_t VLD : 1; /*!< [31] */
mbed_official 324:406fd2029f23 438 } B;
mbed_official 324:406fd2029f23 439 } hw_dma_es_t;
mbed_official 324:406fd2029f23 440
mbed_official 324:406fd2029f23 441 /*!
mbed_official 324:406fd2029f23 442 * @name Constants and macros for entire DMA_ES register
mbed_official 324:406fd2029f23 443 */
mbed_official 324:406fd2029f23 444 /*@{*/
mbed_official 324:406fd2029f23 445 #define HW_DMA_ES_ADDR(x) ((x) + 0x4U)
mbed_official 324:406fd2029f23 446
mbed_official 324:406fd2029f23 447 #define HW_DMA_ES(x) (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
mbed_official 324:406fd2029f23 448 #define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
mbed_official 324:406fd2029f23 449 /*@}*/
mbed_official 324:406fd2029f23 450
mbed_official 324:406fd2029f23 451 /*
mbed_official 324:406fd2029f23 452 * Constants & macros for individual DMA_ES bitfields
mbed_official 324:406fd2029f23 453 */
mbed_official 324:406fd2029f23 454
mbed_official 324:406fd2029f23 455 /*!
mbed_official 324:406fd2029f23 456 * @name Register DMA_ES, field DBE[0] (RO)
mbed_official 324:406fd2029f23 457 *
mbed_official 324:406fd2029f23 458 * Values:
mbed_official 324:406fd2029f23 459 * - 0 - No destination bus error
mbed_official 324:406fd2029f23 460 * - 1 - The last recorded error was a bus error on a destination write
mbed_official 324:406fd2029f23 461 */
mbed_official 324:406fd2029f23 462 /*@{*/
mbed_official 324:406fd2029f23 463 #define BP_DMA_ES_DBE (0U) /*!< Bit position for DMA_ES_DBE. */
mbed_official 324:406fd2029f23 464 #define BM_DMA_ES_DBE (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */
mbed_official 324:406fd2029f23 465 #define BS_DMA_ES_DBE (1U) /*!< Bit field size in bits for DMA_ES_DBE. */
mbed_official 324:406fd2029f23 466
mbed_official 324:406fd2029f23 467 /*! @brief Read current value of the DMA_ES_DBE field. */
mbed_official 324:406fd2029f23 468 #define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
mbed_official 324:406fd2029f23 469 /*@}*/
mbed_official 324:406fd2029f23 470
mbed_official 324:406fd2029f23 471 /*!
mbed_official 324:406fd2029f23 472 * @name Register DMA_ES, field SBE[1] (RO)
mbed_official 324:406fd2029f23 473 *
mbed_official 324:406fd2029f23 474 * Values:
mbed_official 324:406fd2029f23 475 * - 0 - No source bus error
mbed_official 324:406fd2029f23 476 * - 1 - The last recorded error was a bus error on a source read
mbed_official 324:406fd2029f23 477 */
mbed_official 324:406fd2029f23 478 /*@{*/
mbed_official 324:406fd2029f23 479 #define BP_DMA_ES_SBE (1U) /*!< Bit position for DMA_ES_SBE. */
mbed_official 324:406fd2029f23 480 #define BM_DMA_ES_SBE (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */
mbed_official 324:406fd2029f23 481 #define BS_DMA_ES_SBE (1U) /*!< Bit field size in bits for DMA_ES_SBE. */
mbed_official 324:406fd2029f23 482
mbed_official 324:406fd2029f23 483 /*! @brief Read current value of the DMA_ES_SBE field. */
mbed_official 324:406fd2029f23 484 #define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
mbed_official 324:406fd2029f23 485 /*@}*/
mbed_official 324:406fd2029f23 486
mbed_official 324:406fd2029f23 487 /*!
mbed_official 324:406fd2029f23 488 * @name Register DMA_ES, field SGE[2] (RO)
mbed_official 324:406fd2029f23 489 *
mbed_official 324:406fd2029f23 490 * Values:
mbed_official 324:406fd2029f23 491 * - 0 - No scatter/gather configuration error
mbed_official 324:406fd2029f23 492 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 493 * TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
mbed_official 324:406fd2029f23 494 * operation after major loop completion if TCDn_CSR[ESG] is enabled.
mbed_official 324:406fd2029f23 495 * TCDn_DLASTSGA is not on a 32 byte boundary.
mbed_official 324:406fd2029f23 496 */
mbed_official 324:406fd2029f23 497 /*@{*/
mbed_official 324:406fd2029f23 498 #define BP_DMA_ES_SGE (2U) /*!< Bit position for DMA_ES_SGE. */
mbed_official 324:406fd2029f23 499 #define BM_DMA_ES_SGE (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */
mbed_official 324:406fd2029f23 500 #define BS_DMA_ES_SGE (1U) /*!< Bit field size in bits for DMA_ES_SGE. */
mbed_official 324:406fd2029f23 501
mbed_official 324:406fd2029f23 502 /*! @brief Read current value of the DMA_ES_SGE field. */
mbed_official 324:406fd2029f23 503 #define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
mbed_official 324:406fd2029f23 504 /*@}*/
mbed_official 324:406fd2029f23 505
mbed_official 324:406fd2029f23 506 /*!
mbed_official 324:406fd2029f23 507 * @name Register DMA_ES, field NCE[3] (RO)
mbed_official 324:406fd2029f23 508 *
mbed_official 324:406fd2029f23 509 * Values:
mbed_official 324:406fd2029f23 510 * - 0 - No NBYTES/CITER configuration error
mbed_official 324:406fd2029f23 511 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 512 * TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
mbed_official 324:406fd2029f23 513 * TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
mbed_official 324:406fd2029f23 514 * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
mbed_official 324:406fd2029f23 515 */
mbed_official 324:406fd2029f23 516 /*@{*/
mbed_official 324:406fd2029f23 517 #define BP_DMA_ES_NCE (3U) /*!< Bit position for DMA_ES_NCE. */
mbed_official 324:406fd2029f23 518 #define BM_DMA_ES_NCE (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */
mbed_official 324:406fd2029f23 519 #define BS_DMA_ES_NCE (1U) /*!< Bit field size in bits for DMA_ES_NCE. */
mbed_official 324:406fd2029f23 520
mbed_official 324:406fd2029f23 521 /*! @brief Read current value of the DMA_ES_NCE field. */
mbed_official 324:406fd2029f23 522 #define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
mbed_official 324:406fd2029f23 523 /*@}*/
mbed_official 324:406fd2029f23 524
mbed_official 324:406fd2029f23 525 /*!
mbed_official 324:406fd2029f23 526 * @name Register DMA_ES, field DOE[4] (RO)
mbed_official 324:406fd2029f23 527 *
mbed_official 324:406fd2029f23 528 * Values:
mbed_official 324:406fd2029f23 529 * - 0 - No destination offset configuration error
mbed_official 324:406fd2029f23 530 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 531 * TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
mbed_official 324:406fd2029f23 532 */
mbed_official 324:406fd2029f23 533 /*@{*/
mbed_official 324:406fd2029f23 534 #define BP_DMA_ES_DOE (4U) /*!< Bit position for DMA_ES_DOE. */
mbed_official 324:406fd2029f23 535 #define BM_DMA_ES_DOE (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */
mbed_official 324:406fd2029f23 536 #define BS_DMA_ES_DOE (1U) /*!< Bit field size in bits for DMA_ES_DOE. */
mbed_official 324:406fd2029f23 537
mbed_official 324:406fd2029f23 538 /*! @brief Read current value of the DMA_ES_DOE field. */
mbed_official 324:406fd2029f23 539 #define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
mbed_official 324:406fd2029f23 540 /*@}*/
mbed_official 324:406fd2029f23 541
mbed_official 324:406fd2029f23 542 /*!
mbed_official 324:406fd2029f23 543 * @name Register DMA_ES, field DAE[5] (RO)
mbed_official 324:406fd2029f23 544 *
mbed_official 324:406fd2029f23 545 * Values:
mbed_official 324:406fd2029f23 546 * - 0 - No destination address configuration error
mbed_official 324:406fd2029f23 547 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 548 * TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
mbed_official 324:406fd2029f23 549 */
mbed_official 324:406fd2029f23 550 /*@{*/
mbed_official 324:406fd2029f23 551 #define BP_DMA_ES_DAE (5U) /*!< Bit position for DMA_ES_DAE. */
mbed_official 324:406fd2029f23 552 #define BM_DMA_ES_DAE (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */
mbed_official 324:406fd2029f23 553 #define BS_DMA_ES_DAE (1U) /*!< Bit field size in bits for DMA_ES_DAE. */
mbed_official 324:406fd2029f23 554
mbed_official 324:406fd2029f23 555 /*! @brief Read current value of the DMA_ES_DAE field. */
mbed_official 324:406fd2029f23 556 #define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
mbed_official 324:406fd2029f23 557 /*@}*/
mbed_official 324:406fd2029f23 558
mbed_official 324:406fd2029f23 559 /*!
mbed_official 324:406fd2029f23 560 * @name Register DMA_ES, field SOE[6] (RO)
mbed_official 324:406fd2029f23 561 *
mbed_official 324:406fd2029f23 562 * Values:
mbed_official 324:406fd2029f23 563 * - 0 - No source offset configuration error
mbed_official 324:406fd2029f23 564 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 565 * TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
mbed_official 324:406fd2029f23 566 */
mbed_official 324:406fd2029f23 567 /*@{*/
mbed_official 324:406fd2029f23 568 #define BP_DMA_ES_SOE (6U) /*!< Bit position for DMA_ES_SOE. */
mbed_official 324:406fd2029f23 569 #define BM_DMA_ES_SOE (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */
mbed_official 324:406fd2029f23 570 #define BS_DMA_ES_SOE (1U) /*!< Bit field size in bits for DMA_ES_SOE. */
mbed_official 324:406fd2029f23 571
mbed_official 324:406fd2029f23 572 /*! @brief Read current value of the DMA_ES_SOE field. */
mbed_official 324:406fd2029f23 573 #define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
mbed_official 324:406fd2029f23 574 /*@}*/
mbed_official 324:406fd2029f23 575
mbed_official 324:406fd2029f23 576 /*!
mbed_official 324:406fd2029f23 577 * @name Register DMA_ES, field SAE[7] (RO)
mbed_official 324:406fd2029f23 578 *
mbed_official 324:406fd2029f23 579 * Values:
mbed_official 324:406fd2029f23 580 * - 0 - No source address configuration error.
mbed_official 324:406fd2029f23 581 * - 1 - The last recorded error was a configuration error detected in the
mbed_official 324:406fd2029f23 582 * TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
mbed_official 324:406fd2029f23 583 */
mbed_official 324:406fd2029f23 584 /*@{*/
mbed_official 324:406fd2029f23 585 #define BP_DMA_ES_SAE (7U) /*!< Bit position for DMA_ES_SAE. */
mbed_official 324:406fd2029f23 586 #define BM_DMA_ES_SAE (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */
mbed_official 324:406fd2029f23 587 #define BS_DMA_ES_SAE (1U) /*!< Bit field size in bits for DMA_ES_SAE. */
mbed_official 324:406fd2029f23 588
mbed_official 324:406fd2029f23 589 /*! @brief Read current value of the DMA_ES_SAE field. */
mbed_official 324:406fd2029f23 590 #define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
mbed_official 324:406fd2029f23 591 /*@}*/
mbed_official 324:406fd2029f23 592
mbed_official 324:406fd2029f23 593 /*!
mbed_official 324:406fd2029f23 594 * @name Register DMA_ES, field ERRCHN[11:8] (RO)
mbed_official 324:406fd2029f23 595 *
mbed_official 324:406fd2029f23 596 * The channel number of the last recorded error (excluding CPE errors) or last
mbed_official 324:406fd2029f23 597 * recorded error canceled transfer.
mbed_official 324:406fd2029f23 598 */
mbed_official 324:406fd2029f23 599 /*@{*/
mbed_official 324:406fd2029f23 600 #define BP_DMA_ES_ERRCHN (8U) /*!< Bit position for DMA_ES_ERRCHN. */
mbed_official 324:406fd2029f23 601 #define BM_DMA_ES_ERRCHN (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */
mbed_official 324:406fd2029f23 602 #define BS_DMA_ES_ERRCHN (4U) /*!< Bit field size in bits for DMA_ES_ERRCHN. */
mbed_official 324:406fd2029f23 603
mbed_official 324:406fd2029f23 604 /*! @brief Read current value of the DMA_ES_ERRCHN field. */
mbed_official 324:406fd2029f23 605 #define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
mbed_official 324:406fd2029f23 606 /*@}*/
mbed_official 324:406fd2029f23 607
mbed_official 324:406fd2029f23 608 /*!
mbed_official 324:406fd2029f23 609 * @name Register DMA_ES, field CPE[14] (RO)
mbed_official 324:406fd2029f23 610 *
mbed_official 324:406fd2029f23 611 * Values:
mbed_official 324:406fd2029f23 612 * - 0 - No channel priority error
mbed_official 324:406fd2029f23 613 * - 1 - The last recorded error was a configuration error in the channel
mbed_official 324:406fd2029f23 614 * priorities . Channel priorities are not unique.
mbed_official 324:406fd2029f23 615 */
mbed_official 324:406fd2029f23 616 /*@{*/
mbed_official 324:406fd2029f23 617 #define BP_DMA_ES_CPE (14U) /*!< Bit position for DMA_ES_CPE. */
mbed_official 324:406fd2029f23 618 #define BM_DMA_ES_CPE (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */
mbed_official 324:406fd2029f23 619 #define BS_DMA_ES_CPE (1U) /*!< Bit field size in bits for DMA_ES_CPE. */
mbed_official 324:406fd2029f23 620
mbed_official 324:406fd2029f23 621 /*! @brief Read current value of the DMA_ES_CPE field. */
mbed_official 324:406fd2029f23 622 #define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
mbed_official 324:406fd2029f23 623 /*@}*/
mbed_official 324:406fd2029f23 624
mbed_official 324:406fd2029f23 625 /*!
mbed_official 324:406fd2029f23 626 * @name Register DMA_ES, field ECX[16] (RO)
mbed_official 324:406fd2029f23 627 *
mbed_official 324:406fd2029f23 628 * Values:
mbed_official 324:406fd2029f23 629 * - 0 - No canceled transfers
mbed_official 324:406fd2029f23 630 * - 1 - The last recorded entry was a canceled transfer by the error cancel
mbed_official 324:406fd2029f23 631 * transfer input
mbed_official 324:406fd2029f23 632 */
mbed_official 324:406fd2029f23 633 /*@{*/
mbed_official 324:406fd2029f23 634 #define BP_DMA_ES_ECX (16U) /*!< Bit position for DMA_ES_ECX. */
mbed_official 324:406fd2029f23 635 #define BM_DMA_ES_ECX (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */
mbed_official 324:406fd2029f23 636 #define BS_DMA_ES_ECX (1U) /*!< Bit field size in bits for DMA_ES_ECX. */
mbed_official 324:406fd2029f23 637
mbed_official 324:406fd2029f23 638 /*! @brief Read current value of the DMA_ES_ECX field. */
mbed_official 324:406fd2029f23 639 #define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
mbed_official 324:406fd2029f23 640 /*@}*/
mbed_official 324:406fd2029f23 641
mbed_official 324:406fd2029f23 642 /*!
mbed_official 324:406fd2029f23 643 * @name Register DMA_ES, field VLD[31] (RO)
mbed_official 324:406fd2029f23 644 *
mbed_official 324:406fd2029f23 645 * Logical OR of all ERR status bits
mbed_official 324:406fd2029f23 646 *
mbed_official 324:406fd2029f23 647 * Values:
mbed_official 324:406fd2029f23 648 * - 0 - No ERR bits are set
mbed_official 324:406fd2029f23 649 * - 1 - At least one ERR bit is set indicating a valid error exists that has
mbed_official 324:406fd2029f23 650 * not been cleared
mbed_official 324:406fd2029f23 651 */
mbed_official 324:406fd2029f23 652 /*@{*/
mbed_official 324:406fd2029f23 653 #define BP_DMA_ES_VLD (31U) /*!< Bit position for DMA_ES_VLD. */
mbed_official 324:406fd2029f23 654 #define BM_DMA_ES_VLD (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */
mbed_official 324:406fd2029f23 655 #define BS_DMA_ES_VLD (1U) /*!< Bit field size in bits for DMA_ES_VLD. */
mbed_official 324:406fd2029f23 656
mbed_official 324:406fd2029f23 657 /*! @brief Read current value of the DMA_ES_VLD field. */
mbed_official 324:406fd2029f23 658 #define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
mbed_official 324:406fd2029f23 659 /*@}*/
mbed_official 324:406fd2029f23 660
mbed_official 324:406fd2029f23 661 /*******************************************************************************
mbed_official 324:406fd2029f23 662 * HW_DMA_ERQ - Enable Request Register
mbed_official 324:406fd2029f23 663 ******************************************************************************/
mbed_official 324:406fd2029f23 664
mbed_official 324:406fd2029f23 665 /*!
mbed_official 324:406fd2029f23 666 * @brief HW_DMA_ERQ - Enable Request Register (RW)
mbed_official 324:406fd2029f23 667 *
mbed_official 324:406fd2029f23 668 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 669 *
mbed_official 324:406fd2029f23 670 * The ERQ register provides a bit map for the 16 implemented channels to enable
mbed_official 324:406fd2029f23 671 * the request signal for each channel. The state of any given channel enable is
mbed_official 324:406fd2029f23 672 * directly affected by writes to this register; it is also affected by writes
mbed_official 324:406fd2029f23 673 * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
mbed_official 324:406fd2029f23 674 * for a single channel can easily be modified without needing to perform a
mbed_official 324:406fd2029f23 675 * read-modify-write sequence to the ERQ. DMA request input signals and this enable
mbed_official 324:406fd2029f23 676 * request flag must be asserted before a channel's hardware service request is
mbed_official 324:406fd2029f23 677 * accepted. The state of the DMA enable request flag does not affect a channel
mbed_official 324:406fd2029f23 678 * service request made explicitly through software or a linked channel request.
mbed_official 324:406fd2029f23 679 */
mbed_official 324:406fd2029f23 680 typedef union _hw_dma_erq
mbed_official 324:406fd2029f23 681 {
mbed_official 324:406fd2029f23 682 uint32_t U;
mbed_official 324:406fd2029f23 683 struct _hw_dma_erq_bitfields
mbed_official 324:406fd2029f23 684 {
mbed_official 324:406fd2029f23 685 uint32_t ERQ0 : 1; /*!< [0] Enable DMA Request 0 */
mbed_official 324:406fd2029f23 686 uint32_t ERQ1 : 1; /*!< [1] Enable DMA Request 1 */
mbed_official 324:406fd2029f23 687 uint32_t ERQ2 : 1; /*!< [2] Enable DMA Request 2 */
mbed_official 324:406fd2029f23 688 uint32_t ERQ3 : 1; /*!< [3] Enable DMA Request 3 */
mbed_official 324:406fd2029f23 689 uint32_t ERQ4 : 1; /*!< [4] Enable DMA Request 4 */
mbed_official 324:406fd2029f23 690 uint32_t ERQ5 : 1; /*!< [5] Enable DMA Request 5 */
mbed_official 324:406fd2029f23 691 uint32_t ERQ6 : 1; /*!< [6] Enable DMA Request 6 */
mbed_official 324:406fd2029f23 692 uint32_t ERQ7 : 1; /*!< [7] Enable DMA Request 7 */
mbed_official 324:406fd2029f23 693 uint32_t ERQ8 : 1; /*!< [8] Enable DMA Request 8 */
mbed_official 324:406fd2029f23 694 uint32_t ERQ9 : 1; /*!< [9] Enable DMA Request 9 */
mbed_official 324:406fd2029f23 695 uint32_t ERQ10 : 1; /*!< [10] Enable DMA Request 10 */
mbed_official 324:406fd2029f23 696 uint32_t ERQ11 : 1; /*!< [11] Enable DMA Request 11 */
mbed_official 324:406fd2029f23 697 uint32_t ERQ12 : 1; /*!< [12] Enable DMA Request 12 */
mbed_official 324:406fd2029f23 698 uint32_t ERQ13 : 1; /*!< [13] Enable DMA Request 13 */
mbed_official 324:406fd2029f23 699 uint32_t ERQ14 : 1; /*!< [14] Enable DMA Request 14 */
mbed_official 324:406fd2029f23 700 uint32_t ERQ15 : 1; /*!< [15] Enable DMA Request 15 */
mbed_official 324:406fd2029f23 701 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 702 } B;
mbed_official 324:406fd2029f23 703 } hw_dma_erq_t;
mbed_official 324:406fd2029f23 704
mbed_official 324:406fd2029f23 705 /*!
mbed_official 324:406fd2029f23 706 * @name Constants and macros for entire DMA_ERQ register
mbed_official 324:406fd2029f23 707 */
mbed_official 324:406fd2029f23 708 /*@{*/
mbed_official 324:406fd2029f23 709 #define HW_DMA_ERQ_ADDR(x) ((x) + 0xCU)
mbed_official 324:406fd2029f23 710
mbed_official 324:406fd2029f23 711 #define HW_DMA_ERQ(x) (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
mbed_official 324:406fd2029f23 712 #define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
mbed_official 324:406fd2029f23 713 #define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
mbed_official 324:406fd2029f23 714 #define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) | (v)))
mbed_official 324:406fd2029f23 715 #define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 716 #define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 717 /*@}*/
mbed_official 324:406fd2029f23 718
mbed_official 324:406fd2029f23 719 /*
mbed_official 324:406fd2029f23 720 * Constants & macros for individual DMA_ERQ bitfields
mbed_official 324:406fd2029f23 721 */
mbed_official 324:406fd2029f23 722
mbed_official 324:406fd2029f23 723 /*!
mbed_official 324:406fd2029f23 724 * @name Register DMA_ERQ, field ERQ0[0] (RW)
mbed_official 324:406fd2029f23 725 *
mbed_official 324:406fd2029f23 726 * Values:
mbed_official 324:406fd2029f23 727 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 728 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 729 */
mbed_official 324:406fd2029f23 730 /*@{*/
mbed_official 324:406fd2029f23 731 #define BP_DMA_ERQ_ERQ0 (0U) /*!< Bit position for DMA_ERQ_ERQ0. */
mbed_official 324:406fd2029f23 732 #define BM_DMA_ERQ_ERQ0 (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */
mbed_official 324:406fd2029f23 733 #define BS_DMA_ERQ_ERQ0 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ0. */
mbed_official 324:406fd2029f23 734
mbed_official 324:406fd2029f23 735 /*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
mbed_official 324:406fd2029f23 736 #define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
mbed_official 324:406fd2029f23 737
mbed_official 324:406fd2029f23 738 /*! @brief Format value for bitfield DMA_ERQ_ERQ0. */
mbed_official 324:406fd2029f23 739 #define BF_DMA_ERQ_ERQ0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0)
mbed_official 324:406fd2029f23 740
mbed_official 324:406fd2029f23 741 /*! @brief Set the ERQ0 field to a new value. */
mbed_official 324:406fd2029f23 742 #define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
mbed_official 324:406fd2029f23 743 /*@}*/
mbed_official 324:406fd2029f23 744
mbed_official 324:406fd2029f23 745 /*!
mbed_official 324:406fd2029f23 746 * @name Register DMA_ERQ, field ERQ1[1] (RW)
mbed_official 324:406fd2029f23 747 *
mbed_official 324:406fd2029f23 748 * Values:
mbed_official 324:406fd2029f23 749 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 750 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 751 */
mbed_official 324:406fd2029f23 752 /*@{*/
mbed_official 324:406fd2029f23 753 #define BP_DMA_ERQ_ERQ1 (1U) /*!< Bit position for DMA_ERQ_ERQ1. */
mbed_official 324:406fd2029f23 754 #define BM_DMA_ERQ_ERQ1 (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */
mbed_official 324:406fd2029f23 755 #define BS_DMA_ERQ_ERQ1 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ1. */
mbed_official 324:406fd2029f23 756
mbed_official 324:406fd2029f23 757 /*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
mbed_official 324:406fd2029f23 758 #define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
mbed_official 324:406fd2029f23 759
mbed_official 324:406fd2029f23 760 /*! @brief Format value for bitfield DMA_ERQ_ERQ1. */
mbed_official 324:406fd2029f23 761 #define BF_DMA_ERQ_ERQ1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1)
mbed_official 324:406fd2029f23 762
mbed_official 324:406fd2029f23 763 /*! @brief Set the ERQ1 field to a new value. */
mbed_official 324:406fd2029f23 764 #define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
mbed_official 324:406fd2029f23 765 /*@}*/
mbed_official 324:406fd2029f23 766
mbed_official 324:406fd2029f23 767 /*!
mbed_official 324:406fd2029f23 768 * @name Register DMA_ERQ, field ERQ2[2] (RW)
mbed_official 324:406fd2029f23 769 *
mbed_official 324:406fd2029f23 770 * Values:
mbed_official 324:406fd2029f23 771 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 772 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 773 */
mbed_official 324:406fd2029f23 774 /*@{*/
mbed_official 324:406fd2029f23 775 #define BP_DMA_ERQ_ERQ2 (2U) /*!< Bit position for DMA_ERQ_ERQ2. */
mbed_official 324:406fd2029f23 776 #define BM_DMA_ERQ_ERQ2 (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */
mbed_official 324:406fd2029f23 777 #define BS_DMA_ERQ_ERQ2 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ2. */
mbed_official 324:406fd2029f23 778
mbed_official 324:406fd2029f23 779 /*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
mbed_official 324:406fd2029f23 780 #define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
mbed_official 324:406fd2029f23 781
mbed_official 324:406fd2029f23 782 /*! @brief Format value for bitfield DMA_ERQ_ERQ2. */
mbed_official 324:406fd2029f23 783 #define BF_DMA_ERQ_ERQ2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2)
mbed_official 324:406fd2029f23 784
mbed_official 324:406fd2029f23 785 /*! @brief Set the ERQ2 field to a new value. */
mbed_official 324:406fd2029f23 786 #define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
mbed_official 324:406fd2029f23 787 /*@}*/
mbed_official 324:406fd2029f23 788
mbed_official 324:406fd2029f23 789 /*!
mbed_official 324:406fd2029f23 790 * @name Register DMA_ERQ, field ERQ3[3] (RW)
mbed_official 324:406fd2029f23 791 *
mbed_official 324:406fd2029f23 792 * Values:
mbed_official 324:406fd2029f23 793 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 794 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 795 */
mbed_official 324:406fd2029f23 796 /*@{*/
mbed_official 324:406fd2029f23 797 #define BP_DMA_ERQ_ERQ3 (3U) /*!< Bit position for DMA_ERQ_ERQ3. */
mbed_official 324:406fd2029f23 798 #define BM_DMA_ERQ_ERQ3 (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */
mbed_official 324:406fd2029f23 799 #define BS_DMA_ERQ_ERQ3 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ3. */
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 /*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
mbed_official 324:406fd2029f23 802 #define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
mbed_official 324:406fd2029f23 803
mbed_official 324:406fd2029f23 804 /*! @brief Format value for bitfield DMA_ERQ_ERQ3. */
mbed_official 324:406fd2029f23 805 #define BF_DMA_ERQ_ERQ3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3)
mbed_official 324:406fd2029f23 806
mbed_official 324:406fd2029f23 807 /*! @brief Set the ERQ3 field to a new value. */
mbed_official 324:406fd2029f23 808 #define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
mbed_official 324:406fd2029f23 809 /*@}*/
mbed_official 324:406fd2029f23 810
mbed_official 324:406fd2029f23 811 /*!
mbed_official 324:406fd2029f23 812 * @name Register DMA_ERQ, field ERQ4[4] (RW)
mbed_official 324:406fd2029f23 813 *
mbed_official 324:406fd2029f23 814 * Values:
mbed_official 324:406fd2029f23 815 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 816 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 817 */
mbed_official 324:406fd2029f23 818 /*@{*/
mbed_official 324:406fd2029f23 819 #define BP_DMA_ERQ_ERQ4 (4U) /*!< Bit position for DMA_ERQ_ERQ4. */
mbed_official 324:406fd2029f23 820 #define BM_DMA_ERQ_ERQ4 (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */
mbed_official 324:406fd2029f23 821 #define BS_DMA_ERQ_ERQ4 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ4. */
mbed_official 324:406fd2029f23 822
mbed_official 324:406fd2029f23 823 /*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
mbed_official 324:406fd2029f23 824 #define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
mbed_official 324:406fd2029f23 825
mbed_official 324:406fd2029f23 826 /*! @brief Format value for bitfield DMA_ERQ_ERQ4. */
mbed_official 324:406fd2029f23 827 #define BF_DMA_ERQ_ERQ4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4)
mbed_official 324:406fd2029f23 828
mbed_official 324:406fd2029f23 829 /*! @brief Set the ERQ4 field to a new value. */
mbed_official 324:406fd2029f23 830 #define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
mbed_official 324:406fd2029f23 831 /*@}*/
mbed_official 324:406fd2029f23 832
mbed_official 324:406fd2029f23 833 /*!
mbed_official 324:406fd2029f23 834 * @name Register DMA_ERQ, field ERQ5[5] (RW)
mbed_official 324:406fd2029f23 835 *
mbed_official 324:406fd2029f23 836 * Values:
mbed_official 324:406fd2029f23 837 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 838 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 839 */
mbed_official 324:406fd2029f23 840 /*@{*/
mbed_official 324:406fd2029f23 841 #define BP_DMA_ERQ_ERQ5 (5U) /*!< Bit position for DMA_ERQ_ERQ5. */
mbed_official 324:406fd2029f23 842 #define BM_DMA_ERQ_ERQ5 (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */
mbed_official 324:406fd2029f23 843 #define BS_DMA_ERQ_ERQ5 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ5. */
mbed_official 324:406fd2029f23 844
mbed_official 324:406fd2029f23 845 /*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
mbed_official 324:406fd2029f23 846 #define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
mbed_official 324:406fd2029f23 847
mbed_official 324:406fd2029f23 848 /*! @brief Format value for bitfield DMA_ERQ_ERQ5. */
mbed_official 324:406fd2029f23 849 #define BF_DMA_ERQ_ERQ5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5)
mbed_official 324:406fd2029f23 850
mbed_official 324:406fd2029f23 851 /*! @brief Set the ERQ5 field to a new value. */
mbed_official 324:406fd2029f23 852 #define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
mbed_official 324:406fd2029f23 853 /*@}*/
mbed_official 324:406fd2029f23 854
mbed_official 324:406fd2029f23 855 /*!
mbed_official 324:406fd2029f23 856 * @name Register DMA_ERQ, field ERQ6[6] (RW)
mbed_official 324:406fd2029f23 857 *
mbed_official 324:406fd2029f23 858 * Values:
mbed_official 324:406fd2029f23 859 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 860 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 861 */
mbed_official 324:406fd2029f23 862 /*@{*/
mbed_official 324:406fd2029f23 863 #define BP_DMA_ERQ_ERQ6 (6U) /*!< Bit position for DMA_ERQ_ERQ6. */
mbed_official 324:406fd2029f23 864 #define BM_DMA_ERQ_ERQ6 (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */
mbed_official 324:406fd2029f23 865 #define BS_DMA_ERQ_ERQ6 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ6. */
mbed_official 324:406fd2029f23 866
mbed_official 324:406fd2029f23 867 /*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
mbed_official 324:406fd2029f23 868 #define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
mbed_official 324:406fd2029f23 869
mbed_official 324:406fd2029f23 870 /*! @brief Format value for bitfield DMA_ERQ_ERQ6. */
mbed_official 324:406fd2029f23 871 #define BF_DMA_ERQ_ERQ6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6)
mbed_official 324:406fd2029f23 872
mbed_official 324:406fd2029f23 873 /*! @brief Set the ERQ6 field to a new value. */
mbed_official 324:406fd2029f23 874 #define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
mbed_official 324:406fd2029f23 875 /*@}*/
mbed_official 324:406fd2029f23 876
mbed_official 324:406fd2029f23 877 /*!
mbed_official 324:406fd2029f23 878 * @name Register DMA_ERQ, field ERQ7[7] (RW)
mbed_official 324:406fd2029f23 879 *
mbed_official 324:406fd2029f23 880 * Values:
mbed_official 324:406fd2029f23 881 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 882 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 883 */
mbed_official 324:406fd2029f23 884 /*@{*/
mbed_official 324:406fd2029f23 885 #define BP_DMA_ERQ_ERQ7 (7U) /*!< Bit position for DMA_ERQ_ERQ7. */
mbed_official 324:406fd2029f23 886 #define BM_DMA_ERQ_ERQ7 (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */
mbed_official 324:406fd2029f23 887 #define BS_DMA_ERQ_ERQ7 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ7. */
mbed_official 324:406fd2029f23 888
mbed_official 324:406fd2029f23 889 /*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
mbed_official 324:406fd2029f23 890 #define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
mbed_official 324:406fd2029f23 891
mbed_official 324:406fd2029f23 892 /*! @brief Format value for bitfield DMA_ERQ_ERQ7. */
mbed_official 324:406fd2029f23 893 #define BF_DMA_ERQ_ERQ7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7)
mbed_official 324:406fd2029f23 894
mbed_official 324:406fd2029f23 895 /*! @brief Set the ERQ7 field to a new value. */
mbed_official 324:406fd2029f23 896 #define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
mbed_official 324:406fd2029f23 897 /*@}*/
mbed_official 324:406fd2029f23 898
mbed_official 324:406fd2029f23 899 /*!
mbed_official 324:406fd2029f23 900 * @name Register DMA_ERQ, field ERQ8[8] (RW)
mbed_official 324:406fd2029f23 901 *
mbed_official 324:406fd2029f23 902 * Values:
mbed_official 324:406fd2029f23 903 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 904 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 905 */
mbed_official 324:406fd2029f23 906 /*@{*/
mbed_official 324:406fd2029f23 907 #define BP_DMA_ERQ_ERQ8 (8U) /*!< Bit position for DMA_ERQ_ERQ8. */
mbed_official 324:406fd2029f23 908 #define BM_DMA_ERQ_ERQ8 (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */
mbed_official 324:406fd2029f23 909 #define BS_DMA_ERQ_ERQ8 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ8. */
mbed_official 324:406fd2029f23 910
mbed_official 324:406fd2029f23 911 /*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
mbed_official 324:406fd2029f23 912 #define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
mbed_official 324:406fd2029f23 913
mbed_official 324:406fd2029f23 914 /*! @brief Format value for bitfield DMA_ERQ_ERQ8. */
mbed_official 324:406fd2029f23 915 #define BF_DMA_ERQ_ERQ8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8)
mbed_official 324:406fd2029f23 916
mbed_official 324:406fd2029f23 917 /*! @brief Set the ERQ8 field to a new value. */
mbed_official 324:406fd2029f23 918 #define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
mbed_official 324:406fd2029f23 919 /*@}*/
mbed_official 324:406fd2029f23 920
mbed_official 324:406fd2029f23 921 /*!
mbed_official 324:406fd2029f23 922 * @name Register DMA_ERQ, field ERQ9[9] (RW)
mbed_official 324:406fd2029f23 923 *
mbed_official 324:406fd2029f23 924 * Values:
mbed_official 324:406fd2029f23 925 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 926 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 927 */
mbed_official 324:406fd2029f23 928 /*@{*/
mbed_official 324:406fd2029f23 929 #define BP_DMA_ERQ_ERQ9 (9U) /*!< Bit position for DMA_ERQ_ERQ9. */
mbed_official 324:406fd2029f23 930 #define BM_DMA_ERQ_ERQ9 (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */
mbed_official 324:406fd2029f23 931 #define BS_DMA_ERQ_ERQ9 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ9. */
mbed_official 324:406fd2029f23 932
mbed_official 324:406fd2029f23 933 /*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
mbed_official 324:406fd2029f23 934 #define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
mbed_official 324:406fd2029f23 935
mbed_official 324:406fd2029f23 936 /*! @brief Format value for bitfield DMA_ERQ_ERQ9. */
mbed_official 324:406fd2029f23 937 #define BF_DMA_ERQ_ERQ9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9)
mbed_official 324:406fd2029f23 938
mbed_official 324:406fd2029f23 939 /*! @brief Set the ERQ9 field to a new value. */
mbed_official 324:406fd2029f23 940 #define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
mbed_official 324:406fd2029f23 941 /*@}*/
mbed_official 324:406fd2029f23 942
mbed_official 324:406fd2029f23 943 /*!
mbed_official 324:406fd2029f23 944 * @name Register DMA_ERQ, field ERQ10[10] (RW)
mbed_official 324:406fd2029f23 945 *
mbed_official 324:406fd2029f23 946 * Values:
mbed_official 324:406fd2029f23 947 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 948 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 949 */
mbed_official 324:406fd2029f23 950 /*@{*/
mbed_official 324:406fd2029f23 951 #define BP_DMA_ERQ_ERQ10 (10U) /*!< Bit position for DMA_ERQ_ERQ10. */
mbed_official 324:406fd2029f23 952 #define BM_DMA_ERQ_ERQ10 (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */
mbed_official 324:406fd2029f23 953 #define BS_DMA_ERQ_ERQ10 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ10. */
mbed_official 324:406fd2029f23 954
mbed_official 324:406fd2029f23 955 /*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
mbed_official 324:406fd2029f23 956 #define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
mbed_official 324:406fd2029f23 957
mbed_official 324:406fd2029f23 958 /*! @brief Format value for bitfield DMA_ERQ_ERQ10. */
mbed_official 324:406fd2029f23 959 #define BF_DMA_ERQ_ERQ10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10)
mbed_official 324:406fd2029f23 960
mbed_official 324:406fd2029f23 961 /*! @brief Set the ERQ10 field to a new value. */
mbed_official 324:406fd2029f23 962 #define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
mbed_official 324:406fd2029f23 963 /*@}*/
mbed_official 324:406fd2029f23 964
mbed_official 324:406fd2029f23 965 /*!
mbed_official 324:406fd2029f23 966 * @name Register DMA_ERQ, field ERQ11[11] (RW)
mbed_official 324:406fd2029f23 967 *
mbed_official 324:406fd2029f23 968 * Values:
mbed_official 324:406fd2029f23 969 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 970 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 971 */
mbed_official 324:406fd2029f23 972 /*@{*/
mbed_official 324:406fd2029f23 973 #define BP_DMA_ERQ_ERQ11 (11U) /*!< Bit position for DMA_ERQ_ERQ11. */
mbed_official 324:406fd2029f23 974 #define BM_DMA_ERQ_ERQ11 (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */
mbed_official 324:406fd2029f23 975 #define BS_DMA_ERQ_ERQ11 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ11. */
mbed_official 324:406fd2029f23 976
mbed_official 324:406fd2029f23 977 /*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
mbed_official 324:406fd2029f23 978 #define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
mbed_official 324:406fd2029f23 979
mbed_official 324:406fd2029f23 980 /*! @brief Format value for bitfield DMA_ERQ_ERQ11. */
mbed_official 324:406fd2029f23 981 #define BF_DMA_ERQ_ERQ11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11)
mbed_official 324:406fd2029f23 982
mbed_official 324:406fd2029f23 983 /*! @brief Set the ERQ11 field to a new value. */
mbed_official 324:406fd2029f23 984 #define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
mbed_official 324:406fd2029f23 985 /*@}*/
mbed_official 324:406fd2029f23 986
mbed_official 324:406fd2029f23 987 /*!
mbed_official 324:406fd2029f23 988 * @name Register DMA_ERQ, field ERQ12[12] (RW)
mbed_official 324:406fd2029f23 989 *
mbed_official 324:406fd2029f23 990 * Values:
mbed_official 324:406fd2029f23 991 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 992 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 993 */
mbed_official 324:406fd2029f23 994 /*@{*/
mbed_official 324:406fd2029f23 995 #define BP_DMA_ERQ_ERQ12 (12U) /*!< Bit position for DMA_ERQ_ERQ12. */
mbed_official 324:406fd2029f23 996 #define BM_DMA_ERQ_ERQ12 (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */
mbed_official 324:406fd2029f23 997 #define BS_DMA_ERQ_ERQ12 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ12. */
mbed_official 324:406fd2029f23 998
mbed_official 324:406fd2029f23 999 /*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
mbed_official 324:406fd2029f23 1000 #define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
mbed_official 324:406fd2029f23 1001
mbed_official 324:406fd2029f23 1002 /*! @brief Format value for bitfield DMA_ERQ_ERQ12. */
mbed_official 324:406fd2029f23 1003 #define BF_DMA_ERQ_ERQ12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12)
mbed_official 324:406fd2029f23 1004
mbed_official 324:406fd2029f23 1005 /*! @brief Set the ERQ12 field to a new value. */
mbed_official 324:406fd2029f23 1006 #define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
mbed_official 324:406fd2029f23 1007 /*@}*/
mbed_official 324:406fd2029f23 1008
mbed_official 324:406fd2029f23 1009 /*!
mbed_official 324:406fd2029f23 1010 * @name Register DMA_ERQ, field ERQ13[13] (RW)
mbed_official 324:406fd2029f23 1011 *
mbed_official 324:406fd2029f23 1012 * Values:
mbed_official 324:406fd2029f23 1013 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 1014 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 1015 */
mbed_official 324:406fd2029f23 1016 /*@{*/
mbed_official 324:406fd2029f23 1017 #define BP_DMA_ERQ_ERQ13 (13U) /*!< Bit position for DMA_ERQ_ERQ13. */
mbed_official 324:406fd2029f23 1018 #define BM_DMA_ERQ_ERQ13 (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */
mbed_official 324:406fd2029f23 1019 #define BS_DMA_ERQ_ERQ13 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ13. */
mbed_official 324:406fd2029f23 1020
mbed_official 324:406fd2029f23 1021 /*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
mbed_official 324:406fd2029f23 1022 #define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
mbed_official 324:406fd2029f23 1023
mbed_official 324:406fd2029f23 1024 /*! @brief Format value for bitfield DMA_ERQ_ERQ13. */
mbed_official 324:406fd2029f23 1025 #define BF_DMA_ERQ_ERQ13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13)
mbed_official 324:406fd2029f23 1026
mbed_official 324:406fd2029f23 1027 /*! @brief Set the ERQ13 field to a new value. */
mbed_official 324:406fd2029f23 1028 #define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
mbed_official 324:406fd2029f23 1029 /*@}*/
mbed_official 324:406fd2029f23 1030
mbed_official 324:406fd2029f23 1031 /*!
mbed_official 324:406fd2029f23 1032 * @name Register DMA_ERQ, field ERQ14[14] (RW)
mbed_official 324:406fd2029f23 1033 *
mbed_official 324:406fd2029f23 1034 * Values:
mbed_official 324:406fd2029f23 1035 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 1036 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 1037 */
mbed_official 324:406fd2029f23 1038 /*@{*/
mbed_official 324:406fd2029f23 1039 #define BP_DMA_ERQ_ERQ14 (14U) /*!< Bit position for DMA_ERQ_ERQ14. */
mbed_official 324:406fd2029f23 1040 #define BM_DMA_ERQ_ERQ14 (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */
mbed_official 324:406fd2029f23 1041 #define BS_DMA_ERQ_ERQ14 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ14. */
mbed_official 324:406fd2029f23 1042
mbed_official 324:406fd2029f23 1043 /*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
mbed_official 324:406fd2029f23 1044 #define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
mbed_official 324:406fd2029f23 1045
mbed_official 324:406fd2029f23 1046 /*! @brief Format value for bitfield DMA_ERQ_ERQ14. */
mbed_official 324:406fd2029f23 1047 #define BF_DMA_ERQ_ERQ14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14)
mbed_official 324:406fd2029f23 1048
mbed_official 324:406fd2029f23 1049 /*! @brief Set the ERQ14 field to a new value. */
mbed_official 324:406fd2029f23 1050 #define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
mbed_official 324:406fd2029f23 1051 /*@}*/
mbed_official 324:406fd2029f23 1052
mbed_official 324:406fd2029f23 1053 /*!
mbed_official 324:406fd2029f23 1054 * @name Register DMA_ERQ, field ERQ15[15] (RW)
mbed_official 324:406fd2029f23 1055 *
mbed_official 324:406fd2029f23 1056 * Values:
mbed_official 324:406fd2029f23 1057 * - 0 - The DMA request signal for the corresponding channel is disabled
mbed_official 324:406fd2029f23 1058 * - 1 - The DMA request signal for the corresponding channel is enabled
mbed_official 324:406fd2029f23 1059 */
mbed_official 324:406fd2029f23 1060 /*@{*/
mbed_official 324:406fd2029f23 1061 #define BP_DMA_ERQ_ERQ15 (15U) /*!< Bit position for DMA_ERQ_ERQ15. */
mbed_official 324:406fd2029f23 1062 #define BM_DMA_ERQ_ERQ15 (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */
mbed_official 324:406fd2029f23 1063 #define BS_DMA_ERQ_ERQ15 (1U) /*!< Bit field size in bits for DMA_ERQ_ERQ15. */
mbed_official 324:406fd2029f23 1064
mbed_official 324:406fd2029f23 1065 /*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
mbed_official 324:406fd2029f23 1066 #define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
mbed_official 324:406fd2029f23 1067
mbed_official 324:406fd2029f23 1068 /*! @brief Format value for bitfield DMA_ERQ_ERQ15. */
mbed_official 324:406fd2029f23 1069 #define BF_DMA_ERQ_ERQ15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15)
mbed_official 324:406fd2029f23 1070
mbed_official 324:406fd2029f23 1071 /*! @brief Set the ERQ15 field to a new value. */
mbed_official 324:406fd2029f23 1072 #define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
mbed_official 324:406fd2029f23 1073 /*@}*/
mbed_official 324:406fd2029f23 1074
mbed_official 324:406fd2029f23 1075 /*******************************************************************************
mbed_official 324:406fd2029f23 1076 * HW_DMA_EEI - Enable Error Interrupt Register
mbed_official 324:406fd2029f23 1077 ******************************************************************************/
mbed_official 324:406fd2029f23 1078
mbed_official 324:406fd2029f23 1079 /*!
mbed_official 324:406fd2029f23 1080 * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
mbed_official 324:406fd2029f23 1081 *
mbed_official 324:406fd2029f23 1082 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1083 *
mbed_official 324:406fd2029f23 1084 * The EEI register provides a bit map for the 16 channels to enable the error
mbed_official 324:406fd2029f23 1085 * interrupt signal for each channel. The state of any given channel's error
mbed_official 324:406fd2029f23 1086 * interrupt enable is directly affected by writes to this register; it is also
mbed_official 324:406fd2029f23 1087 * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
mbed_official 324:406fd2029f23 1088 * interrupt enable for a single channel can easily be modified without the need to
mbed_official 324:406fd2029f23 1089 * perform a read-modify-write sequence to the EEI register. The DMA error
mbed_official 324:406fd2029f23 1090 * indicator and the error interrupt enable flag must be asserted before an error
mbed_official 324:406fd2029f23 1091 * interrupt request for a given channel is asserted to the interrupt controller.
mbed_official 324:406fd2029f23 1092 */
mbed_official 324:406fd2029f23 1093 typedef union _hw_dma_eei
mbed_official 324:406fd2029f23 1094 {
mbed_official 324:406fd2029f23 1095 uint32_t U;
mbed_official 324:406fd2029f23 1096 struct _hw_dma_eei_bitfields
mbed_official 324:406fd2029f23 1097 {
mbed_official 324:406fd2029f23 1098 uint32_t EEI0 : 1; /*!< [0] Enable Error Interrupt 0 */
mbed_official 324:406fd2029f23 1099 uint32_t EEI1 : 1; /*!< [1] Enable Error Interrupt 1 */
mbed_official 324:406fd2029f23 1100 uint32_t EEI2 : 1; /*!< [2] Enable Error Interrupt 2 */
mbed_official 324:406fd2029f23 1101 uint32_t EEI3 : 1; /*!< [3] Enable Error Interrupt 3 */
mbed_official 324:406fd2029f23 1102 uint32_t EEI4 : 1; /*!< [4] Enable Error Interrupt 4 */
mbed_official 324:406fd2029f23 1103 uint32_t EEI5 : 1; /*!< [5] Enable Error Interrupt 5 */
mbed_official 324:406fd2029f23 1104 uint32_t EEI6 : 1; /*!< [6] Enable Error Interrupt 6 */
mbed_official 324:406fd2029f23 1105 uint32_t EEI7 : 1; /*!< [7] Enable Error Interrupt 7 */
mbed_official 324:406fd2029f23 1106 uint32_t EEI8 : 1; /*!< [8] Enable Error Interrupt 8 */
mbed_official 324:406fd2029f23 1107 uint32_t EEI9 : 1; /*!< [9] Enable Error Interrupt 9 */
mbed_official 324:406fd2029f23 1108 uint32_t EEI10 : 1; /*!< [10] Enable Error Interrupt 10 */
mbed_official 324:406fd2029f23 1109 uint32_t EEI11 : 1; /*!< [11] Enable Error Interrupt 11 */
mbed_official 324:406fd2029f23 1110 uint32_t EEI12 : 1; /*!< [12] Enable Error Interrupt 12 */
mbed_official 324:406fd2029f23 1111 uint32_t EEI13 : 1; /*!< [13] Enable Error Interrupt 13 */
mbed_official 324:406fd2029f23 1112 uint32_t EEI14 : 1; /*!< [14] Enable Error Interrupt 14 */
mbed_official 324:406fd2029f23 1113 uint32_t EEI15 : 1; /*!< [15] Enable Error Interrupt 15 */
mbed_official 324:406fd2029f23 1114 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 1115 } B;
mbed_official 324:406fd2029f23 1116 } hw_dma_eei_t;
mbed_official 324:406fd2029f23 1117
mbed_official 324:406fd2029f23 1118 /*!
mbed_official 324:406fd2029f23 1119 * @name Constants and macros for entire DMA_EEI register
mbed_official 324:406fd2029f23 1120 */
mbed_official 324:406fd2029f23 1121 /*@{*/
mbed_official 324:406fd2029f23 1122 #define HW_DMA_EEI_ADDR(x) ((x) + 0x14U)
mbed_official 324:406fd2029f23 1123
mbed_official 324:406fd2029f23 1124 #define HW_DMA_EEI(x) (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
mbed_official 324:406fd2029f23 1125 #define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
mbed_official 324:406fd2029f23 1126 #define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
mbed_official 324:406fd2029f23 1127 #define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) | (v)))
mbed_official 324:406fd2029f23 1128 #define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1129 #define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1130 /*@}*/
mbed_official 324:406fd2029f23 1131
mbed_official 324:406fd2029f23 1132 /*
mbed_official 324:406fd2029f23 1133 * Constants & macros for individual DMA_EEI bitfields
mbed_official 324:406fd2029f23 1134 */
mbed_official 324:406fd2029f23 1135
mbed_official 324:406fd2029f23 1136 /*!
mbed_official 324:406fd2029f23 1137 * @name Register DMA_EEI, field EEI0[0] (RW)
mbed_official 324:406fd2029f23 1138 *
mbed_official 324:406fd2029f23 1139 * Values:
mbed_official 324:406fd2029f23 1140 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1141 * interrupt
mbed_official 324:406fd2029f23 1142 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1143 * an error interrupt request
mbed_official 324:406fd2029f23 1144 */
mbed_official 324:406fd2029f23 1145 /*@{*/
mbed_official 324:406fd2029f23 1146 #define BP_DMA_EEI_EEI0 (0U) /*!< Bit position for DMA_EEI_EEI0. */
mbed_official 324:406fd2029f23 1147 #define BM_DMA_EEI_EEI0 (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */
mbed_official 324:406fd2029f23 1148 #define BS_DMA_EEI_EEI0 (1U) /*!< Bit field size in bits for DMA_EEI_EEI0. */
mbed_official 324:406fd2029f23 1149
mbed_official 324:406fd2029f23 1150 /*! @brief Read current value of the DMA_EEI_EEI0 field. */
mbed_official 324:406fd2029f23 1151 #define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
mbed_official 324:406fd2029f23 1152
mbed_official 324:406fd2029f23 1153 /*! @brief Format value for bitfield DMA_EEI_EEI0. */
mbed_official 324:406fd2029f23 1154 #define BF_DMA_EEI_EEI0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0)
mbed_official 324:406fd2029f23 1155
mbed_official 324:406fd2029f23 1156 /*! @brief Set the EEI0 field to a new value. */
mbed_official 324:406fd2029f23 1157 #define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
mbed_official 324:406fd2029f23 1158 /*@}*/
mbed_official 324:406fd2029f23 1159
mbed_official 324:406fd2029f23 1160 /*!
mbed_official 324:406fd2029f23 1161 * @name Register DMA_EEI, field EEI1[1] (RW)
mbed_official 324:406fd2029f23 1162 *
mbed_official 324:406fd2029f23 1163 * Values:
mbed_official 324:406fd2029f23 1164 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1165 * interrupt
mbed_official 324:406fd2029f23 1166 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1167 * an error interrupt request
mbed_official 324:406fd2029f23 1168 */
mbed_official 324:406fd2029f23 1169 /*@{*/
mbed_official 324:406fd2029f23 1170 #define BP_DMA_EEI_EEI1 (1U) /*!< Bit position for DMA_EEI_EEI1. */
mbed_official 324:406fd2029f23 1171 #define BM_DMA_EEI_EEI1 (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */
mbed_official 324:406fd2029f23 1172 #define BS_DMA_EEI_EEI1 (1U) /*!< Bit field size in bits for DMA_EEI_EEI1. */
mbed_official 324:406fd2029f23 1173
mbed_official 324:406fd2029f23 1174 /*! @brief Read current value of the DMA_EEI_EEI1 field. */
mbed_official 324:406fd2029f23 1175 #define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
mbed_official 324:406fd2029f23 1176
mbed_official 324:406fd2029f23 1177 /*! @brief Format value for bitfield DMA_EEI_EEI1. */
mbed_official 324:406fd2029f23 1178 #define BF_DMA_EEI_EEI1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1)
mbed_official 324:406fd2029f23 1179
mbed_official 324:406fd2029f23 1180 /*! @brief Set the EEI1 field to a new value. */
mbed_official 324:406fd2029f23 1181 #define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
mbed_official 324:406fd2029f23 1182 /*@}*/
mbed_official 324:406fd2029f23 1183
mbed_official 324:406fd2029f23 1184 /*!
mbed_official 324:406fd2029f23 1185 * @name Register DMA_EEI, field EEI2[2] (RW)
mbed_official 324:406fd2029f23 1186 *
mbed_official 324:406fd2029f23 1187 * Values:
mbed_official 324:406fd2029f23 1188 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1189 * interrupt
mbed_official 324:406fd2029f23 1190 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1191 * an error interrupt request
mbed_official 324:406fd2029f23 1192 */
mbed_official 324:406fd2029f23 1193 /*@{*/
mbed_official 324:406fd2029f23 1194 #define BP_DMA_EEI_EEI2 (2U) /*!< Bit position for DMA_EEI_EEI2. */
mbed_official 324:406fd2029f23 1195 #define BM_DMA_EEI_EEI2 (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */
mbed_official 324:406fd2029f23 1196 #define BS_DMA_EEI_EEI2 (1U) /*!< Bit field size in bits for DMA_EEI_EEI2. */
mbed_official 324:406fd2029f23 1197
mbed_official 324:406fd2029f23 1198 /*! @brief Read current value of the DMA_EEI_EEI2 field. */
mbed_official 324:406fd2029f23 1199 #define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
mbed_official 324:406fd2029f23 1200
mbed_official 324:406fd2029f23 1201 /*! @brief Format value for bitfield DMA_EEI_EEI2. */
mbed_official 324:406fd2029f23 1202 #define BF_DMA_EEI_EEI2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2)
mbed_official 324:406fd2029f23 1203
mbed_official 324:406fd2029f23 1204 /*! @brief Set the EEI2 field to a new value. */
mbed_official 324:406fd2029f23 1205 #define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
mbed_official 324:406fd2029f23 1206 /*@}*/
mbed_official 324:406fd2029f23 1207
mbed_official 324:406fd2029f23 1208 /*!
mbed_official 324:406fd2029f23 1209 * @name Register DMA_EEI, field EEI3[3] (RW)
mbed_official 324:406fd2029f23 1210 *
mbed_official 324:406fd2029f23 1211 * Values:
mbed_official 324:406fd2029f23 1212 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1213 * interrupt
mbed_official 324:406fd2029f23 1214 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1215 * an error interrupt request
mbed_official 324:406fd2029f23 1216 */
mbed_official 324:406fd2029f23 1217 /*@{*/
mbed_official 324:406fd2029f23 1218 #define BP_DMA_EEI_EEI3 (3U) /*!< Bit position for DMA_EEI_EEI3. */
mbed_official 324:406fd2029f23 1219 #define BM_DMA_EEI_EEI3 (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */
mbed_official 324:406fd2029f23 1220 #define BS_DMA_EEI_EEI3 (1U) /*!< Bit field size in bits for DMA_EEI_EEI3. */
mbed_official 324:406fd2029f23 1221
mbed_official 324:406fd2029f23 1222 /*! @brief Read current value of the DMA_EEI_EEI3 field. */
mbed_official 324:406fd2029f23 1223 #define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
mbed_official 324:406fd2029f23 1224
mbed_official 324:406fd2029f23 1225 /*! @brief Format value for bitfield DMA_EEI_EEI3. */
mbed_official 324:406fd2029f23 1226 #define BF_DMA_EEI_EEI3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3)
mbed_official 324:406fd2029f23 1227
mbed_official 324:406fd2029f23 1228 /*! @brief Set the EEI3 field to a new value. */
mbed_official 324:406fd2029f23 1229 #define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
mbed_official 324:406fd2029f23 1230 /*@}*/
mbed_official 324:406fd2029f23 1231
mbed_official 324:406fd2029f23 1232 /*!
mbed_official 324:406fd2029f23 1233 * @name Register DMA_EEI, field EEI4[4] (RW)
mbed_official 324:406fd2029f23 1234 *
mbed_official 324:406fd2029f23 1235 * Values:
mbed_official 324:406fd2029f23 1236 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1237 * interrupt
mbed_official 324:406fd2029f23 1238 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1239 * an error interrupt request
mbed_official 324:406fd2029f23 1240 */
mbed_official 324:406fd2029f23 1241 /*@{*/
mbed_official 324:406fd2029f23 1242 #define BP_DMA_EEI_EEI4 (4U) /*!< Bit position for DMA_EEI_EEI4. */
mbed_official 324:406fd2029f23 1243 #define BM_DMA_EEI_EEI4 (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */
mbed_official 324:406fd2029f23 1244 #define BS_DMA_EEI_EEI4 (1U) /*!< Bit field size in bits for DMA_EEI_EEI4. */
mbed_official 324:406fd2029f23 1245
mbed_official 324:406fd2029f23 1246 /*! @brief Read current value of the DMA_EEI_EEI4 field. */
mbed_official 324:406fd2029f23 1247 #define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
mbed_official 324:406fd2029f23 1248
mbed_official 324:406fd2029f23 1249 /*! @brief Format value for bitfield DMA_EEI_EEI4. */
mbed_official 324:406fd2029f23 1250 #define BF_DMA_EEI_EEI4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4)
mbed_official 324:406fd2029f23 1251
mbed_official 324:406fd2029f23 1252 /*! @brief Set the EEI4 field to a new value. */
mbed_official 324:406fd2029f23 1253 #define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
mbed_official 324:406fd2029f23 1254 /*@}*/
mbed_official 324:406fd2029f23 1255
mbed_official 324:406fd2029f23 1256 /*!
mbed_official 324:406fd2029f23 1257 * @name Register DMA_EEI, field EEI5[5] (RW)
mbed_official 324:406fd2029f23 1258 *
mbed_official 324:406fd2029f23 1259 * Values:
mbed_official 324:406fd2029f23 1260 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1261 * interrupt
mbed_official 324:406fd2029f23 1262 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1263 * an error interrupt request
mbed_official 324:406fd2029f23 1264 */
mbed_official 324:406fd2029f23 1265 /*@{*/
mbed_official 324:406fd2029f23 1266 #define BP_DMA_EEI_EEI5 (5U) /*!< Bit position for DMA_EEI_EEI5. */
mbed_official 324:406fd2029f23 1267 #define BM_DMA_EEI_EEI5 (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */
mbed_official 324:406fd2029f23 1268 #define BS_DMA_EEI_EEI5 (1U) /*!< Bit field size in bits for DMA_EEI_EEI5. */
mbed_official 324:406fd2029f23 1269
mbed_official 324:406fd2029f23 1270 /*! @brief Read current value of the DMA_EEI_EEI5 field. */
mbed_official 324:406fd2029f23 1271 #define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
mbed_official 324:406fd2029f23 1272
mbed_official 324:406fd2029f23 1273 /*! @brief Format value for bitfield DMA_EEI_EEI5. */
mbed_official 324:406fd2029f23 1274 #define BF_DMA_EEI_EEI5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5)
mbed_official 324:406fd2029f23 1275
mbed_official 324:406fd2029f23 1276 /*! @brief Set the EEI5 field to a new value. */
mbed_official 324:406fd2029f23 1277 #define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
mbed_official 324:406fd2029f23 1278 /*@}*/
mbed_official 324:406fd2029f23 1279
mbed_official 324:406fd2029f23 1280 /*!
mbed_official 324:406fd2029f23 1281 * @name Register DMA_EEI, field EEI6[6] (RW)
mbed_official 324:406fd2029f23 1282 *
mbed_official 324:406fd2029f23 1283 * Values:
mbed_official 324:406fd2029f23 1284 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1285 * interrupt
mbed_official 324:406fd2029f23 1286 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1287 * an error interrupt request
mbed_official 324:406fd2029f23 1288 */
mbed_official 324:406fd2029f23 1289 /*@{*/
mbed_official 324:406fd2029f23 1290 #define BP_DMA_EEI_EEI6 (6U) /*!< Bit position for DMA_EEI_EEI6. */
mbed_official 324:406fd2029f23 1291 #define BM_DMA_EEI_EEI6 (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */
mbed_official 324:406fd2029f23 1292 #define BS_DMA_EEI_EEI6 (1U) /*!< Bit field size in bits for DMA_EEI_EEI6. */
mbed_official 324:406fd2029f23 1293
mbed_official 324:406fd2029f23 1294 /*! @brief Read current value of the DMA_EEI_EEI6 field. */
mbed_official 324:406fd2029f23 1295 #define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
mbed_official 324:406fd2029f23 1296
mbed_official 324:406fd2029f23 1297 /*! @brief Format value for bitfield DMA_EEI_EEI6. */
mbed_official 324:406fd2029f23 1298 #define BF_DMA_EEI_EEI6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6)
mbed_official 324:406fd2029f23 1299
mbed_official 324:406fd2029f23 1300 /*! @brief Set the EEI6 field to a new value. */
mbed_official 324:406fd2029f23 1301 #define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
mbed_official 324:406fd2029f23 1302 /*@}*/
mbed_official 324:406fd2029f23 1303
mbed_official 324:406fd2029f23 1304 /*!
mbed_official 324:406fd2029f23 1305 * @name Register DMA_EEI, field EEI7[7] (RW)
mbed_official 324:406fd2029f23 1306 *
mbed_official 324:406fd2029f23 1307 * Values:
mbed_official 324:406fd2029f23 1308 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1309 * interrupt
mbed_official 324:406fd2029f23 1310 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1311 * an error interrupt request
mbed_official 324:406fd2029f23 1312 */
mbed_official 324:406fd2029f23 1313 /*@{*/
mbed_official 324:406fd2029f23 1314 #define BP_DMA_EEI_EEI7 (7U) /*!< Bit position for DMA_EEI_EEI7. */
mbed_official 324:406fd2029f23 1315 #define BM_DMA_EEI_EEI7 (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */
mbed_official 324:406fd2029f23 1316 #define BS_DMA_EEI_EEI7 (1U) /*!< Bit field size in bits for DMA_EEI_EEI7. */
mbed_official 324:406fd2029f23 1317
mbed_official 324:406fd2029f23 1318 /*! @brief Read current value of the DMA_EEI_EEI7 field. */
mbed_official 324:406fd2029f23 1319 #define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
mbed_official 324:406fd2029f23 1320
mbed_official 324:406fd2029f23 1321 /*! @brief Format value for bitfield DMA_EEI_EEI7. */
mbed_official 324:406fd2029f23 1322 #define BF_DMA_EEI_EEI7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7)
mbed_official 324:406fd2029f23 1323
mbed_official 324:406fd2029f23 1324 /*! @brief Set the EEI7 field to a new value. */
mbed_official 324:406fd2029f23 1325 #define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
mbed_official 324:406fd2029f23 1326 /*@}*/
mbed_official 324:406fd2029f23 1327
mbed_official 324:406fd2029f23 1328 /*!
mbed_official 324:406fd2029f23 1329 * @name Register DMA_EEI, field EEI8[8] (RW)
mbed_official 324:406fd2029f23 1330 *
mbed_official 324:406fd2029f23 1331 * Values:
mbed_official 324:406fd2029f23 1332 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1333 * interrupt
mbed_official 324:406fd2029f23 1334 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1335 * an error interrupt request
mbed_official 324:406fd2029f23 1336 */
mbed_official 324:406fd2029f23 1337 /*@{*/
mbed_official 324:406fd2029f23 1338 #define BP_DMA_EEI_EEI8 (8U) /*!< Bit position for DMA_EEI_EEI8. */
mbed_official 324:406fd2029f23 1339 #define BM_DMA_EEI_EEI8 (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */
mbed_official 324:406fd2029f23 1340 #define BS_DMA_EEI_EEI8 (1U) /*!< Bit field size in bits for DMA_EEI_EEI8. */
mbed_official 324:406fd2029f23 1341
mbed_official 324:406fd2029f23 1342 /*! @brief Read current value of the DMA_EEI_EEI8 field. */
mbed_official 324:406fd2029f23 1343 #define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
mbed_official 324:406fd2029f23 1344
mbed_official 324:406fd2029f23 1345 /*! @brief Format value for bitfield DMA_EEI_EEI8. */
mbed_official 324:406fd2029f23 1346 #define BF_DMA_EEI_EEI8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8)
mbed_official 324:406fd2029f23 1347
mbed_official 324:406fd2029f23 1348 /*! @brief Set the EEI8 field to a new value. */
mbed_official 324:406fd2029f23 1349 #define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
mbed_official 324:406fd2029f23 1350 /*@}*/
mbed_official 324:406fd2029f23 1351
mbed_official 324:406fd2029f23 1352 /*!
mbed_official 324:406fd2029f23 1353 * @name Register DMA_EEI, field EEI9[9] (RW)
mbed_official 324:406fd2029f23 1354 *
mbed_official 324:406fd2029f23 1355 * Values:
mbed_official 324:406fd2029f23 1356 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1357 * interrupt
mbed_official 324:406fd2029f23 1358 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1359 * an error interrupt request
mbed_official 324:406fd2029f23 1360 */
mbed_official 324:406fd2029f23 1361 /*@{*/
mbed_official 324:406fd2029f23 1362 #define BP_DMA_EEI_EEI9 (9U) /*!< Bit position for DMA_EEI_EEI9. */
mbed_official 324:406fd2029f23 1363 #define BM_DMA_EEI_EEI9 (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */
mbed_official 324:406fd2029f23 1364 #define BS_DMA_EEI_EEI9 (1U) /*!< Bit field size in bits for DMA_EEI_EEI9. */
mbed_official 324:406fd2029f23 1365
mbed_official 324:406fd2029f23 1366 /*! @brief Read current value of the DMA_EEI_EEI9 field. */
mbed_official 324:406fd2029f23 1367 #define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
mbed_official 324:406fd2029f23 1368
mbed_official 324:406fd2029f23 1369 /*! @brief Format value for bitfield DMA_EEI_EEI9. */
mbed_official 324:406fd2029f23 1370 #define BF_DMA_EEI_EEI9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9)
mbed_official 324:406fd2029f23 1371
mbed_official 324:406fd2029f23 1372 /*! @brief Set the EEI9 field to a new value. */
mbed_official 324:406fd2029f23 1373 #define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
mbed_official 324:406fd2029f23 1374 /*@}*/
mbed_official 324:406fd2029f23 1375
mbed_official 324:406fd2029f23 1376 /*!
mbed_official 324:406fd2029f23 1377 * @name Register DMA_EEI, field EEI10[10] (RW)
mbed_official 324:406fd2029f23 1378 *
mbed_official 324:406fd2029f23 1379 * Values:
mbed_official 324:406fd2029f23 1380 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1381 * interrupt
mbed_official 324:406fd2029f23 1382 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1383 * an error interrupt request
mbed_official 324:406fd2029f23 1384 */
mbed_official 324:406fd2029f23 1385 /*@{*/
mbed_official 324:406fd2029f23 1386 #define BP_DMA_EEI_EEI10 (10U) /*!< Bit position for DMA_EEI_EEI10. */
mbed_official 324:406fd2029f23 1387 #define BM_DMA_EEI_EEI10 (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */
mbed_official 324:406fd2029f23 1388 #define BS_DMA_EEI_EEI10 (1U) /*!< Bit field size in bits for DMA_EEI_EEI10. */
mbed_official 324:406fd2029f23 1389
mbed_official 324:406fd2029f23 1390 /*! @brief Read current value of the DMA_EEI_EEI10 field. */
mbed_official 324:406fd2029f23 1391 #define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
mbed_official 324:406fd2029f23 1392
mbed_official 324:406fd2029f23 1393 /*! @brief Format value for bitfield DMA_EEI_EEI10. */
mbed_official 324:406fd2029f23 1394 #define BF_DMA_EEI_EEI10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10)
mbed_official 324:406fd2029f23 1395
mbed_official 324:406fd2029f23 1396 /*! @brief Set the EEI10 field to a new value. */
mbed_official 324:406fd2029f23 1397 #define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
mbed_official 324:406fd2029f23 1398 /*@}*/
mbed_official 324:406fd2029f23 1399
mbed_official 324:406fd2029f23 1400 /*!
mbed_official 324:406fd2029f23 1401 * @name Register DMA_EEI, field EEI11[11] (RW)
mbed_official 324:406fd2029f23 1402 *
mbed_official 324:406fd2029f23 1403 * Values:
mbed_official 324:406fd2029f23 1404 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1405 * interrupt
mbed_official 324:406fd2029f23 1406 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1407 * an error interrupt request
mbed_official 324:406fd2029f23 1408 */
mbed_official 324:406fd2029f23 1409 /*@{*/
mbed_official 324:406fd2029f23 1410 #define BP_DMA_EEI_EEI11 (11U) /*!< Bit position for DMA_EEI_EEI11. */
mbed_official 324:406fd2029f23 1411 #define BM_DMA_EEI_EEI11 (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */
mbed_official 324:406fd2029f23 1412 #define BS_DMA_EEI_EEI11 (1U) /*!< Bit field size in bits for DMA_EEI_EEI11. */
mbed_official 324:406fd2029f23 1413
mbed_official 324:406fd2029f23 1414 /*! @brief Read current value of the DMA_EEI_EEI11 field. */
mbed_official 324:406fd2029f23 1415 #define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
mbed_official 324:406fd2029f23 1416
mbed_official 324:406fd2029f23 1417 /*! @brief Format value for bitfield DMA_EEI_EEI11. */
mbed_official 324:406fd2029f23 1418 #define BF_DMA_EEI_EEI11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11)
mbed_official 324:406fd2029f23 1419
mbed_official 324:406fd2029f23 1420 /*! @brief Set the EEI11 field to a new value. */
mbed_official 324:406fd2029f23 1421 #define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
mbed_official 324:406fd2029f23 1422 /*@}*/
mbed_official 324:406fd2029f23 1423
mbed_official 324:406fd2029f23 1424 /*!
mbed_official 324:406fd2029f23 1425 * @name Register DMA_EEI, field EEI12[12] (RW)
mbed_official 324:406fd2029f23 1426 *
mbed_official 324:406fd2029f23 1427 * Values:
mbed_official 324:406fd2029f23 1428 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1429 * interrupt
mbed_official 324:406fd2029f23 1430 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1431 * an error interrupt request
mbed_official 324:406fd2029f23 1432 */
mbed_official 324:406fd2029f23 1433 /*@{*/
mbed_official 324:406fd2029f23 1434 #define BP_DMA_EEI_EEI12 (12U) /*!< Bit position for DMA_EEI_EEI12. */
mbed_official 324:406fd2029f23 1435 #define BM_DMA_EEI_EEI12 (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */
mbed_official 324:406fd2029f23 1436 #define BS_DMA_EEI_EEI12 (1U) /*!< Bit field size in bits for DMA_EEI_EEI12. */
mbed_official 324:406fd2029f23 1437
mbed_official 324:406fd2029f23 1438 /*! @brief Read current value of the DMA_EEI_EEI12 field. */
mbed_official 324:406fd2029f23 1439 #define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
mbed_official 324:406fd2029f23 1440
mbed_official 324:406fd2029f23 1441 /*! @brief Format value for bitfield DMA_EEI_EEI12. */
mbed_official 324:406fd2029f23 1442 #define BF_DMA_EEI_EEI12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12)
mbed_official 324:406fd2029f23 1443
mbed_official 324:406fd2029f23 1444 /*! @brief Set the EEI12 field to a new value. */
mbed_official 324:406fd2029f23 1445 #define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
mbed_official 324:406fd2029f23 1446 /*@}*/
mbed_official 324:406fd2029f23 1447
mbed_official 324:406fd2029f23 1448 /*!
mbed_official 324:406fd2029f23 1449 * @name Register DMA_EEI, field EEI13[13] (RW)
mbed_official 324:406fd2029f23 1450 *
mbed_official 324:406fd2029f23 1451 * Values:
mbed_official 324:406fd2029f23 1452 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1453 * interrupt
mbed_official 324:406fd2029f23 1454 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1455 * an error interrupt request
mbed_official 324:406fd2029f23 1456 */
mbed_official 324:406fd2029f23 1457 /*@{*/
mbed_official 324:406fd2029f23 1458 #define BP_DMA_EEI_EEI13 (13U) /*!< Bit position for DMA_EEI_EEI13. */
mbed_official 324:406fd2029f23 1459 #define BM_DMA_EEI_EEI13 (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */
mbed_official 324:406fd2029f23 1460 #define BS_DMA_EEI_EEI13 (1U) /*!< Bit field size in bits for DMA_EEI_EEI13. */
mbed_official 324:406fd2029f23 1461
mbed_official 324:406fd2029f23 1462 /*! @brief Read current value of the DMA_EEI_EEI13 field. */
mbed_official 324:406fd2029f23 1463 #define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
mbed_official 324:406fd2029f23 1464
mbed_official 324:406fd2029f23 1465 /*! @brief Format value for bitfield DMA_EEI_EEI13. */
mbed_official 324:406fd2029f23 1466 #define BF_DMA_EEI_EEI13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13)
mbed_official 324:406fd2029f23 1467
mbed_official 324:406fd2029f23 1468 /*! @brief Set the EEI13 field to a new value. */
mbed_official 324:406fd2029f23 1469 #define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
mbed_official 324:406fd2029f23 1470 /*@}*/
mbed_official 324:406fd2029f23 1471
mbed_official 324:406fd2029f23 1472 /*!
mbed_official 324:406fd2029f23 1473 * @name Register DMA_EEI, field EEI14[14] (RW)
mbed_official 324:406fd2029f23 1474 *
mbed_official 324:406fd2029f23 1475 * Values:
mbed_official 324:406fd2029f23 1476 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1477 * interrupt
mbed_official 324:406fd2029f23 1478 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1479 * an error interrupt request
mbed_official 324:406fd2029f23 1480 */
mbed_official 324:406fd2029f23 1481 /*@{*/
mbed_official 324:406fd2029f23 1482 #define BP_DMA_EEI_EEI14 (14U) /*!< Bit position for DMA_EEI_EEI14. */
mbed_official 324:406fd2029f23 1483 #define BM_DMA_EEI_EEI14 (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */
mbed_official 324:406fd2029f23 1484 #define BS_DMA_EEI_EEI14 (1U) /*!< Bit field size in bits for DMA_EEI_EEI14. */
mbed_official 324:406fd2029f23 1485
mbed_official 324:406fd2029f23 1486 /*! @brief Read current value of the DMA_EEI_EEI14 field. */
mbed_official 324:406fd2029f23 1487 #define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
mbed_official 324:406fd2029f23 1488
mbed_official 324:406fd2029f23 1489 /*! @brief Format value for bitfield DMA_EEI_EEI14. */
mbed_official 324:406fd2029f23 1490 #define BF_DMA_EEI_EEI14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14)
mbed_official 324:406fd2029f23 1491
mbed_official 324:406fd2029f23 1492 /*! @brief Set the EEI14 field to a new value. */
mbed_official 324:406fd2029f23 1493 #define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
mbed_official 324:406fd2029f23 1494 /*@}*/
mbed_official 324:406fd2029f23 1495
mbed_official 324:406fd2029f23 1496 /*!
mbed_official 324:406fd2029f23 1497 * @name Register DMA_EEI, field EEI15[15] (RW)
mbed_official 324:406fd2029f23 1498 *
mbed_official 324:406fd2029f23 1499 * Values:
mbed_official 324:406fd2029f23 1500 * - 0 - The error signal for corresponding channel does not generate an error
mbed_official 324:406fd2029f23 1501 * interrupt
mbed_official 324:406fd2029f23 1502 * - 1 - The assertion of the error signal for corresponding channel generates
mbed_official 324:406fd2029f23 1503 * an error interrupt request
mbed_official 324:406fd2029f23 1504 */
mbed_official 324:406fd2029f23 1505 /*@{*/
mbed_official 324:406fd2029f23 1506 #define BP_DMA_EEI_EEI15 (15U) /*!< Bit position for DMA_EEI_EEI15. */
mbed_official 324:406fd2029f23 1507 #define BM_DMA_EEI_EEI15 (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */
mbed_official 324:406fd2029f23 1508 #define BS_DMA_EEI_EEI15 (1U) /*!< Bit field size in bits for DMA_EEI_EEI15. */
mbed_official 324:406fd2029f23 1509
mbed_official 324:406fd2029f23 1510 /*! @brief Read current value of the DMA_EEI_EEI15 field. */
mbed_official 324:406fd2029f23 1511 #define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
mbed_official 324:406fd2029f23 1512
mbed_official 324:406fd2029f23 1513 /*! @brief Format value for bitfield DMA_EEI_EEI15. */
mbed_official 324:406fd2029f23 1514 #define BF_DMA_EEI_EEI15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15)
mbed_official 324:406fd2029f23 1515
mbed_official 324:406fd2029f23 1516 /*! @brief Set the EEI15 field to a new value. */
mbed_official 324:406fd2029f23 1517 #define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
mbed_official 324:406fd2029f23 1518 /*@}*/
mbed_official 324:406fd2029f23 1519
mbed_official 324:406fd2029f23 1520 /*******************************************************************************
mbed_official 324:406fd2029f23 1521 * HW_DMA_CEEI - Clear Enable Error Interrupt Register
mbed_official 324:406fd2029f23 1522 ******************************************************************************/
mbed_official 324:406fd2029f23 1523
mbed_official 324:406fd2029f23 1524 /*!
mbed_official 324:406fd2029f23 1525 * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
mbed_official 324:406fd2029f23 1526 *
mbed_official 324:406fd2029f23 1527 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1528 *
mbed_official 324:406fd2029f23 1529 * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
mbed_official 324:406fd2029f23 1530 * the EEI to disable the error interrupt for a given channel. The data value on a
mbed_official 324:406fd2029f23 1531 * register write causes the corresponding bit in the EEI to be cleared. Setting
mbed_official 324:406fd2029f23 1532 * the CAEE bit provides a global clear function, forcing the EEI contents to be
mbed_official 324:406fd2029f23 1533 * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
mbed_official 324:406fd2029f23 1534 * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
mbed_official 324:406fd2029f23 1535 * Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 1536 */
mbed_official 324:406fd2029f23 1537 typedef union _hw_dma_ceei
mbed_official 324:406fd2029f23 1538 {
mbed_official 324:406fd2029f23 1539 uint8_t U;
mbed_official 324:406fd2029f23 1540 struct _hw_dma_ceei_bitfields
mbed_official 324:406fd2029f23 1541 {
mbed_official 324:406fd2029f23 1542 uint8_t CEEI : 4; /*!< [3:0] Clear Enable Error Interrupt */
mbed_official 324:406fd2029f23 1543 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1544 uint8_t CAEE : 1; /*!< [6] Clear All Enable Error Interrupts */
mbed_official 324:406fd2029f23 1545 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 1546 } B;
mbed_official 324:406fd2029f23 1547 } hw_dma_ceei_t;
mbed_official 324:406fd2029f23 1548
mbed_official 324:406fd2029f23 1549 /*!
mbed_official 324:406fd2029f23 1550 * @name Constants and macros for entire DMA_CEEI register
mbed_official 324:406fd2029f23 1551 */
mbed_official 324:406fd2029f23 1552 /*@{*/
mbed_official 324:406fd2029f23 1553 #define HW_DMA_CEEI_ADDR(x) ((x) + 0x18U)
mbed_official 324:406fd2029f23 1554
mbed_official 324:406fd2029f23 1555 #define HW_DMA_CEEI(x) (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
mbed_official 324:406fd2029f23 1556 #define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
mbed_official 324:406fd2029f23 1557 #define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
mbed_official 324:406fd2029f23 1558 /*@}*/
mbed_official 324:406fd2029f23 1559
mbed_official 324:406fd2029f23 1560 /*
mbed_official 324:406fd2029f23 1561 * Constants & macros for individual DMA_CEEI bitfields
mbed_official 324:406fd2029f23 1562 */
mbed_official 324:406fd2029f23 1563
mbed_official 324:406fd2029f23 1564 /*!
mbed_official 324:406fd2029f23 1565 * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
mbed_official 324:406fd2029f23 1566 *
mbed_official 324:406fd2029f23 1567 * Clears the corresponding bit in EEI
mbed_official 324:406fd2029f23 1568 */
mbed_official 324:406fd2029f23 1569 /*@{*/
mbed_official 324:406fd2029f23 1570 #define BP_DMA_CEEI_CEEI (0U) /*!< Bit position for DMA_CEEI_CEEI. */
mbed_official 324:406fd2029f23 1571 #define BM_DMA_CEEI_CEEI (0x0FU) /*!< Bit mask for DMA_CEEI_CEEI. */
mbed_official 324:406fd2029f23 1572 #define BS_DMA_CEEI_CEEI (4U) /*!< Bit field size in bits for DMA_CEEI_CEEI. */
mbed_official 324:406fd2029f23 1573
mbed_official 324:406fd2029f23 1574 /*! @brief Format value for bitfield DMA_CEEI_CEEI. */
mbed_official 324:406fd2029f23 1575 #define BF_DMA_CEEI_CEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI)
mbed_official 324:406fd2029f23 1576
mbed_official 324:406fd2029f23 1577 /*! @brief Set the CEEI field to a new value. */
mbed_official 324:406fd2029f23 1578 #define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
mbed_official 324:406fd2029f23 1579 /*@}*/
mbed_official 324:406fd2029f23 1580
mbed_official 324:406fd2029f23 1581 /*!
mbed_official 324:406fd2029f23 1582 * @name Register DMA_CEEI, field CAEE[6] (WORZ)
mbed_official 324:406fd2029f23 1583 *
mbed_official 324:406fd2029f23 1584 * Values:
mbed_official 324:406fd2029f23 1585 * - 0 - Clear only the EEI bit specified in the CEEI field
mbed_official 324:406fd2029f23 1586 * - 1 - Clear all bits in EEI
mbed_official 324:406fd2029f23 1587 */
mbed_official 324:406fd2029f23 1588 /*@{*/
mbed_official 324:406fd2029f23 1589 #define BP_DMA_CEEI_CAEE (6U) /*!< Bit position for DMA_CEEI_CAEE. */
mbed_official 324:406fd2029f23 1590 #define BM_DMA_CEEI_CAEE (0x40U) /*!< Bit mask for DMA_CEEI_CAEE. */
mbed_official 324:406fd2029f23 1591 #define BS_DMA_CEEI_CAEE (1U) /*!< Bit field size in bits for DMA_CEEI_CAEE. */
mbed_official 324:406fd2029f23 1592
mbed_official 324:406fd2029f23 1593 /*! @brief Format value for bitfield DMA_CEEI_CAEE. */
mbed_official 324:406fd2029f23 1594 #define BF_DMA_CEEI_CAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE)
mbed_official 324:406fd2029f23 1595
mbed_official 324:406fd2029f23 1596 /*! @brief Set the CAEE field to a new value. */
mbed_official 324:406fd2029f23 1597 #define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
mbed_official 324:406fd2029f23 1598 /*@}*/
mbed_official 324:406fd2029f23 1599
mbed_official 324:406fd2029f23 1600 /*!
mbed_official 324:406fd2029f23 1601 * @name Register DMA_CEEI, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 1602 *
mbed_official 324:406fd2029f23 1603 * Values:
mbed_official 324:406fd2029f23 1604 * - 0 - Normal operation
mbed_official 324:406fd2029f23 1605 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 1606 */
mbed_official 324:406fd2029f23 1607 /*@{*/
mbed_official 324:406fd2029f23 1608 #define BP_DMA_CEEI_NOP (7U) /*!< Bit position for DMA_CEEI_NOP. */
mbed_official 324:406fd2029f23 1609 #define BM_DMA_CEEI_NOP (0x80U) /*!< Bit mask for DMA_CEEI_NOP. */
mbed_official 324:406fd2029f23 1610 #define BS_DMA_CEEI_NOP (1U) /*!< Bit field size in bits for DMA_CEEI_NOP. */
mbed_official 324:406fd2029f23 1611
mbed_official 324:406fd2029f23 1612 /*! @brief Format value for bitfield DMA_CEEI_NOP. */
mbed_official 324:406fd2029f23 1613 #define BF_DMA_CEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP)
mbed_official 324:406fd2029f23 1614
mbed_official 324:406fd2029f23 1615 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 1616 #define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
mbed_official 324:406fd2029f23 1617 /*@}*/
mbed_official 324:406fd2029f23 1618
mbed_official 324:406fd2029f23 1619 /*******************************************************************************
mbed_official 324:406fd2029f23 1620 * HW_DMA_SEEI - Set Enable Error Interrupt Register
mbed_official 324:406fd2029f23 1621 ******************************************************************************/
mbed_official 324:406fd2029f23 1622
mbed_official 324:406fd2029f23 1623 /*!
mbed_official 324:406fd2029f23 1624 * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
mbed_official 324:406fd2029f23 1625 *
mbed_official 324:406fd2029f23 1626 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1627 *
mbed_official 324:406fd2029f23 1628 * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
mbed_official 324:406fd2029f23 1629 * EEI to enable the error interrupt for a given channel. The data value on a
mbed_official 324:406fd2029f23 1630 * register write causes the corresponding bit in the EEI to be set. Setting the
mbed_official 324:406fd2029f23 1631 * SAEE bit provides a global set function, forcing the entire EEI contents to be
mbed_official 324:406fd2029f23 1632 * set. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official 324:406fd2029f23 1633 * multiple-byte registers as a 32-bit word. Reads of this register return all
mbed_official 324:406fd2029f23 1634 * zeroes.
mbed_official 324:406fd2029f23 1635 */
mbed_official 324:406fd2029f23 1636 typedef union _hw_dma_seei
mbed_official 324:406fd2029f23 1637 {
mbed_official 324:406fd2029f23 1638 uint8_t U;
mbed_official 324:406fd2029f23 1639 struct _hw_dma_seei_bitfields
mbed_official 324:406fd2029f23 1640 {
mbed_official 324:406fd2029f23 1641 uint8_t SEEI : 4; /*!< [3:0] Set Enable Error Interrupt */
mbed_official 324:406fd2029f23 1642 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1643 uint8_t SAEE : 1; /*!< [6] Sets All Enable Error Interrupts */
mbed_official 324:406fd2029f23 1644 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 1645 } B;
mbed_official 324:406fd2029f23 1646 } hw_dma_seei_t;
mbed_official 324:406fd2029f23 1647
mbed_official 324:406fd2029f23 1648 /*!
mbed_official 324:406fd2029f23 1649 * @name Constants and macros for entire DMA_SEEI register
mbed_official 324:406fd2029f23 1650 */
mbed_official 324:406fd2029f23 1651 /*@{*/
mbed_official 324:406fd2029f23 1652 #define HW_DMA_SEEI_ADDR(x) ((x) + 0x19U)
mbed_official 324:406fd2029f23 1653
mbed_official 324:406fd2029f23 1654 #define HW_DMA_SEEI(x) (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
mbed_official 324:406fd2029f23 1655 #define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
mbed_official 324:406fd2029f23 1656 #define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
mbed_official 324:406fd2029f23 1657 /*@}*/
mbed_official 324:406fd2029f23 1658
mbed_official 324:406fd2029f23 1659 /*
mbed_official 324:406fd2029f23 1660 * Constants & macros for individual DMA_SEEI bitfields
mbed_official 324:406fd2029f23 1661 */
mbed_official 324:406fd2029f23 1662
mbed_official 324:406fd2029f23 1663 /*!
mbed_official 324:406fd2029f23 1664 * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
mbed_official 324:406fd2029f23 1665 *
mbed_official 324:406fd2029f23 1666 * Sets the corresponding bit in EEI
mbed_official 324:406fd2029f23 1667 */
mbed_official 324:406fd2029f23 1668 /*@{*/
mbed_official 324:406fd2029f23 1669 #define BP_DMA_SEEI_SEEI (0U) /*!< Bit position for DMA_SEEI_SEEI. */
mbed_official 324:406fd2029f23 1670 #define BM_DMA_SEEI_SEEI (0x0FU) /*!< Bit mask for DMA_SEEI_SEEI. */
mbed_official 324:406fd2029f23 1671 #define BS_DMA_SEEI_SEEI (4U) /*!< Bit field size in bits for DMA_SEEI_SEEI. */
mbed_official 324:406fd2029f23 1672
mbed_official 324:406fd2029f23 1673 /*! @brief Format value for bitfield DMA_SEEI_SEEI. */
mbed_official 324:406fd2029f23 1674 #define BF_DMA_SEEI_SEEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI)
mbed_official 324:406fd2029f23 1675
mbed_official 324:406fd2029f23 1676 /*! @brief Set the SEEI field to a new value. */
mbed_official 324:406fd2029f23 1677 #define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
mbed_official 324:406fd2029f23 1678 /*@}*/
mbed_official 324:406fd2029f23 1679
mbed_official 324:406fd2029f23 1680 /*!
mbed_official 324:406fd2029f23 1681 * @name Register DMA_SEEI, field SAEE[6] (WORZ)
mbed_official 324:406fd2029f23 1682 *
mbed_official 324:406fd2029f23 1683 * Values:
mbed_official 324:406fd2029f23 1684 * - 0 - Set only the EEI bit specified in the SEEI field.
mbed_official 324:406fd2029f23 1685 * - 1 - Sets all bits in EEI
mbed_official 324:406fd2029f23 1686 */
mbed_official 324:406fd2029f23 1687 /*@{*/
mbed_official 324:406fd2029f23 1688 #define BP_DMA_SEEI_SAEE (6U) /*!< Bit position for DMA_SEEI_SAEE. */
mbed_official 324:406fd2029f23 1689 #define BM_DMA_SEEI_SAEE (0x40U) /*!< Bit mask for DMA_SEEI_SAEE. */
mbed_official 324:406fd2029f23 1690 #define BS_DMA_SEEI_SAEE (1U) /*!< Bit field size in bits for DMA_SEEI_SAEE. */
mbed_official 324:406fd2029f23 1691
mbed_official 324:406fd2029f23 1692 /*! @brief Format value for bitfield DMA_SEEI_SAEE. */
mbed_official 324:406fd2029f23 1693 #define BF_DMA_SEEI_SAEE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE)
mbed_official 324:406fd2029f23 1694
mbed_official 324:406fd2029f23 1695 /*! @brief Set the SAEE field to a new value. */
mbed_official 324:406fd2029f23 1696 #define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
mbed_official 324:406fd2029f23 1697 /*@}*/
mbed_official 324:406fd2029f23 1698
mbed_official 324:406fd2029f23 1699 /*!
mbed_official 324:406fd2029f23 1700 * @name Register DMA_SEEI, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 1701 *
mbed_official 324:406fd2029f23 1702 * Values:
mbed_official 324:406fd2029f23 1703 * - 0 - Normal operation
mbed_official 324:406fd2029f23 1704 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 1705 */
mbed_official 324:406fd2029f23 1706 /*@{*/
mbed_official 324:406fd2029f23 1707 #define BP_DMA_SEEI_NOP (7U) /*!< Bit position for DMA_SEEI_NOP. */
mbed_official 324:406fd2029f23 1708 #define BM_DMA_SEEI_NOP (0x80U) /*!< Bit mask for DMA_SEEI_NOP. */
mbed_official 324:406fd2029f23 1709 #define BS_DMA_SEEI_NOP (1U) /*!< Bit field size in bits for DMA_SEEI_NOP. */
mbed_official 324:406fd2029f23 1710
mbed_official 324:406fd2029f23 1711 /*! @brief Format value for bitfield DMA_SEEI_NOP. */
mbed_official 324:406fd2029f23 1712 #define BF_DMA_SEEI_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP)
mbed_official 324:406fd2029f23 1713
mbed_official 324:406fd2029f23 1714 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 1715 #define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
mbed_official 324:406fd2029f23 1716 /*@}*/
mbed_official 324:406fd2029f23 1717
mbed_official 324:406fd2029f23 1718 /*******************************************************************************
mbed_official 324:406fd2029f23 1719 * HW_DMA_CERQ - Clear Enable Request Register
mbed_official 324:406fd2029f23 1720 ******************************************************************************/
mbed_official 324:406fd2029f23 1721
mbed_official 324:406fd2029f23 1722 /*!
mbed_official 324:406fd2029f23 1723 * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
mbed_official 324:406fd2029f23 1724 *
mbed_official 324:406fd2029f23 1725 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1726 *
mbed_official 324:406fd2029f23 1727 * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
mbed_official 324:406fd2029f23 1728 * the ERQ to disable the DMA request for a given channel. The data value on a
mbed_official 324:406fd2029f23 1729 * register write causes the corresponding bit in the ERQ to be cleared. Setting the
mbed_official 324:406fd2029f23 1730 * CAER bit provides a global clear function, forcing the entire contents of the
mbed_official 324:406fd2029f23 1731 * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
mbed_official 324:406fd2029f23 1732 * command is ignored. This allows you to write multiple-byte registers as a 32-bit
mbed_official 324:406fd2029f23 1733 * word. Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 1734 */
mbed_official 324:406fd2029f23 1735 typedef union _hw_dma_cerq
mbed_official 324:406fd2029f23 1736 {
mbed_official 324:406fd2029f23 1737 uint8_t U;
mbed_official 324:406fd2029f23 1738 struct _hw_dma_cerq_bitfields
mbed_official 324:406fd2029f23 1739 {
mbed_official 324:406fd2029f23 1740 uint8_t CERQ : 4; /*!< [3:0] Clear Enable Request */
mbed_official 324:406fd2029f23 1741 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1742 uint8_t CAER : 1; /*!< [6] Clear All Enable Requests */
mbed_official 324:406fd2029f23 1743 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 1744 } B;
mbed_official 324:406fd2029f23 1745 } hw_dma_cerq_t;
mbed_official 324:406fd2029f23 1746
mbed_official 324:406fd2029f23 1747 /*!
mbed_official 324:406fd2029f23 1748 * @name Constants and macros for entire DMA_CERQ register
mbed_official 324:406fd2029f23 1749 */
mbed_official 324:406fd2029f23 1750 /*@{*/
mbed_official 324:406fd2029f23 1751 #define HW_DMA_CERQ_ADDR(x) ((x) + 0x1AU)
mbed_official 324:406fd2029f23 1752
mbed_official 324:406fd2029f23 1753 #define HW_DMA_CERQ(x) (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
mbed_official 324:406fd2029f23 1754 #define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
mbed_official 324:406fd2029f23 1755 #define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
mbed_official 324:406fd2029f23 1756 /*@}*/
mbed_official 324:406fd2029f23 1757
mbed_official 324:406fd2029f23 1758 /*
mbed_official 324:406fd2029f23 1759 * Constants & macros for individual DMA_CERQ bitfields
mbed_official 324:406fd2029f23 1760 */
mbed_official 324:406fd2029f23 1761
mbed_official 324:406fd2029f23 1762 /*!
mbed_official 324:406fd2029f23 1763 * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
mbed_official 324:406fd2029f23 1764 *
mbed_official 324:406fd2029f23 1765 * Clears the corresponding bit in ERQ
mbed_official 324:406fd2029f23 1766 */
mbed_official 324:406fd2029f23 1767 /*@{*/
mbed_official 324:406fd2029f23 1768 #define BP_DMA_CERQ_CERQ (0U) /*!< Bit position for DMA_CERQ_CERQ. */
mbed_official 324:406fd2029f23 1769 #define BM_DMA_CERQ_CERQ (0x0FU) /*!< Bit mask for DMA_CERQ_CERQ. */
mbed_official 324:406fd2029f23 1770 #define BS_DMA_CERQ_CERQ (4U) /*!< Bit field size in bits for DMA_CERQ_CERQ. */
mbed_official 324:406fd2029f23 1771
mbed_official 324:406fd2029f23 1772 /*! @brief Format value for bitfield DMA_CERQ_CERQ. */
mbed_official 324:406fd2029f23 1773 #define BF_DMA_CERQ_CERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ)
mbed_official 324:406fd2029f23 1774
mbed_official 324:406fd2029f23 1775 /*! @brief Set the CERQ field to a new value. */
mbed_official 324:406fd2029f23 1776 #define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
mbed_official 324:406fd2029f23 1777 /*@}*/
mbed_official 324:406fd2029f23 1778
mbed_official 324:406fd2029f23 1779 /*!
mbed_official 324:406fd2029f23 1780 * @name Register DMA_CERQ, field CAER[6] (WORZ)
mbed_official 324:406fd2029f23 1781 *
mbed_official 324:406fd2029f23 1782 * Values:
mbed_official 324:406fd2029f23 1783 * - 0 - Clear only the ERQ bit specified in the CERQ field
mbed_official 324:406fd2029f23 1784 * - 1 - Clear all bits in ERQ
mbed_official 324:406fd2029f23 1785 */
mbed_official 324:406fd2029f23 1786 /*@{*/
mbed_official 324:406fd2029f23 1787 #define BP_DMA_CERQ_CAER (6U) /*!< Bit position for DMA_CERQ_CAER. */
mbed_official 324:406fd2029f23 1788 #define BM_DMA_CERQ_CAER (0x40U) /*!< Bit mask for DMA_CERQ_CAER. */
mbed_official 324:406fd2029f23 1789 #define BS_DMA_CERQ_CAER (1U) /*!< Bit field size in bits for DMA_CERQ_CAER. */
mbed_official 324:406fd2029f23 1790
mbed_official 324:406fd2029f23 1791 /*! @brief Format value for bitfield DMA_CERQ_CAER. */
mbed_official 324:406fd2029f23 1792 #define BF_DMA_CERQ_CAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER)
mbed_official 324:406fd2029f23 1793
mbed_official 324:406fd2029f23 1794 /*! @brief Set the CAER field to a new value. */
mbed_official 324:406fd2029f23 1795 #define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
mbed_official 324:406fd2029f23 1796 /*@}*/
mbed_official 324:406fd2029f23 1797
mbed_official 324:406fd2029f23 1798 /*!
mbed_official 324:406fd2029f23 1799 * @name Register DMA_CERQ, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 1800 *
mbed_official 324:406fd2029f23 1801 * Values:
mbed_official 324:406fd2029f23 1802 * - 0 - Normal operation
mbed_official 324:406fd2029f23 1803 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 1804 */
mbed_official 324:406fd2029f23 1805 /*@{*/
mbed_official 324:406fd2029f23 1806 #define BP_DMA_CERQ_NOP (7U) /*!< Bit position for DMA_CERQ_NOP. */
mbed_official 324:406fd2029f23 1807 #define BM_DMA_CERQ_NOP (0x80U) /*!< Bit mask for DMA_CERQ_NOP. */
mbed_official 324:406fd2029f23 1808 #define BS_DMA_CERQ_NOP (1U) /*!< Bit field size in bits for DMA_CERQ_NOP. */
mbed_official 324:406fd2029f23 1809
mbed_official 324:406fd2029f23 1810 /*! @brief Format value for bitfield DMA_CERQ_NOP. */
mbed_official 324:406fd2029f23 1811 #define BF_DMA_CERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP)
mbed_official 324:406fd2029f23 1812
mbed_official 324:406fd2029f23 1813 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 1814 #define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
mbed_official 324:406fd2029f23 1815 /*@}*/
mbed_official 324:406fd2029f23 1816
mbed_official 324:406fd2029f23 1817 /*******************************************************************************
mbed_official 324:406fd2029f23 1818 * HW_DMA_SERQ - Set Enable Request Register
mbed_official 324:406fd2029f23 1819 ******************************************************************************/
mbed_official 324:406fd2029f23 1820
mbed_official 324:406fd2029f23 1821 /*!
mbed_official 324:406fd2029f23 1822 * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
mbed_official 324:406fd2029f23 1823 *
mbed_official 324:406fd2029f23 1824 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1825 *
mbed_official 324:406fd2029f23 1826 * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
mbed_official 324:406fd2029f23 1827 * ERQ to enable the DMA request for a given channel. The data value on a
mbed_official 324:406fd2029f23 1828 * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
mbed_official 324:406fd2029f23 1829 * bit provides a global set function, forcing the entire contents of ERQ to be
mbed_official 324:406fd2029f23 1830 * set. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official 324:406fd2029f23 1831 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 1832 */
mbed_official 324:406fd2029f23 1833 typedef union _hw_dma_serq
mbed_official 324:406fd2029f23 1834 {
mbed_official 324:406fd2029f23 1835 uint8_t U;
mbed_official 324:406fd2029f23 1836 struct _hw_dma_serq_bitfields
mbed_official 324:406fd2029f23 1837 {
mbed_official 324:406fd2029f23 1838 uint8_t SERQ : 4; /*!< [3:0] Set enable request */
mbed_official 324:406fd2029f23 1839 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1840 uint8_t SAER : 1; /*!< [6] Set All Enable Requests */
mbed_official 324:406fd2029f23 1841 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 1842 } B;
mbed_official 324:406fd2029f23 1843 } hw_dma_serq_t;
mbed_official 324:406fd2029f23 1844
mbed_official 324:406fd2029f23 1845 /*!
mbed_official 324:406fd2029f23 1846 * @name Constants and macros for entire DMA_SERQ register
mbed_official 324:406fd2029f23 1847 */
mbed_official 324:406fd2029f23 1848 /*@{*/
mbed_official 324:406fd2029f23 1849 #define HW_DMA_SERQ_ADDR(x) ((x) + 0x1BU)
mbed_official 324:406fd2029f23 1850
mbed_official 324:406fd2029f23 1851 #define HW_DMA_SERQ(x) (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
mbed_official 324:406fd2029f23 1852 #define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
mbed_official 324:406fd2029f23 1853 #define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
mbed_official 324:406fd2029f23 1854 /*@}*/
mbed_official 324:406fd2029f23 1855
mbed_official 324:406fd2029f23 1856 /*
mbed_official 324:406fd2029f23 1857 * Constants & macros for individual DMA_SERQ bitfields
mbed_official 324:406fd2029f23 1858 */
mbed_official 324:406fd2029f23 1859
mbed_official 324:406fd2029f23 1860 /*!
mbed_official 324:406fd2029f23 1861 * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
mbed_official 324:406fd2029f23 1862 *
mbed_official 324:406fd2029f23 1863 * Sets the corresponding bit in ERQ
mbed_official 324:406fd2029f23 1864 */
mbed_official 324:406fd2029f23 1865 /*@{*/
mbed_official 324:406fd2029f23 1866 #define BP_DMA_SERQ_SERQ (0U) /*!< Bit position for DMA_SERQ_SERQ. */
mbed_official 324:406fd2029f23 1867 #define BM_DMA_SERQ_SERQ (0x0FU) /*!< Bit mask for DMA_SERQ_SERQ. */
mbed_official 324:406fd2029f23 1868 #define BS_DMA_SERQ_SERQ (4U) /*!< Bit field size in bits for DMA_SERQ_SERQ. */
mbed_official 324:406fd2029f23 1869
mbed_official 324:406fd2029f23 1870 /*! @brief Format value for bitfield DMA_SERQ_SERQ. */
mbed_official 324:406fd2029f23 1871 #define BF_DMA_SERQ_SERQ(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ)
mbed_official 324:406fd2029f23 1872
mbed_official 324:406fd2029f23 1873 /*! @brief Set the SERQ field to a new value. */
mbed_official 324:406fd2029f23 1874 #define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
mbed_official 324:406fd2029f23 1875 /*@}*/
mbed_official 324:406fd2029f23 1876
mbed_official 324:406fd2029f23 1877 /*!
mbed_official 324:406fd2029f23 1878 * @name Register DMA_SERQ, field SAER[6] (WORZ)
mbed_official 324:406fd2029f23 1879 *
mbed_official 324:406fd2029f23 1880 * Values:
mbed_official 324:406fd2029f23 1881 * - 0 - Set only the ERQ bit specified in the SERQ field
mbed_official 324:406fd2029f23 1882 * - 1 - Set all bits in ERQ
mbed_official 324:406fd2029f23 1883 */
mbed_official 324:406fd2029f23 1884 /*@{*/
mbed_official 324:406fd2029f23 1885 #define BP_DMA_SERQ_SAER (6U) /*!< Bit position for DMA_SERQ_SAER. */
mbed_official 324:406fd2029f23 1886 #define BM_DMA_SERQ_SAER (0x40U) /*!< Bit mask for DMA_SERQ_SAER. */
mbed_official 324:406fd2029f23 1887 #define BS_DMA_SERQ_SAER (1U) /*!< Bit field size in bits for DMA_SERQ_SAER. */
mbed_official 324:406fd2029f23 1888
mbed_official 324:406fd2029f23 1889 /*! @brief Format value for bitfield DMA_SERQ_SAER. */
mbed_official 324:406fd2029f23 1890 #define BF_DMA_SERQ_SAER(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER)
mbed_official 324:406fd2029f23 1891
mbed_official 324:406fd2029f23 1892 /*! @brief Set the SAER field to a new value. */
mbed_official 324:406fd2029f23 1893 #define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
mbed_official 324:406fd2029f23 1894 /*@}*/
mbed_official 324:406fd2029f23 1895
mbed_official 324:406fd2029f23 1896 /*!
mbed_official 324:406fd2029f23 1897 * @name Register DMA_SERQ, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 1898 *
mbed_official 324:406fd2029f23 1899 * Values:
mbed_official 324:406fd2029f23 1900 * - 0 - Normal operation
mbed_official 324:406fd2029f23 1901 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 1902 */
mbed_official 324:406fd2029f23 1903 /*@{*/
mbed_official 324:406fd2029f23 1904 #define BP_DMA_SERQ_NOP (7U) /*!< Bit position for DMA_SERQ_NOP. */
mbed_official 324:406fd2029f23 1905 #define BM_DMA_SERQ_NOP (0x80U) /*!< Bit mask for DMA_SERQ_NOP. */
mbed_official 324:406fd2029f23 1906 #define BS_DMA_SERQ_NOP (1U) /*!< Bit field size in bits for DMA_SERQ_NOP. */
mbed_official 324:406fd2029f23 1907
mbed_official 324:406fd2029f23 1908 /*! @brief Format value for bitfield DMA_SERQ_NOP. */
mbed_official 324:406fd2029f23 1909 #define BF_DMA_SERQ_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP)
mbed_official 324:406fd2029f23 1910
mbed_official 324:406fd2029f23 1911 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 1912 #define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
mbed_official 324:406fd2029f23 1913 /*@}*/
mbed_official 324:406fd2029f23 1914
mbed_official 324:406fd2029f23 1915 /*******************************************************************************
mbed_official 324:406fd2029f23 1916 * HW_DMA_CDNE - Clear DONE Status Bit Register
mbed_official 324:406fd2029f23 1917 ******************************************************************************/
mbed_official 324:406fd2029f23 1918
mbed_official 324:406fd2029f23 1919 /*!
mbed_official 324:406fd2029f23 1920 * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
mbed_official 324:406fd2029f23 1921 *
mbed_official 324:406fd2029f23 1922 * Reset value: 0x00U
mbed_official 324:406fd2029f23 1923 *
mbed_official 324:406fd2029f23 1924 * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
mbed_official 324:406fd2029f23 1925 * the TCD of the given channel. The data value on a register write causes the
mbed_official 324:406fd2029f23 1926 * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
mbed_official 324:406fd2029f23 1927 * the CADN bit provides a global clear function, forcing all DONE bits to be
mbed_official 324:406fd2029f23 1928 * cleared. If the NOP bit is set, the command is ignored. This allows you to write
mbed_official 324:406fd2029f23 1929 * multiple-byte registers as a 32-bit word. Reads of this register return all
mbed_official 324:406fd2029f23 1930 * zeroes.
mbed_official 324:406fd2029f23 1931 */
mbed_official 324:406fd2029f23 1932 typedef union _hw_dma_cdne
mbed_official 324:406fd2029f23 1933 {
mbed_official 324:406fd2029f23 1934 uint8_t U;
mbed_official 324:406fd2029f23 1935 struct _hw_dma_cdne_bitfields
mbed_official 324:406fd2029f23 1936 {
mbed_official 324:406fd2029f23 1937 uint8_t CDNE : 4; /*!< [3:0] Clear DONE Bit */
mbed_official 324:406fd2029f23 1938 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1939 uint8_t CADN : 1; /*!< [6] Clears All DONE Bits */
mbed_official 324:406fd2029f23 1940 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 1941 } B;
mbed_official 324:406fd2029f23 1942 } hw_dma_cdne_t;
mbed_official 324:406fd2029f23 1943
mbed_official 324:406fd2029f23 1944 /*!
mbed_official 324:406fd2029f23 1945 * @name Constants and macros for entire DMA_CDNE register
mbed_official 324:406fd2029f23 1946 */
mbed_official 324:406fd2029f23 1947 /*@{*/
mbed_official 324:406fd2029f23 1948 #define HW_DMA_CDNE_ADDR(x) ((x) + 0x1CU)
mbed_official 324:406fd2029f23 1949
mbed_official 324:406fd2029f23 1950 #define HW_DMA_CDNE(x) (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
mbed_official 324:406fd2029f23 1951 #define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
mbed_official 324:406fd2029f23 1952 #define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
mbed_official 324:406fd2029f23 1953 /*@}*/
mbed_official 324:406fd2029f23 1954
mbed_official 324:406fd2029f23 1955 /*
mbed_official 324:406fd2029f23 1956 * Constants & macros for individual DMA_CDNE bitfields
mbed_official 324:406fd2029f23 1957 */
mbed_official 324:406fd2029f23 1958
mbed_official 324:406fd2029f23 1959 /*!
mbed_official 324:406fd2029f23 1960 * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
mbed_official 324:406fd2029f23 1961 *
mbed_official 324:406fd2029f23 1962 * Clears the corresponding bit in TCDn_CSR[DONE]
mbed_official 324:406fd2029f23 1963 */
mbed_official 324:406fd2029f23 1964 /*@{*/
mbed_official 324:406fd2029f23 1965 #define BP_DMA_CDNE_CDNE (0U) /*!< Bit position for DMA_CDNE_CDNE. */
mbed_official 324:406fd2029f23 1966 #define BM_DMA_CDNE_CDNE (0x0FU) /*!< Bit mask for DMA_CDNE_CDNE. */
mbed_official 324:406fd2029f23 1967 #define BS_DMA_CDNE_CDNE (4U) /*!< Bit field size in bits for DMA_CDNE_CDNE. */
mbed_official 324:406fd2029f23 1968
mbed_official 324:406fd2029f23 1969 /*! @brief Format value for bitfield DMA_CDNE_CDNE. */
mbed_official 324:406fd2029f23 1970 #define BF_DMA_CDNE_CDNE(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE)
mbed_official 324:406fd2029f23 1971
mbed_official 324:406fd2029f23 1972 /*! @brief Set the CDNE field to a new value. */
mbed_official 324:406fd2029f23 1973 #define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
mbed_official 324:406fd2029f23 1974 /*@}*/
mbed_official 324:406fd2029f23 1975
mbed_official 324:406fd2029f23 1976 /*!
mbed_official 324:406fd2029f23 1977 * @name Register DMA_CDNE, field CADN[6] (WORZ)
mbed_official 324:406fd2029f23 1978 *
mbed_official 324:406fd2029f23 1979 * Values:
mbed_official 324:406fd2029f23 1980 * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
mbed_official 324:406fd2029f23 1981 * - 1 - Clears all bits in TCDn_CSR[DONE]
mbed_official 324:406fd2029f23 1982 */
mbed_official 324:406fd2029f23 1983 /*@{*/
mbed_official 324:406fd2029f23 1984 #define BP_DMA_CDNE_CADN (6U) /*!< Bit position for DMA_CDNE_CADN. */
mbed_official 324:406fd2029f23 1985 #define BM_DMA_CDNE_CADN (0x40U) /*!< Bit mask for DMA_CDNE_CADN. */
mbed_official 324:406fd2029f23 1986 #define BS_DMA_CDNE_CADN (1U) /*!< Bit field size in bits for DMA_CDNE_CADN. */
mbed_official 324:406fd2029f23 1987
mbed_official 324:406fd2029f23 1988 /*! @brief Format value for bitfield DMA_CDNE_CADN. */
mbed_official 324:406fd2029f23 1989 #define BF_DMA_CDNE_CADN(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN)
mbed_official 324:406fd2029f23 1990
mbed_official 324:406fd2029f23 1991 /*! @brief Set the CADN field to a new value. */
mbed_official 324:406fd2029f23 1992 #define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
mbed_official 324:406fd2029f23 1993 /*@}*/
mbed_official 324:406fd2029f23 1994
mbed_official 324:406fd2029f23 1995 /*!
mbed_official 324:406fd2029f23 1996 * @name Register DMA_CDNE, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 1997 *
mbed_official 324:406fd2029f23 1998 * Values:
mbed_official 324:406fd2029f23 1999 * - 0 - Normal operation
mbed_official 324:406fd2029f23 2000 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 2001 */
mbed_official 324:406fd2029f23 2002 /*@{*/
mbed_official 324:406fd2029f23 2003 #define BP_DMA_CDNE_NOP (7U) /*!< Bit position for DMA_CDNE_NOP. */
mbed_official 324:406fd2029f23 2004 #define BM_DMA_CDNE_NOP (0x80U) /*!< Bit mask for DMA_CDNE_NOP. */
mbed_official 324:406fd2029f23 2005 #define BS_DMA_CDNE_NOP (1U) /*!< Bit field size in bits for DMA_CDNE_NOP. */
mbed_official 324:406fd2029f23 2006
mbed_official 324:406fd2029f23 2007 /*! @brief Format value for bitfield DMA_CDNE_NOP. */
mbed_official 324:406fd2029f23 2008 #define BF_DMA_CDNE_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP)
mbed_official 324:406fd2029f23 2009
mbed_official 324:406fd2029f23 2010 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 2011 #define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
mbed_official 324:406fd2029f23 2012 /*@}*/
mbed_official 324:406fd2029f23 2013
mbed_official 324:406fd2029f23 2014 /*******************************************************************************
mbed_official 324:406fd2029f23 2015 * HW_DMA_SSRT - Set START Bit Register
mbed_official 324:406fd2029f23 2016 ******************************************************************************/
mbed_official 324:406fd2029f23 2017
mbed_official 324:406fd2029f23 2018 /*!
mbed_official 324:406fd2029f23 2019 * @brief HW_DMA_SSRT - Set START Bit Register (WO)
mbed_official 324:406fd2029f23 2020 *
mbed_official 324:406fd2029f23 2021 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2022 *
mbed_official 324:406fd2029f23 2023 * The SSRT provides a simple memory-mapped mechanism to set the START bit in
mbed_official 324:406fd2029f23 2024 * the TCD of the given channel. The data value on a register write causes the
mbed_official 324:406fd2029f23 2025 * START bit in the corresponding transfer control descriptor to be set. Setting the
mbed_official 324:406fd2029f23 2026 * SAST bit provides a global set function, forcing all START bits to be set. If
mbed_official 324:406fd2029f23 2027 * the NOP bit is set, the command is ignored. This allows you to write
mbed_official 324:406fd2029f23 2028 * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 2029 */
mbed_official 324:406fd2029f23 2030 typedef union _hw_dma_ssrt
mbed_official 324:406fd2029f23 2031 {
mbed_official 324:406fd2029f23 2032 uint8_t U;
mbed_official 324:406fd2029f23 2033 struct _hw_dma_ssrt_bitfields
mbed_official 324:406fd2029f23 2034 {
mbed_official 324:406fd2029f23 2035 uint8_t SSRT : 4; /*!< [3:0] Set START Bit */
mbed_official 324:406fd2029f23 2036 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 2037 uint8_t SAST : 1; /*!< [6] Set All START Bits (activates all
mbed_official 324:406fd2029f23 2038 * channels) */
mbed_official 324:406fd2029f23 2039 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 2040 } B;
mbed_official 324:406fd2029f23 2041 } hw_dma_ssrt_t;
mbed_official 324:406fd2029f23 2042
mbed_official 324:406fd2029f23 2043 /*!
mbed_official 324:406fd2029f23 2044 * @name Constants and macros for entire DMA_SSRT register
mbed_official 324:406fd2029f23 2045 */
mbed_official 324:406fd2029f23 2046 /*@{*/
mbed_official 324:406fd2029f23 2047 #define HW_DMA_SSRT_ADDR(x) ((x) + 0x1DU)
mbed_official 324:406fd2029f23 2048
mbed_official 324:406fd2029f23 2049 #define HW_DMA_SSRT(x) (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
mbed_official 324:406fd2029f23 2050 #define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
mbed_official 324:406fd2029f23 2051 #define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
mbed_official 324:406fd2029f23 2052 /*@}*/
mbed_official 324:406fd2029f23 2053
mbed_official 324:406fd2029f23 2054 /*
mbed_official 324:406fd2029f23 2055 * Constants & macros for individual DMA_SSRT bitfields
mbed_official 324:406fd2029f23 2056 */
mbed_official 324:406fd2029f23 2057
mbed_official 324:406fd2029f23 2058 /*!
mbed_official 324:406fd2029f23 2059 * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
mbed_official 324:406fd2029f23 2060 *
mbed_official 324:406fd2029f23 2061 * Sets the corresponding bit in TCDn_CSR[START]
mbed_official 324:406fd2029f23 2062 */
mbed_official 324:406fd2029f23 2063 /*@{*/
mbed_official 324:406fd2029f23 2064 #define BP_DMA_SSRT_SSRT (0U) /*!< Bit position for DMA_SSRT_SSRT. */
mbed_official 324:406fd2029f23 2065 #define BM_DMA_SSRT_SSRT (0x0FU) /*!< Bit mask for DMA_SSRT_SSRT. */
mbed_official 324:406fd2029f23 2066 #define BS_DMA_SSRT_SSRT (4U) /*!< Bit field size in bits for DMA_SSRT_SSRT. */
mbed_official 324:406fd2029f23 2067
mbed_official 324:406fd2029f23 2068 /*! @brief Format value for bitfield DMA_SSRT_SSRT. */
mbed_official 324:406fd2029f23 2069 #define BF_DMA_SSRT_SSRT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT)
mbed_official 324:406fd2029f23 2070
mbed_official 324:406fd2029f23 2071 /*! @brief Set the SSRT field to a new value. */
mbed_official 324:406fd2029f23 2072 #define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
mbed_official 324:406fd2029f23 2073 /*@}*/
mbed_official 324:406fd2029f23 2074
mbed_official 324:406fd2029f23 2075 /*!
mbed_official 324:406fd2029f23 2076 * @name Register DMA_SSRT, field SAST[6] (WORZ)
mbed_official 324:406fd2029f23 2077 *
mbed_official 324:406fd2029f23 2078 * Values:
mbed_official 324:406fd2029f23 2079 * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
mbed_official 324:406fd2029f23 2080 * - 1 - Set all bits in TCDn_CSR[START]
mbed_official 324:406fd2029f23 2081 */
mbed_official 324:406fd2029f23 2082 /*@{*/
mbed_official 324:406fd2029f23 2083 #define BP_DMA_SSRT_SAST (6U) /*!< Bit position for DMA_SSRT_SAST. */
mbed_official 324:406fd2029f23 2084 #define BM_DMA_SSRT_SAST (0x40U) /*!< Bit mask for DMA_SSRT_SAST. */
mbed_official 324:406fd2029f23 2085 #define BS_DMA_SSRT_SAST (1U) /*!< Bit field size in bits for DMA_SSRT_SAST. */
mbed_official 324:406fd2029f23 2086
mbed_official 324:406fd2029f23 2087 /*! @brief Format value for bitfield DMA_SSRT_SAST. */
mbed_official 324:406fd2029f23 2088 #define BF_DMA_SSRT_SAST(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST)
mbed_official 324:406fd2029f23 2089
mbed_official 324:406fd2029f23 2090 /*! @brief Set the SAST field to a new value. */
mbed_official 324:406fd2029f23 2091 #define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
mbed_official 324:406fd2029f23 2092 /*@}*/
mbed_official 324:406fd2029f23 2093
mbed_official 324:406fd2029f23 2094 /*!
mbed_official 324:406fd2029f23 2095 * @name Register DMA_SSRT, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 2096 *
mbed_official 324:406fd2029f23 2097 * Values:
mbed_official 324:406fd2029f23 2098 * - 0 - Normal operation
mbed_official 324:406fd2029f23 2099 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 2100 */
mbed_official 324:406fd2029f23 2101 /*@{*/
mbed_official 324:406fd2029f23 2102 #define BP_DMA_SSRT_NOP (7U) /*!< Bit position for DMA_SSRT_NOP. */
mbed_official 324:406fd2029f23 2103 #define BM_DMA_SSRT_NOP (0x80U) /*!< Bit mask for DMA_SSRT_NOP. */
mbed_official 324:406fd2029f23 2104 #define BS_DMA_SSRT_NOP (1U) /*!< Bit field size in bits for DMA_SSRT_NOP. */
mbed_official 324:406fd2029f23 2105
mbed_official 324:406fd2029f23 2106 /*! @brief Format value for bitfield DMA_SSRT_NOP. */
mbed_official 324:406fd2029f23 2107 #define BF_DMA_SSRT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP)
mbed_official 324:406fd2029f23 2108
mbed_official 324:406fd2029f23 2109 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 2110 #define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
mbed_official 324:406fd2029f23 2111 /*@}*/
mbed_official 324:406fd2029f23 2112
mbed_official 324:406fd2029f23 2113 /*******************************************************************************
mbed_official 324:406fd2029f23 2114 * HW_DMA_CERR - Clear Error Register
mbed_official 324:406fd2029f23 2115 ******************************************************************************/
mbed_official 324:406fd2029f23 2116
mbed_official 324:406fd2029f23 2117 /*!
mbed_official 324:406fd2029f23 2118 * @brief HW_DMA_CERR - Clear Error Register (WO)
mbed_official 324:406fd2029f23 2119 *
mbed_official 324:406fd2029f23 2120 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2121 *
mbed_official 324:406fd2029f23 2122 * The CERR provides a simple memory-mapped mechanism to clear a given bit in
mbed_official 324:406fd2029f23 2123 * the ERR to disable the error condition flag for a given channel. The given value
mbed_official 324:406fd2029f23 2124 * on a register write causes the corresponding bit in the ERR to be cleared.
mbed_official 324:406fd2029f23 2125 * Setting the CAEI bit provides a global clear function, forcing the ERR contents
mbed_official 324:406fd2029f23 2126 * to be cleared, clearing all channel error indicators. If the NOP bit is set,
mbed_official 324:406fd2029f23 2127 * the command is ignored. This allows you to write multiple-byte registers as a
mbed_official 324:406fd2029f23 2128 * 32-bit word. Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 2129 */
mbed_official 324:406fd2029f23 2130 typedef union _hw_dma_cerr
mbed_official 324:406fd2029f23 2131 {
mbed_official 324:406fd2029f23 2132 uint8_t U;
mbed_official 324:406fd2029f23 2133 struct _hw_dma_cerr_bitfields
mbed_official 324:406fd2029f23 2134 {
mbed_official 324:406fd2029f23 2135 uint8_t CERR : 4; /*!< [3:0] Clear Error Indicator */
mbed_official 324:406fd2029f23 2136 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 2137 uint8_t CAEI : 1; /*!< [6] Clear All Error Indicators */
mbed_official 324:406fd2029f23 2138 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 2139 } B;
mbed_official 324:406fd2029f23 2140 } hw_dma_cerr_t;
mbed_official 324:406fd2029f23 2141
mbed_official 324:406fd2029f23 2142 /*!
mbed_official 324:406fd2029f23 2143 * @name Constants and macros for entire DMA_CERR register
mbed_official 324:406fd2029f23 2144 */
mbed_official 324:406fd2029f23 2145 /*@{*/
mbed_official 324:406fd2029f23 2146 #define HW_DMA_CERR_ADDR(x) ((x) + 0x1EU)
mbed_official 324:406fd2029f23 2147
mbed_official 324:406fd2029f23 2148 #define HW_DMA_CERR(x) (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
mbed_official 324:406fd2029f23 2149 #define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
mbed_official 324:406fd2029f23 2150 #define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
mbed_official 324:406fd2029f23 2151 /*@}*/
mbed_official 324:406fd2029f23 2152
mbed_official 324:406fd2029f23 2153 /*
mbed_official 324:406fd2029f23 2154 * Constants & macros for individual DMA_CERR bitfields
mbed_official 324:406fd2029f23 2155 */
mbed_official 324:406fd2029f23 2156
mbed_official 324:406fd2029f23 2157 /*!
mbed_official 324:406fd2029f23 2158 * @name Register DMA_CERR, field CERR[3:0] (WORZ)
mbed_official 324:406fd2029f23 2159 *
mbed_official 324:406fd2029f23 2160 * Clears the corresponding bit in ERR
mbed_official 324:406fd2029f23 2161 */
mbed_official 324:406fd2029f23 2162 /*@{*/
mbed_official 324:406fd2029f23 2163 #define BP_DMA_CERR_CERR (0U) /*!< Bit position for DMA_CERR_CERR. */
mbed_official 324:406fd2029f23 2164 #define BM_DMA_CERR_CERR (0x0FU) /*!< Bit mask for DMA_CERR_CERR. */
mbed_official 324:406fd2029f23 2165 #define BS_DMA_CERR_CERR (4U) /*!< Bit field size in bits for DMA_CERR_CERR. */
mbed_official 324:406fd2029f23 2166
mbed_official 324:406fd2029f23 2167 /*! @brief Format value for bitfield DMA_CERR_CERR. */
mbed_official 324:406fd2029f23 2168 #define BF_DMA_CERR_CERR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR)
mbed_official 324:406fd2029f23 2169
mbed_official 324:406fd2029f23 2170 /*! @brief Set the CERR field to a new value. */
mbed_official 324:406fd2029f23 2171 #define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
mbed_official 324:406fd2029f23 2172 /*@}*/
mbed_official 324:406fd2029f23 2173
mbed_official 324:406fd2029f23 2174 /*!
mbed_official 324:406fd2029f23 2175 * @name Register DMA_CERR, field CAEI[6] (WORZ)
mbed_official 324:406fd2029f23 2176 *
mbed_official 324:406fd2029f23 2177 * Values:
mbed_official 324:406fd2029f23 2178 * - 0 - Clear only the ERR bit specified in the CERR field
mbed_official 324:406fd2029f23 2179 * - 1 - Clear all bits in ERR
mbed_official 324:406fd2029f23 2180 */
mbed_official 324:406fd2029f23 2181 /*@{*/
mbed_official 324:406fd2029f23 2182 #define BP_DMA_CERR_CAEI (6U) /*!< Bit position for DMA_CERR_CAEI. */
mbed_official 324:406fd2029f23 2183 #define BM_DMA_CERR_CAEI (0x40U) /*!< Bit mask for DMA_CERR_CAEI. */
mbed_official 324:406fd2029f23 2184 #define BS_DMA_CERR_CAEI (1U) /*!< Bit field size in bits for DMA_CERR_CAEI. */
mbed_official 324:406fd2029f23 2185
mbed_official 324:406fd2029f23 2186 /*! @brief Format value for bitfield DMA_CERR_CAEI. */
mbed_official 324:406fd2029f23 2187 #define BF_DMA_CERR_CAEI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI)
mbed_official 324:406fd2029f23 2188
mbed_official 324:406fd2029f23 2189 /*! @brief Set the CAEI field to a new value. */
mbed_official 324:406fd2029f23 2190 #define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
mbed_official 324:406fd2029f23 2191 /*@}*/
mbed_official 324:406fd2029f23 2192
mbed_official 324:406fd2029f23 2193 /*!
mbed_official 324:406fd2029f23 2194 * @name Register DMA_CERR, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 2195 *
mbed_official 324:406fd2029f23 2196 * Values:
mbed_official 324:406fd2029f23 2197 * - 0 - Normal operation
mbed_official 324:406fd2029f23 2198 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 2199 */
mbed_official 324:406fd2029f23 2200 /*@{*/
mbed_official 324:406fd2029f23 2201 #define BP_DMA_CERR_NOP (7U) /*!< Bit position for DMA_CERR_NOP. */
mbed_official 324:406fd2029f23 2202 #define BM_DMA_CERR_NOP (0x80U) /*!< Bit mask for DMA_CERR_NOP. */
mbed_official 324:406fd2029f23 2203 #define BS_DMA_CERR_NOP (1U) /*!< Bit field size in bits for DMA_CERR_NOP. */
mbed_official 324:406fd2029f23 2204
mbed_official 324:406fd2029f23 2205 /*! @brief Format value for bitfield DMA_CERR_NOP. */
mbed_official 324:406fd2029f23 2206 #define BF_DMA_CERR_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP)
mbed_official 324:406fd2029f23 2207
mbed_official 324:406fd2029f23 2208 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 2209 #define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
mbed_official 324:406fd2029f23 2210 /*@}*/
mbed_official 324:406fd2029f23 2211
mbed_official 324:406fd2029f23 2212 /*******************************************************************************
mbed_official 324:406fd2029f23 2213 * HW_DMA_CINT - Clear Interrupt Request Register
mbed_official 324:406fd2029f23 2214 ******************************************************************************/
mbed_official 324:406fd2029f23 2215
mbed_official 324:406fd2029f23 2216 /*!
mbed_official 324:406fd2029f23 2217 * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
mbed_official 324:406fd2029f23 2218 *
mbed_official 324:406fd2029f23 2219 * Reset value: 0x00U
mbed_official 324:406fd2029f23 2220 *
mbed_official 324:406fd2029f23 2221 * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
mbed_official 324:406fd2029f23 2222 * the INT to disable the interrupt request for a given channel. The given value
mbed_official 324:406fd2029f23 2223 * on a register write causes the corresponding bit in the INT to be cleared.
mbed_official 324:406fd2029f23 2224 * Setting the CAIR bit provides a global clear function, forcing the entire contents
mbed_official 324:406fd2029f23 2225 * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
mbed_official 324:406fd2029f23 2226 * bit is set, the command is ignored. This allows you to write multiple-byte
mbed_official 324:406fd2029f23 2227 * registers as a 32-bit word. Reads of this register return all zeroes.
mbed_official 324:406fd2029f23 2228 */
mbed_official 324:406fd2029f23 2229 typedef union _hw_dma_cint
mbed_official 324:406fd2029f23 2230 {
mbed_official 324:406fd2029f23 2231 uint8_t U;
mbed_official 324:406fd2029f23 2232 struct _hw_dma_cint_bitfields
mbed_official 324:406fd2029f23 2233 {
mbed_official 324:406fd2029f23 2234 uint8_t CINT : 4; /*!< [3:0] Clear Interrupt Request */
mbed_official 324:406fd2029f23 2235 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 2236 uint8_t CAIR : 1; /*!< [6] Clear All Interrupt Requests */
mbed_official 324:406fd2029f23 2237 uint8_t NOP : 1; /*!< [7] No Op enable */
mbed_official 324:406fd2029f23 2238 } B;
mbed_official 324:406fd2029f23 2239 } hw_dma_cint_t;
mbed_official 324:406fd2029f23 2240
mbed_official 324:406fd2029f23 2241 /*!
mbed_official 324:406fd2029f23 2242 * @name Constants and macros for entire DMA_CINT register
mbed_official 324:406fd2029f23 2243 */
mbed_official 324:406fd2029f23 2244 /*@{*/
mbed_official 324:406fd2029f23 2245 #define HW_DMA_CINT_ADDR(x) ((x) + 0x1FU)
mbed_official 324:406fd2029f23 2246
mbed_official 324:406fd2029f23 2247 #define HW_DMA_CINT(x) (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
mbed_official 324:406fd2029f23 2248 #define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
mbed_official 324:406fd2029f23 2249 #define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
mbed_official 324:406fd2029f23 2250 /*@}*/
mbed_official 324:406fd2029f23 2251
mbed_official 324:406fd2029f23 2252 /*
mbed_official 324:406fd2029f23 2253 * Constants & macros for individual DMA_CINT bitfields
mbed_official 324:406fd2029f23 2254 */
mbed_official 324:406fd2029f23 2255
mbed_official 324:406fd2029f23 2256 /*!
mbed_official 324:406fd2029f23 2257 * @name Register DMA_CINT, field CINT[3:0] (WORZ)
mbed_official 324:406fd2029f23 2258 *
mbed_official 324:406fd2029f23 2259 * Clears the corresponding bit in INT
mbed_official 324:406fd2029f23 2260 */
mbed_official 324:406fd2029f23 2261 /*@{*/
mbed_official 324:406fd2029f23 2262 #define BP_DMA_CINT_CINT (0U) /*!< Bit position for DMA_CINT_CINT. */
mbed_official 324:406fd2029f23 2263 #define BM_DMA_CINT_CINT (0x0FU) /*!< Bit mask for DMA_CINT_CINT. */
mbed_official 324:406fd2029f23 2264 #define BS_DMA_CINT_CINT (4U) /*!< Bit field size in bits for DMA_CINT_CINT. */
mbed_official 324:406fd2029f23 2265
mbed_official 324:406fd2029f23 2266 /*! @brief Format value for bitfield DMA_CINT_CINT. */
mbed_official 324:406fd2029f23 2267 #define BF_DMA_CINT_CINT(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT)
mbed_official 324:406fd2029f23 2268
mbed_official 324:406fd2029f23 2269 /*! @brief Set the CINT field to a new value. */
mbed_official 324:406fd2029f23 2270 #define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
mbed_official 324:406fd2029f23 2271 /*@}*/
mbed_official 324:406fd2029f23 2272
mbed_official 324:406fd2029f23 2273 /*!
mbed_official 324:406fd2029f23 2274 * @name Register DMA_CINT, field CAIR[6] (WORZ)
mbed_official 324:406fd2029f23 2275 *
mbed_official 324:406fd2029f23 2276 * Values:
mbed_official 324:406fd2029f23 2277 * - 0 - Clear only the INT bit specified in the CINT field
mbed_official 324:406fd2029f23 2278 * - 1 - Clear all bits in INT
mbed_official 324:406fd2029f23 2279 */
mbed_official 324:406fd2029f23 2280 /*@{*/
mbed_official 324:406fd2029f23 2281 #define BP_DMA_CINT_CAIR (6U) /*!< Bit position for DMA_CINT_CAIR. */
mbed_official 324:406fd2029f23 2282 #define BM_DMA_CINT_CAIR (0x40U) /*!< Bit mask for DMA_CINT_CAIR. */
mbed_official 324:406fd2029f23 2283 #define BS_DMA_CINT_CAIR (1U) /*!< Bit field size in bits for DMA_CINT_CAIR. */
mbed_official 324:406fd2029f23 2284
mbed_official 324:406fd2029f23 2285 /*! @brief Format value for bitfield DMA_CINT_CAIR. */
mbed_official 324:406fd2029f23 2286 #define BF_DMA_CINT_CAIR(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR)
mbed_official 324:406fd2029f23 2287
mbed_official 324:406fd2029f23 2288 /*! @brief Set the CAIR field to a new value. */
mbed_official 324:406fd2029f23 2289 #define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
mbed_official 324:406fd2029f23 2290 /*@}*/
mbed_official 324:406fd2029f23 2291
mbed_official 324:406fd2029f23 2292 /*!
mbed_official 324:406fd2029f23 2293 * @name Register DMA_CINT, field NOP[7] (WORZ)
mbed_official 324:406fd2029f23 2294 *
mbed_official 324:406fd2029f23 2295 * Values:
mbed_official 324:406fd2029f23 2296 * - 0 - Normal operation
mbed_official 324:406fd2029f23 2297 * - 1 - No operation, ignore the other bits in this register
mbed_official 324:406fd2029f23 2298 */
mbed_official 324:406fd2029f23 2299 /*@{*/
mbed_official 324:406fd2029f23 2300 #define BP_DMA_CINT_NOP (7U) /*!< Bit position for DMA_CINT_NOP. */
mbed_official 324:406fd2029f23 2301 #define BM_DMA_CINT_NOP (0x80U) /*!< Bit mask for DMA_CINT_NOP. */
mbed_official 324:406fd2029f23 2302 #define BS_DMA_CINT_NOP (1U) /*!< Bit field size in bits for DMA_CINT_NOP. */
mbed_official 324:406fd2029f23 2303
mbed_official 324:406fd2029f23 2304 /*! @brief Format value for bitfield DMA_CINT_NOP. */
mbed_official 324:406fd2029f23 2305 #define BF_DMA_CINT_NOP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP)
mbed_official 324:406fd2029f23 2306
mbed_official 324:406fd2029f23 2307 /*! @brief Set the NOP field to a new value. */
mbed_official 324:406fd2029f23 2308 #define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
mbed_official 324:406fd2029f23 2309 /*@}*/
mbed_official 324:406fd2029f23 2310
mbed_official 324:406fd2029f23 2311 /*******************************************************************************
mbed_official 324:406fd2029f23 2312 * HW_DMA_INT - Interrupt Request Register
mbed_official 324:406fd2029f23 2313 ******************************************************************************/
mbed_official 324:406fd2029f23 2314
mbed_official 324:406fd2029f23 2315 /*!
mbed_official 324:406fd2029f23 2316 * @brief HW_DMA_INT - Interrupt Request Register (RW)
mbed_official 324:406fd2029f23 2317 *
mbed_official 324:406fd2029f23 2318 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2319 *
mbed_official 324:406fd2029f23 2320 * The INT register provides a bit map for the 16 channels signaling the
mbed_official 324:406fd2029f23 2321 * presence of an interrupt request for each channel. Depending on the appropriate bit
mbed_official 324:406fd2029f23 2322 * setting in the transfer-control descriptors, the eDMA engine generates an
mbed_official 324:406fd2029f23 2323 * interrupt on data transfer completion. The outputs of this register are directly
mbed_official 324:406fd2029f23 2324 * routed to the interrupt controller (INTC). During the interrupt-service routine
mbed_official 324:406fd2029f23 2325 * associated with any given channel, it is the software's responsibility to
mbed_official 324:406fd2029f23 2326 * clear the appropriate bit, negating the interrupt request. Typically, a write to
mbed_official 324:406fd2029f23 2327 * the CINT register in the interrupt service routine is used for this purpose.
mbed_official 324:406fd2029f23 2328 * The state of any given channel's interrupt request is directly affected by
mbed_official 324:406fd2029f23 2329 * writes to this register; it is also affected by writes to the CINT register. On
mbed_official 324:406fd2029f23 2330 * writes to INT, a 1 in any bit position clears the corresponding channel's
mbed_official 324:406fd2029f23 2331 * interrupt request. A zero in any bit position has no affect on the corresponding
mbed_official 324:406fd2029f23 2332 * channel's current interrupt status. The CINT register is provided so the interrupt
mbed_official 324:406fd2029f23 2333 * request for a single channel can easily be cleared without the need to
mbed_official 324:406fd2029f23 2334 * perform a read-modify-write sequence to the INT register.
mbed_official 324:406fd2029f23 2335 */
mbed_official 324:406fd2029f23 2336 typedef union _hw_dma_int
mbed_official 324:406fd2029f23 2337 {
mbed_official 324:406fd2029f23 2338 uint32_t U;
mbed_official 324:406fd2029f23 2339 struct _hw_dma_int_bitfields
mbed_official 324:406fd2029f23 2340 {
mbed_official 324:406fd2029f23 2341 uint32_t INT0 : 1; /*!< [0] Interrupt Request 0 */
mbed_official 324:406fd2029f23 2342 uint32_t INT1 : 1; /*!< [1] Interrupt Request 1 */
mbed_official 324:406fd2029f23 2343 uint32_t INT2 : 1; /*!< [2] Interrupt Request 2 */
mbed_official 324:406fd2029f23 2344 uint32_t INT3 : 1; /*!< [3] Interrupt Request 3 */
mbed_official 324:406fd2029f23 2345 uint32_t INT4 : 1; /*!< [4] Interrupt Request 4 */
mbed_official 324:406fd2029f23 2346 uint32_t INT5 : 1; /*!< [5] Interrupt Request 5 */
mbed_official 324:406fd2029f23 2347 uint32_t INT6 : 1; /*!< [6] Interrupt Request 6 */
mbed_official 324:406fd2029f23 2348 uint32_t INT7 : 1; /*!< [7] Interrupt Request 7 */
mbed_official 324:406fd2029f23 2349 uint32_t INT8 : 1; /*!< [8] Interrupt Request 8 */
mbed_official 324:406fd2029f23 2350 uint32_t INT9 : 1; /*!< [9] Interrupt Request 9 */
mbed_official 324:406fd2029f23 2351 uint32_t INT10 : 1; /*!< [10] Interrupt Request 10 */
mbed_official 324:406fd2029f23 2352 uint32_t INT11 : 1; /*!< [11] Interrupt Request 11 */
mbed_official 324:406fd2029f23 2353 uint32_t INT12 : 1; /*!< [12] Interrupt Request 12 */
mbed_official 324:406fd2029f23 2354 uint32_t INT13 : 1; /*!< [13] Interrupt Request 13 */
mbed_official 324:406fd2029f23 2355 uint32_t INT14 : 1; /*!< [14] Interrupt Request 14 */
mbed_official 324:406fd2029f23 2356 uint32_t INT15 : 1; /*!< [15] Interrupt Request 15 */
mbed_official 324:406fd2029f23 2357 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 2358 } B;
mbed_official 324:406fd2029f23 2359 } hw_dma_int_t;
mbed_official 324:406fd2029f23 2360
mbed_official 324:406fd2029f23 2361 /*!
mbed_official 324:406fd2029f23 2362 * @name Constants and macros for entire DMA_INT register
mbed_official 324:406fd2029f23 2363 */
mbed_official 324:406fd2029f23 2364 /*@{*/
mbed_official 324:406fd2029f23 2365 #define HW_DMA_INT_ADDR(x) ((x) + 0x24U)
mbed_official 324:406fd2029f23 2366
mbed_official 324:406fd2029f23 2367 #define HW_DMA_INT(x) (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
mbed_official 324:406fd2029f23 2368 #define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
mbed_official 324:406fd2029f23 2369 #define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
mbed_official 324:406fd2029f23 2370 #define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) | (v)))
mbed_official 324:406fd2029f23 2371 #define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2372 #define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2373 /*@}*/
mbed_official 324:406fd2029f23 2374
mbed_official 324:406fd2029f23 2375 /*
mbed_official 324:406fd2029f23 2376 * Constants & macros for individual DMA_INT bitfields
mbed_official 324:406fd2029f23 2377 */
mbed_official 324:406fd2029f23 2378
mbed_official 324:406fd2029f23 2379 /*!
mbed_official 324:406fd2029f23 2380 * @name Register DMA_INT, field INT0[0] (W1C)
mbed_official 324:406fd2029f23 2381 *
mbed_official 324:406fd2029f23 2382 * Values:
mbed_official 324:406fd2029f23 2383 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2384 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2385 */
mbed_official 324:406fd2029f23 2386 /*@{*/
mbed_official 324:406fd2029f23 2387 #define BP_DMA_INT_INT0 (0U) /*!< Bit position for DMA_INT_INT0. */
mbed_official 324:406fd2029f23 2388 #define BM_DMA_INT_INT0 (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */
mbed_official 324:406fd2029f23 2389 #define BS_DMA_INT_INT0 (1U) /*!< Bit field size in bits for DMA_INT_INT0. */
mbed_official 324:406fd2029f23 2390
mbed_official 324:406fd2029f23 2391 /*! @brief Read current value of the DMA_INT_INT0 field. */
mbed_official 324:406fd2029f23 2392 #define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
mbed_official 324:406fd2029f23 2393
mbed_official 324:406fd2029f23 2394 /*! @brief Format value for bitfield DMA_INT_INT0. */
mbed_official 324:406fd2029f23 2395 #define BF_DMA_INT_INT0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0)
mbed_official 324:406fd2029f23 2396
mbed_official 324:406fd2029f23 2397 /*! @brief Set the INT0 field to a new value. */
mbed_official 324:406fd2029f23 2398 #define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
mbed_official 324:406fd2029f23 2399 /*@}*/
mbed_official 324:406fd2029f23 2400
mbed_official 324:406fd2029f23 2401 /*!
mbed_official 324:406fd2029f23 2402 * @name Register DMA_INT, field INT1[1] (W1C)
mbed_official 324:406fd2029f23 2403 *
mbed_official 324:406fd2029f23 2404 * Values:
mbed_official 324:406fd2029f23 2405 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2406 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2407 */
mbed_official 324:406fd2029f23 2408 /*@{*/
mbed_official 324:406fd2029f23 2409 #define BP_DMA_INT_INT1 (1U) /*!< Bit position for DMA_INT_INT1. */
mbed_official 324:406fd2029f23 2410 #define BM_DMA_INT_INT1 (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */
mbed_official 324:406fd2029f23 2411 #define BS_DMA_INT_INT1 (1U) /*!< Bit field size in bits for DMA_INT_INT1. */
mbed_official 324:406fd2029f23 2412
mbed_official 324:406fd2029f23 2413 /*! @brief Read current value of the DMA_INT_INT1 field. */
mbed_official 324:406fd2029f23 2414 #define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
mbed_official 324:406fd2029f23 2415
mbed_official 324:406fd2029f23 2416 /*! @brief Format value for bitfield DMA_INT_INT1. */
mbed_official 324:406fd2029f23 2417 #define BF_DMA_INT_INT1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1)
mbed_official 324:406fd2029f23 2418
mbed_official 324:406fd2029f23 2419 /*! @brief Set the INT1 field to a new value. */
mbed_official 324:406fd2029f23 2420 #define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
mbed_official 324:406fd2029f23 2421 /*@}*/
mbed_official 324:406fd2029f23 2422
mbed_official 324:406fd2029f23 2423 /*!
mbed_official 324:406fd2029f23 2424 * @name Register DMA_INT, field INT2[2] (W1C)
mbed_official 324:406fd2029f23 2425 *
mbed_official 324:406fd2029f23 2426 * Values:
mbed_official 324:406fd2029f23 2427 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2428 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2429 */
mbed_official 324:406fd2029f23 2430 /*@{*/
mbed_official 324:406fd2029f23 2431 #define BP_DMA_INT_INT2 (2U) /*!< Bit position for DMA_INT_INT2. */
mbed_official 324:406fd2029f23 2432 #define BM_DMA_INT_INT2 (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */
mbed_official 324:406fd2029f23 2433 #define BS_DMA_INT_INT2 (1U) /*!< Bit field size in bits for DMA_INT_INT2. */
mbed_official 324:406fd2029f23 2434
mbed_official 324:406fd2029f23 2435 /*! @brief Read current value of the DMA_INT_INT2 field. */
mbed_official 324:406fd2029f23 2436 #define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
mbed_official 324:406fd2029f23 2437
mbed_official 324:406fd2029f23 2438 /*! @brief Format value for bitfield DMA_INT_INT2. */
mbed_official 324:406fd2029f23 2439 #define BF_DMA_INT_INT2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2)
mbed_official 324:406fd2029f23 2440
mbed_official 324:406fd2029f23 2441 /*! @brief Set the INT2 field to a new value. */
mbed_official 324:406fd2029f23 2442 #define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
mbed_official 324:406fd2029f23 2443 /*@}*/
mbed_official 324:406fd2029f23 2444
mbed_official 324:406fd2029f23 2445 /*!
mbed_official 324:406fd2029f23 2446 * @name Register DMA_INT, field INT3[3] (W1C)
mbed_official 324:406fd2029f23 2447 *
mbed_official 324:406fd2029f23 2448 * Values:
mbed_official 324:406fd2029f23 2449 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2450 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2451 */
mbed_official 324:406fd2029f23 2452 /*@{*/
mbed_official 324:406fd2029f23 2453 #define BP_DMA_INT_INT3 (3U) /*!< Bit position for DMA_INT_INT3. */
mbed_official 324:406fd2029f23 2454 #define BM_DMA_INT_INT3 (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */
mbed_official 324:406fd2029f23 2455 #define BS_DMA_INT_INT3 (1U) /*!< Bit field size in bits for DMA_INT_INT3. */
mbed_official 324:406fd2029f23 2456
mbed_official 324:406fd2029f23 2457 /*! @brief Read current value of the DMA_INT_INT3 field. */
mbed_official 324:406fd2029f23 2458 #define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
mbed_official 324:406fd2029f23 2459
mbed_official 324:406fd2029f23 2460 /*! @brief Format value for bitfield DMA_INT_INT3. */
mbed_official 324:406fd2029f23 2461 #define BF_DMA_INT_INT3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3)
mbed_official 324:406fd2029f23 2462
mbed_official 324:406fd2029f23 2463 /*! @brief Set the INT3 field to a new value. */
mbed_official 324:406fd2029f23 2464 #define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
mbed_official 324:406fd2029f23 2465 /*@}*/
mbed_official 324:406fd2029f23 2466
mbed_official 324:406fd2029f23 2467 /*!
mbed_official 324:406fd2029f23 2468 * @name Register DMA_INT, field INT4[4] (W1C)
mbed_official 324:406fd2029f23 2469 *
mbed_official 324:406fd2029f23 2470 * Values:
mbed_official 324:406fd2029f23 2471 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2472 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2473 */
mbed_official 324:406fd2029f23 2474 /*@{*/
mbed_official 324:406fd2029f23 2475 #define BP_DMA_INT_INT4 (4U) /*!< Bit position for DMA_INT_INT4. */
mbed_official 324:406fd2029f23 2476 #define BM_DMA_INT_INT4 (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */
mbed_official 324:406fd2029f23 2477 #define BS_DMA_INT_INT4 (1U) /*!< Bit field size in bits for DMA_INT_INT4. */
mbed_official 324:406fd2029f23 2478
mbed_official 324:406fd2029f23 2479 /*! @brief Read current value of the DMA_INT_INT4 field. */
mbed_official 324:406fd2029f23 2480 #define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
mbed_official 324:406fd2029f23 2481
mbed_official 324:406fd2029f23 2482 /*! @brief Format value for bitfield DMA_INT_INT4. */
mbed_official 324:406fd2029f23 2483 #define BF_DMA_INT_INT4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4)
mbed_official 324:406fd2029f23 2484
mbed_official 324:406fd2029f23 2485 /*! @brief Set the INT4 field to a new value. */
mbed_official 324:406fd2029f23 2486 #define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
mbed_official 324:406fd2029f23 2487 /*@}*/
mbed_official 324:406fd2029f23 2488
mbed_official 324:406fd2029f23 2489 /*!
mbed_official 324:406fd2029f23 2490 * @name Register DMA_INT, field INT5[5] (W1C)
mbed_official 324:406fd2029f23 2491 *
mbed_official 324:406fd2029f23 2492 * Values:
mbed_official 324:406fd2029f23 2493 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2494 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2495 */
mbed_official 324:406fd2029f23 2496 /*@{*/
mbed_official 324:406fd2029f23 2497 #define BP_DMA_INT_INT5 (5U) /*!< Bit position for DMA_INT_INT5. */
mbed_official 324:406fd2029f23 2498 #define BM_DMA_INT_INT5 (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */
mbed_official 324:406fd2029f23 2499 #define BS_DMA_INT_INT5 (1U) /*!< Bit field size in bits for DMA_INT_INT5. */
mbed_official 324:406fd2029f23 2500
mbed_official 324:406fd2029f23 2501 /*! @brief Read current value of the DMA_INT_INT5 field. */
mbed_official 324:406fd2029f23 2502 #define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
mbed_official 324:406fd2029f23 2503
mbed_official 324:406fd2029f23 2504 /*! @brief Format value for bitfield DMA_INT_INT5. */
mbed_official 324:406fd2029f23 2505 #define BF_DMA_INT_INT5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5)
mbed_official 324:406fd2029f23 2506
mbed_official 324:406fd2029f23 2507 /*! @brief Set the INT5 field to a new value. */
mbed_official 324:406fd2029f23 2508 #define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
mbed_official 324:406fd2029f23 2509 /*@}*/
mbed_official 324:406fd2029f23 2510
mbed_official 324:406fd2029f23 2511 /*!
mbed_official 324:406fd2029f23 2512 * @name Register DMA_INT, field INT6[6] (W1C)
mbed_official 324:406fd2029f23 2513 *
mbed_official 324:406fd2029f23 2514 * Values:
mbed_official 324:406fd2029f23 2515 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2516 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2517 */
mbed_official 324:406fd2029f23 2518 /*@{*/
mbed_official 324:406fd2029f23 2519 #define BP_DMA_INT_INT6 (6U) /*!< Bit position for DMA_INT_INT6. */
mbed_official 324:406fd2029f23 2520 #define BM_DMA_INT_INT6 (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */
mbed_official 324:406fd2029f23 2521 #define BS_DMA_INT_INT6 (1U) /*!< Bit field size in bits for DMA_INT_INT6. */
mbed_official 324:406fd2029f23 2522
mbed_official 324:406fd2029f23 2523 /*! @brief Read current value of the DMA_INT_INT6 field. */
mbed_official 324:406fd2029f23 2524 #define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
mbed_official 324:406fd2029f23 2525
mbed_official 324:406fd2029f23 2526 /*! @brief Format value for bitfield DMA_INT_INT6. */
mbed_official 324:406fd2029f23 2527 #define BF_DMA_INT_INT6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6)
mbed_official 324:406fd2029f23 2528
mbed_official 324:406fd2029f23 2529 /*! @brief Set the INT6 field to a new value. */
mbed_official 324:406fd2029f23 2530 #define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
mbed_official 324:406fd2029f23 2531 /*@}*/
mbed_official 324:406fd2029f23 2532
mbed_official 324:406fd2029f23 2533 /*!
mbed_official 324:406fd2029f23 2534 * @name Register DMA_INT, field INT7[7] (W1C)
mbed_official 324:406fd2029f23 2535 *
mbed_official 324:406fd2029f23 2536 * Values:
mbed_official 324:406fd2029f23 2537 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2538 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2539 */
mbed_official 324:406fd2029f23 2540 /*@{*/
mbed_official 324:406fd2029f23 2541 #define BP_DMA_INT_INT7 (7U) /*!< Bit position for DMA_INT_INT7. */
mbed_official 324:406fd2029f23 2542 #define BM_DMA_INT_INT7 (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */
mbed_official 324:406fd2029f23 2543 #define BS_DMA_INT_INT7 (1U) /*!< Bit field size in bits for DMA_INT_INT7. */
mbed_official 324:406fd2029f23 2544
mbed_official 324:406fd2029f23 2545 /*! @brief Read current value of the DMA_INT_INT7 field. */
mbed_official 324:406fd2029f23 2546 #define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
mbed_official 324:406fd2029f23 2547
mbed_official 324:406fd2029f23 2548 /*! @brief Format value for bitfield DMA_INT_INT7. */
mbed_official 324:406fd2029f23 2549 #define BF_DMA_INT_INT7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7)
mbed_official 324:406fd2029f23 2550
mbed_official 324:406fd2029f23 2551 /*! @brief Set the INT7 field to a new value. */
mbed_official 324:406fd2029f23 2552 #define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
mbed_official 324:406fd2029f23 2553 /*@}*/
mbed_official 324:406fd2029f23 2554
mbed_official 324:406fd2029f23 2555 /*!
mbed_official 324:406fd2029f23 2556 * @name Register DMA_INT, field INT8[8] (W1C)
mbed_official 324:406fd2029f23 2557 *
mbed_official 324:406fd2029f23 2558 * Values:
mbed_official 324:406fd2029f23 2559 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2560 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2561 */
mbed_official 324:406fd2029f23 2562 /*@{*/
mbed_official 324:406fd2029f23 2563 #define BP_DMA_INT_INT8 (8U) /*!< Bit position for DMA_INT_INT8. */
mbed_official 324:406fd2029f23 2564 #define BM_DMA_INT_INT8 (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */
mbed_official 324:406fd2029f23 2565 #define BS_DMA_INT_INT8 (1U) /*!< Bit field size in bits for DMA_INT_INT8. */
mbed_official 324:406fd2029f23 2566
mbed_official 324:406fd2029f23 2567 /*! @brief Read current value of the DMA_INT_INT8 field. */
mbed_official 324:406fd2029f23 2568 #define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
mbed_official 324:406fd2029f23 2569
mbed_official 324:406fd2029f23 2570 /*! @brief Format value for bitfield DMA_INT_INT8. */
mbed_official 324:406fd2029f23 2571 #define BF_DMA_INT_INT8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8)
mbed_official 324:406fd2029f23 2572
mbed_official 324:406fd2029f23 2573 /*! @brief Set the INT8 field to a new value. */
mbed_official 324:406fd2029f23 2574 #define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
mbed_official 324:406fd2029f23 2575 /*@}*/
mbed_official 324:406fd2029f23 2576
mbed_official 324:406fd2029f23 2577 /*!
mbed_official 324:406fd2029f23 2578 * @name Register DMA_INT, field INT9[9] (W1C)
mbed_official 324:406fd2029f23 2579 *
mbed_official 324:406fd2029f23 2580 * Values:
mbed_official 324:406fd2029f23 2581 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2582 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2583 */
mbed_official 324:406fd2029f23 2584 /*@{*/
mbed_official 324:406fd2029f23 2585 #define BP_DMA_INT_INT9 (9U) /*!< Bit position for DMA_INT_INT9. */
mbed_official 324:406fd2029f23 2586 #define BM_DMA_INT_INT9 (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */
mbed_official 324:406fd2029f23 2587 #define BS_DMA_INT_INT9 (1U) /*!< Bit field size in bits for DMA_INT_INT9. */
mbed_official 324:406fd2029f23 2588
mbed_official 324:406fd2029f23 2589 /*! @brief Read current value of the DMA_INT_INT9 field. */
mbed_official 324:406fd2029f23 2590 #define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
mbed_official 324:406fd2029f23 2591
mbed_official 324:406fd2029f23 2592 /*! @brief Format value for bitfield DMA_INT_INT9. */
mbed_official 324:406fd2029f23 2593 #define BF_DMA_INT_INT9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9)
mbed_official 324:406fd2029f23 2594
mbed_official 324:406fd2029f23 2595 /*! @brief Set the INT9 field to a new value. */
mbed_official 324:406fd2029f23 2596 #define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
mbed_official 324:406fd2029f23 2597 /*@}*/
mbed_official 324:406fd2029f23 2598
mbed_official 324:406fd2029f23 2599 /*!
mbed_official 324:406fd2029f23 2600 * @name Register DMA_INT, field INT10[10] (W1C)
mbed_official 324:406fd2029f23 2601 *
mbed_official 324:406fd2029f23 2602 * Values:
mbed_official 324:406fd2029f23 2603 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2604 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2605 */
mbed_official 324:406fd2029f23 2606 /*@{*/
mbed_official 324:406fd2029f23 2607 #define BP_DMA_INT_INT10 (10U) /*!< Bit position for DMA_INT_INT10. */
mbed_official 324:406fd2029f23 2608 #define BM_DMA_INT_INT10 (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */
mbed_official 324:406fd2029f23 2609 #define BS_DMA_INT_INT10 (1U) /*!< Bit field size in bits for DMA_INT_INT10. */
mbed_official 324:406fd2029f23 2610
mbed_official 324:406fd2029f23 2611 /*! @brief Read current value of the DMA_INT_INT10 field. */
mbed_official 324:406fd2029f23 2612 #define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
mbed_official 324:406fd2029f23 2613
mbed_official 324:406fd2029f23 2614 /*! @brief Format value for bitfield DMA_INT_INT10. */
mbed_official 324:406fd2029f23 2615 #define BF_DMA_INT_INT10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10)
mbed_official 324:406fd2029f23 2616
mbed_official 324:406fd2029f23 2617 /*! @brief Set the INT10 field to a new value. */
mbed_official 324:406fd2029f23 2618 #define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
mbed_official 324:406fd2029f23 2619 /*@}*/
mbed_official 324:406fd2029f23 2620
mbed_official 324:406fd2029f23 2621 /*!
mbed_official 324:406fd2029f23 2622 * @name Register DMA_INT, field INT11[11] (W1C)
mbed_official 324:406fd2029f23 2623 *
mbed_official 324:406fd2029f23 2624 * Values:
mbed_official 324:406fd2029f23 2625 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2626 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2627 */
mbed_official 324:406fd2029f23 2628 /*@{*/
mbed_official 324:406fd2029f23 2629 #define BP_DMA_INT_INT11 (11U) /*!< Bit position for DMA_INT_INT11. */
mbed_official 324:406fd2029f23 2630 #define BM_DMA_INT_INT11 (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */
mbed_official 324:406fd2029f23 2631 #define BS_DMA_INT_INT11 (1U) /*!< Bit field size in bits for DMA_INT_INT11. */
mbed_official 324:406fd2029f23 2632
mbed_official 324:406fd2029f23 2633 /*! @brief Read current value of the DMA_INT_INT11 field. */
mbed_official 324:406fd2029f23 2634 #define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
mbed_official 324:406fd2029f23 2635
mbed_official 324:406fd2029f23 2636 /*! @brief Format value for bitfield DMA_INT_INT11. */
mbed_official 324:406fd2029f23 2637 #define BF_DMA_INT_INT11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11)
mbed_official 324:406fd2029f23 2638
mbed_official 324:406fd2029f23 2639 /*! @brief Set the INT11 field to a new value. */
mbed_official 324:406fd2029f23 2640 #define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
mbed_official 324:406fd2029f23 2641 /*@}*/
mbed_official 324:406fd2029f23 2642
mbed_official 324:406fd2029f23 2643 /*!
mbed_official 324:406fd2029f23 2644 * @name Register DMA_INT, field INT12[12] (W1C)
mbed_official 324:406fd2029f23 2645 *
mbed_official 324:406fd2029f23 2646 * Values:
mbed_official 324:406fd2029f23 2647 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2648 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2649 */
mbed_official 324:406fd2029f23 2650 /*@{*/
mbed_official 324:406fd2029f23 2651 #define BP_DMA_INT_INT12 (12U) /*!< Bit position for DMA_INT_INT12. */
mbed_official 324:406fd2029f23 2652 #define BM_DMA_INT_INT12 (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */
mbed_official 324:406fd2029f23 2653 #define BS_DMA_INT_INT12 (1U) /*!< Bit field size in bits for DMA_INT_INT12. */
mbed_official 324:406fd2029f23 2654
mbed_official 324:406fd2029f23 2655 /*! @brief Read current value of the DMA_INT_INT12 field. */
mbed_official 324:406fd2029f23 2656 #define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
mbed_official 324:406fd2029f23 2657
mbed_official 324:406fd2029f23 2658 /*! @brief Format value for bitfield DMA_INT_INT12. */
mbed_official 324:406fd2029f23 2659 #define BF_DMA_INT_INT12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12)
mbed_official 324:406fd2029f23 2660
mbed_official 324:406fd2029f23 2661 /*! @brief Set the INT12 field to a new value. */
mbed_official 324:406fd2029f23 2662 #define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
mbed_official 324:406fd2029f23 2663 /*@}*/
mbed_official 324:406fd2029f23 2664
mbed_official 324:406fd2029f23 2665 /*!
mbed_official 324:406fd2029f23 2666 * @name Register DMA_INT, field INT13[13] (W1C)
mbed_official 324:406fd2029f23 2667 *
mbed_official 324:406fd2029f23 2668 * Values:
mbed_official 324:406fd2029f23 2669 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2670 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2671 */
mbed_official 324:406fd2029f23 2672 /*@{*/
mbed_official 324:406fd2029f23 2673 #define BP_DMA_INT_INT13 (13U) /*!< Bit position for DMA_INT_INT13. */
mbed_official 324:406fd2029f23 2674 #define BM_DMA_INT_INT13 (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */
mbed_official 324:406fd2029f23 2675 #define BS_DMA_INT_INT13 (1U) /*!< Bit field size in bits for DMA_INT_INT13. */
mbed_official 324:406fd2029f23 2676
mbed_official 324:406fd2029f23 2677 /*! @brief Read current value of the DMA_INT_INT13 field. */
mbed_official 324:406fd2029f23 2678 #define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
mbed_official 324:406fd2029f23 2679
mbed_official 324:406fd2029f23 2680 /*! @brief Format value for bitfield DMA_INT_INT13. */
mbed_official 324:406fd2029f23 2681 #define BF_DMA_INT_INT13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13)
mbed_official 324:406fd2029f23 2682
mbed_official 324:406fd2029f23 2683 /*! @brief Set the INT13 field to a new value. */
mbed_official 324:406fd2029f23 2684 #define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
mbed_official 324:406fd2029f23 2685 /*@}*/
mbed_official 324:406fd2029f23 2686
mbed_official 324:406fd2029f23 2687 /*!
mbed_official 324:406fd2029f23 2688 * @name Register DMA_INT, field INT14[14] (W1C)
mbed_official 324:406fd2029f23 2689 *
mbed_official 324:406fd2029f23 2690 * Values:
mbed_official 324:406fd2029f23 2691 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2692 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2693 */
mbed_official 324:406fd2029f23 2694 /*@{*/
mbed_official 324:406fd2029f23 2695 #define BP_DMA_INT_INT14 (14U) /*!< Bit position for DMA_INT_INT14. */
mbed_official 324:406fd2029f23 2696 #define BM_DMA_INT_INT14 (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */
mbed_official 324:406fd2029f23 2697 #define BS_DMA_INT_INT14 (1U) /*!< Bit field size in bits for DMA_INT_INT14. */
mbed_official 324:406fd2029f23 2698
mbed_official 324:406fd2029f23 2699 /*! @brief Read current value of the DMA_INT_INT14 field. */
mbed_official 324:406fd2029f23 2700 #define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
mbed_official 324:406fd2029f23 2701
mbed_official 324:406fd2029f23 2702 /*! @brief Format value for bitfield DMA_INT_INT14. */
mbed_official 324:406fd2029f23 2703 #define BF_DMA_INT_INT14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14)
mbed_official 324:406fd2029f23 2704
mbed_official 324:406fd2029f23 2705 /*! @brief Set the INT14 field to a new value. */
mbed_official 324:406fd2029f23 2706 #define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
mbed_official 324:406fd2029f23 2707 /*@}*/
mbed_official 324:406fd2029f23 2708
mbed_official 324:406fd2029f23 2709 /*!
mbed_official 324:406fd2029f23 2710 * @name Register DMA_INT, field INT15[15] (W1C)
mbed_official 324:406fd2029f23 2711 *
mbed_official 324:406fd2029f23 2712 * Values:
mbed_official 324:406fd2029f23 2713 * - 0 - The interrupt request for corresponding channel is cleared
mbed_official 324:406fd2029f23 2714 * - 1 - The interrupt request for corresponding channel is active
mbed_official 324:406fd2029f23 2715 */
mbed_official 324:406fd2029f23 2716 /*@{*/
mbed_official 324:406fd2029f23 2717 #define BP_DMA_INT_INT15 (15U) /*!< Bit position for DMA_INT_INT15. */
mbed_official 324:406fd2029f23 2718 #define BM_DMA_INT_INT15 (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */
mbed_official 324:406fd2029f23 2719 #define BS_DMA_INT_INT15 (1U) /*!< Bit field size in bits for DMA_INT_INT15. */
mbed_official 324:406fd2029f23 2720
mbed_official 324:406fd2029f23 2721 /*! @brief Read current value of the DMA_INT_INT15 field. */
mbed_official 324:406fd2029f23 2722 #define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
mbed_official 324:406fd2029f23 2723
mbed_official 324:406fd2029f23 2724 /*! @brief Format value for bitfield DMA_INT_INT15. */
mbed_official 324:406fd2029f23 2725 #define BF_DMA_INT_INT15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15)
mbed_official 324:406fd2029f23 2726
mbed_official 324:406fd2029f23 2727 /*! @brief Set the INT15 field to a new value. */
mbed_official 324:406fd2029f23 2728 #define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
mbed_official 324:406fd2029f23 2729 /*@}*/
mbed_official 324:406fd2029f23 2730
mbed_official 324:406fd2029f23 2731 /*******************************************************************************
mbed_official 324:406fd2029f23 2732 * HW_DMA_ERR - Error Register
mbed_official 324:406fd2029f23 2733 ******************************************************************************/
mbed_official 324:406fd2029f23 2734
mbed_official 324:406fd2029f23 2735 /*!
mbed_official 324:406fd2029f23 2736 * @brief HW_DMA_ERR - Error Register (RW)
mbed_official 324:406fd2029f23 2737 *
mbed_official 324:406fd2029f23 2738 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 2739 *
mbed_official 324:406fd2029f23 2740 * The ERR provides a bit map for the 16 channels, signaling the presence of an
mbed_official 324:406fd2029f23 2741 * error for each channel. The eDMA engine signals the occurrence of an error
mbed_official 324:406fd2029f23 2742 * condition by setting the appropriate bit in this register. The outputs of this
mbed_official 324:406fd2029f23 2743 * register are enabled by the contents of the EEI, and then routed to the
mbed_official 324:406fd2029f23 2744 * interrupt controller. During the execution of the interrupt-service routine associated
mbed_official 324:406fd2029f23 2745 * with any DMA errors, it is software's responsibility to clear the appropriate
mbed_official 324:406fd2029f23 2746 * bit, negating the error-interrupt request. Typically, a write to the CERR in
mbed_official 324:406fd2029f23 2747 * the interrupt-service routine is used for this purpose. The normal DMA channel
mbed_official 324:406fd2029f23 2748 * completion indicators (setting the transfer control descriptor DONE flag and
mbed_official 324:406fd2029f23 2749 * the possible assertion of an interrupt request) are not affected when an error
mbed_official 324:406fd2029f23 2750 * is detected. The contents of this register can also be polled because a
mbed_official 324:406fd2029f23 2751 * non-zero value indicates the presence of a channel error regardless of the state of
mbed_official 324:406fd2029f23 2752 * the EEI. The state of any given channel's error indicators is affected by
mbed_official 324:406fd2029f23 2753 * writes to this register; it is also affected by writes to the CERR. On writes to
mbed_official 324:406fd2029f23 2754 * the ERR, a one in any bit position clears the corresponding channel's error
mbed_official 324:406fd2029f23 2755 * status. A zero in any bit position has no affect on the corresponding channel's
mbed_official 324:406fd2029f23 2756 * current error status. The CERR is provided so the error indicator for a single
mbed_official 324:406fd2029f23 2757 * channel can easily be cleared.
mbed_official 324:406fd2029f23 2758 */
mbed_official 324:406fd2029f23 2759 typedef union _hw_dma_err
mbed_official 324:406fd2029f23 2760 {
mbed_official 324:406fd2029f23 2761 uint32_t U;
mbed_official 324:406fd2029f23 2762 struct _hw_dma_err_bitfields
mbed_official 324:406fd2029f23 2763 {
mbed_official 324:406fd2029f23 2764 uint32_t ERR0 : 1; /*!< [0] Error In Channel 0 */
mbed_official 324:406fd2029f23 2765 uint32_t ERR1 : 1; /*!< [1] Error In Channel 1 */
mbed_official 324:406fd2029f23 2766 uint32_t ERR2 : 1; /*!< [2] Error In Channel 2 */
mbed_official 324:406fd2029f23 2767 uint32_t ERR3 : 1; /*!< [3] Error In Channel 3 */
mbed_official 324:406fd2029f23 2768 uint32_t ERR4 : 1; /*!< [4] Error In Channel 4 */
mbed_official 324:406fd2029f23 2769 uint32_t ERR5 : 1; /*!< [5] Error In Channel 5 */
mbed_official 324:406fd2029f23 2770 uint32_t ERR6 : 1; /*!< [6] Error In Channel 6 */
mbed_official 324:406fd2029f23 2771 uint32_t ERR7 : 1; /*!< [7] Error In Channel 7 */
mbed_official 324:406fd2029f23 2772 uint32_t ERR8 : 1; /*!< [8] Error In Channel 8 */
mbed_official 324:406fd2029f23 2773 uint32_t ERR9 : 1; /*!< [9] Error In Channel 9 */
mbed_official 324:406fd2029f23 2774 uint32_t ERR10 : 1; /*!< [10] Error In Channel 10 */
mbed_official 324:406fd2029f23 2775 uint32_t ERR11 : 1; /*!< [11] Error In Channel 11 */
mbed_official 324:406fd2029f23 2776 uint32_t ERR12 : 1; /*!< [12] Error In Channel 12 */
mbed_official 324:406fd2029f23 2777 uint32_t ERR13 : 1; /*!< [13] Error In Channel 13 */
mbed_official 324:406fd2029f23 2778 uint32_t ERR14 : 1; /*!< [14] Error In Channel 14 */
mbed_official 324:406fd2029f23 2779 uint32_t ERR15 : 1; /*!< [15] Error In Channel 15 */
mbed_official 324:406fd2029f23 2780 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 2781 } B;
mbed_official 324:406fd2029f23 2782 } hw_dma_err_t;
mbed_official 324:406fd2029f23 2783
mbed_official 324:406fd2029f23 2784 /*!
mbed_official 324:406fd2029f23 2785 * @name Constants and macros for entire DMA_ERR register
mbed_official 324:406fd2029f23 2786 */
mbed_official 324:406fd2029f23 2787 /*@{*/
mbed_official 324:406fd2029f23 2788 #define HW_DMA_ERR_ADDR(x) ((x) + 0x2CU)
mbed_official 324:406fd2029f23 2789
mbed_official 324:406fd2029f23 2790 #define HW_DMA_ERR(x) (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
mbed_official 324:406fd2029f23 2791 #define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
mbed_official 324:406fd2029f23 2792 #define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
mbed_official 324:406fd2029f23 2793 #define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) | (v)))
mbed_official 324:406fd2029f23 2794 #define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2795 #define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2796 /*@}*/
mbed_official 324:406fd2029f23 2797
mbed_official 324:406fd2029f23 2798 /*
mbed_official 324:406fd2029f23 2799 * Constants & macros for individual DMA_ERR bitfields
mbed_official 324:406fd2029f23 2800 */
mbed_official 324:406fd2029f23 2801
mbed_official 324:406fd2029f23 2802 /*!
mbed_official 324:406fd2029f23 2803 * @name Register DMA_ERR, field ERR0[0] (W1C)
mbed_official 324:406fd2029f23 2804 *
mbed_official 324:406fd2029f23 2805 * Values:
mbed_official 324:406fd2029f23 2806 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2807 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2808 */
mbed_official 324:406fd2029f23 2809 /*@{*/
mbed_official 324:406fd2029f23 2810 #define BP_DMA_ERR_ERR0 (0U) /*!< Bit position for DMA_ERR_ERR0. */
mbed_official 324:406fd2029f23 2811 #define BM_DMA_ERR_ERR0 (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */
mbed_official 324:406fd2029f23 2812 #define BS_DMA_ERR_ERR0 (1U) /*!< Bit field size in bits for DMA_ERR_ERR0. */
mbed_official 324:406fd2029f23 2813
mbed_official 324:406fd2029f23 2814 /*! @brief Read current value of the DMA_ERR_ERR0 field. */
mbed_official 324:406fd2029f23 2815 #define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
mbed_official 324:406fd2029f23 2816
mbed_official 324:406fd2029f23 2817 /*! @brief Format value for bitfield DMA_ERR_ERR0. */
mbed_official 324:406fd2029f23 2818 #define BF_DMA_ERR_ERR0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0)
mbed_official 324:406fd2029f23 2819
mbed_official 324:406fd2029f23 2820 /*! @brief Set the ERR0 field to a new value. */
mbed_official 324:406fd2029f23 2821 #define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
mbed_official 324:406fd2029f23 2822 /*@}*/
mbed_official 324:406fd2029f23 2823
mbed_official 324:406fd2029f23 2824 /*!
mbed_official 324:406fd2029f23 2825 * @name Register DMA_ERR, field ERR1[1] (W1C)
mbed_official 324:406fd2029f23 2826 *
mbed_official 324:406fd2029f23 2827 * Values:
mbed_official 324:406fd2029f23 2828 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2829 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2830 */
mbed_official 324:406fd2029f23 2831 /*@{*/
mbed_official 324:406fd2029f23 2832 #define BP_DMA_ERR_ERR1 (1U) /*!< Bit position for DMA_ERR_ERR1. */
mbed_official 324:406fd2029f23 2833 #define BM_DMA_ERR_ERR1 (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */
mbed_official 324:406fd2029f23 2834 #define BS_DMA_ERR_ERR1 (1U) /*!< Bit field size in bits for DMA_ERR_ERR1. */
mbed_official 324:406fd2029f23 2835
mbed_official 324:406fd2029f23 2836 /*! @brief Read current value of the DMA_ERR_ERR1 field. */
mbed_official 324:406fd2029f23 2837 #define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
mbed_official 324:406fd2029f23 2838
mbed_official 324:406fd2029f23 2839 /*! @brief Format value for bitfield DMA_ERR_ERR1. */
mbed_official 324:406fd2029f23 2840 #define BF_DMA_ERR_ERR1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1)
mbed_official 324:406fd2029f23 2841
mbed_official 324:406fd2029f23 2842 /*! @brief Set the ERR1 field to a new value. */
mbed_official 324:406fd2029f23 2843 #define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
mbed_official 324:406fd2029f23 2844 /*@}*/
mbed_official 324:406fd2029f23 2845
mbed_official 324:406fd2029f23 2846 /*!
mbed_official 324:406fd2029f23 2847 * @name Register DMA_ERR, field ERR2[2] (W1C)
mbed_official 324:406fd2029f23 2848 *
mbed_official 324:406fd2029f23 2849 * Values:
mbed_official 324:406fd2029f23 2850 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2851 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2852 */
mbed_official 324:406fd2029f23 2853 /*@{*/
mbed_official 324:406fd2029f23 2854 #define BP_DMA_ERR_ERR2 (2U) /*!< Bit position for DMA_ERR_ERR2. */
mbed_official 324:406fd2029f23 2855 #define BM_DMA_ERR_ERR2 (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */
mbed_official 324:406fd2029f23 2856 #define BS_DMA_ERR_ERR2 (1U) /*!< Bit field size in bits for DMA_ERR_ERR2. */
mbed_official 324:406fd2029f23 2857
mbed_official 324:406fd2029f23 2858 /*! @brief Read current value of the DMA_ERR_ERR2 field. */
mbed_official 324:406fd2029f23 2859 #define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
mbed_official 324:406fd2029f23 2860
mbed_official 324:406fd2029f23 2861 /*! @brief Format value for bitfield DMA_ERR_ERR2. */
mbed_official 324:406fd2029f23 2862 #define BF_DMA_ERR_ERR2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2)
mbed_official 324:406fd2029f23 2863
mbed_official 324:406fd2029f23 2864 /*! @brief Set the ERR2 field to a new value. */
mbed_official 324:406fd2029f23 2865 #define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
mbed_official 324:406fd2029f23 2866 /*@}*/
mbed_official 324:406fd2029f23 2867
mbed_official 324:406fd2029f23 2868 /*!
mbed_official 324:406fd2029f23 2869 * @name Register DMA_ERR, field ERR3[3] (W1C)
mbed_official 324:406fd2029f23 2870 *
mbed_official 324:406fd2029f23 2871 * Values:
mbed_official 324:406fd2029f23 2872 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2873 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2874 */
mbed_official 324:406fd2029f23 2875 /*@{*/
mbed_official 324:406fd2029f23 2876 #define BP_DMA_ERR_ERR3 (3U) /*!< Bit position for DMA_ERR_ERR3. */
mbed_official 324:406fd2029f23 2877 #define BM_DMA_ERR_ERR3 (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */
mbed_official 324:406fd2029f23 2878 #define BS_DMA_ERR_ERR3 (1U) /*!< Bit field size in bits for DMA_ERR_ERR3. */
mbed_official 324:406fd2029f23 2879
mbed_official 324:406fd2029f23 2880 /*! @brief Read current value of the DMA_ERR_ERR3 field. */
mbed_official 324:406fd2029f23 2881 #define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
mbed_official 324:406fd2029f23 2882
mbed_official 324:406fd2029f23 2883 /*! @brief Format value for bitfield DMA_ERR_ERR3. */
mbed_official 324:406fd2029f23 2884 #define BF_DMA_ERR_ERR3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3)
mbed_official 324:406fd2029f23 2885
mbed_official 324:406fd2029f23 2886 /*! @brief Set the ERR3 field to a new value. */
mbed_official 324:406fd2029f23 2887 #define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
mbed_official 324:406fd2029f23 2888 /*@}*/
mbed_official 324:406fd2029f23 2889
mbed_official 324:406fd2029f23 2890 /*!
mbed_official 324:406fd2029f23 2891 * @name Register DMA_ERR, field ERR4[4] (W1C)
mbed_official 324:406fd2029f23 2892 *
mbed_official 324:406fd2029f23 2893 * Values:
mbed_official 324:406fd2029f23 2894 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2895 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2896 */
mbed_official 324:406fd2029f23 2897 /*@{*/
mbed_official 324:406fd2029f23 2898 #define BP_DMA_ERR_ERR4 (4U) /*!< Bit position for DMA_ERR_ERR4. */
mbed_official 324:406fd2029f23 2899 #define BM_DMA_ERR_ERR4 (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */
mbed_official 324:406fd2029f23 2900 #define BS_DMA_ERR_ERR4 (1U) /*!< Bit field size in bits for DMA_ERR_ERR4. */
mbed_official 324:406fd2029f23 2901
mbed_official 324:406fd2029f23 2902 /*! @brief Read current value of the DMA_ERR_ERR4 field. */
mbed_official 324:406fd2029f23 2903 #define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
mbed_official 324:406fd2029f23 2904
mbed_official 324:406fd2029f23 2905 /*! @brief Format value for bitfield DMA_ERR_ERR4. */
mbed_official 324:406fd2029f23 2906 #define BF_DMA_ERR_ERR4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4)
mbed_official 324:406fd2029f23 2907
mbed_official 324:406fd2029f23 2908 /*! @brief Set the ERR4 field to a new value. */
mbed_official 324:406fd2029f23 2909 #define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
mbed_official 324:406fd2029f23 2910 /*@}*/
mbed_official 324:406fd2029f23 2911
mbed_official 324:406fd2029f23 2912 /*!
mbed_official 324:406fd2029f23 2913 * @name Register DMA_ERR, field ERR5[5] (W1C)
mbed_official 324:406fd2029f23 2914 *
mbed_official 324:406fd2029f23 2915 * Values:
mbed_official 324:406fd2029f23 2916 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2917 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2918 */
mbed_official 324:406fd2029f23 2919 /*@{*/
mbed_official 324:406fd2029f23 2920 #define BP_DMA_ERR_ERR5 (5U) /*!< Bit position for DMA_ERR_ERR5. */
mbed_official 324:406fd2029f23 2921 #define BM_DMA_ERR_ERR5 (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */
mbed_official 324:406fd2029f23 2922 #define BS_DMA_ERR_ERR5 (1U) /*!< Bit field size in bits for DMA_ERR_ERR5. */
mbed_official 324:406fd2029f23 2923
mbed_official 324:406fd2029f23 2924 /*! @brief Read current value of the DMA_ERR_ERR5 field. */
mbed_official 324:406fd2029f23 2925 #define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
mbed_official 324:406fd2029f23 2926
mbed_official 324:406fd2029f23 2927 /*! @brief Format value for bitfield DMA_ERR_ERR5. */
mbed_official 324:406fd2029f23 2928 #define BF_DMA_ERR_ERR5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5)
mbed_official 324:406fd2029f23 2929
mbed_official 324:406fd2029f23 2930 /*! @brief Set the ERR5 field to a new value. */
mbed_official 324:406fd2029f23 2931 #define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
mbed_official 324:406fd2029f23 2932 /*@}*/
mbed_official 324:406fd2029f23 2933
mbed_official 324:406fd2029f23 2934 /*!
mbed_official 324:406fd2029f23 2935 * @name Register DMA_ERR, field ERR6[6] (W1C)
mbed_official 324:406fd2029f23 2936 *
mbed_official 324:406fd2029f23 2937 * Values:
mbed_official 324:406fd2029f23 2938 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2939 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2940 */
mbed_official 324:406fd2029f23 2941 /*@{*/
mbed_official 324:406fd2029f23 2942 #define BP_DMA_ERR_ERR6 (6U) /*!< Bit position for DMA_ERR_ERR6. */
mbed_official 324:406fd2029f23 2943 #define BM_DMA_ERR_ERR6 (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */
mbed_official 324:406fd2029f23 2944 #define BS_DMA_ERR_ERR6 (1U) /*!< Bit field size in bits for DMA_ERR_ERR6. */
mbed_official 324:406fd2029f23 2945
mbed_official 324:406fd2029f23 2946 /*! @brief Read current value of the DMA_ERR_ERR6 field. */
mbed_official 324:406fd2029f23 2947 #define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
mbed_official 324:406fd2029f23 2948
mbed_official 324:406fd2029f23 2949 /*! @brief Format value for bitfield DMA_ERR_ERR6. */
mbed_official 324:406fd2029f23 2950 #define BF_DMA_ERR_ERR6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6)
mbed_official 324:406fd2029f23 2951
mbed_official 324:406fd2029f23 2952 /*! @brief Set the ERR6 field to a new value. */
mbed_official 324:406fd2029f23 2953 #define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
mbed_official 324:406fd2029f23 2954 /*@}*/
mbed_official 324:406fd2029f23 2955
mbed_official 324:406fd2029f23 2956 /*!
mbed_official 324:406fd2029f23 2957 * @name Register DMA_ERR, field ERR7[7] (W1C)
mbed_official 324:406fd2029f23 2958 *
mbed_official 324:406fd2029f23 2959 * Values:
mbed_official 324:406fd2029f23 2960 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2961 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2962 */
mbed_official 324:406fd2029f23 2963 /*@{*/
mbed_official 324:406fd2029f23 2964 #define BP_DMA_ERR_ERR7 (7U) /*!< Bit position for DMA_ERR_ERR7. */
mbed_official 324:406fd2029f23 2965 #define BM_DMA_ERR_ERR7 (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */
mbed_official 324:406fd2029f23 2966 #define BS_DMA_ERR_ERR7 (1U) /*!< Bit field size in bits for DMA_ERR_ERR7. */
mbed_official 324:406fd2029f23 2967
mbed_official 324:406fd2029f23 2968 /*! @brief Read current value of the DMA_ERR_ERR7 field. */
mbed_official 324:406fd2029f23 2969 #define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
mbed_official 324:406fd2029f23 2970
mbed_official 324:406fd2029f23 2971 /*! @brief Format value for bitfield DMA_ERR_ERR7. */
mbed_official 324:406fd2029f23 2972 #define BF_DMA_ERR_ERR7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7)
mbed_official 324:406fd2029f23 2973
mbed_official 324:406fd2029f23 2974 /*! @brief Set the ERR7 field to a new value. */
mbed_official 324:406fd2029f23 2975 #define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
mbed_official 324:406fd2029f23 2976 /*@}*/
mbed_official 324:406fd2029f23 2977
mbed_official 324:406fd2029f23 2978 /*!
mbed_official 324:406fd2029f23 2979 * @name Register DMA_ERR, field ERR8[8] (W1C)
mbed_official 324:406fd2029f23 2980 *
mbed_official 324:406fd2029f23 2981 * Values:
mbed_official 324:406fd2029f23 2982 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 2983 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 2984 */
mbed_official 324:406fd2029f23 2985 /*@{*/
mbed_official 324:406fd2029f23 2986 #define BP_DMA_ERR_ERR8 (8U) /*!< Bit position for DMA_ERR_ERR8. */
mbed_official 324:406fd2029f23 2987 #define BM_DMA_ERR_ERR8 (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */
mbed_official 324:406fd2029f23 2988 #define BS_DMA_ERR_ERR8 (1U) /*!< Bit field size in bits for DMA_ERR_ERR8. */
mbed_official 324:406fd2029f23 2989
mbed_official 324:406fd2029f23 2990 /*! @brief Read current value of the DMA_ERR_ERR8 field. */
mbed_official 324:406fd2029f23 2991 #define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
mbed_official 324:406fd2029f23 2992
mbed_official 324:406fd2029f23 2993 /*! @brief Format value for bitfield DMA_ERR_ERR8. */
mbed_official 324:406fd2029f23 2994 #define BF_DMA_ERR_ERR8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8)
mbed_official 324:406fd2029f23 2995
mbed_official 324:406fd2029f23 2996 /*! @brief Set the ERR8 field to a new value. */
mbed_official 324:406fd2029f23 2997 #define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
mbed_official 324:406fd2029f23 2998 /*@}*/
mbed_official 324:406fd2029f23 2999
mbed_official 324:406fd2029f23 3000 /*!
mbed_official 324:406fd2029f23 3001 * @name Register DMA_ERR, field ERR9[9] (W1C)
mbed_official 324:406fd2029f23 3002 *
mbed_official 324:406fd2029f23 3003 * Values:
mbed_official 324:406fd2029f23 3004 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3005 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3006 */
mbed_official 324:406fd2029f23 3007 /*@{*/
mbed_official 324:406fd2029f23 3008 #define BP_DMA_ERR_ERR9 (9U) /*!< Bit position for DMA_ERR_ERR9. */
mbed_official 324:406fd2029f23 3009 #define BM_DMA_ERR_ERR9 (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */
mbed_official 324:406fd2029f23 3010 #define BS_DMA_ERR_ERR9 (1U) /*!< Bit field size in bits for DMA_ERR_ERR9. */
mbed_official 324:406fd2029f23 3011
mbed_official 324:406fd2029f23 3012 /*! @brief Read current value of the DMA_ERR_ERR9 field. */
mbed_official 324:406fd2029f23 3013 #define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
mbed_official 324:406fd2029f23 3014
mbed_official 324:406fd2029f23 3015 /*! @brief Format value for bitfield DMA_ERR_ERR9. */
mbed_official 324:406fd2029f23 3016 #define BF_DMA_ERR_ERR9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9)
mbed_official 324:406fd2029f23 3017
mbed_official 324:406fd2029f23 3018 /*! @brief Set the ERR9 field to a new value. */
mbed_official 324:406fd2029f23 3019 #define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
mbed_official 324:406fd2029f23 3020 /*@}*/
mbed_official 324:406fd2029f23 3021
mbed_official 324:406fd2029f23 3022 /*!
mbed_official 324:406fd2029f23 3023 * @name Register DMA_ERR, field ERR10[10] (W1C)
mbed_official 324:406fd2029f23 3024 *
mbed_official 324:406fd2029f23 3025 * Values:
mbed_official 324:406fd2029f23 3026 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3027 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3028 */
mbed_official 324:406fd2029f23 3029 /*@{*/
mbed_official 324:406fd2029f23 3030 #define BP_DMA_ERR_ERR10 (10U) /*!< Bit position for DMA_ERR_ERR10. */
mbed_official 324:406fd2029f23 3031 #define BM_DMA_ERR_ERR10 (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */
mbed_official 324:406fd2029f23 3032 #define BS_DMA_ERR_ERR10 (1U) /*!< Bit field size in bits for DMA_ERR_ERR10. */
mbed_official 324:406fd2029f23 3033
mbed_official 324:406fd2029f23 3034 /*! @brief Read current value of the DMA_ERR_ERR10 field. */
mbed_official 324:406fd2029f23 3035 #define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
mbed_official 324:406fd2029f23 3036
mbed_official 324:406fd2029f23 3037 /*! @brief Format value for bitfield DMA_ERR_ERR10. */
mbed_official 324:406fd2029f23 3038 #define BF_DMA_ERR_ERR10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10)
mbed_official 324:406fd2029f23 3039
mbed_official 324:406fd2029f23 3040 /*! @brief Set the ERR10 field to a new value. */
mbed_official 324:406fd2029f23 3041 #define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
mbed_official 324:406fd2029f23 3042 /*@}*/
mbed_official 324:406fd2029f23 3043
mbed_official 324:406fd2029f23 3044 /*!
mbed_official 324:406fd2029f23 3045 * @name Register DMA_ERR, field ERR11[11] (W1C)
mbed_official 324:406fd2029f23 3046 *
mbed_official 324:406fd2029f23 3047 * Values:
mbed_official 324:406fd2029f23 3048 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3049 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3050 */
mbed_official 324:406fd2029f23 3051 /*@{*/
mbed_official 324:406fd2029f23 3052 #define BP_DMA_ERR_ERR11 (11U) /*!< Bit position for DMA_ERR_ERR11. */
mbed_official 324:406fd2029f23 3053 #define BM_DMA_ERR_ERR11 (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */
mbed_official 324:406fd2029f23 3054 #define BS_DMA_ERR_ERR11 (1U) /*!< Bit field size in bits for DMA_ERR_ERR11. */
mbed_official 324:406fd2029f23 3055
mbed_official 324:406fd2029f23 3056 /*! @brief Read current value of the DMA_ERR_ERR11 field. */
mbed_official 324:406fd2029f23 3057 #define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
mbed_official 324:406fd2029f23 3058
mbed_official 324:406fd2029f23 3059 /*! @brief Format value for bitfield DMA_ERR_ERR11. */
mbed_official 324:406fd2029f23 3060 #define BF_DMA_ERR_ERR11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11)
mbed_official 324:406fd2029f23 3061
mbed_official 324:406fd2029f23 3062 /*! @brief Set the ERR11 field to a new value. */
mbed_official 324:406fd2029f23 3063 #define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
mbed_official 324:406fd2029f23 3064 /*@}*/
mbed_official 324:406fd2029f23 3065
mbed_official 324:406fd2029f23 3066 /*!
mbed_official 324:406fd2029f23 3067 * @name Register DMA_ERR, field ERR12[12] (W1C)
mbed_official 324:406fd2029f23 3068 *
mbed_official 324:406fd2029f23 3069 * Values:
mbed_official 324:406fd2029f23 3070 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3071 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3072 */
mbed_official 324:406fd2029f23 3073 /*@{*/
mbed_official 324:406fd2029f23 3074 #define BP_DMA_ERR_ERR12 (12U) /*!< Bit position for DMA_ERR_ERR12. */
mbed_official 324:406fd2029f23 3075 #define BM_DMA_ERR_ERR12 (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */
mbed_official 324:406fd2029f23 3076 #define BS_DMA_ERR_ERR12 (1U) /*!< Bit field size in bits for DMA_ERR_ERR12. */
mbed_official 324:406fd2029f23 3077
mbed_official 324:406fd2029f23 3078 /*! @brief Read current value of the DMA_ERR_ERR12 field. */
mbed_official 324:406fd2029f23 3079 #define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
mbed_official 324:406fd2029f23 3080
mbed_official 324:406fd2029f23 3081 /*! @brief Format value for bitfield DMA_ERR_ERR12. */
mbed_official 324:406fd2029f23 3082 #define BF_DMA_ERR_ERR12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12)
mbed_official 324:406fd2029f23 3083
mbed_official 324:406fd2029f23 3084 /*! @brief Set the ERR12 field to a new value. */
mbed_official 324:406fd2029f23 3085 #define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
mbed_official 324:406fd2029f23 3086 /*@}*/
mbed_official 324:406fd2029f23 3087
mbed_official 324:406fd2029f23 3088 /*!
mbed_official 324:406fd2029f23 3089 * @name Register DMA_ERR, field ERR13[13] (W1C)
mbed_official 324:406fd2029f23 3090 *
mbed_official 324:406fd2029f23 3091 * Values:
mbed_official 324:406fd2029f23 3092 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3093 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3094 */
mbed_official 324:406fd2029f23 3095 /*@{*/
mbed_official 324:406fd2029f23 3096 #define BP_DMA_ERR_ERR13 (13U) /*!< Bit position for DMA_ERR_ERR13. */
mbed_official 324:406fd2029f23 3097 #define BM_DMA_ERR_ERR13 (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */
mbed_official 324:406fd2029f23 3098 #define BS_DMA_ERR_ERR13 (1U) /*!< Bit field size in bits for DMA_ERR_ERR13. */
mbed_official 324:406fd2029f23 3099
mbed_official 324:406fd2029f23 3100 /*! @brief Read current value of the DMA_ERR_ERR13 field. */
mbed_official 324:406fd2029f23 3101 #define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
mbed_official 324:406fd2029f23 3102
mbed_official 324:406fd2029f23 3103 /*! @brief Format value for bitfield DMA_ERR_ERR13. */
mbed_official 324:406fd2029f23 3104 #define BF_DMA_ERR_ERR13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13)
mbed_official 324:406fd2029f23 3105
mbed_official 324:406fd2029f23 3106 /*! @brief Set the ERR13 field to a new value. */
mbed_official 324:406fd2029f23 3107 #define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
mbed_official 324:406fd2029f23 3108 /*@}*/
mbed_official 324:406fd2029f23 3109
mbed_official 324:406fd2029f23 3110 /*!
mbed_official 324:406fd2029f23 3111 * @name Register DMA_ERR, field ERR14[14] (W1C)
mbed_official 324:406fd2029f23 3112 *
mbed_official 324:406fd2029f23 3113 * Values:
mbed_official 324:406fd2029f23 3114 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3115 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3116 */
mbed_official 324:406fd2029f23 3117 /*@{*/
mbed_official 324:406fd2029f23 3118 #define BP_DMA_ERR_ERR14 (14U) /*!< Bit position for DMA_ERR_ERR14. */
mbed_official 324:406fd2029f23 3119 #define BM_DMA_ERR_ERR14 (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */
mbed_official 324:406fd2029f23 3120 #define BS_DMA_ERR_ERR14 (1U) /*!< Bit field size in bits for DMA_ERR_ERR14. */
mbed_official 324:406fd2029f23 3121
mbed_official 324:406fd2029f23 3122 /*! @brief Read current value of the DMA_ERR_ERR14 field. */
mbed_official 324:406fd2029f23 3123 #define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
mbed_official 324:406fd2029f23 3124
mbed_official 324:406fd2029f23 3125 /*! @brief Format value for bitfield DMA_ERR_ERR14. */
mbed_official 324:406fd2029f23 3126 #define BF_DMA_ERR_ERR14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14)
mbed_official 324:406fd2029f23 3127
mbed_official 324:406fd2029f23 3128 /*! @brief Set the ERR14 field to a new value. */
mbed_official 324:406fd2029f23 3129 #define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
mbed_official 324:406fd2029f23 3130 /*@}*/
mbed_official 324:406fd2029f23 3131
mbed_official 324:406fd2029f23 3132 /*!
mbed_official 324:406fd2029f23 3133 * @name Register DMA_ERR, field ERR15[15] (W1C)
mbed_official 324:406fd2029f23 3134 *
mbed_official 324:406fd2029f23 3135 * Values:
mbed_official 324:406fd2029f23 3136 * - 0 - An error in the corresponding channel has not occurred
mbed_official 324:406fd2029f23 3137 * - 1 - An error in the corresponding channel has occurred
mbed_official 324:406fd2029f23 3138 */
mbed_official 324:406fd2029f23 3139 /*@{*/
mbed_official 324:406fd2029f23 3140 #define BP_DMA_ERR_ERR15 (15U) /*!< Bit position for DMA_ERR_ERR15. */
mbed_official 324:406fd2029f23 3141 #define BM_DMA_ERR_ERR15 (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */
mbed_official 324:406fd2029f23 3142 #define BS_DMA_ERR_ERR15 (1U) /*!< Bit field size in bits for DMA_ERR_ERR15. */
mbed_official 324:406fd2029f23 3143
mbed_official 324:406fd2029f23 3144 /*! @brief Read current value of the DMA_ERR_ERR15 field. */
mbed_official 324:406fd2029f23 3145 #define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
mbed_official 324:406fd2029f23 3146
mbed_official 324:406fd2029f23 3147 /*! @brief Format value for bitfield DMA_ERR_ERR15. */
mbed_official 324:406fd2029f23 3148 #define BF_DMA_ERR_ERR15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15)
mbed_official 324:406fd2029f23 3149
mbed_official 324:406fd2029f23 3150 /*! @brief Set the ERR15 field to a new value. */
mbed_official 324:406fd2029f23 3151 #define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
mbed_official 324:406fd2029f23 3152 /*@}*/
mbed_official 324:406fd2029f23 3153
mbed_official 324:406fd2029f23 3154 /*******************************************************************************
mbed_official 324:406fd2029f23 3155 * HW_DMA_HRS - Hardware Request Status Register
mbed_official 324:406fd2029f23 3156 ******************************************************************************/
mbed_official 324:406fd2029f23 3157
mbed_official 324:406fd2029f23 3158 /*!
mbed_official 324:406fd2029f23 3159 * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
mbed_official 324:406fd2029f23 3160 *
mbed_official 324:406fd2029f23 3161 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3162 *
mbed_official 324:406fd2029f23 3163 * The HRS register provides a bit map for the DMA channels, signaling the
mbed_official 324:406fd2029f23 3164 * presence of a hardware request for each channel. The hardware request status bits
mbed_official 324:406fd2029f23 3165 * reflect the current state of the register and qualified (via the ERQ fields)
mbed_official 324:406fd2029f23 3166 * DMA request signals as seen by the DMA's arbitration logic. This view into the
mbed_official 324:406fd2029f23 3167 * hardware request signals may be used for debug purposes. These bits reflect the
mbed_official 324:406fd2029f23 3168 * state of the request as seen by the arbitration logic. Therefore, this status
mbed_official 324:406fd2029f23 3169 * is affected by the ERQ bits.
mbed_official 324:406fd2029f23 3170 */
mbed_official 324:406fd2029f23 3171 typedef union _hw_dma_hrs
mbed_official 324:406fd2029f23 3172 {
mbed_official 324:406fd2029f23 3173 uint32_t U;
mbed_official 324:406fd2029f23 3174 struct _hw_dma_hrs_bitfields
mbed_official 324:406fd2029f23 3175 {
mbed_official 324:406fd2029f23 3176 uint32_t HRS0 : 1; /*!< [0] Hardware Request Status Channel 0 */
mbed_official 324:406fd2029f23 3177 uint32_t HRS1 : 1; /*!< [1] Hardware Request Status Channel 1 */
mbed_official 324:406fd2029f23 3178 uint32_t HRS2 : 1; /*!< [2] Hardware Request Status Channel 2 */
mbed_official 324:406fd2029f23 3179 uint32_t HRS3 : 1; /*!< [3] Hardware Request Status Channel 3 */
mbed_official 324:406fd2029f23 3180 uint32_t HRS4 : 1; /*!< [4] Hardware Request Status Channel 4 */
mbed_official 324:406fd2029f23 3181 uint32_t HRS5 : 1; /*!< [5] Hardware Request Status Channel 5 */
mbed_official 324:406fd2029f23 3182 uint32_t HRS6 : 1; /*!< [6] Hardware Request Status Channel 6 */
mbed_official 324:406fd2029f23 3183 uint32_t HRS7 : 1; /*!< [7] Hardware Request Status Channel 7 */
mbed_official 324:406fd2029f23 3184 uint32_t HRS8 : 1; /*!< [8] Hardware Request Status Channel 8 */
mbed_official 324:406fd2029f23 3185 uint32_t HRS9 : 1; /*!< [9] Hardware Request Status Channel 9 */
mbed_official 324:406fd2029f23 3186 uint32_t HRS10 : 1; /*!< [10] Hardware Request Status Channel 10 */
mbed_official 324:406fd2029f23 3187 uint32_t HRS11 : 1; /*!< [11] Hardware Request Status Channel 11 */
mbed_official 324:406fd2029f23 3188 uint32_t HRS12 : 1; /*!< [12] Hardware Request Status Channel 12 */
mbed_official 324:406fd2029f23 3189 uint32_t HRS13 : 1; /*!< [13] Hardware Request Status Channel 13 */
mbed_official 324:406fd2029f23 3190 uint32_t HRS14 : 1; /*!< [14] Hardware Request Status Channel 14 */
mbed_official 324:406fd2029f23 3191 uint32_t HRS15 : 1; /*!< [15] Hardware Request Status Channel 15 */
mbed_official 324:406fd2029f23 3192 uint32_t RESERVED0 : 16; /*!< [31:16] Reserved */
mbed_official 324:406fd2029f23 3193 } B;
mbed_official 324:406fd2029f23 3194 } hw_dma_hrs_t;
mbed_official 324:406fd2029f23 3195
mbed_official 324:406fd2029f23 3196 /*!
mbed_official 324:406fd2029f23 3197 * @name Constants and macros for entire DMA_HRS register
mbed_official 324:406fd2029f23 3198 */
mbed_official 324:406fd2029f23 3199 /*@{*/
mbed_official 324:406fd2029f23 3200 #define HW_DMA_HRS_ADDR(x) ((x) + 0x34U)
mbed_official 324:406fd2029f23 3201
mbed_official 324:406fd2029f23 3202 #define HW_DMA_HRS(x) (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
mbed_official 324:406fd2029f23 3203 #define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
mbed_official 324:406fd2029f23 3204 /*@}*/
mbed_official 324:406fd2029f23 3205
mbed_official 324:406fd2029f23 3206 /*
mbed_official 324:406fd2029f23 3207 * Constants & macros for individual DMA_HRS bitfields
mbed_official 324:406fd2029f23 3208 */
mbed_official 324:406fd2029f23 3209
mbed_official 324:406fd2029f23 3210 /*!
mbed_official 324:406fd2029f23 3211 * @name Register DMA_HRS, field HRS0[0] (RO)
mbed_official 324:406fd2029f23 3212 *
mbed_official 324:406fd2029f23 3213 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3214 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3215 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3216 *
mbed_official 324:406fd2029f23 3217 * Values:
mbed_official 324:406fd2029f23 3218 * - 0 - A hardware service request for channel 0 is not present
mbed_official 324:406fd2029f23 3219 * - 1 - A hardware service request for channel 0 is present
mbed_official 324:406fd2029f23 3220 */
mbed_official 324:406fd2029f23 3221 /*@{*/
mbed_official 324:406fd2029f23 3222 #define BP_DMA_HRS_HRS0 (0U) /*!< Bit position for DMA_HRS_HRS0. */
mbed_official 324:406fd2029f23 3223 #define BM_DMA_HRS_HRS0 (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */
mbed_official 324:406fd2029f23 3224 #define BS_DMA_HRS_HRS0 (1U) /*!< Bit field size in bits for DMA_HRS_HRS0. */
mbed_official 324:406fd2029f23 3225
mbed_official 324:406fd2029f23 3226 /*! @brief Read current value of the DMA_HRS_HRS0 field. */
mbed_official 324:406fd2029f23 3227 #define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
mbed_official 324:406fd2029f23 3228 /*@}*/
mbed_official 324:406fd2029f23 3229
mbed_official 324:406fd2029f23 3230 /*!
mbed_official 324:406fd2029f23 3231 * @name Register DMA_HRS, field HRS1[1] (RO)
mbed_official 324:406fd2029f23 3232 *
mbed_official 324:406fd2029f23 3233 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3234 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3235 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3236 *
mbed_official 324:406fd2029f23 3237 * Values:
mbed_official 324:406fd2029f23 3238 * - 0 - A hardware service request for channel 1 is not present
mbed_official 324:406fd2029f23 3239 * - 1 - A hardware service request for channel 1 is present
mbed_official 324:406fd2029f23 3240 */
mbed_official 324:406fd2029f23 3241 /*@{*/
mbed_official 324:406fd2029f23 3242 #define BP_DMA_HRS_HRS1 (1U) /*!< Bit position for DMA_HRS_HRS1. */
mbed_official 324:406fd2029f23 3243 #define BM_DMA_HRS_HRS1 (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */
mbed_official 324:406fd2029f23 3244 #define BS_DMA_HRS_HRS1 (1U) /*!< Bit field size in bits for DMA_HRS_HRS1. */
mbed_official 324:406fd2029f23 3245
mbed_official 324:406fd2029f23 3246 /*! @brief Read current value of the DMA_HRS_HRS1 field. */
mbed_official 324:406fd2029f23 3247 #define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
mbed_official 324:406fd2029f23 3248 /*@}*/
mbed_official 324:406fd2029f23 3249
mbed_official 324:406fd2029f23 3250 /*!
mbed_official 324:406fd2029f23 3251 * @name Register DMA_HRS, field HRS2[2] (RO)
mbed_official 324:406fd2029f23 3252 *
mbed_official 324:406fd2029f23 3253 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3254 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3255 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3256 *
mbed_official 324:406fd2029f23 3257 * Values:
mbed_official 324:406fd2029f23 3258 * - 0 - A hardware service request for channel 2 is not present
mbed_official 324:406fd2029f23 3259 * - 1 - A hardware service request for channel 2 is present
mbed_official 324:406fd2029f23 3260 */
mbed_official 324:406fd2029f23 3261 /*@{*/
mbed_official 324:406fd2029f23 3262 #define BP_DMA_HRS_HRS2 (2U) /*!< Bit position for DMA_HRS_HRS2. */
mbed_official 324:406fd2029f23 3263 #define BM_DMA_HRS_HRS2 (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */
mbed_official 324:406fd2029f23 3264 #define BS_DMA_HRS_HRS2 (1U) /*!< Bit field size in bits for DMA_HRS_HRS2. */
mbed_official 324:406fd2029f23 3265
mbed_official 324:406fd2029f23 3266 /*! @brief Read current value of the DMA_HRS_HRS2 field. */
mbed_official 324:406fd2029f23 3267 #define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
mbed_official 324:406fd2029f23 3268 /*@}*/
mbed_official 324:406fd2029f23 3269
mbed_official 324:406fd2029f23 3270 /*!
mbed_official 324:406fd2029f23 3271 * @name Register DMA_HRS, field HRS3[3] (RO)
mbed_official 324:406fd2029f23 3272 *
mbed_official 324:406fd2029f23 3273 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3274 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3275 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3276 *
mbed_official 324:406fd2029f23 3277 * Values:
mbed_official 324:406fd2029f23 3278 * - 0 - A hardware service request for channel 3 is not present
mbed_official 324:406fd2029f23 3279 * - 1 - A hardware service request for channel 3 is present
mbed_official 324:406fd2029f23 3280 */
mbed_official 324:406fd2029f23 3281 /*@{*/
mbed_official 324:406fd2029f23 3282 #define BP_DMA_HRS_HRS3 (3U) /*!< Bit position for DMA_HRS_HRS3. */
mbed_official 324:406fd2029f23 3283 #define BM_DMA_HRS_HRS3 (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */
mbed_official 324:406fd2029f23 3284 #define BS_DMA_HRS_HRS3 (1U) /*!< Bit field size in bits for DMA_HRS_HRS3. */
mbed_official 324:406fd2029f23 3285
mbed_official 324:406fd2029f23 3286 /*! @brief Read current value of the DMA_HRS_HRS3 field. */
mbed_official 324:406fd2029f23 3287 #define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
mbed_official 324:406fd2029f23 3288 /*@}*/
mbed_official 324:406fd2029f23 3289
mbed_official 324:406fd2029f23 3290 /*!
mbed_official 324:406fd2029f23 3291 * @name Register DMA_HRS, field HRS4[4] (RO)
mbed_official 324:406fd2029f23 3292 *
mbed_official 324:406fd2029f23 3293 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3294 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3295 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3296 *
mbed_official 324:406fd2029f23 3297 * Values:
mbed_official 324:406fd2029f23 3298 * - 0 - A hardware service request for channel 4 is not present
mbed_official 324:406fd2029f23 3299 * - 1 - A hardware service request for channel 4 is present
mbed_official 324:406fd2029f23 3300 */
mbed_official 324:406fd2029f23 3301 /*@{*/
mbed_official 324:406fd2029f23 3302 #define BP_DMA_HRS_HRS4 (4U) /*!< Bit position for DMA_HRS_HRS4. */
mbed_official 324:406fd2029f23 3303 #define BM_DMA_HRS_HRS4 (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */
mbed_official 324:406fd2029f23 3304 #define BS_DMA_HRS_HRS4 (1U) /*!< Bit field size in bits for DMA_HRS_HRS4. */
mbed_official 324:406fd2029f23 3305
mbed_official 324:406fd2029f23 3306 /*! @brief Read current value of the DMA_HRS_HRS4 field. */
mbed_official 324:406fd2029f23 3307 #define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
mbed_official 324:406fd2029f23 3308 /*@}*/
mbed_official 324:406fd2029f23 3309
mbed_official 324:406fd2029f23 3310 /*!
mbed_official 324:406fd2029f23 3311 * @name Register DMA_HRS, field HRS5[5] (RO)
mbed_official 324:406fd2029f23 3312 *
mbed_official 324:406fd2029f23 3313 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3314 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3315 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3316 *
mbed_official 324:406fd2029f23 3317 * Values:
mbed_official 324:406fd2029f23 3318 * - 0 - A hardware service request for channel 5 is not present
mbed_official 324:406fd2029f23 3319 * - 1 - A hardware service request for channel 5 is present
mbed_official 324:406fd2029f23 3320 */
mbed_official 324:406fd2029f23 3321 /*@{*/
mbed_official 324:406fd2029f23 3322 #define BP_DMA_HRS_HRS5 (5U) /*!< Bit position for DMA_HRS_HRS5. */
mbed_official 324:406fd2029f23 3323 #define BM_DMA_HRS_HRS5 (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */
mbed_official 324:406fd2029f23 3324 #define BS_DMA_HRS_HRS5 (1U) /*!< Bit field size in bits for DMA_HRS_HRS5. */
mbed_official 324:406fd2029f23 3325
mbed_official 324:406fd2029f23 3326 /*! @brief Read current value of the DMA_HRS_HRS5 field. */
mbed_official 324:406fd2029f23 3327 #define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
mbed_official 324:406fd2029f23 3328 /*@}*/
mbed_official 324:406fd2029f23 3329
mbed_official 324:406fd2029f23 3330 /*!
mbed_official 324:406fd2029f23 3331 * @name Register DMA_HRS, field HRS6[6] (RO)
mbed_official 324:406fd2029f23 3332 *
mbed_official 324:406fd2029f23 3333 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3334 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3335 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3336 *
mbed_official 324:406fd2029f23 3337 * Values:
mbed_official 324:406fd2029f23 3338 * - 0 - A hardware service request for channel 6 is not present
mbed_official 324:406fd2029f23 3339 * - 1 - A hardware service request for channel 6 is present
mbed_official 324:406fd2029f23 3340 */
mbed_official 324:406fd2029f23 3341 /*@{*/
mbed_official 324:406fd2029f23 3342 #define BP_DMA_HRS_HRS6 (6U) /*!< Bit position for DMA_HRS_HRS6. */
mbed_official 324:406fd2029f23 3343 #define BM_DMA_HRS_HRS6 (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */
mbed_official 324:406fd2029f23 3344 #define BS_DMA_HRS_HRS6 (1U) /*!< Bit field size in bits for DMA_HRS_HRS6. */
mbed_official 324:406fd2029f23 3345
mbed_official 324:406fd2029f23 3346 /*! @brief Read current value of the DMA_HRS_HRS6 field. */
mbed_official 324:406fd2029f23 3347 #define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
mbed_official 324:406fd2029f23 3348 /*@}*/
mbed_official 324:406fd2029f23 3349
mbed_official 324:406fd2029f23 3350 /*!
mbed_official 324:406fd2029f23 3351 * @name Register DMA_HRS, field HRS7[7] (RO)
mbed_official 324:406fd2029f23 3352 *
mbed_official 324:406fd2029f23 3353 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3354 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3355 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3356 *
mbed_official 324:406fd2029f23 3357 * Values:
mbed_official 324:406fd2029f23 3358 * - 0 - A hardware service request for channel 7 is not present
mbed_official 324:406fd2029f23 3359 * - 1 - A hardware service request for channel 7 is present
mbed_official 324:406fd2029f23 3360 */
mbed_official 324:406fd2029f23 3361 /*@{*/
mbed_official 324:406fd2029f23 3362 #define BP_DMA_HRS_HRS7 (7U) /*!< Bit position for DMA_HRS_HRS7. */
mbed_official 324:406fd2029f23 3363 #define BM_DMA_HRS_HRS7 (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */
mbed_official 324:406fd2029f23 3364 #define BS_DMA_HRS_HRS7 (1U) /*!< Bit field size in bits for DMA_HRS_HRS7. */
mbed_official 324:406fd2029f23 3365
mbed_official 324:406fd2029f23 3366 /*! @brief Read current value of the DMA_HRS_HRS7 field. */
mbed_official 324:406fd2029f23 3367 #define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
mbed_official 324:406fd2029f23 3368 /*@}*/
mbed_official 324:406fd2029f23 3369
mbed_official 324:406fd2029f23 3370 /*!
mbed_official 324:406fd2029f23 3371 * @name Register DMA_HRS, field HRS8[8] (RO)
mbed_official 324:406fd2029f23 3372 *
mbed_official 324:406fd2029f23 3373 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3374 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3375 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3376 *
mbed_official 324:406fd2029f23 3377 * Values:
mbed_official 324:406fd2029f23 3378 * - 0 - A hardware service request for channel 8 is not present
mbed_official 324:406fd2029f23 3379 * - 1 - A hardware service request for channel 8 is present
mbed_official 324:406fd2029f23 3380 */
mbed_official 324:406fd2029f23 3381 /*@{*/
mbed_official 324:406fd2029f23 3382 #define BP_DMA_HRS_HRS8 (8U) /*!< Bit position for DMA_HRS_HRS8. */
mbed_official 324:406fd2029f23 3383 #define BM_DMA_HRS_HRS8 (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */
mbed_official 324:406fd2029f23 3384 #define BS_DMA_HRS_HRS8 (1U) /*!< Bit field size in bits for DMA_HRS_HRS8. */
mbed_official 324:406fd2029f23 3385
mbed_official 324:406fd2029f23 3386 /*! @brief Read current value of the DMA_HRS_HRS8 field. */
mbed_official 324:406fd2029f23 3387 #define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
mbed_official 324:406fd2029f23 3388 /*@}*/
mbed_official 324:406fd2029f23 3389
mbed_official 324:406fd2029f23 3390 /*!
mbed_official 324:406fd2029f23 3391 * @name Register DMA_HRS, field HRS9[9] (RO)
mbed_official 324:406fd2029f23 3392 *
mbed_official 324:406fd2029f23 3393 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3394 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3395 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3396 *
mbed_official 324:406fd2029f23 3397 * Values:
mbed_official 324:406fd2029f23 3398 * - 0 - A hardware service request for channel 9 is not present
mbed_official 324:406fd2029f23 3399 * - 1 - A hardware service request for channel 9 is present
mbed_official 324:406fd2029f23 3400 */
mbed_official 324:406fd2029f23 3401 /*@{*/
mbed_official 324:406fd2029f23 3402 #define BP_DMA_HRS_HRS9 (9U) /*!< Bit position for DMA_HRS_HRS9. */
mbed_official 324:406fd2029f23 3403 #define BM_DMA_HRS_HRS9 (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */
mbed_official 324:406fd2029f23 3404 #define BS_DMA_HRS_HRS9 (1U) /*!< Bit field size in bits for DMA_HRS_HRS9. */
mbed_official 324:406fd2029f23 3405
mbed_official 324:406fd2029f23 3406 /*! @brief Read current value of the DMA_HRS_HRS9 field. */
mbed_official 324:406fd2029f23 3407 #define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
mbed_official 324:406fd2029f23 3408 /*@}*/
mbed_official 324:406fd2029f23 3409
mbed_official 324:406fd2029f23 3410 /*!
mbed_official 324:406fd2029f23 3411 * @name Register DMA_HRS, field HRS10[10] (RO)
mbed_official 324:406fd2029f23 3412 *
mbed_official 324:406fd2029f23 3413 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3414 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3415 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3416 *
mbed_official 324:406fd2029f23 3417 * Values:
mbed_official 324:406fd2029f23 3418 * - 0 - A hardware service request for channel 10 is not present
mbed_official 324:406fd2029f23 3419 * - 1 - A hardware service request for channel 10 is present
mbed_official 324:406fd2029f23 3420 */
mbed_official 324:406fd2029f23 3421 /*@{*/
mbed_official 324:406fd2029f23 3422 #define BP_DMA_HRS_HRS10 (10U) /*!< Bit position for DMA_HRS_HRS10. */
mbed_official 324:406fd2029f23 3423 #define BM_DMA_HRS_HRS10 (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */
mbed_official 324:406fd2029f23 3424 #define BS_DMA_HRS_HRS10 (1U) /*!< Bit field size in bits for DMA_HRS_HRS10. */
mbed_official 324:406fd2029f23 3425
mbed_official 324:406fd2029f23 3426 /*! @brief Read current value of the DMA_HRS_HRS10 field. */
mbed_official 324:406fd2029f23 3427 #define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
mbed_official 324:406fd2029f23 3428 /*@}*/
mbed_official 324:406fd2029f23 3429
mbed_official 324:406fd2029f23 3430 /*!
mbed_official 324:406fd2029f23 3431 * @name Register DMA_HRS, field HRS11[11] (RO)
mbed_official 324:406fd2029f23 3432 *
mbed_official 324:406fd2029f23 3433 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3434 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3435 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3436 *
mbed_official 324:406fd2029f23 3437 * Values:
mbed_official 324:406fd2029f23 3438 * - 0 - A hardware service request for channel 11 is not present
mbed_official 324:406fd2029f23 3439 * - 1 - A hardware service request for channel 11 is present
mbed_official 324:406fd2029f23 3440 */
mbed_official 324:406fd2029f23 3441 /*@{*/
mbed_official 324:406fd2029f23 3442 #define BP_DMA_HRS_HRS11 (11U) /*!< Bit position for DMA_HRS_HRS11. */
mbed_official 324:406fd2029f23 3443 #define BM_DMA_HRS_HRS11 (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */
mbed_official 324:406fd2029f23 3444 #define BS_DMA_HRS_HRS11 (1U) /*!< Bit field size in bits for DMA_HRS_HRS11. */
mbed_official 324:406fd2029f23 3445
mbed_official 324:406fd2029f23 3446 /*! @brief Read current value of the DMA_HRS_HRS11 field. */
mbed_official 324:406fd2029f23 3447 #define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
mbed_official 324:406fd2029f23 3448 /*@}*/
mbed_official 324:406fd2029f23 3449
mbed_official 324:406fd2029f23 3450 /*!
mbed_official 324:406fd2029f23 3451 * @name Register DMA_HRS, field HRS12[12] (RO)
mbed_official 324:406fd2029f23 3452 *
mbed_official 324:406fd2029f23 3453 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3454 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3455 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3456 *
mbed_official 324:406fd2029f23 3457 * Values:
mbed_official 324:406fd2029f23 3458 * - 0 - A hardware service request for channel 12 is not present
mbed_official 324:406fd2029f23 3459 * - 1 - A hardware service request for channel 12 is present
mbed_official 324:406fd2029f23 3460 */
mbed_official 324:406fd2029f23 3461 /*@{*/
mbed_official 324:406fd2029f23 3462 #define BP_DMA_HRS_HRS12 (12U) /*!< Bit position for DMA_HRS_HRS12. */
mbed_official 324:406fd2029f23 3463 #define BM_DMA_HRS_HRS12 (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */
mbed_official 324:406fd2029f23 3464 #define BS_DMA_HRS_HRS12 (1U) /*!< Bit field size in bits for DMA_HRS_HRS12. */
mbed_official 324:406fd2029f23 3465
mbed_official 324:406fd2029f23 3466 /*! @brief Read current value of the DMA_HRS_HRS12 field. */
mbed_official 324:406fd2029f23 3467 #define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
mbed_official 324:406fd2029f23 3468 /*@}*/
mbed_official 324:406fd2029f23 3469
mbed_official 324:406fd2029f23 3470 /*!
mbed_official 324:406fd2029f23 3471 * @name Register DMA_HRS, field HRS13[13] (RO)
mbed_official 324:406fd2029f23 3472 *
mbed_official 324:406fd2029f23 3473 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3474 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3475 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3476 *
mbed_official 324:406fd2029f23 3477 * Values:
mbed_official 324:406fd2029f23 3478 * - 0 - A hardware service request for channel 13 is not present
mbed_official 324:406fd2029f23 3479 * - 1 - A hardware service request for channel 13 is present
mbed_official 324:406fd2029f23 3480 */
mbed_official 324:406fd2029f23 3481 /*@{*/
mbed_official 324:406fd2029f23 3482 #define BP_DMA_HRS_HRS13 (13U) /*!< Bit position for DMA_HRS_HRS13. */
mbed_official 324:406fd2029f23 3483 #define BM_DMA_HRS_HRS13 (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */
mbed_official 324:406fd2029f23 3484 #define BS_DMA_HRS_HRS13 (1U) /*!< Bit field size in bits for DMA_HRS_HRS13. */
mbed_official 324:406fd2029f23 3485
mbed_official 324:406fd2029f23 3486 /*! @brief Read current value of the DMA_HRS_HRS13 field. */
mbed_official 324:406fd2029f23 3487 #define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
mbed_official 324:406fd2029f23 3488 /*@}*/
mbed_official 324:406fd2029f23 3489
mbed_official 324:406fd2029f23 3490 /*!
mbed_official 324:406fd2029f23 3491 * @name Register DMA_HRS, field HRS14[14] (RO)
mbed_official 324:406fd2029f23 3492 *
mbed_official 324:406fd2029f23 3493 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3494 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3495 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3496 *
mbed_official 324:406fd2029f23 3497 * Values:
mbed_official 324:406fd2029f23 3498 * - 0 - A hardware service request for channel 14 is not present
mbed_official 324:406fd2029f23 3499 * - 1 - A hardware service request for channel 14 is present
mbed_official 324:406fd2029f23 3500 */
mbed_official 324:406fd2029f23 3501 /*@{*/
mbed_official 324:406fd2029f23 3502 #define BP_DMA_HRS_HRS14 (14U) /*!< Bit position for DMA_HRS_HRS14. */
mbed_official 324:406fd2029f23 3503 #define BM_DMA_HRS_HRS14 (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */
mbed_official 324:406fd2029f23 3504 #define BS_DMA_HRS_HRS14 (1U) /*!< Bit field size in bits for DMA_HRS_HRS14. */
mbed_official 324:406fd2029f23 3505
mbed_official 324:406fd2029f23 3506 /*! @brief Read current value of the DMA_HRS_HRS14 field. */
mbed_official 324:406fd2029f23 3507 #define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
mbed_official 324:406fd2029f23 3508 /*@}*/
mbed_official 324:406fd2029f23 3509
mbed_official 324:406fd2029f23 3510 /*!
mbed_official 324:406fd2029f23 3511 * @name Register DMA_HRS, field HRS15[15] (RO)
mbed_official 324:406fd2029f23 3512 *
mbed_official 324:406fd2029f23 3513 * The HRS bit for its respective channel remains asserted for the period when a
mbed_official 324:406fd2029f23 3514 * Hardware Request is Present on the Channel. After the Request is completed
mbed_official 324:406fd2029f23 3515 * and Channel is free , the HRS bit is automatically cleared by hardware.
mbed_official 324:406fd2029f23 3516 *
mbed_official 324:406fd2029f23 3517 * Values:
mbed_official 324:406fd2029f23 3518 * - 0 - A hardware service request for channel 15 is not present
mbed_official 324:406fd2029f23 3519 * - 1 - A hardware service request for channel 15 is present
mbed_official 324:406fd2029f23 3520 */
mbed_official 324:406fd2029f23 3521 /*@{*/
mbed_official 324:406fd2029f23 3522 #define BP_DMA_HRS_HRS15 (15U) /*!< Bit position for DMA_HRS_HRS15. */
mbed_official 324:406fd2029f23 3523 #define BM_DMA_HRS_HRS15 (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */
mbed_official 324:406fd2029f23 3524 #define BS_DMA_HRS_HRS15 (1U) /*!< Bit field size in bits for DMA_HRS_HRS15. */
mbed_official 324:406fd2029f23 3525
mbed_official 324:406fd2029f23 3526 /*! @brief Read current value of the DMA_HRS_HRS15 field. */
mbed_official 324:406fd2029f23 3527 #define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
mbed_official 324:406fd2029f23 3528 /*@}*/
mbed_official 324:406fd2029f23 3529
mbed_official 324:406fd2029f23 3530 /*******************************************************************************
mbed_official 324:406fd2029f23 3531 * HW_DMA_EARS - Enable Asynchronous Request in Stop Register
mbed_official 324:406fd2029f23 3532 ******************************************************************************/
mbed_official 324:406fd2029f23 3533
mbed_official 324:406fd2029f23 3534 /*!
mbed_official 324:406fd2029f23 3535 * @brief HW_DMA_EARS - Enable Asynchronous Request in Stop Register (RW)
mbed_official 324:406fd2029f23 3536 *
mbed_official 324:406fd2029f23 3537 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 3538 */
mbed_official 324:406fd2029f23 3539 typedef union _hw_dma_ears
mbed_official 324:406fd2029f23 3540 {
mbed_official 324:406fd2029f23 3541 uint32_t U;
mbed_official 324:406fd2029f23 3542 struct _hw_dma_ears_bitfields
mbed_official 324:406fd2029f23 3543 {
mbed_official 324:406fd2029f23 3544 uint32_t EDREQ_0 : 1; /*!< [0] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3545 * stop for channel 0. */
mbed_official 324:406fd2029f23 3546 uint32_t EDREQ_1 : 1; /*!< [1] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3547 * stop for channel 1. */
mbed_official 324:406fd2029f23 3548 uint32_t EDREQ_2 : 1; /*!< [2] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3549 * stop for channel 2. */
mbed_official 324:406fd2029f23 3550 uint32_t EDREQ_3 : 1; /*!< [3] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3551 * stop for channel 3. */
mbed_official 324:406fd2029f23 3552 uint32_t EDREQ_4 : 1; /*!< [4] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3553 * stop for channel 4 */
mbed_official 324:406fd2029f23 3554 uint32_t EDREQ_5 : 1; /*!< [5] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3555 * stop for channel 5 */
mbed_official 324:406fd2029f23 3556 uint32_t EDREQ_6 : 1; /*!< [6] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3557 * stop for channel 6 */
mbed_official 324:406fd2029f23 3558 uint32_t EDREQ_7 : 1; /*!< [7] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3559 * stop for channel 7 */
mbed_official 324:406fd2029f23 3560 uint32_t EDREQ_8 : 1; /*!< [8] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3561 * stop for channel 8 */
mbed_official 324:406fd2029f23 3562 uint32_t EDREQ_9 : 1; /*!< [9] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3563 * stop for channel 9 */
mbed_official 324:406fd2029f23 3564 uint32_t EDREQ_10 : 1; /*!< [10] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3565 * stop for channel 10 */
mbed_official 324:406fd2029f23 3566 uint32_t EDREQ_11 : 1; /*!< [11] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3567 * stop for channel 11 */
mbed_official 324:406fd2029f23 3568 uint32_t EDREQ_12 : 1; /*!< [12] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3569 * stop for channel 12 */
mbed_official 324:406fd2029f23 3570 uint32_t EDREQ_13 : 1; /*!< [13] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3571 * stop for channel 13 */
mbed_official 324:406fd2029f23 3572 uint32_t EDREQ_14 : 1; /*!< [14] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3573 * stop for channel 14 */
mbed_official 324:406fd2029f23 3574 uint32_t EDREQ_15 : 1; /*!< [15] Enable asynchronous DMA request in
mbed_official 324:406fd2029f23 3575 * stop for channel 15 */
mbed_official 324:406fd2029f23 3576 uint32_t RESERVED0 : 16; /*!< [31:16] Reserved. */
mbed_official 324:406fd2029f23 3577 } B;
mbed_official 324:406fd2029f23 3578 } hw_dma_ears_t;
mbed_official 324:406fd2029f23 3579
mbed_official 324:406fd2029f23 3580 /*!
mbed_official 324:406fd2029f23 3581 * @name Constants and macros for entire DMA_EARS register
mbed_official 324:406fd2029f23 3582 */
mbed_official 324:406fd2029f23 3583 /*@{*/
mbed_official 324:406fd2029f23 3584 #define HW_DMA_EARS_ADDR(x) ((x) + 0x44U)
mbed_official 324:406fd2029f23 3585
mbed_official 324:406fd2029f23 3586 #define HW_DMA_EARS(x) (*(__IO hw_dma_ears_t *) HW_DMA_EARS_ADDR(x))
mbed_official 324:406fd2029f23 3587 #define HW_DMA_EARS_RD(x) (HW_DMA_EARS(x).U)
mbed_official 324:406fd2029f23 3588 #define HW_DMA_EARS_WR(x, v) (HW_DMA_EARS(x).U = (v))
mbed_official 324:406fd2029f23 3589 #define HW_DMA_EARS_SET(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) | (v)))
mbed_official 324:406fd2029f23 3590 #define HW_DMA_EARS_CLR(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 3591 #define HW_DMA_EARS_TOG(x, v) (HW_DMA_EARS_WR(x, HW_DMA_EARS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 3592 /*@}*/
mbed_official 324:406fd2029f23 3593
mbed_official 324:406fd2029f23 3594 /*
mbed_official 324:406fd2029f23 3595 * Constants & macros for individual DMA_EARS bitfields
mbed_official 324:406fd2029f23 3596 */
mbed_official 324:406fd2029f23 3597
mbed_official 324:406fd2029f23 3598 /*!
mbed_official 324:406fd2029f23 3599 * @name Register DMA_EARS, field EDREQ_0[0] (RW)
mbed_official 324:406fd2029f23 3600 *
mbed_official 324:406fd2029f23 3601 * Values:
mbed_official 324:406fd2029f23 3602 * - 0 - Disable asynchronous DMA request for channel 0.
mbed_official 324:406fd2029f23 3603 * - 1 - Enable asynchronous DMA request for channel 0.
mbed_official 324:406fd2029f23 3604 */
mbed_official 324:406fd2029f23 3605 /*@{*/
mbed_official 324:406fd2029f23 3606 #define BP_DMA_EARS_EDREQ_0 (0U) /*!< Bit position for DMA_EARS_EDREQ_0. */
mbed_official 324:406fd2029f23 3607 #define BM_DMA_EARS_EDREQ_0 (0x00000001U) /*!< Bit mask for DMA_EARS_EDREQ_0. */
mbed_official 324:406fd2029f23 3608 #define BS_DMA_EARS_EDREQ_0 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_0. */
mbed_official 324:406fd2029f23 3609
mbed_official 324:406fd2029f23 3610 /*! @brief Read current value of the DMA_EARS_EDREQ_0 field. */
mbed_official 324:406fd2029f23 3611 #define BR_DMA_EARS_EDREQ_0(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0))
mbed_official 324:406fd2029f23 3612
mbed_official 324:406fd2029f23 3613 /*! @brief Format value for bitfield DMA_EARS_EDREQ_0. */
mbed_official 324:406fd2029f23 3614 #define BF_DMA_EARS_EDREQ_0(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_0) & BM_DMA_EARS_EDREQ_0)
mbed_official 324:406fd2029f23 3615
mbed_official 324:406fd2029f23 3616 /*! @brief Set the EDREQ_0 field to a new value. */
mbed_official 324:406fd2029f23 3617 #define BW_DMA_EARS_EDREQ_0(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_0) = (v))
mbed_official 324:406fd2029f23 3618 /*@}*/
mbed_official 324:406fd2029f23 3619
mbed_official 324:406fd2029f23 3620 /*!
mbed_official 324:406fd2029f23 3621 * @name Register DMA_EARS, field EDREQ_1[1] (RW)
mbed_official 324:406fd2029f23 3622 *
mbed_official 324:406fd2029f23 3623 * Values:
mbed_official 324:406fd2029f23 3624 * - 0 - Disable asynchronous DMA request for channel 1
mbed_official 324:406fd2029f23 3625 * - 1 - Enable asynchronous DMA request for channel 1.
mbed_official 324:406fd2029f23 3626 */
mbed_official 324:406fd2029f23 3627 /*@{*/
mbed_official 324:406fd2029f23 3628 #define BP_DMA_EARS_EDREQ_1 (1U) /*!< Bit position for DMA_EARS_EDREQ_1. */
mbed_official 324:406fd2029f23 3629 #define BM_DMA_EARS_EDREQ_1 (0x00000002U) /*!< Bit mask for DMA_EARS_EDREQ_1. */
mbed_official 324:406fd2029f23 3630 #define BS_DMA_EARS_EDREQ_1 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_1. */
mbed_official 324:406fd2029f23 3631
mbed_official 324:406fd2029f23 3632 /*! @brief Read current value of the DMA_EARS_EDREQ_1 field. */
mbed_official 324:406fd2029f23 3633 #define BR_DMA_EARS_EDREQ_1(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1))
mbed_official 324:406fd2029f23 3634
mbed_official 324:406fd2029f23 3635 /*! @brief Format value for bitfield DMA_EARS_EDREQ_1. */
mbed_official 324:406fd2029f23 3636 #define BF_DMA_EARS_EDREQ_1(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_1) & BM_DMA_EARS_EDREQ_1)
mbed_official 324:406fd2029f23 3637
mbed_official 324:406fd2029f23 3638 /*! @brief Set the EDREQ_1 field to a new value. */
mbed_official 324:406fd2029f23 3639 #define BW_DMA_EARS_EDREQ_1(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_1) = (v))
mbed_official 324:406fd2029f23 3640 /*@}*/
mbed_official 324:406fd2029f23 3641
mbed_official 324:406fd2029f23 3642 /*!
mbed_official 324:406fd2029f23 3643 * @name Register DMA_EARS, field EDREQ_2[2] (RW)
mbed_official 324:406fd2029f23 3644 *
mbed_official 324:406fd2029f23 3645 * Values:
mbed_official 324:406fd2029f23 3646 * - 0 - Disable asynchronous DMA request for channel 2.
mbed_official 324:406fd2029f23 3647 * - 1 - Enable asynchronous DMA request for channel 2.
mbed_official 324:406fd2029f23 3648 */
mbed_official 324:406fd2029f23 3649 /*@{*/
mbed_official 324:406fd2029f23 3650 #define BP_DMA_EARS_EDREQ_2 (2U) /*!< Bit position for DMA_EARS_EDREQ_2. */
mbed_official 324:406fd2029f23 3651 #define BM_DMA_EARS_EDREQ_2 (0x00000004U) /*!< Bit mask for DMA_EARS_EDREQ_2. */
mbed_official 324:406fd2029f23 3652 #define BS_DMA_EARS_EDREQ_2 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_2. */
mbed_official 324:406fd2029f23 3653
mbed_official 324:406fd2029f23 3654 /*! @brief Read current value of the DMA_EARS_EDREQ_2 field. */
mbed_official 324:406fd2029f23 3655 #define BR_DMA_EARS_EDREQ_2(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2))
mbed_official 324:406fd2029f23 3656
mbed_official 324:406fd2029f23 3657 /*! @brief Format value for bitfield DMA_EARS_EDREQ_2. */
mbed_official 324:406fd2029f23 3658 #define BF_DMA_EARS_EDREQ_2(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_2) & BM_DMA_EARS_EDREQ_2)
mbed_official 324:406fd2029f23 3659
mbed_official 324:406fd2029f23 3660 /*! @brief Set the EDREQ_2 field to a new value. */
mbed_official 324:406fd2029f23 3661 #define BW_DMA_EARS_EDREQ_2(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_2) = (v))
mbed_official 324:406fd2029f23 3662 /*@}*/
mbed_official 324:406fd2029f23 3663
mbed_official 324:406fd2029f23 3664 /*!
mbed_official 324:406fd2029f23 3665 * @name Register DMA_EARS, field EDREQ_3[3] (RW)
mbed_official 324:406fd2029f23 3666 *
mbed_official 324:406fd2029f23 3667 * Values:
mbed_official 324:406fd2029f23 3668 * - 0 - Disable asynchronous DMA request for channel 3.
mbed_official 324:406fd2029f23 3669 * - 1 - Enable asynchronous DMA request for channel 3.
mbed_official 324:406fd2029f23 3670 */
mbed_official 324:406fd2029f23 3671 /*@{*/
mbed_official 324:406fd2029f23 3672 #define BP_DMA_EARS_EDREQ_3 (3U) /*!< Bit position for DMA_EARS_EDREQ_3. */
mbed_official 324:406fd2029f23 3673 #define BM_DMA_EARS_EDREQ_3 (0x00000008U) /*!< Bit mask for DMA_EARS_EDREQ_3. */
mbed_official 324:406fd2029f23 3674 #define BS_DMA_EARS_EDREQ_3 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_3. */
mbed_official 324:406fd2029f23 3675
mbed_official 324:406fd2029f23 3676 /*! @brief Read current value of the DMA_EARS_EDREQ_3 field. */
mbed_official 324:406fd2029f23 3677 #define BR_DMA_EARS_EDREQ_3(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3))
mbed_official 324:406fd2029f23 3678
mbed_official 324:406fd2029f23 3679 /*! @brief Format value for bitfield DMA_EARS_EDREQ_3. */
mbed_official 324:406fd2029f23 3680 #define BF_DMA_EARS_EDREQ_3(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_3) & BM_DMA_EARS_EDREQ_3)
mbed_official 324:406fd2029f23 3681
mbed_official 324:406fd2029f23 3682 /*! @brief Set the EDREQ_3 field to a new value. */
mbed_official 324:406fd2029f23 3683 #define BW_DMA_EARS_EDREQ_3(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_3) = (v))
mbed_official 324:406fd2029f23 3684 /*@}*/
mbed_official 324:406fd2029f23 3685
mbed_official 324:406fd2029f23 3686 /*!
mbed_official 324:406fd2029f23 3687 * @name Register DMA_EARS, field EDREQ_4[4] (RW)
mbed_official 324:406fd2029f23 3688 *
mbed_official 324:406fd2029f23 3689 * Values:
mbed_official 324:406fd2029f23 3690 * - 0 - Disable asynchronous DMA request for channel 4.
mbed_official 324:406fd2029f23 3691 * - 1 - Enable asynchronous DMA request for channel 4.
mbed_official 324:406fd2029f23 3692 */
mbed_official 324:406fd2029f23 3693 /*@{*/
mbed_official 324:406fd2029f23 3694 #define BP_DMA_EARS_EDREQ_4 (4U) /*!< Bit position for DMA_EARS_EDREQ_4. */
mbed_official 324:406fd2029f23 3695 #define BM_DMA_EARS_EDREQ_4 (0x00000010U) /*!< Bit mask for DMA_EARS_EDREQ_4. */
mbed_official 324:406fd2029f23 3696 #define BS_DMA_EARS_EDREQ_4 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_4. */
mbed_official 324:406fd2029f23 3697
mbed_official 324:406fd2029f23 3698 /*! @brief Read current value of the DMA_EARS_EDREQ_4 field. */
mbed_official 324:406fd2029f23 3699 #define BR_DMA_EARS_EDREQ_4(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4))
mbed_official 324:406fd2029f23 3700
mbed_official 324:406fd2029f23 3701 /*! @brief Format value for bitfield DMA_EARS_EDREQ_4. */
mbed_official 324:406fd2029f23 3702 #define BF_DMA_EARS_EDREQ_4(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_4) & BM_DMA_EARS_EDREQ_4)
mbed_official 324:406fd2029f23 3703
mbed_official 324:406fd2029f23 3704 /*! @brief Set the EDREQ_4 field to a new value. */
mbed_official 324:406fd2029f23 3705 #define BW_DMA_EARS_EDREQ_4(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_4) = (v))
mbed_official 324:406fd2029f23 3706 /*@}*/
mbed_official 324:406fd2029f23 3707
mbed_official 324:406fd2029f23 3708 /*!
mbed_official 324:406fd2029f23 3709 * @name Register DMA_EARS, field EDREQ_5[5] (RW)
mbed_official 324:406fd2029f23 3710 *
mbed_official 324:406fd2029f23 3711 * Values:
mbed_official 324:406fd2029f23 3712 * - 0 - Disable asynchronous DMA request for channel 5.
mbed_official 324:406fd2029f23 3713 * - 1 - Enable asynchronous DMA request for channel 5.
mbed_official 324:406fd2029f23 3714 */
mbed_official 324:406fd2029f23 3715 /*@{*/
mbed_official 324:406fd2029f23 3716 #define BP_DMA_EARS_EDREQ_5 (5U) /*!< Bit position for DMA_EARS_EDREQ_5. */
mbed_official 324:406fd2029f23 3717 #define BM_DMA_EARS_EDREQ_5 (0x00000020U) /*!< Bit mask for DMA_EARS_EDREQ_5. */
mbed_official 324:406fd2029f23 3718 #define BS_DMA_EARS_EDREQ_5 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_5. */
mbed_official 324:406fd2029f23 3719
mbed_official 324:406fd2029f23 3720 /*! @brief Read current value of the DMA_EARS_EDREQ_5 field. */
mbed_official 324:406fd2029f23 3721 #define BR_DMA_EARS_EDREQ_5(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5))
mbed_official 324:406fd2029f23 3722
mbed_official 324:406fd2029f23 3723 /*! @brief Format value for bitfield DMA_EARS_EDREQ_5. */
mbed_official 324:406fd2029f23 3724 #define BF_DMA_EARS_EDREQ_5(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_5) & BM_DMA_EARS_EDREQ_5)
mbed_official 324:406fd2029f23 3725
mbed_official 324:406fd2029f23 3726 /*! @brief Set the EDREQ_5 field to a new value. */
mbed_official 324:406fd2029f23 3727 #define BW_DMA_EARS_EDREQ_5(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_5) = (v))
mbed_official 324:406fd2029f23 3728 /*@}*/
mbed_official 324:406fd2029f23 3729
mbed_official 324:406fd2029f23 3730 /*!
mbed_official 324:406fd2029f23 3731 * @name Register DMA_EARS, field EDREQ_6[6] (RW)
mbed_official 324:406fd2029f23 3732 *
mbed_official 324:406fd2029f23 3733 * Values:
mbed_official 324:406fd2029f23 3734 * - 0 - Disable asynchronous DMA request for channel 6.
mbed_official 324:406fd2029f23 3735 * - 1 - Enable asynchronous DMA request for channel 6.
mbed_official 324:406fd2029f23 3736 */
mbed_official 324:406fd2029f23 3737 /*@{*/
mbed_official 324:406fd2029f23 3738 #define BP_DMA_EARS_EDREQ_6 (6U) /*!< Bit position for DMA_EARS_EDREQ_6. */
mbed_official 324:406fd2029f23 3739 #define BM_DMA_EARS_EDREQ_6 (0x00000040U) /*!< Bit mask for DMA_EARS_EDREQ_6. */
mbed_official 324:406fd2029f23 3740 #define BS_DMA_EARS_EDREQ_6 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_6. */
mbed_official 324:406fd2029f23 3741
mbed_official 324:406fd2029f23 3742 /*! @brief Read current value of the DMA_EARS_EDREQ_6 field. */
mbed_official 324:406fd2029f23 3743 #define BR_DMA_EARS_EDREQ_6(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6))
mbed_official 324:406fd2029f23 3744
mbed_official 324:406fd2029f23 3745 /*! @brief Format value for bitfield DMA_EARS_EDREQ_6. */
mbed_official 324:406fd2029f23 3746 #define BF_DMA_EARS_EDREQ_6(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_6) & BM_DMA_EARS_EDREQ_6)
mbed_official 324:406fd2029f23 3747
mbed_official 324:406fd2029f23 3748 /*! @brief Set the EDREQ_6 field to a new value. */
mbed_official 324:406fd2029f23 3749 #define BW_DMA_EARS_EDREQ_6(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_6) = (v))
mbed_official 324:406fd2029f23 3750 /*@}*/
mbed_official 324:406fd2029f23 3751
mbed_official 324:406fd2029f23 3752 /*!
mbed_official 324:406fd2029f23 3753 * @name Register DMA_EARS, field EDREQ_7[7] (RW)
mbed_official 324:406fd2029f23 3754 *
mbed_official 324:406fd2029f23 3755 * Values:
mbed_official 324:406fd2029f23 3756 * - 0 - Disable asynchronous DMA request for channel 7.
mbed_official 324:406fd2029f23 3757 * - 1 - Enable asynchronous DMA request for channel 7.
mbed_official 324:406fd2029f23 3758 */
mbed_official 324:406fd2029f23 3759 /*@{*/
mbed_official 324:406fd2029f23 3760 #define BP_DMA_EARS_EDREQ_7 (7U) /*!< Bit position for DMA_EARS_EDREQ_7. */
mbed_official 324:406fd2029f23 3761 #define BM_DMA_EARS_EDREQ_7 (0x00000080U) /*!< Bit mask for DMA_EARS_EDREQ_7. */
mbed_official 324:406fd2029f23 3762 #define BS_DMA_EARS_EDREQ_7 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_7. */
mbed_official 324:406fd2029f23 3763
mbed_official 324:406fd2029f23 3764 /*! @brief Read current value of the DMA_EARS_EDREQ_7 field. */
mbed_official 324:406fd2029f23 3765 #define BR_DMA_EARS_EDREQ_7(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7))
mbed_official 324:406fd2029f23 3766
mbed_official 324:406fd2029f23 3767 /*! @brief Format value for bitfield DMA_EARS_EDREQ_7. */
mbed_official 324:406fd2029f23 3768 #define BF_DMA_EARS_EDREQ_7(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_7) & BM_DMA_EARS_EDREQ_7)
mbed_official 324:406fd2029f23 3769
mbed_official 324:406fd2029f23 3770 /*! @brief Set the EDREQ_7 field to a new value. */
mbed_official 324:406fd2029f23 3771 #define BW_DMA_EARS_EDREQ_7(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_7) = (v))
mbed_official 324:406fd2029f23 3772 /*@}*/
mbed_official 324:406fd2029f23 3773
mbed_official 324:406fd2029f23 3774 /*!
mbed_official 324:406fd2029f23 3775 * @name Register DMA_EARS, field EDREQ_8[8] (RW)
mbed_official 324:406fd2029f23 3776 *
mbed_official 324:406fd2029f23 3777 * Values:
mbed_official 324:406fd2029f23 3778 * - 0 - Disable asynchronous DMA request for channel 8.
mbed_official 324:406fd2029f23 3779 * - 1 - Enable asynchronous DMA request for channel 8.
mbed_official 324:406fd2029f23 3780 */
mbed_official 324:406fd2029f23 3781 /*@{*/
mbed_official 324:406fd2029f23 3782 #define BP_DMA_EARS_EDREQ_8 (8U) /*!< Bit position for DMA_EARS_EDREQ_8. */
mbed_official 324:406fd2029f23 3783 #define BM_DMA_EARS_EDREQ_8 (0x00000100U) /*!< Bit mask for DMA_EARS_EDREQ_8. */
mbed_official 324:406fd2029f23 3784 #define BS_DMA_EARS_EDREQ_8 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_8. */
mbed_official 324:406fd2029f23 3785
mbed_official 324:406fd2029f23 3786 /*! @brief Read current value of the DMA_EARS_EDREQ_8 field. */
mbed_official 324:406fd2029f23 3787 #define BR_DMA_EARS_EDREQ_8(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8))
mbed_official 324:406fd2029f23 3788
mbed_official 324:406fd2029f23 3789 /*! @brief Format value for bitfield DMA_EARS_EDREQ_8. */
mbed_official 324:406fd2029f23 3790 #define BF_DMA_EARS_EDREQ_8(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_8) & BM_DMA_EARS_EDREQ_8)
mbed_official 324:406fd2029f23 3791
mbed_official 324:406fd2029f23 3792 /*! @brief Set the EDREQ_8 field to a new value. */
mbed_official 324:406fd2029f23 3793 #define BW_DMA_EARS_EDREQ_8(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_8) = (v))
mbed_official 324:406fd2029f23 3794 /*@}*/
mbed_official 324:406fd2029f23 3795
mbed_official 324:406fd2029f23 3796 /*!
mbed_official 324:406fd2029f23 3797 * @name Register DMA_EARS, field EDREQ_9[9] (RW)
mbed_official 324:406fd2029f23 3798 *
mbed_official 324:406fd2029f23 3799 * Values:
mbed_official 324:406fd2029f23 3800 * - 0 - Disable asynchronous DMA request for channel 9.
mbed_official 324:406fd2029f23 3801 * - 1 - Enable asynchronous DMA request for channel 9.
mbed_official 324:406fd2029f23 3802 */
mbed_official 324:406fd2029f23 3803 /*@{*/
mbed_official 324:406fd2029f23 3804 #define BP_DMA_EARS_EDREQ_9 (9U) /*!< Bit position for DMA_EARS_EDREQ_9. */
mbed_official 324:406fd2029f23 3805 #define BM_DMA_EARS_EDREQ_9 (0x00000200U) /*!< Bit mask for DMA_EARS_EDREQ_9. */
mbed_official 324:406fd2029f23 3806 #define BS_DMA_EARS_EDREQ_9 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_9. */
mbed_official 324:406fd2029f23 3807
mbed_official 324:406fd2029f23 3808 /*! @brief Read current value of the DMA_EARS_EDREQ_9 field. */
mbed_official 324:406fd2029f23 3809 #define BR_DMA_EARS_EDREQ_9(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9))
mbed_official 324:406fd2029f23 3810
mbed_official 324:406fd2029f23 3811 /*! @brief Format value for bitfield DMA_EARS_EDREQ_9. */
mbed_official 324:406fd2029f23 3812 #define BF_DMA_EARS_EDREQ_9(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_9) & BM_DMA_EARS_EDREQ_9)
mbed_official 324:406fd2029f23 3813
mbed_official 324:406fd2029f23 3814 /*! @brief Set the EDREQ_9 field to a new value. */
mbed_official 324:406fd2029f23 3815 #define BW_DMA_EARS_EDREQ_9(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_9) = (v))
mbed_official 324:406fd2029f23 3816 /*@}*/
mbed_official 324:406fd2029f23 3817
mbed_official 324:406fd2029f23 3818 /*!
mbed_official 324:406fd2029f23 3819 * @name Register DMA_EARS, field EDREQ_10[10] (RW)
mbed_official 324:406fd2029f23 3820 *
mbed_official 324:406fd2029f23 3821 * Values:
mbed_official 324:406fd2029f23 3822 * - 0 - Disable asynchronous DMA request for channel 10.
mbed_official 324:406fd2029f23 3823 * - 1 - Enable asynchronous DMA request for channel 10.
mbed_official 324:406fd2029f23 3824 */
mbed_official 324:406fd2029f23 3825 /*@{*/
mbed_official 324:406fd2029f23 3826 #define BP_DMA_EARS_EDREQ_10 (10U) /*!< Bit position for DMA_EARS_EDREQ_10. */
mbed_official 324:406fd2029f23 3827 #define BM_DMA_EARS_EDREQ_10 (0x00000400U) /*!< Bit mask for DMA_EARS_EDREQ_10. */
mbed_official 324:406fd2029f23 3828 #define BS_DMA_EARS_EDREQ_10 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_10. */
mbed_official 324:406fd2029f23 3829
mbed_official 324:406fd2029f23 3830 /*! @brief Read current value of the DMA_EARS_EDREQ_10 field. */
mbed_official 324:406fd2029f23 3831 #define BR_DMA_EARS_EDREQ_10(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10))
mbed_official 324:406fd2029f23 3832
mbed_official 324:406fd2029f23 3833 /*! @brief Format value for bitfield DMA_EARS_EDREQ_10. */
mbed_official 324:406fd2029f23 3834 #define BF_DMA_EARS_EDREQ_10(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_10) & BM_DMA_EARS_EDREQ_10)
mbed_official 324:406fd2029f23 3835
mbed_official 324:406fd2029f23 3836 /*! @brief Set the EDREQ_10 field to a new value. */
mbed_official 324:406fd2029f23 3837 #define BW_DMA_EARS_EDREQ_10(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_10) = (v))
mbed_official 324:406fd2029f23 3838 /*@}*/
mbed_official 324:406fd2029f23 3839
mbed_official 324:406fd2029f23 3840 /*!
mbed_official 324:406fd2029f23 3841 * @name Register DMA_EARS, field EDREQ_11[11] (RW)
mbed_official 324:406fd2029f23 3842 *
mbed_official 324:406fd2029f23 3843 * Values:
mbed_official 324:406fd2029f23 3844 * - 0 - Disable asynchronous DMA request for channel 11.
mbed_official 324:406fd2029f23 3845 * - 1 - Enable asynchronous DMA request for channel 11.
mbed_official 324:406fd2029f23 3846 */
mbed_official 324:406fd2029f23 3847 /*@{*/
mbed_official 324:406fd2029f23 3848 #define BP_DMA_EARS_EDREQ_11 (11U) /*!< Bit position for DMA_EARS_EDREQ_11. */
mbed_official 324:406fd2029f23 3849 #define BM_DMA_EARS_EDREQ_11 (0x00000800U) /*!< Bit mask for DMA_EARS_EDREQ_11. */
mbed_official 324:406fd2029f23 3850 #define BS_DMA_EARS_EDREQ_11 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_11. */
mbed_official 324:406fd2029f23 3851
mbed_official 324:406fd2029f23 3852 /*! @brief Read current value of the DMA_EARS_EDREQ_11 field. */
mbed_official 324:406fd2029f23 3853 #define BR_DMA_EARS_EDREQ_11(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11))
mbed_official 324:406fd2029f23 3854
mbed_official 324:406fd2029f23 3855 /*! @brief Format value for bitfield DMA_EARS_EDREQ_11. */
mbed_official 324:406fd2029f23 3856 #define BF_DMA_EARS_EDREQ_11(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_11) & BM_DMA_EARS_EDREQ_11)
mbed_official 324:406fd2029f23 3857
mbed_official 324:406fd2029f23 3858 /*! @brief Set the EDREQ_11 field to a new value. */
mbed_official 324:406fd2029f23 3859 #define BW_DMA_EARS_EDREQ_11(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_11) = (v))
mbed_official 324:406fd2029f23 3860 /*@}*/
mbed_official 324:406fd2029f23 3861
mbed_official 324:406fd2029f23 3862 /*!
mbed_official 324:406fd2029f23 3863 * @name Register DMA_EARS, field EDREQ_12[12] (RW)
mbed_official 324:406fd2029f23 3864 *
mbed_official 324:406fd2029f23 3865 * Values:
mbed_official 324:406fd2029f23 3866 * - 0 - Disable asynchronous DMA request for channel 12.
mbed_official 324:406fd2029f23 3867 * - 1 - Enable asynchronous DMA request for channel 12.
mbed_official 324:406fd2029f23 3868 */
mbed_official 324:406fd2029f23 3869 /*@{*/
mbed_official 324:406fd2029f23 3870 #define BP_DMA_EARS_EDREQ_12 (12U) /*!< Bit position for DMA_EARS_EDREQ_12. */
mbed_official 324:406fd2029f23 3871 #define BM_DMA_EARS_EDREQ_12 (0x00001000U) /*!< Bit mask for DMA_EARS_EDREQ_12. */
mbed_official 324:406fd2029f23 3872 #define BS_DMA_EARS_EDREQ_12 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_12. */
mbed_official 324:406fd2029f23 3873
mbed_official 324:406fd2029f23 3874 /*! @brief Read current value of the DMA_EARS_EDREQ_12 field. */
mbed_official 324:406fd2029f23 3875 #define BR_DMA_EARS_EDREQ_12(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12))
mbed_official 324:406fd2029f23 3876
mbed_official 324:406fd2029f23 3877 /*! @brief Format value for bitfield DMA_EARS_EDREQ_12. */
mbed_official 324:406fd2029f23 3878 #define BF_DMA_EARS_EDREQ_12(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_12) & BM_DMA_EARS_EDREQ_12)
mbed_official 324:406fd2029f23 3879
mbed_official 324:406fd2029f23 3880 /*! @brief Set the EDREQ_12 field to a new value. */
mbed_official 324:406fd2029f23 3881 #define BW_DMA_EARS_EDREQ_12(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_12) = (v))
mbed_official 324:406fd2029f23 3882 /*@}*/
mbed_official 324:406fd2029f23 3883
mbed_official 324:406fd2029f23 3884 /*!
mbed_official 324:406fd2029f23 3885 * @name Register DMA_EARS, field EDREQ_13[13] (RW)
mbed_official 324:406fd2029f23 3886 *
mbed_official 324:406fd2029f23 3887 * Values:
mbed_official 324:406fd2029f23 3888 * - 0 - Disable asynchronous DMA request for channel 13.
mbed_official 324:406fd2029f23 3889 * - 1 - Enable asynchronous DMA request for channel 13.
mbed_official 324:406fd2029f23 3890 */
mbed_official 324:406fd2029f23 3891 /*@{*/
mbed_official 324:406fd2029f23 3892 #define BP_DMA_EARS_EDREQ_13 (13U) /*!< Bit position for DMA_EARS_EDREQ_13. */
mbed_official 324:406fd2029f23 3893 #define BM_DMA_EARS_EDREQ_13 (0x00002000U) /*!< Bit mask for DMA_EARS_EDREQ_13. */
mbed_official 324:406fd2029f23 3894 #define BS_DMA_EARS_EDREQ_13 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_13. */
mbed_official 324:406fd2029f23 3895
mbed_official 324:406fd2029f23 3896 /*! @brief Read current value of the DMA_EARS_EDREQ_13 field. */
mbed_official 324:406fd2029f23 3897 #define BR_DMA_EARS_EDREQ_13(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13))
mbed_official 324:406fd2029f23 3898
mbed_official 324:406fd2029f23 3899 /*! @brief Format value for bitfield DMA_EARS_EDREQ_13. */
mbed_official 324:406fd2029f23 3900 #define BF_DMA_EARS_EDREQ_13(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_13) & BM_DMA_EARS_EDREQ_13)
mbed_official 324:406fd2029f23 3901
mbed_official 324:406fd2029f23 3902 /*! @brief Set the EDREQ_13 field to a new value. */
mbed_official 324:406fd2029f23 3903 #define BW_DMA_EARS_EDREQ_13(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_13) = (v))
mbed_official 324:406fd2029f23 3904 /*@}*/
mbed_official 324:406fd2029f23 3905
mbed_official 324:406fd2029f23 3906 /*!
mbed_official 324:406fd2029f23 3907 * @name Register DMA_EARS, field EDREQ_14[14] (RW)
mbed_official 324:406fd2029f23 3908 *
mbed_official 324:406fd2029f23 3909 * Values:
mbed_official 324:406fd2029f23 3910 * - 0 - Disable asynchronous DMA request for channel 14.
mbed_official 324:406fd2029f23 3911 * - 1 - Enable asynchronous DMA request for channel 14.
mbed_official 324:406fd2029f23 3912 */
mbed_official 324:406fd2029f23 3913 /*@{*/
mbed_official 324:406fd2029f23 3914 #define BP_DMA_EARS_EDREQ_14 (14U) /*!< Bit position for DMA_EARS_EDREQ_14. */
mbed_official 324:406fd2029f23 3915 #define BM_DMA_EARS_EDREQ_14 (0x00004000U) /*!< Bit mask for DMA_EARS_EDREQ_14. */
mbed_official 324:406fd2029f23 3916 #define BS_DMA_EARS_EDREQ_14 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_14. */
mbed_official 324:406fd2029f23 3917
mbed_official 324:406fd2029f23 3918 /*! @brief Read current value of the DMA_EARS_EDREQ_14 field. */
mbed_official 324:406fd2029f23 3919 #define BR_DMA_EARS_EDREQ_14(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14))
mbed_official 324:406fd2029f23 3920
mbed_official 324:406fd2029f23 3921 /*! @brief Format value for bitfield DMA_EARS_EDREQ_14. */
mbed_official 324:406fd2029f23 3922 #define BF_DMA_EARS_EDREQ_14(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_14) & BM_DMA_EARS_EDREQ_14)
mbed_official 324:406fd2029f23 3923
mbed_official 324:406fd2029f23 3924 /*! @brief Set the EDREQ_14 field to a new value. */
mbed_official 324:406fd2029f23 3925 #define BW_DMA_EARS_EDREQ_14(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_14) = (v))
mbed_official 324:406fd2029f23 3926 /*@}*/
mbed_official 324:406fd2029f23 3927
mbed_official 324:406fd2029f23 3928 /*!
mbed_official 324:406fd2029f23 3929 * @name Register DMA_EARS, field EDREQ_15[15] (RW)
mbed_official 324:406fd2029f23 3930 *
mbed_official 324:406fd2029f23 3931 * Values:
mbed_official 324:406fd2029f23 3932 * - 0 - Disable asynchronous DMA request for channel 15.
mbed_official 324:406fd2029f23 3933 * - 1 - Enable asynchronous DMA request for channel 15.
mbed_official 324:406fd2029f23 3934 */
mbed_official 324:406fd2029f23 3935 /*@{*/
mbed_official 324:406fd2029f23 3936 #define BP_DMA_EARS_EDREQ_15 (15U) /*!< Bit position for DMA_EARS_EDREQ_15. */
mbed_official 324:406fd2029f23 3937 #define BM_DMA_EARS_EDREQ_15 (0x00008000U) /*!< Bit mask for DMA_EARS_EDREQ_15. */
mbed_official 324:406fd2029f23 3938 #define BS_DMA_EARS_EDREQ_15 (1U) /*!< Bit field size in bits for DMA_EARS_EDREQ_15. */
mbed_official 324:406fd2029f23 3939
mbed_official 324:406fd2029f23 3940 /*! @brief Read current value of the DMA_EARS_EDREQ_15 field. */
mbed_official 324:406fd2029f23 3941 #define BR_DMA_EARS_EDREQ_15(x) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15))
mbed_official 324:406fd2029f23 3942
mbed_official 324:406fd2029f23 3943 /*! @brief Format value for bitfield DMA_EARS_EDREQ_15. */
mbed_official 324:406fd2029f23 3944 #define BF_DMA_EARS_EDREQ_15(v) ((uint32_t)((uint32_t)(v) << BP_DMA_EARS_EDREQ_15) & BM_DMA_EARS_EDREQ_15)
mbed_official 324:406fd2029f23 3945
mbed_official 324:406fd2029f23 3946 /*! @brief Set the EDREQ_15 field to a new value. */
mbed_official 324:406fd2029f23 3947 #define BW_DMA_EARS_EDREQ_15(x, v) (BITBAND_ACCESS32(HW_DMA_EARS_ADDR(x), BP_DMA_EARS_EDREQ_15) = (v))
mbed_official 324:406fd2029f23 3948 /*@}*/
mbed_official 324:406fd2029f23 3949
mbed_official 324:406fd2029f23 3950 /*******************************************************************************
mbed_official 324:406fd2029f23 3951 * HW_DMA_DCHPRIn - Channel n Priority Register
mbed_official 324:406fd2029f23 3952 ******************************************************************************/
mbed_official 324:406fd2029f23 3953
mbed_official 324:406fd2029f23 3954 /*!
mbed_official 324:406fd2029f23 3955 * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
mbed_official 324:406fd2029f23 3956 *
mbed_official 324:406fd2029f23 3957 * Reset value: 0x00U
mbed_official 324:406fd2029f23 3958 *
mbed_official 324:406fd2029f23 3959 * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
mbed_official 324:406fd2029f23 3960 * contents of these registers define the unique priorities associated with each
mbed_official 324:406fd2029f23 3961 * channel . The channel priorities are evaluated by numeric value; for example, 0 is
mbed_official 324:406fd2029f23 3962 * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
mbed_official 324:406fd2029f23 3963 * program the channel priorities with unique values; otherwise, a configuration
mbed_official 324:406fd2029f23 3964 * error is reported. The range of the priority value is limited to the values of 0
mbed_official 324:406fd2029f23 3965 * through 15.
mbed_official 324:406fd2029f23 3966 */
mbed_official 324:406fd2029f23 3967 typedef union _hw_dma_dchprin
mbed_official 324:406fd2029f23 3968 {
mbed_official 324:406fd2029f23 3969 uint8_t U;
mbed_official 324:406fd2029f23 3970 struct _hw_dma_dchprin_bitfields
mbed_official 324:406fd2029f23 3971 {
mbed_official 324:406fd2029f23 3972 uint8_t CHPRI : 4; /*!< [3:0] Channel n Arbitration Priority */
mbed_official 324:406fd2029f23 3973 uint8_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 3974 uint8_t DPA : 1; /*!< [6] Disable Preempt Ability */
mbed_official 324:406fd2029f23 3975 uint8_t ECP : 1; /*!< [7] Enable Channel Preemption */
mbed_official 324:406fd2029f23 3976 } B;
mbed_official 324:406fd2029f23 3977 } hw_dma_dchprin_t;
mbed_official 324:406fd2029f23 3978
mbed_official 324:406fd2029f23 3979 /*!
mbed_official 324:406fd2029f23 3980 * @name Constants and macros for entire DMA_DCHPRIn register
mbed_official 324:406fd2029f23 3981 */
mbed_official 324:406fd2029f23 3982 /*@{*/
mbed_official 324:406fd2029f23 3983 #define HW_DMA_DCHPRIn_COUNT (16U)
mbed_official 324:406fd2029f23 3984
mbed_official 324:406fd2029f23 3985 #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n)))
mbed_official 324:406fd2029f23 3986
mbed_official 324:406fd2029f23 3987 /* DMA channel index to DMA channel priority register array index conversion macro */
mbed_official 324:406fd2029f23 3988 #define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
mbed_official 324:406fd2029f23 3989
mbed_official 324:406fd2029f23 3990 #define HW_DMA_DCHPRIn(x, n) (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
mbed_official 324:406fd2029f23 3991 #define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
mbed_official 324:406fd2029f23 3992 #define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
mbed_official 324:406fd2029f23 3993 #define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 3994 #define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 3995 #define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 3996 /*@}*/
mbed_official 324:406fd2029f23 3997
mbed_official 324:406fd2029f23 3998 /*
mbed_official 324:406fd2029f23 3999 * Constants & macros for individual DMA_DCHPRIn bitfields
mbed_official 324:406fd2029f23 4000 */
mbed_official 324:406fd2029f23 4001
mbed_official 324:406fd2029f23 4002 /*!
mbed_official 324:406fd2029f23 4003 * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
mbed_official 324:406fd2029f23 4004 *
mbed_official 324:406fd2029f23 4005 * Channel priority when fixed-priority arbitration is enabled Reset value for
mbed_official 324:406fd2029f23 4006 * the channel priority fields, CHPRI, is equal to the corresponding channel
mbed_official 324:406fd2029f23 4007 * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
mbed_official 324:406fd2029f23 4008 */
mbed_official 324:406fd2029f23 4009 /*@{*/
mbed_official 324:406fd2029f23 4010 #define BP_DMA_DCHPRIn_CHPRI (0U) /*!< Bit position for DMA_DCHPRIn_CHPRI. */
mbed_official 324:406fd2029f23 4011 #define BM_DMA_DCHPRIn_CHPRI (0x0FU) /*!< Bit mask for DMA_DCHPRIn_CHPRI. */
mbed_official 324:406fd2029f23 4012 #define BS_DMA_DCHPRIn_CHPRI (4U) /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */
mbed_official 324:406fd2029f23 4013
mbed_official 324:406fd2029f23 4014 /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */
mbed_official 324:406fd2029f23 4015 #define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
mbed_official 324:406fd2029f23 4016
mbed_official 324:406fd2029f23 4017 /*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */
mbed_official 324:406fd2029f23 4018 #define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI)
mbed_official 324:406fd2029f23 4019
mbed_official 324:406fd2029f23 4020 /*! @brief Set the CHPRI field to a new value. */
mbed_official 324:406fd2029f23 4021 #define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
mbed_official 324:406fd2029f23 4022 /*@}*/
mbed_official 324:406fd2029f23 4023
mbed_official 324:406fd2029f23 4024 /*!
mbed_official 324:406fd2029f23 4025 * @name Register DMA_DCHPRIn, field DPA[6] (RW)
mbed_official 324:406fd2029f23 4026 *
mbed_official 324:406fd2029f23 4027 * Values:
mbed_official 324:406fd2029f23 4028 * - 0 - Channel n can suspend a lower priority channel
mbed_official 324:406fd2029f23 4029 * - 1 - Channel n cannot suspend any channel, regardless of channel priority
mbed_official 324:406fd2029f23 4030 */
mbed_official 324:406fd2029f23 4031 /*@{*/
mbed_official 324:406fd2029f23 4032 #define BP_DMA_DCHPRIn_DPA (6U) /*!< Bit position for DMA_DCHPRIn_DPA. */
mbed_official 324:406fd2029f23 4033 #define BM_DMA_DCHPRIn_DPA (0x40U) /*!< Bit mask for DMA_DCHPRIn_DPA. */
mbed_official 324:406fd2029f23 4034 #define BS_DMA_DCHPRIn_DPA (1U) /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */
mbed_official 324:406fd2029f23 4035
mbed_official 324:406fd2029f23 4036 /*! @brief Read current value of the DMA_DCHPRIn_DPA field. */
mbed_official 324:406fd2029f23 4037 #define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
mbed_official 324:406fd2029f23 4038
mbed_official 324:406fd2029f23 4039 /*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */
mbed_official 324:406fd2029f23 4040 #define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA)
mbed_official 324:406fd2029f23 4041
mbed_official 324:406fd2029f23 4042 /*! @brief Set the DPA field to a new value. */
mbed_official 324:406fd2029f23 4043 #define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
mbed_official 324:406fd2029f23 4044 /*@}*/
mbed_official 324:406fd2029f23 4045
mbed_official 324:406fd2029f23 4046 /*!
mbed_official 324:406fd2029f23 4047 * @name Register DMA_DCHPRIn, field ECP[7] (RW)
mbed_official 324:406fd2029f23 4048 *
mbed_official 324:406fd2029f23 4049 * Values:
mbed_official 324:406fd2029f23 4050 * - 0 - Channel n cannot be suspended by a higher priority channel's service
mbed_official 324:406fd2029f23 4051 * request
mbed_official 324:406fd2029f23 4052 * - 1 - Channel n can be temporarily suspended by the service request of a
mbed_official 324:406fd2029f23 4053 * higher priority channel
mbed_official 324:406fd2029f23 4054 */
mbed_official 324:406fd2029f23 4055 /*@{*/
mbed_official 324:406fd2029f23 4056 #define BP_DMA_DCHPRIn_ECP (7U) /*!< Bit position for DMA_DCHPRIn_ECP. */
mbed_official 324:406fd2029f23 4057 #define BM_DMA_DCHPRIn_ECP (0x80U) /*!< Bit mask for DMA_DCHPRIn_ECP. */
mbed_official 324:406fd2029f23 4058 #define BS_DMA_DCHPRIn_ECP (1U) /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */
mbed_official 324:406fd2029f23 4059
mbed_official 324:406fd2029f23 4060 /*! @brief Read current value of the DMA_DCHPRIn_ECP field. */
mbed_official 324:406fd2029f23 4061 #define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
mbed_official 324:406fd2029f23 4062
mbed_official 324:406fd2029f23 4063 /*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */
mbed_official 324:406fd2029f23 4064 #define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP)
mbed_official 324:406fd2029f23 4065
mbed_official 324:406fd2029f23 4066 /*! @brief Set the ECP field to a new value. */
mbed_official 324:406fd2029f23 4067 #define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
mbed_official 324:406fd2029f23 4068 /*@}*/
mbed_official 324:406fd2029f23 4069
mbed_official 324:406fd2029f23 4070 /*******************************************************************************
mbed_official 324:406fd2029f23 4071 * HW_DMA_TCDn_SADDR - TCD Source Address
mbed_official 324:406fd2029f23 4072 ******************************************************************************/
mbed_official 324:406fd2029f23 4073
mbed_official 324:406fd2029f23 4074 /*!
mbed_official 324:406fd2029f23 4075 * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
mbed_official 324:406fd2029f23 4076 *
mbed_official 324:406fd2029f23 4077 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4078 */
mbed_official 324:406fd2029f23 4079 typedef union _hw_dma_tcdn_saddr
mbed_official 324:406fd2029f23 4080 {
mbed_official 324:406fd2029f23 4081 uint32_t U;
mbed_official 324:406fd2029f23 4082 struct _hw_dma_tcdn_saddr_bitfields
mbed_official 324:406fd2029f23 4083 {
mbed_official 324:406fd2029f23 4084 uint32_t SADDR : 32; /*!< [31:0] Source Address */
mbed_official 324:406fd2029f23 4085 } B;
mbed_official 324:406fd2029f23 4086 } hw_dma_tcdn_saddr_t;
mbed_official 324:406fd2029f23 4087
mbed_official 324:406fd2029f23 4088 /*!
mbed_official 324:406fd2029f23 4089 * @name Constants and macros for entire DMA_TCDn_SADDR register
mbed_official 324:406fd2029f23 4090 */
mbed_official 324:406fd2029f23 4091 /*@{*/
mbed_official 324:406fd2029f23 4092 #define HW_DMA_TCDn_SADDR_COUNT (16U)
mbed_official 324:406fd2029f23 4093
mbed_official 324:406fd2029f23 4094 #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4095
mbed_official 324:406fd2029f23 4096 #define HW_DMA_TCDn_SADDR(x, n) (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
mbed_official 324:406fd2029f23 4097 #define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
mbed_official 324:406fd2029f23 4098 #define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
mbed_official 324:406fd2029f23 4099 #define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4100 #define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4101 #define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4102 /*@}*/
mbed_official 324:406fd2029f23 4103
mbed_official 324:406fd2029f23 4104 /*
mbed_official 324:406fd2029f23 4105 * Constants & macros for individual DMA_TCDn_SADDR bitfields
mbed_official 324:406fd2029f23 4106 */
mbed_official 324:406fd2029f23 4107
mbed_official 324:406fd2029f23 4108 /*!
mbed_official 324:406fd2029f23 4109 * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
mbed_official 324:406fd2029f23 4110 *
mbed_official 324:406fd2029f23 4111 * Memory address pointing to the source data.
mbed_official 324:406fd2029f23 4112 */
mbed_official 324:406fd2029f23 4113 /*@{*/
mbed_official 324:406fd2029f23 4114 #define BP_DMA_TCDn_SADDR_SADDR (0U) /*!< Bit position for DMA_TCDn_SADDR_SADDR. */
mbed_official 324:406fd2029f23 4115 #define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */
mbed_official 324:406fd2029f23 4116 #define BS_DMA_TCDn_SADDR_SADDR (32U) /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */
mbed_official 324:406fd2029f23 4117
mbed_official 324:406fd2029f23 4118 /*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */
mbed_official 324:406fd2029f23 4119 #define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
mbed_official 324:406fd2029f23 4120
mbed_official 324:406fd2029f23 4121 /*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */
mbed_official 324:406fd2029f23 4122 #define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR)
mbed_official 324:406fd2029f23 4123
mbed_official 324:406fd2029f23 4124 /*! @brief Set the SADDR field to a new value. */
mbed_official 324:406fd2029f23 4125 #define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
mbed_official 324:406fd2029f23 4126 /*@}*/
mbed_official 324:406fd2029f23 4127 /*******************************************************************************
mbed_official 324:406fd2029f23 4128 * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
mbed_official 324:406fd2029f23 4129 ******************************************************************************/
mbed_official 324:406fd2029f23 4130
mbed_official 324:406fd2029f23 4131 /*!
mbed_official 324:406fd2029f23 4132 * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
mbed_official 324:406fd2029f23 4133 *
mbed_official 324:406fd2029f23 4134 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 4135 */
mbed_official 324:406fd2029f23 4136 typedef union _hw_dma_tcdn_soff
mbed_official 324:406fd2029f23 4137 {
mbed_official 324:406fd2029f23 4138 uint16_t U;
mbed_official 324:406fd2029f23 4139 struct _hw_dma_tcdn_soff_bitfields
mbed_official 324:406fd2029f23 4140 {
mbed_official 324:406fd2029f23 4141 uint16_t SOFF : 16; /*!< [15:0] Source address signed offset */
mbed_official 324:406fd2029f23 4142 } B;
mbed_official 324:406fd2029f23 4143 } hw_dma_tcdn_soff_t;
mbed_official 324:406fd2029f23 4144
mbed_official 324:406fd2029f23 4145 /*!
mbed_official 324:406fd2029f23 4146 * @name Constants and macros for entire DMA_TCDn_SOFF register
mbed_official 324:406fd2029f23 4147 */
mbed_official 324:406fd2029f23 4148 /*@{*/
mbed_official 324:406fd2029f23 4149 #define HW_DMA_TCDn_SOFF_COUNT (16U)
mbed_official 324:406fd2029f23 4150
mbed_official 324:406fd2029f23 4151 #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4152
mbed_official 324:406fd2029f23 4153 #define HW_DMA_TCDn_SOFF(x, n) (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
mbed_official 324:406fd2029f23 4154 #define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
mbed_official 324:406fd2029f23 4155 #define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
mbed_official 324:406fd2029f23 4156 #define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4157 #define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4158 #define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4159 /*@}*/
mbed_official 324:406fd2029f23 4160
mbed_official 324:406fd2029f23 4161 /*
mbed_official 324:406fd2029f23 4162 * Constants & macros for individual DMA_TCDn_SOFF bitfields
mbed_official 324:406fd2029f23 4163 */
mbed_official 324:406fd2029f23 4164
mbed_official 324:406fd2029f23 4165 /*!
mbed_official 324:406fd2029f23 4166 * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
mbed_official 324:406fd2029f23 4167 *
mbed_official 324:406fd2029f23 4168 * Sign-extended offset applied to the current source address to form the
mbed_official 324:406fd2029f23 4169 * next-state value as each source read is completed.
mbed_official 324:406fd2029f23 4170 */
mbed_official 324:406fd2029f23 4171 /*@{*/
mbed_official 324:406fd2029f23 4172 #define BP_DMA_TCDn_SOFF_SOFF (0U) /*!< Bit position for DMA_TCDn_SOFF_SOFF. */
mbed_official 324:406fd2029f23 4173 #define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */
mbed_official 324:406fd2029f23 4174 #define BS_DMA_TCDn_SOFF_SOFF (16U) /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */
mbed_official 324:406fd2029f23 4175
mbed_official 324:406fd2029f23 4176 /*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */
mbed_official 324:406fd2029f23 4177 #define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
mbed_official 324:406fd2029f23 4178
mbed_official 324:406fd2029f23 4179 /*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */
mbed_official 324:406fd2029f23 4180 #define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF)
mbed_official 324:406fd2029f23 4181
mbed_official 324:406fd2029f23 4182 /*! @brief Set the SOFF field to a new value. */
mbed_official 324:406fd2029f23 4183 #define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
mbed_official 324:406fd2029f23 4184 /*@}*/
mbed_official 324:406fd2029f23 4185 /*******************************************************************************
mbed_official 324:406fd2029f23 4186 * HW_DMA_TCDn_ATTR - TCD Transfer Attributes
mbed_official 324:406fd2029f23 4187 ******************************************************************************/
mbed_official 324:406fd2029f23 4188
mbed_official 324:406fd2029f23 4189 /*!
mbed_official 324:406fd2029f23 4190 * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
mbed_official 324:406fd2029f23 4191 *
mbed_official 324:406fd2029f23 4192 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 4193 */
mbed_official 324:406fd2029f23 4194 typedef union _hw_dma_tcdn_attr
mbed_official 324:406fd2029f23 4195 {
mbed_official 324:406fd2029f23 4196 uint16_t U;
mbed_official 324:406fd2029f23 4197 struct _hw_dma_tcdn_attr_bitfields
mbed_official 324:406fd2029f23 4198 {
mbed_official 324:406fd2029f23 4199 uint16_t DSIZE : 3; /*!< [2:0] Destination Data Transfer Size */
mbed_official 324:406fd2029f23 4200 uint16_t DMOD : 5; /*!< [7:3] Destination Address Modulo */
mbed_official 324:406fd2029f23 4201 uint16_t SSIZE : 3; /*!< [10:8] Source data transfer size */
mbed_official 324:406fd2029f23 4202 uint16_t SMOD : 5; /*!< [15:11] Source Address Modulo. */
mbed_official 324:406fd2029f23 4203 } B;
mbed_official 324:406fd2029f23 4204 } hw_dma_tcdn_attr_t;
mbed_official 324:406fd2029f23 4205
mbed_official 324:406fd2029f23 4206 /*!
mbed_official 324:406fd2029f23 4207 * @name Constants and macros for entire DMA_TCDn_ATTR register
mbed_official 324:406fd2029f23 4208 */
mbed_official 324:406fd2029f23 4209 /*@{*/
mbed_official 324:406fd2029f23 4210 #define HW_DMA_TCDn_ATTR_COUNT (16U)
mbed_official 324:406fd2029f23 4211
mbed_official 324:406fd2029f23 4212 #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4213
mbed_official 324:406fd2029f23 4214 #define HW_DMA_TCDn_ATTR(x, n) (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
mbed_official 324:406fd2029f23 4215 #define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
mbed_official 324:406fd2029f23 4216 #define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
mbed_official 324:406fd2029f23 4217 #define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4218 #define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4219 #define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4220 /*@}*/
mbed_official 324:406fd2029f23 4221
mbed_official 324:406fd2029f23 4222 /*
mbed_official 324:406fd2029f23 4223 * Constants & macros for individual DMA_TCDn_ATTR bitfields
mbed_official 324:406fd2029f23 4224 */
mbed_official 324:406fd2029f23 4225
mbed_official 324:406fd2029f23 4226 /*!
mbed_official 324:406fd2029f23 4227 * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
mbed_official 324:406fd2029f23 4228 *
mbed_official 324:406fd2029f23 4229 * See the SSIZE definition
mbed_official 324:406fd2029f23 4230 */
mbed_official 324:406fd2029f23 4231 /*@{*/
mbed_official 324:406fd2029f23 4232 #define BP_DMA_TCDn_ATTR_DSIZE (0U) /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */
mbed_official 324:406fd2029f23 4233 #define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */
mbed_official 324:406fd2029f23 4234 #define BS_DMA_TCDn_ATTR_DSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */
mbed_official 324:406fd2029f23 4235
mbed_official 324:406fd2029f23 4236 /*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */
mbed_official 324:406fd2029f23 4237 #define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
mbed_official 324:406fd2029f23 4238
mbed_official 324:406fd2029f23 4239 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */
mbed_official 324:406fd2029f23 4240 #define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE)
mbed_official 324:406fd2029f23 4241
mbed_official 324:406fd2029f23 4242 /*! @brief Set the DSIZE field to a new value. */
mbed_official 324:406fd2029f23 4243 #define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
mbed_official 324:406fd2029f23 4244 /*@}*/
mbed_official 324:406fd2029f23 4245
mbed_official 324:406fd2029f23 4246 /*!
mbed_official 324:406fd2029f23 4247 * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
mbed_official 324:406fd2029f23 4248 *
mbed_official 324:406fd2029f23 4249 * See the SMOD definition
mbed_official 324:406fd2029f23 4250 */
mbed_official 324:406fd2029f23 4251 /*@{*/
mbed_official 324:406fd2029f23 4252 #define BP_DMA_TCDn_ATTR_DMOD (3U) /*!< Bit position for DMA_TCDn_ATTR_DMOD. */
mbed_official 324:406fd2029f23 4253 #define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */
mbed_official 324:406fd2029f23 4254 #define BS_DMA_TCDn_ATTR_DMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */
mbed_official 324:406fd2029f23 4255
mbed_official 324:406fd2029f23 4256 /*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */
mbed_official 324:406fd2029f23 4257 #define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
mbed_official 324:406fd2029f23 4258
mbed_official 324:406fd2029f23 4259 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */
mbed_official 324:406fd2029f23 4260 #define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD)
mbed_official 324:406fd2029f23 4261
mbed_official 324:406fd2029f23 4262 /*! @brief Set the DMOD field to a new value. */
mbed_official 324:406fd2029f23 4263 #define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
mbed_official 324:406fd2029f23 4264 /*@}*/
mbed_official 324:406fd2029f23 4265
mbed_official 324:406fd2029f23 4266 /*!
mbed_official 324:406fd2029f23 4267 * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
mbed_official 324:406fd2029f23 4268 *
mbed_official 324:406fd2029f23 4269 * The attempted use of a Reserved encoding causes a configuration error.
mbed_official 324:406fd2029f23 4270 *
mbed_official 324:406fd2029f23 4271 * Values:
mbed_official 324:406fd2029f23 4272 * - 000 - 8-bit
mbed_official 324:406fd2029f23 4273 * - 001 - 16-bit
mbed_official 324:406fd2029f23 4274 * - 010 - 32-bit
mbed_official 324:406fd2029f23 4275 * - 011 - Reserved
mbed_official 324:406fd2029f23 4276 * - 100 - 16-byte
mbed_official 324:406fd2029f23 4277 * - 101 - 32-byte
mbed_official 324:406fd2029f23 4278 * - 110 - Reserved
mbed_official 324:406fd2029f23 4279 * - 111 - Reserved
mbed_official 324:406fd2029f23 4280 */
mbed_official 324:406fd2029f23 4281 /*@{*/
mbed_official 324:406fd2029f23 4282 #define BP_DMA_TCDn_ATTR_SSIZE (8U) /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */
mbed_official 324:406fd2029f23 4283 #define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */
mbed_official 324:406fd2029f23 4284 #define BS_DMA_TCDn_ATTR_SSIZE (3U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */
mbed_official 324:406fd2029f23 4285
mbed_official 324:406fd2029f23 4286 /*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */
mbed_official 324:406fd2029f23 4287 #define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
mbed_official 324:406fd2029f23 4288
mbed_official 324:406fd2029f23 4289 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */
mbed_official 324:406fd2029f23 4290 #define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE)
mbed_official 324:406fd2029f23 4291
mbed_official 324:406fd2029f23 4292 /*! @brief Set the SSIZE field to a new value. */
mbed_official 324:406fd2029f23 4293 #define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
mbed_official 324:406fd2029f23 4294 /*@}*/
mbed_official 324:406fd2029f23 4295
mbed_official 324:406fd2029f23 4296 /*!
mbed_official 324:406fd2029f23 4297 * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
mbed_official 324:406fd2029f23 4298 *
mbed_official 324:406fd2029f23 4299 * Values:
mbed_official 324:406fd2029f23 4300 * - 0 - Source address modulo feature is disabled
mbed_official 324:406fd2029f23 4301 */
mbed_official 324:406fd2029f23 4302 /*@{*/
mbed_official 324:406fd2029f23 4303 #define BP_DMA_TCDn_ATTR_SMOD (11U) /*!< Bit position for DMA_TCDn_ATTR_SMOD. */
mbed_official 324:406fd2029f23 4304 #define BM_DMA_TCDn_ATTR_SMOD (0xF800U) /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */
mbed_official 324:406fd2029f23 4305 #define BS_DMA_TCDn_ATTR_SMOD (5U) /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */
mbed_official 324:406fd2029f23 4306
mbed_official 324:406fd2029f23 4307 /*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */
mbed_official 324:406fd2029f23 4308 #define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
mbed_official 324:406fd2029f23 4309
mbed_official 324:406fd2029f23 4310 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */
mbed_official 324:406fd2029f23 4311 #define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD)
mbed_official 324:406fd2029f23 4312
mbed_official 324:406fd2029f23 4313 /*! @brief Set the SMOD field to a new value. */
mbed_official 324:406fd2029f23 4314 #define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
mbed_official 324:406fd2029f23 4315 /*@}*/
mbed_official 324:406fd2029f23 4316 /*******************************************************************************
mbed_official 324:406fd2029f23 4317 * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
mbed_official 324:406fd2029f23 4318 ******************************************************************************/
mbed_official 324:406fd2029f23 4319
mbed_official 324:406fd2029f23 4320 /*!
mbed_official 324:406fd2029f23 4321 * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
mbed_official 324:406fd2029f23 4322 *
mbed_official 324:406fd2029f23 4323 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4324 *
mbed_official 324:406fd2029f23 4325 * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
mbed_official 324:406fd2029f23 4326 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
mbed_official 324:406fd2029f23 4327 * register to use depends on whether minor loop mapping is disabled, enabled but not
mbed_official 324:406fd2029f23 4328 * used for this channel, or enabled and used. TCD word 2 is defined as follows
mbed_official 324:406fd2029f23 4329 * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
mbed_official 324:406fd2029f23 4330 * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
mbed_official 324:406fd2029f23 4331 * for TCD word 2's definition.
mbed_official 324:406fd2029f23 4332 */
mbed_official 324:406fd2029f23 4333 typedef union _hw_dma_tcdn_nbytes_mlno
mbed_official 324:406fd2029f23 4334 {
mbed_official 324:406fd2029f23 4335 uint32_t U;
mbed_official 324:406fd2029f23 4336 struct _hw_dma_tcdn_nbytes_mlno_bitfields
mbed_official 324:406fd2029f23 4337 {
mbed_official 324:406fd2029f23 4338 uint32_t NBYTES : 32; /*!< [31:0] Minor Byte Transfer Count */
mbed_official 324:406fd2029f23 4339 } B;
mbed_official 324:406fd2029f23 4340 } hw_dma_tcdn_nbytes_mlno_t;
mbed_official 324:406fd2029f23 4341
mbed_official 324:406fd2029f23 4342 /*!
mbed_official 324:406fd2029f23 4343 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
mbed_official 324:406fd2029f23 4344 */
mbed_official 324:406fd2029f23 4345 /*@{*/
mbed_official 324:406fd2029f23 4346 #define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
mbed_official 324:406fd2029f23 4347
mbed_official 324:406fd2029f23 4348 #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4349
mbed_official 324:406fd2029f23 4350 #define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
mbed_official 324:406fd2029f23 4351 #define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
mbed_official 324:406fd2029f23 4352 #define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
mbed_official 324:406fd2029f23 4353 #define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4354 #define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4355 #define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4356 /*@}*/
mbed_official 324:406fd2029f23 4357
mbed_official 324:406fd2029f23 4358 /*
mbed_official 324:406fd2029f23 4359 * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
mbed_official 324:406fd2029f23 4360 */
mbed_official 324:406fd2029f23 4361
mbed_official 324:406fd2029f23 4362 /*!
mbed_official 324:406fd2029f23 4363 * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
mbed_official 324:406fd2029f23 4364 *
mbed_official 324:406fd2029f23 4365 * Number of bytes to be transferred in each service request of the channel. As
mbed_official 324:406fd2029f23 4366 * a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official 324:406fd2029f23 4367 * and the appropriate reads and writes perform until the minor byte transfer
mbed_official 324:406fd2029f23 4368 * count has transferred. This is an indivisible operation and cannot be halted.
mbed_official 324:406fd2029f23 4369 * (Although, it may be stalled by using the bandwidth control field, or via
mbed_official 324:406fd2029f23 4370 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
mbed_official 324:406fd2029f23 4371 * written back into the TCD memory, the major iteration count is decremented and
mbed_official 324:406fd2029f23 4372 * restored to the TCD memory. If the major iteration count is completed, additional
mbed_official 324:406fd2029f23 4373 * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
mbed_official 324:406fd2029f23 4374 * GB transfer.
mbed_official 324:406fd2029f23 4375 */
mbed_official 324:406fd2029f23 4376 /*@{*/
mbed_official 324:406fd2029f23 4377 #define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */
mbed_official 324:406fd2029f23 4378 #define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */
mbed_official 324:406fd2029f23 4379 #define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */
mbed_official 324:406fd2029f23 4380
mbed_official 324:406fd2029f23 4381 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */
mbed_official 324:406fd2029f23 4382 #define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
mbed_official 324:406fd2029f23 4383
mbed_official 324:406fd2029f23 4384 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */
mbed_official 324:406fd2029f23 4385 #define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
mbed_official 324:406fd2029f23 4386
mbed_official 324:406fd2029f23 4387 /*! @brief Set the NBYTES field to a new value. */
mbed_official 324:406fd2029f23 4388 #define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
mbed_official 324:406fd2029f23 4389 /*@}*/
mbed_official 324:406fd2029f23 4390 /*******************************************************************************
mbed_official 324:406fd2029f23 4391 * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
mbed_official 324:406fd2029f23 4392 ******************************************************************************/
mbed_official 324:406fd2029f23 4393
mbed_official 324:406fd2029f23 4394 /*!
mbed_official 324:406fd2029f23 4395 * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
mbed_official 324:406fd2029f23 4396 *
mbed_official 324:406fd2029f23 4397 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4398 *
mbed_official 324:406fd2029f23 4399 * One of three registers (this register, TCD_NBYTES_MLNO, or
mbed_official 324:406fd2029f23 4400 * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
mbed_official 324:406fd2029f23 4401 * depends on whether minor loop mapping is disabled, enabled but not used for
mbed_official 324:406fd2029f23 4402 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
mbed_official 324:406fd2029f23 4403 * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
mbed_official 324:406fd2029f23 4404 * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
mbed_official 324:406fd2029f23 4405 * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
mbed_official 324:406fd2029f23 4406 * the TCD_NBYTES_MLNO register description.
mbed_official 324:406fd2029f23 4407 */
mbed_official 324:406fd2029f23 4408 typedef union _hw_dma_tcdn_nbytes_mloffno
mbed_official 324:406fd2029f23 4409 {
mbed_official 324:406fd2029f23 4410 uint32_t U;
mbed_official 324:406fd2029f23 4411 struct _hw_dma_tcdn_nbytes_mloffno_bitfields
mbed_official 324:406fd2029f23 4412 {
mbed_official 324:406fd2029f23 4413 uint32_t NBYTES : 30; /*!< [29:0] Minor Byte Transfer Count */
mbed_official 324:406fd2029f23 4414 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
mbed_official 324:406fd2029f23 4415 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
mbed_official 324:406fd2029f23 4416 } B;
mbed_official 324:406fd2029f23 4417 } hw_dma_tcdn_nbytes_mloffno_t;
mbed_official 324:406fd2029f23 4418
mbed_official 324:406fd2029f23 4419 /*!
mbed_official 324:406fd2029f23 4420 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
mbed_official 324:406fd2029f23 4421 */
mbed_official 324:406fd2029f23 4422 /*@{*/
mbed_official 324:406fd2029f23 4423 #define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
mbed_official 324:406fd2029f23 4424
mbed_official 324:406fd2029f23 4425 #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4426
mbed_official 324:406fd2029f23 4427 #define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
mbed_official 324:406fd2029f23 4428 #define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
mbed_official 324:406fd2029f23 4429 #define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
mbed_official 324:406fd2029f23 4430 #define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4431 #define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4432 #define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4433 /*@}*/
mbed_official 324:406fd2029f23 4434
mbed_official 324:406fd2029f23 4435 /*
mbed_official 324:406fd2029f23 4436 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
mbed_official 324:406fd2029f23 4437 */
mbed_official 324:406fd2029f23 4438
mbed_official 324:406fd2029f23 4439 /*!
mbed_official 324:406fd2029f23 4440 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
mbed_official 324:406fd2029f23 4441 *
mbed_official 324:406fd2029f23 4442 * Number of bytes to be transferred in each service request of the channel. As
mbed_official 324:406fd2029f23 4443 * a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official 324:406fd2029f23 4444 * and the appropriate reads and writes perform until the minor byte transfer
mbed_official 324:406fd2029f23 4445 * count has transferred. This is an indivisible operation and cannot be halted;
mbed_official 324:406fd2029f23 4446 * although, it may be stalled by using the bandwidth control field, or via
mbed_official 324:406fd2029f23 4447 * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
mbed_official 324:406fd2029f23 4448 * back into the TCD memory, the major iteration count is decremented and
mbed_official 324:406fd2029f23 4449 * restored to the TCD memory. If the major iteration count is completed, additional
mbed_official 324:406fd2029f23 4450 * processing is performed.
mbed_official 324:406fd2029f23 4451 */
mbed_official 324:406fd2029f23 4452 /*@{*/
mbed_official 324:406fd2029f23 4453 #define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
mbed_official 324:406fd2029f23 4454 #define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
mbed_official 324:406fd2029f23 4455 #define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
mbed_official 324:406fd2029f23 4456
mbed_official 324:406fd2029f23 4457 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */
mbed_official 324:406fd2029f23 4458 #define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
mbed_official 324:406fd2029f23 4459
mbed_official 324:406fd2029f23 4460 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
mbed_official 324:406fd2029f23 4461 #define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
mbed_official 324:406fd2029f23 4462
mbed_official 324:406fd2029f23 4463 /*! @brief Set the NBYTES field to a new value. */
mbed_official 324:406fd2029f23 4464 #define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
mbed_official 324:406fd2029f23 4465 /*@}*/
mbed_official 324:406fd2029f23 4466
mbed_official 324:406fd2029f23 4467 /*!
mbed_official 324:406fd2029f23 4468 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
mbed_official 324:406fd2029f23 4469 *
mbed_official 324:406fd2029f23 4470 * Selects whether the minor loop offset is applied to the destination address
mbed_official 324:406fd2029f23 4471 * upon minor loop completion.
mbed_official 324:406fd2029f23 4472 *
mbed_official 324:406fd2029f23 4473 * Values:
mbed_official 324:406fd2029f23 4474 * - 0 - The minor loop offset is not applied to the DADDR
mbed_official 324:406fd2029f23 4475 * - 1 - The minor loop offset is applied to the DADDR
mbed_official 324:406fd2029f23 4476 */
mbed_official 324:406fd2029f23 4477 /*@{*/
mbed_official 324:406fd2029f23 4478 #define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
mbed_official 324:406fd2029f23 4479 #define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
mbed_official 324:406fd2029f23 4480 #define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
mbed_official 324:406fd2029f23 4481
mbed_official 324:406fd2029f23 4482 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */
mbed_official 324:406fd2029f23 4483 #define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
mbed_official 324:406fd2029f23 4484
mbed_official 324:406fd2029f23 4485 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
mbed_official 324:406fd2029f23 4486 #define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
mbed_official 324:406fd2029f23 4487
mbed_official 324:406fd2029f23 4488 /*! @brief Set the DMLOE field to a new value. */
mbed_official 324:406fd2029f23 4489 #define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
mbed_official 324:406fd2029f23 4490 /*@}*/
mbed_official 324:406fd2029f23 4491
mbed_official 324:406fd2029f23 4492 /*!
mbed_official 324:406fd2029f23 4493 * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
mbed_official 324:406fd2029f23 4494 *
mbed_official 324:406fd2029f23 4495 * Selects whether the minor loop offset is applied to the source address upon
mbed_official 324:406fd2029f23 4496 * minor loop completion.
mbed_official 324:406fd2029f23 4497 *
mbed_official 324:406fd2029f23 4498 * Values:
mbed_official 324:406fd2029f23 4499 * - 0 - The minor loop offset is not applied to the SADDR
mbed_official 324:406fd2029f23 4500 * - 1 - The minor loop offset is applied to the SADDR
mbed_official 324:406fd2029f23 4501 */
mbed_official 324:406fd2029f23 4502 /*@{*/
mbed_official 324:406fd2029f23 4503 #define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
mbed_official 324:406fd2029f23 4504 #define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
mbed_official 324:406fd2029f23 4505 #define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
mbed_official 324:406fd2029f23 4506
mbed_official 324:406fd2029f23 4507 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */
mbed_official 324:406fd2029f23 4508 #define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
mbed_official 324:406fd2029f23 4509
mbed_official 324:406fd2029f23 4510 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
mbed_official 324:406fd2029f23 4511 #define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
mbed_official 324:406fd2029f23 4512
mbed_official 324:406fd2029f23 4513 /*! @brief Set the SMLOE field to a new value. */
mbed_official 324:406fd2029f23 4514 #define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
mbed_official 324:406fd2029f23 4515 /*@}*/
mbed_official 324:406fd2029f23 4516 /*******************************************************************************
mbed_official 324:406fd2029f23 4517 * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
mbed_official 324:406fd2029f23 4518 ******************************************************************************/
mbed_official 324:406fd2029f23 4519
mbed_official 324:406fd2029f23 4520 /*!
mbed_official 324:406fd2029f23 4521 * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
mbed_official 324:406fd2029f23 4522 *
mbed_official 324:406fd2029f23 4523 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4524 *
mbed_official 324:406fd2029f23 4525 * One of three registers (this register, TCD_NBYTES_MLNO, or
mbed_official 324:406fd2029f23 4526 * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
mbed_official 324:406fd2029f23 4527 * depends on whether minor loop mapping is disabled, enabled but not used for
mbed_official 324:406fd2029f23 4528 * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
mbed_official 324:406fd2029f23 4529 * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
mbed_official 324:406fd2029f23 4530 * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
mbed_official 324:406fd2029f23 4531 * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
mbed_official 324:406fd2029f23 4532 * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
mbed_official 324:406fd2029f23 4533 */
mbed_official 324:406fd2029f23 4534 typedef union _hw_dma_tcdn_nbytes_mloffyes
mbed_official 324:406fd2029f23 4535 {
mbed_official 324:406fd2029f23 4536 uint32_t U;
mbed_official 324:406fd2029f23 4537 struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
mbed_official 324:406fd2029f23 4538 {
mbed_official 324:406fd2029f23 4539 uint32_t NBYTES : 10; /*!< [9:0] Minor Byte Transfer Count */
mbed_official 324:406fd2029f23 4540 uint32_t MLOFF : 20; /*!< [29:10] If SMLOE or DMLOE is set, this
mbed_official 324:406fd2029f23 4541 * field represents a sign-extended offset applied to the source or destination
mbed_official 324:406fd2029f23 4542 * address to form the next-state value after the minor loop completes. */
mbed_official 324:406fd2029f23 4543 uint32_t DMLOE : 1; /*!< [30] Destination Minor Loop Offset enable */
mbed_official 324:406fd2029f23 4544 uint32_t SMLOE : 1; /*!< [31] Source Minor Loop Offset Enable */
mbed_official 324:406fd2029f23 4545 } B;
mbed_official 324:406fd2029f23 4546 } hw_dma_tcdn_nbytes_mloffyes_t;
mbed_official 324:406fd2029f23 4547
mbed_official 324:406fd2029f23 4548 /*!
mbed_official 324:406fd2029f23 4549 * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
mbed_official 324:406fd2029f23 4550 */
mbed_official 324:406fd2029f23 4551 /*@{*/
mbed_official 324:406fd2029f23 4552 #define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
mbed_official 324:406fd2029f23 4553
mbed_official 324:406fd2029f23 4554 #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4555
mbed_official 324:406fd2029f23 4556 #define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
mbed_official 324:406fd2029f23 4557 #define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
mbed_official 324:406fd2029f23 4558 #define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
mbed_official 324:406fd2029f23 4559 #define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4560 #define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4561 #define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4562 /*@}*/
mbed_official 324:406fd2029f23 4563
mbed_official 324:406fd2029f23 4564 /*
mbed_official 324:406fd2029f23 4565 * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
mbed_official 324:406fd2029f23 4566 */
mbed_official 324:406fd2029f23 4567
mbed_official 324:406fd2029f23 4568 /*!
mbed_official 324:406fd2029f23 4569 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
mbed_official 324:406fd2029f23 4570 *
mbed_official 324:406fd2029f23 4571 * Number of bytes to be transferred in each service request of the channel. As
mbed_official 324:406fd2029f23 4572 * a channel activates, the appropriate TCD contents load into the eDMA engine,
mbed_official 324:406fd2029f23 4573 * and the appropriate reads and writes perform until the minor byte transfer
mbed_official 324:406fd2029f23 4574 * count has transferred. This is an indivisible operation and cannot be halted.
mbed_official 324:406fd2029f23 4575 * (Although, it may be stalled by using the bandwidth control field, or via
mbed_official 324:406fd2029f23 4576 * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
mbed_official 324:406fd2029f23 4577 * written back into the TCD memory, the major iteration count is decremented and
mbed_official 324:406fd2029f23 4578 * restored to the TCD memory. If the major iteration count is completed, additional
mbed_official 324:406fd2029f23 4579 * processing is performed.
mbed_official 324:406fd2029f23 4580 */
mbed_official 324:406fd2029f23 4581 /*@{*/
mbed_official 324:406fd2029f23 4582 #define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
mbed_official 324:406fd2029f23 4583 #define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
mbed_official 324:406fd2029f23 4584 #define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
mbed_official 324:406fd2029f23 4585
mbed_official 324:406fd2029f23 4586 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */
mbed_official 324:406fd2029f23 4587 #define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
mbed_official 324:406fd2029f23 4588
mbed_official 324:406fd2029f23 4589 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
mbed_official 324:406fd2029f23 4590 #define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
mbed_official 324:406fd2029f23 4591
mbed_official 324:406fd2029f23 4592 /*! @brief Set the NBYTES field to a new value. */
mbed_official 324:406fd2029f23 4593 #define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
mbed_official 324:406fd2029f23 4594 /*@}*/
mbed_official 324:406fd2029f23 4595
mbed_official 324:406fd2029f23 4596 /*!
mbed_official 324:406fd2029f23 4597 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
mbed_official 324:406fd2029f23 4598 */
mbed_official 324:406fd2029f23 4599 /*@{*/
mbed_official 324:406fd2029f23 4600 #define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
mbed_official 324:406fd2029f23 4601 #define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
mbed_official 324:406fd2029f23 4602 #define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
mbed_official 324:406fd2029f23 4603
mbed_official 324:406fd2029f23 4604 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */
mbed_official 324:406fd2029f23 4605 #define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
mbed_official 324:406fd2029f23 4606
mbed_official 324:406fd2029f23 4607 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
mbed_official 324:406fd2029f23 4608 #define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
mbed_official 324:406fd2029f23 4609
mbed_official 324:406fd2029f23 4610 /*! @brief Set the MLOFF field to a new value. */
mbed_official 324:406fd2029f23 4611 #define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
mbed_official 324:406fd2029f23 4612 /*@}*/
mbed_official 324:406fd2029f23 4613
mbed_official 324:406fd2029f23 4614 /*!
mbed_official 324:406fd2029f23 4615 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
mbed_official 324:406fd2029f23 4616 *
mbed_official 324:406fd2029f23 4617 * Selects whether the minor loop offset is applied to the destination address
mbed_official 324:406fd2029f23 4618 * upon minor loop completion.
mbed_official 324:406fd2029f23 4619 *
mbed_official 324:406fd2029f23 4620 * Values:
mbed_official 324:406fd2029f23 4621 * - 0 - The minor loop offset is not applied to the DADDR
mbed_official 324:406fd2029f23 4622 * - 1 - The minor loop offset is applied to the DADDR
mbed_official 324:406fd2029f23 4623 */
mbed_official 324:406fd2029f23 4624 /*@{*/
mbed_official 324:406fd2029f23 4625 #define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
mbed_official 324:406fd2029f23 4626 #define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
mbed_official 324:406fd2029f23 4627 #define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
mbed_official 324:406fd2029f23 4628
mbed_official 324:406fd2029f23 4629 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */
mbed_official 324:406fd2029f23 4630 #define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
mbed_official 324:406fd2029f23 4631
mbed_official 324:406fd2029f23 4632 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
mbed_official 324:406fd2029f23 4633 #define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
mbed_official 324:406fd2029f23 4634
mbed_official 324:406fd2029f23 4635 /*! @brief Set the DMLOE field to a new value. */
mbed_official 324:406fd2029f23 4636 #define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
mbed_official 324:406fd2029f23 4637 /*@}*/
mbed_official 324:406fd2029f23 4638
mbed_official 324:406fd2029f23 4639 /*!
mbed_official 324:406fd2029f23 4640 * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
mbed_official 324:406fd2029f23 4641 *
mbed_official 324:406fd2029f23 4642 * Selects whether the minor loop offset is applied to the source address upon
mbed_official 324:406fd2029f23 4643 * minor loop completion.
mbed_official 324:406fd2029f23 4644 *
mbed_official 324:406fd2029f23 4645 * Values:
mbed_official 324:406fd2029f23 4646 * - 0 - The minor loop offset is not applied to the SADDR
mbed_official 324:406fd2029f23 4647 * - 1 - The minor loop offset is applied to the SADDR
mbed_official 324:406fd2029f23 4648 */
mbed_official 324:406fd2029f23 4649 /*@{*/
mbed_official 324:406fd2029f23 4650 #define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
mbed_official 324:406fd2029f23 4651 #define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
mbed_official 324:406fd2029f23 4652 #define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
mbed_official 324:406fd2029f23 4653
mbed_official 324:406fd2029f23 4654 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */
mbed_official 324:406fd2029f23 4655 #define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
mbed_official 324:406fd2029f23 4656
mbed_official 324:406fd2029f23 4657 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
mbed_official 324:406fd2029f23 4658 #define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
mbed_official 324:406fd2029f23 4659
mbed_official 324:406fd2029f23 4660 /*! @brief Set the SMLOE field to a new value. */
mbed_official 324:406fd2029f23 4661 #define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
mbed_official 324:406fd2029f23 4662 /*@}*/
mbed_official 324:406fd2029f23 4663 /*******************************************************************************
mbed_official 324:406fd2029f23 4664 * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
mbed_official 324:406fd2029f23 4665 ******************************************************************************/
mbed_official 324:406fd2029f23 4666
mbed_official 324:406fd2029f23 4667 /*!
mbed_official 324:406fd2029f23 4668 * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
mbed_official 324:406fd2029f23 4669 *
mbed_official 324:406fd2029f23 4670 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4671 */
mbed_official 324:406fd2029f23 4672 typedef union _hw_dma_tcdn_slast
mbed_official 324:406fd2029f23 4673 {
mbed_official 324:406fd2029f23 4674 uint32_t U;
mbed_official 324:406fd2029f23 4675 struct _hw_dma_tcdn_slast_bitfields
mbed_official 324:406fd2029f23 4676 {
mbed_official 324:406fd2029f23 4677 uint32_t SLAST : 32; /*!< [31:0] Last source Address Adjustment */
mbed_official 324:406fd2029f23 4678 } B;
mbed_official 324:406fd2029f23 4679 } hw_dma_tcdn_slast_t;
mbed_official 324:406fd2029f23 4680
mbed_official 324:406fd2029f23 4681 /*!
mbed_official 324:406fd2029f23 4682 * @name Constants and macros for entire DMA_TCDn_SLAST register
mbed_official 324:406fd2029f23 4683 */
mbed_official 324:406fd2029f23 4684 /*@{*/
mbed_official 324:406fd2029f23 4685 #define HW_DMA_TCDn_SLAST_COUNT (16U)
mbed_official 324:406fd2029f23 4686
mbed_official 324:406fd2029f23 4687 #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n)))
mbed_official 324:406fd2029f23 4688
mbed_official 324:406fd2029f23 4689 #define HW_DMA_TCDn_SLAST(x, n) (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
mbed_official 324:406fd2029f23 4690 #define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
mbed_official 324:406fd2029f23 4691 #define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
mbed_official 324:406fd2029f23 4692 #define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4693 #define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4694 #define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4695 /*@}*/
mbed_official 324:406fd2029f23 4696
mbed_official 324:406fd2029f23 4697 /*
mbed_official 324:406fd2029f23 4698 * Constants & macros for individual DMA_TCDn_SLAST bitfields
mbed_official 324:406fd2029f23 4699 */
mbed_official 324:406fd2029f23 4700
mbed_official 324:406fd2029f23 4701 /*!
mbed_official 324:406fd2029f23 4702 * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
mbed_official 324:406fd2029f23 4703 *
mbed_official 324:406fd2029f23 4704 * Adjustment value added to the source address at the completion of the major
mbed_official 324:406fd2029f23 4705 * iteration count. This value can be applied to restore the source address to the
mbed_official 324:406fd2029f23 4706 * initial value, or adjust the address to reference the next data structure.
mbed_official 324:406fd2029f23 4707 * This register uses two's complement notation; the overflow bit is discarded.
mbed_official 324:406fd2029f23 4708 */
mbed_official 324:406fd2029f23 4709 /*@{*/
mbed_official 324:406fd2029f23 4710 #define BP_DMA_TCDn_SLAST_SLAST (0U) /*!< Bit position for DMA_TCDn_SLAST_SLAST. */
mbed_official 324:406fd2029f23 4711 #define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */
mbed_official 324:406fd2029f23 4712 #define BS_DMA_TCDn_SLAST_SLAST (32U) /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */
mbed_official 324:406fd2029f23 4713
mbed_official 324:406fd2029f23 4714 /*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */
mbed_official 324:406fd2029f23 4715 #define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
mbed_official 324:406fd2029f23 4716
mbed_official 324:406fd2029f23 4717 /*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */
mbed_official 324:406fd2029f23 4718 #define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST)
mbed_official 324:406fd2029f23 4719
mbed_official 324:406fd2029f23 4720 /*! @brief Set the SLAST field to a new value. */
mbed_official 324:406fd2029f23 4721 #define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
mbed_official 324:406fd2029f23 4722 /*@}*/
mbed_official 324:406fd2029f23 4723 /*******************************************************************************
mbed_official 324:406fd2029f23 4724 * HW_DMA_TCDn_DADDR - TCD Destination Address
mbed_official 324:406fd2029f23 4725 ******************************************************************************/
mbed_official 324:406fd2029f23 4726
mbed_official 324:406fd2029f23 4727 /*!
mbed_official 324:406fd2029f23 4728 * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
mbed_official 324:406fd2029f23 4729 *
mbed_official 324:406fd2029f23 4730 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 4731 */
mbed_official 324:406fd2029f23 4732 typedef union _hw_dma_tcdn_daddr
mbed_official 324:406fd2029f23 4733 {
mbed_official 324:406fd2029f23 4734 uint32_t U;
mbed_official 324:406fd2029f23 4735 struct _hw_dma_tcdn_daddr_bitfields
mbed_official 324:406fd2029f23 4736 {
mbed_official 324:406fd2029f23 4737 uint32_t DADDR : 32; /*!< [31:0] Destination Address */
mbed_official 324:406fd2029f23 4738 } B;
mbed_official 324:406fd2029f23 4739 } hw_dma_tcdn_daddr_t;
mbed_official 324:406fd2029f23 4740
mbed_official 324:406fd2029f23 4741 /*!
mbed_official 324:406fd2029f23 4742 * @name Constants and macros for entire DMA_TCDn_DADDR register
mbed_official 324:406fd2029f23 4743 */
mbed_official 324:406fd2029f23 4744 /*@{*/
mbed_official 324:406fd2029f23 4745 #define HW_DMA_TCDn_DADDR_COUNT (16U)
mbed_official 324:406fd2029f23 4746
mbed_official 324:406fd2029f23 4747 #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4748
mbed_official 324:406fd2029f23 4749 #define HW_DMA_TCDn_DADDR(x, n) (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
mbed_official 324:406fd2029f23 4750 #define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
mbed_official 324:406fd2029f23 4751 #define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
mbed_official 324:406fd2029f23 4752 #define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4753 #define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4754 #define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4755 /*@}*/
mbed_official 324:406fd2029f23 4756
mbed_official 324:406fd2029f23 4757 /*
mbed_official 324:406fd2029f23 4758 * Constants & macros for individual DMA_TCDn_DADDR bitfields
mbed_official 324:406fd2029f23 4759 */
mbed_official 324:406fd2029f23 4760
mbed_official 324:406fd2029f23 4761 /*!
mbed_official 324:406fd2029f23 4762 * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
mbed_official 324:406fd2029f23 4763 *
mbed_official 324:406fd2029f23 4764 * Memory address pointing to the destination data.
mbed_official 324:406fd2029f23 4765 */
mbed_official 324:406fd2029f23 4766 /*@{*/
mbed_official 324:406fd2029f23 4767 #define BP_DMA_TCDn_DADDR_DADDR (0U) /*!< Bit position for DMA_TCDn_DADDR_DADDR. */
mbed_official 324:406fd2029f23 4768 #define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */
mbed_official 324:406fd2029f23 4769 #define BS_DMA_TCDn_DADDR_DADDR (32U) /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */
mbed_official 324:406fd2029f23 4770
mbed_official 324:406fd2029f23 4771 /*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */
mbed_official 324:406fd2029f23 4772 #define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
mbed_official 324:406fd2029f23 4773
mbed_official 324:406fd2029f23 4774 /*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */
mbed_official 324:406fd2029f23 4775 #define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR)
mbed_official 324:406fd2029f23 4776
mbed_official 324:406fd2029f23 4777 /*! @brief Set the DADDR field to a new value. */
mbed_official 324:406fd2029f23 4778 #define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
mbed_official 324:406fd2029f23 4779 /*@}*/
mbed_official 324:406fd2029f23 4780 /*******************************************************************************
mbed_official 324:406fd2029f23 4781 * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
mbed_official 324:406fd2029f23 4782 ******************************************************************************/
mbed_official 324:406fd2029f23 4783
mbed_official 324:406fd2029f23 4784 /*!
mbed_official 324:406fd2029f23 4785 * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
mbed_official 324:406fd2029f23 4786 *
mbed_official 324:406fd2029f23 4787 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 4788 */
mbed_official 324:406fd2029f23 4789 typedef union _hw_dma_tcdn_doff
mbed_official 324:406fd2029f23 4790 {
mbed_official 324:406fd2029f23 4791 uint16_t U;
mbed_official 324:406fd2029f23 4792 struct _hw_dma_tcdn_doff_bitfields
mbed_official 324:406fd2029f23 4793 {
mbed_official 324:406fd2029f23 4794 uint16_t DOFF : 16; /*!< [15:0] Destination Address Signed offset */
mbed_official 324:406fd2029f23 4795 } B;
mbed_official 324:406fd2029f23 4796 } hw_dma_tcdn_doff_t;
mbed_official 324:406fd2029f23 4797
mbed_official 324:406fd2029f23 4798 /*!
mbed_official 324:406fd2029f23 4799 * @name Constants and macros for entire DMA_TCDn_DOFF register
mbed_official 324:406fd2029f23 4800 */
mbed_official 324:406fd2029f23 4801 /*@{*/
mbed_official 324:406fd2029f23 4802 #define HW_DMA_TCDn_DOFF_COUNT (16U)
mbed_official 324:406fd2029f23 4803
mbed_official 324:406fd2029f23 4804 #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4805
mbed_official 324:406fd2029f23 4806 #define HW_DMA_TCDn_DOFF(x, n) (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
mbed_official 324:406fd2029f23 4807 #define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
mbed_official 324:406fd2029f23 4808 #define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
mbed_official 324:406fd2029f23 4809 #define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4810 #define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4811 #define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4812 /*@}*/
mbed_official 324:406fd2029f23 4813
mbed_official 324:406fd2029f23 4814 /*
mbed_official 324:406fd2029f23 4815 * Constants & macros for individual DMA_TCDn_DOFF bitfields
mbed_official 324:406fd2029f23 4816 */
mbed_official 324:406fd2029f23 4817
mbed_official 324:406fd2029f23 4818 /*!
mbed_official 324:406fd2029f23 4819 * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
mbed_official 324:406fd2029f23 4820 *
mbed_official 324:406fd2029f23 4821 * Sign-extended offset applied to the current destination address to form the
mbed_official 324:406fd2029f23 4822 * next-state value as each destination write is completed.
mbed_official 324:406fd2029f23 4823 */
mbed_official 324:406fd2029f23 4824 /*@{*/
mbed_official 324:406fd2029f23 4825 #define BP_DMA_TCDn_DOFF_DOFF (0U) /*!< Bit position for DMA_TCDn_DOFF_DOFF. */
mbed_official 324:406fd2029f23 4826 #define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */
mbed_official 324:406fd2029f23 4827 #define BS_DMA_TCDn_DOFF_DOFF (16U) /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */
mbed_official 324:406fd2029f23 4828
mbed_official 324:406fd2029f23 4829 /*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */
mbed_official 324:406fd2029f23 4830 #define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
mbed_official 324:406fd2029f23 4831
mbed_official 324:406fd2029f23 4832 /*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */
mbed_official 324:406fd2029f23 4833 #define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF)
mbed_official 324:406fd2029f23 4834
mbed_official 324:406fd2029f23 4835 /*! @brief Set the DOFF field to a new value. */
mbed_official 324:406fd2029f23 4836 #define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
mbed_official 324:406fd2029f23 4837 /*@}*/
mbed_official 324:406fd2029f23 4838 /*******************************************************************************
mbed_official 324:406fd2029f23 4839 * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official 324:406fd2029f23 4840 ******************************************************************************/
mbed_official 324:406fd2029f23 4841
mbed_official 324:406fd2029f23 4842 /*!
mbed_official 324:406fd2029f23 4843 * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
mbed_official 324:406fd2029f23 4844 *
mbed_official 324:406fd2029f23 4845 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 4846 *
mbed_official 324:406fd2029f23 4847 * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
mbed_official 324:406fd2029f23 4848 * follows.
mbed_official 324:406fd2029f23 4849 */
mbed_official 324:406fd2029f23 4850 typedef union _hw_dma_tcdn_citer_elinkno
mbed_official 324:406fd2029f23 4851 {
mbed_official 324:406fd2029f23 4852 uint16_t U;
mbed_official 324:406fd2029f23 4853 struct _hw_dma_tcdn_citer_elinkno_bitfields
mbed_official 324:406fd2029f23 4854 {
mbed_official 324:406fd2029f23 4855 uint16_t CITER : 15; /*!< [14:0] Current Major Iteration Count */
mbed_official 324:406fd2029f23 4856 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
mbed_official 324:406fd2029f23 4857 * minor-loop complete */
mbed_official 324:406fd2029f23 4858 } B;
mbed_official 324:406fd2029f23 4859 } hw_dma_tcdn_citer_elinkno_t;
mbed_official 324:406fd2029f23 4860
mbed_official 324:406fd2029f23 4861 /*!
mbed_official 324:406fd2029f23 4862 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
mbed_official 324:406fd2029f23 4863 */
mbed_official 324:406fd2029f23 4864 /*@{*/
mbed_official 324:406fd2029f23 4865 #define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
mbed_official 324:406fd2029f23 4866
mbed_official 324:406fd2029f23 4867 #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4868
mbed_official 324:406fd2029f23 4869 #define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
mbed_official 324:406fd2029f23 4870 #define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
mbed_official 324:406fd2029f23 4871 #define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
mbed_official 324:406fd2029f23 4872 #define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4873 #define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4874 #define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4875 /*@}*/
mbed_official 324:406fd2029f23 4876
mbed_official 324:406fd2029f23 4877 /*
mbed_official 324:406fd2029f23 4878 * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
mbed_official 324:406fd2029f23 4879 */
mbed_official 324:406fd2029f23 4880
mbed_official 324:406fd2029f23 4881 /*!
mbed_official 324:406fd2029f23 4882 * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
mbed_official 324:406fd2029f23 4883 *
mbed_official 324:406fd2029f23 4884 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
mbed_official 324:406fd2029f23 4885 * major loop count for the channel. It is decremented each time the minor loop is
mbed_official 324:406fd2029f23 4886 * completed and updated in the transfer control descriptor memory. After the
mbed_official 324:406fd2029f23 4887 * major iteration count is exhausted, the channel performs a number of operations
mbed_official 324:406fd2029f23 4888 * (e.g., final source and destination address calculations), optionally generating
mbed_official 324:406fd2029f23 4889 * an interrupt to signal channel completion before reloading the CITER field
mbed_official 324:406fd2029f23 4890 * from the beginning iteration count (BITER) field. When the CITER field is
mbed_official 324:406fd2029f23 4891 * initially loaded by software, it must be set to the same value as that contained in
mbed_official 324:406fd2029f23 4892 * the BITER field. If the channel is configured to execute a single service
mbed_official 324:406fd2029f23 4893 * request, the initial values of BITER and CITER should be 0x0001.
mbed_official 324:406fd2029f23 4894 */
mbed_official 324:406fd2029f23 4895 /*@{*/
mbed_official 324:406fd2029f23 4896 #define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */
mbed_official 324:406fd2029f23 4897 #define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */
mbed_official 324:406fd2029f23 4898 #define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */
mbed_official 324:406fd2029f23 4899
mbed_official 324:406fd2029f23 4900 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */
mbed_official 324:406fd2029f23 4901 #define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
mbed_official 324:406fd2029f23 4902
mbed_official 324:406fd2029f23 4903 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */
mbed_official 324:406fd2029f23 4904 #define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
mbed_official 324:406fd2029f23 4905
mbed_official 324:406fd2029f23 4906 /*! @brief Set the CITER field to a new value. */
mbed_official 324:406fd2029f23 4907 #define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
mbed_official 324:406fd2029f23 4908 /*@}*/
mbed_official 324:406fd2029f23 4909
mbed_official 324:406fd2029f23 4910 /*!
mbed_official 324:406fd2029f23 4911 * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
mbed_official 324:406fd2029f23 4912 *
mbed_official 324:406fd2029f23 4913 * As the channel completes the minor loop, this flag enables linking to another
mbed_official 324:406fd2029f23 4914 * channel, defined by the LINKCH field. The link target channel initiates a
mbed_official 324:406fd2029f23 4915 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official 324:406fd2029f23 4916 * bit of the specified channel. If channel linking is disabled, the CITER value
mbed_official 324:406fd2029f23 4917 * is extended to 15 bits in place of a link channel number. If the major loop is
mbed_official 324:406fd2029f23 4918 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
mbed_official 324:406fd2029f23 4919 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
mbed_official 324:406fd2029f23 4920 * configuration error is reported.
mbed_official 324:406fd2029f23 4921 *
mbed_official 324:406fd2029f23 4922 * Values:
mbed_official 324:406fd2029f23 4923 * - 0 - The channel-to-channel linking is disabled
mbed_official 324:406fd2029f23 4924 * - 1 - The channel-to-channel linking is enabled
mbed_official 324:406fd2029f23 4925 */
mbed_official 324:406fd2029f23 4926 /*@{*/
mbed_official 324:406fd2029f23 4927 #define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 4928 #define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 4929 #define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 4930
mbed_official 324:406fd2029f23 4931 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */
mbed_official 324:406fd2029f23 4932 #define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
mbed_official 324:406fd2029f23 4933
mbed_official 324:406fd2029f23 4934 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 4935 #define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
mbed_official 324:406fd2029f23 4936
mbed_official 324:406fd2029f23 4937 /*! @brief Set the ELINK field to a new value. */
mbed_official 324:406fd2029f23 4938 #define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
mbed_official 324:406fd2029f23 4939 /*@}*/
mbed_official 324:406fd2029f23 4940 /*******************************************************************************
mbed_official 324:406fd2029f23 4941 * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official 324:406fd2029f23 4942 ******************************************************************************/
mbed_official 324:406fd2029f23 4943
mbed_official 324:406fd2029f23 4944 /*!
mbed_official 324:406fd2029f23 4945 * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
mbed_official 324:406fd2029f23 4946 *
mbed_official 324:406fd2029f23 4947 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 4948 *
mbed_official 324:406fd2029f23 4949 * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
mbed_official 324:406fd2029f23 4950 */
mbed_official 324:406fd2029f23 4951 typedef union _hw_dma_tcdn_citer_elinkyes
mbed_official 324:406fd2029f23 4952 {
mbed_official 324:406fd2029f23 4953 uint16_t U;
mbed_official 324:406fd2029f23 4954 struct _hw_dma_tcdn_citer_elinkyes_bitfields
mbed_official 324:406fd2029f23 4955 {
mbed_official 324:406fd2029f23 4956 uint16_t CITER : 9; /*!< [8:0] Current Major Iteration Count */
mbed_official 324:406fd2029f23 4957 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
mbed_official 324:406fd2029f23 4958 uint16_t RESERVED0 : 2; /*!< [14:13] */
mbed_official 324:406fd2029f23 4959 uint16_t ELINK : 1; /*!< [15] Enable channel-to-channel linking on
mbed_official 324:406fd2029f23 4960 * minor-loop complete */
mbed_official 324:406fd2029f23 4961 } B;
mbed_official 324:406fd2029f23 4962 } hw_dma_tcdn_citer_elinkyes_t;
mbed_official 324:406fd2029f23 4963
mbed_official 324:406fd2029f23 4964 /*!
mbed_official 324:406fd2029f23 4965 * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
mbed_official 324:406fd2029f23 4966 */
mbed_official 324:406fd2029f23 4967 /*@{*/
mbed_official 324:406fd2029f23 4968 #define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
mbed_official 324:406fd2029f23 4969
mbed_official 324:406fd2029f23 4970 #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
mbed_official 324:406fd2029f23 4971
mbed_official 324:406fd2029f23 4972 #define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
mbed_official 324:406fd2029f23 4973 #define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
mbed_official 324:406fd2029f23 4974 #define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
mbed_official 324:406fd2029f23 4975 #define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 4976 #define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 4977 #define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 4978 /*@}*/
mbed_official 324:406fd2029f23 4979
mbed_official 324:406fd2029f23 4980 /*
mbed_official 324:406fd2029f23 4981 * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
mbed_official 324:406fd2029f23 4982 */
mbed_official 324:406fd2029f23 4983
mbed_official 324:406fd2029f23 4984 /*!
mbed_official 324:406fd2029f23 4985 * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
mbed_official 324:406fd2029f23 4986 *
mbed_official 324:406fd2029f23 4987 * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
mbed_official 324:406fd2029f23 4988 * major loop count for the channel. It is decremented each time the minor loop is
mbed_official 324:406fd2029f23 4989 * completed and updated in the transfer control descriptor memory. After the
mbed_official 324:406fd2029f23 4990 * major iteration count is exhausted, the channel performs a number of operations
mbed_official 324:406fd2029f23 4991 * (e.g., final source and destination address calculations), optionally generating
mbed_official 324:406fd2029f23 4992 * an interrupt to signal channel completion before reloading the CITER field
mbed_official 324:406fd2029f23 4993 * from the beginning iteration count (BITER) field. When the CITER field is
mbed_official 324:406fd2029f23 4994 * initially loaded by software, it must be set to the same value as that contained in
mbed_official 324:406fd2029f23 4995 * the BITER field. If the channel is configured to execute a single service
mbed_official 324:406fd2029f23 4996 * request, the initial values of BITER and CITER should be 0x0001.
mbed_official 324:406fd2029f23 4997 */
mbed_official 324:406fd2029f23 4998 /*@{*/
mbed_official 324:406fd2029f23 4999 #define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */
mbed_official 324:406fd2029f23 5000 #define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */
mbed_official 324:406fd2029f23 5001 #define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */
mbed_official 324:406fd2029f23 5002
mbed_official 324:406fd2029f23 5003 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */
mbed_official 324:406fd2029f23 5004 #define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
mbed_official 324:406fd2029f23 5005
mbed_official 324:406fd2029f23 5006 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */
mbed_official 324:406fd2029f23 5007 #define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
mbed_official 324:406fd2029f23 5008
mbed_official 324:406fd2029f23 5009 /*! @brief Set the CITER field to a new value. */
mbed_official 324:406fd2029f23 5010 #define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
mbed_official 324:406fd2029f23 5011 /*@}*/
mbed_official 324:406fd2029f23 5012
mbed_official 324:406fd2029f23 5013 /*!
mbed_official 324:406fd2029f23 5014 * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
mbed_official 324:406fd2029f23 5015 *
mbed_official 324:406fd2029f23 5016 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
mbed_official 324:406fd2029f23 5017 * loop is exhausted, the eDMA engine initiates a channel service request to the
mbed_official 324:406fd2029f23 5018 * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
mbed_official 324:406fd2029f23 5019 */
mbed_official 324:406fd2029f23 5020 /*@{*/
mbed_official 324:406fd2029f23 5021 #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5022 #define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5023 #define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5024
mbed_official 324:406fd2029f23 5025 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */
mbed_official 324:406fd2029f23 5026 #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
mbed_official 324:406fd2029f23 5027
mbed_official 324:406fd2029f23 5028 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5029 #define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
mbed_official 324:406fd2029f23 5030
mbed_official 324:406fd2029f23 5031 /*! @brief Set the LINKCH field to a new value. */
mbed_official 324:406fd2029f23 5032 #define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
mbed_official 324:406fd2029f23 5033 /*@}*/
mbed_official 324:406fd2029f23 5034
mbed_official 324:406fd2029f23 5035 /*!
mbed_official 324:406fd2029f23 5036 * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
mbed_official 324:406fd2029f23 5037 *
mbed_official 324:406fd2029f23 5038 * As the channel completes the minor loop, this flag enables linking to another
mbed_official 324:406fd2029f23 5039 * channel, defined by the LINKCH field. The link target channel initiates a
mbed_official 324:406fd2029f23 5040 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official 324:406fd2029f23 5041 * bit of the specified channel. If channel linking is disabled, the CITER value
mbed_official 324:406fd2029f23 5042 * is extended to 15 bits in place of a link channel number. If the major loop is
mbed_official 324:406fd2029f23 5043 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
mbed_official 324:406fd2029f23 5044 * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
mbed_official 324:406fd2029f23 5045 * configuration error is reported.
mbed_official 324:406fd2029f23 5046 *
mbed_official 324:406fd2029f23 5047 * Values:
mbed_official 324:406fd2029f23 5048 * - 0 - The channel-to-channel linking is disabled
mbed_official 324:406fd2029f23 5049 * - 1 - The channel-to-channel linking is enabled
mbed_official 324:406fd2029f23 5050 */
mbed_official 324:406fd2029f23 5051 /*@{*/
mbed_official 324:406fd2029f23 5052 #define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5053 #define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5054 #define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5055
mbed_official 324:406fd2029f23 5056 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */
mbed_official 324:406fd2029f23 5057 #define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
mbed_official 324:406fd2029f23 5058
mbed_official 324:406fd2029f23 5059 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5060 #define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
mbed_official 324:406fd2029f23 5061
mbed_official 324:406fd2029f23 5062 /*! @brief Set the ELINK field to a new value. */
mbed_official 324:406fd2029f23 5063 #define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
mbed_official 324:406fd2029f23 5064 /*@}*/
mbed_official 324:406fd2029f23 5065 /*******************************************************************************
mbed_official 324:406fd2029f23 5066 * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
mbed_official 324:406fd2029f23 5067 ******************************************************************************/
mbed_official 324:406fd2029f23 5068
mbed_official 324:406fd2029f23 5069 /*!
mbed_official 324:406fd2029f23 5070 * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
mbed_official 324:406fd2029f23 5071 *
mbed_official 324:406fd2029f23 5072 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 5073 */
mbed_official 324:406fd2029f23 5074 typedef union _hw_dma_tcdn_dlastsga
mbed_official 324:406fd2029f23 5075 {
mbed_official 324:406fd2029f23 5076 uint32_t U;
mbed_official 324:406fd2029f23 5077 struct _hw_dma_tcdn_dlastsga_bitfields
mbed_official 324:406fd2029f23 5078 {
mbed_official 324:406fd2029f23 5079 uint32_t DLASTSGA : 32; /*!< [31:0] */
mbed_official 324:406fd2029f23 5080 } B;
mbed_official 324:406fd2029f23 5081 } hw_dma_tcdn_dlastsga_t;
mbed_official 324:406fd2029f23 5082
mbed_official 324:406fd2029f23 5083 /*!
mbed_official 324:406fd2029f23 5084 * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
mbed_official 324:406fd2029f23 5085 */
mbed_official 324:406fd2029f23 5086 /*@{*/
mbed_official 324:406fd2029f23 5087 #define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
mbed_official 324:406fd2029f23 5088
mbed_official 324:406fd2029f23 5089 #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n)))
mbed_official 324:406fd2029f23 5090
mbed_official 324:406fd2029f23 5091 #define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
mbed_official 324:406fd2029f23 5092 #define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
mbed_official 324:406fd2029f23 5093 #define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
mbed_official 324:406fd2029f23 5094 #define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 5095 #define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 5096 #define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 5097 /*@}*/
mbed_official 324:406fd2029f23 5098
mbed_official 324:406fd2029f23 5099 /*
mbed_official 324:406fd2029f23 5100 * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
mbed_official 324:406fd2029f23 5101 */
mbed_official 324:406fd2029f23 5102
mbed_official 324:406fd2029f23 5103 /*!
mbed_official 324:406fd2029f23 5104 * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
mbed_official 324:406fd2029f23 5105 *
mbed_official 324:406fd2029f23 5106 * Destination last address adjustment or the memory address for the next
mbed_official 324:406fd2029f23 5107 * transfer control descriptor to be loaded into this channel (scatter/gather). If
mbed_official 324:406fd2029f23 5108 * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
mbed_official 324:406fd2029f23 5109 * the completion of the major iteration count. This value can apply to restore the
mbed_official 324:406fd2029f23 5110 * destination address to the initial value or adjust the address to reference
mbed_official 324:406fd2029f23 5111 * the next data structure. This field uses two's complement notation for the
mbed_official 324:406fd2029f23 5112 * final destination address adjustment. Otherwise: This address points to the
mbed_official 324:406fd2029f23 5113 * beginning of a 0-modulo-32-byte region containing the next transfer control
mbed_official 324:406fd2029f23 5114 * descriptor to be loaded into this channel. This channel reload is performed as the
mbed_official 324:406fd2029f23 5115 * major iteration count completes. The scatter/gather address must be
mbed_official 324:406fd2029f23 5116 * 0-modulo-32-byte, else a configuration error is reported.
mbed_official 324:406fd2029f23 5117 */
mbed_official 324:406fd2029f23 5118 /*@{*/
mbed_official 324:406fd2029f23 5119 #define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */
mbed_official 324:406fd2029f23 5120 #define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */
mbed_official 324:406fd2029f23 5121 #define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */
mbed_official 324:406fd2029f23 5122
mbed_official 324:406fd2029f23 5123 /*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */
mbed_official 324:406fd2029f23 5124 #define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
mbed_official 324:406fd2029f23 5125
mbed_official 324:406fd2029f23 5126 /*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */
mbed_official 324:406fd2029f23 5127 #define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
mbed_official 324:406fd2029f23 5128
mbed_official 324:406fd2029f23 5129 /*! @brief Set the DLASTSGA field to a new value. */
mbed_official 324:406fd2029f23 5130 #define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
mbed_official 324:406fd2029f23 5131 /*@}*/
mbed_official 324:406fd2029f23 5132 /*******************************************************************************
mbed_official 324:406fd2029f23 5133 * HW_DMA_TCDn_CSR - TCD Control and Status
mbed_official 324:406fd2029f23 5134 ******************************************************************************/
mbed_official 324:406fd2029f23 5135
mbed_official 324:406fd2029f23 5136 /*!
mbed_official 324:406fd2029f23 5137 * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
mbed_official 324:406fd2029f23 5138 *
mbed_official 324:406fd2029f23 5139 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 5140 */
mbed_official 324:406fd2029f23 5141 typedef union _hw_dma_tcdn_csr
mbed_official 324:406fd2029f23 5142 {
mbed_official 324:406fd2029f23 5143 uint16_t U;
mbed_official 324:406fd2029f23 5144 struct _hw_dma_tcdn_csr_bitfields
mbed_official 324:406fd2029f23 5145 {
mbed_official 324:406fd2029f23 5146 uint16_t START : 1; /*!< [0] Channel Start */
mbed_official 324:406fd2029f23 5147 uint16_t INTMAJOR : 1; /*!< [1] Enable an interrupt when major
mbed_official 324:406fd2029f23 5148 * iteration count completes */
mbed_official 324:406fd2029f23 5149 uint16_t INTHALF : 1; /*!< [2] Enable an interrupt when major counter
mbed_official 324:406fd2029f23 5150 * is half complete. */
mbed_official 324:406fd2029f23 5151 uint16_t DREQ : 1; /*!< [3] Disable Request */
mbed_official 324:406fd2029f23 5152 uint16_t ESG : 1; /*!< [4] Enable Scatter/Gather Processing */
mbed_official 324:406fd2029f23 5153 uint16_t MAJORELINK : 1; /*!< [5] Enable channel-to-channel linking
mbed_official 324:406fd2029f23 5154 * on major loop complete */
mbed_official 324:406fd2029f23 5155 uint16_t ACTIVE : 1; /*!< [6] Channel Active */
mbed_official 324:406fd2029f23 5156 uint16_t DONE : 1; /*!< [7] Channel Done */
mbed_official 324:406fd2029f23 5157 uint16_t MAJORLINKCH : 4; /*!< [11:8] Link Channel Number */
mbed_official 324:406fd2029f23 5158 uint16_t RESERVED0 : 2; /*!< [13:12] */
mbed_official 324:406fd2029f23 5159 uint16_t BWC : 2; /*!< [15:14] Bandwidth Control */
mbed_official 324:406fd2029f23 5160 } B;
mbed_official 324:406fd2029f23 5161 } hw_dma_tcdn_csr_t;
mbed_official 324:406fd2029f23 5162
mbed_official 324:406fd2029f23 5163 /*!
mbed_official 324:406fd2029f23 5164 * @name Constants and macros for entire DMA_TCDn_CSR register
mbed_official 324:406fd2029f23 5165 */
mbed_official 324:406fd2029f23 5166 /*@{*/
mbed_official 324:406fd2029f23 5167 #define HW_DMA_TCDn_CSR_COUNT (16U)
mbed_official 324:406fd2029f23 5168
mbed_official 324:406fd2029f23 5169 #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n)))
mbed_official 324:406fd2029f23 5170
mbed_official 324:406fd2029f23 5171 #define HW_DMA_TCDn_CSR(x, n) (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
mbed_official 324:406fd2029f23 5172 #define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
mbed_official 324:406fd2029f23 5173 #define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
mbed_official 324:406fd2029f23 5174 #define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 5175 #define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 5176 #define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 5177 /*@}*/
mbed_official 324:406fd2029f23 5178
mbed_official 324:406fd2029f23 5179 /*
mbed_official 324:406fd2029f23 5180 * Constants & macros for individual DMA_TCDn_CSR bitfields
mbed_official 324:406fd2029f23 5181 */
mbed_official 324:406fd2029f23 5182
mbed_official 324:406fd2029f23 5183 /*!
mbed_official 324:406fd2029f23 5184 * @name Register DMA_TCDn_CSR, field START[0] (RW)
mbed_official 324:406fd2029f23 5185 *
mbed_official 324:406fd2029f23 5186 * If this flag is set, the channel is requesting service. The eDMA hardware
mbed_official 324:406fd2029f23 5187 * automatically clears this flag after the channel begins execution.
mbed_official 324:406fd2029f23 5188 *
mbed_official 324:406fd2029f23 5189 * Values:
mbed_official 324:406fd2029f23 5190 * - 0 - The channel is not explicitly started
mbed_official 324:406fd2029f23 5191 * - 1 - The channel is explicitly started via a software initiated service
mbed_official 324:406fd2029f23 5192 * request
mbed_official 324:406fd2029f23 5193 */
mbed_official 324:406fd2029f23 5194 /*@{*/
mbed_official 324:406fd2029f23 5195 #define BP_DMA_TCDn_CSR_START (0U) /*!< Bit position for DMA_TCDn_CSR_START. */
mbed_official 324:406fd2029f23 5196 #define BM_DMA_TCDn_CSR_START (0x0001U) /*!< Bit mask for DMA_TCDn_CSR_START. */
mbed_official 324:406fd2029f23 5197 #define BS_DMA_TCDn_CSR_START (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_START. */
mbed_official 324:406fd2029f23 5198
mbed_official 324:406fd2029f23 5199 /*! @brief Read current value of the DMA_TCDn_CSR_START field. */
mbed_official 324:406fd2029f23 5200 #define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
mbed_official 324:406fd2029f23 5201
mbed_official 324:406fd2029f23 5202 /*! @brief Format value for bitfield DMA_TCDn_CSR_START. */
mbed_official 324:406fd2029f23 5203 #define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START)
mbed_official 324:406fd2029f23 5204
mbed_official 324:406fd2029f23 5205 /*! @brief Set the START field to a new value. */
mbed_official 324:406fd2029f23 5206 #define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
mbed_official 324:406fd2029f23 5207 /*@}*/
mbed_official 324:406fd2029f23 5208
mbed_official 324:406fd2029f23 5209 /*!
mbed_official 324:406fd2029f23 5210 * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
mbed_official 324:406fd2029f23 5211 *
mbed_official 324:406fd2029f23 5212 * If this flag is set, the channel generates an interrupt request by setting
mbed_official 324:406fd2029f23 5213 * the appropriate bit in the INT when the current major iteration count reaches
mbed_official 324:406fd2029f23 5214 * zero.
mbed_official 324:406fd2029f23 5215 *
mbed_official 324:406fd2029f23 5216 * Values:
mbed_official 324:406fd2029f23 5217 * - 0 - The end-of-major loop interrupt is disabled
mbed_official 324:406fd2029f23 5218 * - 1 - The end-of-major loop interrupt is enabled
mbed_official 324:406fd2029f23 5219 */
mbed_official 324:406fd2029f23 5220 /*@{*/
mbed_official 324:406fd2029f23 5221 #define BP_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */
mbed_official 324:406fd2029f23 5222 #define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */
mbed_official 324:406fd2029f23 5223 #define BS_DMA_TCDn_CSR_INTMAJOR (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */
mbed_official 324:406fd2029f23 5224
mbed_official 324:406fd2029f23 5225 /*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */
mbed_official 324:406fd2029f23 5226 #define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
mbed_official 324:406fd2029f23 5227
mbed_official 324:406fd2029f23 5228 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */
mbed_official 324:406fd2029f23 5229 #define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR)
mbed_official 324:406fd2029f23 5230
mbed_official 324:406fd2029f23 5231 /*! @brief Set the INTMAJOR field to a new value. */
mbed_official 324:406fd2029f23 5232 #define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
mbed_official 324:406fd2029f23 5233 /*@}*/
mbed_official 324:406fd2029f23 5234
mbed_official 324:406fd2029f23 5235 /*!
mbed_official 324:406fd2029f23 5236 * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
mbed_official 324:406fd2029f23 5237 *
mbed_official 324:406fd2029f23 5238 * If this flag is set, the channel generates an interrupt request by setting
mbed_official 324:406fd2029f23 5239 * the appropriate bit in the INT register when the current major iteration count
mbed_official 324:406fd2029f23 5240 * reaches the halfway point. Specifically, the comparison performed by the eDMA
mbed_official 324:406fd2029f23 5241 * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
mbed_official 324:406fd2029f23 5242 * provided to support double-buffered (aka ping-pong) schemes or other types of data
mbed_official 324:406fd2029f23 5243 * movement where the processor needs an early indication of the transfer's
mbed_official 324:406fd2029f23 5244 * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
mbed_official 324:406fd2029f23 5245 *
mbed_official 324:406fd2029f23 5246 * Values:
mbed_official 324:406fd2029f23 5247 * - 0 - The half-point interrupt is disabled
mbed_official 324:406fd2029f23 5248 * - 1 - The half-point interrupt is enabled
mbed_official 324:406fd2029f23 5249 */
mbed_official 324:406fd2029f23 5250 /*@{*/
mbed_official 324:406fd2029f23 5251 #define BP_DMA_TCDn_CSR_INTHALF (2U) /*!< Bit position for DMA_TCDn_CSR_INTHALF. */
mbed_official 324:406fd2029f23 5252 #define BM_DMA_TCDn_CSR_INTHALF (0x0004U) /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */
mbed_official 324:406fd2029f23 5253 #define BS_DMA_TCDn_CSR_INTHALF (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */
mbed_official 324:406fd2029f23 5254
mbed_official 324:406fd2029f23 5255 /*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */
mbed_official 324:406fd2029f23 5256 #define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
mbed_official 324:406fd2029f23 5257
mbed_official 324:406fd2029f23 5258 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */
mbed_official 324:406fd2029f23 5259 #define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF)
mbed_official 324:406fd2029f23 5260
mbed_official 324:406fd2029f23 5261 /*! @brief Set the INTHALF field to a new value. */
mbed_official 324:406fd2029f23 5262 #define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
mbed_official 324:406fd2029f23 5263 /*@}*/
mbed_official 324:406fd2029f23 5264
mbed_official 324:406fd2029f23 5265 /*!
mbed_official 324:406fd2029f23 5266 * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
mbed_official 324:406fd2029f23 5267 *
mbed_official 324:406fd2029f23 5268 * If this flag is set, the eDMA hardware automatically clears the corresponding
mbed_official 324:406fd2029f23 5269 * ERQ bit when the current major iteration count reaches zero.
mbed_official 324:406fd2029f23 5270 *
mbed_official 324:406fd2029f23 5271 * Values:
mbed_official 324:406fd2029f23 5272 * - 0 - The channel's ERQ bit is not affected
mbed_official 324:406fd2029f23 5273 * - 1 - The channel's ERQ bit is cleared when the major loop is complete
mbed_official 324:406fd2029f23 5274 */
mbed_official 324:406fd2029f23 5275 /*@{*/
mbed_official 324:406fd2029f23 5276 #define BP_DMA_TCDn_CSR_DREQ (3U) /*!< Bit position for DMA_TCDn_CSR_DREQ. */
mbed_official 324:406fd2029f23 5277 #define BM_DMA_TCDn_CSR_DREQ (0x0008U) /*!< Bit mask for DMA_TCDn_CSR_DREQ. */
mbed_official 324:406fd2029f23 5278 #define BS_DMA_TCDn_CSR_DREQ (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */
mbed_official 324:406fd2029f23 5279
mbed_official 324:406fd2029f23 5280 /*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */
mbed_official 324:406fd2029f23 5281 #define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
mbed_official 324:406fd2029f23 5282
mbed_official 324:406fd2029f23 5283 /*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */
mbed_official 324:406fd2029f23 5284 #define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ)
mbed_official 324:406fd2029f23 5285
mbed_official 324:406fd2029f23 5286 /*! @brief Set the DREQ field to a new value. */
mbed_official 324:406fd2029f23 5287 #define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
mbed_official 324:406fd2029f23 5288 /*@}*/
mbed_official 324:406fd2029f23 5289
mbed_official 324:406fd2029f23 5290 /*!
mbed_official 324:406fd2029f23 5291 * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
mbed_official 324:406fd2029f23 5292 *
mbed_official 324:406fd2029f23 5293 * As the channel completes the major loop, this flag enables scatter/gather
mbed_official 324:406fd2029f23 5294 * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
mbed_official 324:406fd2029f23 5295 * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
mbed_official 324:406fd2029f23 5296 * loaded as the transfer control descriptor into the local memory. To support the
mbed_official 324:406fd2029f23 5297 * dynamic scatter/gather coherency model, this field is forced to zero when
mbed_official 324:406fd2029f23 5298 * written to while the TCDn_CSR[DONE] bit is set.
mbed_official 324:406fd2029f23 5299 *
mbed_official 324:406fd2029f23 5300 * Values:
mbed_official 324:406fd2029f23 5301 * - 0 - The current channel's TCD is normal format.
mbed_official 324:406fd2029f23 5302 * - 1 - The current channel's TCD specifies a scatter gather format. The
mbed_official 324:406fd2029f23 5303 * DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
mbed_official 324:406fd2029f23 5304 * channel after the major loop completes its execution.
mbed_official 324:406fd2029f23 5305 */
mbed_official 324:406fd2029f23 5306 /*@{*/
mbed_official 324:406fd2029f23 5307 #define BP_DMA_TCDn_CSR_ESG (4U) /*!< Bit position for DMA_TCDn_CSR_ESG. */
mbed_official 324:406fd2029f23 5308 #define BM_DMA_TCDn_CSR_ESG (0x0010U) /*!< Bit mask for DMA_TCDn_CSR_ESG. */
mbed_official 324:406fd2029f23 5309 #define BS_DMA_TCDn_CSR_ESG (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */
mbed_official 324:406fd2029f23 5310
mbed_official 324:406fd2029f23 5311 /*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */
mbed_official 324:406fd2029f23 5312 #define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
mbed_official 324:406fd2029f23 5313
mbed_official 324:406fd2029f23 5314 /*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */
mbed_official 324:406fd2029f23 5315 #define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG)
mbed_official 324:406fd2029f23 5316
mbed_official 324:406fd2029f23 5317 /*! @brief Set the ESG field to a new value. */
mbed_official 324:406fd2029f23 5318 #define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
mbed_official 324:406fd2029f23 5319 /*@}*/
mbed_official 324:406fd2029f23 5320
mbed_official 324:406fd2029f23 5321 /*!
mbed_official 324:406fd2029f23 5322 * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
mbed_official 324:406fd2029f23 5323 *
mbed_official 324:406fd2029f23 5324 * As the channel completes the major loop, this flag enables the linking to
mbed_official 324:406fd2029f23 5325 * another channel, defined by MAJORLINKCH. The link target channel initiates a
mbed_official 324:406fd2029f23 5326 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official 324:406fd2029f23 5327 * bit of the specified channel. To support the dynamic linking coherency model,
mbed_official 324:406fd2029f23 5328 * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
mbed_official 324:406fd2029f23 5329 *
mbed_official 324:406fd2029f23 5330 * Values:
mbed_official 324:406fd2029f23 5331 * - 0 - The channel-to-channel linking is disabled
mbed_official 324:406fd2029f23 5332 * - 1 - The channel-to-channel linking is enabled
mbed_official 324:406fd2029f23 5333 */
mbed_official 324:406fd2029f23 5334 /*@{*/
mbed_official 324:406fd2029f23 5335 #define BP_DMA_TCDn_CSR_MAJORELINK (5U) /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */
mbed_official 324:406fd2029f23 5336 #define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */
mbed_official 324:406fd2029f23 5337 #define BS_DMA_TCDn_CSR_MAJORELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */
mbed_official 324:406fd2029f23 5338
mbed_official 324:406fd2029f23 5339 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */
mbed_official 324:406fd2029f23 5340 #define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
mbed_official 324:406fd2029f23 5341
mbed_official 324:406fd2029f23 5342 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */
mbed_official 324:406fd2029f23 5343 #define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK)
mbed_official 324:406fd2029f23 5344
mbed_official 324:406fd2029f23 5345 /*! @brief Set the MAJORELINK field to a new value. */
mbed_official 324:406fd2029f23 5346 #define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
mbed_official 324:406fd2029f23 5347 /*@}*/
mbed_official 324:406fd2029f23 5348
mbed_official 324:406fd2029f23 5349 /*!
mbed_official 324:406fd2029f23 5350 * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
mbed_official 324:406fd2029f23 5351 *
mbed_official 324:406fd2029f23 5352 * This flag signals the channel is currently in execution. It is set when
mbed_official 324:406fd2029f23 5353 * channel service begins, and the eDMA clears it as the minor loop completes or if
mbed_official 324:406fd2029f23 5354 * any error condition is detected. This bit resets to zero.
mbed_official 324:406fd2029f23 5355 */
mbed_official 324:406fd2029f23 5356 /*@{*/
mbed_official 324:406fd2029f23 5357 #define BP_DMA_TCDn_CSR_ACTIVE (6U) /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */
mbed_official 324:406fd2029f23 5358 #define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */
mbed_official 324:406fd2029f23 5359 #define BS_DMA_TCDn_CSR_ACTIVE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */
mbed_official 324:406fd2029f23 5360
mbed_official 324:406fd2029f23 5361 /*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */
mbed_official 324:406fd2029f23 5362 #define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
mbed_official 324:406fd2029f23 5363
mbed_official 324:406fd2029f23 5364 /*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */
mbed_official 324:406fd2029f23 5365 #define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE)
mbed_official 324:406fd2029f23 5366
mbed_official 324:406fd2029f23 5367 /*! @brief Set the ACTIVE field to a new value. */
mbed_official 324:406fd2029f23 5368 #define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
mbed_official 324:406fd2029f23 5369 /*@}*/
mbed_official 324:406fd2029f23 5370
mbed_official 324:406fd2029f23 5371 /*!
mbed_official 324:406fd2029f23 5372 * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
mbed_official 324:406fd2029f23 5373 *
mbed_official 324:406fd2029f23 5374 * This flag indicates the eDMA has completed the major loop. The eDMA engine
mbed_official 324:406fd2029f23 5375 * sets it as the CITER count reaches zero; The software clears it, or the hardware
mbed_official 324:406fd2029f23 5376 * when the channel is activated. This bit must be cleared to write the
mbed_official 324:406fd2029f23 5377 * MAJORELINK or ESG bits.
mbed_official 324:406fd2029f23 5378 */
mbed_official 324:406fd2029f23 5379 /*@{*/
mbed_official 324:406fd2029f23 5380 #define BP_DMA_TCDn_CSR_DONE (7U) /*!< Bit position for DMA_TCDn_CSR_DONE. */
mbed_official 324:406fd2029f23 5381 #define BM_DMA_TCDn_CSR_DONE (0x0080U) /*!< Bit mask for DMA_TCDn_CSR_DONE. */
mbed_official 324:406fd2029f23 5382 #define BS_DMA_TCDn_CSR_DONE (1U) /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */
mbed_official 324:406fd2029f23 5383
mbed_official 324:406fd2029f23 5384 /*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */
mbed_official 324:406fd2029f23 5385 #define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
mbed_official 324:406fd2029f23 5386
mbed_official 324:406fd2029f23 5387 /*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */
mbed_official 324:406fd2029f23 5388 #define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE)
mbed_official 324:406fd2029f23 5389
mbed_official 324:406fd2029f23 5390 /*! @brief Set the DONE field to a new value. */
mbed_official 324:406fd2029f23 5391 #define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
mbed_official 324:406fd2029f23 5392 /*@}*/
mbed_official 324:406fd2029f23 5393
mbed_official 324:406fd2029f23 5394 /*!
mbed_official 324:406fd2029f23 5395 * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
mbed_official 324:406fd2029f23 5396 *
mbed_official 324:406fd2029f23 5397 * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
mbed_official 324:406fd2029f23 5398 * performed after the major loop counter is exhausted. else After the major loop
mbed_official 324:406fd2029f23 5399 * counter is exhausted, the eDMA engine initiates a channel service request at the
mbed_official 324:406fd2029f23 5400 * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
mbed_official 324:406fd2029f23 5401 */
mbed_official 324:406fd2029f23 5402 /*@{*/
mbed_official 324:406fd2029f23 5403 #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */
mbed_official 324:406fd2029f23 5404 #define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */
mbed_official 324:406fd2029f23 5405 #define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */
mbed_official 324:406fd2029f23 5406
mbed_official 324:406fd2029f23 5407 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */
mbed_official 324:406fd2029f23 5408 #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
mbed_official 324:406fd2029f23 5409
mbed_official 324:406fd2029f23 5410 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */
mbed_official 324:406fd2029f23 5411 #define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH)
mbed_official 324:406fd2029f23 5412
mbed_official 324:406fd2029f23 5413 /*! @brief Set the MAJORLINKCH field to a new value. */
mbed_official 324:406fd2029f23 5414 #define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
mbed_official 324:406fd2029f23 5415 /*@}*/
mbed_official 324:406fd2029f23 5416
mbed_official 324:406fd2029f23 5417 /*!
mbed_official 324:406fd2029f23 5418 * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
mbed_official 324:406fd2029f23 5419 *
mbed_official 324:406fd2029f23 5420 * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
mbed_official 324:406fd2029f23 5421 * the eDMA processes the minor loop, it continuously generates read/write
mbed_official 324:406fd2029f23 5422 * sequences until the minor count is exhausted. This field forces the eDMA to stall
mbed_official 324:406fd2029f23 5423 * after the completion of each read/write access to control the bus request
mbed_official 324:406fd2029f23 5424 * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
mbed_official 324:406fd2029f23 5425 * this field is ignored between the first and second transfers and after the
mbed_official 324:406fd2029f23 5426 * last write of each minor loop. This behavior is a side effect of reducing
mbed_official 324:406fd2029f23 5427 * start-up latency.
mbed_official 324:406fd2029f23 5428 *
mbed_official 324:406fd2029f23 5429 * Values:
mbed_official 324:406fd2029f23 5430 * - 00 - No eDMA engine stalls
mbed_official 324:406fd2029f23 5431 * - 01 - Reserved
mbed_official 324:406fd2029f23 5432 * - 10 - eDMA engine stalls for 4 cycles after each r/w
mbed_official 324:406fd2029f23 5433 * - 11 - eDMA engine stalls for 8 cycles after each r/w
mbed_official 324:406fd2029f23 5434 */
mbed_official 324:406fd2029f23 5435 /*@{*/
mbed_official 324:406fd2029f23 5436 #define BP_DMA_TCDn_CSR_BWC (14U) /*!< Bit position for DMA_TCDn_CSR_BWC. */
mbed_official 324:406fd2029f23 5437 #define BM_DMA_TCDn_CSR_BWC (0xC000U) /*!< Bit mask for DMA_TCDn_CSR_BWC. */
mbed_official 324:406fd2029f23 5438 #define BS_DMA_TCDn_CSR_BWC (2U) /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */
mbed_official 324:406fd2029f23 5439
mbed_official 324:406fd2029f23 5440 /*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */
mbed_official 324:406fd2029f23 5441 #define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
mbed_official 324:406fd2029f23 5442
mbed_official 324:406fd2029f23 5443 /*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */
mbed_official 324:406fd2029f23 5444 #define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC)
mbed_official 324:406fd2029f23 5445
mbed_official 324:406fd2029f23 5446 /*! @brief Set the BWC field to a new value. */
mbed_official 324:406fd2029f23 5447 #define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
mbed_official 324:406fd2029f23 5448 /*@}*/
mbed_official 324:406fd2029f23 5449 /*******************************************************************************
mbed_official 324:406fd2029f23 5450 * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
mbed_official 324:406fd2029f23 5451 ******************************************************************************/
mbed_official 324:406fd2029f23 5452
mbed_official 324:406fd2029f23 5453 /*!
mbed_official 324:406fd2029f23 5454 * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
mbed_official 324:406fd2029f23 5455 *
mbed_official 324:406fd2029f23 5456 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 5457 *
mbed_official 324:406fd2029f23 5458 * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
mbed_official 324:406fd2029f23 5459 * as follows.
mbed_official 324:406fd2029f23 5460 */
mbed_official 324:406fd2029f23 5461 typedef union _hw_dma_tcdn_biter_elinkno
mbed_official 324:406fd2029f23 5462 {
mbed_official 324:406fd2029f23 5463 uint16_t U;
mbed_official 324:406fd2029f23 5464 struct _hw_dma_tcdn_biter_elinkno_bitfields
mbed_official 324:406fd2029f23 5465 {
mbed_official 324:406fd2029f23 5466 uint16_t BITER : 15; /*!< [14:0] Starting Major Iteration Count */
mbed_official 324:406fd2029f23 5467 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
mbed_official 324:406fd2029f23 5468 * minor loop complete */
mbed_official 324:406fd2029f23 5469 } B;
mbed_official 324:406fd2029f23 5470 } hw_dma_tcdn_biter_elinkno_t;
mbed_official 324:406fd2029f23 5471
mbed_official 324:406fd2029f23 5472 /*!
mbed_official 324:406fd2029f23 5473 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
mbed_official 324:406fd2029f23 5474 */
mbed_official 324:406fd2029f23 5475 /*@{*/
mbed_official 324:406fd2029f23 5476 #define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
mbed_official 324:406fd2029f23 5477
mbed_official 324:406fd2029f23 5478 #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
mbed_official 324:406fd2029f23 5479
mbed_official 324:406fd2029f23 5480 #define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
mbed_official 324:406fd2029f23 5481 #define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
mbed_official 324:406fd2029f23 5482 #define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
mbed_official 324:406fd2029f23 5483 #define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 5484 #define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 5485 #define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 5486 /*@}*/
mbed_official 324:406fd2029f23 5487
mbed_official 324:406fd2029f23 5488 /*
mbed_official 324:406fd2029f23 5489 * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
mbed_official 324:406fd2029f23 5490 */
mbed_official 324:406fd2029f23 5491
mbed_official 324:406fd2029f23 5492 /*!
mbed_official 324:406fd2029f23 5493 * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
mbed_official 324:406fd2029f23 5494 *
mbed_official 324:406fd2029f23 5495 * As the transfer control descriptor is first loaded by software, this 9-bit
mbed_official 324:406fd2029f23 5496 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
mbed_official 324:406fd2029f23 5497 * field. As the major iteration count is exhausted, the contents of this field
mbed_official 324:406fd2029f23 5498 * are reloaded into the CITER field. When the software loads the TCD, this field
mbed_official 324:406fd2029f23 5499 * must be set equal to the corresponding CITER field; otherwise, a configuration
mbed_official 324:406fd2029f23 5500 * error is reported. As the major iteration count is exhausted, the contents of
mbed_official 324:406fd2029f23 5501 * this field is reloaded into the CITER field. If the channel is configured to
mbed_official 324:406fd2029f23 5502 * execute a single service request, the initial values of BITER and CITER should
mbed_official 324:406fd2029f23 5503 * be 0x0001.
mbed_official 324:406fd2029f23 5504 */
mbed_official 324:406fd2029f23 5505 /*@{*/
mbed_official 324:406fd2029f23 5506 #define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */
mbed_official 324:406fd2029f23 5507 #define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */
mbed_official 324:406fd2029f23 5508 #define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */
mbed_official 324:406fd2029f23 5509
mbed_official 324:406fd2029f23 5510 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */
mbed_official 324:406fd2029f23 5511 #define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
mbed_official 324:406fd2029f23 5512
mbed_official 324:406fd2029f23 5513 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */
mbed_official 324:406fd2029f23 5514 #define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
mbed_official 324:406fd2029f23 5515
mbed_official 324:406fd2029f23 5516 /*! @brief Set the BITER field to a new value. */
mbed_official 324:406fd2029f23 5517 #define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
mbed_official 324:406fd2029f23 5518 /*@}*/
mbed_official 324:406fd2029f23 5519
mbed_official 324:406fd2029f23 5520 /*!
mbed_official 324:406fd2029f23 5521 * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
mbed_official 324:406fd2029f23 5522 *
mbed_official 324:406fd2029f23 5523 * As the channel completes the minor loop, this flag enables the linking to
mbed_official 324:406fd2029f23 5524 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
mbed_official 324:406fd2029f23 5525 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official 324:406fd2029f23 5526 * bit of the specified channel. If channel linking is disabled, the BITER value
mbed_official 324:406fd2029f23 5527 * extends to 15 bits in place of a link channel number. If the major loop is
mbed_official 324:406fd2029f23 5528 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
mbed_official 324:406fd2029f23 5529 * linking. When the software loads the TCD, this field must be set equal to the
mbed_official 324:406fd2029f23 5530 * corresponding CITER field; otherwise, a configuration error is reported. As the
mbed_official 324:406fd2029f23 5531 * major iteration count is exhausted, the contents of this field is reloaded
mbed_official 324:406fd2029f23 5532 * into the CITER field.
mbed_official 324:406fd2029f23 5533 *
mbed_official 324:406fd2029f23 5534 * Values:
mbed_official 324:406fd2029f23 5535 * - 0 - The channel-to-channel linking is disabled
mbed_official 324:406fd2029f23 5536 * - 1 - The channel-to-channel linking is enabled
mbed_official 324:406fd2029f23 5537 */
mbed_official 324:406fd2029f23 5538 /*@{*/
mbed_official 324:406fd2029f23 5539 #define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 5540 #define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 5541 #define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 5542
mbed_official 324:406fd2029f23 5543 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */
mbed_official 324:406fd2029f23 5544 #define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
mbed_official 324:406fd2029f23 5545
mbed_official 324:406fd2029f23 5546 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */
mbed_official 324:406fd2029f23 5547 #define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
mbed_official 324:406fd2029f23 5548
mbed_official 324:406fd2029f23 5549 /*! @brief Set the ELINK field to a new value. */
mbed_official 324:406fd2029f23 5550 #define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
mbed_official 324:406fd2029f23 5551 /*@}*/
mbed_official 324:406fd2029f23 5552 /*******************************************************************************
mbed_official 324:406fd2029f23 5553 * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
mbed_official 324:406fd2029f23 5554 ******************************************************************************/
mbed_official 324:406fd2029f23 5555
mbed_official 324:406fd2029f23 5556 /*!
mbed_official 324:406fd2029f23 5557 * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
mbed_official 324:406fd2029f23 5558 *
mbed_official 324:406fd2029f23 5559 * Reset value: 0x0000U
mbed_official 324:406fd2029f23 5560 *
mbed_official 324:406fd2029f23 5561 * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
mbed_official 324:406fd2029f23 5562 * follows.
mbed_official 324:406fd2029f23 5563 */
mbed_official 324:406fd2029f23 5564 typedef union _hw_dma_tcdn_biter_elinkyes
mbed_official 324:406fd2029f23 5565 {
mbed_official 324:406fd2029f23 5566 uint16_t U;
mbed_official 324:406fd2029f23 5567 struct _hw_dma_tcdn_biter_elinkyes_bitfields
mbed_official 324:406fd2029f23 5568 {
mbed_official 324:406fd2029f23 5569 uint16_t BITER : 9; /*!< [8:0] Starting Major Iteration Count */
mbed_official 324:406fd2029f23 5570 uint16_t LINKCH : 4; /*!< [12:9] Link Channel Number */
mbed_official 324:406fd2029f23 5571 uint16_t RESERVED0 : 2; /*!< [14:13] */
mbed_official 324:406fd2029f23 5572 uint16_t ELINK : 1; /*!< [15] Enables channel-to-channel linking on
mbed_official 324:406fd2029f23 5573 * minor loop complete */
mbed_official 324:406fd2029f23 5574 } B;
mbed_official 324:406fd2029f23 5575 } hw_dma_tcdn_biter_elinkyes_t;
mbed_official 324:406fd2029f23 5576
mbed_official 324:406fd2029f23 5577 /*!
mbed_official 324:406fd2029f23 5578 * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
mbed_official 324:406fd2029f23 5579 */
mbed_official 324:406fd2029f23 5580 /*@{*/
mbed_official 324:406fd2029f23 5581 #define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
mbed_official 324:406fd2029f23 5582
mbed_official 324:406fd2029f23 5583 #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
mbed_official 324:406fd2029f23 5584
mbed_official 324:406fd2029f23 5585 #define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
mbed_official 324:406fd2029f23 5586 #define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
mbed_official 324:406fd2029f23 5587 #define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
mbed_official 324:406fd2029f23 5588 #define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 5589 #define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 5590 #define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 5591 /*@}*/
mbed_official 324:406fd2029f23 5592
mbed_official 324:406fd2029f23 5593 /*
mbed_official 324:406fd2029f23 5594 * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
mbed_official 324:406fd2029f23 5595 */
mbed_official 324:406fd2029f23 5596
mbed_official 324:406fd2029f23 5597 /*!
mbed_official 324:406fd2029f23 5598 * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
mbed_official 324:406fd2029f23 5599 *
mbed_official 324:406fd2029f23 5600 * As the transfer control descriptor is first loaded by software, this 9-bit
mbed_official 324:406fd2029f23 5601 * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
mbed_official 324:406fd2029f23 5602 * field. As the major iteration count is exhausted, the contents of this field
mbed_official 324:406fd2029f23 5603 * are reloaded into the CITER field. When the software loads the TCD, this field
mbed_official 324:406fd2029f23 5604 * must be set equal to the corresponding CITER field; otherwise, a configuration
mbed_official 324:406fd2029f23 5605 * error is reported. As the major iteration count is exhausted, the contents of
mbed_official 324:406fd2029f23 5606 * this field is reloaded into the CITER field. If the channel is configured to
mbed_official 324:406fd2029f23 5607 * execute a single service request, the initial values of BITER and CITER should
mbed_official 324:406fd2029f23 5608 * be 0x0001.
mbed_official 324:406fd2029f23 5609 */
mbed_official 324:406fd2029f23 5610 /*@{*/
mbed_official 324:406fd2029f23 5611 #define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */
mbed_official 324:406fd2029f23 5612 #define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */
mbed_official 324:406fd2029f23 5613 #define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */
mbed_official 324:406fd2029f23 5614
mbed_official 324:406fd2029f23 5615 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */
mbed_official 324:406fd2029f23 5616 #define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
mbed_official 324:406fd2029f23 5617
mbed_official 324:406fd2029f23 5618 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */
mbed_official 324:406fd2029f23 5619 #define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
mbed_official 324:406fd2029f23 5620
mbed_official 324:406fd2029f23 5621 /*! @brief Set the BITER field to a new value. */
mbed_official 324:406fd2029f23 5622 #define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
mbed_official 324:406fd2029f23 5623 /*@}*/
mbed_official 324:406fd2029f23 5624
mbed_official 324:406fd2029f23 5625 /*!
mbed_official 324:406fd2029f23 5626 * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
mbed_official 324:406fd2029f23 5627 *
mbed_official 324:406fd2029f23 5628 * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
mbed_official 324:406fd2029f23 5629 * loop is exhausted, the eDMA engine initiates a channel service request at the
mbed_official 324:406fd2029f23 5630 * channel defined by these four bits by setting that channel's TCDn_CSR[START]
mbed_official 324:406fd2029f23 5631 * bit. When the software loads the TCD, this field must be set equal to the
mbed_official 324:406fd2029f23 5632 * corresponding CITER field; otherwise, a configuration error is reported. As the major
mbed_official 324:406fd2029f23 5633 * iteration count is exhausted, the contents of this field is reloaded into the
mbed_official 324:406fd2029f23 5634 * CITER field.
mbed_official 324:406fd2029f23 5635 */
mbed_official 324:406fd2029f23 5636 /*@{*/
mbed_official 324:406fd2029f23 5637 #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5638 #define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5639 #define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5640
mbed_official 324:406fd2029f23 5641 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */
mbed_official 324:406fd2029f23 5642 #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
mbed_official 324:406fd2029f23 5643
mbed_official 324:406fd2029f23 5644 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */
mbed_official 324:406fd2029f23 5645 #define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
mbed_official 324:406fd2029f23 5646
mbed_official 324:406fd2029f23 5647 /*! @brief Set the LINKCH field to a new value. */
mbed_official 324:406fd2029f23 5648 #define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
mbed_official 324:406fd2029f23 5649 /*@}*/
mbed_official 324:406fd2029f23 5650
mbed_official 324:406fd2029f23 5651 /*!
mbed_official 324:406fd2029f23 5652 * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
mbed_official 324:406fd2029f23 5653 *
mbed_official 324:406fd2029f23 5654 * As the channel completes the minor loop, this flag enables the linking to
mbed_official 324:406fd2029f23 5655 * another channel, defined by BITER[LINKCH]. The link target channel initiates a
mbed_official 324:406fd2029f23 5656 * channel service request via an internal mechanism that sets the TCDn_CSR[START]
mbed_official 324:406fd2029f23 5657 * bit of the specified channel. If channel linking disables, the BITER value
mbed_official 324:406fd2029f23 5658 * extends to 15 bits in place of a link channel number. If the major loop is
mbed_official 324:406fd2029f23 5659 * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
mbed_official 324:406fd2029f23 5660 * linking. When the software loads the TCD, this field must be set equal to the
mbed_official 324:406fd2029f23 5661 * corresponding CITER field; otherwise, a configuration error is reported. As the
mbed_official 324:406fd2029f23 5662 * major iteration count is exhausted, the contents of this field is reloaded into
mbed_official 324:406fd2029f23 5663 * the CITER field.
mbed_official 324:406fd2029f23 5664 *
mbed_official 324:406fd2029f23 5665 * Values:
mbed_official 324:406fd2029f23 5666 * - 0 - The channel-to-channel linking is disabled
mbed_official 324:406fd2029f23 5667 * - 1 - The channel-to-channel linking is enabled
mbed_official 324:406fd2029f23 5668 */
mbed_official 324:406fd2029f23 5669 /*@{*/
mbed_official 324:406fd2029f23 5670 #define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5671 #define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5672 #define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5673
mbed_official 324:406fd2029f23 5674 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */
mbed_official 324:406fd2029f23 5675 #define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
mbed_official 324:406fd2029f23 5676
mbed_official 324:406fd2029f23 5677 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */
mbed_official 324:406fd2029f23 5678 #define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
mbed_official 324:406fd2029f23 5679
mbed_official 324:406fd2029f23 5680 /*! @brief Set the ELINK field to a new value. */
mbed_official 324:406fd2029f23 5681 #define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
mbed_official 324:406fd2029f23 5682 /*@}*/
mbed_official 324:406fd2029f23 5683
mbed_official 324:406fd2029f23 5684 /*
mbed_official 324:406fd2029f23 5685 ** Start of section using anonymous unions
mbed_official 324:406fd2029f23 5686 */
mbed_official 324:406fd2029f23 5687
mbed_official 324:406fd2029f23 5688 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 5689 #pragma push
mbed_official 324:406fd2029f23 5690 #pragma anon_unions
mbed_official 324:406fd2029f23 5691 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 5692 #pragma push
mbed_official 324:406fd2029f23 5693 #pragma cpp_extensions on
mbed_official 324:406fd2029f23 5694 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 5695 /* anonymous unions are enabled by default */
mbed_official 324:406fd2029f23 5696 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 5697 #pragma language=extended
mbed_official 324:406fd2029f23 5698 #else
mbed_official 324:406fd2029f23 5699 #error Not supported compiler type
mbed_official 324:406fd2029f23 5700 #endif
mbed_official 324:406fd2029f23 5701
mbed_official 324:406fd2029f23 5702 /*******************************************************************************
mbed_official 324:406fd2029f23 5703 * hw_dma_t - module struct
mbed_official 324:406fd2029f23 5704 ******************************************************************************/
mbed_official 324:406fd2029f23 5705 /*!
mbed_official 324:406fd2029f23 5706 * @brief All DMA module registers.
mbed_official 324:406fd2029f23 5707 */
mbed_official 324:406fd2029f23 5708 #pragma pack(1)
mbed_official 324:406fd2029f23 5709 typedef struct _hw_dma
mbed_official 324:406fd2029f23 5710 {
mbed_official 324:406fd2029f23 5711 __IO hw_dma_cr_t CR; /*!< [0x0] Control Register */
mbed_official 324:406fd2029f23 5712 __I hw_dma_es_t ES; /*!< [0x4] Error Status Register */
mbed_official 324:406fd2029f23 5713 uint8_t _reserved0[4];
mbed_official 324:406fd2029f23 5714 __IO hw_dma_erq_t ERQ; /*!< [0xC] Enable Request Register */
mbed_official 324:406fd2029f23 5715 uint8_t _reserved1[4];
mbed_official 324:406fd2029f23 5716 __IO hw_dma_eei_t EEI; /*!< [0x14] Enable Error Interrupt Register */
mbed_official 324:406fd2029f23 5717 __O hw_dma_ceei_t CEEI; /*!< [0x18] Clear Enable Error Interrupt Register */
mbed_official 324:406fd2029f23 5718 __O hw_dma_seei_t SEEI; /*!< [0x19] Set Enable Error Interrupt Register */
mbed_official 324:406fd2029f23 5719 __O hw_dma_cerq_t CERQ; /*!< [0x1A] Clear Enable Request Register */
mbed_official 324:406fd2029f23 5720 __O hw_dma_serq_t SERQ; /*!< [0x1B] Set Enable Request Register */
mbed_official 324:406fd2029f23 5721 __O hw_dma_cdne_t CDNE; /*!< [0x1C] Clear DONE Status Bit Register */
mbed_official 324:406fd2029f23 5722 __O hw_dma_ssrt_t SSRT; /*!< [0x1D] Set START Bit Register */
mbed_official 324:406fd2029f23 5723 __O hw_dma_cerr_t CERR; /*!< [0x1E] Clear Error Register */
mbed_official 324:406fd2029f23 5724 __O hw_dma_cint_t CINT; /*!< [0x1F] Clear Interrupt Request Register */
mbed_official 324:406fd2029f23 5725 uint8_t _reserved2[4];
mbed_official 324:406fd2029f23 5726 __IO hw_dma_int_t INT; /*!< [0x24] Interrupt Request Register */
mbed_official 324:406fd2029f23 5727 uint8_t _reserved3[4];
mbed_official 324:406fd2029f23 5728 __IO hw_dma_err_t ERR; /*!< [0x2C] Error Register */
mbed_official 324:406fd2029f23 5729 uint8_t _reserved4[4];
mbed_official 324:406fd2029f23 5730 __I hw_dma_hrs_t HRS; /*!< [0x34] Hardware Request Status Register */
mbed_official 324:406fd2029f23 5731 uint8_t _reserved5[12];
mbed_official 324:406fd2029f23 5732 __IO hw_dma_ears_t EARS; /*!< [0x44] Enable Asynchronous Request in Stop Register */
mbed_official 324:406fd2029f23 5733 uint8_t _reserved6[184];
mbed_official 324:406fd2029f23 5734 __IO hw_dma_dchprin_t DCHPRIn[16]; /*!< [0x100] Channel n Priority Register */
mbed_official 324:406fd2029f23 5735 uint8_t _reserved7[3824];
mbed_official 324:406fd2029f23 5736 struct {
mbed_official 324:406fd2029f23 5737 __IO hw_dma_tcdn_saddr_t TCDn_SADDR; /*!< [0x1000] TCD Source Address */
mbed_official 324:406fd2029f23 5738 __IO hw_dma_tcdn_soff_t TCDn_SOFF; /*!< [0x1004] TCD Signed Source Address Offset */
mbed_official 324:406fd2029f23 5739 __IO hw_dma_tcdn_attr_t TCDn_ATTR; /*!< [0x1006] TCD Transfer Attributes */
mbed_official 324:406fd2029f23 5740 union {
mbed_official 324:406fd2029f23 5741 __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */
mbed_official 324:406fd2029f23 5742 __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
mbed_official 324:406fd2029f23 5743 __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
mbed_official 324:406fd2029f23 5744 };
mbed_official 324:406fd2029f23 5745 __IO hw_dma_tcdn_slast_t TCDn_SLAST; /*!< [0x100C] TCD Last Source Address Adjustment */
mbed_official 324:406fd2029f23 5746 __IO hw_dma_tcdn_daddr_t TCDn_DADDR; /*!< [0x1010] TCD Destination Address */
mbed_official 324:406fd2029f23 5747 __IO hw_dma_tcdn_doff_t TCDn_DOFF; /*!< [0x1014] TCD Signed Destination Address Offset */
mbed_official 324:406fd2029f23 5748 union {
mbed_official 324:406fd2029f23 5749 __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
mbed_official 324:406fd2029f23 5750 __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
mbed_official 324:406fd2029f23 5751 };
mbed_official 324:406fd2029f23 5752 __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */
mbed_official 324:406fd2029f23 5753 __IO hw_dma_tcdn_csr_t TCDn_CSR; /*!< [0x101C] TCD Control and Status */
mbed_official 324:406fd2029f23 5754 union {
mbed_official 324:406fd2029f23 5755 __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
mbed_official 324:406fd2029f23 5756 __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
mbed_official 324:406fd2029f23 5757 };
mbed_official 324:406fd2029f23 5758 } TCD[16];
mbed_official 324:406fd2029f23 5759 } hw_dma_t;
mbed_official 324:406fd2029f23 5760 #pragma pack()
mbed_official 324:406fd2029f23 5761
mbed_official 324:406fd2029f23 5762 /*! @brief Macro to access all DMA registers. */
mbed_official 324:406fd2029f23 5763 /*! @param x DMA module instance base address. */
mbed_official 324:406fd2029f23 5764 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 5765 * use the '&' operator, like <code>&HW_DMA(DMA_BASE)</code>. */
mbed_official 324:406fd2029f23 5766 #define HW_DMA(x) (*(hw_dma_t *)(x))
mbed_official 324:406fd2029f23 5767
mbed_official 324:406fd2029f23 5768 /*
mbed_official 324:406fd2029f23 5769 ** End of section using anonymous unions
mbed_official 324:406fd2029f23 5770 */
mbed_official 324:406fd2029f23 5771
mbed_official 324:406fd2029f23 5772 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 5773 #pragma pop
mbed_official 324:406fd2029f23 5774 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 5775 #pragma pop
mbed_official 324:406fd2029f23 5776 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 5777 /* leave anonymous unions enabled */
mbed_official 324:406fd2029f23 5778 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 5779 #pragma language=default
mbed_official 324:406fd2029f23 5780 #else
mbed_official 324:406fd2029f23 5781 #error Not supported compiler type
mbed_official 324:406fd2029f23 5782 #endif
mbed_official 324:406fd2029f23 5783
mbed_official 324:406fd2029f23 5784 #endif /* __HW_DMA_REGISTERS_H__ */
mbed_official 324:406fd2029f23 5785 /* EOF */