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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_dac.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_DAC_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_DAC_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 DAC
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * 12-Bit Digital-to-Analog Converter
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_DAC_DATnL - DAC Data Low Register
mbed_official 324:406fd2029f23 90 * - HW_DAC_DATnH - DAC Data High Register
mbed_official 324:406fd2029f23 91 * - HW_DAC_SR - DAC Status Register
mbed_official 324:406fd2029f23 92 * - HW_DAC_C0 - DAC Control Register
mbed_official 324:406fd2029f23 93 * - HW_DAC_C1 - DAC Control Register 1
mbed_official 324:406fd2029f23 94 * - HW_DAC_C2 - DAC Control Register 2
mbed_official 324:406fd2029f23 95 *
mbed_official 324:406fd2029f23 96 * - hw_dac_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 97 */
mbed_official 324:406fd2029f23 98
mbed_official 324:406fd2029f23 99 #define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
mbed_official 324:406fd2029f23 100 #define HW_DAC0 (0U) /*!< Instance number for DAC0. */
mbed_official 324:406fd2029f23 101 #define HW_DAC1 (1U) /*!< Instance number for DAC1. */
mbed_official 324:406fd2029f23 102
mbed_official 324:406fd2029f23 103 /*******************************************************************************
mbed_official 324:406fd2029f23 104 * HW_DAC_DATnL - DAC Data Low Register
mbed_official 324:406fd2029f23 105 ******************************************************************************/
mbed_official 324:406fd2029f23 106
mbed_official 324:406fd2029f23 107 /*!
mbed_official 324:406fd2029f23 108 * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
mbed_official 324:406fd2029f23 109 *
mbed_official 324:406fd2029f23 110 * Reset value: 0x00U
mbed_official 324:406fd2029f23 111 */
mbed_official 324:406fd2029f23 112 typedef union _hw_dac_datnl
mbed_official 324:406fd2029f23 113 {
mbed_official 324:406fd2029f23 114 uint8_t U;
mbed_official 324:406fd2029f23 115 struct _hw_dac_datnl_bitfields
mbed_official 324:406fd2029f23 116 {
mbed_official 324:406fd2029f23 117 uint8_t DATA0 : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 118 } B;
mbed_official 324:406fd2029f23 119 } hw_dac_datnl_t;
mbed_official 324:406fd2029f23 120
mbed_official 324:406fd2029f23 121 /*!
mbed_official 324:406fd2029f23 122 * @name Constants and macros for entire DAC_DATnL register
mbed_official 324:406fd2029f23 123 */
mbed_official 324:406fd2029f23 124 /*@{*/
mbed_official 324:406fd2029f23 125 #define HW_DAC_DATnL_COUNT (16U)
mbed_official 324:406fd2029f23 126
mbed_official 324:406fd2029f23 127 #define HW_DAC_DATnL_ADDR(x, n) ((x) + 0x0U + (0x2U * (n)))
mbed_official 324:406fd2029f23 128
mbed_official 324:406fd2029f23 129 #define HW_DAC_DATnL(x, n) (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
mbed_official 324:406fd2029f23 130 #define HW_DAC_DATnL_RD(x, n) (HW_DAC_DATnL(x, n).U)
mbed_official 324:406fd2029f23 131 #define HW_DAC_DATnL_WR(x, n, v) (HW_DAC_DATnL(x, n).U = (v))
mbed_official 324:406fd2029f23 132 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 133 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 134 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 135 /*@}*/
mbed_official 324:406fd2029f23 136
mbed_official 324:406fd2029f23 137 /*
mbed_official 324:406fd2029f23 138 * Constants & macros for individual DAC_DATnL bitfields
mbed_official 324:406fd2029f23 139 */
mbed_official 324:406fd2029f23 140
mbed_official 324:406fd2029f23 141 /*!
mbed_official 324:406fd2029f23 142 * @name Register DAC_DATnL, field DATA0[7:0] (RW)
mbed_official 324:406fd2029f23 143 *
mbed_official 324:406fd2029f23 144 * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
mbed_official 324:406fd2029f23 145 * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
mbed_official 324:406fd2029f23 146 * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
mbed_official 324:406fd2029f23 147 */
mbed_official 324:406fd2029f23 148 /*@{*/
mbed_official 324:406fd2029f23 149 #define BP_DAC_DATnL_DATA0 (0U) /*!< Bit position for DAC_DATnL_DATA0. */
mbed_official 324:406fd2029f23 150 #define BM_DAC_DATnL_DATA0 (0xFFU) /*!< Bit mask for DAC_DATnL_DATA0. */
mbed_official 324:406fd2029f23 151 #define BS_DAC_DATnL_DATA0 (8U) /*!< Bit field size in bits for DAC_DATnL_DATA0. */
mbed_official 324:406fd2029f23 152
mbed_official 324:406fd2029f23 153 /*! @brief Read current value of the DAC_DATnL_DATA0 field. */
mbed_official 324:406fd2029f23 154 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
mbed_official 324:406fd2029f23 155
mbed_official 324:406fd2029f23 156 /*! @brief Format value for bitfield DAC_DATnL_DATA0. */
mbed_official 324:406fd2029f23 157 #define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
mbed_official 324:406fd2029f23 158
mbed_official 324:406fd2029f23 159 /*! @brief Set the DATA0 field to a new value. */
mbed_official 324:406fd2029f23 160 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
mbed_official 324:406fd2029f23 161 /*@}*/
mbed_official 324:406fd2029f23 162 /*******************************************************************************
mbed_official 324:406fd2029f23 163 * HW_DAC_DATnH - DAC Data High Register
mbed_official 324:406fd2029f23 164 ******************************************************************************/
mbed_official 324:406fd2029f23 165
mbed_official 324:406fd2029f23 166 /*!
mbed_official 324:406fd2029f23 167 * @brief HW_DAC_DATnH - DAC Data High Register (RW)
mbed_official 324:406fd2029f23 168 *
mbed_official 324:406fd2029f23 169 * Reset value: 0x00U
mbed_official 324:406fd2029f23 170 */
mbed_official 324:406fd2029f23 171 typedef union _hw_dac_datnh
mbed_official 324:406fd2029f23 172 {
mbed_official 324:406fd2029f23 173 uint8_t U;
mbed_official 324:406fd2029f23 174 struct _hw_dac_datnh_bitfields
mbed_official 324:406fd2029f23 175 {
mbed_official 324:406fd2029f23 176 uint8_t DATA1 : 4; /*!< [3:0] */
mbed_official 324:406fd2029f23 177 uint8_t RESERVED0 : 4; /*!< [7:4] */
mbed_official 324:406fd2029f23 178 } B;
mbed_official 324:406fd2029f23 179 } hw_dac_datnh_t;
mbed_official 324:406fd2029f23 180
mbed_official 324:406fd2029f23 181 /*!
mbed_official 324:406fd2029f23 182 * @name Constants and macros for entire DAC_DATnH register
mbed_official 324:406fd2029f23 183 */
mbed_official 324:406fd2029f23 184 /*@{*/
mbed_official 324:406fd2029f23 185 #define HW_DAC_DATnH_COUNT (16U)
mbed_official 324:406fd2029f23 186
mbed_official 324:406fd2029f23 187 #define HW_DAC_DATnH_ADDR(x, n) ((x) + 0x1U + (0x2U * (n)))
mbed_official 324:406fd2029f23 188
mbed_official 324:406fd2029f23 189 #define HW_DAC_DATnH(x, n) (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
mbed_official 324:406fd2029f23 190 #define HW_DAC_DATnH_RD(x, n) (HW_DAC_DATnH(x, n).U)
mbed_official 324:406fd2029f23 191 #define HW_DAC_DATnH_WR(x, n, v) (HW_DAC_DATnH(x, n).U = (v))
mbed_official 324:406fd2029f23 192 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 193 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 194 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 195 /*@}*/
mbed_official 324:406fd2029f23 196
mbed_official 324:406fd2029f23 197 /*
mbed_official 324:406fd2029f23 198 * Constants & macros for individual DAC_DATnH bitfields
mbed_official 324:406fd2029f23 199 */
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 /*!
mbed_official 324:406fd2029f23 202 * @name Register DAC_DATnH, field DATA1[3:0] (RW)
mbed_official 324:406fd2029f23 203 *
mbed_official 324:406fd2029f23 204 * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
mbed_official 324:406fd2029f23 205 * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
mbed_official 324:406fd2029f23 206 * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
mbed_official 324:406fd2029f23 207 */
mbed_official 324:406fd2029f23 208 /*@{*/
mbed_official 324:406fd2029f23 209 #define BP_DAC_DATnH_DATA1 (0U) /*!< Bit position for DAC_DATnH_DATA1. */
mbed_official 324:406fd2029f23 210 #define BM_DAC_DATnH_DATA1 (0x0FU) /*!< Bit mask for DAC_DATnH_DATA1. */
mbed_official 324:406fd2029f23 211 #define BS_DAC_DATnH_DATA1 (4U) /*!< Bit field size in bits for DAC_DATnH_DATA1. */
mbed_official 324:406fd2029f23 212
mbed_official 324:406fd2029f23 213 /*! @brief Read current value of the DAC_DATnH_DATA1 field. */
mbed_official 324:406fd2029f23 214 #define BR_DAC_DATnH_DATA1(x, n) (HW_DAC_DATnH(x, n).B.DATA1)
mbed_official 324:406fd2029f23 215
mbed_official 324:406fd2029f23 216 /*! @brief Format value for bitfield DAC_DATnH_DATA1. */
mbed_official 324:406fd2029f23 217 #define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
mbed_official 324:406fd2029f23 218
mbed_official 324:406fd2029f23 219 /*! @brief Set the DATA1 field to a new value. */
mbed_official 324:406fd2029f23 220 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
mbed_official 324:406fd2029f23 221 /*@}*/
mbed_official 324:406fd2029f23 222
mbed_official 324:406fd2029f23 223 /*******************************************************************************
mbed_official 324:406fd2029f23 224 * HW_DAC_SR - DAC Status Register
mbed_official 324:406fd2029f23 225 ******************************************************************************/
mbed_official 324:406fd2029f23 226
mbed_official 324:406fd2029f23 227 /*!
mbed_official 324:406fd2029f23 228 * @brief HW_DAC_SR - DAC Status Register (RW)
mbed_official 324:406fd2029f23 229 *
mbed_official 324:406fd2029f23 230 * Reset value: 0x02U
mbed_official 324:406fd2029f23 231 *
mbed_official 324:406fd2029f23 232 * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
mbed_official 324:406fd2029f23 233 * request is done. Writing 0 to a field clears it whereas writing 1 has no
mbed_official 324:406fd2029f23 234 * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
mbed_official 324:406fd2029f23 235 * The flags are set only when the data buffer status is changed.
mbed_official 324:406fd2029f23 236 */
mbed_official 324:406fd2029f23 237 typedef union _hw_dac_sr
mbed_official 324:406fd2029f23 238 {
mbed_official 324:406fd2029f23 239 uint8_t U;
mbed_official 324:406fd2029f23 240 struct _hw_dac_sr_bitfields
mbed_official 324:406fd2029f23 241 {
mbed_official 324:406fd2029f23 242 uint8_t DACBFRPBF : 1; /*!< [0] DAC Buffer Read Pointer Bottom
mbed_official 324:406fd2029f23 243 * Position Flag */
mbed_official 324:406fd2029f23 244 uint8_t DACBFRPTF : 1; /*!< [1] DAC Buffer Read Pointer Top Position
mbed_official 324:406fd2029f23 245 * Flag */
mbed_official 324:406fd2029f23 246 uint8_t DACBFWMF : 1; /*!< [2] DAC Buffer Watermark Flag */
mbed_official 324:406fd2029f23 247 uint8_t RESERVED0 : 5; /*!< [7:3] */
mbed_official 324:406fd2029f23 248 } B;
mbed_official 324:406fd2029f23 249 } hw_dac_sr_t;
mbed_official 324:406fd2029f23 250
mbed_official 324:406fd2029f23 251 /*!
mbed_official 324:406fd2029f23 252 * @name Constants and macros for entire DAC_SR register
mbed_official 324:406fd2029f23 253 */
mbed_official 324:406fd2029f23 254 /*@{*/
mbed_official 324:406fd2029f23 255 #define HW_DAC_SR_ADDR(x) ((x) + 0x20U)
mbed_official 324:406fd2029f23 256
mbed_official 324:406fd2029f23 257 #define HW_DAC_SR(x) (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
mbed_official 324:406fd2029f23 258 #define HW_DAC_SR_RD(x) (HW_DAC_SR(x).U)
mbed_official 324:406fd2029f23 259 #define HW_DAC_SR_WR(x, v) (HW_DAC_SR(x).U = (v))
mbed_official 324:406fd2029f23 260 #define HW_DAC_SR_SET(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) | (v)))
mbed_official 324:406fd2029f23 261 #define HW_DAC_SR_CLR(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 262 #define HW_DAC_SR_TOG(x, v) (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 263 /*@}*/
mbed_official 324:406fd2029f23 264
mbed_official 324:406fd2029f23 265 /*
mbed_official 324:406fd2029f23 266 * Constants & macros for individual DAC_SR bitfields
mbed_official 324:406fd2029f23 267 */
mbed_official 324:406fd2029f23 268
mbed_official 324:406fd2029f23 269 /*!
mbed_official 324:406fd2029f23 270 * @name Register DAC_SR, field DACBFRPBF[0] (RW)
mbed_official 324:406fd2029f23 271 *
mbed_official 324:406fd2029f23 272 * In FIFO mode, it is FIFO FULL status bit. It means FIFO read pointer equals
mbed_official 324:406fd2029f23 273 * Write Pointer because of Write Pointer increase. If this bit is set, any write
mbed_official 324:406fd2029f23 274 * to FIFO from either DMA or CPU is ignored by DAC. It is cleared if there is
mbed_official 324:406fd2029f23 275 * any DAC trigger making the DAC read pointer increase. Write to this bit is
mbed_official 324:406fd2029f23 276 * ignored in FIFO mode.
mbed_official 324:406fd2029f23 277 *
mbed_official 324:406fd2029f23 278 * Values:
mbed_official 324:406fd2029f23 279 * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
mbed_official 324:406fd2029f23 280 * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
mbed_official 324:406fd2029f23 281 */
mbed_official 324:406fd2029f23 282 /*@{*/
mbed_official 324:406fd2029f23 283 #define BP_DAC_SR_DACBFRPBF (0U) /*!< Bit position for DAC_SR_DACBFRPBF. */
mbed_official 324:406fd2029f23 284 #define BM_DAC_SR_DACBFRPBF (0x01U) /*!< Bit mask for DAC_SR_DACBFRPBF. */
mbed_official 324:406fd2029f23 285 #define BS_DAC_SR_DACBFRPBF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
mbed_official 324:406fd2029f23 286
mbed_official 324:406fd2029f23 287 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
mbed_official 324:406fd2029f23 288 #define BR_DAC_SR_DACBFRPBF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF))
mbed_official 324:406fd2029f23 289
mbed_official 324:406fd2029f23 290 /*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
mbed_official 324:406fd2029f23 291 #define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
mbed_official 324:406fd2029f23 292
mbed_official 324:406fd2029f23 293 /*! @brief Set the DACBFRPBF field to a new value. */
mbed_official 324:406fd2029f23 294 #define BW_DAC_SR_DACBFRPBF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF) = (v))
mbed_official 324:406fd2029f23 295 /*@}*/
mbed_official 324:406fd2029f23 296
mbed_official 324:406fd2029f23 297 /*!
mbed_official 324:406fd2029f23 298 * @name Register DAC_SR, field DACBFRPTF[1] (RW)
mbed_official 324:406fd2029f23 299 *
mbed_official 324:406fd2029f23 300 * In FIFO mode, it is FIFO nearly empty flag. It is set when only one data
mbed_official 324:406fd2029f23 301 * remains in FIFO. Any DAC trigger does not increase the Read Pointer if this bit is
mbed_official 324:406fd2029f23 302 * set to avoid any possible glitch or abrupt change at DAC output. It is
mbed_official 324:406fd2029f23 303 * cleared automatically if FIFO is not empty.
mbed_official 324:406fd2029f23 304 *
mbed_official 324:406fd2029f23 305 * Values:
mbed_official 324:406fd2029f23 306 * - 0 - The DAC buffer read pointer is not zero.
mbed_official 324:406fd2029f23 307 * - 1 - The DAC buffer read pointer is zero.
mbed_official 324:406fd2029f23 308 */
mbed_official 324:406fd2029f23 309 /*@{*/
mbed_official 324:406fd2029f23 310 #define BP_DAC_SR_DACBFRPTF (1U) /*!< Bit position for DAC_SR_DACBFRPTF. */
mbed_official 324:406fd2029f23 311 #define BM_DAC_SR_DACBFRPTF (0x02U) /*!< Bit mask for DAC_SR_DACBFRPTF. */
mbed_official 324:406fd2029f23 312 #define BS_DAC_SR_DACBFRPTF (1U) /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
mbed_official 324:406fd2029f23 313
mbed_official 324:406fd2029f23 314 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
mbed_official 324:406fd2029f23 315 #define BR_DAC_SR_DACBFRPTF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF))
mbed_official 324:406fd2029f23 316
mbed_official 324:406fd2029f23 317 /*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
mbed_official 324:406fd2029f23 318 #define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
mbed_official 324:406fd2029f23 319
mbed_official 324:406fd2029f23 320 /*! @brief Set the DACBFRPTF field to a new value. */
mbed_official 324:406fd2029f23 321 #define BW_DAC_SR_DACBFRPTF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF) = (v))
mbed_official 324:406fd2029f23 322 /*@}*/
mbed_official 324:406fd2029f23 323
mbed_official 324:406fd2029f23 324 /*!
mbed_official 324:406fd2029f23 325 * @name Register DAC_SR, field DACBFWMF[2] (RW)
mbed_official 324:406fd2029f23 326 *
mbed_official 324:406fd2029f23 327 * This bit is set if the remaining FIFO data is less than the watermark
mbed_official 324:406fd2029f23 328 * setting. It is cleared automatically by writing data into FIFO by DMA or CPU. Write
mbed_official 324:406fd2029f23 329 * to this bit is ignored in FIFO mode.
mbed_official 324:406fd2029f23 330 *
mbed_official 324:406fd2029f23 331 * Values:
mbed_official 324:406fd2029f23 332 * - 0 - The DAC buffer read pointer has not reached the watermark level.
mbed_official 324:406fd2029f23 333 * - 1 - The DAC buffer read pointer has reached the watermark level.
mbed_official 324:406fd2029f23 334 */
mbed_official 324:406fd2029f23 335 /*@{*/
mbed_official 324:406fd2029f23 336 #define BP_DAC_SR_DACBFWMF (2U) /*!< Bit position for DAC_SR_DACBFWMF. */
mbed_official 324:406fd2029f23 337 #define BM_DAC_SR_DACBFWMF (0x04U) /*!< Bit mask for DAC_SR_DACBFWMF. */
mbed_official 324:406fd2029f23 338 #define BS_DAC_SR_DACBFWMF (1U) /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
mbed_official 324:406fd2029f23 339
mbed_official 324:406fd2029f23 340 /*! @brief Read current value of the DAC_SR_DACBFWMF field. */
mbed_official 324:406fd2029f23 341 #define BR_DAC_SR_DACBFWMF(x) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF))
mbed_official 324:406fd2029f23 342
mbed_official 324:406fd2029f23 343 /*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
mbed_official 324:406fd2029f23 344 #define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
mbed_official 324:406fd2029f23 345
mbed_official 324:406fd2029f23 346 /*! @brief Set the DACBFWMF field to a new value. */
mbed_official 324:406fd2029f23 347 #define BW_DAC_SR_DACBFWMF(x, v) (BITBAND_ACCESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF) = (v))
mbed_official 324:406fd2029f23 348 /*@}*/
mbed_official 324:406fd2029f23 349
mbed_official 324:406fd2029f23 350 /*******************************************************************************
mbed_official 324:406fd2029f23 351 * HW_DAC_C0 - DAC Control Register
mbed_official 324:406fd2029f23 352 ******************************************************************************/
mbed_official 324:406fd2029f23 353
mbed_official 324:406fd2029f23 354 /*!
mbed_official 324:406fd2029f23 355 * @brief HW_DAC_C0 - DAC Control Register (RW)
mbed_official 324:406fd2029f23 356 *
mbed_official 324:406fd2029f23 357 * Reset value: 0x00U
mbed_official 324:406fd2029f23 358 */
mbed_official 324:406fd2029f23 359 typedef union _hw_dac_c0
mbed_official 324:406fd2029f23 360 {
mbed_official 324:406fd2029f23 361 uint8_t U;
mbed_official 324:406fd2029f23 362 struct _hw_dac_c0_bitfields
mbed_official 324:406fd2029f23 363 {
mbed_official 324:406fd2029f23 364 uint8_t DACBBIEN : 1; /*!< [0] DAC Buffer Read Pointer Bottom Flag
mbed_official 324:406fd2029f23 365 * Interrupt Enable */
mbed_official 324:406fd2029f23 366 uint8_t DACBTIEN : 1; /*!< [1] DAC Buffer Read Pointer Top Flag
mbed_official 324:406fd2029f23 367 * Interrupt Enable */
mbed_official 324:406fd2029f23 368 uint8_t DACBWIEN : 1; /*!< [2] DAC Buffer Watermark Interrupt Enable
mbed_official 324:406fd2029f23 369 * */
mbed_official 324:406fd2029f23 370 uint8_t LPEN : 1; /*!< [3] DAC Low Power Control */
mbed_official 324:406fd2029f23 371 uint8_t DACSWTRG : 1; /*!< [4] DAC Software Trigger */
mbed_official 324:406fd2029f23 372 uint8_t DACTRGSEL : 1; /*!< [5] DAC Trigger Select */
mbed_official 324:406fd2029f23 373 uint8_t DACRFS : 1; /*!< [6] DAC Reference Select */
mbed_official 324:406fd2029f23 374 uint8_t DACEN : 1; /*!< [7] DAC Enable */
mbed_official 324:406fd2029f23 375 } B;
mbed_official 324:406fd2029f23 376 } hw_dac_c0_t;
mbed_official 324:406fd2029f23 377
mbed_official 324:406fd2029f23 378 /*!
mbed_official 324:406fd2029f23 379 * @name Constants and macros for entire DAC_C0 register
mbed_official 324:406fd2029f23 380 */
mbed_official 324:406fd2029f23 381 /*@{*/
mbed_official 324:406fd2029f23 382 #define HW_DAC_C0_ADDR(x) ((x) + 0x21U)
mbed_official 324:406fd2029f23 383
mbed_official 324:406fd2029f23 384 #define HW_DAC_C0(x) (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
mbed_official 324:406fd2029f23 385 #define HW_DAC_C0_RD(x) (HW_DAC_C0(x).U)
mbed_official 324:406fd2029f23 386 #define HW_DAC_C0_WR(x, v) (HW_DAC_C0(x).U = (v))
mbed_official 324:406fd2029f23 387 #define HW_DAC_C0_SET(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) | (v)))
mbed_official 324:406fd2029f23 388 #define HW_DAC_C0_CLR(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 389 #define HW_DAC_C0_TOG(x, v) (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 390 /*@}*/
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392 /*
mbed_official 324:406fd2029f23 393 * Constants & macros for individual DAC_C0 bitfields
mbed_official 324:406fd2029f23 394 */
mbed_official 324:406fd2029f23 395
mbed_official 324:406fd2029f23 396 /*!
mbed_official 324:406fd2029f23 397 * @name Register DAC_C0, field DACBBIEN[0] (RW)
mbed_official 324:406fd2029f23 398 *
mbed_official 324:406fd2029f23 399 * Values:
mbed_official 324:406fd2029f23 400 * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
mbed_official 324:406fd2029f23 401 * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
mbed_official 324:406fd2029f23 402 */
mbed_official 324:406fd2029f23 403 /*@{*/
mbed_official 324:406fd2029f23 404 #define BP_DAC_C0_DACBBIEN (0U) /*!< Bit position for DAC_C0_DACBBIEN. */
mbed_official 324:406fd2029f23 405 #define BM_DAC_C0_DACBBIEN (0x01U) /*!< Bit mask for DAC_C0_DACBBIEN. */
mbed_official 324:406fd2029f23 406 #define BS_DAC_C0_DACBBIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
mbed_official 324:406fd2029f23 407
mbed_official 324:406fd2029f23 408 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
mbed_official 324:406fd2029f23 409 #define BR_DAC_C0_DACBBIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN))
mbed_official 324:406fd2029f23 410
mbed_official 324:406fd2029f23 411 /*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
mbed_official 324:406fd2029f23 412 #define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
mbed_official 324:406fd2029f23 413
mbed_official 324:406fd2029f23 414 /*! @brief Set the DACBBIEN field to a new value. */
mbed_official 324:406fd2029f23 415 #define BW_DAC_C0_DACBBIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN) = (v))
mbed_official 324:406fd2029f23 416 /*@}*/
mbed_official 324:406fd2029f23 417
mbed_official 324:406fd2029f23 418 /*!
mbed_official 324:406fd2029f23 419 * @name Register DAC_C0, field DACBTIEN[1] (RW)
mbed_official 324:406fd2029f23 420 *
mbed_official 324:406fd2029f23 421 * Values:
mbed_official 324:406fd2029f23 422 * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
mbed_official 324:406fd2029f23 423 * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
mbed_official 324:406fd2029f23 424 */
mbed_official 324:406fd2029f23 425 /*@{*/
mbed_official 324:406fd2029f23 426 #define BP_DAC_C0_DACBTIEN (1U) /*!< Bit position for DAC_C0_DACBTIEN. */
mbed_official 324:406fd2029f23 427 #define BM_DAC_C0_DACBTIEN (0x02U) /*!< Bit mask for DAC_C0_DACBTIEN. */
mbed_official 324:406fd2029f23 428 #define BS_DAC_C0_DACBTIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
mbed_official 324:406fd2029f23 429
mbed_official 324:406fd2029f23 430 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
mbed_official 324:406fd2029f23 431 #define BR_DAC_C0_DACBTIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN))
mbed_official 324:406fd2029f23 432
mbed_official 324:406fd2029f23 433 /*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
mbed_official 324:406fd2029f23 434 #define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
mbed_official 324:406fd2029f23 435
mbed_official 324:406fd2029f23 436 /*! @brief Set the DACBTIEN field to a new value. */
mbed_official 324:406fd2029f23 437 #define BW_DAC_C0_DACBTIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN) = (v))
mbed_official 324:406fd2029f23 438 /*@}*/
mbed_official 324:406fd2029f23 439
mbed_official 324:406fd2029f23 440 /*!
mbed_official 324:406fd2029f23 441 * @name Register DAC_C0, field DACBWIEN[2] (RW)
mbed_official 324:406fd2029f23 442 *
mbed_official 324:406fd2029f23 443 * Values:
mbed_official 324:406fd2029f23 444 * - 0 - The DAC buffer watermark interrupt is disabled.
mbed_official 324:406fd2029f23 445 * - 1 - The DAC buffer watermark interrupt is enabled.
mbed_official 324:406fd2029f23 446 */
mbed_official 324:406fd2029f23 447 /*@{*/
mbed_official 324:406fd2029f23 448 #define BP_DAC_C0_DACBWIEN (2U) /*!< Bit position for DAC_C0_DACBWIEN. */
mbed_official 324:406fd2029f23 449 #define BM_DAC_C0_DACBWIEN (0x04U) /*!< Bit mask for DAC_C0_DACBWIEN. */
mbed_official 324:406fd2029f23 450 #define BS_DAC_C0_DACBWIEN (1U) /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
mbed_official 324:406fd2029f23 451
mbed_official 324:406fd2029f23 452 /*! @brief Read current value of the DAC_C0_DACBWIEN field. */
mbed_official 324:406fd2029f23 453 #define BR_DAC_C0_DACBWIEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN))
mbed_official 324:406fd2029f23 454
mbed_official 324:406fd2029f23 455 /*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
mbed_official 324:406fd2029f23 456 #define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
mbed_official 324:406fd2029f23 457
mbed_official 324:406fd2029f23 458 /*! @brief Set the DACBWIEN field to a new value. */
mbed_official 324:406fd2029f23 459 #define BW_DAC_C0_DACBWIEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN) = (v))
mbed_official 324:406fd2029f23 460 /*@}*/
mbed_official 324:406fd2029f23 461
mbed_official 324:406fd2029f23 462 /*!
mbed_official 324:406fd2029f23 463 * @name Register DAC_C0, field LPEN[3] (RW)
mbed_official 324:406fd2029f23 464 *
mbed_official 324:406fd2029f23 465 * See the 12-bit DAC electrical characteristics of the device data sheet for
mbed_official 324:406fd2029f23 466 * details on the impact of the modes below.
mbed_official 324:406fd2029f23 467 *
mbed_official 324:406fd2029f23 468 * Values:
mbed_official 324:406fd2029f23 469 * - 0 - High-Power mode
mbed_official 324:406fd2029f23 470 * - 1 - Low-Power mode
mbed_official 324:406fd2029f23 471 */
mbed_official 324:406fd2029f23 472 /*@{*/
mbed_official 324:406fd2029f23 473 #define BP_DAC_C0_LPEN (3U) /*!< Bit position for DAC_C0_LPEN. */
mbed_official 324:406fd2029f23 474 #define BM_DAC_C0_LPEN (0x08U) /*!< Bit mask for DAC_C0_LPEN. */
mbed_official 324:406fd2029f23 475 #define BS_DAC_C0_LPEN (1U) /*!< Bit field size in bits for DAC_C0_LPEN. */
mbed_official 324:406fd2029f23 476
mbed_official 324:406fd2029f23 477 /*! @brief Read current value of the DAC_C0_LPEN field. */
mbed_official 324:406fd2029f23 478 #define BR_DAC_C0_LPEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN))
mbed_official 324:406fd2029f23 479
mbed_official 324:406fd2029f23 480 /*! @brief Format value for bitfield DAC_C0_LPEN. */
mbed_official 324:406fd2029f23 481 #define BF_DAC_C0_LPEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
mbed_official 324:406fd2029f23 482
mbed_official 324:406fd2029f23 483 /*! @brief Set the LPEN field to a new value. */
mbed_official 324:406fd2029f23 484 #define BW_DAC_C0_LPEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN) = (v))
mbed_official 324:406fd2029f23 485 /*@}*/
mbed_official 324:406fd2029f23 486
mbed_official 324:406fd2029f23 487 /*!
mbed_official 324:406fd2029f23 488 * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
mbed_official 324:406fd2029f23 489 *
mbed_official 324:406fd2029f23 490 * Active high. This is a write-only field, which always reads 0. If DAC
mbed_official 324:406fd2029f23 491 * software trigger is selected and buffer is enabled, writing 1 to this field will
mbed_official 324:406fd2029f23 492 * advance the buffer read pointer once.
mbed_official 324:406fd2029f23 493 *
mbed_official 324:406fd2029f23 494 * Values:
mbed_official 324:406fd2029f23 495 * - 0 - The DAC soft trigger is not valid.
mbed_official 324:406fd2029f23 496 * - 1 - The DAC soft trigger is valid.
mbed_official 324:406fd2029f23 497 */
mbed_official 324:406fd2029f23 498 /*@{*/
mbed_official 324:406fd2029f23 499 #define BP_DAC_C0_DACSWTRG (4U) /*!< Bit position for DAC_C0_DACSWTRG. */
mbed_official 324:406fd2029f23 500 #define BM_DAC_C0_DACSWTRG (0x10U) /*!< Bit mask for DAC_C0_DACSWTRG. */
mbed_official 324:406fd2029f23 501 #define BS_DAC_C0_DACSWTRG (1U) /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
mbed_official 324:406fd2029f23 502
mbed_official 324:406fd2029f23 503 /*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
mbed_official 324:406fd2029f23 504 #define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
mbed_official 324:406fd2029f23 505
mbed_official 324:406fd2029f23 506 /*! @brief Set the DACSWTRG field to a new value. */
mbed_official 324:406fd2029f23 507 #define BW_DAC_C0_DACSWTRG(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG) = (v))
mbed_official 324:406fd2029f23 508 /*@}*/
mbed_official 324:406fd2029f23 509
mbed_official 324:406fd2029f23 510 /*!
mbed_official 324:406fd2029f23 511 * @name Register DAC_C0, field DACTRGSEL[5] (RW)
mbed_official 324:406fd2029f23 512 *
mbed_official 324:406fd2029f23 513 * Values:
mbed_official 324:406fd2029f23 514 * - 0 - The DAC hardware trigger is selected.
mbed_official 324:406fd2029f23 515 * - 1 - The DAC software trigger is selected.
mbed_official 324:406fd2029f23 516 */
mbed_official 324:406fd2029f23 517 /*@{*/
mbed_official 324:406fd2029f23 518 #define BP_DAC_C0_DACTRGSEL (5U) /*!< Bit position for DAC_C0_DACTRGSEL. */
mbed_official 324:406fd2029f23 519 #define BM_DAC_C0_DACTRGSEL (0x20U) /*!< Bit mask for DAC_C0_DACTRGSEL. */
mbed_official 324:406fd2029f23 520 #define BS_DAC_C0_DACTRGSEL (1U) /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
mbed_official 324:406fd2029f23 521
mbed_official 324:406fd2029f23 522 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
mbed_official 324:406fd2029f23 523 #define BR_DAC_C0_DACTRGSEL(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL))
mbed_official 324:406fd2029f23 524
mbed_official 324:406fd2029f23 525 /*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
mbed_official 324:406fd2029f23 526 #define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
mbed_official 324:406fd2029f23 527
mbed_official 324:406fd2029f23 528 /*! @brief Set the DACTRGSEL field to a new value. */
mbed_official 324:406fd2029f23 529 #define BW_DAC_C0_DACTRGSEL(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL) = (v))
mbed_official 324:406fd2029f23 530 /*@}*/
mbed_official 324:406fd2029f23 531
mbed_official 324:406fd2029f23 532 /*!
mbed_official 324:406fd2029f23 533 * @name Register DAC_C0, field DACRFS[6] (RW)
mbed_official 324:406fd2029f23 534 *
mbed_official 324:406fd2029f23 535 * Values:
mbed_official 324:406fd2029f23 536 * - 0 - The DAC selects DACREF_1 as the reference voltage.
mbed_official 324:406fd2029f23 537 * - 1 - The DAC selects DACREF_2 as the reference voltage.
mbed_official 324:406fd2029f23 538 */
mbed_official 324:406fd2029f23 539 /*@{*/
mbed_official 324:406fd2029f23 540 #define BP_DAC_C0_DACRFS (6U) /*!< Bit position for DAC_C0_DACRFS. */
mbed_official 324:406fd2029f23 541 #define BM_DAC_C0_DACRFS (0x40U) /*!< Bit mask for DAC_C0_DACRFS. */
mbed_official 324:406fd2029f23 542 #define BS_DAC_C0_DACRFS (1U) /*!< Bit field size in bits for DAC_C0_DACRFS. */
mbed_official 324:406fd2029f23 543
mbed_official 324:406fd2029f23 544 /*! @brief Read current value of the DAC_C0_DACRFS field. */
mbed_official 324:406fd2029f23 545 #define BR_DAC_C0_DACRFS(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS))
mbed_official 324:406fd2029f23 546
mbed_official 324:406fd2029f23 547 /*! @brief Format value for bitfield DAC_C0_DACRFS. */
mbed_official 324:406fd2029f23 548 #define BF_DAC_C0_DACRFS(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
mbed_official 324:406fd2029f23 549
mbed_official 324:406fd2029f23 550 /*! @brief Set the DACRFS field to a new value. */
mbed_official 324:406fd2029f23 551 #define BW_DAC_C0_DACRFS(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS) = (v))
mbed_official 324:406fd2029f23 552 /*@}*/
mbed_official 324:406fd2029f23 553
mbed_official 324:406fd2029f23 554 /*!
mbed_official 324:406fd2029f23 555 * @name Register DAC_C0, field DACEN[7] (RW)
mbed_official 324:406fd2029f23 556 *
mbed_official 324:406fd2029f23 557 * Starts the Programmable Reference Generator operation.
mbed_official 324:406fd2029f23 558 *
mbed_official 324:406fd2029f23 559 * Values:
mbed_official 324:406fd2029f23 560 * - 0 - The DAC system is disabled.
mbed_official 324:406fd2029f23 561 * - 1 - The DAC system is enabled.
mbed_official 324:406fd2029f23 562 */
mbed_official 324:406fd2029f23 563 /*@{*/
mbed_official 324:406fd2029f23 564 #define BP_DAC_C0_DACEN (7U) /*!< Bit position for DAC_C0_DACEN. */
mbed_official 324:406fd2029f23 565 #define BM_DAC_C0_DACEN (0x80U) /*!< Bit mask for DAC_C0_DACEN. */
mbed_official 324:406fd2029f23 566 #define BS_DAC_C0_DACEN (1U) /*!< Bit field size in bits for DAC_C0_DACEN. */
mbed_official 324:406fd2029f23 567
mbed_official 324:406fd2029f23 568 /*! @brief Read current value of the DAC_C0_DACEN field. */
mbed_official 324:406fd2029f23 569 #define BR_DAC_C0_DACEN(x) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN))
mbed_official 324:406fd2029f23 570
mbed_official 324:406fd2029f23 571 /*! @brief Format value for bitfield DAC_C0_DACEN. */
mbed_official 324:406fd2029f23 572 #define BF_DAC_C0_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
mbed_official 324:406fd2029f23 573
mbed_official 324:406fd2029f23 574 /*! @brief Set the DACEN field to a new value. */
mbed_official 324:406fd2029f23 575 #define BW_DAC_C0_DACEN(x, v) (BITBAND_ACCESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN) = (v))
mbed_official 324:406fd2029f23 576 /*@}*/
mbed_official 324:406fd2029f23 577
mbed_official 324:406fd2029f23 578 /*******************************************************************************
mbed_official 324:406fd2029f23 579 * HW_DAC_C1 - DAC Control Register 1
mbed_official 324:406fd2029f23 580 ******************************************************************************/
mbed_official 324:406fd2029f23 581
mbed_official 324:406fd2029f23 582 /*!
mbed_official 324:406fd2029f23 583 * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
mbed_official 324:406fd2029f23 584 *
mbed_official 324:406fd2029f23 585 * Reset value: 0x00U
mbed_official 324:406fd2029f23 586 */
mbed_official 324:406fd2029f23 587 typedef union _hw_dac_c1
mbed_official 324:406fd2029f23 588 {
mbed_official 324:406fd2029f23 589 uint8_t U;
mbed_official 324:406fd2029f23 590 struct _hw_dac_c1_bitfields
mbed_official 324:406fd2029f23 591 {
mbed_official 324:406fd2029f23 592 uint8_t DACBFEN : 1; /*!< [0] DAC Buffer Enable */
mbed_official 324:406fd2029f23 593 uint8_t DACBFMD : 2; /*!< [2:1] DAC Buffer Work Mode Select */
mbed_official 324:406fd2029f23 594 uint8_t DACBFWM : 2; /*!< [4:3] DAC Buffer Watermark Select */
mbed_official 324:406fd2029f23 595 uint8_t RESERVED0 : 2; /*!< [6:5] */
mbed_official 324:406fd2029f23 596 uint8_t DMAEN : 1; /*!< [7] DMA Enable Select */
mbed_official 324:406fd2029f23 597 } B;
mbed_official 324:406fd2029f23 598 } hw_dac_c1_t;
mbed_official 324:406fd2029f23 599
mbed_official 324:406fd2029f23 600 /*!
mbed_official 324:406fd2029f23 601 * @name Constants and macros for entire DAC_C1 register
mbed_official 324:406fd2029f23 602 */
mbed_official 324:406fd2029f23 603 /*@{*/
mbed_official 324:406fd2029f23 604 #define HW_DAC_C1_ADDR(x) ((x) + 0x22U)
mbed_official 324:406fd2029f23 605
mbed_official 324:406fd2029f23 606 #define HW_DAC_C1(x) (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
mbed_official 324:406fd2029f23 607 #define HW_DAC_C1_RD(x) (HW_DAC_C1(x).U)
mbed_official 324:406fd2029f23 608 #define HW_DAC_C1_WR(x, v) (HW_DAC_C1(x).U = (v))
mbed_official 324:406fd2029f23 609 #define HW_DAC_C1_SET(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) | (v)))
mbed_official 324:406fd2029f23 610 #define HW_DAC_C1_CLR(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 611 #define HW_DAC_C1_TOG(x, v) (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 612 /*@}*/
mbed_official 324:406fd2029f23 613
mbed_official 324:406fd2029f23 614 /*
mbed_official 324:406fd2029f23 615 * Constants & macros for individual DAC_C1 bitfields
mbed_official 324:406fd2029f23 616 */
mbed_official 324:406fd2029f23 617
mbed_official 324:406fd2029f23 618 /*!
mbed_official 324:406fd2029f23 619 * @name Register DAC_C1, field DACBFEN[0] (RW)
mbed_official 324:406fd2029f23 620 *
mbed_official 324:406fd2029f23 621 * Values:
mbed_official 324:406fd2029f23 622 * - 0 - Buffer read pointer is disabled. The converted data is always the first
mbed_official 324:406fd2029f23 623 * word of the buffer.
mbed_official 324:406fd2029f23 624 * - 1 - Buffer read pointer is enabled. The converted data is the word that the
mbed_official 324:406fd2029f23 625 * read pointer points to. It means converted data can be from any word of
mbed_official 324:406fd2029f23 626 * the buffer.
mbed_official 324:406fd2029f23 627 */
mbed_official 324:406fd2029f23 628 /*@{*/
mbed_official 324:406fd2029f23 629 #define BP_DAC_C1_DACBFEN (0U) /*!< Bit position for DAC_C1_DACBFEN. */
mbed_official 324:406fd2029f23 630 #define BM_DAC_C1_DACBFEN (0x01U) /*!< Bit mask for DAC_C1_DACBFEN. */
mbed_official 324:406fd2029f23 631 #define BS_DAC_C1_DACBFEN (1U) /*!< Bit field size in bits for DAC_C1_DACBFEN. */
mbed_official 324:406fd2029f23 632
mbed_official 324:406fd2029f23 633 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
mbed_official 324:406fd2029f23 634 #define BR_DAC_C1_DACBFEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN))
mbed_official 324:406fd2029f23 635
mbed_official 324:406fd2029f23 636 /*! @brief Format value for bitfield DAC_C1_DACBFEN. */
mbed_official 324:406fd2029f23 637 #define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
mbed_official 324:406fd2029f23 638
mbed_official 324:406fd2029f23 639 /*! @brief Set the DACBFEN field to a new value. */
mbed_official 324:406fd2029f23 640 #define BW_DAC_C1_DACBFEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN) = (v))
mbed_official 324:406fd2029f23 641 /*@}*/
mbed_official 324:406fd2029f23 642
mbed_official 324:406fd2029f23 643 /*!
mbed_official 324:406fd2029f23 644 * @name Register DAC_C1, field DACBFMD[2:1] (RW)
mbed_official 324:406fd2029f23 645 *
mbed_official 324:406fd2029f23 646 * Values:
mbed_official 324:406fd2029f23 647 * - 00 - Normal mode
mbed_official 324:406fd2029f23 648 * - 01 - Swing mode
mbed_official 324:406fd2029f23 649 * - 10 - One-Time Scan mode
mbed_official 324:406fd2029f23 650 * - 11 - FIFO mode
mbed_official 324:406fd2029f23 651 */
mbed_official 324:406fd2029f23 652 /*@{*/
mbed_official 324:406fd2029f23 653 #define BP_DAC_C1_DACBFMD (1U) /*!< Bit position for DAC_C1_DACBFMD. */
mbed_official 324:406fd2029f23 654 #define BM_DAC_C1_DACBFMD (0x06U) /*!< Bit mask for DAC_C1_DACBFMD. */
mbed_official 324:406fd2029f23 655 #define BS_DAC_C1_DACBFMD (2U) /*!< Bit field size in bits for DAC_C1_DACBFMD. */
mbed_official 324:406fd2029f23 656
mbed_official 324:406fd2029f23 657 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
mbed_official 324:406fd2029f23 658 #define BR_DAC_C1_DACBFMD(x) (HW_DAC_C1(x).B.DACBFMD)
mbed_official 324:406fd2029f23 659
mbed_official 324:406fd2029f23 660 /*! @brief Format value for bitfield DAC_C1_DACBFMD. */
mbed_official 324:406fd2029f23 661 #define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
mbed_official 324:406fd2029f23 662
mbed_official 324:406fd2029f23 663 /*! @brief Set the DACBFMD field to a new value. */
mbed_official 324:406fd2029f23 664 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
mbed_official 324:406fd2029f23 665 /*@}*/
mbed_official 324:406fd2029f23 666
mbed_official 324:406fd2029f23 667 /*!
mbed_official 324:406fd2029f23 668 * @name Register DAC_C1, field DACBFWM[4:3] (RW)
mbed_official 324:406fd2029f23 669 *
mbed_official 324:406fd2029f23 670 * In normal mode it controls when SR[DACBFWMF] is set. When the DAC buffer read
mbed_official 324:406fd2029f23 671 * pointer reaches the word defined by this field, which is 1-4 words away from
mbed_official 324:406fd2029f23 672 * the upper limit (DACBUP), SR[DACBFWMF] will be set. This allows user
mbed_official 324:406fd2029f23 673 * configuration of the watermark interrupt. In FIFO mode, it is FIFO watermark select
mbed_official 324:406fd2029f23 674 * field.
mbed_official 324:406fd2029f23 675 *
mbed_official 324:406fd2029f23 676 * Values:
mbed_official 324:406fd2029f23 677 * - 00 - In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining
mbed_official 324:406fd2029f23 678 * in FIFO will set watermark status bit.
mbed_official 324:406fd2029f23 679 * - 01 - In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data
mbed_official 324:406fd2029f23 680 * remaining in FIFO will set watermark status bit.
mbed_official 324:406fd2029f23 681 * - 10 - In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data
mbed_official 324:406fd2029f23 682 * remaining in FIFO will set watermark status bit.
mbed_official 324:406fd2029f23 683 * - 11 - In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data
mbed_official 324:406fd2029f23 684 * remaining in FIFO will set watermark status bit.
mbed_official 324:406fd2029f23 685 */
mbed_official 324:406fd2029f23 686 /*@{*/
mbed_official 324:406fd2029f23 687 #define BP_DAC_C1_DACBFWM (3U) /*!< Bit position for DAC_C1_DACBFWM. */
mbed_official 324:406fd2029f23 688 #define BM_DAC_C1_DACBFWM (0x18U) /*!< Bit mask for DAC_C1_DACBFWM. */
mbed_official 324:406fd2029f23 689 #define BS_DAC_C1_DACBFWM (2U) /*!< Bit field size in bits for DAC_C1_DACBFWM. */
mbed_official 324:406fd2029f23 690
mbed_official 324:406fd2029f23 691 /*! @brief Read current value of the DAC_C1_DACBFWM field. */
mbed_official 324:406fd2029f23 692 #define BR_DAC_C1_DACBFWM(x) (HW_DAC_C1(x).B.DACBFWM)
mbed_official 324:406fd2029f23 693
mbed_official 324:406fd2029f23 694 /*! @brief Format value for bitfield DAC_C1_DACBFWM. */
mbed_official 324:406fd2029f23 695 #define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
mbed_official 324:406fd2029f23 696
mbed_official 324:406fd2029f23 697 /*! @brief Set the DACBFWM field to a new value. */
mbed_official 324:406fd2029f23 698 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
mbed_official 324:406fd2029f23 699 /*@}*/
mbed_official 324:406fd2029f23 700
mbed_official 324:406fd2029f23 701 /*!
mbed_official 324:406fd2029f23 702 * @name Register DAC_C1, field DMAEN[7] (RW)
mbed_official 324:406fd2029f23 703 *
mbed_official 324:406fd2029f23 704 * Values:
mbed_official 324:406fd2029f23 705 * - 0 - DMA is disabled.
mbed_official 324:406fd2029f23 706 * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
mbed_official 324:406fd2029f23 707 * by original interrupts. The interrupts will not be presented on this
mbed_official 324:406fd2029f23 708 * module at the same time.
mbed_official 324:406fd2029f23 709 */
mbed_official 324:406fd2029f23 710 /*@{*/
mbed_official 324:406fd2029f23 711 #define BP_DAC_C1_DMAEN (7U) /*!< Bit position for DAC_C1_DMAEN. */
mbed_official 324:406fd2029f23 712 #define BM_DAC_C1_DMAEN (0x80U) /*!< Bit mask for DAC_C1_DMAEN. */
mbed_official 324:406fd2029f23 713 #define BS_DAC_C1_DMAEN (1U) /*!< Bit field size in bits for DAC_C1_DMAEN. */
mbed_official 324:406fd2029f23 714
mbed_official 324:406fd2029f23 715 /*! @brief Read current value of the DAC_C1_DMAEN field. */
mbed_official 324:406fd2029f23 716 #define BR_DAC_C1_DMAEN(x) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN))
mbed_official 324:406fd2029f23 717
mbed_official 324:406fd2029f23 718 /*! @brief Format value for bitfield DAC_C1_DMAEN. */
mbed_official 324:406fd2029f23 719 #define BF_DAC_C1_DMAEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
mbed_official 324:406fd2029f23 720
mbed_official 324:406fd2029f23 721 /*! @brief Set the DMAEN field to a new value. */
mbed_official 324:406fd2029f23 722 #define BW_DAC_C1_DMAEN(x, v) (BITBAND_ACCESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN) = (v))
mbed_official 324:406fd2029f23 723 /*@}*/
mbed_official 324:406fd2029f23 724
mbed_official 324:406fd2029f23 725 /*******************************************************************************
mbed_official 324:406fd2029f23 726 * HW_DAC_C2 - DAC Control Register 2
mbed_official 324:406fd2029f23 727 ******************************************************************************/
mbed_official 324:406fd2029f23 728
mbed_official 324:406fd2029f23 729 /*!
mbed_official 324:406fd2029f23 730 * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
mbed_official 324:406fd2029f23 731 *
mbed_official 324:406fd2029f23 732 * Reset value: 0x0FU
mbed_official 324:406fd2029f23 733 */
mbed_official 324:406fd2029f23 734 typedef union _hw_dac_c2
mbed_official 324:406fd2029f23 735 {
mbed_official 324:406fd2029f23 736 uint8_t U;
mbed_official 324:406fd2029f23 737 struct _hw_dac_c2_bitfields
mbed_official 324:406fd2029f23 738 {
mbed_official 324:406fd2029f23 739 uint8_t DACBFUP : 4; /*!< [3:0] DAC Buffer Upper Limit */
mbed_official 324:406fd2029f23 740 uint8_t DACBFRP : 4; /*!< [7:4] DAC Buffer Read Pointer */
mbed_official 324:406fd2029f23 741 } B;
mbed_official 324:406fd2029f23 742 } hw_dac_c2_t;
mbed_official 324:406fd2029f23 743
mbed_official 324:406fd2029f23 744 /*!
mbed_official 324:406fd2029f23 745 * @name Constants and macros for entire DAC_C2 register
mbed_official 324:406fd2029f23 746 */
mbed_official 324:406fd2029f23 747 /*@{*/
mbed_official 324:406fd2029f23 748 #define HW_DAC_C2_ADDR(x) ((x) + 0x23U)
mbed_official 324:406fd2029f23 749
mbed_official 324:406fd2029f23 750 #define HW_DAC_C2(x) (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
mbed_official 324:406fd2029f23 751 #define HW_DAC_C2_RD(x) (HW_DAC_C2(x).U)
mbed_official 324:406fd2029f23 752 #define HW_DAC_C2_WR(x, v) (HW_DAC_C2(x).U = (v))
mbed_official 324:406fd2029f23 753 #define HW_DAC_C2_SET(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) | (v)))
mbed_official 324:406fd2029f23 754 #define HW_DAC_C2_CLR(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 755 #define HW_DAC_C2_TOG(x, v) (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 756 /*@}*/
mbed_official 324:406fd2029f23 757
mbed_official 324:406fd2029f23 758 /*
mbed_official 324:406fd2029f23 759 * Constants & macros for individual DAC_C2 bitfields
mbed_official 324:406fd2029f23 760 */
mbed_official 324:406fd2029f23 761
mbed_official 324:406fd2029f23 762 /*!
mbed_official 324:406fd2029f23 763 * @name Register DAC_C2, field DACBFUP[3:0] (RW)
mbed_official 324:406fd2029f23 764 *
mbed_official 324:406fd2029f23 765 * In normal mode it selects the upper limit of the DAC buffer. The buffer read
mbed_official 324:406fd2029f23 766 * pointer cannot exceed it. In FIFO mode it is the FIFO write pointer. User
mbed_official 324:406fd2029f23 767 * cannot set Buffer Up limit in FIFO mode. In Normal mode its reset value is MAX.
mbed_official 324:406fd2029f23 768 * When IP is configured to FIFO mode, this register becomes Write_Pointer, and its
mbed_official 324:406fd2029f23 769 * value is initially set to equal READ_POINTER automatically, and the FIFO
mbed_official 324:406fd2029f23 770 * status is empty. It is writable and user can configure it to the same address to
mbed_official 324:406fd2029f23 771 * reset FIFO as empty.
mbed_official 324:406fd2029f23 772 */
mbed_official 324:406fd2029f23 773 /*@{*/
mbed_official 324:406fd2029f23 774 #define BP_DAC_C2_DACBFUP (0U) /*!< Bit position for DAC_C2_DACBFUP. */
mbed_official 324:406fd2029f23 775 #define BM_DAC_C2_DACBFUP (0x0FU) /*!< Bit mask for DAC_C2_DACBFUP. */
mbed_official 324:406fd2029f23 776 #define BS_DAC_C2_DACBFUP (4U) /*!< Bit field size in bits for DAC_C2_DACBFUP. */
mbed_official 324:406fd2029f23 777
mbed_official 324:406fd2029f23 778 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
mbed_official 324:406fd2029f23 779 #define BR_DAC_C2_DACBFUP(x) (HW_DAC_C2(x).B.DACBFUP)
mbed_official 324:406fd2029f23 780
mbed_official 324:406fd2029f23 781 /*! @brief Format value for bitfield DAC_C2_DACBFUP. */
mbed_official 324:406fd2029f23 782 #define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
mbed_official 324:406fd2029f23 783
mbed_official 324:406fd2029f23 784 /*! @brief Set the DACBFUP field to a new value. */
mbed_official 324:406fd2029f23 785 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
mbed_official 324:406fd2029f23 786 /*@}*/
mbed_official 324:406fd2029f23 787
mbed_official 324:406fd2029f23 788 /*!
mbed_official 324:406fd2029f23 789 * @name Register DAC_C2, field DACBFRP[7:4] (RW)
mbed_official 324:406fd2029f23 790 *
mbed_official 324:406fd2029f23 791 * In normal mode it keeps the current value of the buffer read pointer. FIFO
mbed_official 324:406fd2029f23 792 * mode, it is the FIFO read pointer. It is writable in FIFO mode. User can
mbed_official 324:406fd2029f23 793 * configure it to same address to reset FIFO as empty.
mbed_official 324:406fd2029f23 794 */
mbed_official 324:406fd2029f23 795 /*@{*/
mbed_official 324:406fd2029f23 796 #define BP_DAC_C2_DACBFRP (4U) /*!< Bit position for DAC_C2_DACBFRP. */
mbed_official 324:406fd2029f23 797 #define BM_DAC_C2_DACBFRP (0xF0U) /*!< Bit mask for DAC_C2_DACBFRP. */
mbed_official 324:406fd2029f23 798 #define BS_DAC_C2_DACBFRP (4U) /*!< Bit field size in bits for DAC_C2_DACBFRP. */
mbed_official 324:406fd2029f23 799
mbed_official 324:406fd2029f23 800 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
mbed_official 324:406fd2029f23 801 #define BR_DAC_C2_DACBFRP(x) (HW_DAC_C2(x).B.DACBFRP)
mbed_official 324:406fd2029f23 802
mbed_official 324:406fd2029f23 803 /*! @brief Format value for bitfield DAC_C2_DACBFRP. */
mbed_official 324:406fd2029f23 804 #define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
mbed_official 324:406fd2029f23 805
mbed_official 324:406fd2029f23 806 /*! @brief Set the DACBFRP field to a new value. */
mbed_official 324:406fd2029f23 807 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
mbed_official 324:406fd2029f23 808 /*@}*/
mbed_official 324:406fd2029f23 809
mbed_official 324:406fd2029f23 810 /*******************************************************************************
mbed_official 324:406fd2029f23 811 * hw_dac_t - module struct
mbed_official 324:406fd2029f23 812 ******************************************************************************/
mbed_official 324:406fd2029f23 813 /*!
mbed_official 324:406fd2029f23 814 * @brief All DAC module registers.
mbed_official 324:406fd2029f23 815 */
mbed_official 324:406fd2029f23 816 #pragma pack(1)
mbed_official 324:406fd2029f23 817 typedef struct _hw_dac
mbed_official 324:406fd2029f23 818 {
mbed_official 324:406fd2029f23 819 struct {
mbed_official 324:406fd2029f23 820 __IO hw_dac_datnl_t DATnL; /*!< [0x0] DAC Data Low Register */
mbed_official 324:406fd2029f23 821 __IO hw_dac_datnh_t DATnH; /*!< [0x1] DAC Data High Register */
mbed_official 324:406fd2029f23 822 } DAT[16];
mbed_official 324:406fd2029f23 823 __IO hw_dac_sr_t SR; /*!< [0x20] DAC Status Register */
mbed_official 324:406fd2029f23 824 __IO hw_dac_c0_t C0; /*!< [0x21] DAC Control Register */
mbed_official 324:406fd2029f23 825 __IO hw_dac_c1_t C1; /*!< [0x22] DAC Control Register 1 */
mbed_official 324:406fd2029f23 826 __IO hw_dac_c2_t C2; /*!< [0x23] DAC Control Register 2 */
mbed_official 324:406fd2029f23 827 } hw_dac_t;
mbed_official 324:406fd2029f23 828 #pragma pack()
mbed_official 324:406fd2029f23 829
mbed_official 324:406fd2029f23 830 /*! @brief Macro to access all DAC registers. */
mbed_official 324:406fd2029f23 831 /*! @param x DAC module instance base address. */
mbed_official 324:406fd2029f23 832 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 833 * use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
mbed_official 324:406fd2029f23 834 #define HW_DAC(x) (*(hw_dac_t *)(x))
mbed_official 324:406fd2029f23 835
mbed_official 324:406fd2029f23 836 #endif /* __HW_DAC_REGISTERS_H__ */
mbed_official 324:406fd2029f23 837 /* EOF */