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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K22F/device/MK22F51212/MK22F51212_adc.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 7 **
mbed_official 324:406fd2029f23 8 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 9 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 10 ** Build: b140604
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Abstract:
mbed_official 324:406fd2029f23 13 ** Extension to the CMSIS register access layer header.
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 16 ** All rights reserved.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 19 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 22 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 25 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 26 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 29 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 30 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 33 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 34 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 35 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 36 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 37 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 38 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 39 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 41 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 42 **
mbed_official 324:406fd2029f23 43 ** http: www.freescale.com
mbed_official 324:406fd2029f23 44 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** Revisions:
mbed_official 324:406fd2029f23 47 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 48 ** Initial version.
mbed_official 324:406fd2029f23 49 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 50 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 51 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 52 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 53 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 54 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 55 ** System initialization updated.
mbed_official 324:406fd2029f23 56 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 57 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 58 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 59 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 60 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 61 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 62 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 63 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 64 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 65 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 66 ** Update of system and startup files.
mbed_official 324:406fd2029f23 67 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 68 **
mbed_official 324:406fd2029f23 69 ** ###################################################################
mbed_official 324:406fd2029f23 70 */
mbed_official 324:406fd2029f23 71
mbed_official 324:406fd2029f23 72 /*
mbed_official 324:406fd2029f23 73 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
mbed_official 324:406fd2029f23 74 *
mbed_official 324:406fd2029f23 75 * This file was generated automatically and any changes may be lost.
mbed_official 324:406fd2029f23 76 */
mbed_official 324:406fd2029f23 77 #ifndef __HW_ADC_REGISTERS_H__
mbed_official 324:406fd2029f23 78 #define __HW_ADC_REGISTERS_H__
mbed_official 324:406fd2029f23 79
mbed_official 324:406fd2029f23 80 #include "MK22F51212.h"
mbed_official 324:406fd2029f23 81 #include "fsl_bitaccess.h"
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /*
mbed_official 324:406fd2029f23 84 * MK22F51212 ADC
mbed_official 324:406fd2029f23 85 *
mbed_official 324:406fd2029f23 86 * Analog-to-Digital Converter
mbed_official 324:406fd2029f23 87 *
mbed_official 324:406fd2029f23 88 * Registers defined in this header file:
mbed_official 324:406fd2029f23 89 * - HW_ADC_SC1n - ADC Status and Control Registers 1
mbed_official 324:406fd2029f23 90 * - HW_ADC_CFG1 - ADC Configuration Register 1
mbed_official 324:406fd2029f23 91 * - HW_ADC_CFG2 - ADC Configuration Register 2
mbed_official 324:406fd2029f23 92 * - HW_ADC_Rn - ADC Data Result Register
mbed_official 324:406fd2029f23 93 * - HW_ADC_CV1 - Compare Value Registers
mbed_official 324:406fd2029f23 94 * - HW_ADC_CV2 - Compare Value Registers
mbed_official 324:406fd2029f23 95 * - HW_ADC_SC2 - Status and Control Register 2
mbed_official 324:406fd2029f23 96 * - HW_ADC_SC3 - Status and Control Register 3
mbed_official 324:406fd2029f23 97 * - HW_ADC_OFS - ADC Offset Correction Register
mbed_official 324:406fd2029f23 98 * - HW_ADC_PG - ADC Plus-Side Gain Register
mbed_official 324:406fd2029f23 99 * - HW_ADC_MG - ADC Minus-Side Gain Register
mbed_official 324:406fd2029f23 100 * - HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 101 * - HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 102 * - HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 103 * - HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 104 * - HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 105 * - HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 106 * - HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 107 * - HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 108 * - HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 109 * - HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 110 * - HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 111 * - HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 112 * - HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 113 * - HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 114 *
mbed_official 324:406fd2029f23 115 * - hw_adc_t - Struct containing all module registers.
mbed_official 324:406fd2029f23 116 */
mbed_official 324:406fd2029f23 117
mbed_official 324:406fd2029f23 118 #define HW_ADC_INSTANCE_COUNT (2U) /*!< Number of instances of the ADC module. */
mbed_official 324:406fd2029f23 119 #define HW_ADC0 (0U) /*!< Instance number for ADC0. */
mbed_official 324:406fd2029f23 120 #define HW_ADC1 (1U) /*!< Instance number for ADC1. */
mbed_official 324:406fd2029f23 121
mbed_official 324:406fd2029f23 122 /*******************************************************************************
mbed_official 324:406fd2029f23 123 * HW_ADC_SC1n - ADC Status and Control Registers 1
mbed_official 324:406fd2029f23 124 ******************************************************************************/
mbed_official 324:406fd2029f23 125
mbed_official 324:406fd2029f23 126 /*!
mbed_official 324:406fd2029f23 127 * @brief HW_ADC_SC1n - ADC Status and Control Registers 1 (RW)
mbed_official 324:406fd2029f23 128 *
mbed_official 324:406fd2029f23 129 * Reset value: 0x0000001FU
mbed_official 324:406fd2029f23 130 *
mbed_official 324:406fd2029f23 131 * SC1A is used for both software and hardware trigger modes of operation. To
mbed_official 324:406fd2029f23 132 * allow sequential conversions of the ADC to be triggered by internal peripherals,
mbed_official 324:406fd2029f23 133 * the ADC can have more than one status and control register: one for each
mbed_official 324:406fd2029f23 134 * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
mbed_official 324:406fd2029f23 135 * for use only in hardware trigger mode. See the chip configuration information
mbed_official 324:406fd2029f23 136 * about the number of SC1n registers specific to this device. The SC1n registers
mbed_official 324:406fd2029f23 137 * have identical fields, and are used in a "ping-pong" approach to control ADC
mbed_official 324:406fd2029f23 138 * operation. At any one point in time, only one of the SC1n registers is actively
mbed_official 324:406fd2029f23 139 * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
mbed_official 324:406fd2029f23 140 * a conversion is allowed, and vice-versa for any of the SC1n registers specific
mbed_official 324:406fd2029f23 141 * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
mbed_official 324:406fd2029f23 142 * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
mbed_official 324:406fd2029f23 143 * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
mbed_official 324:406fd2029f23 144 * value other than all 1s. Writing any of the SC1n registers while that specific
mbed_official 324:406fd2029f23 145 * SC1n register is actively controlling a conversion aborts the current conversion.
mbed_official 324:406fd2029f23 146 * None of the SC1B-SC1n registers are used for software trigger operation and
mbed_official 324:406fd2029f23 147 * therefore writes to the SC1B-SC1n registers do not initiate a new conversion.
mbed_official 324:406fd2029f23 148 */
mbed_official 324:406fd2029f23 149 typedef union _hw_adc_sc1n
mbed_official 324:406fd2029f23 150 {
mbed_official 324:406fd2029f23 151 uint32_t U;
mbed_official 324:406fd2029f23 152 struct _hw_adc_sc1n_bitfields
mbed_official 324:406fd2029f23 153 {
mbed_official 324:406fd2029f23 154 uint32_t ADCH : 5; /*!< [4:0] Input channel select */
mbed_official 324:406fd2029f23 155 uint32_t DIFF : 1; /*!< [5] Differential Mode Enable */
mbed_official 324:406fd2029f23 156 uint32_t AIEN : 1; /*!< [6] Interrupt Enable */
mbed_official 324:406fd2029f23 157 uint32_t COCO : 1; /*!< [7] Conversion Complete Flag */
mbed_official 324:406fd2029f23 158 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 159 } B;
mbed_official 324:406fd2029f23 160 } hw_adc_sc1n_t;
mbed_official 324:406fd2029f23 161
mbed_official 324:406fd2029f23 162 /*!
mbed_official 324:406fd2029f23 163 * @name Constants and macros for entire ADC_SC1n register
mbed_official 324:406fd2029f23 164 */
mbed_official 324:406fd2029f23 165 /*@{*/
mbed_official 324:406fd2029f23 166 #define HW_ADC_SC1n_COUNT (2U)
mbed_official 324:406fd2029f23 167
mbed_official 324:406fd2029f23 168 #define HW_ADC_SC1n_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
mbed_official 324:406fd2029f23 169
mbed_official 324:406fd2029f23 170 #define HW_ADC_SC1n(x, n) (*(__IO hw_adc_sc1n_t *) HW_ADC_SC1n_ADDR(x, n))
mbed_official 324:406fd2029f23 171 #define HW_ADC_SC1n_RD(x, n) (HW_ADC_SC1n(x, n).U)
mbed_official 324:406fd2029f23 172 #define HW_ADC_SC1n_WR(x, n, v) (HW_ADC_SC1n(x, n).U = (v))
mbed_official 324:406fd2029f23 173 #define HW_ADC_SC1n_SET(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) | (v)))
mbed_official 324:406fd2029f23 174 #define HW_ADC_SC1n_CLR(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) & ~(v)))
mbed_official 324:406fd2029f23 175 #define HW_ADC_SC1n_TOG(x, n, v) (HW_ADC_SC1n_WR(x, n, HW_ADC_SC1n_RD(x, n) ^ (v)))
mbed_official 324:406fd2029f23 176 /*@}*/
mbed_official 324:406fd2029f23 177
mbed_official 324:406fd2029f23 178 /*
mbed_official 324:406fd2029f23 179 * Constants & macros for individual ADC_SC1n bitfields
mbed_official 324:406fd2029f23 180 */
mbed_official 324:406fd2029f23 181
mbed_official 324:406fd2029f23 182 /*!
mbed_official 324:406fd2029f23 183 * @name Register ADC_SC1n, field ADCH[4:0] (RW)
mbed_official 324:406fd2029f23 184 *
mbed_official 324:406fd2029f23 185 * Selects one of the input channels. The input channel decode depends on the
mbed_official 324:406fd2029f23 186 * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
mbed_official 324:406fd2029f23 187 * DADMx. Some of the input channel options in the bitfield-setting descriptions might
mbed_official 324:406fd2029f23 188 * not be available for your device. For the actual ADC channel assignments for
mbed_official 324:406fd2029f23 189 * your device, see the Chip Configuration details. The successive approximation
mbed_official 324:406fd2029f23 190 * converter subsystem is turned off when the channel select bits are all set,
mbed_official 324:406fd2029f23 191 * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
mbed_official 324:406fd2029f23 192 * isolation of the input channel from all sources. Terminating continuous
mbed_official 324:406fd2029f23 193 * conversions this way prevents an additional single conversion from being performed. It
mbed_official 324:406fd2029f23 194 * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
mbed_official 324:406fd2029f23 195 * when continuous conversions are not enabled because the module automatically
mbed_official 324:406fd2029f23 196 * enters a low-power state when a conversion completes.
mbed_official 324:406fd2029f23 197 *
mbed_official 324:406fd2029f23 198 * Values:
mbed_official 324:406fd2029f23 199 * - 00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
mbed_official 324:406fd2029f23 200 * selected as input.
mbed_official 324:406fd2029f23 201 * - 00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
mbed_official 324:406fd2029f23 202 * selected as input.
mbed_official 324:406fd2029f23 203 * - 00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
mbed_official 324:406fd2029f23 204 * selected as input.
mbed_official 324:406fd2029f23 205 * - 00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
mbed_official 324:406fd2029f23 206 * selected as input.
mbed_official 324:406fd2029f23 207 * - 00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 208 * - 00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 209 * - 00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 210 * - 00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 211 * - 01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 212 * - 01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 213 * - 01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 214 * - 01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 215 * - 01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 216 * - 01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 217 * - 01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 218 * - 01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 219 * - 10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 220 * - 10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 221 * - 10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 222 * - 10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 223 * - 10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 224 * - 10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 225 * - 10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 226 * - 10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
mbed_official 324:406fd2029f23 227 * - 11000 - Reserved.
mbed_official 324:406fd2029f23 228 * - 11001 - Reserved.
mbed_official 324:406fd2029f23 229 * - 11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input; when
mbed_official 324:406fd2029f23 230 * DIFF=1, Temp Sensor (differential) is selected as input.
mbed_official 324:406fd2029f23 231 * - 11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
mbed_official 324:406fd2029f23 232 * DIFF=1, Bandgap (differential) is selected as input.
mbed_official 324:406fd2029f23 233 * - 11100 - Reserved.
mbed_official 324:406fd2029f23 234 * - 11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
mbed_official 324:406fd2029f23 235 * (differential) is selected as input. Voltage reference selected is determined
mbed_official 324:406fd2029f23 236 * by SC2[REFSEL].
mbed_official 324:406fd2029f23 237 * - 11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
mbed_official 324:406fd2029f23 238 * reserved. Voltage reference selected is determined by SC2[REFSEL].
mbed_official 324:406fd2029f23 239 * - 11111 - Module is disabled.
mbed_official 324:406fd2029f23 240 */
mbed_official 324:406fd2029f23 241 /*@{*/
mbed_official 324:406fd2029f23 242 #define BP_ADC_SC1n_ADCH (0U) /*!< Bit position for ADC_SC1n_ADCH. */
mbed_official 324:406fd2029f23 243 #define BM_ADC_SC1n_ADCH (0x0000001FU) /*!< Bit mask for ADC_SC1n_ADCH. */
mbed_official 324:406fd2029f23 244 #define BS_ADC_SC1n_ADCH (5U) /*!< Bit field size in bits for ADC_SC1n_ADCH. */
mbed_official 324:406fd2029f23 245
mbed_official 324:406fd2029f23 246 /*! @brief Read current value of the ADC_SC1n_ADCH field. */
mbed_official 324:406fd2029f23 247 #define BR_ADC_SC1n_ADCH(x, n) (HW_ADC_SC1n(x, n).B.ADCH)
mbed_official 324:406fd2029f23 248
mbed_official 324:406fd2029f23 249 /*! @brief Format value for bitfield ADC_SC1n_ADCH. */
mbed_official 324:406fd2029f23 250 #define BF_ADC_SC1n_ADCH(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_ADCH) & BM_ADC_SC1n_ADCH)
mbed_official 324:406fd2029f23 251
mbed_official 324:406fd2029f23 252 /*! @brief Set the ADCH field to a new value. */
mbed_official 324:406fd2029f23 253 #define BW_ADC_SC1n_ADCH(x, n, v) (HW_ADC_SC1n_WR(x, n, (HW_ADC_SC1n_RD(x, n) & ~BM_ADC_SC1n_ADCH) | BF_ADC_SC1n_ADCH(v)))
mbed_official 324:406fd2029f23 254 /*@}*/
mbed_official 324:406fd2029f23 255
mbed_official 324:406fd2029f23 256 /*!
mbed_official 324:406fd2029f23 257 * @name Register ADC_SC1n, field DIFF[5] (RW)
mbed_official 324:406fd2029f23 258 *
mbed_official 324:406fd2029f23 259 * Configures the ADC to operate in differential mode. When enabled, this mode
mbed_official 324:406fd2029f23 260 * automatically selects from the differential channels, and changes the
mbed_official 324:406fd2029f23 261 * conversion algorithm and the number of cycles to complete a conversion.
mbed_official 324:406fd2029f23 262 *
mbed_official 324:406fd2029f23 263 * Values:
mbed_official 324:406fd2029f23 264 * - 0 - Single-ended conversions and input channels are selected.
mbed_official 324:406fd2029f23 265 * - 1 - Differential conversions and input channels are selected.
mbed_official 324:406fd2029f23 266 */
mbed_official 324:406fd2029f23 267 /*@{*/
mbed_official 324:406fd2029f23 268 #define BP_ADC_SC1n_DIFF (5U) /*!< Bit position for ADC_SC1n_DIFF. */
mbed_official 324:406fd2029f23 269 #define BM_ADC_SC1n_DIFF (0x00000020U) /*!< Bit mask for ADC_SC1n_DIFF. */
mbed_official 324:406fd2029f23 270 #define BS_ADC_SC1n_DIFF (1U) /*!< Bit field size in bits for ADC_SC1n_DIFF. */
mbed_official 324:406fd2029f23 271
mbed_official 324:406fd2029f23 272 /*! @brief Read current value of the ADC_SC1n_DIFF field. */
mbed_official 324:406fd2029f23 273 #define BR_ADC_SC1n_DIFF(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF))
mbed_official 324:406fd2029f23 274
mbed_official 324:406fd2029f23 275 /*! @brief Format value for bitfield ADC_SC1n_DIFF. */
mbed_official 324:406fd2029f23 276 #define BF_ADC_SC1n_DIFF(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_DIFF) & BM_ADC_SC1n_DIFF)
mbed_official 324:406fd2029f23 277
mbed_official 324:406fd2029f23 278 /*! @brief Set the DIFF field to a new value. */
mbed_official 324:406fd2029f23 279 #define BW_ADC_SC1n_DIFF(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_DIFF) = (v))
mbed_official 324:406fd2029f23 280 /*@}*/
mbed_official 324:406fd2029f23 281
mbed_official 324:406fd2029f23 282 /*!
mbed_official 324:406fd2029f23 283 * @name Register ADC_SC1n, field AIEN[6] (RW)
mbed_official 324:406fd2029f23 284 *
mbed_official 324:406fd2029f23 285 * Enables conversion complete interrupts. When COCO becomes set while the
mbed_official 324:406fd2029f23 286 * respective AIEN is high, an interrupt is asserted.
mbed_official 324:406fd2029f23 287 *
mbed_official 324:406fd2029f23 288 * Values:
mbed_official 324:406fd2029f23 289 * - 0 - Conversion complete interrupt is disabled.
mbed_official 324:406fd2029f23 290 * - 1 - Conversion complete interrupt is enabled.
mbed_official 324:406fd2029f23 291 */
mbed_official 324:406fd2029f23 292 /*@{*/
mbed_official 324:406fd2029f23 293 #define BP_ADC_SC1n_AIEN (6U) /*!< Bit position for ADC_SC1n_AIEN. */
mbed_official 324:406fd2029f23 294 #define BM_ADC_SC1n_AIEN (0x00000040U) /*!< Bit mask for ADC_SC1n_AIEN. */
mbed_official 324:406fd2029f23 295 #define BS_ADC_SC1n_AIEN (1U) /*!< Bit field size in bits for ADC_SC1n_AIEN. */
mbed_official 324:406fd2029f23 296
mbed_official 324:406fd2029f23 297 /*! @brief Read current value of the ADC_SC1n_AIEN field. */
mbed_official 324:406fd2029f23 298 #define BR_ADC_SC1n_AIEN(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN))
mbed_official 324:406fd2029f23 299
mbed_official 324:406fd2029f23 300 /*! @brief Format value for bitfield ADC_SC1n_AIEN. */
mbed_official 324:406fd2029f23 301 #define BF_ADC_SC1n_AIEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC1n_AIEN) & BM_ADC_SC1n_AIEN)
mbed_official 324:406fd2029f23 302
mbed_official 324:406fd2029f23 303 /*! @brief Set the AIEN field to a new value. */
mbed_official 324:406fd2029f23 304 #define BW_ADC_SC1n_AIEN(x, n, v) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_AIEN) = (v))
mbed_official 324:406fd2029f23 305 /*@}*/
mbed_official 324:406fd2029f23 306
mbed_official 324:406fd2029f23 307 /*!
mbed_official 324:406fd2029f23 308 * @name Register ADC_SC1n, field COCO[7] (RO)
mbed_official 324:406fd2029f23 309 *
mbed_official 324:406fd2029f23 310 * This is a read-only field that is set each time a conversion is completed
mbed_official 324:406fd2029f23 311 * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
mbed_official 324:406fd2029f23 312 * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
mbed_official 324:406fd2029f23 313 * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
mbed_official 324:406fd2029f23 314 * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
mbed_official 324:406fd2029f23 315 * COCO is set upon completion of the selected number of conversions (determined
mbed_official 324:406fd2029f23 316 * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
mbed_official 324:406fd2029f23 317 * COCO is cleared when the respective SC1n register is written or when the
mbed_official 324:406fd2029f23 318 * respective Rn register is read.
mbed_official 324:406fd2029f23 319 *
mbed_official 324:406fd2029f23 320 * Values:
mbed_official 324:406fd2029f23 321 * - 0 - Conversion is not completed.
mbed_official 324:406fd2029f23 322 * - 1 - Conversion is completed.
mbed_official 324:406fd2029f23 323 */
mbed_official 324:406fd2029f23 324 /*@{*/
mbed_official 324:406fd2029f23 325 #define BP_ADC_SC1n_COCO (7U) /*!< Bit position for ADC_SC1n_COCO. */
mbed_official 324:406fd2029f23 326 #define BM_ADC_SC1n_COCO (0x00000080U) /*!< Bit mask for ADC_SC1n_COCO. */
mbed_official 324:406fd2029f23 327 #define BS_ADC_SC1n_COCO (1U) /*!< Bit field size in bits for ADC_SC1n_COCO. */
mbed_official 324:406fd2029f23 328
mbed_official 324:406fd2029f23 329 /*! @brief Read current value of the ADC_SC1n_COCO field. */
mbed_official 324:406fd2029f23 330 #define BR_ADC_SC1n_COCO(x, n) (BITBAND_ACCESS32(HW_ADC_SC1n_ADDR(x, n), BP_ADC_SC1n_COCO))
mbed_official 324:406fd2029f23 331 /*@}*/
mbed_official 324:406fd2029f23 332
mbed_official 324:406fd2029f23 333 /*******************************************************************************
mbed_official 324:406fd2029f23 334 * HW_ADC_CFG1 - ADC Configuration Register 1
mbed_official 324:406fd2029f23 335 ******************************************************************************/
mbed_official 324:406fd2029f23 336
mbed_official 324:406fd2029f23 337 /*!
mbed_official 324:406fd2029f23 338 * @brief HW_ADC_CFG1 - ADC Configuration Register 1 (RW)
mbed_official 324:406fd2029f23 339 *
mbed_official 324:406fd2029f23 340 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 341 *
mbed_official 324:406fd2029f23 342 * The configuration Register 1 (CFG1) selects the mode of operation, clock
mbed_official 324:406fd2029f23 343 * source, clock divide, and configuration for low power or long sample time.
mbed_official 324:406fd2029f23 344 */
mbed_official 324:406fd2029f23 345 typedef union _hw_adc_cfg1
mbed_official 324:406fd2029f23 346 {
mbed_official 324:406fd2029f23 347 uint32_t U;
mbed_official 324:406fd2029f23 348 struct _hw_adc_cfg1_bitfields
mbed_official 324:406fd2029f23 349 {
mbed_official 324:406fd2029f23 350 uint32_t ADICLK : 2; /*!< [1:0] Input Clock Select */
mbed_official 324:406fd2029f23 351 uint32_t MODE : 2; /*!< [3:2] Conversion mode selection */
mbed_official 324:406fd2029f23 352 uint32_t ADLSMP : 1; /*!< [4] Sample Time Configuration */
mbed_official 324:406fd2029f23 353 uint32_t ADIV : 2; /*!< [6:5] Clock Divide Select */
mbed_official 324:406fd2029f23 354 uint32_t ADLPC : 1; /*!< [7] Low-Power Configuration */
mbed_official 324:406fd2029f23 355 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 356 } B;
mbed_official 324:406fd2029f23 357 } hw_adc_cfg1_t;
mbed_official 324:406fd2029f23 358
mbed_official 324:406fd2029f23 359 /*!
mbed_official 324:406fd2029f23 360 * @name Constants and macros for entire ADC_CFG1 register
mbed_official 324:406fd2029f23 361 */
mbed_official 324:406fd2029f23 362 /*@{*/
mbed_official 324:406fd2029f23 363 #define HW_ADC_CFG1_ADDR(x) ((x) + 0x8U)
mbed_official 324:406fd2029f23 364
mbed_official 324:406fd2029f23 365 #define HW_ADC_CFG1(x) (*(__IO hw_adc_cfg1_t *) HW_ADC_CFG1_ADDR(x))
mbed_official 324:406fd2029f23 366 #define HW_ADC_CFG1_RD(x) (HW_ADC_CFG1(x).U)
mbed_official 324:406fd2029f23 367 #define HW_ADC_CFG1_WR(x, v) (HW_ADC_CFG1(x).U = (v))
mbed_official 324:406fd2029f23 368 #define HW_ADC_CFG1_SET(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) | (v)))
mbed_official 324:406fd2029f23 369 #define HW_ADC_CFG1_CLR(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 370 #define HW_ADC_CFG1_TOG(x, v) (HW_ADC_CFG1_WR(x, HW_ADC_CFG1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 371 /*@}*/
mbed_official 324:406fd2029f23 372
mbed_official 324:406fd2029f23 373 /*
mbed_official 324:406fd2029f23 374 * Constants & macros for individual ADC_CFG1 bitfields
mbed_official 324:406fd2029f23 375 */
mbed_official 324:406fd2029f23 376
mbed_official 324:406fd2029f23 377 /*!
mbed_official 324:406fd2029f23 378 * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
mbed_official 324:406fd2029f23 379 *
mbed_official 324:406fd2029f23 380 * Selects the input clock source to generate the internal clock, ADCK. Note
mbed_official 324:406fd2029f23 381 * that when the ADACK clock source is selected, it is not required to be active
mbed_official 324:406fd2029f23 382 * prior to conversion start. When it is selected and it is not active prior to a
mbed_official 324:406fd2029f23 383 * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
mbed_official 324:406fd2029f23 384 * the start of a conversion and deactivated when conversions are terminated. In
mbed_official 324:406fd2029f23 385 * this case, there is an associated clock startup delay each time the clock
mbed_official 324:406fd2029f23 386 * source is re-activated.
mbed_official 324:406fd2029f23 387 *
mbed_official 324:406fd2029f23 388 * Values:
mbed_official 324:406fd2029f23 389 * - 00 - Bus clock
mbed_official 324:406fd2029f23 390 * - 01 - Alternate clock 2 (ALTCLK2)
mbed_official 324:406fd2029f23 391 * - 10 - Alternate clock (ALTCLK)
mbed_official 324:406fd2029f23 392 * - 11 - Asynchronous clock (ADACK)
mbed_official 324:406fd2029f23 393 */
mbed_official 324:406fd2029f23 394 /*@{*/
mbed_official 324:406fd2029f23 395 #define BP_ADC_CFG1_ADICLK (0U) /*!< Bit position for ADC_CFG1_ADICLK. */
mbed_official 324:406fd2029f23 396 #define BM_ADC_CFG1_ADICLK (0x00000003U) /*!< Bit mask for ADC_CFG1_ADICLK. */
mbed_official 324:406fd2029f23 397 #define BS_ADC_CFG1_ADICLK (2U) /*!< Bit field size in bits for ADC_CFG1_ADICLK. */
mbed_official 324:406fd2029f23 398
mbed_official 324:406fd2029f23 399 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
mbed_official 324:406fd2029f23 400 #define BR_ADC_CFG1_ADICLK(x) (HW_ADC_CFG1(x).B.ADICLK)
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /*! @brief Format value for bitfield ADC_CFG1_ADICLK. */
mbed_official 324:406fd2029f23 403 #define BF_ADC_CFG1_ADICLK(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADICLK) & BM_ADC_CFG1_ADICLK)
mbed_official 324:406fd2029f23 404
mbed_official 324:406fd2029f23 405 /*! @brief Set the ADICLK field to a new value. */
mbed_official 324:406fd2029f23 406 #define BW_ADC_CFG1_ADICLK(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADICLK) | BF_ADC_CFG1_ADICLK(v)))
mbed_official 324:406fd2029f23 407 /*@}*/
mbed_official 324:406fd2029f23 408
mbed_official 324:406fd2029f23 409 /*!
mbed_official 324:406fd2029f23 410 * @name Register ADC_CFG1, field MODE[3:2] (RW)
mbed_official 324:406fd2029f23 411 *
mbed_official 324:406fd2029f23 412 * Selects the ADC resolution mode.
mbed_official 324:406fd2029f23 413 *
mbed_official 324:406fd2029f23 414 * Values:
mbed_official 324:406fd2029f23 415 * - 00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
mbed_official 324:406fd2029f23 416 * differential 9-bit conversion with 2's complement output.
mbed_official 324:406fd2029f23 417 * - 01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is
mbed_official 324:406fd2029f23 418 * differential 13-bit conversion with 2's complement output.
mbed_official 324:406fd2029f23 419 * - 10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is
mbed_official 324:406fd2029f23 420 * differential 11-bit conversion with 2's complement output
mbed_official 324:406fd2029f23 421 * - 11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is
mbed_official 324:406fd2029f23 422 * differential 16-bit conversion with 2's complement output
mbed_official 324:406fd2029f23 423 */
mbed_official 324:406fd2029f23 424 /*@{*/
mbed_official 324:406fd2029f23 425 #define BP_ADC_CFG1_MODE (2U) /*!< Bit position for ADC_CFG1_MODE. */
mbed_official 324:406fd2029f23 426 #define BM_ADC_CFG1_MODE (0x0000000CU) /*!< Bit mask for ADC_CFG1_MODE. */
mbed_official 324:406fd2029f23 427 #define BS_ADC_CFG1_MODE (2U) /*!< Bit field size in bits for ADC_CFG1_MODE. */
mbed_official 324:406fd2029f23 428
mbed_official 324:406fd2029f23 429 /*! @brief Read current value of the ADC_CFG1_MODE field. */
mbed_official 324:406fd2029f23 430 #define BR_ADC_CFG1_MODE(x) (HW_ADC_CFG1(x).B.MODE)
mbed_official 324:406fd2029f23 431
mbed_official 324:406fd2029f23 432 /*! @brief Format value for bitfield ADC_CFG1_MODE. */
mbed_official 324:406fd2029f23 433 #define BF_ADC_CFG1_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_MODE) & BM_ADC_CFG1_MODE)
mbed_official 324:406fd2029f23 434
mbed_official 324:406fd2029f23 435 /*! @brief Set the MODE field to a new value. */
mbed_official 324:406fd2029f23 436 #define BW_ADC_CFG1_MODE(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_MODE) | BF_ADC_CFG1_MODE(v)))
mbed_official 324:406fd2029f23 437 /*@}*/
mbed_official 324:406fd2029f23 438
mbed_official 324:406fd2029f23 439 /*!
mbed_official 324:406fd2029f23 440 * @name Register ADC_CFG1, field ADLSMP[4] (RW)
mbed_official 324:406fd2029f23 441 *
mbed_official 324:406fd2029f23 442 * Selects between different sample times based on the conversion mode selected.
mbed_official 324:406fd2029f23 443 * This field adjusts the sample period to allow higher impedance inputs to be
mbed_official 324:406fd2029f23 444 * accurately sampled or to maximize conversion speed for lower impedance inputs.
mbed_official 324:406fd2029f23 445 * Longer sample times can also be used to lower overall power consumption if
mbed_official 324:406fd2029f23 446 * continuous conversions are enabled and high conversion rates are not required.
mbed_official 324:406fd2029f23 447 * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
mbed_official 324:406fd2029f23 448 * extent of the long sample time.
mbed_official 324:406fd2029f23 449 *
mbed_official 324:406fd2029f23 450 * Values:
mbed_official 324:406fd2029f23 451 * - 0 - Short sample time.
mbed_official 324:406fd2029f23 452 * - 1 - Long sample time.
mbed_official 324:406fd2029f23 453 */
mbed_official 324:406fd2029f23 454 /*@{*/
mbed_official 324:406fd2029f23 455 #define BP_ADC_CFG1_ADLSMP (4U) /*!< Bit position for ADC_CFG1_ADLSMP. */
mbed_official 324:406fd2029f23 456 #define BM_ADC_CFG1_ADLSMP (0x00000010U) /*!< Bit mask for ADC_CFG1_ADLSMP. */
mbed_official 324:406fd2029f23 457 #define BS_ADC_CFG1_ADLSMP (1U) /*!< Bit field size in bits for ADC_CFG1_ADLSMP. */
mbed_official 324:406fd2029f23 458
mbed_official 324:406fd2029f23 459 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
mbed_official 324:406fd2029f23 460 #define BR_ADC_CFG1_ADLSMP(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP))
mbed_official 324:406fd2029f23 461
mbed_official 324:406fd2029f23 462 /*! @brief Format value for bitfield ADC_CFG1_ADLSMP. */
mbed_official 324:406fd2029f23 463 #define BF_ADC_CFG1_ADLSMP(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLSMP) & BM_ADC_CFG1_ADLSMP)
mbed_official 324:406fd2029f23 464
mbed_official 324:406fd2029f23 465 /*! @brief Set the ADLSMP field to a new value. */
mbed_official 324:406fd2029f23 466 #define BW_ADC_CFG1_ADLSMP(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLSMP) = (v))
mbed_official 324:406fd2029f23 467 /*@}*/
mbed_official 324:406fd2029f23 468
mbed_official 324:406fd2029f23 469 /*!
mbed_official 324:406fd2029f23 470 * @name Register ADC_CFG1, field ADIV[6:5] (RW)
mbed_official 324:406fd2029f23 471 *
mbed_official 324:406fd2029f23 472 * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
mbed_official 324:406fd2029f23 473 *
mbed_official 324:406fd2029f23 474 * Values:
mbed_official 324:406fd2029f23 475 * - 00 - The divide ratio is 1 and the clock rate is input clock.
mbed_official 324:406fd2029f23 476 * - 01 - The divide ratio is 2 and the clock rate is (input clock)/2.
mbed_official 324:406fd2029f23 477 * - 10 - The divide ratio is 4 and the clock rate is (input clock)/4.
mbed_official 324:406fd2029f23 478 * - 11 - The divide ratio is 8 and the clock rate is (input clock)/8.
mbed_official 324:406fd2029f23 479 */
mbed_official 324:406fd2029f23 480 /*@{*/
mbed_official 324:406fd2029f23 481 #define BP_ADC_CFG1_ADIV (5U) /*!< Bit position for ADC_CFG1_ADIV. */
mbed_official 324:406fd2029f23 482 #define BM_ADC_CFG1_ADIV (0x00000060U) /*!< Bit mask for ADC_CFG1_ADIV. */
mbed_official 324:406fd2029f23 483 #define BS_ADC_CFG1_ADIV (2U) /*!< Bit field size in bits for ADC_CFG1_ADIV. */
mbed_official 324:406fd2029f23 484
mbed_official 324:406fd2029f23 485 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
mbed_official 324:406fd2029f23 486 #define BR_ADC_CFG1_ADIV(x) (HW_ADC_CFG1(x).B.ADIV)
mbed_official 324:406fd2029f23 487
mbed_official 324:406fd2029f23 488 /*! @brief Format value for bitfield ADC_CFG1_ADIV. */
mbed_official 324:406fd2029f23 489 #define BF_ADC_CFG1_ADIV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADIV) & BM_ADC_CFG1_ADIV)
mbed_official 324:406fd2029f23 490
mbed_official 324:406fd2029f23 491 /*! @brief Set the ADIV field to a new value. */
mbed_official 324:406fd2029f23 492 #define BW_ADC_CFG1_ADIV(x, v) (HW_ADC_CFG1_WR(x, (HW_ADC_CFG1_RD(x) & ~BM_ADC_CFG1_ADIV) | BF_ADC_CFG1_ADIV(v)))
mbed_official 324:406fd2029f23 493 /*@}*/
mbed_official 324:406fd2029f23 494
mbed_official 324:406fd2029f23 495 /*!
mbed_official 324:406fd2029f23 496 * @name Register ADC_CFG1, field ADLPC[7] (RW)
mbed_official 324:406fd2029f23 497 *
mbed_official 324:406fd2029f23 498 * Controls the power configuration of the successive approximation converter.
mbed_official 324:406fd2029f23 499 * This optimizes power consumption when higher sample rates are not required.
mbed_official 324:406fd2029f23 500 *
mbed_official 324:406fd2029f23 501 * Values:
mbed_official 324:406fd2029f23 502 * - 0 - Normal power configuration.
mbed_official 324:406fd2029f23 503 * - 1 - Low-power configuration. The power is reduced at the expense of maximum
mbed_official 324:406fd2029f23 504 * clock speed.
mbed_official 324:406fd2029f23 505 */
mbed_official 324:406fd2029f23 506 /*@{*/
mbed_official 324:406fd2029f23 507 #define BP_ADC_CFG1_ADLPC (7U) /*!< Bit position for ADC_CFG1_ADLPC. */
mbed_official 324:406fd2029f23 508 #define BM_ADC_CFG1_ADLPC (0x00000080U) /*!< Bit mask for ADC_CFG1_ADLPC. */
mbed_official 324:406fd2029f23 509 #define BS_ADC_CFG1_ADLPC (1U) /*!< Bit field size in bits for ADC_CFG1_ADLPC. */
mbed_official 324:406fd2029f23 510
mbed_official 324:406fd2029f23 511 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
mbed_official 324:406fd2029f23 512 #define BR_ADC_CFG1_ADLPC(x) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC))
mbed_official 324:406fd2029f23 513
mbed_official 324:406fd2029f23 514 /*! @brief Format value for bitfield ADC_CFG1_ADLPC. */
mbed_official 324:406fd2029f23 515 #define BF_ADC_CFG1_ADLPC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG1_ADLPC) & BM_ADC_CFG1_ADLPC)
mbed_official 324:406fd2029f23 516
mbed_official 324:406fd2029f23 517 /*! @brief Set the ADLPC field to a new value. */
mbed_official 324:406fd2029f23 518 #define BW_ADC_CFG1_ADLPC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG1_ADDR(x), BP_ADC_CFG1_ADLPC) = (v))
mbed_official 324:406fd2029f23 519 /*@}*/
mbed_official 324:406fd2029f23 520
mbed_official 324:406fd2029f23 521 /*******************************************************************************
mbed_official 324:406fd2029f23 522 * HW_ADC_CFG2 - ADC Configuration Register 2
mbed_official 324:406fd2029f23 523 ******************************************************************************/
mbed_official 324:406fd2029f23 524
mbed_official 324:406fd2029f23 525 /*!
mbed_official 324:406fd2029f23 526 * @brief HW_ADC_CFG2 - ADC Configuration Register 2 (RW)
mbed_official 324:406fd2029f23 527 *
mbed_official 324:406fd2029f23 528 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 529 *
mbed_official 324:406fd2029f23 530 * Configuration Register 2 (CFG2) selects the special high-speed configuration
mbed_official 324:406fd2029f23 531 * for very high speed conversions and selects the long sample time duration
mbed_official 324:406fd2029f23 532 * during long sample mode.
mbed_official 324:406fd2029f23 533 */
mbed_official 324:406fd2029f23 534 typedef union _hw_adc_cfg2
mbed_official 324:406fd2029f23 535 {
mbed_official 324:406fd2029f23 536 uint32_t U;
mbed_official 324:406fd2029f23 537 struct _hw_adc_cfg2_bitfields
mbed_official 324:406fd2029f23 538 {
mbed_official 324:406fd2029f23 539 uint32_t ADLSTS : 2; /*!< [1:0] Long Sample Time Select */
mbed_official 324:406fd2029f23 540 uint32_t ADHSC : 1; /*!< [2] High-Speed Configuration */
mbed_official 324:406fd2029f23 541 uint32_t ADACKEN : 1; /*!< [3] Asynchronous Clock Output Enable */
mbed_official 324:406fd2029f23 542 uint32_t MUXSEL : 1; /*!< [4] ADC Mux Select */
mbed_official 324:406fd2029f23 543 uint32_t RESERVED0 : 27; /*!< [31:5] */
mbed_official 324:406fd2029f23 544 } B;
mbed_official 324:406fd2029f23 545 } hw_adc_cfg2_t;
mbed_official 324:406fd2029f23 546
mbed_official 324:406fd2029f23 547 /*!
mbed_official 324:406fd2029f23 548 * @name Constants and macros for entire ADC_CFG2 register
mbed_official 324:406fd2029f23 549 */
mbed_official 324:406fd2029f23 550 /*@{*/
mbed_official 324:406fd2029f23 551 #define HW_ADC_CFG2_ADDR(x) ((x) + 0xCU)
mbed_official 324:406fd2029f23 552
mbed_official 324:406fd2029f23 553 #define HW_ADC_CFG2(x) (*(__IO hw_adc_cfg2_t *) HW_ADC_CFG2_ADDR(x))
mbed_official 324:406fd2029f23 554 #define HW_ADC_CFG2_RD(x) (HW_ADC_CFG2(x).U)
mbed_official 324:406fd2029f23 555 #define HW_ADC_CFG2_WR(x, v) (HW_ADC_CFG2(x).U = (v))
mbed_official 324:406fd2029f23 556 #define HW_ADC_CFG2_SET(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) | (v)))
mbed_official 324:406fd2029f23 557 #define HW_ADC_CFG2_CLR(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 558 #define HW_ADC_CFG2_TOG(x, v) (HW_ADC_CFG2_WR(x, HW_ADC_CFG2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 559 /*@}*/
mbed_official 324:406fd2029f23 560
mbed_official 324:406fd2029f23 561 /*
mbed_official 324:406fd2029f23 562 * Constants & macros for individual ADC_CFG2 bitfields
mbed_official 324:406fd2029f23 563 */
mbed_official 324:406fd2029f23 564
mbed_official 324:406fd2029f23 565 /*!
mbed_official 324:406fd2029f23 566 * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
mbed_official 324:406fd2029f23 567 *
mbed_official 324:406fd2029f23 568 * Selects between the extended sample times when long sample time is selected,
mbed_official 324:406fd2029f23 569 * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
mbed_official 324:406fd2029f23 570 * accurately sampled or to maximize conversion speed for lower impedance inputs.
mbed_official 324:406fd2029f23 571 * Longer sample times can also be used to lower overall power consumption when
mbed_official 324:406fd2029f23 572 * continuous conversions are enabled if high conversion rates are not required.
mbed_official 324:406fd2029f23 573 *
mbed_official 324:406fd2029f23 574 * Values:
mbed_official 324:406fd2029f23 575 * - 00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
mbed_official 324:406fd2029f23 576 * total.
mbed_official 324:406fd2029f23 577 * - 01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
mbed_official 324:406fd2029f23 578 * - 10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
mbed_official 324:406fd2029f23 579 * - 11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
mbed_official 324:406fd2029f23 580 */
mbed_official 324:406fd2029f23 581 /*@{*/
mbed_official 324:406fd2029f23 582 #define BP_ADC_CFG2_ADLSTS (0U) /*!< Bit position for ADC_CFG2_ADLSTS. */
mbed_official 324:406fd2029f23 583 #define BM_ADC_CFG2_ADLSTS (0x00000003U) /*!< Bit mask for ADC_CFG2_ADLSTS. */
mbed_official 324:406fd2029f23 584 #define BS_ADC_CFG2_ADLSTS (2U) /*!< Bit field size in bits for ADC_CFG2_ADLSTS. */
mbed_official 324:406fd2029f23 585
mbed_official 324:406fd2029f23 586 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
mbed_official 324:406fd2029f23 587 #define BR_ADC_CFG2_ADLSTS(x) (HW_ADC_CFG2(x).B.ADLSTS)
mbed_official 324:406fd2029f23 588
mbed_official 324:406fd2029f23 589 /*! @brief Format value for bitfield ADC_CFG2_ADLSTS. */
mbed_official 324:406fd2029f23 590 #define BF_ADC_CFG2_ADLSTS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADLSTS) & BM_ADC_CFG2_ADLSTS)
mbed_official 324:406fd2029f23 591
mbed_official 324:406fd2029f23 592 /*! @brief Set the ADLSTS field to a new value. */
mbed_official 324:406fd2029f23 593 #define BW_ADC_CFG2_ADLSTS(x, v) (HW_ADC_CFG2_WR(x, (HW_ADC_CFG2_RD(x) & ~BM_ADC_CFG2_ADLSTS) | BF_ADC_CFG2_ADLSTS(v)))
mbed_official 324:406fd2029f23 594 /*@}*/
mbed_official 324:406fd2029f23 595
mbed_official 324:406fd2029f23 596 /*!
mbed_official 324:406fd2029f23 597 * @name Register ADC_CFG2, field ADHSC[2] (RW)
mbed_official 324:406fd2029f23 598 *
mbed_official 324:406fd2029f23 599 * Configures the ADC for very high-speed operation. The conversion sequence is
mbed_official 324:406fd2029f23 600 * altered with 2 ADCK cycles added to the conversion time to allow higher speed
mbed_official 324:406fd2029f23 601 * conversion clocks.
mbed_official 324:406fd2029f23 602 *
mbed_official 324:406fd2029f23 603 * Values:
mbed_official 324:406fd2029f23 604 * - 0 - Normal conversion sequence selected.
mbed_official 324:406fd2029f23 605 * - 1 - High-speed conversion sequence selected with 2 additional ADCK cycles
mbed_official 324:406fd2029f23 606 * to total conversion time.
mbed_official 324:406fd2029f23 607 */
mbed_official 324:406fd2029f23 608 /*@{*/
mbed_official 324:406fd2029f23 609 #define BP_ADC_CFG2_ADHSC (2U) /*!< Bit position for ADC_CFG2_ADHSC. */
mbed_official 324:406fd2029f23 610 #define BM_ADC_CFG2_ADHSC (0x00000004U) /*!< Bit mask for ADC_CFG2_ADHSC. */
mbed_official 324:406fd2029f23 611 #define BS_ADC_CFG2_ADHSC (1U) /*!< Bit field size in bits for ADC_CFG2_ADHSC. */
mbed_official 324:406fd2029f23 612
mbed_official 324:406fd2029f23 613 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
mbed_official 324:406fd2029f23 614 #define BR_ADC_CFG2_ADHSC(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC))
mbed_official 324:406fd2029f23 615
mbed_official 324:406fd2029f23 616 /*! @brief Format value for bitfield ADC_CFG2_ADHSC. */
mbed_official 324:406fd2029f23 617 #define BF_ADC_CFG2_ADHSC(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADHSC) & BM_ADC_CFG2_ADHSC)
mbed_official 324:406fd2029f23 618
mbed_official 324:406fd2029f23 619 /*! @brief Set the ADHSC field to a new value. */
mbed_official 324:406fd2029f23 620 #define BW_ADC_CFG2_ADHSC(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADHSC) = (v))
mbed_official 324:406fd2029f23 621 /*@}*/
mbed_official 324:406fd2029f23 622
mbed_official 324:406fd2029f23 623 /*!
mbed_official 324:406fd2029f23 624 * @name Register ADC_CFG2, field ADACKEN[3] (RW)
mbed_official 324:406fd2029f23 625 *
mbed_official 324:406fd2029f23 626 * Enables the asynchronous clock source and the clock source output regardless
mbed_official 324:406fd2029f23 627 * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
mbed_official 324:406fd2029f23 628 * asynchronous clock may be used by other modules. See chip configuration
mbed_official 324:406fd2029f23 629 * information. Setting this field allows the clock to be used even while the ADC is
mbed_official 324:406fd2029f23 630 * idle or operating from a different clock source. Also, latency of initiating a
mbed_official 324:406fd2029f23 631 * single or first-continuous conversion with the asynchronous clock selected is
mbed_official 324:406fd2029f23 632 * reduced because the ADACK clock is already operational.
mbed_official 324:406fd2029f23 633 *
mbed_official 324:406fd2029f23 634 * Values:
mbed_official 324:406fd2029f23 635 * - 0 - Asynchronous clock output disabled; Asynchronous clock is enabled only
mbed_official 324:406fd2029f23 636 * if selected by ADICLK and a conversion is active.
mbed_official 324:406fd2029f23 637 * - 1 - Asynchronous clock and clock output is enabled regardless of the state
mbed_official 324:406fd2029f23 638 * of the ADC.
mbed_official 324:406fd2029f23 639 */
mbed_official 324:406fd2029f23 640 /*@{*/
mbed_official 324:406fd2029f23 641 #define BP_ADC_CFG2_ADACKEN (3U) /*!< Bit position for ADC_CFG2_ADACKEN. */
mbed_official 324:406fd2029f23 642 #define BM_ADC_CFG2_ADACKEN (0x00000008U) /*!< Bit mask for ADC_CFG2_ADACKEN. */
mbed_official 324:406fd2029f23 643 #define BS_ADC_CFG2_ADACKEN (1U) /*!< Bit field size in bits for ADC_CFG2_ADACKEN. */
mbed_official 324:406fd2029f23 644
mbed_official 324:406fd2029f23 645 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
mbed_official 324:406fd2029f23 646 #define BR_ADC_CFG2_ADACKEN(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN))
mbed_official 324:406fd2029f23 647
mbed_official 324:406fd2029f23 648 /*! @brief Format value for bitfield ADC_CFG2_ADACKEN. */
mbed_official 324:406fd2029f23 649 #define BF_ADC_CFG2_ADACKEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_ADACKEN) & BM_ADC_CFG2_ADACKEN)
mbed_official 324:406fd2029f23 650
mbed_official 324:406fd2029f23 651 /*! @brief Set the ADACKEN field to a new value. */
mbed_official 324:406fd2029f23 652 #define BW_ADC_CFG2_ADACKEN(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_ADACKEN) = (v))
mbed_official 324:406fd2029f23 653 /*@}*/
mbed_official 324:406fd2029f23 654
mbed_official 324:406fd2029f23 655 /*!
mbed_official 324:406fd2029f23 656 * @name Register ADC_CFG2, field MUXSEL[4] (RW)
mbed_official 324:406fd2029f23 657 *
mbed_official 324:406fd2029f23 658 * Changes the ADC mux setting to select between alternate sets of ADC channels.
mbed_official 324:406fd2029f23 659 *
mbed_official 324:406fd2029f23 660 * Values:
mbed_official 324:406fd2029f23 661 * - 0 - ADxxa channels are selected.
mbed_official 324:406fd2029f23 662 * - 1 - ADxxb channels are selected.
mbed_official 324:406fd2029f23 663 */
mbed_official 324:406fd2029f23 664 /*@{*/
mbed_official 324:406fd2029f23 665 #define BP_ADC_CFG2_MUXSEL (4U) /*!< Bit position for ADC_CFG2_MUXSEL. */
mbed_official 324:406fd2029f23 666 #define BM_ADC_CFG2_MUXSEL (0x00000010U) /*!< Bit mask for ADC_CFG2_MUXSEL. */
mbed_official 324:406fd2029f23 667 #define BS_ADC_CFG2_MUXSEL (1U) /*!< Bit field size in bits for ADC_CFG2_MUXSEL. */
mbed_official 324:406fd2029f23 668
mbed_official 324:406fd2029f23 669 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
mbed_official 324:406fd2029f23 670 #define BR_ADC_CFG2_MUXSEL(x) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL))
mbed_official 324:406fd2029f23 671
mbed_official 324:406fd2029f23 672 /*! @brief Format value for bitfield ADC_CFG2_MUXSEL. */
mbed_official 324:406fd2029f23 673 #define BF_ADC_CFG2_MUXSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CFG2_MUXSEL) & BM_ADC_CFG2_MUXSEL)
mbed_official 324:406fd2029f23 674
mbed_official 324:406fd2029f23 675 /*! @brief Set the MUXSEL field to a new value. */
mbed_official 324:406fd2029f23 676 #define BW_ADC_CFG2_MUXSEL(x, v) (BITBAND_ACCESS32(HW_ADC_CFG2_ADDR(x), BP_ADC_CFG2_MUXSEL) = (v))
mbed_official 324:406fd2029f23 677 /*@}*/
mbed_official 324:406fd2029f23 678
mbed_official 324:406fd2029f23 679 /*******************************************************************************
mbed_official 324:406fd2029f23 680 * HW_ADC_Rn - ADC Data Result Register
mbed_official 324:406fd2029f23 681 ******************************************************************************/
mbed_official 324:406fd2029f23 682
mbed_official 324:406fd2029f23 683 /*!
mbed_official 324:406fd2029f23 684 * @brief HW_ADC_Rn - ADC Data Result Register (RO)
mbed_official 324:406fd2029f23 685 *
mbed_official 324:406fd2029f23 686 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 687 *
mbed_official 324:406fd2029f23 688 * The data result registers (Rn) contain the result of an ADC conversion of the
mbed_official 324:406fd2029f23 689 * channel selected by the corresponding status and channel control register
mbed_official 324:406fd2029f23 690 * (SC1A:SC1n). For every status and channel control register, there is a
mbed_official 324:406fd2029f23 691 * corresponding data result register. Unused bits in R n are cleared in unsigned
mbed_official 324:406fd2029f23 692 * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement modes.
mbed_official 324:406fd2029f23 693 * For example, when configured for 10-bit single-ended mode, D[15:10] are
mbed_official 324:406fd2029f23 694 * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign bit,
mbed_official 324:406fd2029f23 695 * that is, bit 10 extended through bit 15. The following table describes the
mbed_official 324:406fd2029f23 696 * behavior of the data result registers in the different modes of operation. Data
mbed_official 324:406fd2029f23 697 * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
mbed_official 324:406fd2029f23 698 * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D D
mbed_official 324:406fd2029f23 699 * Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
mbed_official 324:406fd2029f23 700 * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
mbed_official 324:406fd2029f23 701 * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
mbed_official 324:406fd2029f23 702 * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
mbed_official 324:406fd2029f23 703 * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D D
mbed_official 324:406fd2029f23 704 * Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
mbed_official 324:406fd2029f23 705 * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D D
mbed_official 324:406fd2029f23 706 * Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which is
mbed_official 324:406fd2029f23 707 * 2's complement data if indicated
mbed_official 324:406fd2029f23 708 */
mbed_official 324:406fd2029f23 709 typedef union _hw_adc_rn
mbed_official 324:406fd2029f23 710 {
mbed_official 324:406fd2029f23 711 uint32_t U;
mbed_official 324:406fd2029f23 712 struct _hw_adc_rn_bitfields
mbed_official 324:406fd2029f23 713 {
mbed_official 324:406fd2029f23 714 uint32_t D : 16; /*!< [15:0] Data result */
mbed_official 324:406fd2029f23 715 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 716 } B;
mbed_official 324:406fd2029f23 717 } hw_adc_rn_t;
mbed_official 324:406fd2029f23 718
mbed_official 324:406fd2029f23 719 /*!
mbed_official 324:406fd2029f23 720 * @name Constants and macros for entire ADC_Rn register
mbed_official 324:406fd2029f23 721 */
mbed_official 324:406fd2029f23 722 /*@{*/
mbed_official 324:406fd2029f23 723 #define HW_ADC_Rn_COUNT (2U)
mbed_official 324:406fd2029f23 724
mbed_official 324:406fd2029f23 725 #define HW_ADC_Rn_ADDR(x, n) ((x) + 0x10U + (0x4U * (n)))
mbed_official 324:406fd2029f23 726
mbed_official 324:406fd2029f23 727 #define HW_ADC_Rn(x, n) (*(__I hw_adc_rn_t *) HW_ADC_Rn_ADDR(x, n))
mbed_official 324:406fd2029f23 728 #define HW_ADC_Rn_RD(x, n) (HW_ADC_Rn(x, n).U)
mbed_official 324:406fd2029f23 729 /*@}*/
mbed_official 324:406fd2029f23 730
mbed_official 324:406fd2029f23 731 /*
mbed_official 324:406fd2029f23 732 * Constants & macros for individual ADC_Rn bitfields
mbed_official 324:406fd2029f23 733 */
mbed_official 324:406fd2029f23 734
mbed_official 324:406fd2029f23 735 /*!
mbed_official 324:406fd2029f23 736 * @name Register ADC_Rn, field D[15:0] (RO)
mbed_official 324:406fd2029f23 737 */
mbed_official 324:406fd2029f23 738 /*@{*/
mbed_official 324:406fd2029f23 739 #define BP_ADC_Rn_D (0U) /*!< Bit position for ADC_Rn_D. */
mbed_official 324:406fd2029f23 740 #define BM_ADC_Rn_D (0x0000FFFFU) /*!< Bit mask for ADC_Rn_D. */
mbed_official 324:406fd2029f23 741 #define BS_ADC_Rn_D (16U) /*!< Bit field size in bits for ADC_Rn_D. */
mbed_official 324:406fd2029f23 742
mbed_official 324:406fd2029f23 743 /*! @brief Read current value of the ADC_Rn_D field. */
mbed_official 324:406fd2029f23 744 #define BR_ADC_Rn_D(x, n) (HW_ADC_Rn(x, n).B.D)
mbed_official 324:406fd2029f23 745 /*@}*/
mbed_official 324:406fd2029f23 746
mbed_official 324:406fd2029f23 747 /*******************************************************************************
mbed_official 324:406fd2029f23 748 * HW_ADC_CV1 - Compare Value Registers
mbed_official 324:406fd2029f23 749 ******************************************************************************/
mbed_official 324:406fd2029f23 750
mbed_official 324:406fd2029f23 751 /*!
mbed_official 324:406fd2029f23 752 * @brief HW_ADC_CV1 - Compare Value Registers (RW)
mbed_official 324:406fd2029f23 753 *
mbed_official 324:406fd2029f23 754 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 755 *
mbed_official 324:406fd2029f23 756 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
mbed_official 324:406fd2029f23 757 * compare the conversion result when the compare function is enabled, that is,
mbed_official 324:406fd2029f23 758 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
mbed_official 324:406fd2029f23 759 * different modes of operation for both bit position definition and value format
mbed_official 324:406fd2029f23 760 * using unsigned or sign-extended 2's complement. Therefore, the compare function
mbed_official 324:406fd2029f23 761 * uses only the CVn fields that are related to the ADC mode of operation. The
mbed_official 324:406fd2029f23 762 * compare value 2 register (CV2) is used only when the compare range function is
mbed_official 324:406fd2029f23 763 * enabled, that is, SC2[ACREN]=1.
mbed_official 324:406fd2029f23 764 */
mbed_official 324:406fd2029f23 765 typedef union _hw_adc_cv1
mbed_official 324:406fd2029f23 766 {
mbed_official 324:406fd2029f23 767 uint32_t U;
mbed_official 324:406fd2029f23 768 struct _hw_adc_cv1_bitfields
mbed_official 324:406fd2029f23 769 {
mbed_official 324:406fd2029f23 770 uint32_t CV : 16; /*!< [15:0] Compare Value. */
mbed_official 324:406fd2029f23 771 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 772 } B;
mbed_official 324:406fd2029f23 773 } hw_adc_cv1_t;
mbed_official 324:406fd2029f23 774
mbed_official 324:406fd2029f23 775 /*!
mbed_official 324:406fd2029f23 776 * @name Constants and macros for entire ADC_CV1 register
mbed_official 324:406fd2029f23 777 */
mbed_official 324:406fd2029f23 778 /*@{*/
mbed_official 324:406fd2029f23 779 #define HW_ADC_CV1_ADDR(x) ((x) + 0x18U)
mbed_official 324:406fd2029f23 780
mbed_official 324:406fd2029f23 781 #define HW_ADC_CV1(x) (*(__IO hw_adc_cv1_t *) HW_ADC_CV1_ADDR(x))
mbed_official 324:406fd2029f23 782 #define HW_ADC_CV1_RD(x) (HW_ADC_CV1(x).U)
mbed_official 324:406fd2029f23 783 #define HW_ADC_CV1_WR(x, v) (HW_ADC_CV1(x).U = (v))
mbed_official 324:406fd2029f23 784 #define HW_ADC_CV1_SET(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) | (v)))
mbed_official 324:406fd2029f23 785 #define HW_ADC_CV1_CLR(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 786 #define HW_ADC_CV1_TOG(x, v) (HW_ADC_CV1_WR(x, HW_ADC_CV1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 787 /*@}*/
mbed_official 324:406fd2029f23 788
mbed_official 324:406fd2029f23 789 /*
mbed_official 324:406fd2029f23 790 * Constants & macros for individual ADC_CV1 bitfields
mbed_official 324:406fd2029f23 791 */
mbed_official 324:406fd2029f23 792
mbed_official 324:406fd2029f23 793 /*!
mbed_official 324:406fd2029f23 794 * @name Register ADC_CV1, field CV[15:0] (RW)
mbed_official 324:406fd2029f23 795 */
mbed_official 324:406fd2029f23 796 /*@{*/
mbed_official 324:406fd2029f23 797 #define BP_ADC_CV1_CV (0U) /*!< Bit position for ADC_CV1_CV. */
mbed_official 324:406fd2029f23 798 #define BM_ADC_CV1_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV1_CV. */
mbed_official 324:406fd2029f23 799 #define BS_ADC_CV1_CV (16U) /*!< Bit field size in bits for ADC_CV1_CV. */
mbed_official 324:406fd2029f23 800
mbed_official 324:406fd2029f23 801 /*! @brief Read current value of the ADC_CV1_CV field. */
mbed_official 324:406fd2029f23 802 #define BR_ADC_CV1_CV(x) (HW_ADC_CV1(x).B.CV)
mbed_official 324:406fd2029f23 803
mbed_official 324:406fd2029f23 804 /*! @brief Format value for bitfield ADC_CV1_CV. */
mbed_official 324:406fd2029f23 805 #define BF_ADC_CV1_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV1_CV) & BM_ADC_CV1_CV)
mbed_official 324:406fd2029f23 806
mbed_official 324:406fd2029f23 807 /*! @brief Set the CV field to a new value. */
mbed_official 324:406fd2029f23 808 #define BW_ADC_CV1_CV(x, v) (HW_ADC_CV1_WR(x, (HW_ADC_CV1_RD(x) & ~BM_ADC_CV1_CV) | BF_ADC_CV1_CV(v)))
mbed_official 324:406fd2029f23 809 /*@}*/
mbed_official 324:406fd2029f23 810
mbed_official 324:406fd2029f23 811 /*******************************************************************************
mbed_official 324:406fd2029f23 812 * HW_ADC_CV2 - Compare Value Registers
mbed_official 324:406fd2029f23 813 ******************************************************************************/
mbed_official 324:406fd2029f23 814
mbed_official 324:406fd2029f23 815 /*!
mbed_official 324:406fd2029f23 816 * @brief HW_ADC_CV2 - Compare Value Registers (RW)
mbed_official 324:406fd2029f23 817 *
mbed_official 324:406fd2029f23 818 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 819 *
mbed_official 324:406fd2029f23 820 * The Compare Value Registers (CV1 and CV2) contain a compare value used to
mbed_official 324:406fd2029f23 821 * compare the conversion result when the compare function is enabled, that is,
mbed_official 324:406fd2029f23 822 * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
mbed_official 324:406fd2029f23 823 * different modes of operation for both bit position definition and value format
mbed_official 324:406fd2029f23 824 * using unsigned or sign-extended 2's complement. Therefore, the compare function
mbed_official 324:406fd2029f23 825 * uses only the CVn fields that are related to the ADC mode of operation. The
mbed_official 324:406fd2029f23 826 * compare value 2 register (CV2) is used only when the compare range function is
mbed_official 324:406fd2029f23 827 * enabled, that is, SC2[ACREN]=1.
mbed_official 324:406fd2029f23 828 */
mbed_official 324:406fd2029f23 829 typedef union _hw_adc_cv2
mbed_official 324:406fd2029f23 830 {
mbed_official 324:406fd2029f23 831 uint32_t U;
mbed_official 324:406fd2029f23 832 struct _hw_adc_cv2_bitfields
mbed_official 324:406fd2029f23 833 {
mbed_official 324:406fd2029f23 834 uint32_t CV : 16; /*!< [15:0] Compare Value. */
mbed_official 324:406fd2029f23 835 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 836 } B;
mbed_official 324:406fd2029f23 837 } hw_adc_cv2_t;
mbed_official 324:406fd2029f23 838
mbed_official 324:406fd2029f23 839 /*!
mbed_official 324:406fd2029f23 840 * @name Constants and macros for entire ADC_CV2 register
mbed_official 324:406fd2029f23 841 */
mbed_official 324:406fd2029f23 842 /*@{*/
mbed_official 324:406fd2029f23 843 #define HW_ADC_CV2_ADDR(x) ((x) + 0x1CU)
mbed_official 324:406fd2029f23 844
mbed_official 324:406fd2029f23 845 #define HW_ADC_CV2(x) (*(__IO hw_adc_cv2_t *) HW_ADC_CV2_ADDR(x))
mbed_official 324:406fd2029f23 846 #define HW_ADC_CV2_RD(x) (HW_ADC_CV2(x).U)
mbed_official 324:406fd2029f23 847 #define HW_ADC_CV2_WR(x, v) (HW_ADC_CV2(x).U = (v))
mbed_official 324:406fd2029f23 848 #define HW_ADC_CV2_SET(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) | (v)))
mbed_official 324:406fd2029f23 849 #define HW_ADC_CV2_CLR(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 850 #define HW_ADC_CV2_TOG(x, v) (HW_ADC_CV2_WR(x, HW_ADC_CV2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 851 /*@}*/
mbed_official 324:406fd2029f23 852
mbed_official 324:406fd2029f23 853 /*
mbed_official 324:406fd2029f23 854 * Constants & macros for individual ADC_CV2 bitfields
mbed_official 324:406fd2029f23 855 */
mbed_official 324:406fd2029f23 856
mbed_official 324:406fd2029f23 857 /*!
mbed_official 324:406fd2029f23 858 * @name Register ADC_CV2, field CV[15:0] (RW)
mbed_official 324:406fd2029f23 859 */
mbed_official 324:406fd2029f23 860 /*@{*/
mbed_official 324:406fd2029f23 861 #define BP_ADC_CV2_CV (0U) /*!< Bit position for ADC_CV2_CV. */
mbed_official 324:406fd2029f23 862 #define BM_ADC_CV2_CV (0x0000FFFFU) /*!< Bit mask for ADC_CV2_CV. */
mbed_official 324:406fd2029f23 863 #define BS_ADC_CV2_CV (16U) /*!< Bit field size in bits for ADC_CV2_CV. */
mbed_official 324:406fd2029f23 864
mbed_official 324:406fd2029f23 865 /*! @brief Read current value of the ADC_CV2_CV field. */
mbed_official 324:406fd2029f23 866 #define BR_ADC_CV2_CV(x) (HW_ADC_CV2(x).B.CV)
mbed_official 324:406fd2029f23 867
mbed_official 324:406fd2029f23 868 /*! @brief Format value for bitfield ADC_CV2_CV. */
mbed_official 324:406fd2029f23 869 #define BF_ADC_CV2_CV(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CV2_CV) & BM_ADC_CV2_CV)
mbed_official 324:406fd2029f23 870
mbed_official 324:406fd2029f23 871 /*! @brief Set the CV field to a new value. */
mbed_official 324:406fd2029f23 872 #define BW_ADC_CV2_CV(x, v) (HW_ADC_CV2_WR(x, (HW_ADC_CV2_RD(x) & ~BM_ADC_CV2_CV) | BF_ADC_CV2_CV(v)))
mbed_official 324:406fd2029f23 873 /*@}*/
mbed_official 324:406fd2029f23 874
mbed_official 324:406fd2029f23 875 /*******************************************************************************
mbed_official 324:406fd2029f23 876 * HW_ADC_SC2 - Status and Control Register 2
mbed_official 324:406fd2029f23 877 ******************************************************************************/
mbed_official 324:406fd2029f23 878
mbed_official 324:406fd2029f23 879 /*!
mbed_official 324:406fd2029f23 880 * @brief HW_ADC_SC2 - Status and Control Register 2 (RW)
mbed_official 324:406fd2029f23 881 *
mbed_official 324:406fd2029f23 882 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 883 *
mbed_official 324:406fd2029f23 884 * The status and control register 2 (SC2) contains the conversion active,
mbed_official 324:406fd2029f23 885 * hardware/software trigger select, compare function, and voltage reference select of
mbed_official 324:406fd2029f23 886 * the ADC module.
mbed_official 324:406fd2029f23 887 */
mbed_official 324:406fd2029f23 888 typedef union _hw_adc_sc2
mbed_official 324:406fd2029f23 889 {
mbed_official 324:406fd2029f23 890 uint32_t U;
mbed_official 324:406fd2029f23 891 struct _hw_adc_sc2_bitfields
mbed_official 324:406fd2029f23 892 {
mbed_official 324:406fd2029f23 893 uint32_t REFSEL : 2; /*!< [1:0] Voltage Reference Selection */
mbed_official 324:406fd2029f23 894 uint32_t DMAEN : 1; /*!< [2] DMA Enable */
mbed_official 324:406fd2029f23 895 uint32_t ACREN : 1; /*!< [3] Compare Function Range Enable */
mbed_official 324:406fd2029f23 896 uint32_t ACFGT : 1; /*!< [4] Compare Function Greater Than Enable */
mbed_official 324:406fd2029f23 897 uint32_t ACFE : 1; /*!< [5] Compare Function Enable */
mbed_official 324:406fd2029f23 898 uint32_t ADTRG : 1; /*!< [6] Conversion Trigger Select */
mbed_official 324:406fd2029f23 899 uint32_t ADACT : 1; /*!< [7] Conversion Active */
mbed_official 324:406fd2029f23 900 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 901 } B;
mbed_official 324:406fd2029f23 902 } hw_adc_sc2_t;
mbed_official 324:406fd2029f23 903
mbed_official 324:406fd2029f23 904 /*!
mbed_official 324:406fd2029f23 905 * @name Constants and macros for entire ADC_SC2 register
mbed_official 324:406fd2029f23 906 */
mbed_official 324:406fd2029f23 907 /*@{*/
mbed_official 324:406fd2029f23 908 #define HW_ADC_SC2_ADDR(x) ((x) + 0x20U)
mbed_official 324:406fd2029f23 909
mbed_official 324:406fd2029f23 910 #define HW_ADC_SC2(x) (*(__IO hw_adc_sc2_t *) HW_ADC_SC2_ADDR(x))
mbed_official 324:406fd2029f23 911 #define HW_ADC_SC2_RD(x) (HW_ADC_SC2(x).U)
mbed_official 324:406fd2029f23 912 #define HW_ADC_SC2_WR(x, v) (HW_ADC_SC2(x).U = (v))
mbed_official 324:406fd2029f23 913 #define HW_ADC_SC2_SET(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) | (v)))
mbed_official 324:406fd2029f23 914 #define HW_ADC_SC2_CLR(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 915 #define HW_ADC_SC2_TOG(x, v) (HW_ADC_SC2_WR(x, HW_ADC_SC2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 916 /*@}*/
mbed_official 324:406fd2029f23 917
mbed_official 324:406fd2029f23 918 /*
mbed_official 324:406fd2029f23 919 * Constants & macros for individual ADC_SC2 bitfields
mbed_official 324:406fd2029f23 920 */
mbed_official 324:406fd2029f23 921
mbed_official 324:406fd2029f23 922 /*!
mbed_official 324:406fd2029f23 923 * @name Register ADC_SC2, field REFSEL[1:0] (RW)
mbed_official 324:406fd2029f23 924 *
mbed_official 324:406fd2029f23 925 * Selects the voltage reference source used for conversions.
mbed_official 324:406fd2029f23 926 *
mbed_official 324:406fd2029f23 927 * Values:
mbed_official 324:406fd2029f23 928 * - 00 - Default voltage reference pin pair, that is, external pins VREFH and
mbed_official 324:406fd2029f23 929 * VREFL
mbed_official 324:406fd2029f23 930 * - 01 - Alternate reference pair, that is, VALTH and VALTL . This pair may be
mbed_official 324:406fd2029f23 931 * additional external pins or internal sources depending on the MCU
mbed_official 324:406fd2029f23 932 * configuration. See the chip configuration information for details specific to this
mbed_official 324:406fd2029f23 933 * MCU
mbed_official 324:406fd2029f23 934 * - 10 - Reserved
mbed_official 324:406fd2029f23 935 * - 11 - Reserved
mbed_official 324:406fd2029f23 936 */
mbed_official 324:406fd2029f23 937 /*@{*/
mbed_official 324:406fd2029f23 938 #define BP_ADC_SC2_REFSEL (0U) /*!< Bit position for ADC_SC2_REFSEL. */
mbed_official 324:406fd2029f23 939 #define BM_ADC_SC2_REFSEL (0x00000003U) /*!< Bit mask for ADC_SC2_REFSEL. */
mbed_official 324:406fd2029f23 940 #define BS_ADC_SC2_REFSEL (2U) /*!< Bit field size in bits for ADC_SC2_REFSEL. */
mbed_official 324:406fd2029f23 941
mbed_official 324:406fd2029f23 942 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
mbed_official 324:406fd2029f23 943 #define BR_ADC_SC2_REFSEL(x) (HW_ADC_SC2(x).B.REFSEL)
mbed_official 324:406fd2029f23 944
mbed_official 324:406fd2029f23 945 /*! @brief Format value for bitfield ADC_SC2_REFSEL. */
mbed_official 324:406fd2029f23 946 #define BF_ADC_SC2_REFSEL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_REFSEL) & BM_ADC_SC2_REFSEL)
mbed_official 324:406fd2029f23 947
mbed_official 324:406fd2029f23 948 /*! @brief Set the REFSEL field to a new value. */
mbed_official 324:406fd2029f23 949 #define BW_ADC_SC2_REFSEL(x, v) (HW_ADC_SC2_WR(x, (HW_ADC_SC2_RD(x) & ~BM_ADC_SC2_REFSEL) | BF_ADC_SC2_REFSEL(v)))
mbed_official 324:406fd2029f23 950 /*@}*/
mbed_official 324:406fd2029f23 951
mbed_official 324:406fd2029f23 952 /*!
mbed_official 324:406fd2029f23 953 * @name Register ADC_SC2, field DMAEN[2] (RW)
mbed_official 324:406fd2029f23 954 *
mbed_official 324:406fd2029f23 955 * Values:
mbed_official 324:406fd2029f23 956 * - 0 - DMA is disabled.
mbed_official 324:406fd2029f23 957 * - 1 - DMA is enabled and will assert the ADC DMA request during an ADC
mbed_official 324:406fd2029f23 958 * conversion complete event noted when any of the SC1n[COCO] flags is asserted.
mbed_official 324:406fd2029f23 959 */
mbed_official 324:406fd2029f23 960 /*@{*/
mbed_official 324:406fd2029f23 961 #define BP_ADC_SC2_DMAEN (2U) /*!< Bit position for ADC_SC2_DMAEN. */
mbed_official 324:406fd2029f23 962 #define BM_ADC_SC2_DMAEN (0x00000004U) /*!< Bit mask for ADC_SC2_DMAEN. */
mbed_official 324:406fd2029f23 963 #define BS_ADC_SC2_DMAEN (1U) /*!< Bit field size in bits for ADC_SC2_DMAEN. */
mbed_official 324:406fd2029f23 964
mbed_official 324:406fd2029f23 965 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
mbed_official 324:406fd2029f23 966 #define BR_ADC_SC2_DMAEN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN))
mbed_official 324:406fd2029f23 967
mbed_official 324:406fd2029f23 968 /*! @brief Format value for bitfield ADC_SC2_DMAEN. */
mbed_official 324:406fd2029f23 969 #define BF_ADC_SC2_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_DMAEN) & BM_ADC_SC2_DMAEN)
mbed_official 324:406fd2029f23 970
mbed_official 324:406fd2029f23 971 /*! @brief Set the DMAEN field to a new value. */
mbed_official 324:406fd2029f23 972 #define BW_ADC_SC2_DMAEN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_DMAEN) = (v))
mbed_official 324:406fd2029f23 973 /*@}*/
mbed_official 324:406fd2029f23 974
mbed_official 324:406fd2029f23 975 /*!
mbed_official 324:406fd2029f23 976 * @name Register ADC_SC2, field ACREN[3] (RW)
mbed_official 324:406fd2029f23 977 *
mbed_official 324:406fd2029f23 978 * Configures the compare function to check if the conversion result of the
mbed_official 324:406fd2029f23 979 * input being monitored is either between or outside the range formed by CV1 and CV2
mbed_official 324:406fd2029f23 980 * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
mbed_official 324:406fd2029f23 981 * effect.
mbed_official 324:406fd2029f23 982 *
mbed_official 324:406fd2029f23 983 * Values:
mbed_official 324:406fd2029f23 984 * - 0 - Range function disabled. Only CV1 is compared.
mbed_official 324:406fd2029f23 985 * - 1 - Range function enabled. Both CV1 and CV2 are compared.
mbed_official 324:406fd2029f23 986 */
mbed_official 324:406fd2029f23 987 /*@{*/
mbed_official 324:406fd2029f23 988 #define BP_ADC_SC2_ACREN (3U) /*!< Bit position for ADC_SC2_ACREN. */
mbed_official 324:406fd2029f23 989 #define BM_ADC_SC2_ACREN (0x00000008U) /*!< Bit mask for ADC_SC2_ACREN. */
mbed_official 324:406fd2029f23 990 #define BS_ADC_SC2_ACREN (1U) /*!< Bit field size in bits for ADC_SC2_ACREN. */
mbed_official 324:406fd2029f23 991
mbed_official 324:406fd2029f23 992 /*! @brief Read current value of the ADC_SC2_ACREN field. */
mbed_official 324:406fd2029f23 993 #define BR_ADC_SC2_ACREN(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN))
mbed_official 324:406fd2029f23 994
mbed_official 324:406fd2029f23 995 /*! @brief Format value for bitfield ADC_SC2_ACREN. */
mbed_official 324:406fd2029f23 996 #define BF_ADC_SC2_ACREN(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACREN) & BM_ADC_SC2_ACREN)
mbed_official 324:406fd2029f23 997
mbed_official 324:406fd2029f23 998 /*! @brief Set the ACREN field to a new value. */
mbed_official 324:406fd2029f23 999 #define BW_ADC_SC2_ACREN(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACREN) = (v))
mbed_official 324:406fd2029f23 1000 /*@}*/
mbed_official 324:406fd2029f23 1001
mbed_official 324:406fd2029f23 1002 /*!
mbed_official 324:406fd2029f23 1003 * @name Register ADC_SC2, field ACFGT[4] (RW)
mbed_official 324:406fd2029f23 1004 *
mbed_official 324:406fd2029f23 1005 * Configures the compare function to check the conversion result relative to
mbed_official 324:406fd2029f23 1006 * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
mbed_official 324:406fd2029f23 1007 * have any effect.
mbed_official 324:406fd2029f23 1008 *
mbed_official 324:406fd2029f23 1009 * Values:
mbed_official 324:406fd2029f23 1010 * - 0 - Configures less than threshold, outside range not inclusive and inside
mbed_official 324:406fd2029f23 1011 * range not inclusive; functionality based on the values placed in CV1 and
mbed_official 324:406fd2029f23 1012 * CV2.
mbed_official 324:406fd2029f23 1013 * - 1 - Configures greater than or equal to threshold, outside and inside
mbed_official 324:406fd2029f23 1014 * ranges inclusive; functionality based on the values placed in CV1 and CV2.
mbed_official 324:406fd2029f23 1015 */
mbed_official 324:406fd2029f23 1016 /*@{*/
mbed_official 324:406fd2029f23 1017 #define BP_ADC_SC2_ACFGT (4U) /*!< Bit position for ADC_SC2_ACFGT. */
mbed_official 324:406fd2029f23 1018 #define BM_ADC_SC2_ACFGT (0x00000010U) /*!< Bit mask for ADC_SC2_ACFGT. */
mbed_official 324:406fd2029f23 1019 #define BS_ADC_SC2_ACFGT (1U) /*!< Bit field size in bits for ADC_SC2_ACFGT. */
mbed_official 324:406fd2029f23 1020
mbed_official 324:406fd2029f23 1021 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
mbed_official 324:406fd2029f23 1022 #define BR_ADC_SC2_ACFGT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT))
mbed_official 324:406fd2029f23 1023
mbed_official 324:406fd2029f23 1024 /*! @brief Format value for bitfield ADC_SC2_ACFGT. */
mbed_official 324:406fd2029f23 1025 #define BF_ADC_SC2_ACFGT(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFGT) & BM_ADC_SC2_ACFGT)
mbed_official 324:406fd2029f23 1026
mbed_official 324:406fd2029f23 1027 /*! @brief Set the ACFGT field to a new value. */
mbed_official 324:406fd2029f23 1028 #define BW_ADC_SC2_ACFGT(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFGT) = (v))
mbed_official 324:406fd2029f23 1029 /*@}*/
mbed_official 324:406fd2029f23 1030
mbed_official 324:406fd2029f23 1031 /*!
mbed_official 324:406fd2029f23 1032 * @name Register ADC_SC2, field ACFE[5] (RW)
mbed_official 324:406fd2029f23 1033 *
mbed_official 324:406fd2029f23 1034 * Enables the compare function.
mbed_official 324:406fd2029f23 1035 *
mbed_official 324:406fd2029f23 1036 * Values:
mbed_official 324:406fd2029f23 1037 * - 0 - Compare function disabled.
mbed_official 324:406fd2029f23 1038 * - 1 - Compare function enabled.
mbed_official 324:406fd2029f23 1039 */
mbed_official 324:406fd2029f23 1040 /*@{*/
mbed_official 324:406fd2029f23 1041 #define BP_ADC_SC2_ACFE (5U) /*!< Bit position for ADC_SC2_ACFE. */
mbed_official 324:406fd2029f23 1042 #define BM_ADC_SC2_ACFE (0x00000020U) /*!< Bit mask for ADC_SC2_ACFE. */
mbed_official 324:406fd2029f23 1043 #define BS_ADC_SC2_ACFE (1U) /*!< Bit field size in bits for ADC_SC2_ACFE. */
mbed_official 324:406fd2029f23 1044
mbed_official 324:406fd2029f23 1045 /*! @brief Read current value of the ADC_SC2_ACFE field. */
mbed_official 324:406fd2029f23 1046 #define BR_ADC_SC2_ACFE(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE))
mbed_official 324:406fd2029f23 1047
mbed_official 324:406fd2029f23 1048 /*! @brief Format value for bitfield ADC_SC2_ACFE. */
mbed_official 324:406fd2029f23 1049 #define BF_ADC_SC2_ACFE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ACFE) & BM_ADC_SC2_ACFE)
mbed_official 324:406fd2029f23 1050
mbed_official 324:406fd2029f23 1051 /*! @brief Set the ACFE field to a new value. */
mbed_official 324:406fd2029f23 1052 #define BW_ADC_SC2_ACFE(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ACFE) = (v))
mbed_official 324:406fd2029f23 1053 /*@}*/
mbed_official 324:406fd2029f23 1054
mbed_official 324:406fd2029f23 1055 /*!
mbed_official 324:406fd2029f23 1056 * @name Register ADC_SC2, field ADTRG[6] (RW)
mbed_official 324:406fd2029f23 1057 *
mbed_official 324:406fd2029f23 1058 * Selects the type of trigger used for initiating a conversion. Two types of
mbed_official 324:406fd2029f23 1059 * trigger are selectable: Software trigger: When software trigger is selected, a
mbed_official 324:406fd2029f23 1060 * conversion is initiated following a write to SC1A. Hardware trigger: When
mbed_official 324:406fd2029f23 1061 * hardware trigger is selected, a conversion is initiated following the assertion of
mbed_official 324:406fd2029f23 1062 * the ADHWT input after a pulse of the ADHWTSn input.
mbed_official 324:406fd2029f23 1063 *
mbed_official 324:406fd2029f23 1064 * Values:
mbed_official 324:406fd2029f23 1065 * - 0 - Software trigger selected.
mbed_official 324:406fd2029f23 1066 * - 1 - Hardware trigger selected.
mbed_official 324:406fd2029f23 1067 */
mbed_official 324:406fd2029f23 1068 /*@{*/
mbed_official 324:406fd2029f23 1069 #define BP_ADC_SC2_ADTRG (6U) /*!< Bit position for ADC_SC2_ADTRG. */
mbed_official 324:406fd2029f23 1070 #define BM_ADC_SC2_ADTRG (0x00000040U) /*!< Bit mask for ADC_SC2_ADTRG. */
mbed_official 324:406fd2029f23 1071 #define BS_ADC_SC2_ADTRG (1U) /*!< Bit field size in bits for ADC_SC2_ADTRG. */
mbed_official 324:406fd2029f23 1072
mbed_official 324:406fd2029f23 1073 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
mbed_official 324:406fd2029f23 1074 #define BR_ADC_SC2_ADTRG(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG))
mbed_official 324:406fd2029f23 1075
mbed_official 324:406fd2029f23 1076 /*! @brief Format value for bitfield ADC_SC2_ADTRG. */
mbed_official 324:406fd2029f23 1077 #define BF_ADC_SC2_ADTRG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC2_ADTRG) & BM_ADC_SC2_ADTRG)
mbed_official 324:406fd2029f23 1078
mbed_official 324:406fd2029f23 1079 /*! @brief Set the ADTRG field to a new value. */
mbed_official 324:406fd2029f23 1080 #define BW_ADC_SC2_ADTRG(x, v) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADTRG) = (v))
mbed_official 324:406fd2029f23 1081 /*@}*/
mbed_official 324:406fd2029f23 1082
mbed_official 324:406fd2029f23 1083 /*!
mbed_official 324:406fd2029f23 1084 * @name Register ADC_SC2, field ADACT[7] (RO)
mbed_official 324:406fd2029f23 1085 *
mbed_official 324:406fd2029f23 1086 * Indicates that a conversion or hardware averaging is in progress. ADACT is
mbed_official 324:406fd2029f23 1087 * set when a conversion is initiated and cleared when a conversion is completed or
mbed_official 324:406fd2029f23 1088 * aborted.
mbed_official 324:406fd2029f23 1089 *
mbed_official 324:406fd2029f23 1090 * Values:
mbed_official 324:406fd2029f23 1091 * - 0 - Conversion not in progress.
mbed_official 324:406fd2029f23 1092 * - 1 - Conversion in progress.
mbed_official 324:406fd2029f23 1093 */
mbed_official 324:406fd2029f23 1094 /*@{*/
mbed_official 324:406fd2029f23 1095 #define BP_ADC_SC2_ADACT (7U) /*!< Bit position for ADC_SC2_ADACT. */
mbed_official 324:406fd2029f23 1096 #define BM_ADC_SC2_ADACT (0x00000080U) /*!< Bit mask for ADC_SC2_ADACT. */
mbed_official 324:406fd2029f23 1097 #define BS_ADC_SC2_ADACT (1U) /*!< Bit field size in bits for ADC_SC2_ADACT. */
mbed_official 324:406fd2029f23 1098
mbed_official 324:406fd2029f23 1099 /*! @brief Read current value of the ADC_SC2_ADACT field. */
mbed_official 324:406fd2029f23 1100 #define BR_ADC_SC2_ADACT(x) (BITBAND_ACCESS32(HW_ADC_SC2_ADDR(x), BP_ADC_SC2_ADACT))
mbed_official 324:406fd2029f23 1101 /*@}*/
mbed_official 324:406fd2029f23 1102
mbed_official 324:406fd2029f23 1103 /*******************************************************************************
mbed_official 324:406fd2029f23 1104 * HW_ADC_SC3 - Status and Control Register 3
mbed_official 324:406fd2029f23 1105 ******************************************************************************/
mbed_official 324:406fd2029f23 1106
mbed_official 324:406fd2029f23 1107 /*!
mbed_official 324:406fd2029f23 1108 * @brief HW_ADC_SC3 - Status and Control Register 3 (RW)
mbed_official 324:406fd2029f23 1109 *
mbed_official 324:406fd2029f23 1110 * Reset value: 0x00000000U
mbed_official 324:406fd2029f23 1111 *
mbed_official 324:406fd2029f23 1112 * The Status and Control Register 3 (SC3) controls the calibration, continuous
mbed_official 324:406fd2029f23 1113 * convert, and hardware averaging functions of the ADC module.
mbed_official 324:406fd2029f23 1114 */
mbed_official 324:406fd2029f23 1115 typedef union _hw_adc_sc3
mbed_official 324:406fd2029f23 1116 {
mbed_official 324:406fd2029f23 1117 uint32_t U;
mbed_official 324:406fd2029f23 1118 struct _hw_adc_sc3_bitfields
mbed_official 324:406fd2029f23 1119 {
mbed_official 324:406fd2029f23 1120 uint32_t AVGS : 2; /*!< [1:0] Hardware Average Select */
mbed_official 324:406fd2029f23 1121 uint32_t AVGE : 1; /*!< [2] Hardware Average Enable */
mbed_official 324:406fd2029f23 1122 uint32_t ADCO : 1; /*!< [3] Continuous Conversion Enable */
mbed_official 324:406fd2029f23 1123 uint32_t RESERVED0 : 2; /*!< [5:4] */
mbed_official 324:406fd2029f23 1124 uint32_t CALF : 1; /*!< [6] Calibration Failed Flag */
mbed_official 324:406fd2029f23 1125 uint32_t CAL : 1; /*!< [7] Calibration */
mbed_official 324:406fd2029f23 1126 uint32_t RESERVED1 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1127 } B;
mbed_official 324:406fd2029f23 1128 } hw_adc_sc3_t;
mbed_official 324:406fd2029f23 1129
mbed_official 324:406fd2029f23 1130 /*!
mbed_official 324:406fd2029f23 1131 * @name Constants and macros for entire ADC_SC3 register
mbed_official 324:406fd2029f23 1132 */
mbed_official 324:406fd2029f23 1133 /*@{*/
mbed_official 324:406fd2029f23 1134 #define HW_ADC_SC3_ADDR(x) ((x) + 0x24U)
mbed_official 324:406fd2029f23 1135
mbed_official 324:406fd2029f23 1136 #define HW_ADC_SC3(x) (*(__IO hw_adc_sc3_t *) HW_ADC_SC3_ADDR(x))
mbed_official 324:406fd2029f23 1137 #define HW_ADC_SC3_RD(x) (HW_ADC_SC3(x).U)
mbed_official 324:406fd2029f23 1138 #define HW_ADC_SC3_WR(x, v) (HW_ADC_SC3(x).U = (v))
mbed_official 324:406fd2029f23 1139 #define HW_ADC_SC3_SET(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) | (v)))
mbed_official 324:406fd2029f23 1140 #define HW_ADC_SC3_CLR(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1141 #define HW_ADC_SC3_TOG(x, v) (HW_ADC_SC3_WR(x, HW_ADC_SC3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1142 /*@}*/
mbed_official 324:406fd2029f23 1143
mbed_official 324:406fd2029f23 1144 /*
mbed_official 324:406fd2029f23 1145 * Constants & macros for individual ADC_SC3 bitfields
mbed_official 324:406fd2029f23 1146 */
mbed_official 324:406fd2029f23 1147
mbed_official 324:406fd2029f23 1148 /*!
mbed_official 324:406fd2029f23 1149 * @name Register ADC_SC3, field AVGS[1:0] (RW)
mbed_official 324:406fd2029f23 1150 *
mbed_official 324:406fd2029f23 1151 * Determines how many ADC conversions will be averaged to create the ADC
mbed_official 324:406fd2029f23 1152 * average result.
mbed_official 324:406fd2029f23 1153 *
mbed_official 324:406fd2029f23 1154 * Values:
mbed_official 324:406fd2029f23 1155 * - 00 - 4 samples averaged.
mbed_official 324:406fd2029f23 1156 * - 01 - 8 samples averaged.
mbed_official 324:406fd2029f23 1157 * - 10 - 16 samples averaged.
mbed_official 324:406fd2029f23 1158 * - 11 - 32 samples averaged.
mbed_official 324:406fd2029f23 1159 */
mbed_official 324:406fd2029f23 1160 /*@{*/
mbed_official 324:406fd2029f23 1161 #define BP_ADC_SC3_AVGS (0U) /*!< Bit position for ADC_SC3_AVGS. */
mbed_official 324:406fd2029f23 1162 #define BM_ADC_SC3_AVGS (0x00000003U) /*!< Bit mask for ADC_SC3_AVGS. */
mbed_official 324:406fd2029f23 1163 #define BS_ADC_SC3_AVGS (2U) /*!< Bit field size in bits for ADC_SC3_AVGS. */
mbed_official 324:406fd2029f23 1164
mbed_official 324:406fd2029f23 1165 /*! @brief Read current value of the ADC_SC3_AVGS field. */
mbed_official 324:406fd2029f23 1166 #define BR_ADC_SC3_AVGS(x) (HW_ADC_SC3(x).B.AVGS)
mbed_official 324:406fd2029f23 1167
mbed_official 324:406fd2029f23 1168 /*! @brief Format value for bitfield ADC_SC3_AVGS. */
mbed_official 324:406fd2029f23 1169 #define BF_ADC_SC3_AVGS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGS) & BM_ADC_SC3_AVGS)
mbed_official 324:406fd2029f23 1170
mbed_official 324:406fd2029f23 1171 /*! @brief Set the AVGS field to a new value. */
mbed_official 324:406fd2029f23 1172 #define BW_ADC_SC3_AVGS(x, v) (HW_ADC_SC3_WR(x, (HW_ADC_SC3_RD(x) & ~BM_ADC_SC3_AVGS) | BF_ADC_SC3_AVGS(v)))
mbed_official 324:406fd2029f23 1173 /*@}*/
mbed_official 324:406fd2029f23 1174
mbed_official 324:406fd2029f23 1175 /*!
mbed_official 324:406fd2029f23 1176 * @name Register ADC_SC3, field AVGE[2] (RW)
mbed_official 324:406fd2029f23 1177 *
mbed_official 324:406fd2029f23 1178 * Enables the hardware average function of the ADC.
mbed_official 324:406fd2029f23 1179 *
mbed_official 324:406fd2029f23 1180 * Values:
mbed_official 324:406fd2029f23 1181 * - 0 - Hardware average function disabled.
mbed_official 324:406fd2029f23 1182 * - 1 - Hardware average function enabled.
mbed_official 324:406fd2029f23 1183 */
mbed_official 324:406fd2029f23 1184 /*@{*/
mbed_official 324:406fd2029f23 1185 #define BP_ADC_SC3_AVGE (2U) /*!< Bit position for ADC_SC3_AVGE. */
mbed_official 324:406fd2029f23 1186 #define BM_ADC_SC3_AVGE (0x00000004U) /*!< Bit mask for ADC_SC3_AVGE. */
mbed_official 324:406fd2029f23 1187 #define BS_ADC_SC3_AVGE (1U) /*!< Bit field size in bits for ADC_SC3_AVGE. */
mbed_official 324:406fd2029f23 1188
mbed_official 324:406fd2029f23 1189 /*! @brief Read current value of the ADC_SC3_AVGE field. */
mbed_official 324:406fd2029f23 1190 #define BR_ADC_SC3_AVGE(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE))
mbed_official 324:406fd2029f23 1191
mbed_official 324:406fd2029f23 1192 /*! @brief Format value for bitfield ADC_SC3_AVGE. */
mbed_official 324:406fd2029f23 1193 #define BF_ADC_SC3_AVGE(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_AVGE) & BM_ADC_SC3_AVGE)
mbed_official 324:406fd2029f23 1194
mbed_official 324:406fd2029f23 1195 /*! @brief Set the AVGE field to a new value. */
mbed_official 324:406fd2029f23 1196 #define BW_ADC_SC3_AVGE(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_AVGE) = (v))
mbed_official 324:406fd2029f23 1197 /*@}*/
mbed_official 324:406fd2029f23 1198
mbed_official 324:406fd2029f23 1199 /*!
mbed_official 324:406fd2029f23 1200 * @name Register ADC_SC3, field ADCO[3] (RW)
mbed_official 324:406fd2029f23 1201 *
mbed_official 324:406fd2029f23 1202 * Enables continuous conversions.
mbed_official 324:406fd2029f23 1203 *
mbed_official 324:406fd2029f23 1204 * Values:
mbed_official 324:406fd2029f23 1205 * - 0 - One conversion or one set of conversions if the hardware average
mbed_official 324:406fd2029f23 1206 * function is enabled, that is, AVGE=1, after initiating a conversion.
mbed_official 324:406fd2029f23 1207 * - 1 - Continuous conversions or sets of conversions if the hardware average
mbed_official 324:406fd2029f23 1208 * function is enabled, that is, AVGE=1, after initiating a conversion.
mbed_official 324:406fd2029f23 1209 */
mbed_official 324:406fd2029f23 1210 /*@{*/
mbed_official 324:406fd2029f23 1211 #define BP_ADC_SC3_ADCO (3U) /*!< Bit position for ADC_SC3_ADCO. */
mbed_official 324:406fd2029f23 1212 #define BM_ADC_SC3_ADCO (0x00000008U) /*!< Bit mask for ADC_SC3_ADCO. */
mbed_official 324:406fd2029f23 1213 #define BS_ADC_SC3_ADCO (1U) /*!< Bit field size in bits for ADC_SC3_ADCO. */
mbed_official 324:406fd2029f23 1214
mbed_official 324:406fd2029f23 1215 /*! @brief Read current value of the ADC_SC3_ADCO field. */
mbed_official 324:406fd2029f23 1216 #define BR_ADC_SC3_ADCO(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO))
mbed_official 324:406fd2029f23 1217
mbed_official 324:406fd2029f23 1218 /*! @brief Format value for bitfield ADC_SC3_ADCO. */
mbed_official 324:406fd2029f23 1219 #define BF_ADC_SC3_ADCO(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_ADCO) & BM_ADC_SC3_ADCO)
mbed_official 324:406fd2029f23 1220
mbed_official 324:406fd2029f23 1221 /*! @brief Set the ADCO field to a new value. */
mbed_official 324:406fd2029f23 1222 #define BW_ADC_SC3_ADCO(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_ADCO) = (v))
mbed_official 324:406fd2029f23 1223 /*@}*/
mbed_official 324:406fd2029f23 1224
mbed_official 324:406fd2029f23 1225 /*!
mbed_official 324:406fd2029f23 1226 * @name Register ADC_SC3, field CALF[6] (RO)
mbed_official 324:406fd2029f23 1227 *
mbed_official 324:406fd2029f23 1228 * Displays the result of the calibration sequence. The calibration sequence
mbed_official 324:406fd2029f23 1229 * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
mbed_official 324:406fd2029f23 1230 * entered before the calibration sequence completes. Writing 1 to CALF clears it.
mbed_official 324:406fd2029f23 1231 *
mbed_official 324:406fd2029f23 1232 * Values:
mbed_official 324:406fd2029f23 1233 * - 0 - Calibration completed normally.
mbed_official 324:406fd2029f23 1234 * - 1 - Calibration failed. ADC accuracy specifications are not guaranteed.
mbed_official 324:406fd2029f23 1235 */
mbed_official 324:406fd2029f23 1236 /*@{*/
mbed_official 324:406fd2029f23 1237 #define BP_ADC_SC3_CALF (6U) /*!< Bit position for ADC_SC3_CALF. */
mbed_official 324:406fd2029f23 1238 #define BM_ADC_SC3_CALF (0x00000040U) /*!< Bit mask for ADC_SC3_CALF. */
mbed_official 324:406fd2029f23 1239 #define BS_ADC_SC3_CALF (1U) /*!< Bit field size in bits for ADC_SC3_CALF. */
mbed_official 324:406fd2029f23 1240
mbed_official 324:406fd2029f23 1241 /*! @brief Read current value of the ADC_SC3_CALF field. */
mbed_official 324:406fd2029f23 1242 #define BR_ADC_SC3_CALF(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CALF))
mbed_official 324:406fd2029f23 1243 /*@}*/
mbed_official 324:406fd2029f23 1244
mbed_official 324:406fd2029f23 1245 /*!
mbed_official 324:406fd2029f23 1246 * @name Register ADC_SC3, field CAL[7] (RW)
mbed_official 324:406fd2029f23 1247 *
mbed_official 324:406fd2029f23 1248 * Begins the calibration sequence when set. This field stays set while the
mbed_official 324:406fd2029f23 1249 * calibration is in progress and is cleared when the calibration sequence is
mbed_official 324:406fd2029f23 1250 * completed. CALF must be checked to determine the result of the calibration sequence.
mbed_official 324:406fd2029f23 1251 * Once started, the calibration routine cannot be interrupted by writes to the
mbed_official 324:406fd2029f23 1252 * ADC registers or the results will be invalid and CALF will set. Setting CAL
mbed_official 324:406fd2029f23 1253 * will abort any current conversion.
mbed_official 324:406fd2029f23 1254 */
mbed_official 324:406fd2029f23 1255 /*@{*/
mbed_official 324:406fd2029f23 1256 #define BP_ADC_SC3_CAL (7U) /*!< Bit position for ADC_SC3_CAL. */
mbed_official 324:406fd2029f23 1257 #define BM_ADC_SC3_CAL (0x00000080U) /*!< Bit mask for ADC_SC3_CAL. */
mbed_official 324:406fd2029f23 1258 #define BS_ADC_SC3_CAL (1U) /*!< Bit field size in bits for ADC_SC3_CAL. */
mbed_official 324:406fd2029f23 1259
mbed_official 324:406fd2029f23 1260 /*! @brief Read current value of the ADC_SC3_CAL field. */
mbed_official 324:406fd2029f23 1261 #define BR_ADC_SC3_CAL(x) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL))
mbed_official 324:406fd2029f23 1262
mbed_official 324:406fd2029f23 1263 /*! @brief Format value for bitfield ADC_SC3_CAL. */
mbed_official 324:406fd2029f23 1264 #define BF_ADC_SC3_CAL(v) ((uint32_t)((uint32_t)(v) << BP_ADC_SC3_CAL) & BM_ADC_SC3_CAL)
mbed_official 324:406fd2029f23 1265
mbed_official 324:406fd2029f23 1266 /*! @brief Set the CAL field to a new value. */
mbed_official 324:406fd2029f23 1267 #define BW_ADC_SC3_CAL(x, v) (BITBAND_ACCESS32(HW_ADC_SC3_ADDR(x), BP_ADC_SC3_CAL) = (v))
mbed_official 324:406fd2029f23 1268 /*@}*/
mbed_official 324:406fd2029f23 1269
mbed_official 324:406fd2029f23 1270 /*******************************************************************************
mbed_official 324:406fd2029f23 1271 * HW_ADC_OFS - ADC Offset Correction Register
mbed_official 324:406fd2029f23 1272 ******************************************************************************/
mbed_official 324:406fd2029f23 1273
mbed_official 324:406fd2029f23 1274 /*!
mbed_official 324:406fd2029f23 1275 * @brief HW_ADC_OFS - ADC Offset Correction Register (RW)
mbed_official 324:406fd2029f23 1276 *
mbed_official 324:406fd2029f23 1277 * Reset value: 0x00000004U
mbed_official 324:406fd2029f23 1278 *
mbed_official 324:406fd2029f23 1279 * The ADC Offset Correction Register (OFS) contains the user-selected or
mbed_official 324:406fd2029f23 1280 * calibration-generated offset error correction value. This register is a 2's
mbed_official 324:406fd2029f23 1281 * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
mbed_official 324:406fd2029f23 1282 * conversion and the result is transferred into the result registers, Rn. If the
mbed_official 324:406fd2029f23 1283 * result is greater than the maximum or less than the minimum result value, it is
mbed_official 324:406fd2029f23 1284 * forced to the appropriate limit for the current mode of operation.
mbed_official 324:406fd2029f23 1285 */
mbed_official 324:406fd2029f23 1286 typedef union _hw_adc_ofs
mbed_official 324:406fd2029f23 1287 {
mbed_official 324:406fd2029f23 1288 uint32_t U;
mbed_official 324:406fd2029f23 1289 struct _hw_adc_ofs_bitfields
mbed_official 324:406fd2029f23 1290 {
mbed_official 324:406fd2029f23 1291 uint32_t OFS : 16; /*!< [15:0] Offset Error Correction Value */
mbed_official 324:406fd2029f23 1292 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 1293 } B;
mbed_official 324:406fd2029f23 1294 } hw_adc_ofs_t;
mbed_official 324:406fd2029f23 1295
mbed_official 324:406fd2029f23 1296 /*!
mbed_official 324:406fd2029f23 1297 * @name Constants and macros for entire ADC_OFS register
mbed_official 324:406fd2029f23 1298 */
mbed_official 324:406fd2029f23 1299 /*@{*/
mbed_official 324:406fd2029f23 1300 #define HW_ADC_OFS_ADDR(x) ((x) + 0x28U)
mbed_official 324:406fd2029f23 1301
mbed_official 324:406fd2029f23 1302 #define HW_ADC_OFS(x) (*(__IO hw_adc_ofs_t *) HW_ADC_OFS_ADDR(x))
mbed_official 324:406fd2029f23 1303 #define HW_ADC_OFS_RD(x) (HW_ADC_OFS(x).U)
mbed_official 324:406fd2029f23 1304 #define HW_ADC_OFS_WR(x, v) (HW_ADC_OFS(x).U = (v))
mbed_official 324:406fd2029f23 1305 #define HW_ADC_OFS_SET(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) | (v)))
mbed_official 324:406fd2029f23 1306 #define HW_ADC_OFS_CLR(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1307 #define HW_ADC_OFS_TOG(x, v) (HW_ADC_OFS_WR(x, HW_ADC_OFS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1308 /*@}*/
mbed_official 324:406fd2029f23 1309
mbed_official 324:406fd2029f23 1310 /*
mbed_official 324:406fd2029f23 1311 * Constants & macros for individual ADC_OFS bitfields
mbed_official 324:406fd2029f23 1312 */
mbed_official 324:406fd2029f23 1313
mbed_official 324:406fd2029f23 1314 /*!
mbed_official 324:406fd2029f23 1315 * @name Register ADC_OFS, field OFS[15:0] (RW)
mbed_official 324:406fd2029f23 1316 */
mbed_official 324:406fd2029f23 1317 /*@{*/
mbed_official 324:406fd2029f23 1318 #define BP_ADC_OFS_OFS (0U) /*!< Bit position for ADC_OFS_OFS. */
mbed_official 324:406fd2029f23 1319 #define BM_ADC_OFS_OFS (0x0000FFFFU) /*!< Bit mask for ADC_OFS_OFS. */
mbed_official 324:406fd2029f23 1320 #define BS_ADC_OFS_OFS (16U) /*!< Bit field size in bits for ADC_OFS_OFS. */
mbed_official 324:406fd2029f23 1321
mbed_official 324:406fd2029f23 1322 /*! @brief Read current value of the ADC_OFS_OFS field. */
mbed_official 324:406fd2029f23 1323 #define BR_ADC_OFS_OFS(x) (HW_ADC_OFS(x).B.OFS)
mbed_official 324:406fd2029f23 1324
mbed_official 324:406fd2029f23 1325 /*! @brief Format value for bitfield ADC_OFS_OFS. */
mbed_official 324:406fd2029f23 1326 #define BF_ADC_OFS_OFS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_OFS_OFS) & BM_ADC_OFS_OFS)
mbed_official 324:406fd2029f23 1327
mbed_official 324:406fd2029f23 1328 /*! @brief Set the OFS field to a new value. */
mbed_official 324:406fd2029f23 1329 #define BW_ADC_OFS_OFS(x, v) (HW_ADC_OFS_WR(x, (HW_ADC_OFS_RD(x) & ~BM_ADC_OFS_OFS) | BF_ADC_OFS_OFS(v)))
mbed_official 324:406fd2029f23 1330 /*@}*/
mbed_official 324:406fd2029f23 1331
mbed_official 324:406fd2029f23 1332 /*******************************************************************************
mbed_official 324:406fd2029f23 1333 * HW_ADC_PG - ADC Plus-Side Gain Register
mbed_official 324:406fd2029f23 1334 ******************************************************************************/
mbed_official 324:406fd2029f23 1335
mbed_official 324:406fd2029f23 1336 /*!
mbed_official 324:406fd2029f23 1337 * @brief HW_ADC_PG - ADC Plus-Side Gain Register (RW)
mbed_official 324:406fd2029f23 1338 *
mbed_official 324:406fd2029f23 1339 * Reset value: 0x00008200U
mbed_official 324:406fd2029f23 1340 *
mbed_official 324:406fd2029f23 1341 * The Plus-Side Gain Register (PG) contains the gain error correction for the
mbed_official 324:406fd2029f23 1342 * plus-side input in differential mode or the overall conversion in single-ended
mbed_official 324:406fd2029f23 1343 * mode. PG, a 16-bit real number in binary format, is the gain adjustment
mbed_official 324:406fd2029f23 1344 * factor, with the radix point fixed between ADPG15 and ADPG14. This register must be
mbed_official 324:406fd2029f23 1345 * written by the user with the value described in the calibration procedure.
mbed_official 324:406fd2029f23 1346 * Otherwise, the gain error specifications may not be met.
mbed_official 324:406fd2029f23 1347 */
mbed_official 324:406fd2029f23 1348 typedef union _hw_adc_pg
mbed_official 324:406fd2029f23 1349 {
mbed_official 324:406fd2029f23 1350 uint32_t U;
mbed_official 324:406fd2029f23 1351 struct _hw_adc_pg_bitfields
mbed_official 324:406fd2029f23 1352 {
mbed_official 324:406fd2029f23 1353 uint32_t PG : 16; /*!< [15:0] Plus-Side Gain */
mbed_official 324:406fd2029f23 1354 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 1355 } B;
mbed_official 324:406fd2029f23 1356 } hw_adc_pg_t;
mbed_official 324:406fd2029f23 1357
mbed_official 324:406fd2029f23 1358 /*!
mbed_official 324:406fd2029f23 1359 * @name Constants and macros for entire ADC_PG register
mbed_official 324:406fd2029f23 1360 */
mbed_official 324:406fd2029f23 1361 /*@{*/
mbed_official 324:406fd2029f23 1362 #define HW_ADC_PG_ADDR(x) ((x) + 0x2CU)
mbed_official 324:406fd2029f23 1363
mbed_official 324:406fd2029f23 1364 #define HW_ADC_PG(x) (*(__IO hw_adc_pg_t *) HW_ADC_PG_ADDR(x))
mbed_official 324:406fd2029f23 1365 #define HW_ADC_PG_RD(x) (HW_ADC_PG(x).U)
mbed_official 324:406fd2029f23 1366 #define HW_ADC_PG_WR(x, v) (HW_ADC_PG(x).U = (v))
mbed_official 324:406fd2029f23 1367 #define HW_ADC_PG_SET(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) | (v)))
mbed_official 324:406fd2029f23 1368 #define HW_ADC_PG_CLR(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1369 #define HW_ADC_PG_TOG(x, v) (HW_ADC_PG_WR(x, HW_ADC_PG_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1370 /*@}*/
mbed_official 324:406fd2029f23 1371
mbed_official 324:406fd2029f23 1372 /*
mbed_official 324:406fd2029f23 1373 * Constants & macros for individual ADC_PG bitfields
mbed_official 324:406fd2029f23 1374 */
mbed_official 324:406fd2029f23 1375
mbed_official 324:406fd2029f23 1376 /*!
mbed_official 324:406fd2029f23 1377 * @name Register ADC_PG, field PG[15:0] (RW)
mbed_official 324:406fd2029f23 1378 */
mbed_official 324:406fd2029f23 1379 /*@{*/
mbed_official 324:406fd2029f23 1380 #define BP_ADC_PG_PG (0U) /*!< Bit position for ADC_PG_PG. */
mbed_official 324:406fd2029f23 1381 #define BM_ADC_PG_PG (0x0000FFFFU) /*!< Bit mask for ADC_PG_PG. */
mbed_official 324:406fd2029f23 1382 #define BS_ADC_PG_PG (16U) /*!< Bit field size in bits for ADC_PG_PG. */
mbed_official 324:406fd2029f23 1383
mbed_official 324:406fd2029f23 1384 /*! @brief Read current value of the ADC_PG_PG field. */
mbed_official 324:406fd2029f23 1385 #define BR_ADC_PG_PG(x) (HW_ADC_PG(x).B.PG)
mbed_official 324:406fd2029f23 1386
mbed_official 324:406fd2029f23 1387 /*! @brief Format value for bitfield ADC_PG_PG. */
mbed_official 324:406fd2029f23 1388 #define BF_ADC_PG_PG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_PG_PG) & BM_ADC_PG_PG)
mbed_official 324:406fd2029f23 1389
mbed_official 324:406fd2029f23 1390 /*! @brief Set the PG field to a new value. */
mbed_official 324:406fd2029f23 1391 #define BW_ADC_PG_PG(x, v) (HW_ADC_PG_WR(x, (HW_ADC_PG_RD(x) & ~BM_ADC_PG_PG) | BF_ADC_PG_PG(v)))
mbed_official 324:406fd2029f23 1392 /*@}*/
mbed_official 324:406fd2029f23 1393
mbed_official 324:406fd2029f23 1394 /*******************************************************************************
mbed_official 324:406fd2029f23 1395 * HW_ADC_MG - ADC Minus-Side Gain Register
mbed_official 324:406fd2029f23 1396 ******************************************************************************/
mbed_official 324:406fd2029f23 1397
mbed_official 324:406fd2029f23 1398 /*!
mbed_official 324:406fd2029f23 1399 * @brief HW_ADC_MG - ADC Minus-Side Gain Register (RW)
mbed_official 324:406fd2029f23 1400 *
mbed_official 324:406fd2029f23 1401 * Reset value: 0x00008200U
mbed_official 324:406fd2029f23 1402 *
mbed_official 324:406fd2029f23 1403 * The Minus-Side Gain Register (MG) contains the gain error correction for the
mbed_official 324:406fd2029f23 1404 * minus-side input in differential mode. This register is ignored in
mbed_official 324:406fd2029f23 1405 * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
mbed_official 324:406fd2029f23 1406 * factor, with the radix point fixed between ADMG15 and ADMG14. This register must
mbed_official 324:406fd2029f23 1407 * be written by the user with the value described in the calibration procedure.
mbed_official 324:406fd2029f23 1408 * Otherwise, the gain error specifications may not be met.
mbed_official 324:406fd2029f23 1409 */
mbed_official 324:406fd2029f23 1410 typedef union _hw_adc_mg
mbed_official 324:406fd2029f23 1411 {
mbed_official 324:406fd2029f23 1412 uint32_t U;
mbed_official 324:406fd2029f23 1413 struct _hw_adc_mg_bitfields
mbed_official 324:406fd2029f23 1414 {
mbed_official 324:406fd2029f23 1415 uint32_t MG : 16; /*!< [15:0] Minus-Side Gain */
mbed_official 324:406fd2029f23 1416 uint32_t RESERVED0 : 16; /*!< [31:16] */
mbed_official 324:406fd2029f23 1417 } B;
mbed_official 324:406fd2029f23 1418 } hw_adc_mg_t;
mbed_official 324:406fd2029f23 1419
mbed_official 324:406fd2029f23 1420 /*!
mbed_official 324:406fd2029f23 1421 * @name Constants and macros for entire ADC_MG register
mbed_official 324:406fd2029f23 1422 */
mbed_official 324:406fd2029f23 1423 /*@{*/
mbed_official 324:406fd2029f23 1424 #define HW_ADC_MG_ADDR(x) ((x) + 0x30U)
mbed_official 324:406fd2029f23 1425
mbed_official 324:406fd2029f23 1426 #define HW_ADC_MG(x) (*(__IO hw_adc_mg_t *) HW_ADC_MG_ADDR(x))
mbed_official 324:406fd2029f23 1427 #define HW_ADC_MG_RD(x) (HW_ADC_MG(x).U)
mbed_official 324:406fd2029f23 1428 #define HW_ADC_MG_WR(x, v) (HW_ADC_MG(x).U = (v))
mbed_official 324:406fd2029f23 1429 #define HW_ADC_MG_SET(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) | (v)))
mbed_official 324:406fd2029f23 1430 #define HW_ADC_MG_CLR(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1431 #define HW_ADC_MG_TOG(x, v) (HW_ADC_MG_WR(x, HW_ADC_MG_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1432 /*@}*/
mbed_official 324:406fd2029f23 1433
mbed_official 324:406fd2029f23 1434 /*
mbed_official 324:406fd2029f23 1435 * Constants & macros for individual ADC_MG bitfields
mbed_official 324:406fd2029f23 1436 */
mbed_official 324:406fd2029f23 1437
mbed_official 324:406fd2029f23 1438 /*!
mbed_official 324:406fd2029f23 1439 * @name Register ADC_MG, field MG[15:0] (RW)
mbed_official 324:406fd2029f23 1440 */
mbed_official 324:406fd2029f23 1441 /*@{*/
mbed_official 324:406fd2029f23 1442 #define BP_ADC_MG_MG (0U) /*!< Bit position for ADC_MG_MG. */
mbed_official 324:406fd2029f23 1443 #define BM_ADC_MG_MG (0x0000FFFFU) /*!< Bit mask for ADC_MG_MG. */
mbed_official 324:406fd2029f23 1444 #define BS_ADC_MG_MG (16U) /*!< Bit field size in bits for ADC_MG_MG. */
mbed_official 324:406fd2029f23 1445
mbed_official 324:406fd2029f23 1446 /*! @brief Read current value of the ADC_MG_MG field. */
mbed_official 324:406fd2029f23 1447 #define BR_ADC_MG_MG(x) (HW_ADC_MG(x).B.MG)
mbed_official 324:406fd2029f23 1448
mbed_official 324:406fd2029f23 1449 /*! @brief Format value for bitfield ADC_MG_MG. */
mbed_official 324:406fd2029f23 1450 #define BF_ADC_MG_MG(v) ((uint32_t)((uint32_t)(v) << BP_ADC_MG_MG) & BM_ADC_MG_MG)
mbed_official 324:406fd2029f23 1451
mbed_official 324:406fd2029f23 1452 /*! @brief Set the MG field to a new value. */
mbed_official 324:406fd2029f23 1453 #define BW_ADC_MG_MG(x, v) (HW_ADC_MG_WR(x, (HW_ADC_MG_RD(x) & ~BM_ADC_MG_MG) | BF_ADC_MG_MG(v)))
mbed_official 324:406fd2029f23 1454 /*@}*/
mbed_official 324:406fd2029f23 1455
mbed_official 324:406fd2029f23 1456 /*******************************************************************************
mbed_official 324:406fd2029f23 1457 * HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1458 ******************************************************************************/
mbed_official 324:406fd2029f23 1459
mbed_official 324:406fd2029f23 1460 /*!
mbed_official 324:406fd2029f23 1461 * @brief HW_ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1462 *
mbed_official 324:406fd2029f23 1463 * Reset value: 0x0000000AU
mbed_official 324:406fd2029f23 1464 *
mbed_official 324:406fd2029f23 1465 * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
mbed_official 324:406fd2029f23 1466 * information that is generated by the calibration function. These registers
mbed_official 324:406fd2029f23 1467 * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
mbed_official 324:406fd2029f23 1468 * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
mbed_official 324:406fd2029f23 1469 * when the self-calibration sequence is done, that is, CAL is cleared. If these
mbed_official 324:406fd2029f23 1470 * registers are written by the user after calibration, the linearity error
mbed_official 324:406fd2029f23 1471 * specifications may not be met.
mbed_official 324:406fd2029f23 1472 */
mbed_official 324:406fd2029f23 1473 typedef union _hw_adc_clpd
mbed_official 324:406fd2029f23 1474 {
mbed_official 324:406fd2029f23 1475 uint32_t U;
mbed_official 324:406fd2029f23 1476 struct _hw_adc_clpd_bitfields
mbed_official 324:406fd2029f23 1477 {
mbed_official 324:406fd2029f23 1478 uint32_t CLPD : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 1479 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 1480 } B;
mbed_official 324:406fd2029f23 1481 } hw_adc_clpd_t;
mbed_official 324:406fd2029f23 1482
mbed_official 324:406fd2029f23 1483 /*!
mbed_official 324:406fd2029f23 1484 * @name Constants and macros for entire ADC_CLPD register
mbed_official 324:406fd2029f23 1485 */
mbed_official 324:406fd2029f23 1486 /*@{*/
mbed_official 324:406fd2029f23 1487 #define HW_ADC_CLPD_ADDR(x) ((x) + 0x34U)
mbed_official 324:406fd2029f23 1488
mbed_official 324:406fd2029f23 1489 #define HW_ADC_CLPD(x) (*(__IO hw_adc_clpd_t *) HW_ADC_CLPD_ADDR(x))
mbed_official 324:406fd2029f23 1490 #define HW_ADC_CLPD_RD(x) (HW_ADC_CLPD(x).U)
mbed_official 324:406fd2029f23 1491 #define HW_ADC_CLPD_WR(x, v) (HW_ADC_CLPD(x).U = (v))
mbed_official 324:406fd2029f23 1492 #define HW_ADC_CLPD_SET(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) | (v)))
mbed_official 324:406fd2029f23 1493 #define HW_ADC_CLPD_CLR(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1494 #define HW_ADC_CLPD_TOG(x, v) (HW_ADC_CLPD_WR(x, HW_ADC_CLPD_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1495 /*@}*/
mbed_official 324:406fd2029f23 1496
mbed_official 324:406fd2029f23 1497 /*
mbed_official 324:406fd2029f23 1498 * Constants & macros for individual ADC_CLPD bitfields
mbed_official 324:406fd2029f23 1499 */
mbed_official 324:406fd2029f23 1500
mbed_official 324:406fd2029f23 1501 /*!
mbed_official 324:406fd2029f23 1502 * @name Register ADC_CLPD, field CLPD[5:0] (RW)
mbed_official 324:406fd2029f23 1503 *
mbed_official 324:406fd2029f23 1504 * Calibration Value
mbed_official 324:406fd2029f23 1505 */
mbed_official 324:406fd2029f23 1506 /*@{*/
mbed_official 324:406fd2029f23 1507 #define BP_ADC_CLPD_CLPD (0U) /*!< Bit position for ADC_CLPD_CLPD. */
mbed_official 324:406fd2029f23 1508 #define BM_ADC_CLPD_CLPD (0x0000003FU) /*!< Bit mask for ADC_CLPD_CLPD. */
mbed_official 324:406fd2029f23 1509 #define BS_ADC_CLPD_CLPD (6U) /*!< Bit field size in bits for ADC_CLPD_CLPD. */
mbed_official 324:406fd2029f23 1510
mbed_official 324:406fd2029f23 1511 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
mbed_official 324:406fd2029f23 1512 #define BR_ADC_CLPD_CLPD(x) (HW_ADC_CLPD(x).B.CLPD)
mbed_official 324:406fd2029f23 1513
mbed_official 324:406fd2029f23 1514 /*! @brief Format value for bitfield ADC_CLPD_CLPD. */
mbed_official 324:406fd2029f23 1515 #define BF_ADC_CLPD_CLPD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPD_CLPD) & BM_ADC_CLPD_CLPD)
mbed_official 324:406fd2029f23 1516
mbed_official 324:406fd2029f23 1517 /*! @brief Set the CLPD field to a new value. */
mbed_official 324:406fd2029f23 1518 #define BW_ADC_CLPD_CLPD(x, v) (HW_ADC_CLPD_WR(x, (HW_ADC_CLPD_RD(x) & ~BM_ADC_CLPD_CLPD) | BF_ADC_CLPD_CLPD(v)))
mbed_official 324:406fd2029f23 1519 /*@}*/
mbed_official 324:406fd2029f23 1520
mbed_official 324:406fd2029f23 1521 /*******************************************************************************
mbed_official 324:406fd2029f23 1522 * HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1523 ******************************************************************************/
mbed_official 324:406fd2029f23 1524
mbed_official 324:406fd2029f23 1525 /*!
mbed_official 324:406fd2029f23 1526 * @brief HW_ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1527 *
mbed_official 324:406fd2029f23 1528 * Reset value: 0x00000020U
mbed_official 324:406fd2029f23 1529 *
mbed_official 324:406fd2029f23 1530 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1531 */
mbed_official 324:406fd2029f23 1532 typedef union _hw_adc_clps
mbed_official 324:406fd2029f23 1533 {
mbed_official 324:406fd2029f23 1534 uint32_t U;
mbed_official 324:406fd2029f23 1535 struct _hw_adc_clps_bitfields
mbed_official 324:406fd2029f23 1536 {
mbed_official 324:406fd2029f23 1537 uint32_t CLPS : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 1538 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 1539 } B;
mbed_official 324:406fd2029f23 1540 } hw_adc_clps_t;
mbed_official 324:406fd2029f23 1541
mbed_official 324:406fd2029f23 1542 /*!
mbed_official 324:406fd2029f23 1543 * @name Constants and macros for entire ADC_CLPS register
mbed_official 324:406fd2029f23 1544 */
mbed_official 324:406fd2029f23 1545 /*@{*/
mbed_official 324:406fd2029f23 1546 #define HW_ADC_CLPS_ADDR(x) ((x) + 0x38U)
mbed_official 324:406fd2029f23 1547
mbed_official 324:406fd2029f23 1548 #define HW_ADC_CLPS(x) (*(__IO hw_adc_clps_t *) HW_ADC_CLPS_ADDR(x))
mbed_official 324:406fd2029f23 1549 #define HW_ADC_CLPS_RD(x) (HW_ADC_CLPS(x).U)
mbed_official 324:406fd2029f23 1550 #define HW_ADC_CLPS_WR(x, v) (HW_ADC_CLPS(x).U = (v))
mbed_official 324:406fd2029f23 1551 #define HW_ADC_CLPS_SET(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) | (v)))
mbed_official 324:406fd2029f23 1552 #define HW_ADC_CLPS_CLR(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1553 #define HW_ADC_CLPS_TOG(x, v) (HW_ADC_CLPS_WR(x, HW_ADC_CLPS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1554 /*@}*/
mbed_official 324:406fd2029f23 1555
mbed_official 324:406fd2029f23 1556 /*
mbed_official 324:406fd2029f23 1557 * Constants & macros for individual ADC_CLPS bitfields
mbed_official 324:406fd2029f23 1558 */
mbed_official 324:406fd2029f23 1559
mbed_official 324:406fd2029f23 1560 /*!
mbed_official 324:406fd2029f23 1561 * @name Register ADC_CLPS, field CLPS[5:0] (RW)
mbed_official 324:406fd2029f23 1562 *
mbed_official 324:406fd2029f23 1563 * Calibration Value
mbed_official 324:406fd2029f23 1564 */
mbed_official 324:406fd2029f23 1565 /*@{*/
mbed_official 324:406fd2029f23 1566 #define BP_ADC_CLPS_CLPS (0U) /*!< Bit position for ADC_CLPS_CLPS. */
mbed_official 324:406fd2029f23 1567 #define BM_ADC_CLPS_CLPS (0x0000003FU) /*!< Bit mask for ADC_CLPS_CLPS. */
mbed_official 324:406fd2029f23 1568 #define BS_ADC_CLPS_CLPS (6U) /*!< Bit field size in bits for ADC_CLPS_CLPS. */
mbed_official 324:406fd2029f23 1569
mbed_official 324:406fd2029f23 1570 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
mbed_official 324:406fd2029f23 1571 #define BR_ADC_CLPS_CLPS(x) (HW_ADC_CLPS(x).B.CLPS)
mbed_official 324:406fd2029f23 1572
mbed_official 324:406fd2029f23 1573 /*! @brief Format value for bitfield ADC_CLPS_CLPS. */
mbed_official 324:406fd2029f23 1574 #define BF_ADC_CLPS_CLPS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLPS_CLPS) & BM_ADC_CLPS_CLPS)
mbed_official 324:406fd2029f23 1575
mbed_official 324:406fd2029f23 1576 /*! @brief Set the CLPS field to a new value. */
mbed_official 324:406fd2029f23 1577 #define BW_ADC_CLPS_CLPS(x, v) (HW_ADC_CLPS_WR(x, (HW_ADC_CLPS_RD(x) & ~BM_ADC_CLPS_CLPS) | BF_ADC_CLPS_CLPS(v)))
mbed_official 324:406fd2029f23 1578 /*@}*/
mbed_official 324:406fd2029f23 1579
mbed_official 324:406fd2029f23 1580 /*******************************************************************************
mbed_official 324:406fd2029f23 1581 * HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1582 ******************************************************************************/
mbed_official 324:406fd2029f23 1583
mbed_official 324:406fd2029f23 1584 /*!
mbed_official 324:406fd2029f23 1585 * @brief HW_ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1586 *
mbed_official 324:406fd2029f23 1587 * Reset value: 0x00000200U
mbed_official 324:406fd2029f23 1588 *
mbed_official 324:406fd2029f23 1589 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1590 */
mbed_official 324:406fd2029f23 1591 typedef union _hw_adc_clp4
mbed_official 324:406fd2029f23 1592 {
mbed_official 324:406fd2029f23 1593 uint32_t U;
mbed_official 324:406fd2029f23 1594 struct _hw_adc_clp4_bitfields
mbed_official 324:406fd2029f23 1595 {
mbed_official 324:406fd2029f23 1596 uint32_t CLP4 : 10; /*!< [9:0] */
mbed_official 324:406fd2029f23 1597 uint32_t RESERVED0 : 22; /*!< [31:10] */
mbed_official 324:406fd2029f23 1598 } B;
mbed_official 324:406fd2029f23 1599 } hw_adc_clp4_t;
mbed_official 324:406fd2029f23 1600
mbed_official 324:406fd2029f23 1601 /*!
mbed_official 324:406fd2029f23 1602 * @name Constants and macros for entire ADC_CLP4 register
mbed_official 324:406fd2029f23 1603 */
mbed_official 324:406fd2029f23 1604 /*@{*/
mbed_official 324:406fd2029f23 1605 #define HW_ADC_CLP4_ADDR(x) ((x) + 0x3CU)
mbed_official 324:406fd2029f23 1606
mbed_official 324:406fd2029f23 1607 #define HW_ADC_CLP4(x) (*(__IO hw_adc_clp4_t *) HW_ADC_CLP4_ADDR(x))
mbed_official 324:406fd2029f23 1608 #define HW_ADC_CLP4_RD(x) (HW_ADC_CLP4(x).U)
mbed_official 324:406fd2029f23 1609 #define HW_ADC_CLP4_WR(x, v) (HW_ADC_CLP4(x).U = (v))
mbed_official 324:406fd2029f23 1610 #define HW_ADC_CLP4_SET(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) | (v)))
mbed_official 324:406fd2029f23 1611 #define HW_ADC_CLP4_CLR(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1612 #define HW_ADC_CLP4_TOG(x, v) (HW_ADC_CLP4_WR(x, HW_ADC_CLP4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1613 /*@}*/
mbed_official 324:406fd2029f23 1614
mbed_official 324:406fd2029f23 1615 /*
mbed_official 324:406fd2029f23 1616 * Constants & macros for individual ADC_CLP4 bitfields
mbed_official 324:406fd2029f23 1617 */
mbed_official 324:406fd2029f23 1618
mbed_official 324:406fd2029f23 1619 /*!
mbed_official 324:406fd2029f23 1620 * @name Register ADC_CLP4, field CLP4[9:0] (RW)
mbed_official 324:406fd2029f23 1621 *
mbed_official 324:406fd2029f23 1622 * Calibration Value
mbed_official 324:406fd2029f23 1623 */
mbed_official 324:406fd2029f23 1624 /*@{*/
mbed_official 324:406fd2029f23 1625 #define BP_ADC_CLP4_CLP4 (0U) /*!< Bit position for ADC_CLP4_CLP4. */
mbed_official 324:406fd2029f23 1626 #define BM_ADC_CLP4_CLP4 (0x000003FFU) /*!< Bit mask for ADC_CLP4_CLP4. */
mbed_official 324:406fd2029f23 1627 #define BS_ADC_CLP4_CLP4 (10U) /*!< Bit field size in bits for ADC_CLP4_CLP4. */
mbed_official 324:406fd2029f23 1628
mbed_official 324:406fd2029f23 1629 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
mbed_official 324:406fd2029f23 1630 #define BR_ADC_CLP4_CLP4(x) (HW_ADC_CLP4(x).B.CLP4)
mbed_official 324:406fd2029f23 1631
mbed_official 324:406fd2029f23 1632 /*! @brief Format value for bitfield ADC_CLP4_CLP4. */
mbed_official 324:406fd2029f23 1633 #define BF_ADC_CLP4_CLP4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP4_CLP4) & BM_ADC_CLP4_CLP4)
mbed_official 324:406fd2029f23 1634
mbed_official 324:406fd2029f23 1635 /*! @brief Set the CLP4 field to a new value. */
mbed_official 324:406fd2029f23 1636 #define BW_ADC_CLP4_CLP4(x, v) (HW_ADC_CLP4_WR(x, (HW_ADC_CLP4_RD(x) & ~BM_ADC_CLP4_CLP4) | BF_ADC_CLP4_CLP4(v)))
mbed_official 324:406fd2029f23 1637 /*@}*/
mbed_official 324:406fd2029f23 1638
mbed_official 324:406fd2029f23 1639 /*******************************************************************************
mbed_official 324:406fd2029f23 1640 * HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1641 ******************************************************************************/
mbed_official 324:406fd2029f23 1642
mbed_official 324:406fd2029f23 1643 /*!
mbed_official 324:406fd2029f23 1644 * @brief HW_ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1645 *
mbed_official 324:406fd2029f23 1646 * Reset value: 0x00000100U
mbed_official 324:406fd2029f23 1647 *
mbed_official 324:406fd2029f23 1648 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1649 */
mbed_official 324:406fd2029f23 1650 typedef union _hw_adc_clp3
mbed_official 324:406fd2029f23 1651 {
mbed_official 324:406fd2029f23 1652 uint32_t U;
mbed_official 324:406fd2029f23 1653 struct _hw_adc_clp3_bitfields
mbed_official 324:406fd2029f23 1654 {
mbed_official 324:406fd2029f23 1655 uint32_t CLP3 : 9; /*!< [8:0] */
mbed_official 324:406fd2029f23 1656 uint32_t RESERVED0 : 23; /*!< [31:9] */
mbed_official 324:406fd2029f23 1657 } B;
mbed_official 324:406fd2029f23 1658 } hw_adc_clp3_t;
mbed_official 324:406fd2029f23 1659
mbed_official 324:406fd2029f23 1660 /*!
mbed_official 324:406fd2029f23 1661 * @name Constants and macros for entire ADC_CLP3 register
mbed_official 324:406fd2029f23 1662 */
mbed_official 324:406fd2029f23 1663 /*@{*/
mbed_official 324:406fd2029f23 1664 #define HW_ADC_CLP3_ADDR(x) ((x) + 0x40U)
mbed_official 324:406fd2029f23 1665
mbed_official 324:406fd2029f23 1666 #define HW_ADC_CLP3(x) (*(__IO hw_adc_clp3_t *) HW_ADC_CLP3_ADDR(x))
mbed_official 324:406fd2029f23 1667 #define HW_ADC_CLP3_RD(x) (HW_ADC_CLP3(x).U)
mbed_official 324:406fd2029f23 1668 #define HW_ADC_CLP3_WR(x, v) (HW_ADC_CLP3(x).U = (v))
mbed_official 324:406fd2029f23 1669 #define HW_ADC_CLP3_SET(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) | (v)))
mbed_official 324:406fd2029f23 1670 #define HW_ADC_CLP3_CLR(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1671 #define HW_ADC_CLP3_TOG(x, v) (HW_ADC_CLP3_WR(x, HW_ADC_CLP3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1672 /*@}*/
mbed_official 324:406fd2029f23 1673
mbed_official 324:406fd2029f23 1674 /*
mbed_official 324:406fd2029f23 1675 * Constants & macros for individual ADC_CLP3 bitfields
mbed_official 324:406fd2029f23 1676 */
mbed_official 324:406fd2029f23 1677
mbed_official 324:406fd2029f23 1678 /*!
mbed_official 324:406fd2029f23 1679 * @name Register ADC_CLP3, field CLP3[8:0] (RW)
mbed_official 324:406fd2029f23 1680 *
mbed_official 324:406fd2029f23 1681 * Calibration Value
mbed_official 324:406fd2029f23 1682 */
mbed_official 324:406fd2029f23 1683 /*@{*/
mbed_official 324:406fd2029f23 1684 #define BP_ADC_CLP3_CLP3 (0U) /*!< Bit position for ADC_CLP3_CLP3. */
mbed_official 324:406fd2029f23 1685 #define BM_ADC_CLP3_CLP3 (0x000001FFU) /*!< Bit mask for ADC_CLP3_CLP3. */
mbed_official 324:406fd2029f23 1686 #define BS_ADC_CLP3_CLP3 (9U) /*!< Bit field size in bits for ADC_CLP3_CLP3. */
mbed_official 324:406fd2029f23 1687
mbed_official 324:406fd2029f23 1688 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
mbed_official 324:406fd2029f23 1689 #define BR_ADC_CLP3_CLP3(x) (HW_ADC_CLP3(x).B.CLP3)
mbed_official 324:406fd2029f23 1690
mbed_official 324:406fd2029f23 1691 /*! @brief Format value for bitfield ADC_CLP3_CLP3. */
mbed_official 324:406fd2029f23 1692 #define BF_ADC_CLP3_CLP3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP3_CLP3) & BM_ADC_CLP3_CLP3)
mbed_official 324:406fd2029f23 1693
mbed_official 324:406fd2029f23 1694 /*! @brief Set the CLP3 field to a new value. */
mbed_official 324:406fd2029f23 1695 #define BW_ADC_CLP3_CLP3(x, v) (HW_ADC_CLP3_WR(x, (HW_ADC_CLP3_RD(x) & ~BM_ADC_CLP3_CLP3) | BF_ADC_CLP3_CLP3(v)))
mbed_official 324:406fd2029f23 1696 /*@}*/
mbed_official 324:406fd2029f23 1697
mbed_official 324:406fd2029f23 1698 /*******************************************************************************
mbed_official 324:406fd2029f23 1699 * HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1700 ******************************************************************************/
mbed_official 324:406fd2029f23 1701
mbed_official 324:406fd2029f23 1702 /*!
mbed_official 324:406fd2029f23 1703 * @brief HW_ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1704 *
mbed_official 324:406fd2029f23 1705 * Reset value: 0x00000080U
mbed_official 324:406fd2029f23 1706 *
mbed_official 324:406fd2029f23 1707 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1708 */
mbed_official 324:406fd2029f23 1709 typedef union _hw_adc_clp2
mbed_official 324:406fd2029f23 1710 {
mbed_official 324:406fd2029f23 1711 uint32_t U;
mbed_official 324:406fd2029f23 1712 struct _hw_adc_clp2_bitfields
mbed_official 324:406fd2029f23 1713 {
mbed_official 324:406fd2029f23 1714 uint32_t CLP2 : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 1715 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 1716 } B;
mbed_official 324:406fd2029f23 1717 } hw_adc_clp2_t;
mbed_official 324:406fd2029f23 1718
mbed_official 324:406fd2029f23 1719 /*!
mbed_official 324:406fd2029f23 1720 * @name Constants and macros for entire ADC_CLP2 register
mbed_official 324:406fd2029f23 1721 */
mbed_official 324:406fd2029f23 1722 /*@{*/
mbed_official 324:406fd2029f23 1723 #define HW_ADC_CLP2_ADDR(x) ((x) + 0x44U)
mbed_official 324:406fd2029f23 1724
mbed_official 324:406fd2029f23 1725 #define HW_ADC_CLP2(x) (*(__IO hw_adc_clp2_t *) HW_ADC_CLP2_ADDR(x))
mbed_official 324:406fd2029f23 1726 #define HW_ADC_CLP2_RD(x) (HW_ADC_CLP2(x).U)
mbed_official 324:406fd2029f23 1727 #define HW_ADC_CLP2_WR(x, v) (HW_ADC_CLP2(x).U = (v))
mbed_official 324:406fd2029f23 1728 #define HW_ADC_CLP2_SET(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) | (v)))
mbed_official 324:406fd2029f23 1729 #define HW_ADC_CLP2_CLR(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1730 #define HW_ADC_CLP2_TOG(x, v) (HW_ADC_CLP2_WR(x, HW_ADC_CLP2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1731 /*@}*/
mbed_official 324:406fd2029f23 1732
mbed_official 324:406fd2029f23 1733 /*
mbed_official 324:406fd2029f23 1734 * Constants & macros for individual ADC_CLP2 bitfields
mbed_official 324:406fd2029f23 1735 */
mbed_official 324:406fd2029f23 1736
mbed_official 324:406fd2029f23 1737 /*!
mbed_official 324:406fd2029f23 1738 * @name Register ADC_CLP2, field CLP2[7:0] (RW)
mbed_official 324:406fd2029f23 1739 *
mbed_official 324:406fd2029f23 1740 * Calibration Value
mbed_official 324:406fd2029f23 1741 */
mbed_official 324:406fd2029f23 1742 /*@{*/
mbed_official 324:406fd2029f23 1743 #define BP_ADC_CLP2_CLP2 (0U) /*!< Bit position for ADC_CLP2_CLP2. */
mbed_official 324:406fd2029f23 1744 #define BM_ADC_CLP2_CLP2 (0x000000FFU) /*!< Bit mask for ADC_CLP2_CLP2. */
mbed_official 324:406fd2029f23 1745 #define BS_ADC_CLP2_CLP2 (8U) /*!< Bit field size in bits for ADC_CLP2_CLP2. */
mbed_official 324:406fd2029f23 1746
mbed_official 324:406fd2029f23 1747 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
mbed_official 324:406fd2029f23 1748 #define BR_ADC_CLP2_CLP2(x) (HW_ADC_CLP2(x).B.CLP2)
mbed_official 324:406fd2029f23 1749
mbed_official 324:406fd2029f23 1750 /*! @brief Format value for bitfield ADC_CLP2_CLP2. */
mbed_official 324:406fd2029f23 1751 #define BF_ADC_CLP2_CLP2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP2_CLP2) & BM_ADC_CLP2_CLP2)
mbed_official 324:406fd2029f23 1752
mbed_official 324:406fd2029f23 1753 /*! @brief Set the CLP2 field to a new value. */
mbed_official 324:406fd2029f23 1754 #define BW_ADC_CLP2_CLP2(x, v) (HW_ADC_CLP2_WR(x, (HW_ADC_CLP2_RD(x) & ~BM_ADC_CLP2_CLP2) | BF_ADC_CLP2_CLP2(v)))
mbed_official 324:406fd2029f23 1755 /*@}*/
mbed_official 324:406fd2029f23 1756
mbed_official 324:406fd2029f23 1757 /*******************************************************************************
mbed_official 324:406fd2029f23 1758 * HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1759 ******************************************************************************/
mbed_official 324:406fd2029f23 1760
mbed_official 324:406fd2029f23 1761 /*!
mbed_official 324:406fd2029f23 1762 * @brief HW_ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1763 *
mbed_official 324:406fd2029f23 1764 * Reset value: 0x00000040U
mbed_official 324:406fd2029f23 1765 *
mbed_official 324:406fd2029f23 1766 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1767 */
mbed_official 324:406fd2029f23 1768 typedef union _hw_adc_clp1
mbed_official 324:406fd2029f23 1769 {
mbed_official 324:406fd2029f23 1770 uint32_t U;
mbed_official 324:406fd2029f23 1771 struct _hw_adc_clp1_bitfields
mbed_official 324:406fd2029f23 1772 {
mbed_official 324:406fd2029f23 1773 uint32_t CLP1 : 7; /*!< [6:0] */
mbed_official 324:406fd2029f23 1774 uint32_t RESERVED0 : 25; /*!< [31:7] */
mbed_official 324:406fd2029f23 1775 } B;
mbed_official 324:406fd2029f23 1776 } hw_adc_clp1_t;
mbed_official 324:406fd2029f23 1777
mbed_official 324:406fd2029f23 1778 /*!
mbed_official 324:406fd2029f23 1779 * @name Constants and macros for entire ADC_CLP1 register
mbed_official 324:406fd2029f23 1780 */
mbed_official 324:406fd2029f23 1781 /*@{*/
mbed_official 324:406fd2029f23 1782 #define HW_ADC_CLP1_ADDR(x) ((x) + 0x48U)
mbed_official 324:406fd2029f23 1783
mbed_official 324:406fd2029f23 1784 #define HW_ADC_CLP1(x) (*(__IO hw_adc_clp1_t *) HW_ADC_CLP1_ADDR(x))
mbed_official 324:406fd2029f23 1785 #define HW_ADC_CLP1_RD(x) (HW_ADC_CLP1(x).U)
mbed_official 324:406fd2029f23 1786 #define HW_ADC_CLP1_WR(x, v) (HW_ADC_CLP1(x).U = (v))
mbed_official 324:406fd2029f23 1787 #define HW_ADC_CLP1_SET(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) | (v)))
mbed_official 324:406fd2029f23 1788 #define HW_ADC_CLP1_CLR(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1789 #define HW_ADC_CLP1_TOG(x, v) (HW_ADC_CLP1_WR(x, HW_ADC_CLP1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1790 /*@}*/
mbed_official 324:406fd2029f23 1791
mbed_official 324:406fd2029f23 1792 /*
mbed_official 324:406fd2029f23 1793 * Constants & macros for individual ADC_CLP1 bitfields
mbed_official 324:406fd2029f23 1794 */
mbed_official 324:406fd2029f23 1795
mbed_official 324:406fd2029f23 1796 /*!
mbed_official 324:406fd2029f23 1797 * @name Register ADC_CLP1, field CLP1[6:0] (RW)
mbed_official 324:406fd2029f23 1798 *
mbed_official 324:406fd2029f23 1799 * Calibration Value
mbed_official 324:406fd2029f23 1800 */
mbed_official 324:406fd2029f23 1801 /*@{*/
mbed_official 324:406fd2029f23 1802 #define BP_ADC_CLP1_CLP1 (0U) /*!< Bit position for ADC_CLP1_CLP1. */
mbed_official 324:406fd2029f23 1803 #define BM_ADC_CLP1_CLP1 (0x0000007FU) /*!< Bit mask for ADC_CLP1_CLP1. */
mbed_official 324:406fd2029f23 1804 #define BS_ADC_CLP1_CLP1 (7U) /*!< Bit field size in bits for ADC_CLP1_CLP1. */
mbed_official 324:406fd2029f23 1805
mbed_official 324:406fd2029f23 1806 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
mbed_official 324:406fd2029f23 1807 #define BR_ADC_CLP1_CLP1(x) (HW_ADC_CLP1(x).B.CLP1)
mbed_official 324:406fd2029f23 1808
mbed_official 324:406fd2029f23 1809 /*! @brief Format value for bitfield ADC_CLP1_CLP1. */
mbed_official 324:406fd2029f23 1810 #define BF_ADC_CLP1_CLP1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP1_CLP1) & BM_ADC_CLP1_CLP1)
mbed_official 324:406fd2029f23 1811
mbed_official 324:406fd2029f23 1812 /*! @brief Set the CLP1 field to a new value. */
mbed_official 324:406fd2029f23 1813 #define BW_ADC_CLP1_CLP1(x, v) (HW_ADC_CLP1_WR(x, (HW_ADC_CLP1_RD(x) & ~BM_ADC_CLP1_CLP1) | BF_ADC_CLP1_CLP1(v)))
mbed_official 324:406fd2029f23 1814 /*@}*/
mbed_official 324:406fd2029f23 1815
mbed_official 324:406fd2029f23 1816 /*******************************************************************************
mbed_official 324:406fd2029f23 1817 * HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1818 ******************************************************************************/
mbed_official 324:406fd2029f23 1819
mbed_official 324:406fd2029f23 1820 /*!
mbed_official 324:406fd2029f23 1821 * @brief HW_ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1822 *
mbed_official 324:406fd2029f23 1823 * Reset value: 0x00000020U
mbed_official 324:406fd2029f23 1824 *
mbed_official 324:406fd2029f23 1825 * For more information, see CLPD register description.
mbed_official 324:406fd2029f23 1826 */
mbed_official 324:406fd2029f23 1827 typedef union _hw_adc_clp0
mbed_official 324:406fd2029f23 1828 {
mbed_official 324:406fd2029f23 1829 uint32_t U;
mbed_official 324:406fd2029f23 1830 struct _hw_adc_clp0_bitfields
mbed_official 324:406fd2029f23 1831 {
mbed_official 324:406fd2029f23 1832 uint32_t CLP0 : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 1833 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 1834 } B;
mbed_official 324:406fd2029f23 1835 } hw_adc_clp0_t;
mbed_official 324:406fd2029f23 1836
mbed_official 324:406fd2029f23 1837 /*!
mbed_official 324:406fd2029f23 1838 * @name Constants and macros for entire ADC_CLP0 register
mbed_official 324:406fd2029f23 1839 */
mbed_official 324:406fd2029f23 1840 /*@{*/
mbed_official 324:406fd2029f23 1841 #define HW_ADC_CLP0_ADDR(x) ((x) + 0x4CU)
mbed_official 324:406fd2029f23 1842
mbed_official 324:406fd2029f23 1843 #define HW_ADC_CLP0(x) (*(__IO hw_adc_clp0_t *) HW_ADC_CLP0_ADDR(x))
mbed_official 324:406fd2029f23 1844 #define HW_ADC_CLP0_RD(x) (HW_ADC_CLP0(x).U)
mbed_official 324:406fd2029f23 1845 #define HW_ADC_CLP0_WR(x, v) (HW_ADC_CLP0(x).U = (v))
mbed_official 324:406fd2029f23 1846 #define HW_ADC_CLP0_SET(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) | (v)))
mbed_official 324:406fd2029f23 1847 #define HW_ADC_CLP0_CLR(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1848 #define HW_ADC_CLP0_TOG(x, v) (HW_ADC_CLP0_WR(x, HW_ADC_CLP0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1849 /*@}*/
mbed_official 324:406fd2029f23 1850
mbed_official 324:406fd2029f23 1851 /*
mbed_official 324:406fd2029f23 1852 * Constants & macros for individual ADC_CLP0 bitfields
mbed_official 324:406fd2029f23 1853 */
mbed_official 324:406fd2029f23 1854
mbed_official 324:406fd2029f23 1855 /*!
mbed_official 324:406fd2029f23 1856 * @name Register ADC_CLP0, field CLP0[5:0] (RW)
mbed_official 324:406fd2029f23 1857 *
mbed_official 324:406fd2029f23 1858 * Calibration Value
mbed_official 324:406fd2029f23 1859 */
mbed_official 324:406fd2029f23 1860 /*@{*/
mbed_official 324:406fd2029f23 1861 #define BP_ADC_CLP0_CLP0 (0U) /*!< Bit position for ADC_CLP0_CLP0. */
mbed_official 324:406fd2029f23 1862 #define BM_ADC_CLP0_CLP0 (0x0000003FU) /*!< Bit mask for ADC_CLP0_CLP0. */
mbed_official 324:406fd2029f23 1863 #define BS_ADC_CLP0_CLP0 (6U) /*!< Bit field size in bits for ADC_CLP0_CLP0. */
mbed_official 324:406fd2029f23 1864
mbed_official 324:406fd2029f23 1865 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
mbed_official 324:406fd2029f23 1866 #define BR_ADC_CLP0_CLP0(x) (HW_ADC_CLP0(x).B.CLP0)
mbed_official 324:406fd2029f23 1867
mbed_official 324:406fd2029f23 1868 /*! @brief Format value for bitfield ADC_CLP0_CLP0. */
mbed_official 324:406fd2029f23 1869 #define BF_ADC_CLP0_CLP0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLP0_CLP0) & BM_ADC_CLP0_CLP0)
mbed_official 324:406fd2029f23 1870
mbed_official 324:406fd2029f23 1871 /*! @brief Set the CLP0 field to a new value. */
mbed_official 324:406fd2029f23 1872 #define BW_ADC_CLP0_CLP0(x, v) (HW_ADC_CLP0_WR(x, (HW_ADC_CLP0_RD(x) & ~BM_ADC_CLP0_CLP0) | BF_ADC_CLP0_CLP0(v)))
mbed_official 324:406fd2029f23 1873 /*@}*/
mbed_official 324:406fd2029f23 1874
mbed_official 324:406fd2029f23 1875 /*******************************************************************************
mbed_official 324:406fd2029f23 1876 * HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1877 ******************************************************************************/
mbed_official 324:406fd2029f23 1878
mbed_official 324:406fd2029f23 1879 /*!
mbed_official 324:406fd2029f23 1880 * @brief HW_ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1881 *
mbed_official 324:406fd2029f23 1882 * Reset value: 0x0000000AU
mbed_official 324:406fd2029f23 1883 *
mbed_official 324:406fd2029f23 1884 * The Minus-Side General Calibration Value (CLMx) registers contain calibration
mbed_official 324:406fd2029f23 1885 * information that is generated by the calibration function. These registers
mbed_official 324:406fd2029f23 1886 * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
mbed_official 324:406fd2029f23 1887 * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
mbed_official 324:406fd2029f23 1888 * set when the self-calibration sequence is done, that is, CAL is cleared. If
mbed_official 324:406fd2029f23 1889 * these registers are written by the user after calibration, the linearity error
mbed_official 324:406fd2029f23 1890 * specifications may not be met.
mbed_official 324:406fd2029f23 1891 */
mbed_official 324:406fd2029f23 1892 typedef union _hw_adc_clmd
mbed_official 324:406fd2029f23 1893 {
mbed_official 324:406fd2029f23 1894 uint32_t U;
mbed_official 324:406fd2029f23 1895 struct _hw_adc_clmd_bitfields
mbed_official 324:406fd2029f23 1896 {
mbed_official 324:406fd2029f23 1897 uint32_t CLMD : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 1898 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 1899 } B;
mbed_official 324:406fd2029f23 1900 } hw_adc_clmd_t;
mbed_official 324:406fd2029f23 1901
mbed_official 324:406fd2029f23 1902 /*!
mbed_official 324:406fd2029f23 1903 * @name Constants and macros for entire ADC_CLMD register
mbed_official 324:406fd2029f23 1904 */
mbed_official 324:406fd2029f23 1905 /*@{*/
mbed_official 324:406fd2029f23 1906 #define HW_ADC_CLMD_ADDR(x) ((x) + 0x54U)
mbed_official 324:406fd2029f23 1907
mbed_official 324:406fd2029f23 1908 #define HW_ADC_CLMD(x) (*(__IO hw_adc_clmd_t *) HW_ADC_CLMD_ADDR(x))
mbed_official 324:406fd2029f23 1909 #define HW_ADC_CLMD_RD(x) (HW_ADC_CLMD(x).U)
mbed_official 324:406fd2029f23 1910 #define HW_ADC_CLMD_WR(x, v) (HW_ADC_CLMD(x).U = (v))
mbed_official 324:406fd2029f23 1911 #define HW_ADC_CLMD_SET(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) | (v)))
mbed_official 324:406fd2029f23 1912 #define HW_ADC_CLMD_CLR(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1913 #define HW_ADC_CLMD_TOG(x, v) (HW_ADC_CLMD_WR(x, HW_ADC_CLMD_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1914 /*@}*/
mbed_official 324:406fd2029f23 1915
mbed_official 324:406fd2029f23 1916 /*
mbed_official 324:406fd2029f23 1917 * Constants & macros for individual ADC_CLMD bitfields
mbed_official 324:406fd2029f23 1918 */
mbed_official 324:406fd2029f23 1919
mbed_official 324:406fd2029f23 1920 /*!
mbed_official 324:406fd2029f23 1921 * @name Register ADC_CLMD, field CLMD[5:0] (RW)
mbed_official 324:406fd2029f23 1922 *
mbed_official 324:406fd2029f23 1923 * Calibration Value
mbed_official 324:406fd2029f23 1924 */
mbed_official 324:406fd2029f23 1925 /*@{*/
mbed_official 324:406fd2029f23 1926 #define BP_ADC_CLMD_CLMD (0U) /*!< Bit position for ADC_CLMD_CLMD. */
mbed_official 324:406fd2029f23 1927 #define BM_ADC_CLMD_CLMD (0x0000003FU) /*!< Bit mask for ADC_CLMD_CLMD. */
mbed_official 324:406fd2029f23 1928 #define BS_ADC_CLMD_CLMD (6U) /*!< Bit field size in bits for ADC_CLMD_CLMD. */
mbed_official 324:406fd2029f23 1929
mbed_official 324:406fd2029f23 1930 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
mbed_official 324:406fd2029f23 1931 #define BR_ADC_CLMD_CLMD(x) (HW_ADC_CLMD(x).B.CLMD)
mbed_official 324:406fd2029f23 1932
mbed_official 324:406fd2029f23 1933 /*! @brief Format value for bitfield ADC_CLMD_CLMD. */
mbed_official 324:406fd2029f23 1934 #define BF_ADC_CLMD_CLMD(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMD_CLMD) & BM_ADC_CLMD_CLMD)
mbed_official 324:406fd2029f23 1935
mbed_official 324:406fd2029f23 1936 /*! @brief Set the CLMD field to a new value. */
mbed_official 324:406fd2029f23 1937 #define BW_ADC_CLMD_CLMD(x, v) (HW_ADC_CLMD_WR(x, (HW_ADC_CLMD_RD(x) & ~BM_ADC_CLMD_CLMD) | BF_ADC_CLMD_CLMD(v)))
mbed_official 324:406fd2029f23 1938 /*@}*/
mbed_official 324:406fd2029f23 1939
mbed_official 324:406fd2029f23 1940 /*******************************************************************************
mbed_official 324:406fd2029f23 1941 * HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 1942 ******************************************************************************/
mbed_official 324:406fd2029f23 1943
mbed_official 324:406fd2029f23 1944 /*!
mbed_official 324:406fd2029f23 1945 * @brief HW_ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 1946 *
mbed_official 324:406fd2029f23 1947 * Reset value: 0x00000020U
mbed_official 324:406fd2029f23 1948 *
mbed_official 324:406fd2029f23 1949 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 1950 */
mbed_official 324:406fd2029f23 1951 typedef union _hw_adc_clms
mbed_official 324:406fd2029f23 1952 {
mbed_official 324:406fd2029f23 1953 uint32_t U;
mbed_official 324:406fd2029f23 1954 struct _hw_adc_clms_bitfields
mbed_official 324:406fd2029f23 1955 {
mbed_official 324:406fd2029f23 1956 uint32_t CLMS : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 1957 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 1958 } B;
mbed_official 324:406fd2029f23 1959 } hw_adc_clms_t;
mbed_official 324:406fd2029f23 1960
mbed_official 324:406fd2029f23 1961 /*!
mbed_official 324:406fd2029f23 1962 * @name Constants and macros for entire ADC_CLMS register
mbed_official 324:406fd2029f23 1963 */
mbed_official 324:406fd2029f23 1964 /*@{*/
mbed_official 324:406fd2029f23 1965 #define HW_ADC_CLMS_ADDR(x) ((x) + 0x58U)
mbed_official 324:406fd2029f23 1966
mbed_official 324:406fd2029f23 1967 #define HW_ADC_CLMS(x) (*(__IO hw_adc_clms_t *) HW_ADC_CLMS_ADDR(x))
mbed_official 324:406fd2029f23 1968 #define HW_ADC_CLMS_RD(x) (HW_ADC_CLMS(x).U)
mbed_official 324:406fd2029f23 1969 #define HW_ADC_CLMS_WR(x, v) (HW_ADC_CLMS(x).U = (v))
mbed_official 324:406fd2029f23 1970 #define HW_ADC_CLMS_SET(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) | (v)))
mbed_official 324:406fd2029f23 1971 #define HW_ADC_CLMS_CLR(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 1972 #define HW_ADC_CLMS_TOG(x, v) (HW_ADC_CLMS_WR(x, HW_ADC_CLMS_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 1973 /*@}*/
mbed_official 324:406fd2029f23 1974
mbed_official 324:406fd2029f23 1975 /*
mbed_official 324:406fd2029f23 1976 * Constants & macros for individual ADC_CLMS bitfields
mbed_official 324:406fd2029f23 1977 */
mbed_official 324:406fd2029f23 1978
mbed_official 324:406fd2029f23 1979 /*!
mbed_official 324:406fd2029f23 1980 * @name Register ADC_CLMS, field CLMS[5:0] (RW)
mbed_official 324:406fd2029f23 1981 *
mbed_official 324:406fd2029f23 1982 * Calibration Value
mbed_official 324:406fd2029f23 1983 */
mbed_official 324:406fd2029f23 1984 /*@{*/
mbed_official 324:406fd2029f23 1985 #define BP_ADC_CLMS_CLMS (0U) /*!< Bit position for ADC_CLMS_CLMS. */
mbed_official 324:406fd2029f23 1986 #define BM_ADC_CLMS_CLMS (0x0000003FU) /*!< Bit mask for ADC_CLMS_CLMS. */
mbed_official 324:406fd2029f23 1987 #define BS_ADC_CLMS_CLMS (6U) /*!< Bit field size in bits for ADC_CLMS_CLMS. */
mbed_official 324:406fd2029f23 1988
mbed_official 324:406fd2029f23 1989 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
mbed_official 324:406fd2029f23 1990 #define BR_ADC_CLMS_CLMS(x) (HW_ADC_CLMS(x).B.CLMS)
mbed_official 324:406fd2029f23 1991
mbed_official 324:406fd2029f23 1992 /*! @brief Format value for bitfield ADC_CLMS_CLMS. */
mbed_official 324:406fd2029f23 1993 #define BF_ADC_CLMS_CLMS(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLMS_CLMS) & BM_ADC_CLMS_CLMS)
mbed_official 324:406fd2029f23 1994
mbed_official 324:406fd2029f23 1995 /*! @brief Set the CLMS field to a new value. */
mbed_official 324:406fd2029f23 1996 #define BW_ADC_CLMS_CLMS(x, v) (HW_ADC_CLMS_WR(x, (HW_ADC_CLMS_RD(x) & ~BM_ADC_CLMS_CLMS) | BF_ADC_CLMS_CLMS(v)))
mbed_official 324:406fd2029f23 1997 /*@}*/
mbed_official 324:406fd2029f23 1998
mbed_official 324:406fd2029f23 1999 /*******************************************************************************
mbed_official 324:406fd2029f23 2000 * HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 2001 ******************************************************************************/
mbed_official 324:406fd2029f23 2002
mbed_official 324:406fd2029f23 2003 /*!
mbed_official 324:406fd2029f23 2004 * @brief HW_ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 2005 *
mbed_official 324:406fd2029f23 2006 * Reset value: 0x00000200U
mbed_official 324:406fd2029f23 2007 *
mbed_official 324:406fd2029f23 2008 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 2009 */
mbed_official 324:406fd2029f23 2010 typedef union _hw_adc_clm4
mbed_official 324:406fd2029f23 2011 {
mbed_official 324:406fd2029f23 2012 uint32_t U;
mbed_official 324:406fd2029f23 2013 struct _hw_adc_clm4_bitfields
mbed_official 324:406fd2029f23 2014 {
mbed_official 324:406fd2029f23 2015 uint32_t CLM4 : 10; /*!< [9:0] */
mbed_official 324:406fd2029f23 2016 uint32_t RESERVED0 : 22; /*!< [31:10] */
mbed_official 324:406fd2029f23 2017 } B;
mbed_official 324:406fd2029f23 2018 } hw_adc_clm4_t;
mbed_official 324:406fd2029f23 2019
mbed_official 324:406fd2029f23 2020 /*!
mbed_official 324:406fd2029f23 2021 * @name Constants and macros for entire ADC_CLM4 register
mbed_official 324:406fd2029f23 2022 */
mbed_official 324:406fd2029f23 2023 /*@{*/
mbed_official 324:406fd2029f23 2024 #define HW_ADC_CLM4_ADDR(x) ((x) + 0x5CU)
mbed_official 324:406fd2029f23 2025
mbed_official 324:406fd2029f23 2026 #define HW_ADC_CLM4(x) (*(__IO hw_adc_clm4_t *) HW_ADC_CLM4_ADDR(x))
mbed_official 324:406fd2029f23 2027 #define HW_ADC_CLM4_RD(x) (HW_ADC_CLM4(x).U)
mbed_official 324:406fd2029f23 2028 #define HW_ADC_CLM4_WR(x, v) (HW_ADC_CLM4(x).U = (v))
mbed_official 324:406fd2029f23 2029 #define HW_ADC_CLM4_SET(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) | (v)))
mbed_official 324:406fd2029f23 2030 #define HW_ADC_CLM4_CLR(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2031 #define HW_ADC_CLM4_TOG(x, v) (HW_ADC_CLM4_WR(x, HW_ADC_CLM4_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2032 /*@}*/
mbed_official 324:406fd2029f23 2033
mbed_official 324:406fd2029f23 2034 /*
mbed_official 324:406fd2029f23 2035 * Constants & macros for individual ADC_CLM4 bitfields
mbed_official 324:406fd2029f23 2036 */
mbed_official 324:406fd2029f23 2037
mbed_official 324:406fd2029f23 2038 /*!
mbed_official 324:406fd2029f23 2039 * @name Register ADC_CLM4, field CLM4[9:0] (RW)
mbed_official 324:406fd2029f23 2040 *
mbed_official 324:406fd2029f23 2041 * Calibration Value
mbed_official 324:406fd2029f23 2042 */
mbed_official 324:406fd2029f23 2043 /*@{*/
mbed_official 324:406fd2029f23 2044 #define BP_ADC_CLM4_CLM4 (0U) /*!< Bit position for ADC_CLM4_CLM4. */
mbed_official 324:406fd2029f23 2045 #define BM_ADC_CLM4_CLM4 (0x000003FFU) /*!< Bit mask for ADC_CLM4_CLM4. */
mbed_official 324:406fd2029f23 2046 #define BS_ADC_CLM4_CLM4 (10U) /*!< Bit field size in bits for ADC_CLM4_CLM4. */
mbed_official 324:406fd2029f23 2047
mbed_official 324:406fd2029f23 2048 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
mbed_official 324:406fd2029f23 2049 #define BR_ADC_CLM4_CLM4(x) (HW_ADC_CLM4(x).B.CLM4)
mbed_official 324:406fd2029f23 2050
mbed_official 324:406fd2029f23 2051 /*! @brief Format value for bitfield ADC_CLM4_CLM4. */
mbed_official 324:406fd2029f23 2052 #define BF_ADC_CLM4_CLM4(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM4_CLM4) & BM_ADC_CLM4_CLM4)
mbed_official 324:406fd2029f23 2053
mbed_official 324:406fd2029f23 2054 /*! @brief Set the CLM4 field to a new value. */
mbed_official 324:406fd2029f23 2055 #define BW_ADC_CLM4_CLM4(x, v) (HW_ADC_CLM4_WR(x, (HW_ADC_CLM4_RD(x) & ~BM_ADC_CLM4_CLM4) | BF_ADC_CLM4_CLM4(v)))
mbed_official 324:406fd2029f23 2056 /*@}*/
mbed_official 324:406fd2029f23 2057
mbed_official 324:406fd2029f23 2058 /*******************************************************************************
mbed_official 324:406fd2029f23 2059 * HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 2060 ******************************************************************************/
mbed_official 324:406fd2029f23 2061
mbed_official 324:406fd2029f23 2062 /*!
mbed_official 324:406fd2029f23 2063 * @brief HW_ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 2064 *
mbed_official 324:406fd2029f23 2065 * Reset value: 0x00000100U
mbed_official 324:406fd2029f23 2066 *
mbed_official 324:406fd2029f23 2067 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 2068 */
mbed_official 324:406fd2029f23 2069 typedef union _hw_adc_clm3
mbed_official 324:406fd2029f23 2070 {
mbed_official 324:406fd2029f23 2071 uint32_t U;
mbed_official 324:406fd2029f23 2072 struct _hw_adc_clm3_bitfields
mbed_official 324:406fd2029f23 2073 {
mbed_official 324:406fd2029f23 2074 uint32_t CLM3 : 9; /*!< [8:0] */
mbed_official 324:406fd2029f23 2075 uint32_t RESERVED0 : 23; /*!< [31:9] */
mbed_official 324:406fd2029f23 2076 } B;
mbed_official 324:406fd2029f23 2077 } hw_adc_clm3_t;
mbed_official 324:406fd2029f23 2078
mbed_official 324:406fd2029f23 2079 /*!
mbed_official 324:406fd2029f23 2080 * @name Constants and macros for entire ADC_CLM3 register
mbed_official 324:406fd2029f23 2081 */
mbed_official 324:406fd2029f23 2082 /*@{*/
mbed_official 324:406fd2029f23 2083 #define HW_ADC_CLM3_ADDR(x) ((x) + 0x60U)
mbed_official 324:406fd2029f23 2084
mbed_official 324:406fd2029f23 2085 #define HW_ADC_CLM3(x) (*(__IO hw_adc_clm3_t *) HW_ADC_CLM3_ADDR(x))
mbed_official 324:406fd2029f23 2086 #define HW_ADC_CLM3_RD(x) (HW_ADC_CLM3(x).U)
mbed_official 324:406fd2029f23 2087 #define HW_ADC_CLM3_WR(x, v) (HW_ADC_CLM3(x).U = (v))
mbed_official 324:406fd2029f23 2088 #define HW_ADC_CLM3_SET(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) | (v)))
mbed_official 324:406fd2029f23 2089 #define HW_ADC_CLM3_CLR(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2090 #define HW_ADC_CLM3_TOG(x, v) (HW_ADC_CLM3_WR(x, HW_ADC_CLM3_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2091 /*@}*/
mbed_official 324:406fd2029f23 2092
mbed_official 324:406fd2029f23 2093 /*
mbed_official 324:406fd2029f23 2094 * Constants & macros for individual ADC_CLM3 bitfields
mbed_official 324:406fd2029f23 2095 */
mbed_official 324:406fd2029f23 2096
mbed_official 324:406fd2029f23 2097 /*!
mbed_official 324:406fd2029f23 2098 * @name Register ADC_CLM3, field CLM3[8:0] (RW)
mbed_official 324:406fd2029f23 2099 *
mbed_official 324:406fd2029f23 2100 * Calibration Value
mbed_official 324:406fd2029f23 2101 */
mbed_official 324:406fd2029f23 2102 /*@{*/
mbed_official 324:406fd2029f23 2103 #define BP_ADC_CLM3_CLM3 (0U) /*!< Bit position for ADC_CLM3_CLM3. */
mbed_official 324:406fd2029f23 2104 #define BM_ADC_CLM3_CLM3 (0x000001FFU) /*!< Bit mask for ADC_CLM3_CLM3. */
mbed_official 324:406fd2029f23 2105 #define BS_ADC_CLM3_CLM3 (9U) /*!< Bit field size in bits for ADC_CLM3_CLM3. */
mbed_official 324:406fd2029f23 2106
mbed_official 324:406fd2029f23 2107 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
mbed_official 324:406fd2029f23 2108 #define BR_ADC_CLM3_CLM3(x) (HW_ADC_CLM3(x).B.CLM3)
mbed_official 324:406fd2029f23 2109
mbed_official 324:406fd2029f23 2110 /*! @brief Format value for bitfield ADC_CLM3_CLM3. */
mbed_official 324:406fd2029f23 2111 #define BF_ADC_CLM3_CLM3(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM3_CLM3) & BM_ADC_CLM3_CLM3)
mbed_official 324:406fd2029f23 2112
mbed_official 324:406fd2029f23 2113 /*! @brief Set the CLM3 field to a new value. */
mbed_official 324:406fd2029f23 2114 #define BW_ADC_CLM3_CLM3(x, v) (HW_ADC_CLM3_WR(x, (HW_ADC_CLM3_RD(x) & ~BM_ADC_CLM3_CLM3) | BF_ADC_CLM3_CLM3(v)))
mbed_official 324:406fd2029f23 2115 /*@}*/
mbed_official 324:406fd2029f23 2116
mbed_official 324:406fd2029f23 2117 /*******************************************************************************
mbed_official 324:406fd2029f23 2118 * HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 2119 ******************************************************************************/
mbed_official 324:406fd2029f23 2120
mbed_official 324:406fd2029f23 2121 /*!
mbed_official 324:406fd2029f23 2122 * @brief HW_ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 2123 *
mbed_official 324:406fd2029f23 2124 * Reset value: 0x00000080U
mbed_official 324:406fd2029f23 2125 *
mbed_official 324:406fd2029f23 2126 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 2127 */
mbed_official 324:406fd2029f23 2128 typedef union _hw_adc_clm2
mbed_official 324:406fd2029f23 2129 {
mbed_official 324:406fd2029f23 2130 uint32_t U;
mbed_official 324:406fd2029f23 2131 struct _hw_adc_clm2_bitfields
mbed_official 324:406fd2029f23 2132 {
mbed_official 324:406fd2029f23 2133 uint32_t CLM2 : 8; /*!< [7:0] */
mbed_official 324:406fd2029f23 2134 uint32_t RESERVED0 : 24; /*!< [31:8] */
mbed_official 324:406fd2029f23 2135 } B;
mbed_official 324:406fd2029f23 2136 } hw_adc_clm2_t;
mbed_official 324:406fd2029f23 2137
mbed_official 324:406fd2029f23 2138 /*!
mbed_official 324:406fd2029f23 2139 * @name Constants and macros for entire ADC_CLM2 register
mbed_official 324:406fd2029f23 2140 */
mbed_official 324:406fd2029f23 2141 /*@{*/
mbed_official 324:406fd2029f23 2142 #define HW_ADC_CLM2_ADDR(x) ((x) + 0x64U)
mbed_official 324:406fd2029f23 2143
mbed_official 324:406fd2029f23 2144 #define HW_ADC_CLM2(x) (*(__IO hw_adc_clm2_t *) HW_ADC_CLM2_ADDR(x))
mbed_official 324:406fd2029f23 2145 #define HW_ADC_CLM2_RD(x) (HW_ADC_CLM2(x).U)
mbed_official 324:406fd2029f23 2146 #define HW_ADC_CLM2_WR(x, v) (HW_ADC_CLM2(x).U = (v))
mbed_official 324:406fd2029f23 2147 #define HW_ADC_CLM2_SET(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) | (v)))
mbed_official 324:406fd2029f23 2148 #define HW_ADC_CLM2_CLR(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2149 #define HW_ADC_CLM2_TOG(x, v) (HW_ADC_CLM2_WR(x, HW_ADC_CLM2_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2150 /*@}*/
mbed_official 324:406fd2029f23 2151
mbed_official 324:406fd2029f23 2152 /*
mbed_official 324:406fd2029f23 2153 * Constants & macros for individual ADC_CLM2 bitfields
mbed_official 324:406fd2029f23 2154 */
mbed_official 324:406fd2029f23 2155
mbed_official 324:406fd2029f23 2156 /*!
mbed_official 324:406fd2029f23 2157 * @name Register ADC_CLM2, field CLM2[7:0] (RW)
mbed_official 324:406fd2029f23 2158 *
mbed_official 324:406fd2029f23 2159 * Calibration Value
mbed_official 324:406fd2029f23 2160 */
mbed_official 324:406fd2029f23 2161 /*@{*/
mbed_official 324:406fd2029f23 2162 #define BP_ADC_CLM2_CLM2 (0U) /*!< Bit position for ADC_CLM2_CLM2. */
mbed_official 324:406fd2029f23 2163 #define BM_ADC_CLM2_CLM2 (0x000000FFU) /*!< Bit mask for ADC_CLM2_CLM2. */
mbed_official 324:406fd2029f23 2164 #define BS_ADC_CLM2_CLM2 (8U) /*!< Bit field size in bits for ADC_CLM2_CLM2. */
mbed_official 324:406fd2029f23 2165
mbed_official 324:406fd2029f23 2166 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
mbed_official 324:406fd2029f23 2167 #define BR_ADC_CLM2_CLM2(x) (HW_ADC_CLM2(x).B.CLM2)
mbed_official 324:406fd2029f23 2168
mbed_official 324:406fd2029f23 2169 /*! @brief Format value for bitfield ADC_CLM2_CLM2. */
mbed_official 324:406fd2029f23 2170 #define BF_ADC_CLM2_CLM2(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM2_CLM2) & BM_ADC_CLM2_CLM2)
mbed_official 324:406fd2029f23 2171
mbed_official 324:406fd2029f23 2172 /*! @brief Set the CLM2 field to a new value. */
mbed_official 324:406fd2029f23 2173 #define BW_ADC_CLM2_CLM2(x, v) (HW_ADC_CLM2_WR(x, (HW_ADC_CLM2_RD(x) & ~BM_ADC_CLM2_CLM2) | BF_ADC_CLM2_CLM2(v)))
mbed_official 324:406fd2029f23 2174 /*@}*/
mbed_official 324:406fd2029f23 2175
mbed_official 324:406fd2029f23 2176 /*******************************************************************************
mbed_official 324:406fd2029f23 2177 * HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 2178 ******************************************************************************/
mbed_official 324:406fd2029f23 2179
mbed_official 324:406fd2029f23 2180 /*!
mbed_official 324:406fd2029f23 2181 * @brief HW_ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 2182 *
mbed_official 324:406fd2029f23 2183 * Reset value: 0x00000040U
mbed_official 324:406fd2029f23 2184 *
mbed_official 324:406fd2029f23 2185 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 2186 */
mbed_official 324:406fd2029f23 2187 typedef union _hw_adc_clm1
mbed_official 324:406fd2029f23 2188 {
mbed_official 324:406fd2029f23 2189 uint32_t U;
mbed_official 324:406fd2029f23 2190 struct _hw_adc_clm1_bitfields
mbed_official 324:406fd2029f23 2191 {
mbed_official 324:406fd2029f23 2192 uint32_t CLM1 : 7; /*!< [6:0] */
mbed_official 324:406fd2029f23 2193 uint32_t RESERVED0 : 25; /*!< [31:7] */
mbed_official 324:406fd2029f23 2194 } B;
mbed_official 324:406fd2029f23 2195 } hw_adc_clm1_t;
mbed_official 324:406fd2029f23 2196
mbed_official 324:406fd2029f23 2197 /*!
mbed_official 324:406fd2029f23 2198 * @name Constants and macros for entire ADC_CLM1 register
mbed_official 324:406fd2029f23 2199 */
mbed_official 324:406fd2029f23 2200 /*@{*/
mbed_official 324:406fd2029f23 2201 #define HW_ADC_CLM1_ADDR(x) ((x) + 0x68U)
mbed_official 324:406fd2029f23 2202
mbed_official 324:406fd2029f23 2203 #define HW_ADC_CLM1(x) (*(__IO hw_adc_clm1_t *) HW_ADC_CLM1_ADDR(x))
mbed_official 324:406fd2029f23 2204 #define HW_ADC_CLM1_RD(x) (HW_ADC_CLM1(x).U)
mbed_official 324:406fd2029f23 2205 #define HW_ADC_CLM1_WR(x, v) (HW_ADC_CLM1(x).U = (v))
mbed_official 324:406fd2029f23 2206 #define HW_ADC_CLM1_SET(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) | (v)))
mbed_official 324:406fd2029f23 2207 #define HW_ADC_CLM1_CLR(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2208 #define HW_ADC_CLM1_TOG(x, v) (HW_ADC_CLM1_WR(x, HW_ADC_CLM1_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2209 /*@}*/
mbed_official 324:406fd2029f23 2210
mbed_official 324:406fd2029f23 2211 /*
mbed_official 324:406fd2029f23 2212 * Constants & macros for individual ADC_CLM1 bitfields
mbed_official 324:406fd2029f23 2213 */
mbed_official 324:406fd2029f23 2214
mbed_official 324:406fd2029f23 2215 /*!
mbed_official 324:406fd2029f23 2216 * @name Register ADC_CLM1, field CLM1[6:0] (RW)
mbed_official 324:406fd2029f23 2217 *
mbed_official 324:406fd2029f23 2218 * Calibration Value
mbed_official 324:406fd2029f23 2219 */
mbed_official 324:406fd2029f23 2220 /*@{*/
mbed_official 324:406fd2029f23 2221 #define BP_ADC_CLM1_CLM1 (0U) /*!< Bit position for ADC_CLM1_CLM1. */
mbed_official 324:406fd2029f23 2222 #define BM_ADC_CLM1_CLM1 (0x0000007FU) /*!< Bit mask for ADC_CLM1_CLM1. */
mbed_official 324:406fd2029f23 2223 #define BS_ADC_CLM1_CLM1 (7U) /*!< Bit field size in bits for ADC_CLM1_CLM1. */
mbed_official 324:406fd2029f23 2224
mbed_official 324:406fd2029f23 2225 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
mbed_official 324:406fd2029f23 2226 #define BR_ADC_CLM1_CLM1(x) (HW_ADC_CLM1(x).B.CLM1)
mbed_official 324:406fd2029f23 2227
mbed_official 324:406fd2029f23 2228 /*! @brief Format value for bitfield ADC_CLM1_CLM1. */
mbed_official 324:406fd2029f23 2229 #define BF_ADC_CLM1_CLM1(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM1_CLM1) & BM_ADC_CLM1_CLM1)
mbed_official 324:406fd2029f23 2230
mbed_official 324:406fd2029f23 2231 /*! @brief Set the CLM1 field to a new value. */
mbed_official 324:406fd2029f23 2232 #define BW_ADC_CLM1_CLM1(x, v) (HW_ADC_CLM1_WR(x, (HW_ADC_CLM1_RD(x) & ~BM_ADC_CLM1_CLM1) | BF_ADC_CLM1_CLM1(v)))
mbed_official 324:406fd2029f23 2233 /*@}*/
mbed_official 324:406fd2029f23 2234
mbed_official 324:406fd2029f23 2235 /*******************************************************************************
mbed_official 324:406fd2029f23 2236 * HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register
mbed_official 324:406fd2029f23 2237 ******************************************************************************/
mbed_official 324:406fd2029f23 2238
mbed_official 324:406fd2029f23 2239 /*!
mbed_official 324:406fd2029f23 2240 * @brief HW_ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
mbed_official 324:406fd2029f23 2241 *
mbed_official 324:406fd2029f23 2242 * Reset value: 0x00000020U
mbed_official 324:406fd2029f23 2243 *
mbed_official 324:406fd2029f23 2244 * For more information, see CLMD register description.
mbed_official 324:406fd2029f23 2245 */
mbed_official 324:406fd2029f23 2246 typedef union _hw_adc_clm0
mbed_official 324:406fd2029f23 2247 {
mbed_official 324:406fd2029f23 2248 uint32_t U;
mbed_official 324:406fd2029f23 2249 struct _hw_adc_clm0_bitfields
mbed_official 324:406fd2029f23 2250 {
mbed_official 324:406fd2029f23 2251 uint32_t CLM0 : 6; /*!< [5:0] */
mbed_official 324:406fd2029f23 2252 uint32_t RESERVED0 : 26; /*!< [31:6] */
mbed_official 324:406fd2029f23 2253 } B;
mbed_official 324:406fd2029f23 2254 } hw_adc_clm0_t;
mbed_official 324:406fd2029f23 2255
mbed_official 324:406fd2029f23 2256 /*!
mbed_official 324:406fd2029f23 2257 * @name Constants and macros for entire ADC_CLM0 register
mbed_official 324:406fd2029f23 2258 */
mbed_official 324:406fd2029f23 2259 /*@{*/
mbed_official 324:406fd2029f23 2260 #define HW_ADC_CLM0_ADDR(x) ((x) + 0x6CU)
mbed_official 324:406fd2029f23 2261
mbed_official 324:406fd2029f23 2262 #define HW_ADC_CLM0(x) (*(__IO hw_adc_clm0_t *) HW_ADC_CLM0_ADDR(x))
mbed_official 324:406fd2029f23 2263 #define HW_ADC_CLM0_RD(x) (HW_ADC_CLM0(x).U)
mbed_official 324:406fd2029f23 2264 #define HW_ADC_CLM0_WR(x, v) (HW_ADC_CLM0(x).U = (v))
mbed_official 324:406fd2029f23 2265 #define HW_ADC_CLM0_SET(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) | (v)))
mbed_official 324:406fd2029f23 2266 #define HW_ADC_CLM0_CLR(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) & ~(v)))
mbed_official 324:406fd2029f23 2267 #define HW_ADC_CLM0_TOG(x, v) (HW_ADC_CLM0_WR(x, HW_ADC_CLM0_RD(x) ^ (v)))
mbed_official 324:406fd2029f23 2268 /*@}*/
mbed_official 324:406fd2029f23 2269
mbed_official 324:406fd2029f23 2270 /*
mbed_official 324:406fd2029f23 2271 * Constants & macros for individual ADC_CLM0 bitfields
mbed_official 324:406fd2029f23 2272 */
mbed_official 324:406fd2029f23 2273
mbed_official 324:406fd2029f23 2274 /*!
mbed_official 324:406fd2029f23 2275 * @name Register ADC_CLM0, field CLM0[5:0] (RW)
mbed_official 324:406fd2029f23 2276 *
mbed_official 324:406fd2029f23 2277 * Calibration Value
mbed_official 324:406fd2029f23 2278 */
mbed_official 324:406fd2029f23 2279 /*@{*/
mbed_official 324:406fd2029f23 2280 #define BP_ADC_CLM0_CLM0 (0U) /*!< Bit position for ADC_CLM0_CLM0. */
mbed_official 324:406fd2029f23 2281 #define BM_ADC_CLM0_CLM0 (0x0000003FU) /*!< Bit mask for ADC_CLM0_CLM0. */
mbed_official 324:406fd2029f23 2282 #define BS_ADC_CLM0_CLM0 (6U) /*!< Bit field size in bits for ADC_CLM0_CLM0. */
mbed_official 324:406fd2029f23 2283
mbed_official 324:406fd2029f23 2284 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
mbed_official 324:406fd2029f23 2285 #define BR_ADC_CLM0_CLM0(x) (HW_ADC_CLM0(x).B.CLM0)
mbed_official 324:406fd2029f23 2286
mbed_official 324:406fd2029f23 2287 /*! @brief Format value for bitfield ADC_CLM0_CLM0. */
mbed_official 324:406fd2029f23 2288 #define BF_ADC_CLM0_CLM0(v) ((uint32_t)((uint32_t)(v) << BP_ADC_CLM0_CLM0) & BM_ADC_CLM0_CLM0)
mbed_official 324:406fd2029f23 2289
mbed_official 324:406fd2029f23 2290 /*! @brief Set the CLM0 field to a new value. */
mbed_official 324:406fd2029f23 2291 #define BW_ADC_CLM0_CLM0(x, v) (HW_ADC_CLM0_WR(x, (HW_ADC_CLM0_RD(x) & ~BM_ADC_CLM0_CLM0) | BF_ADC_CLM0_CLM0(v)))
mbed_official 324:406fd2029f23 2292 /*@}*/
mbed_official 324:406fd2029f23 2293
mbed_official 324:406fd2029f23 2294 /*******************************************************************************
mbed_official 324:406fd2029f23 2295 * hw_adc_t - module struct
mbed_official 324:406fd2029f23 2296 ******************************************************************************/
mbed_official 324:406fd2029f23 2297 /*!
mbed_official 324:406fd2029f23 2298 * @brief All ADC module registers.
mbed_official 324:406fd2029f23 2299 */
mbed_official 324:406fd2029f23 2300 #pragma pack(1)
mbed_official 324:406fd2029f23 2301 typedef struct _hw_adc
mbed_official 324:406fd2029f23 2302 {
mbed_official 324:406fd2029f23 2303 __IO hw_adc_sc1n_t SC1n[2]; /*!< [0x0] ADC Status and Control Registers 1 */
mbed_official 324:406fd2029f23 2304 __IO hw_adc_cfg1_t CFG1; /*!< [0x8] ADC Configuration Register 1 */
mbed_official 324:406fd2029f23 2305 __IO hw_adc_cfg2_t CFG2; /*!< [0xC] ADC Configuration Register 2 */
mbed_official 324:406fd2029f23 2306 __I hw_adc_rn_t Rn[2]; /*!< [0x10] ADC Data Result Register */
mbed_official 324:406fd2029f23 2307 __IO hw_adc_cv1_t CV1; /*!< [0x18] Compare Value Registers */
mbed_official 324:406fd2029f23 2308 __IO hw_adc_cv2_t CV2; /*!< [0x1C] Compare Value Registers */
mbed_official 324:406fd2029f23 2309 __IO hw_adc_sc2_t SC2; /*!< [0x20] Status and Control Register 2 */
mbed_official 324:406fd2029f23 2310 __IO hw_adc_sc3_t SC3; /*!< [0x24] Status and Control Register 3 */
mbed_official 324:406fd2029f23 2311 __IO hw_adc_ofs_t OFS; /*!< [0x28] ADC Offset Correction Register */
mbed_official 324:406fd2029f23 2312 __IO hw_adc_pg_t PG; /*!< [0x2C] ADC Plus-Side Gain Register */
mbed_official 324:406fd2029f23 2313 __IO hw_adc_mg_t MG; /*!< [0x30] ADC Minus-Side Gain Register */
mbed_official 324:406fd2029f23 2314 __IO hw_adc_clpd_t CLPD; /*!< [0x34] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2315 __IO hw_adc_clps_t CLPS; /*!< [0x38] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2316 __IO hw_adc_clp4_t CLP4; /*!< [0x3C] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2317 __IO hw_adc_clp3_t CLP3; /*!< [0x40] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2318 __IO hw_adc_clp2_t CLP2; /*!< [0x44] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2319 __IO hw_adc_clp1_t CLP1; /*!< [0x48] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2320 __IO hw_adc_clp0_t CLP0; /*!< [0x4C] ADC Plus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2321 uint8_t _reserved0[4];
mbed_official 324:406fd2029f23 2322 __IO hw_adc_clmd_t CLMD; /*!< [0x54] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2323 __IO hw_adc_clms_t CLMS; /*!< [0x58] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2324 __IO hw_adc_clm4_t CLM4; /*!< [0x5C] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2325 __IO hw_adc_clm3_t CLM3; /*!< [0x60] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2326 __IO hw_adc_clm2_t CLM2; /*!< [0x64] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2327 __IO hw_adc_clm1_t CLM1; /*!< [0x68] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2328 __IO hw_adc_clm0_t CLM0; /*!< [0x6C] ADC Minus-Side General Calibration Value Register */
mbed_official 324:406fd2029f23 2329 } hw_adc_t;
mbed_official 324:406fd2029f23 2330 #pragma pack()
mbed_official 324:406fd2029f23 2331
mbed_official 324:406fd2029f23 2332 /*! @brief Macro to access all ADC registers. */
mbed_official 324:406fd2029f23 2333 /*! @param x ADC module instance base address. */
mbed_official 324:406fd2029f23 2334 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
mbed_official 324:406fd2029f23 2335 * use the '&' operator, like <code>&HW_ADC(ADC0_BASE)</code>. */
mbed_official 324:406fd2029f23 2336 #define HW_ADC(x) (*(hw_adc_t *)(x))
mbed_official 324:406fd2029f23 2337
mbed_official 324:406fd2029f23 2338 #endif /* __HW_ADC_REGISTERS_H__ */
mbed_official 324:406fd2029f23 2339 /* EOF */