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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
320:be04b2b1e3f2 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 ** ###################################################################
mbed_official 146:f64d43ff0c18 3 ** Processor: MK64FN1M0VMD12
mbed_official 324:406fd2029f23 4 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 146:f64d43ff0c18 5 ** Freescale C/C++ for Embedded ARM
mbed_official 146:f64d43ff0c18 6 ** GNU C Compiler
mbed_official 146:f64d43ff0c18 7 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 146:f64d43ff0c18 8 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 146:f64d43ff0c18 9 **
mbed_official 324:406fd2029f23 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 11 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 12 ** Build: b140611
mbed_official 146:f64d43ff0c18 13 **
mbed_official 146:f64d43ff0c18 14 ** Abstract:
mbed_official 146:f64d43ff0c18 15 ** Provides a system configuration function and a global variable that
mbed_official 146:f64d43ff0c18 16 ** contains the system frequency. It configures the device and initializes
mbed_official 146:f64d43ff0c18 17 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 146:f64d43ff0c18 18 **
mbed_official 324:406fd2029f23 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 20 ** All rights reserved.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 23 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 24 **
mbed_official 324:406fd2029f23 25 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 26 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 29 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 30 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 33 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 34 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 35 **
mbed_official 324:406fd2029f23 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 46 **
mbed_official 146:f64d43ff0c18 47 ** http: www.freescale.com
mbed_official 146:f64d43ff0c18 48 ** mail: support@freescale.com
mbed_official 146:f64d43ff0c18 49 **
mbed_official 146:f64d43ff0c18 50 ** Revisions:
mbed_official 146:f64d43ff0c18 51 ** - rev. 1.0 (2013-08-12)
mbed_official 146:f64d43ff0c18 52 ** Initial version.
mbed_official 146:f64d43ff0c18 53 ** - rev. 2.0 (2013-10-29)
mbed_official 146:f64d43ff0c18 54 ** Register accessor macros added to the memory map.
mbed_official 146:f64d43ff0c18 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 146:f64d43ff0c18 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 146:f64d43ff0c18 57 ** System initialization updated.
mbed_official 146:f64d43ff0c18 58 ** MCG - registers updated.
mbed_official 146:f64d43ff0c18 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 60 ** - rev. 2.1 (2013-10-30)
mbed_official 146:f64d43ff0c18 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 62 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 63 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 64 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 65 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 66 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 67 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 68 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 71 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 146:f64d43ff0c18 75 **
mbed_official 146:f64d43ff0c18 76 ** ###################################################################
mbed_official 146:f64d43ff0c18 77 */
mbed_official 146:f64d43ff0c18 78
mbed_official 146:f64d43ff0c18 79 /*!
mbed_official 146:f64d43ff0c18 80 * @file MK64F12
mbed_official 324:406fd2029f23 81 * @version 2.5
mbed_official 324:406fd2029f23 82 * @date 2014-02-10
mbed_official 146:f64d43ff0c18 83 * @brief Device specific configuration file for MK64F12 (header file)
mbed_official 146:f64d43ff0c18 84 *
mbed_official 146:f64d43ff0c18 85 * Provides a system configuration function and a global variable that contains
mbed_official 146:f64d43ff0c18 86 * the system frequency. It configures the device and initializes the oscillator
mbed_official 146:f64d43ff0c18 87 * (PLL) that is part of the microcontroller device.
mbed_official 146:f64d43ff0c18 88 */
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 #ifndef SYSTEM_MK64F12_H_
mbed_official 146:f64d43ff0c18 91 #define SYSTEM_MK64F12_H_ /**< Symbol preventing repeated inclusion */
mbed_official 146:f64d43ff0c18 92
mbed_official 146:f64d43ff0c18 93 #ifdef __cplusplus
mbed_official 146:f64d43ff0c18 94 extern "C" {
mbed_official 146:f64d43ff0c18 95 #endif
mbed_official 146:f64d43ff0c18 96
mbed_official 146:f64d43ff0c18 97 #include <stdint.h>
mbed_official 146:f64d43ff0c18 98
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 #define DISABLE_WDOG 1
mbed_official 324:406fd2029f23 101
mbed_official 324:406fd2029f23 102 #ifndef CLOCK_SETUP
mbed_official 324:406fd2029f23 103 #define CLOCK_SETUP 4
mbed_official 324:406fd2029f23 104 #endif
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 /* MCG mode constants */
mbed_official 324:406fd2029f23 107
mbed_official 324:406fd2029f23 108 #define MCG_MODE_FEI 0U
mbed_official 324:406fd2029f23 109 #define MCG_MODE_FBI 1U
mbed_official 324:406fd2029f23 110 #define MCG_MODE_BLPI 2U
mbed_official 324:406fd2029f23 111 #define MCG_MODE_FEE 3U
mbed_official 324:406fd2029f23 112 #define MCG_MODE_FBE 4U
mbed_official 324:406fd2029f23 113 #define MCG_MODE_BLPE 5U
mbed_official 324:406fd2029f23 114 #define MCG_MODE_PBE 6U
mbed_official 324:406fd2029f23 115 #define MCG_MODE_PEE 7U
mbed_official 324:406fd2029f23 116
mbed_official 324:406fd2029f23 117 /* Predefined clock setups
mbed_official 324:406fd2029f23 118 0 ... Default part configuration
mbed_official 324:406fd2029f23 119 Multipurpose Clock Generator (MCG) in FEI mode.
mbed_official 324:406fd2029f23 120 Reference clock source for MCG module: Slow internal reference clock
mbed_official 324:406fd2029f23 121 Core clock = 20.97152MHz
mbed_official 324:406fd2029f23 122 Bus clock = 20.97152MHz
mbed_official 324:406fd2029f23 123 1 ... Maximum achievable clock frequency configuration
mbed_official 324:406fd2029f23 124 Multipurpose Clock Generator (MCG) in PEE mode.
mbed_official 324:406fd2029f23 125 Reference clock source for MCG module: System oscillator 0 reference clock
mbed_official 324:406fd2029f23 126 Core clock = 120MHz
mbed_official 324:406fd2029f23 127 Bus clock = 60MHz
mbed_official 324:406fd2029f23 128 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
mbed_official 324:406fd2029f23 129 Multipurpose Clock Generator (MCG) in BLPI mode.
mbed_official 324:406fd2029f23 130 Reference clock source for MCG module: Fast internal reference clock
mbed_official 324:406fd2029f23 131 Core clock = 4MHz
mbed_official 324:406fd2029f23 132 Bus clock = 4MHz
mbed_official 324:406fd2029f23 133 3 ... Chip externally clocked, ready for Very Low Power Run mode.
mbed_official 324:406fd2029f23 134 Multipurpose Clock Generator (MCG) in BLPE mode.
mbed_official 324:406fd2029f23 135 Reference clock source for MCG module: RTC oscillator reference clock
mbed_official 324:406fd2029f23 136 Core clock = 0.032768MHz
mbed_official 324:406fd2029f23 137 Bus clock = 0.032768MHz
mbed_official 324:406fd2029f23 138 4 ... USB clock setup
mbed_official 324:406fd2029f23 139 Multipurpose Clock Generator (MCG) in PEE mode.
mbed_official 324:406fd2029f23 140 Reference clock source for MCG module: System oscillator 0 reference clock
mbed_official 324:406fd2029f23 141 Core clock = 120MHz
mbed_official 324:406fd2029f23 142 Bus clock = 60MHz
mbed_official 324:406fd2029f23 143 */
mbed_official 324:406fd2029f23 144
mbed_official 324:406fd2029f23 145 /* Define clock source values */
mbed_official 324:406fd2029f23 146
mbed_official 324:406fd2029f23 147 #define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 324:406fd2029f23 148 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
mbed_official 324:406fd2029f23 149 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 324:406fd2029f23 150 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 324:406fd2029f23 151 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
mbed_official 324:406fd2029f23 152
mbed_official 324:406fd2029f23 153 /* RTC oscillator setting */
mbed_official 324:406fd2029f23 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
mbed_official 324:406fd2029f23 155 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
mbed_official 324:406fd2029f23 156
mbed_official 324:406fd2029f23 157 /* Low power mode enable */
mbed_official 324:406fd2029f23 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
mbed_official 324:406fd2029f23 159 #define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */
mbed_official 324:406fd2029f23 160
mbed_official 324:406fd2029f23 161 /* Internal reference clock trim */
mbed_official 324:406fd2029f23 162 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
mbed_official 324:406fd2029f23 163 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
mbed_official 324:406fd2029f23 164 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
mbed_official 324:406fd2029f23 165 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
mbed_official 324:406fd2029f23 166
mbed_official 324:406fd2029f23 167 #if (CLOCK_SETUP == 0)
mbed_official 324:406fd2029f23 168 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
mbed_official 324:406fd2029f23 169 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
mbed_official 324:406fd2029f23 170 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 324:406fd2029f23 171 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
mbed_official 324:406fd2029f23 172 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
mbed_official 324:406fd2029f23 173 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
mbed_official 324:406fd2029f23 174 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 324:406fd2029f23 175 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
mbed_official 324:406fd2029f23 176 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
mbed_official 324:406fd2029f23 177 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
mbed_official 324:406fd2029f23 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 324:406fd2029f23 179 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
mbed_official 324:406fd2029f23 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 324:406fd2029f23 181 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
mbed_official 324:406fd2029f23 182 /* MCG_C7: OSCSEL=0 */
mbed_official 324:406fd2029f23 183 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
mbed_official 324:406fd2029f23 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 324:406fd2029f23 185 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
mbed_official 324:406fd2029f23 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
mbed_official 324:406fd2029f23 187 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
mbed_official 324:406fd2029f23 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
mbed_official 324:406fd2029f23 189 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
mbed_official 324:406fd2029f23 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
mbed_official 324:406fd2029f23 191 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
mbed_official 324:406fd2029f23 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 324:406fd2029f23 193 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
mbed_official 324:406fd2029f23 194 #elif (CLOCK_SETUP == 1)
mbed_official 324:406fd2029f23 195 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
mbed_official 324:406fd2029f23 196 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
mbed_official 324:406fd2029f23 197 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 324:406fd2029f23 198 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
mbed_official 324:406fd2029f23 199 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
mbed_official 324:406fd2029f23 200 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
mbed_official 324:406fd2029f23 201 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 324:406fd2029f23 202 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
mbed_official 324:406fd2029f23 203 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
mbed_official 324:406fd2029f23 204 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
mbed_official 324:406fd2029f23 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
mbed_official 324:406fd2029f23 206 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
mbed_official 324:406fd2029f23 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
mbed_official 324:406fd2029f23 208 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
mbed_official 324:406fd2029f23 209 /* MCG_C7: OSCSEL=0 */
mbed_official 324:406fd2029f23 210 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
mbed_official 324:406fd2029f23 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 324:406fd2029f23 212 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
mbed_official 324:406fd2029f23 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
mbed_official 324:406fd2029f23 214 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
mbed_official 324:406fd2029f23 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
mbed_official 324:406fd2029f23 216 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
mbed_official 324:406fd2029f23 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
mbed_official 324:406fd2029f23 218 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
mbed_official 324:406fd2029f23 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 324:406fd2029f23 220 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
mbed_official 324:406fd2029f23 221 #elif (CLOCK_SETUP == 2)
mbed_official 324:406fd2029f23 222 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
mbed_official 324:406fd2029f23 223 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
mbed_official 324:406fd2029f23 224 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 324:406fd2029f23 225 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
mbed_official 324:406fd2029f23 226 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
mbed_official 324:406fd2029f23 227 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
mbed_official 324:406fd2029f23 228 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 324:406fd2029f23 229 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
mbed_official 324:406fd2029f23 230 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
mbed_official 324:406fd2029f23 231 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
mbed_official 324:406fd2029f23 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 324:406fd2029f23 233 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
mbed_official 324:406fd2029f23 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 324:406fd2029f23 235 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
mbed_official 324:406fd2029f23 236 /* MCG_C7: OSCSEL=0 */
mbed_official 324:406fd2029f23 237 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
mbed_official 324:406fd2029f23 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 324:406fd2029f23 239 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
mbed_official 324:406fd2029f23 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
mbed_official 324:406fd2029f23 241 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
mbed_official 324:406fd2029f23 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
mbed_official 324:406fd2029f23 243 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
mbed_official 324:406fd2029f23 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
mbed_official 324:406fd2029f23 245 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
mbed_official 324:406fd2029f23 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 324:406fd2029f23 247 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
mbed_official 324:406fd2029f23 248 #elif (CLOCK_SETUP == 3)
mbed_official 324:406fd2029f23 249 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
mbed_official 324:406fd2029f23 250 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
mbed_official 324:406fd2029f23 251 /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 324:406fd2029f23 252 #define SYSTEM_MCG_C1_VALUE 0x82U /* MCG_C1 */
mbed_official 324:406fd2029f23 253 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
mbed_official 324:406fd2029f23 254 #define SYSTEM_MCG_C2_VALUE 0x23U /* MCG_C2 */
mbed_official 324:406fd2029f23 255 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 324:406fd2029f23 256 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
mbed_official 324:406fd2029f23 257 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
mbed_official 324:406fd2029f23 258 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
mbed_official 324:406fd2029f23 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
mbed_official 324:406fd2029f23 260 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
mbed_official 324:406fd2029f23 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
mbed_official 324:406fd2029f23 262 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
mbed_official 324:406fd2029f23 263 /* MCG_C7: OSCSEL=1 */
mbed_official 324:406fd2029f23 264 #define SYSTEM_MCG_C7_VALUE 0x01U /* MCG_C7 */
mbed_official 324:406fd2029f23 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 324:406fd2029f23 266 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
mbed_official 324:406fd2029f23 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
mbed_official 324:406fd2029f23 268 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
mbed_official 324:406fd2029f23 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
mbed_official 324:406fd2029f23 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00U /* SIM_CLKDIV1 */
mbed_official 324:406fd2029f23 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
mbed_official 324:406fd2029f23 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
mbed_official 324:406fd2029f23 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 324:406fd2029f23 274 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
mbed_official 324:406fd2029f23 275 #elif (CLOCK_SETUP == 4)
mbed_official 324:406fd2029f23 276 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
mbed_official 324:406fd2029f23 277 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
mbed_official 324:406fd2029f23 278 /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 324:406fd2029f23 279 #define SYSTEM_MCG_C1_VALUE 0x3AU /* MCG_C1 */
mbed_official 324:406fd2029f23 280 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
mbed_official 324:406fd2029f23 281 #define SYSTEM_MCG_C2_VALUE 0x20U /* MCG_C2 */
mbed_official 324:406fd2029f23 282 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
mbed_official 324:406fd2029f23 283 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
mbed_official 324:406fd2029f23 284 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
mbed_official 324:406fd2029f23 285 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
mbed_official 324:406fd2029f23 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
mbed_official 324:406fd2029f23 287 #define SYSTEM_MCG_C5_VALUE 0x13U /* MCG_C5 */
mbed_official 324:406fd2029f23 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
mbed_official 324:406fd2029f23 289 #define SYSTEM_MCG_C6_VALUE 0x58U /* MCG_C6 */
mbed_official 324:406fd2029f23 290 /* MCG_C7: OSCSEL=0 */
mbed_official 324:406fd2029f23 291 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
mbed_official 324:406fd2029f23 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 324:406fd2029f23 293 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
mbed_official 324:406fd2029f23 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
mbed_official 324:406fd2029f23 295 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
mbed_official 324:406fd2029f23 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
mbed_official 324:406fd2029f23 297 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
mbed_official 324:406fd2029f23 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
mbed_official 324:406fd2029f23 299 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
mbed_official 324:406fd2029f23 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
mbed_official 324:406fd2029f23 301 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
mbed_official 324:406fd2029f23 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 324:406fd2029f23 303 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
mbed_official 324:406fd2029f23 304 #endif
mbed_official 324:406fd2029f23 305
mbed_official 146:f64d43ff0c18 306 /**
mbed_official 146:f64d43ff0c18 307 * @brief System clock frequency (core clock)
mbed_official 146:f64d43ff0c18 308 *
mbed_official 146:f64d43ff0c18 309 * The system clock frequency supplied to the SysTick timer and the processor
mbed_official 146:f64d43ff0c18 310 * core clock. This variable can be used by the user application to setup the
mbed_official 146:f64d43ff0c18 311 * SysTick timer or configure other parameters. It may also be used by debugger to
mbed_official 146:f64d43ff0c18 312 * query the frequency of the debug timer or configure the trace clock speed
mbed_official 146:f64d43ff0c18 313 * SystemCoreClock is initialized with a correct predefined value.
mbed_official 146:f64d43ff0c18 314 */
mbed_official 146:f64d43ff0c18 315 extern uint32_t SystemCoreClock;
mbed_official 146:f64d43ff0c18 316
mbed_official 146:f64d43ff0c18 317 /**
mbed_official 146:f64d43ff0c18 318 * @brief Setup the microcontroller system.
mbed_official 146:f64d43ff0c18 319 *
mbed_official 146:f64d43ff0c18 320 * Typically this function configures the oscillator (PLL) that is part of the
mbed_official 146:f64d43ff0c18 321 * microcontroller device. For systems with variable clock speed it also updates
mbed_official 146:f64d43ff0c18 322 * the variable SystemCoreClock. SystemInit is called from startup_device file.
mbed_official 146:f64d43ff0c18 323 */
mbed_official 146:f64d43ff0c18 324 void SystemInit (void);
mbed_official 146:f64d43ff0c18 325
mbed_official 146:f64d43ff0c18 326 /**
mbed_official 146:f64d43ff0c18 327 * @brief Updates the SystemCoreClock variable.
mbed_official 146:f64d43ff0c18 328 *
mbed_official 146:f64d43ff0c18 329 * It must be called whenever the core clock is changed during program
mbed_official 146:f64d43ff0c18 330 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
mbed_official 146:f64d43ff0c18 331 * the current core clock.
mbed_official 146:f64d43ff0c18 332 */
mbed_official 146:f64d43ff0c18 333 void SystemCoreClockUpdate (void);
mbed_official 146:f64d43ff0c18 334
mbed_official 146:f64d43ff0c18 335 #ifdef __cplusplus
mbed_official 146:f64d43ff0c18 336 }
mbed_official 146:f64d43ff0c18 337 #endif
mbed_official 146:f64d43ff0c18 338
mbed_official 146:f64d43ff0c18 339 #endif /* #if !defined(SYSTEM_MK64F12_H_) */