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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/system_LPC23xx.c@323:3e2706a32e81, 2014-09-15 (annotated)

Committer:
mbed_official
Date:
Mon Sep 15 15:30:06 2014 +0100
Revision:
323:3e2706a32e81
Parent:
13:0645d8841f51 
Synchronized with git revision ffa4168e11172fe7e9f2905047fa8a65eaa09588



Full URL: https://github.com/mbedmicro/mbed/commit/ffa4168e11172fe7e9f2905047fa8a65eaa09588/



[HAL] MTS_GAMBIT - SPI pin names expansion

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
emilmont 10:3bc89ef62ce7 5 */
emilmont 10:3bc89ef62ce7 6
emilmont 10:3bc89ef62ce7 7 #include <stdint.h>
emilmont 10:3bc89ef62ce7 8 #include "LPC23xx.h"
emilmont 10:3bc89ef62ce7 9
emilmont 10:3bc89ef62ce7 10 #define CLOCK_SETUP 1
emilmont 10:3bc89ef62ce7 11 #define SCS_Val 0x00000020
emilmont 10:3bc89ef62ce7 12 #define CLKSRCSEL_Val 0x00000001
emilmont 10:3bc89ef62ce7 13
emilmont 10:3bc89ef62ce7 14 #define PLL0_SETUP 1
emilmont 10:3bc89ef62ce7 15 #define PLL0CFG_Val 0x00000013
emilmont 10:3bc89ef62ce7 16 #define CCLKCFG_Val 0x00000007
emilmont 10:3bc89ef62ce7 17 #define USBCLKCFG_Val 0x00000009
emilmont 10:3bc89ef62ce7 18 #define PCLKSEL0_Val 0x00000000
emilmont 10:3bc89ef62ce7 19 #define PCLKSEL1_Val 0x00000000
emilmont 10:3bc89ef62ce7 20 #define PCONP_Val 0x042887DE
emilmont 10:3bc89ef62ce7 21 #define CLKOUTCFG_Val 0x00000000
emilmont 10:3bc89ef62ce7 22 #define MAMCR_Val 0x00000001 // there is a bug in the MAM so it should never be fully enabled (only disabled or partially enabled)
emilmont 10:3bc89ef62ce7 23 #define MAMTIM_Val 0x00000004
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 26 DEFINES
emilmont 10:3bc89ef62ce7 27 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 #define XTAL (12000000UL) /* Oscillator frequency */
emilmont 10:3bc89ef62ce7 30 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
emilmont 10:3bc89ef62ce7 31 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
emilmont 10:3bc89ef62ce7 32 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 /* F_cco0 = (2 * M * F_in) / N */
emilmont 10:3bc89ef62ce7 35 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
emilmont 10:3bc89ef62ce7 36 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
emilmont 10:3bc89ef62ce7 37 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
emilmont 10:3bc89ef62ce7 38 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 /* Determine core clock frequency according to settings */
emilmont 10:3bc89ef62ce7 41 #if (PLL0_SETUP)
emilmont 10:3bc89ef62ce7 42 #if ((CLKSRCSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 43 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 44 #elif ((CLKSRCSEL_Val & 0x03) == 2)
emilmont 10:3bc89ef62ce7 45 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 46 #else
emilmont 10:3bc89ef62ce7 47 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
emilmont 10:3bc89ef62ce7 48 #endif
emilmont 10:3bc89ef62ce7 49 #endif
emilmont 10:3bc89ef62ce7 50
emilmont 10:3bc89ef62ce7 51
emilmont 10:3bc89ef62ce7 52 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 53 Clock Variable definitions
emilmont 10:3bc89ef62ce7 54 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 55 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 58 Clock functions
emilmont 10:3bc89ef62ce7 59 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 60 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
emilmont 10:3bc89ef62ce7 61 {
emilmont 10:3bc89ef62ce7 62 /* Determine clock frequency according to clock register values */
emilmont 10:3bc89ef62ce7 63 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
emilmont 10:3bc89ef62ce7 64 switch (LPC_SC->CLKSRCSEL & 0x03) {
emilmont 10:3bc89ef62ce7 65 case 0: /* Int. RC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 66 case 3: /* Reserved, default to Int. RC */
emilmont 10:3bc89ef62ce7 67 SystemCoreClock = (IRC_OSC *
emilmont 10:3bc89ef62ce7 68 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 69 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
emilmont 10:3bc89ef62ce7 70 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 71 break;
emilmont 10:3bc89ef62ce7 72 case 1: /* Main oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 73 SystemCoreClock = (OSC_CLK *
emilmont 10:3bc89ef62ce7 74 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 75 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
emilmont 10:3bc89ef62ce7 76 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 77 break;
emilmont 10:3bc89ef62ce7 78 case 2: /* RTC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 79 SystemCoreClock = (RTC_CLK *
emilmont 10:3bc89ef62ce7 80 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
emilmont 10:3bc89ef62ce7 81 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
emilmont 10:3bc89ef62ce7 82 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
emilmont 10:3bc89ef62ce7 83 break;
emilmont 10:3bc89ef62ce7 84 }
emilmont 10:3bc89ef62ce7 85 } else {
emilmont 10:3bc89ef62ce7 86 switch (LPC_SC->CLKSRCSEL & 0x03) {
emilmont 10:3bc89ef62ce7 87 case 0: /* Int. RC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 88 case 3: /* Reserved, default to Int. RC */
emilmont 10:3bc89ef62ce7 89 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 90 break;
emilmont 10:3bc89ef62ce7 91 case 1: /* Main oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 92 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 93 break;
emilmont 10:3bc89ef62ce7 94 case 2: /* RTC oscillator => PLL0 */
emilmont 10:3bc89ef62ce7 95 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
emilmont 10:3bc89ef62ce7 96 break;
emilmont 10:3bc89ef62ce7 97 }
emilmont 10:3bc89ef62ce7 98 }
emilmont 10:3bc89ef62ce7 99 }
emilmont 10:3bc89ef62ce7 100
emilmont 10:3bc89ef62ce7 101 /**
emilmont 10:3bc89ef62ce7 102 * Initialize the system
emilmont 10:3bc89ef62ce7 103 *
emilmont 10:3bc89ef62ce7 104 * @param none
emilmont 10:3bc89ef62ce7 105 * @return none
emilmont 10:3bc89ef62ce7 106 *
emilmont 10:3bc89ef62ce7 107 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 108 * Initialize the System and update the SystemFrequency variable.
emilmont 10:3bc89ef62ce7 109 */
emilmont 10:3bc89ef62ce7 110 void SystemInit (void)
emilmont 10:3bc89ef62ce7 111 {
emilmont 10:3bc89ef62ce7 112 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 113 LPC_SC->SCS = SCS_Val;
emilmont 10:3bc89ef62ce7 114 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
emilmont 10:3bc89ef62ce7 115 while ((LPC_SC->SCS & (1 << 6)) == 0); /* Wait for Oscillator to be ready */
emilmont 10:3bc89ef62ce7 116 }
emilmont 10:3bc89ef62ce7 117
emilmont 10:3bc89ef62ce7 118 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120 #if (PLL0_SETUP)
emilmont 10:3bc89ef62ce7 121 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
emilmont 10:3bc89ef62ce7 122 LPC_SC->PLL0CFG = PLL0CFG_Val;
emilmont 10:3bc89ef62ce7 123 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
emilmont 10:3bc89ef62ce7 124 LPC_SC->PLL0FEED = 0xAA;
emilmont 10:3bc89ef62ce7 125 LPC_SC->PLL0FEED = 0x55;
emilmont 10:3bc89ef62ce7 126 while (!(LPC_SC->PLL0STAT & (1 << 26))); /* Wait for PLOCK0 */
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
emilmont 10:3bc89ef62ce7 129 LPC_SC->PLL0FEED = 0xAA;
emilmont 10:3bc89ef62ce7 130 LPC_SC->PLL0FEED = 0x55;
emilmont 10:3bc89ef62ce7 131 #endif
emilmont 10:3bc89ef62ce7 132
emilmont 10:3bc89ef62ce7 133 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
emilmont 10:3bc89ef62ce7 134 #endif
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
emilmont 10:3bc89ef62ce7 137 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
emilmont 10:3bc89ef62ce7 140
emilmont 10:3bc89ef62ce7 141 // Setup MAM
emilmont 10:3bc89ef62ce7 142 LPC_SC->MAMTIM = MAMTIM_Val;
emilmont 10:3bc89ef62ce7 143 LPC_SC->MAMCR = MAMCR_Val;
emilmont 10:3bc89ef62ce7 144 }