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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h@323:3e2706a32e81, 2014-09-15 (annotated)

Committer:
mbed_official
Date:
Mon Sep 15 15:30:06 2014 +0100
Revision:
323:3e2706a32e81
Parent:
13:0645d8841f51 
Synchronized with git revision ffa4168e11172fe7e9f2905047fa8a65eaa09588



Full URL: https://github.com/mbedmicro/mbed/commit/ffa4168e11172fe7e9f2905047fa8a65eaa09588/



[HAL] MTS_GAMBIT - SPI pin names expansion

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
emilmont 10:3bc89ef62ce7 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
emilmont 10:3bc89ef62ce7 5 */
emilmont 10:3bc89ef62ce7 6
emilmont 10:3bc89ef62ce7 7 #ifndef __LPC23xx_H
emilmont 10:3bc89ef62ce7 8 #define __LPC23xx_H
emilmont 10:3bc89ef62ce7 9
emilmont 10:3bc89ef62ce7 10 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 11 extern "C" {
emilmont 10:3bc89ef62ce7 12 #endif
emilmont 10:3bc89ef62ce7 13
emilmont 10:3bc89ef62ce7 14 /*
emilmont 10:3bc89ef62ce7 15 * ==========================================================================
emilmont 10:3bc89ef62ce7 16 * ---------- Interrupt Number Definition -----------------------------------
emilmont 10:3bc89ef62ce7 17 * ==========================================================================
emilmont 10:3bc89ef62ce7 18 */
emilmont 10:3bc89ef62ce7 19
emilmont 10:3bc89ef62ce7 20 typedef enum IRQn
emilmont 10:3bc89ef62ce7 21 {
emilmont 10:3bc89ef62ce7 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
emilmont 10:3bc89ef62ce7 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
emilmont 10:3bc89ef62ce7 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
emilmont 10:3bc89ef62ce7 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
emilmont 10:3bc89ef62ce7 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
emilmont 10:3bc89ef62ce7 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
emilmont 10:3bc89ef62ce7 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
emilmont 10:3bc89ef62ce7 31 SPI_IRQn = 10, /*!< SPI Interrupt */
emilmont 10:3bc89ef62ce7 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
emilmont 10:3bc89ef62ce7 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
emilmont 10:3bc89ef62ce7 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
emilmont 10:3bc89ef62ce7 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
emilmont 10:3bc89ef62ce7 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
emilmont 10:3bc89ef62ce7 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
emilmont 10:3bc89ef62ce7 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
emilmont 10:3bc89ef62ce7 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
emilmont 10:3bc89ef62ce7 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
emilmont 10:3bc89ef62ce7 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
emilmont 10:3bc89ef62ce7 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
emilmont 10:3bc89ef62ce7 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
emilmont 10:3bc89ef62ce7 44 USB_IRQn = 22, /*!< USB Interrupt */
emilmont 10:3bc89ef62ce7 45 CAN_IRQn = 23, /*!< CAN Interrupt */
emilmont 10:3bc89ef62ce7 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
emilmont 10:3bc89ef62ce7 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
emilmont 10:3bc89ef62ce7 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
emilmont 10:3bc89ef62ce7 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
emilmont 10:3bc89ef62ce7 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
emilmont 10:3bc89ef62ce7 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
emilmont 10:3bc89ef62ce7 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
emilmont 10:3bc89ef62ce7 53 I2S_IRQn = 31, /*!< I2S Interrupt */
emilmont 10:3bc89ef62ce7 54 } IRQn_Type;
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 /*
emilmont 10:3bc89ef62ce7 57 * ==========================================================================
emilmont 10:3bc89ef62ce7 58 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 10:3bc89ef62ce7 59 * ==========================================================================
emilmont 10:3bc89ef62ce7 60 */
emilmont 10:3bc89ef62ce7 61
emilmont 10:3bc89ef62ce7 62 /* Configuration of the ARM7 Processor and Core Peripherals */
emilmont 10:3bc89ef62ce7 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 10:3bc89ef62ce7 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
emilmont 10:3bc89ef62ce7 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 10:3bc89ef62ce7 66
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 #include <core_arm7.h>
emilmont 10:3bc89ef62ce7 69 #include "system_LPC23xx.h" /* System Header */
emilmont 10:3bc89ef62ce7 70
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 /******************************************************************************/
emilmont 10:3bc89ef62ce7 73 /* Device Specific Peripheral registers structures */
emilmont 10:3bc89ef62ce7 74 /******************************************************************************/
emilmont 10:3bc89ef62ce7 75 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 76 #pragma anon_unions
emilmont 10:3bc89ef62ce7 77 #endif
emilmont 10:3bc89ef62ce7 78
emilmont 10:3bc89ef62ce7 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
emilmont 10:3bc89ef62ce7 80 typedef struct
emilmont 10:3bc89ef62ce7 81 {
emilmont 10:3bc89ef62ce7 82 __I uint32_t IRQStatus;
emilmont 10:3bc89ef62ce7 83 __I uint32_t FIQStatus;
emilmont 10:3bc89ef62ce7 84 __I uint32_t RawIntr;
emilmont 10:3bc89ef62ce7 85 __IO uint32_t IntSelect;
emilmont 10:3bc89ef62ce7 86 __IO uint32_t IntEnable;
emilmont 10:3bc89ef62ce7 87 __O uint32_t IntEnClr;
emilmont 10:3bc89ef62ce7 88 __IO uint32_t SoftInt;
emilmont 10:3bc89ef62ce7 89 __O uint32_t SoftIntClr;
emilmont 10:3bc89ef62ce7 90 __IO uint32_t Protection;
emilmont 10:3bc89ef62ce7 91 __IO uint32_t SWPriorityMask;
emilmont 10:3bc89ef62ce7 92 __IO uint32_t RESERVED0[54];
emilmont 10:3bc89ef62ce7 93 __IO uint32_t VectAddr[32];
emilmont 10:3bc89ef62ce7 94 __IO uint32_t RESERVED1[32];
emilmont 10:3bc89ef62ce7 95 __IO uint32_t VectPriority[32];
emilmont 10:3bc89ef62ce7 96 __IO uint32_t RESERVED2[800];
emilmont 10:3bc89ef62ce7 97 __IO uint32_t Address;
emilmont 10:3bc89ef62ce7 98 } LPC_VIC_TypeDef;
emilmont 10:3bc89ef62ce7 99
emilmont 10:3bc89ef62ce7 100 /*------------- System Control (SC) ------------------------------------------*/
emilmont 10:3bc89ef62ce7 101 typedef struct
emilmont 10:3bc89ef62ce7 102 {
emilmont 10:3bc89ef62ce7 103 __IO uint32_t MAMCR;
emilmont 10:3bc89ef62ce7 104 __IO uint32_t MAMTIM;
emilmont 10:3bc89ef62ce7 105 uint32_t RESERVED0[14];
emilmont 10:3bc89ef62ce7 106 __IO uint32_t MEMMAP;
emilmont 10:3bc89ef62ce7 107 uint32_t RESERVED1[15];
emilmont 10:3bc89ef62ce7 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
emilmont 10:3bc89ef62ce7 109 __IO uint32_t PLL0CFG;
emilmont 10:3bc89ef62ce7 110 __I uint32_t PLL0STAT;
emilmont 10:3bc89ef62ce7 111 __O uint32_t PLL0FEED;
emilmont 10:3bc89ef62ce7 112 uint32_t RESERVED2[12];
emilmont 10:3bc89ef62ce7 113 __IO uint32_t PCON;
emilmont 10:3bc89ef62ce7 114 __IO uint32_t PCONP;
emilmont 10:3bc89ef62ce7 115 uint32_t RESERVED3[15];
emilmont 10:3bc89ef62ce7 116 __IO uint32_t CCLKCFG;
emilmont 10:3bc89ef62ce7 117 __IO uint32_t USBCLKCFG;
emilmont 10:3bc89ef62ce7 118 __IO uint32_t CLKSRCSEL;
emilmont 10:3bc89ef62ce7 119 uint32_t RESERVED4[12];
emilmont 10:3bc89ef62ce7 120 __IO uint32_t EXTINT; /* External Interrupts */
emilmont 10:3bc89ef62ce7 121 __IO uint32_t INTWAKE;
emilmont 10:3bc89ef62ce7 122 __IO uint32_t EXTMODE;
emilmont 10:3bc89ef62ce7 123 __IO uint32_t EXTPOLAR;
emilmont 10:3bc89ef62ce7 124 uint32_t RESERVED6[12];
emilmont 10:3bc89ef62ce7 125 __IO uint32_t RSID; /* Reset */
emilmont 10:3bc89ef62ce7 126 __IO uint32_t CSPR;
emilmont 10:3bc89ef62ce7 127 __IO uint32_t AHBCFG1;
emilmont 10:3bc89ef62ce7 128 __IO uint32_t AHBCFG2;
emilmont 10:3bc89ef62ce7 129 uint32_t RESERVED7[4];
emilmont 10:3bc89ef62ce7 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
emilmont 10:3bc89ef62ce7 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
emilmont 10:3bc89ef62ce7 132 __IO uint32_t PCLKSEL0;
emilmont 10:3bc89ef62ce7 133 __IO uint32_t PCLKSEL1;
emilmont 10:3bc89ef62ce7 134 uint32_t RESERVED8[4];
emilmont 10:3bc89ef62ce7 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
emilmont 10:3bc89ef62ce7 136 uint32_t RESERVED9;
emilmont 10:3bc89ef62ce7 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
emilmont 10:3bc89ef62ce7 138 } LPC_SC_TypeDef;
emilmont 10:3bc89ef62ce7 139
emilmont 10:3bc89ef62ce7 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
emilmont 10:3bc89ef62ce7 141 typedef struct
emilmont 10:3bc89ef62ce7 142 {
emilmont 10:3bc89ef62ce7 143 __IO uint32_t PINSEL0;
emilmont 10:3bc89ef62ce7 144 __IO uint32_t PINSEL1;
emilmont 10:3bc89ef62ce7 145 __IO uint32_t PINSEL2;
emilmont 10:3bc89ef62ce7 146 __IO uint32_t PINSEL3;
emilmont 10:3bc89ef62ce7 147 __IO uint32_t PINSEL4;
emilmont 10:3bc89ef62ce7 148 __IO uint32_t PINSEL5;
emilmont 10:3bc89ef62ce7 149 __IO uint32_t PINSEL6;
emilmont 10:3bc89ef62ce7 150 __IO uint32_t PINSEL7;
emilmont 10:3bc89ef62ce7 151 __IO uint32_t PINSEL8;
emilmont 10:3bc89ef62ce7 152 __IO uint32_t PINSEL9;
emilmont 10:3bc89ef62ce7 153 __IO uint32_t PINSEL10;
emilmont 10:3bc89ef62ce7 154 uint32_t RESERVED0[5];
emilmont 10:3bc89ef62ce7 155 __IO uint32_t PINMODE0;
emilmont 10:3bc89ef62ce7 156 __IO uint32_t PINMODE1;
emilmont 10:3bc89ef62ce7 157 __IO uint32_t PINMODE2;
emilmont 10:3bc89ef62ce7 158 __IO uint32_t PINMODE3;
emilmont 10:3bc89ef62ce7 159 __IO uint32_t PINMODE4;
emilmont 10:3bc89ef62ce7 160 __IO uint32_t PINMODE5;
emilmont 10:3bc89ef62ce7 161 __IO uint32_t PINMODE6;
emilmont 10:3bc89ef62ce7 162 __IO uint32_t PINMODE7;
emilmont 10:3bc89ef62ce7 163 __IO uint32_t PINMODE8;
emilmont 10:3bc89ef62ce7 164 __IO uint32_t PINMODE9;
emilmont 10:3bc89ef62ce7 165 __IO uint32_t PINMODE_OD0;
emilmont 10:3bc89ef62ce7 166 __IO uint32_t PINMODE_OD1;
emilmont 10:3bc89ef62ce7 167 __IO uint32_t PINMODE_OD2;
emilmont 10:3bc89ef62ce7 168 __IO uint32_t PINMODE_OD3;
emilmont 10:3bc89ef62ce7 169 __IO uint32_t PINMODE_OD4;
emilmont 10:3bc89ef62ce7 170 } LPC_PINCON_TypeDef;
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
emilmont 10:3bc89ef62ce7 173 typedef struct
emilmont 10:3bc89ef62ce7 174 {
emilmont 10:3bc89ef62ce7 175 __IO uint32_t FIODIR;
emilmont 10:3bc89ef62ce7 176 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 177 __IO uint32_t FIOMASK;
emilmont 10:3bc89ef62ce7 178 __IO uint32_t FIOPIN;
emilmont 10:3bc89ef62ce7 179 __IO uint32_t FIOSET;
emilmont 10:3bc89ef62ce7 180 __O uint32_t FIOCLR;
emilmont 10:3bc89ef62ce7 181 } LPC_GPIO_TypeDef;
emilmont 10:3bc89ef62ce7 182
emilmont 10:3bc89ef62ce7 183 typedef struct
emilmont 10:3bc89ef62ce7 184 {
emilmont 10:3bc89ef62ce7 185 __I uint32_t IntStatus;
emilmont 10:3bc89ef62ce7 186 __I uint32_t IO0IntStatR;
emilmont 10:3bc89ef62ce7 187 __I uint32_t IO0IntStatF;
emilmont 10:3bc89ef62ce7 188 __O uint32_t IO0IntClr;
emilmont 10:3bc89ef62ce7 189 __IO uint32_t IO0IntEnR;
emilmont 10:3bc89ef62ce7 190 __IO uint32_t IO0IntEnF;
emilmont 10:3bc89ef62ce7 191 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 192 __I uint32_t IO2IntStatR;
emilmont 10:3bc89ef62ce7 193 __I uint32_t IO2IntStatF;
emilmont 10:3bc89ef62ce7 194 __O uint32_t IO2IntClr;
emilmont 10:3bc89ef62ce7 195 __IO uint32_t IO2IntEnR;
emilmont 10:3bc89ef62ce7 196 __IO uint32_t IO2IntEnF;
emilmont 10:3bc89ef62ce7 197 } LPC_GPIOINT_TypeDef;
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 /*------------- Timer (TIM) --------------------------------------------------*/
emilmont 10:3bc89ef62ce7 200 typedef struct
emilmont 10:3bc89ef62ce7 201 {
emilmont 10:3bc89ef62ce7 202 __IO uint32_t IR;
emilmont 10:3bc89ef62ce7 203 __IO uint32_t TCR;
emilmont 10:3bc89ef62ce7 204 __IO uint32_t TC;
emilmont 10:3bc89ef62ce7 205 __IO uint32_t PR;
emilmont 10:3bc89ef62ce7 206 __IO uint32_t PC;
emilmont 10:3bc89ef62ce7 207 __IO uint32_t MCR;
emilmont 10:3bc89ef62ce7 208 __IO uint32_t MR0;
emilmont 10:3bc89ef62ce7 209 __IO uint32_t MR1;
emilmont 10:3bc89ef62ce7 210 __IO uint32_t MR2;
emilmont 10:3bc89ef62ce7 211 __IO uint32_t MR3;
emilmont 10:3bc89ef62ce7 212 __IO uint32_t CCR;
emilmont 10:3bc89ef62ce7 213 __I uint32_t CR0;
emilmont 10:3bc89ef62ce7 214 __I uint32_t CR1;
emilmont 10:3bc89ef62ce7 215 uint32_t RESERVED0[2];
emilmont 10:3bc89ef62ce7 216 __IO uint32_t EMR;
emilmont 10:3bc89ef62ce7 217 uint32_t RESERVED1[12];
emilmont 10:3bc89ef62ce7 218 __IO uint32_t CTCR;
emilmont 10:3bc89ef62ce7 219 } LPC_TIM_TypeDef;
emilmont 10:3bc89ef62ce7 220
emilmont 10:3bc89ef62ce7 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
emilmont 10:3bc89ef62ce7 222 typedef struct
emilmont 10:3bc89ef62ce7 223 {
emilmont 10:3bc89ef62ce7 224 __IO uint32_t IR;
emilmont 10:3bc89ef62ce7 225 __IO uint32_t TCR;
emilmont 10:3bc89ef62ce7 226 __IO uint32_t TC;
emilmont 10:3bc89ef62ce7 227 __IO uint32_t PR;
emilmont 10:3bc89ef62ce7 228 __IO uint32_t PC;
emilmont 10:3bc89ef62ce7 229 __IO uint32_t MCR;
emilmont 10:3bc89ef62ce7 230 __IO uint32_t MR0;
emilmont 10:3bc89ef62ce7 231 __IO uint32_t MR1;
emilmont 10:3bc89ef62ce7 232 __IO uint32_t MR2;
emilmont 10:3bc89ef62ce7 233 __IO uint32_t MR3;
emilmont 10:3bc89ef62ce7 234 __IO uint32_t CCR;
emilmont 10:3bc89ef62ce7 235 __I uint32_t CR0;
emilmont 10:3bc89ef62ce7 236 __I uint32_t CR1;
emilmont 10:3bc89ef62ce7 237 __I uint32_t CR2;
emilmont 10:3bc89ef62ce7 238 __I uint32_t CR3;
emilmont 10:3bc89ef62ce7 239 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 240 __IO uint32_t MR4;
emilmont 10:3bc89ef62ce7 241 __IO uint32_t MR5;
emilmont 10:3bc89ef62ce7 242 __IO uint32_t MR6;
emilmont 10:3bc89ef62ce7 243 __IO uint32_t PCR;
emilmont 10:3bc89ef62ce7 244 __IO uint32_t LER;
emilmont 10:3bc89ef62ce7 245 uint32_t RESERVED1[7];
emilmont 10:3bc89ef62ce7 246 __IO uint32_t CTCR;
emilmont 10:3bc89ef62ce7 247 } LPC_PWM_TypeDef;
emilmont 10:3bc89ef62ce7 248
emilmont 10:3bc89ef62ce7 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
emilmont 10:3bc89ef62ce7 250 typedef struct
emilmont 10:3bc89ef62ce7 251 {
emilmont 10:3bc89ef62ce7 252 union {
emilmont 10:3bc89ef62ce7 253 __I uint8_t RBR;
emilmont 10:3bc89ef62ce7 254 __O uint8_t THR;
emilmont 10:3bc89ef62ce7 255 __IO uint8_t DLL;
emilmont 10:3bc89ef62ce7 256 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 257 };
emilmont 10:3bc89ef62ce7 258 union {
emilmont 10:3bc89ef62ce7 259 __IO uint8_t DLM;
emilmont 10:3bc89ef62ce7 260 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 261 };
emilmont 10:3bc89ef62ce7 262 union {
emilmont 10:3bc89ef62ce7 263 __I uint32_t IIR;
emilmont 10:3bc89ef62ce7 264 __O uint8_t FCR;
emilmont 10:3bc89ef62ce7 265 };
emilmont 10:3bc89ef62ce7 266 __IO uint8_t LCR;
emilmont 10:3bc89ef62ce7 267 uint8_t RESERVED1[7];
emilmont 10:3bc89ef62ce7 268 __IO uint8_t LSR;
emilmont 10:3bc89ef62ce7 269 uint8_t RESERVED2[7];
emilmont 10:3bc89ef62ce7 270 __IO uint8_t SCR;
emilmont 10:3bc89ef62ce7 271 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 272 __IO uint32_t ACR;
emilmont 10:3bc89ef62ce7 273 __IO uint8_t ICR;
emilmont 10:3bc89ef62ce7 274 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 275 __IO uint8_t FDR;
emilmont 10:3bc89ef62ce7 276 uint8_t RESERVED5[7];
emilmont 10:3bc89ef62ce7 277 __IO uint8_t TER;
emilmont 10:3bc89ef62ce7 278 uint8_t RESERVED6[27];
emilmont 10:3bc89ef62ce7 279 __IO uint8_t RS485CTRL;
emilmont 10:3bc89ef62ce7 280 uint8_t RESERVED7[3];
emilmont 10:3bc89ef62ce7 281 __IO uint8_t ADRMATCH;
emilmont 10:3bc89ef62ce7 282 } LPC_UART_TypeDef;
emilmont 10:3bc89ef62ce7 283
emilmont 10:3bc89ef62ce7 284 typedef struct
emilmont 10:3bc89ef62ce7 285 {
emilmont 10:3bc89ef62ce7 286 union {
emilmont 10:3bc89ef62ce7 287 __I uint8_t RBR;
emilmont 10:3bc89ef62ce7 288 __O uint8_t THR;
emilmont 10:3bc89ef62ce7 289 __IO uint8_t DLL;
emilmont 10:3bc89ef62ce7 290 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 291 };
emilmont 10:3bc89ef62ce7 292 union {
emilmont 10:3bc89ef62ce7 293 __IO uint8_t DLM;
emilmont 10:3bc89ef62ce7 294 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 295 };
emilmont 10:3bc89ef62ce7 296 union {
emilmont 10:3bc89ef62ce7 297 __I uint32_t IIR;
emilmont 10:3bc89ef62ce7 298 __O uint8_t FCR;
emilmont 10:3bc89ef62ce7 299 };
emilmont 10:3bc89ef62ce7 300 __IO uint8_t LCR;
emilmont 10:3bc89ef62ce7 301 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 302 __IO uint8_t MCR;
emilmont 10:3bc89ef62ce7 303 uint8_t RESERVED2[3];
emilmont 10:3bc89ef62ce7 304 __IO uint8_t LSR;
emilmont 10:3bc89ef62ce7 305 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 306 __IO uint8_t MSR;
emilmont 10:3bc89ef62ce7 307 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 308 __IO uint8_t SCR;
emilmont 10:3bc89ef62ce7 309 uint8_t RESERVED5[3];
emilmont 10:3bc89ef62ce7 310 __IO uint32_t ACR;
emilmont 10:3bc89ef62ce7 311 uint32_t RESERVED6;
emilmont 10:3bc89ef62ce7 312 __IO uint32_t FDR;
emilmont 10:3bc89ef62ce7 313 uint32_t RESERVED7;
emilmont 10:3bc89ef62ce7 314 __IO uint8_t TER;
emilmont 10:3bc89ef62ce7 315 uint8_t RESERVED8[27];
emilmont 10:3bc89ef62ce7 316 __IO uint8_t RS485CTRL;
emilmont 10:3bc89ef62ce7 317 uint8_t RESERVED9[3];
emilmont 10:3bc89ef62ce7 318 __IO uint8_t ADRMATCH;
emilmont 10:3bc89ef62ce7 319 uint8_t RESERVED10[3];
emilmont 10:3bc89ef62ce7 320 __IO uint8_t RS485DLY;
emilmont 10:3bc89ef62ce7 321 } LPC_UART1_TypeDef;
emilmont 10:3bc89ef62ce7 322
emilmont 10:3bc89ef62ce7 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
emilmont 10:3bc89ef62ce7 324 typedef struct
emilmont 10:3bc89ef62ce7 325 {
emilmont 10:3bc89ef62ce7 326 __IO uint32_t SPCR;
emilmont 10:3bc89ef62ce7 327 __I uint32_t SPSR;
emilmont 10:3bc89ef62ce7 328 __IO uint32_t SPDR;
emilmont 10:3bc89ef62ce7 329 __IO uint32_t SPCCR;
emilmont 10:3bc89ef62ce7 330 uint32_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 331 __IO uint32_t SPINT;
emilmont 10:3bc89ef62ce7 332 } LPC_SPI_TypeDef;
emilmont 10:3bc89ef62ce7 333
emilmont 10:3bc89ef62ce7 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
emilmont 10:3bc89ef62ce7 335 typedef struct
emilmont 10:3bc89ef62ce7 336 {
emilmont 10:3bc89ef62ce7 337 __IO uint32_t CR0;
emilmont 10:3bc89ef62ce7 338 __IO uint32_t CR1;
emilmont 10:3bc89ef62ce7 339 __IO uint32_t DR;
emilmont 10:3bc89ef62ce7 340 __I uint32_t SR;
emilmont 10:3bc89ef62ce7 341 __IO uint32_t CPSR;
emilmont 10:3bc89ef62ce7 342 __IO uint32_t IMSC;
emilmont 10:3bc89ef62ce7 343 __IO uint32_t RIS;
emilmont 10:3bc89ef62ce7 344 __IO uint32_t MIS;
emilmont 10:3bc89ef62ce7 345 __IO uint32_t ICR;
emilmont 10:3bc89ef62ce7 346 __IO uint32_t DMACR;
emilmont 10:3bc89ef62ce7 347 } LPC_SSP_TypeDef;
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 10:3bc89ef62ce7 350 typedef struct
emilmont 10:3bc89ef62ce7 351 {
emilmont 10:3bc89ef62ce7 352 __IO uint32_t I2CONSET;
emilmont 10:3bc89ef62ce7 353 __I uint32_t I2STAT;
emilmont 10:3bc89ef62ce7 354 __IO uint32_t I2DAT;
emilmont 10:3bc89ef62ce7 355 __IO uint32_t I2ADR0;
emilmont 10:3bc89ef62ce7 356 __IO uint32_t I2SCLH;
emilmont 10:3bc89ef62ce7 357 __IO uint32_t I2SCLL;
emilmont 10:3bc89ef62ce7 358 __O uint32_t I2CONCLR;
emilmont 10:3bc89ef62ce7 359 __IO uint32_t MMCTRL;
emilmont 10:3bc89ef62ce7 360 __IO uint32_t I2ADR1;
emilmont 10:3bc89ef62ce7 361 __IO uint32_t I2ADR2;
emilmont 10:3bc89ef62ce7 362 __IO uint32_t I2ADR3;
emilmont 10:3bc89ef62ce7 363 __I uint32_t I2DATA_BUFFER;
emilmont 10:3bc89ef62ce7 364 __IO uint32_t I2MASK0;
emilmont 10:3bc89ef62ce7 365 __IO uint32_t I2MASK1;
emilmont 10:3bc89ef62ce7 366 __IO uint32_t I2MASK2;
emilmont 10:3bc89ef62ce7 367 __IO uint32_t I2MASK3;
emilmont 10:3bc89ef62ce7 368 } LPC_I2C_TypeDef;
emilmont 10:3bc89ef62ce7 369
emilmont 10:3bc89ef62ce7 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 371 typedef struct
emilmont 10:3bc89ef62ce7 372 {
emilmont 10:3bc89ef62ce7 373 __IO uint32_t I2SDAO;
emilmont 10:3bc89ef62ce7 374 __I uint32_t I2SDAI;
emilmont 10:3bc89ef62ce7 375 __O uint32_t I2STXFIFO;
emilmont 10:3bc89ef62ce7 376 __I uint32_t I2SRXFIFO;
emilmont 10:3bc89ef62ce7 377 __I uint32_t I2SSTATE;
emilmont 10:3bc89ef62ce7 378 __IO uint32_t I2SDMA1;
emilmont 10:3bc89ef62ce7 379 __IO uint32_t I2SDMA2;
emilmont 10:3bc89ef62ce7 380 __IO uint32_t I2SIRQ;
emilmont 10:3bc89ef62ce7 381 __IO uint32_t I2STXRATE;
emilmont 10:3bc89ef62ce7 382 __IO uint32_t I2SRXRATE;
emilmont 10:3bc89ef62ce7 383 __IO uint32_t I2STXBITRATE;
emilmont 10:3bc89ef62ce7 384 __IO uint32_t I2SRXBITRATE;
emilmont 10:3bc89ef62ce7 385 __IO uint32_t I2STXMODE;
emilmont 10:3bc89ef62ce7 386 __IO uint32_t I2SRXMODE;
emilmont 10:3bc89ef62ce7 387 } LPC_I2S_TypeDef;
emilmont 10:3bc89ef62ce7 388
emilmont 10:3bc89ef62ce7 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
emilmont 10:3bc89ef62ce7 390 typedef struct
emilmont 10:3bc89ef62ce7 391 {
emilmont 10:3bc89ef62ce7 392 __IO uint8_t ILR;
emilmont 10:3bc89ef62ce7 393 uint8_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 394 __IO uint8_t CTC;
emilmont 10:3bc89ef62ce7 395 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 396 __IO uint8_t CCR;
emilmont 10:3bc89ef62ce7 397 uint8_t RESERVED2[3];
emilmont 10:3bc89ef62ce7 398 __IO uint8_t CIIR;
emilmont 10:3bc89ef62ce7 399 uint8_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 400 __IO uint8_t AMR;
emilmont 10:3bc89ef62ce7 401 uint8_t RESERVED4[3];
emilmont 10:3bc89ef62ce7 402 __I uint32_t CTIME0;
emilmont 10:3bc89ef62ce7 403 __I uint32_t CTIME1;
emilmont 10:3bc89ef62ce7 404 __I uint32_t CTIME2;
emilmont 10:3bc89ef62ce7 405 __IO uint8_t SEC;
emilmont 10:3bc89ef62ce7 406 uint8_t RESERVED5[3];
emilmont 10:3bc89ef62ce7 407 __IO uint8_t MIN;
emilmont 10:3bc89ef62ce7 408 uint8_t RESERVED6[3];
emilmont 10:3bc89ef62ce7 409 __IO uint8_t HOUR;
emilmont 10:3bc89ef62ce7 410 uint8_t RESERVED7[3];
emilmont 10:3bc89ef62ce7 411 __IO uint8_t DOM;
emilmont 10:3bc89ef62ce7 412 uint8_t RESERVED8[3];
emilmont 10:3bc89ef62ce7 413 __IO uint8_t DOW;
emilmont 10:3bc89ef62ce7 414 uint8_t RESERVED9[3];
emilmont 10:3bc89ef62ce7 415 __IO uint16_t DOY;
emilmont 10:3bc89ef62ce7 416 uint16_t RESERVED10;
emilmont 10:3bc89ef62ce7 417 __IO uint8_t MONTH;
emilmont 10:3bc89ef62ce7 418 uint8_t RESERVED11[3];
emilmont 10:3bc89ef62ce7 419 __IO uint16_t YEAR;
emilmont 10:3bc89ef62ce7 420 uint16_t RESERVED12;
emilmont 10:3bc89ef62ce7 421 __IO uint32_t CALIBRATION;
emilmont 10:3bc89ef62ce7 422 __IO uint32_t GPREG0;
emilmont 10:3bc89ef62ce7 423 __IO uint32_t GPREG1;
emilmont 10:3bc89ef62ce7 424 __IO uint32_t GPREG2;
emilmont 10:3bc89ef62ce7 425 __IO uint32_t GPREG3;
emilmont 10:3bc89ef62ce7 426 __IO uint32_t GPREG4;
emilmont 10:3bc89ef62ce7 427 __IO uint8_t WAKEUPDIS;
emilmont 10:3bc89ef62ce7 428 uint8_t RESERVED13[3];
emilmont 10:3bc89ef62ce7 429 __IO uint8_t PWRCTRL;
emilmont 10:3bc89ef62ce7 430 uint8_t RESERVED14[3];
emilmont 10:3bc89ef62ce7 431 __IO uint8_t ALSEC;
emilmont 10:3bc89ef62ce7 432 uint8_t RESERVED15[3];
emilmont 10:3bc89ef62ce7 433 __IO uint8_t ALMIN;
emilmont 10:3bc89ef62ce7 434 uint8_t RESERVED16[3];
emilmont 10:3bc89ef62ce7 435 __IO uint8_t ALHOUR;
emilmont 10:3bc89ef62ce7 436 uint8_t RESERVED17[3];
emilmont 10:3bc89ef62ce7 437 __IO uint8_t ALDOM;
emilmont 10:3bc89ef62ce7 438 uint8_t RESERVED18[3];
emilmont 10:3bc89ef62ce7 439 __IO uint8_t ALDOW;
emilmont 10:3bc89ef62ce7 440 uint8_t RESERVED19[3];
emilmont 10:3bc89ef62ce7 441 __IO uint16_t ALDOY;
emilmont 10:3bc89ef62ce7 442 uint16_t RESERVED20;
emilmont 10:3bc89ef62ce7 443 __IO uint8_t ALMON;
emilmont 10:3bc89ef62ce7 444 uint8_t RESERVED21[3];
emilmont 10:3bc89ef62ce7 445 __IO uint16_t ALYEAR;
emilmont 10:3bc89ef62ce7 446 uint16_t RESERVED22;
emilmont 10:3bc89ef62ce7 447 } LPC_RTC_TypeDef;
emilmont 10:3bc89ef62ce7 448
emilmont 10:3bc89ef62ce7 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
emilmont 10:3bc89ef62ce7 450 typedef struct
emilmont 10:3bc89ef62ce7 451 {
emilmont 10:3bc89ef62ce7 452 __IO uint8_t WDMOD;
emilmont 10:3bc89ef62ce7 453 uint8_t RESERVED0[3];
emilmont 10:3bc89ef62ce7 454 __IO uint32_t WDTC;
emilmont 10:3bc89ef62ce7 455 __O uint8_t WDFEED;
emilmont 10:3bc89ef62ce7 456 uint8_t RESERVED1[3];
emilmont 10:3bc89ef62ce7 457 __I uint32_t WDTV;
emilmont 10:3bc89ef62ce7 458 __IO uint32_t WDCLKSEL;
emilmont 10:3bc89ef62ce7 459 } LPC_WDT_TypeDef;
emilmont 10:3bc89ef62ce7 460
emilmont 10:3bc89ef62ce7 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
emilmont 10:3bc89ef62ce7 462 typedef struct
emilmont 10:3bc89ef62ce7 463 {
emilmont 10:3bc89ef62ce7 464 __IO uint32_t ADCR;
emilmont 10:3bc89ef62ce7 465 __IO uint32_t ADGDR;
emilmont 10:3bc89ef62ce7 466 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 467 __IO uint32_t ADINTEN;
emilmont 10:3bc89ef62ce7 468 __I uint32_t ADDR0;
emilmont 10:3bc89ef62ce7 469 __I uint32_t ADDR1;
emilmont 10:3bc89ef62ce7 470 __I uint32_t ADDR2;
emilmont 10:3bc89ef62ce7 471 __I uint32_t ADDR3;
emilmont 10:3bc89ef62ce7 472 __I uint32_t ADDR4;
emilmont 10:3bc89ef62ce7 473 __I uint32_t ADDR5;
emilmont 10:3bc89ef62ce7 474 __I uint32_t ADDR6;
emilmont 10:3bc89ef62ce7 475 __I uint32_t ADDR7;
emilmont 10:3bc89ef62ce7 476 __I uint32_t ADSTAT;
emilmont 10:3bc89ef62ce7 477 __IO uint32_t ADTRM;
emilmont 10:3bc89ef62ce7 478 } LPC_ADC_TypeDef;
emilmont 10:3bc89ef62ce7 479
emilmont 10:3bc89ef62ce7 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
emilmont 10:3bc89ef62ce7 481 typedef struct
emilmont 10:3bc89ef62ce7 482 {
emilmont 10:3bc89ef62ce7 483 __IO uint32_t DACR;
emilmont 10:3bc89ef62ce7 484 __IO uint32_t DACCTRL;
emilmont 10:3bc89ef62ce7 485 __IO uint16_t DACCNTVAL;
emilmont 10:3bc89ef62ce7 486 } LPC_DAC_TypeDef;
emilmont 10:3bc89ef62ce7 487
emilmont 10:3bc89ef62ce7 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
emilmont 10:3bc89ef62ce7 489 typedef struct
emilmont 10:3bc89ef62ce7 490 {
emilmont 10:3bc89ef62ce7 491 __IO uint32_t MCIPower; /* Power control */
emilmont 10:3bc89ef62ce7 492 __IO uint32_t MCIClock; /* Clock control */
emilmont 10:3bc89ef62ce7 493 __IO uint32_t MCIArgument;
emilmont 10:3bc89ef62ce7 494 __IO uint32_t MMCCommand;
emilmont 10:3bc89ef62ce7 495 __I uint32_t MCIRespCmd;
emilmont 10:3bc89ef62ce7 496 __I uint32_t MCIResponse0;
emilmont 10:3bc89ef62ce7 497 __I uint32_t MCIResponse1;
emilmont 10:3bc89ef62ce7 498 __I uint32_t MCIResponse2;
emilmont 10:3bc89ef62ce7 499 __I uint32_t MCIResponse3;
emilmont 10:3bc89ef62ce7 500 __IO uint32_t MCIDataTimer;
emilmont 10:3bc89ef62ce7 501 __IO uint32_t MCIDataLength;
emilmont 10:3bc89ef62ce7 502 __IO uint32_t MCIDataCtrl;
emilmont 10:3bc89ef62ce7 503 __I uint32_t MCIDataCnt;
emilmont 10:3bc89ef62ce7 504 } LPC_MCI_TypeDef;
emilmont 10:3bc89ef62ce7 505
emilmont 10:3bc89ef62ce7 506 /*------------- Controller Area Network (CAN) --------------------------------*/
emilmont 10:3bc89ef62ce7 507 typedef struct
emilmont 10:3bc89ef62ce7 508 {
emilmont 10:3bc89ef62ce7 509 __IO uint32_t mask[512]; /* ID Masks */
emilmont 10:3bc89ef62ce7 510 } LPC_CANAF_RAM_TypeDef;
emilmont 10:3bc89ef62ce7 511
emilmont 10:3bc89ef62ce7 512 typedef struct /* Acceptance Filter Registers */
emilmont 10:3bc89ef62ce7 513 {
emilmont 10:3bc89ef62ce7 514 __IO uint32_t AFMR;
emilmont 10:3bc89ef62ce7 515 __IO uint32_t SFF_sa;
emilmont 10:3bc89ef62ce7 516 __IO uint32_t SFF_GRP_sa;
emilmont 10:3bc89ef62ce7 517 __IO uint32_t EFF_sa;
emilmont 10:3bc89ef62ce7 518 __IO uint32_t EFF_GRP_sa;
emilmont 10:3bc89ef62ce7 519 __IO uint32_t ENDofTable;
emilmont 10:3bc89ef62ce7 520 __I uint32_t LUTerrAd;
emilmont 10:3bc89ef62ce7 521 __I uint32_t LUTerr;
emilmont 10:3bc89ef62ce7 522 } LPC_CANAF_TypeDef;
emilmont 10:3bc89ef62ce7 523
emilmont 10:3bc89ef62ce7 524 typedef struct /* Central Registers */
emilmont 10:3bc89ef62ce7 525 {
emilmont 10:3bc89ef62ce7 526 __I uint32_t CANTxSR;
emilmont 10:3bc89ef62ce7 527 __I uint32_t CANRxSR;
emilmont 10:3bc89ef62ce7 528 __I uint32_t CANMSR;
emilmont 10:3bc89ef62ce7 529 } LPC_CANCR_TypeDef;
emilmont 10:3bc89ef62ce7 530
emilmont 10:3bc89ef62ce7 531 typedef struct /* Controller Registers */
emilmont 10:3bc89ef62ce7 532 {
emilmont 10:3bc89ef62ce7 533 __IO uint32_t MOD;
emilmont 10:3bc89ef62ce7 534 __O uint32_t CMR;
emilmont 10:3bc89ef62ce7 535 __IO uint32_t GSR;
emilmont 10:3bc89ef62ce7 536 __I uint32_t ICR;
emilmont 10:3bc89ef62ce7 537 __IO uint32_t IER;
emilmont 10:3bc89ef62ce7 538 __IO uint32_t BTR;
emilmont 10:3bc89ef62ce7 539 __IO uint32_t EWL;
emilmont 10:3bc89ef62ce7 540 __I uint32_t SR;
emilmont 10:3bc89ef62ce7 541 __IO uint32_t RFS;
emilmont 10:3bc89ef62ce7 542 __IO uint32_t RID;
emilmont 10:3bc89ef62ce7 543 __IO uint32_t RDA;
emilmont 10:3bc89ef62ce7 544 __IO uint32_t RDB;
emilmont 10:3bc89ef62ce7 545 __IO uint32_t TFI1;
emilmont 10:3bc89ef62ce7 546 __IO uint32_t TID1;
emilmont 10:3bc89ef62ce7 547 __IO uint32_t TDA1;
emilmont 10:3bc89ef62ce7 548 __IO uint32_t TDB1;
emilmont 10:3bc89ef62ce7 549 __IO uint32_t TFI2;
emilmont 10:3bc89ef62ce7 550 __IO uint32_t TID2;
emilmont 10:3bc89ef62ce7 551 __IO uint32_t TDA2;
emilmont 10:3bc89ef62ce7 552 __IO uint32_t TDB2;
emilmont 10:3bc89ef62ce7 553 __IO uint32_t TFI3;
emilmont 10:3bc89ef62ce7 554 __IO uint32_t TID3;
emilmont 10:3bc89ef62ce7 555 __IO uint32_t TDA3;
emilmont 10:3bc89ef62ce7 556 __IO uint32_t TDB3;
emilmont 10:3bc89ef62ce7 557 } LPC_CAN_TypeDef;
emilmont 10:3bc89ef62ce7 558
emilmont 10:3bc89ef62ce7 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
emilmont 10:3bc89ef62ce7 560 typedef struct /* Common Registers */
emilmont 10:3bc89ef62ce7 561 {
emilmont 10:3bc89ef62ce7 562 __I uint32_t DMACIntStat;
emilmont 10:3bc89ef62ce7 563 __I uint32_t DMACIntTCStat;
emilmont 10:3bc89ef62ce7 564 __O uint32_t DMACIntTCClear;
emilmont 10:3bc89ef62ce7 565 __I uint32_t DMACIntErrStat;
emilmont 10:3bc89ef62ce7 566 __O uint32_t DMACIntErrClr;
emilmont 10:3bc89ef62ce7 567 __I uint32_t DMACRawIntTCStat;
emilmont 10:3bc89ef62ce7 568 __I uint32_t DMACRawIntErrStat;
emilmont 10:3bc89ef62ce7 569 __I uint32_t DMACEnbldChns;
emilmont 10:3bc89ef62ce7 570 __IO uint32_t DMACSoftBReq;
emilmont 10:3bc89ef62ce7 571 __IO uint32_t DMACSoftSReq;
emilmont 10:3bc89ef62ce7 572 __IO uint32_t DMACSoftLBReq;
emilmont 10:3bc89ef62ce7 573 __IO uint32_t DMACSoftLSReq;
emilmont 10:3bc89ef62ce7 574 __IO uint32_t DMACConfig;
emilmont 10:3bc89ef62ce7 575 __IO uint32_t DMACSync;
emilmont 10:3bc89ef62ce7 576 } LPC_GPDMA_TypeDef;
emilmont 10:3bc89ef62ce7 577
emilmont 10:3bc89ef62ce7 578 typedef struct /* Channel Registers */
emilmont 10:3bc89ef62ce7 579 {
emilmont 10:3bc89ef62ce7 580 __IO uint32_t DMACCSrcAddr;
emilmont 10:3bc89ef62ce7 581 __IO uint32_t DMACCDestAddr;
emilmont 10:3bc89ef62ce7 582 __IO uint32_t DMACCLLI;
emilmont 10:3bc89ef62ce7 583 __IO uint32_t DMACCControl;
emilmont 10:3bc89ef62ce7 584 __IO uint32_t DMACCConfig;
emilmont 10:3bc89ef62ce7 585 } LPC_GPDMACH_TypeDef;
emilmont 10:3bc89ef62ce7 586
emilmont 10:3bc89ef62ce7 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
emilmont 10:3bc89ef62ce7 588 typedef struct
emilmont 10:3bc89ef62ce7 589 {
emilmont 10:3bc89ef62ce7 590 __I uint32_t HcRevision; /* USB Host Registers */
emilmont 10:3bc89ef62ce7 591 __IO uint32_t HcControl;
emilmont 10:3bc89ef62ce7 592 __IO uint32_t HcCommandStatus;
emilmont 10:3bc89ef62ce7 593 __IO uint32_t HcInterruptStatus;
emilmont 10:3bc89ef62ce7 594 __IO uint32_t HcInterruptEnable;
emilmont 10:3bc89ef62ce7 595 __IO uint32_t HcInterruptDisable;
emilmont 10:3bc89ef62ce7 596 __IO uint32_t HcHCCA;
emilmont 10:3bc89ef62ce7 597 __I uint32_t HcPeriodCurrentED;
emilmont 10:3bc89ef62ce7 598 __IO uint32_t HcControlHeadED;
emilmont 10:3bc89ef62ce7 599 __IO uint32_t HcControlCurrentED;
emilmont 10:3bc89ef62ce7 600 __IO uint32_t HcBulkHeadED;
emilmont 10:3bc89ef62ce7 601 __IO uint32_t HcBulkCurrentED;
emilmont 10:3bc89ef62ce7 602 __I uint32_t HcDoneHead;
emilmont 10:3bc89ef62ce7 603 __IO uint32_t HcFmInterval;
emilmont 10:3bc89ef62ce7 604 __I uint32_t HcFmRemaining;
emilmont 10:3bc89ef62ce7 605 __I uint32_t HcFmNumber;
emilmont 10:3bc89ef62ce7 606 __IO uint32_t HcPeriodicStart;
emilmont 10:3bc89ef62ce7 607 __IO uint32_t HcLSTreshold;
emilmont 10:3bc89ef62ce7 608 __IO uint32_t HcRhDescriptorA;
emilmont 10:3bc89ef62ce7 609 __IO uint32_t HcRhDescriptorB;
emilmont 10:3bc89ef62ce7 610 __IO uint32_t HcRhStatus;
emilmont 10:3bc89ef62ce7 611 __IO uint32_t HcRhPortStatus1;
emilmont 10:3bc89ef62ce7 612 __IO uint32_t HcRhPortStatus2;
emilmont 10:3bc89ef62ce7 613 uint32_t RESERVED0[40];
emilmont 10:3bc89ef62ce7 614 __I uint32_t Module_ID;
emilmont 10:3bc89ef62ce7 615
emilmont 10:3bc89ef62ce7 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
emilmont 10:3bc89ef62ce7 617 __IO uint32_t OTGIntEn;
emilmont 10:3bc89ef62ce7 618 __O uint32_t OTGIntSet;
emilmont 10:3bc89ef62ce7 619 __O uint32_t OTGIntClr;
emilmont 10:3bc89ef62ce7 620 __IO uint32_t OTGStCtrl;
emilmont 10:3bc89ef62ce7 621 __IO uint32_t OTGTmr;
emilmont 10:3bc89ef62ce7 622 uint32_t RESERVED1[58];
emilmont 10:3bc89ef62ce7 623
emilmont 10:3bc89ef62ce7 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
emilmont 10:3bc89ef62ce7 625 __IO uint32_t USBDevIntEn;
emilmont 10:3bc89ef62ce7 626 __O uint32_t USBDevIntClr;
emilmont 10:3bc89ef62ce7 627 __O uint32_t USBDevIntSet;
emilmont 10:3bc89ef62ce7 628
emilmont 10:3bc89ef62ce7 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
emilmont 10:3bc89ef62ce7 630 __I uint32_t USBCmdData;
emilmont 10:3bc89ef62ce7 631
emilmont 10:3bc89ef62ce7 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
emilmont 10:3bc89ef62ce7 633 __O uint32_t USBTxData;
emilmont 10:3bc89ef62ce7 634 __I uint32_t USBRxPLen;
emilmont 10:3bc89ef62ce7 635 __O uint32_t USBTxPLen;
emilmont 10:3bc89ef62ce7 636 __IO uint32_t USBCtrl;
emilmont 10:3bc89ef62ce7 637 __O uint32_t USBDevIntPri;
emilmont 10:3bc89ef62ce7 638
emilmont 10:3bc89ef62ce7 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
emilmont 10:3bc89ef62ce7 640 __IO uint32_t USBEpIntEn;
emilmont 10:3bc89ef62ce7 641 __O uint32_t USBEpIntClr;
emilmont 10:3bc89ef62ce7 642 __O uint32_t USBEpIntSet;
emilmont 10:3bc89ef62ce7 643 __O uint32_t USBEpIntPri;
emilmont 10:3bc89ef62ce7 644
emilmont 10:3bc89ef62ce7 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
emilmont 10:3bc89ef62ce7 646 __O uint32_t USBEpInd;
emilmont 10:3bc89ef62ce7 647 __IO uint32_t USBMaxPSize;
emilmont 10:3bc89ef62ce7 648
emilmont 10:3bc89ef62ce7 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
emilmont 10:3bc89ef62ce7 650 __O uint32_t USBDMARClr;
emilmont 10:3bc89ef62ce7 651 __O uint32_t USBDMARSet;
emilmont 10:3bc89ef62ce7 652 uint32_t RESERVED2[9];
emilmont 10:3bc89ef62ce7 653 __IO uint32_t USBUDCAH;
emilmont 10:3bc89ef62ce7 654 __I uint32_t USBEpDMASt;
emilmont 10:3bc89ef62ce7 655 __O uint32_t USBEpDMAEn;
emilmont 10:3bc89ef62ce7 656 __O uint32_t USBEpDMADis;
emilmont 10:3bc89ef62ce7 657 __I uint32_t USBDMAIntSt;
emilmont 10:3bc89ef62ce7 658 __IO uint32_t USBDMAIntEn;
emilmont 10:3bc89ef62ce7 659 uint32_t RESERVED3[2];
emilmont 10:3bc89ef62ce7 660 __I uint32_t USBEoTIntSt;
emilmont 10:3bc89ef62ce7 661 __O uint32_t USBEoTIntClr;
emilmont 10:3bc89ef62ce7 662 __O uint32_t USBEoTIntSet;
emilmont 10:3bc89ef62ce7 663 __I uint32_t USBNDDRIntSt;
emilmont 10:3bc89ef62ce7 664 __O uint32_t USBNDDRIntClr;
emilmont 10:3bc89ef62ce7 665 __O uint32_t USBNDDRIntSet;
emilmont 10:3bc89ef62ce7 666 __I uint32_t USBSysErrIntSt;
emilmont 10:3bc89ef62ce7 667 __O uint32_t USBSysErrIntClr;
emilmont 10:3bc89ef62ce7 668 __O uint32_t USBSysErrIntSet;
emilmont 10:3bc89ef62ce7 669 uint32_t RESERVED4[15];
emilmont 10:3bc89ef62ce7 670
emilmont 10:3bc89ef62ce7 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
emilmont 10:3bc89ef62ce7 672 __O uint32_t I2C_WO;
emilmont 10:3bc89ef62ce7 673 __I uint32_t I2C_STS;
emilmont 10:3bc89ef62ce7 674 __IO uint32_t I2C_CTL;
emilmont 10:3bc89ef62ce7 675 __IO uint32_t I2C_CLKHI;
emilmont 10:3bc89ef62ce7 676 __O uint32_t I2C_CLKLO;
emilmont 10:3bc89ef62ce7 677 uint32_t RESERVED5[823];
emilmont 10:3bc89ef62ce7 678
emilmont 10:3bc89ef62ce7 679 union {
emilmont 10:3bc89ef62ce7 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
emilmont 10:3bc89ef62ce7 681 __IO uint32_t OTGClkCtrl;
emilmont 10:3bc89ef62ce7 682 };
emilmont 10:3bc89ef62ce7 683 union {
emilmont 10:3bc89ef62ce7 684 __I uint32_t USBClkSt;
emilmont 10:3bc89ef62ce7 685 __I uint32_t OTGClkSt;
emilmont 10:3bc89ef62ce7 686 };
emilmont 10:3bc89ef62ce7 687 } LPC_USB_TypeDef;
emilmont 10:3bc89ef62ce7 688
emilmont 10:3bc89ef62ce7 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
emilmont 10:3bc89ef62ce7 690 typedef struct
emilmont 10:3bc89ef62ce7 691 {
emilmont 10:3bc89ef62ce7 692 __IO uint32_t MAC1; /* MAC Registers */
emilmont 10:3bc89ef62ce7 693 __IO uint32_t MAC2;
emilmont 10:3bc89ef62ce7 694 __IO uint32_t IPGT;
emilmont 10:3bc89ef62ce7 695 __IO uint32_t IPGR;
emilmont 10:3bc89ef62ce7 696 __IO uint32_t CLRT;
emilmont 10:3bc89ef62ce7 697 __IO uint32_t MAXF;
emilmont 10:3bc89ef62ce7 698 __IO uint32_t SUPP;
emilmont 10:3bc89ef62ce7 699 __IO uint32_t TEST;
emilmont 10:3bc89ef62ce7 700 __IO uint32_t MCFG;
emilmont 10:3bc89ef62ce7 701 __IO uint32_t MCMD;
emilmont 10:3bc89ef62ce7 702 __IO uint32_t MADR;
emilmont 10:3bc89ef62ce7 703 __O uint32_t MWTD;
emilmont 10:3bc89ef62ce7 704 __I uint32_t MRDD;
emilmont 10:3bc89ef62ce7 705 __I uint32_t MIND;
emilmont 10:3bc89ef62ce7 706 uint32_t RESERVED0[2];
emilmont 10:3bc89ef62ce7 707 __IO uint32_t SA0;
emilmont 10:3bc89ef62ce7 708 __IO uint32_t SA1;
emilmont 10:3bc89ef62ce7 709 __IO uint32_t SA2;
emilmont 10:3bc89ef62ce7 710 uint32_t RESERVED1[45];
emilmont 10:3bc89ef62ce7 711 __IO uint32_t Command; /* Control Registers */
emilmont 10:3bc89ef62ce7 712 __I uint32_t Status;
emilmont 10:3bc89ef62ce7 713 __IO uint32_t RxDescriptor;
emilmont 10:3bc89ef62ce7 714 __IO uint32_t RxStatus;
emilmont 10:3bc89ef62ce7 715 __IO uint32_t RxDescriptorNumber;
emilmont 10:3bc89ef62ce7 716 __I uint32_t RxProduceIndex;
emilmont 10:3bc89ef62ce7 717 __IO uint32_t RxConsumeIndex;
emilmont 10:3bc89ef62ce7 718 __IO uint32_t TxDescriptor;
emilmont 10:3bc89ef62ce7 719 __IO uint32_t TxStatus;
emilmont 10:3bc89ef62ce7 720 __IO uint32_t TxDescriptorNumber;
emilmont 10:3bc89ef62ce7 721 __IO uint32_t TxProduceIndex;
emilmont 10:3bc89ef62ce7 722 __I uint32_t TxConsumeIndex;
emilmont 10:3bc89ef62ce7 723 uint32_t RESERVED2[10];
emilmont 10:3bc89ef62ce7 724 __I uint32_t TSV0;
emilmont 10:3bc89ef62ce7 725 __I uint32_t TSV1;
emilmont 10:3bc89ef62ce7 726 __I uint32_t RSV;
emilmont 10:3bc89ef62ce7 727 uint32_t RESERVED3[3];
emilmont 10:3bc89ef62ce7 728 __IO uint32_t FlowControlCounter;
emilmont 10:3bc89ef62ce7 729 __I uint32_t FlowControlStatus;
emilmont 10:3bc89ef62ce7 730 uint32_t RESERVED4[34];
emilmont 10:3bc89ef62ce7 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
emilmont 10:3bc89ef62ce7 732 __IO uint32_t RxFilterWoLStatus;
emilmont 10:3bc89ef62ce7 733 __IO uint32_t RxFilterWoLClear;
emilmont 10:3bc89ef62ce7 734 uint32_t RESERVED5;
emilmont 10:3bc89ef62ce7 735 __IO uint32_t HashFilterL;
emilmont 10:3bc89ef62ce7 736 __IO uint32_t HashFilterH;
emilmont 10:3bc89ef62ce7 737 uint32_t RESERVED6[882];
emilmont 10:3bc89ef62ce7 738 __I uint32_t IntStatus; /* Module Control Registers */
emilmont 10:3bc89ef62ce7 739 __IO uint32_t IntEnable;
emilmont 10:3bc89ef62ce7 740 __O uint32_t IntClear;
emilmont 10:3bc89ef62ce7 741 __O uint32_t IntSet;
emilmont 10:3bc89ef62ce7 742 uint32_t RESERVED7;
emilmont 10:3bc89ef62ce7 743 __IO uint32_t PowerDown;
emilmont 10:3bc89ef62ce7 744 uint32_t RESERVED8;
emilmont 10:3bc89ef62ce7 745 __IO uint32_t Module_ID;
emilmont 10:3bc89ef62ce7 746 } LPC_EMAC_TypeDef;
emilmont 10:3bc89ef62ce7 747
emilmont 10:3bc89ef62ce7 748 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 749 #pragma no_anon_unions
emilmont 10:3bc89ef62ce7 750 #endif
emilmont 10:3bc89ef62ce7 751
emilmont 10:3bc89ef62ce7 752 /******************************************************************************/
emilmont 10:3bc89ef62ce7 753 /* Peripheral memory map */
emilmont 10:3bc89ef62ce7 754 /******************************************************************************/
emilmont 10:3bc89ef62ce7 755 /* Base addresses */
emilmont 10:3bc89ef62ce7 756
emilmont 10:3bc89ef62ce7 757 /* AHB Peripheral # 0 */
emilmont 10:3bc89ef62ce7 758
emilmont 10:3bc89ef62ce7 759 /*
emilmont 10:3bc89ef62ce7 760 #define FLASH_BASE (0x00000000UL)
emilmont 10:3bc89ef62ce7 761 #define RAM_BASE (0x10000000UL)
emilmont 10:3bc89ef62ce7 762 #define GPIO_BASE (0x2009C000UL)
emilmont 10:3bc89ef62ce7 763 #define APB0_BASE (0x40000000UL)
emilmont 10:3bc89ef62ce7 764 #define APB1_BASE (0x40080000UL)
emilmont 10:3bc89ef62ce7 765 #define AHB_BASE (0x50000000UL)
emilmont 10:3bc89ef62ce7 766 #define CM3_BASE (0xE0000000UL)
emilmont 10:3bc89ef62ce7 767 */
emilmont 10:3bc89ef62ce7 768
emilmont 10:3bc89ef62ce7 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
emilmont 10:3bc89ef62ce7 770
emilmont 10:3bc89ef62ce7 771 #define LPC_WDT_BASE (0xE0000000)
emilmont 10:3bc89ef62ce7 772 #define LPC_TIM0_BASE (0xE0004000)
emilmont 10:3bc89ef62ce7 773 #define LPC_TIM1_BASE (0xE0008000)
emilmont 10:3bc89ef62ce7 774 #define LPC_UART0_BASE (0xE000C000)
emilmont 10:3bc89ef62ce7 775 #define LPC_UART1_BASE (0xE0010000)
emilmont 10:3bc89ef62ce7 776 #define LPC_PWM1_BASE (0xE0018000)
emilmont 10:3bc89ef62ce7 777 #define LPC_I2C0_BASE (0xE001C000)
emilmont 10:3bc89ef62ce7 778 #define LPC_SPI_BASE (0xE0020000)
emilmont 10:3bc89ef62ce7 779 #define LPC_RTC_BASE (0xE0024000)
emilmont 10:3bc89ef62ce7 780 #define LPC_GPIOINT_BASE (0xE0028080)
emilmont 10:3bc89ef62ce7 781 #define LPC_PINCON_BASE (0xE002C000)
emilmont 10:3bc89ef62ce7 782 #define LPC_SSP1_BASE (0xE0030000)
emilmont 10:3bc89ef62ce7 783 #define LPC_ADC_BASE (0xE0034000)
emilmont 10:3bc89ef62ce7 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
emilmont 10:3bc89ef62ce7 785 #define LPC_CANAF_BASE (0xE003C000)
emilmont 10:3bc89ef62ce7 786 #define LPC_CANCR_BASE (0xE0040000)
emilmont 10:3bc89ef62ce7 787 #define LPC_CAN1_BASE (0xE0044000)
emilmont 10:3bc89ef62ce7 788 #define LPC_CAN2_BASE (0xE0048000)
emilmont 10:3bc89ef62ce7 789 #define LPC_I2C1_BASE (0xE005C000)
emilmont 10:3bc89ef62ce7 790 #define LPC_SSP0_BASE (0xE0068000)
emilmont 10:3bc89ef62ce7 791 #define LPC_DAC_BASE (0xE006C000)
emilmont 10:3bc89ef62ce7 792 #define LPC_TIM2_BASE (0xE0070000)
emilmont 10:3bc89ef62ce7 793 #define LPC_TIM3_BASE (0xE0074000)
emilmont 10:3bc89ef62ce7 794 #define LPC_UART2_BASE (0xE0078000)
emilmont 10:3bc89ef62ce7 795 #define LPC_UART3_BASE (0xE007C000)
emilmont 10:3bc89ef62ce7 796 #define LPC_I2C2_BASE (0xE0080000)
emilmont 10:3bc89ef62ce7 797 #define LPC_I2S_BASE (0xE0088000)
emilmont 10:3bc89ef62ce7 798 #define LPC_MCI_BASE (0xE008C000)
emilmont 10:3bc89ef62ce7 799 #define LPC_SC_BASE (0xE01FC000)
emilmont 10:3bc89ef62ce7 800 #define LPC_EMAC_BASE (0xFFE00000)
emilmont 10:3bc89ef62ce7 801 #define LPC_GPDMA_BASE (0xFFE04000)
emilmont 10:3bc89ef62ce7 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
emilmont 10:3bc89ef62ce7 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
emilmont 10:3bc89ef62ce7 804 #define LPC_USB_BASE (0xFFE0C000)
emilmont 10:3bc89ef62ce7 805 #define LPC_VIC_BASE (0xFFFFF000)
emilmont 10:3bc89ef62ce7 806
emilmont 10:3bc89ef62ce7 807 /* GPIOs */
emilmont 10:3bc89ef62ce7 808 #define LPC_GPIO0_BASE (0x3FFFC000)
emilmont 10:3bc89ef62ce7 809 #define LPC_GPIO1_BASE (0x3FFFC020)
emilmont 10:3bc89ef62ce7 810 #define LPC_GPIO2_BASE (0x3FFFC040)
emilmont 10:3bc89ef62ce7 811 #define LPC_GPIO3_BASE (0x3FFFC060)
emilmont 10:3bc89ef62ce7 812 #define LPC_GPIO4_BASE (0x3FFFC080)
emilmont 10:3bc89ef62ce7 813
emilmont 10:3bc89ef62ce7 814
emilmont 10:3bc89ef62ce7 815 /******************************************************************************/
emilmont 10:3bc89ef62ce7 816 /* Peripheral declaration */
emilmont 10:3bc89ef62ce7 817 /******************************************************************************/
emilmont 10:3bc89ef62ce7 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
emilmont 10:3bc89ef62ce7 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
emilmont 10:3bc89ef62ce7 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
emilmont 10:3bc89ef62ce7 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
emilmont 10:3bc89ef62ce7 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
emilmont 10:3bc89ef62ce7 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
emilmont 10:3bc89ef62ce7 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
emilmont 10:3bc89ef62ce7 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
emilmont 10:3bc89ef62ce7 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
emilmont 10:3bc89ef62ce7 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
emilmont 10:3bc89ef62ce7 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
emilmont 10:3bc89ef62ce7 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
emilmont 10:3bc89ef62ce7 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
emilmont 10:3bc89ef62ce7 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
emilmont 10:3bc89ef62ce7 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
emilmont 10:3bc89ef62ce7 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
emilmont 10:3bc89ef62ce7 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
emilmont 10:3bc89ef62ce7 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
emilmont 10:3bc89ef62ce7 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
emilmont 10:3bc89ef62ce7 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
emilmont 10:3bc89ef62ce7 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
emilmont 10:3bc89ef62ce7 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
emilmont 10:3bc89ef62ce7 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
emilmont 10:3bc89ef62ce7 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
emilmont 10:3bc89ef62ce7 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
emilmont 10:3bc89ef62ce7 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
emilmont 10:3bc89ef62ce7 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
emilmont 10:3bc89ef62ce7 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
emilmont 10:3bc89ef62ce7 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
emilmont 10:3bc89ef62ce7 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
emilmont 10:3bc89ef62ce7 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
emilmont 10:3bc89ef62ce7 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
emilmont 10:3bc89ef62ce7 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
emilmont 10:3bc89ef62ce7 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
emilmont 10:3bc89ef62ce7 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
emilmont 10:3bc89ef62ce7 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
emilmont 10:3bc89ef62ce7 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
emilmont 10:3bc89ef62ce7 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
emilmont 10:3bc89ef62ce7 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
emilmont 10:3bc89ef62ce7 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
emilmont 10:3bc89ef62ce7 858
emilmont 10:3bc89ef62ce7 859 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 860 }
emilmont 10:3bc89ef62ce7 861 #endif
emilmont 10:3bc89ef62ce7 862
emilmont 10:3bc89ef62ce7 863 #endif // __LPC23xx_H
emilmont 10:3bc89ef62ce7 864