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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_M0P/CMSDK_CM0plus.h@580:3c14cb9b87c5, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:15:09 2015 +0100
Revision:
580:3c14cb9b87c5
Synchronized with git revision 213caf296f26963a7bea129b8ec4f33bbd1e6588



Full URL: https://github.com/mbedmicro/mbed/commit/213caf296f26963a7bea129b8ec4f33bbd1e6588/



commit of mps2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 580:3c14cb9b87c5 1 /* MPS2 CMSIS Library
mbed_official 580:3c14cb9b87c5 2 *
mbed_official 580:3c14cb9b87c5 3 * Copyright (c) 2006-2015 ARM Limited
mbed_official 580:3c14cb9b87c5 4 * All rights reserved.
mbed_official 580:3c14cb9b87c5 5 *
mbed_official 580:3c14cb9b87c5 6 * Redistribution and use in source and binary forms, with or without
mbed_official 580:3c14cb9b87c5 7 * modification, are permitted provided that the following conditions are met:
mbed_official 580:3c14cb9b87c5 8 *
mbed_official 580:3c14cb9b87c5 9 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 580:3c14cb9b87c5 10 * this list of conditions and the following disclaimer.
mbed_official 580:3c14cb9b87c5 11 *
mbed_official 580:3c14cb9b87c5 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 580:3c14cb9b87c5 13 * this list of conditions and the following disclaimer in the documentation
mbed_official 580:3c14cb9b87c5 14 * and/or other materials provided with the distribution.
mbed_official 580:3c14cb9b87c5 15 *
mbed_official 580:3c14cb9b87c5 16 * 3. Neither the name of the copyright holder nor the names of its contributors
mbed_official 580:3c14cb9b87c5 17 * may be used to endorse or promote products derived from this software without
mbed_official 580:3c14cb9b87c5 18 * specific prior written permission.
mbed_official 580:3c14cb9b87c5 19 *
mbed_official 580:3c14cb9b87c5 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 580:3c14cb9b87c5 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 580:3c14cb9b87c5 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 580:3c14cb9b87c5 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
mbed_official 580:3c14cb9b87c5 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 580:3c14cb9b87c5 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 580:3c14cb9b87c5 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 580:3c14cb9b87c5 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 580:3c14cb9b87c5 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 580:3c14cb9b87c5 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 580:3c14cb9b87c5 30 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 580:3c14cb9b87c5 31 *******************************************************************************
mbed_official 580:3c14cb9b87c5 32 * @file CMSDK_CM0plus.h
mbed_official 580:3c14cb9b87c5 33 * @brief CMSIS Core Peripheral Access Layer Header File for
mbed_official 580:3c14cb9b87c5 34 * CMSDK_CM0plus Device
mbed_official 580:3c14cb9b87c5 35 * @version V3.02
mbed_official 580:3c14cb9b87c5 36 * @date 15. November 2013
mbed_official 580:3c14cb9b87c5 37 *
mbed_official 580:3c14cb9b87c5 38 * @note configured for CM7 without FPU
mbed_official 580:3c14cb9b87c5 39 *
mbed_official 580:3c14cb9b87c5 40 *******************************************************************************/
mbed_official 580:3c14cb9b87c5 41
mbed_official 580:3c14cb9b87c5 42
mbed_official 580:3c14cb9b87c5 43 #ifndef CMSDK_CM0plus_H
mbed_official 580:3c14cb9b87c5 44 #define CMSDK_CM0plus_H
mbed_official 580:3c14cb9b87c5 45
mbed_official 580:3c14cb9b87c5 46 #ifdef __cplusplus
mbed_official 580:3c14cb9b87c5 47 extern "C" {
mbed_official 580:3c14cb9b87c5 48 #endif
mbed_official 580:3c14cb9b87c5 49
mbed_official 580:3c14cb9b87c5 50
mbed_official 580:3c14cb9b87c5 51 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 580:3c14cb9b87c5 52
mbed_official 580:3c14cb9b87c5 53 typedef enum IRQn
mbed_official 580:3c14cb9b87c5 54 {
mbed_official 580:3c14cb9b87c5 55 /* ------------------- Cortex-M0+ Processor Exceptions Numbers ------------------ */
mbed_official 580:3c14cb9b87c5 56 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
mbed_official 580:3c14cb9b87c5 57 HardFault_IRQn = -13, /* 3 HardFault Interrupt */
mbed_official 580:3c14cb9b87c5 58
mbed_official 580:3c14cb9b87c5 59
mbed_official 580:3c14cb9b87c5 60
mbed_official 580:3c14cb9b87c5 61 SVCall_IRQn = -5, /* 11 SV Call Interrupt */
mbed_official 580:3c14cb9b87c5 62
mbed_official 580:3c14cb9b87c5 63 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
mbed_official 580:3c14cb9b87c5 64 SysTick_IRQn = -1, /* 15 System Tick Interrupt */
mbed_official 580:3c14cb9b87c5 65
mbed_official 580:3c14cb9b87c5 66 /* ---------------------- CMSDK_CM0plus Specific Interrupt Numbers -------------- */
mbed_official 580:3c14cb9b87c5 67 UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
mbed_official 580:3c14cb9b87c5 68 UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
mbed_official 580:3c14cb9b87c5 69 UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
mbed_official 580:3c14cb9b87c5 70 UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
mbed_official 580:3c14cb9b87c5 71 UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
mbed_official 580:3c14cb9b87c5 72 UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
mbed_official 580:3c14cb9b87c5 73 PORT0_ALL_IRQn = 6, /* Port 1 combined Interrupt */
mbed_official 580:3c14cb9b87c5 74 PORT1_ALL_IRQn = 7, /* Port 1 combined Interrupt */
mbed_official 580:3c14cb9b87c5 75 TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
mbed_official 580:3c14cb9b87c5 76 TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
mbed_official 580:3c14cb9b87c5 77 DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
mbed_official 580:3c14cb9b87c5 78 SPI_IRQn = 11, /* SPI Interrupt */
mbed_official 580:3c14cb9b87c5 79 UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
mbed_official 580:3c14cb9b87c5 80 ETHERNET_IRQn = 13, /* Ethernet Interrupt */
mbed_official 580:3c14cb9b87c5 81 I2S_IRQn = 14, /* I2S Interrupt */
mbed_official 580:3c14cb9b87c5 82 TSC_IRQn = 15, /* Touch Screen Interrupt */
mbed_official 580:3c14cb9b87c5 83 // DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
mbed_official 580:3c14cb9b87c5 84 PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
mbed_official 580:3c14cb9b87c5 85 PORT0_1_IRQn = 17, /* There are 16 pins in total */
mbed_official 580:3c14cb9b87c5 86 PORT0_2_IRQn = 18,
mbed_official 580:3c14cb9b87c5 87 PORT0_3_IRQn = 19,
mbed_official 580:3c14cb9b87c5 88 PORT0_4_IRQn = 20,
mbed_official 580:3c14cb9b87c5 89 PORT0_5_IRQn = 21,
mbed_official 580:3c14cb9b87c5 90 PORT0_6_IRQn = 22,
mbed_official 580:3c14cb9b87c5 91 PORT0_7_IRQn = 23,
mbed_official 580:3c14cb9b87c5 92 PORT0_8_IRQn = 24,
mbed_official 580:3c14cb9b87c5 93 PORT0_9_IRQn = 25,
mbed_official 580:3c14cb9b87c5 94 PORT0_10_IRQn = 26,
mbed_official 580:3c14cb9b87c5 95 PORT0_11_IRQn = 27,
mbed_official 580:3c14cb9b87c5 96 PORT0_12_IRQn = 28,
mbed_official 580:3c14cb9b87c5 97 PORT0_13_IRQn = 29,
mbed_official 580:3c14cb9b87c5 98 PORT0_14_IRQn = 30,
mbed_official 580:3c14cb9b87c5 99 PORT0_15_IRQn = 31,
mbed_official 580:3c14cb9b87c5 100 } IRQn_Type;
mbed_official 580:3c14cb9b87c5 101
mbed_official 580:3c14cb9b87c5 102
mbed_official 580:3c14cb9b87c5 103 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 104 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 580:3c14cb9b87c5 105 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 106
mbed_official 580:3c14cb9b87c5 107 /* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
mbed_official 580:3c14cb9b87c5 108 #define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */
mbed_official 580:3c14cb9b87c5 109 #define __MPU_PRESENT 1 /* MPU present or not */
mbed_official 580:3c14cb9b87c5 110 #define __VTOR_PRESENT 1 /* VTOR present or not */
mbed_official 580:3c14cb9b87c5 111 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
mbed_official 580:3c14cb9b87c5 112 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official 580:3c14cb9b87c5 113
mbed_official 580:3c14cb9b87c5 114 #include <core_cm0plus.h> /* Processor and core peripherals */
mbed_official 580:3c14cb9b87c5 115 #include "system_CMSDK_CM0plus.h" /* System Header */
mbed_official 580:3c14cb9b87c5 116
mbed_official 580:3c14cb9b87c5 117
mbed_official 580:3c14cb9b87c5 118 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 119 /* ================ Device Specific Peripheral Section ================ */
mbed_official 580:3c14cb9b87c5 120 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 121
mbed_official 580:3c14cb9b87c5 122 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 580:3c14cb9b87c5 123 #if defined ( __CC_ARM )
mbed_official 580:3c14cb9b87c5 124 #pragma push
mbed_official 580:3c14cb9b87c5 125 #pragma anon_unions
mbed_official 580:3c14cb9b87c5 126 #elif defined(__ICCARM__)
mbed_official 580:3c14cb9b87c5 127 #pragma language=extended
mbed_official 580:3c14cb9b87c5 128 #elif defined(__GNUC__)
mbed_official 580:3c14cb9b87c5 129 /* anonymous unions are enabled by default */
mbed_official 580:3c14cb9b87c5 130 #elif defined(__TMS470__)
mbed_official 580:3c14cb9b87c5 131 /* anonymous unions are enabled by default */
mbed_official 580:3c14cb9b87c5 132 #elif defined(__TASKING__)
mbed_official 580:3c14cb9b87c5 133 #pragma warning 586
mbed_official 580:3c14cb9b87c5 134 #else
mbed_official 580:3c14cb9b87c5 135 #warning Not supported compiler type
mbed_official 580:3c14cb9b87c5 136 #endif
mbed_official 580:3c14cb9b87c5 137
mbed_official 580:3c14cb9b87c5 138 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
mbed_official 580:3c14cb9b87c5 139 typedef struct
mbed_official 580:3c14cb9b87c5 140 {
mbed_official 580:3c14cb9b87c5 141 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
mbed_official 580:3c14cb9b87c5 142 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
mbed_official 580:3c14cb9b87c5 143 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
mbed_official 580:3c14cb9b87c5 144 union {
mbed_official 580:3c14cb9b87c5 145 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 146 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 580:3c14cb9b87c5 147 };
mbed_official 580:3c14cb9b87c5 148 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
mbed_official 580:3c14cb9b87c5 149
mbed_official 580:3c14cb9b87c5 150 } CMSDK_UART_TypeDef;
mbed_official 580:3c14cb9b87c5 151
mbed_official 580:3c14cb9b87c5 152 /* CMSDK_UART DATA Register Definitions */
mbed_official 580:3c14cb9b87c5 153
mbed_official 580:3c14cb9b87c5 154 #define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
mbed_official 580:3c14cb9b87c5 155 #define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
mbed_official 580:3c14cb9b87c5 156
mbed_official 580:3c14cb9b87c5 157 #define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
mbed_official 580:3c14cb9b87c5 158 #define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
mbed_official 580:3c14cb9b87c5 159
mbed_official 580:3c14cb9b87c5 160 #define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
mbed_official 580:3c14cb9b87c5 161 #define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
mbed_official 580:3c14cb9b87c5 162
mbed_official 580:3c14cb9b87c5 163 #define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
mbed_official 580:3c14cb9b87c5 164 #define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
mbed_official 580:3c14cb9b87c5 165
mbed_official 580:3c14cb9b87c5 166 #define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
mbed_official 580:3c14cb9b87c5 167 #define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
mbed_official 580:3c14cb9b87c5 168
mbed_official 580:3c14cb9b87c5 169 #define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
mbed_official 580:3c14cb9b87c5 170 #define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
mbed_official 580:3c14cb9b87c5 171
mbed_official 580:3c14cb9b87c5 172 #define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
mbed_official 580:3c14cb9b87c5 173 #define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
mbed_official 580:3c14cb9b87c5 174
mbed_official 580:3c14cb9b87c5 175 #define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
mbed_official 580:3c14cb9b87c5 176 #define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
mbed_official 580:3c14cb9b87c5 177
mbed_official 580:3c14cb9b87c5 178 #define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
mbed_official 580:3c14cb9b87c5 179 #define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
mbed_official 580:3c14cb9b87c5 180
mbed_official 580:3c14cb9b87c5 181 #define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
mbed_official 580:3c14cb9b87c5 182 #define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
mbed_official 580:3c14cb9b87c5 183
mbed_official 580:3c14cb9b87c5 184 #define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
mbed_official 580:3c14cb9b87c5 185 #define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
mbed_official 580:3c14cb9b87c5 186
mbed_official 580:3c14cb9b87c5 187 #define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
mbed_official 580:3c14cb9b87c5 188 #define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
mbed_official 580:3c14cb9b87c5 189
mbed_official 580:3c14cb9b87c5 190 #define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
mbed_official 580:3c14cb9b87c5 191 #define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
mbed_official 580:3c14cb9b87c5 192
mbed_official 580:3c14cb9b87c5 193 #define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
mbed_official 580:3c14cb9b87c5 194 #define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
mbed_official 580:3c14cb9b87c5 195
mbed_official 580:3c14cb9b87c5 196 #define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
mbed_official 580:3c14cb9b87c5 197 #define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
mbed_official 580:3c14cb9b87c5 198
mbed_official 580:3c14cb9b87c5 199 #define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
mbed_official 580:3c14cb9b87c5 200 #define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
mbed_official 580:3c14cb9b87c5 201
mbed_official 580:3c14cb9b87c5 202 #define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
mbed_official 580:3c14cb9b87c5 203 #define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
mbed_official 580:3c14cb9b87c5 204
mbed_official 580:3c14cb9b87c5 205
mbed_official 580:3c14cb9b87c5 206 /*----------------------------- Timer (TIMER) -------------------------------*/
mbed_official 580:3c14cb9b87c5 207 typedef struct
mbed_official 580:3c14cb9b87c5 208 {
mbed_official 580:3c14cb9b87c5 209 __IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
mbed_official 580:3c14cb9b87c5 210 __IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
mbed_official 580:3c14cb9b87c5 211 __IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
mbed_official 580:3c14cb9b87c5 212 union {
mbed_official 580:3c14cb9b87c5 213 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 214 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
mbed_official 580:3c14cb9b87c5 215 };
mbed_official 580:3c14cb9b87c5 216
mbed_official 580:3c14cb9b87c5 217 } CMSDK_TIMER_TypeDef;
mbed_official 580:3c14cb9b87c5 218
mbed_official 580:3c14cb9b87c5 219 /* CMSDK_TIMER CTRL Register Definitions */
mbed_official 580:3c14cb9b87c5 220
mbed_official 580:3c14cb9b87c5 221 #define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
mbed_official 580:3c14cb9b87c5 222 #define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
mbed_official 580:3c14cb9b87c5 223
mbed_official 580:3c14cb9b87c5 224 #define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
mbed_official 580:3c14cb9b87c5 225 #define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
mbed_official 580:3c14cb9b87c5 226
mbed_official 580:3c14cb9b87c5 227 #define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
mbed_official 580:3c14cb9b87c5 228 #define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
mbed_official 580:3c14cb9b87c5 229
mbed_official 580:3c14cb9b87c5 230 #define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
mbed_official 580:3c14cb9b87c5 231 #define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
mbed_official 580:3c14cb9b87c5 232
mbed_official 580:3c14cb9b87c5 233 #define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
mbed_official 580:3c14cb9b87c5 234 #define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
mbed_official 580:3c14cb9b87c5 235
mbed_official 580:3c14cb9b87c5 236 #define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
mbed_official 580:3c14cb9b87c5 237 #define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
mbed_official 580:3c14cb9b87c5 238
mbed_official 580:3c14cb9b87c5 239 #define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
mbed_official 580:3c14cb9b87c5 240 #define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
mbed_official 580:3c14cb9b87c5 241
mbed_official 580:3c14cb9b87c5 242 #define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
mbed_official 580:3c14cb9b87c5 243 #define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
mbed_official 580:3c14cb9b87c5 244
mbed_official 580:3c14cb9b87c5 245
mbed_official 580:3c14cb9b87c5 246 /*------------- Timer (TIM) --------------------------------------------------*/
mbed_official 580:3c14cb9b87c5 247 typedef struct
mbed_official 580:3c14cb9b87c5 248 {
mbed_official 580:3c14cb9b87c5 249 __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
mbed_official 580:3c14cb9b87c5 250 __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
mbed_official 580:3c14cb9b87c5 251 __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
mbed_official 580:3c14cb9b87c5 252 __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
mbed_official 580:3c14cb9b87c5 253 __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 254 __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 255 __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 256 uint32_t RESERVED0;
mbed_official 580:3c14cb9b87c5 257 __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
mbed_official 580:3c14cb9b87c5 258 __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
mbed_official 580:3c14cb9b87c5 259 __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
mbed_official 580:3c14cb9b87c5 260 __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
mbed_official 580:3c14cb9b87c5 261 __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 262 __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 263 __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 264 uint32_t RESERVED1[945];
mbed_official 580:3c14cb9b87c5 265 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
mbed_official 580:3c14cb9b87c5 266 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
mbed_official 580:3c14cb9b87c5 267 } CMSDK_DUALTIMER_BOTH_TypeDef;
mbed_official 580:3c14cb9b87c5 268
mbed_official 580:3c14cb9b87c5 269 #define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 270 #define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 271
mbed_official 580:3c14cb9b87c5 272 #define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 273 #define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 274
mbed_official 580:3c14cb9b87c5 275 #define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 276 #define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 277
mbed_official 580:3c14cb9b87c5 278 #define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 279 #define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 280
mbed_official 580:3c14cb9b87c5 281 #define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 282 #define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 283
mbed_official 580:3c14cb9b87c5 284 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 285 #define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 286
mbed_official 580:3c14cb9b87c5 287 #define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 288 #define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 289
mbed_official 580:3c14cb9b87c5 290 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 291 #define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 292
mbed_official 580:3c14cb9b87c5 293 #define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 294 #define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 295
mbed_official 580:3c14cb9b87c5 296 #define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 297 #define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 298
mbed_official 580:3c14cb9b87c5 299 #define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 300 #define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 301
mbed_official 580:3c14cb9b87c5 302 #define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 303 #define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 304
mbed_official 580:3c14cb9b87c5 305 #define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 306 #define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 307
mbed_official 580:3c14cb9b87c5 308 #define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 309 #define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 310
mbed_official 580:3c14cb9b87c5 311 #define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 312 #define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 313
mbed_official 580:3c14cb9b87c5 314 #define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 315 #define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 316
mbed_official 580:3c14cb9b87c5 317 #define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 318 #define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 319
mbed_official 580:3c14cb9b87c5 320 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 321 #define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 322
mbed_official 580:3c14cb9b87c5 323 #define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 324 #define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 325
mbed_official 580:3c14cb9b87c5 326 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 327 #define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 328
mbed_official 580:3c14cb9b87c5 329 #define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 330 #define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 331
mbed_official 580:3c14cb9b87c5 332 #define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 333 #define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 334
mbed_official 580:3c14cb9b87c5 335 #define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 336 #define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 337
mbed_official 580:3c14cb9b87c5 338 #define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 339 #define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 340
mbed_official 580:3c14cb9b87c5 341
mbed_official 580:3c14cb9b87c5 342 typedef struct
mbed_official 580:3c14cb9b87c5 343 {
mbed_official 580:3c14cb9b87c5 344 __IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
mbed_official 580:3c14cb9b87c5 345 __I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
mbed_official 580:3c14cb9b87c5 346 __IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
mbed_official 580:3c14cb9b87c5 347 __O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
mbed_official 580:3c14cb9b87c5 348 __I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
mbed_official 580:3c14cb9b87c5 349 __I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
mbed_official 580:3c14cb9b87c5 350 __IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
mbed_official 580:3c14cb9b87c5 351 } CMSDK_DUALTIMER_SINGLE_TypeDef;
mbed_official 580:3c14cb9b87c5 352
mbed_official 580:3c14cb9b87c5 353 #define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 354 #define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 355
mbed_official 580:3c14cb9b87c5 356 #define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 357 #define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 358
mbed_official 580:3c14cb9b87c5 359 #define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
mbed_official 580:3c14cb9b87c5 360 #define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
mbed_official 580:3c14cb9b87c5 361
mbed_official 580:3c14cb9b87c5 362 #define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
mbed_official 580:3c14cb9b87c5 363 #define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
mbed_official 580:3c14cb9b87c5 364
mbed_official 580:3c14cb9b87c5 365 #define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
mbed_official 580:3c14cb9b87c5 366 #define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
mbed_official 580:3c14cb9b87c5 367
mbed_official 580:3c14cb9b87c5 368 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
mbed_official 580:3c14cb9b87c5 369 #define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
mbed_official 580:3c14cb9b87c5 370
mbed_official 580:3c14cb9b87c5 371 #define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
mbed_official 580:3c14cb9b87c5 372 #define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
mbed_official 580:3c14cb9b87c5 373
mbed_official 580:3c14cb9b87c5 374 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
mbed_official 580:3c14cb9b87c5 375 #define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
mbed_official 580:3c14cb9b87c5 376
mbed_official 580:3c14cb9b87c5 377 #define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
mbed_official 580:3c14cb9b87c5 378 #define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
mbed_official 580:3c14cb9b87c5 379
mbed_official 580:3c14cb9b87c5 380 #define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 381 #define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 382
mbed_official 580:3c14cb9b87c5 383 #define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 384 #define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 385
mbed_official 580:3c14cb9b87c5 386 #define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
mbed_official 580:3c14cb9b87c5 387 #define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
mbed_official 580:3c14cb9b87c5 388
mbed_official 580:3c14cb9b87c5 389
mbed_official 580:3c14cb9b87c5 390 /*-------------------- General Purpose Input Output (GPIO) -------------------*/
mbed_official 580:3c14cb9b87c5 391 typedef struct
mbed_official 580:3c14cb9b87c5 392 {
mbed_official 580:3c14cb9b87c5 393 __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
mbed_official 580:3c14cb9b87c5 394 __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
mbed_official 580:3c14cb9b87c5 395 uint32_t RESERVED0[2];
mbed_official 580:3c14cb9b87c5 396 __IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
mbed_official 580:3c14cb9b87c5 397 __IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
mbed_official 580:3c14cb9b87c5 398 __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
mbed_official 580:3c14cb9b87c5 399 __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
mbed_official 580:3c14cb9b87c5 400 __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
mbed_official 580:3c14cb9b87c5 401 __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
mbed_official 580:3c14cb9b87c5 402 __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
mbed_official 580:3c14cb9b87c5 403 __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
mbed_official 580:3c14cb9b87c5 404 __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
mbed_official 580:3c14cb9b87c5 405 __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
mbed_official 580:3c14cb9b87c5 406 union {
mbed_official 580:3c14cb9b87c5 407 __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 408 __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
mbed_official 580:3c14cb9b87c5 409 };
mbed_official 580:3c14cb9b87c5 410 uint32_t RESERVED1[241];
mbed_official 580:3c14cb9b87c5 411 __IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
mbed_official 580:3c14cb9b87c5 412 __IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
mbed_official 580:3c14cb9b87c5 413 } CMSDK_GPIO_TypeDef;
mbed_official 580:3c14cb9b87c5 414
mbed_official 580:3c14cb9b87c5 415 #define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
mbed_official 580:3c14cb9b87c5 416 #define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
mbed_official 580:3c14cb9b87c5 417
mbed_official 580:3c14cb9b87c5 418 #define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
mbed_official 580:3c14cb9b87c5 419 #define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
mbed_official 580:3c14cb9b87c5 420
mbed_official 580:3c14cb9b87c5 421 #define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 580:3c14cb9b87c5 422 #define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 580:3c14cb9b87c5 423
mbed_official 580:3c14cb9b87c5 424 #define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
mbed_official 580:3c14cb9b87c5 425 #define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
mbed_official 580:3c14cb9b87c5 426
mbed_official 580:3c14cb9b87c5 427 #define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 580:3c14cb9b87c5 428 #define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 580:3c14cb9b87c5 429
mbed_official 580:3c14cb9b87c5 430 #define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
mbed_official 580:3c14cb9b87c5 431 #define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
mbed_official 580:3c14cb9b87c5 432
mbed_official 580:3c14cb9b87c5 433 #define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 580:3c14cb9b87c5 434 #define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 580:3c14cb9b87c5 435
mbed_official 580:3c14cb9b87c5 436 #define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
mbed_official 580:3c14cb9b87c5 437 #define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
mbed_official 580:3c14cb9b87c5 438
mbed_official 580:3c14cb9b87c5 439 #define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 580:3c14cb9b87c5 440 #define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 580:3c14cb9b87c5 441
mbed_official 580:3c14cb9b87c5 442 #define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
mbed_official 580:3c14cb9b87c5 443 #define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
mbed_official 580:3c14cb9b87c5 444
mbed_official 580:3c14cb9b87c5 445 #define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 580:3c14cb9b87c5 446 #define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 580:3c14cb9b87c5 447
mbed_official 580:3c14cb9b87c5 448 #define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
mbed_official 580:3c14cb9b87c5 449 #define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
mbed_official 580:3c14cb9b87c5 450
mbed_official 580:3c14cb9b87c5 451 #define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
mbed_official 580:3c14cb9b87c5 452 #define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
mbed_official 580:3c14cb9b87c5 453
mbed_official 580:3c14cb9b87c5 454 #define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
mbed_official 580:3c14cb9b87c5 455 #define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
mbed_official 580:3c14cb9b87c5 456
mbed_official 580:3c14cb9b87c5 457 #define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
mbed_official 580:3c14cb9b87c5 458 #define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
mbed_official 580:3c14cb9b87c5 459
mbed_official 580:3c14cb9b87c5 460 #define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
mbed_official 580:3c14cb9b87c5 461 #define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
mbed_official 580:3c14cb9b87c5 462
mbed_official 580:3c14cb9b87c5 463
mbed_official 580:3c14cb9b87c5 464 /*------------- System Control (SYSCON) --------------------------------------*/
mbed_official 580:3c14cb9b87c5 465 typedef struct
mbed_official 580:3c14cb9b87c5 466 {
mbed_official 580:3c14cb9b87c5 467 __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
mbed_official 580:3c14cb9b87c5 468 __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
mbed_official 580:3c14cb9b87c5 469 __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
mbed_official 580:3c14cb9b87c5 470 __IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
mbed_official 580:3c14cb9b87c5 471 __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
mbed_official 580:3c14cb9b87c5 472 } CMSDK_SYSCON_TypeDef;
mbed_official 580:3c14cb9b87c5 473
mbed_official 580:3c14cb9b87c5 474 #define CMSDK_SYSCON_REMAP_Pos 0
mbed_official 580:3c14cb9b87c5 475 #define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
mbed_official 580:3c14cb9b87c5 476
mbed_official 580:3c14cb9b87c5 477 #define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
mbed_official 580:3c14cb9b87c5 478 #define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
mbed_official 580:3c14cb9b87c5 479
mbed_official 580:3c14cb9b87c5 480 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
mbed_official 580:3c14cb9b87c5 481 #define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
mbed_official 580:3c14cb9b87c5 482
mbed_official 580:3c14cb9b87c5 483 #define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
mbed_official 580:3c14cb9b87c5 484 #define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
mbed_official 580:3c14cb9b87c5 485
mbed_official 580:3c14cb9b87c5 486 #define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
mbed_official 580:3c14cb9b87c5 487 #define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
mbed_official 580:3c14cb9b87c5 488
mbed_official 580:3c14cb9b87c5 489 #define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
mbed_official 580:3c14cb9b87c5 490 #define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
mbed_official 580:3c14cb9b87c5 491
mbed_official 580:3c14cb9b87c5 492 #define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
mbed_official 580:3c14cb9b87c5 493 #define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
mbed_official 580:3c14cb9b87c5 494
mbed_official 580:3c14cb9b87c5 495 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
mbed_official 580:3c14cb9b87c5 496 #define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
mbed_official 580:3c14cb9b87c5 497
mbed_official 580:3c14cb9b87c5 498 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
mbed_official 580:3c14cb9b87c5 499 #define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
mbed_official 580:3c14cb9b87c5 500
mbed_official 580:3c14cb9b87c5 501 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
mbed_official 580:3c14cb9b87c5 502 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
mbed_official 580:3c14cb9b87c5 503
mbed_official 580:3c14cb9b87c5 504
mbed_official 580:3c14cb9b87c5 505 /*------------- PL230 uDMA (PL230) --------------------------------------*/
mbed_official 580:3c14cb9b87c5 506 typedef struct
mbed_official 580:3c14cb9b87c5 507 {
mbed_official 580:3c14cb9b87c5 508 __I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
mbed_official 580:3c14cb9b87c5 509 __O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
mbed_official 580:3c14cb9b87c5 510 __IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
mbed_official 580:3c14cb9b87c5 511 __I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
mbed_official 580:3c14cb9b87c5 512 __I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
mbed_official 580:3c14cb9b87c5 513 __O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
mbed_official 580:3c14cb9b87c5 514 __IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
mbed_official 580:3c14cb9b87c5 515 __O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
mbed_official 580:3c14cb9b87c5 516 __IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
mbed_official 580:3c14cb9b87c5 517 __O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
mbed_official 580:3c14cb9b87c5 518 __IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
mbed_official 580:3c14cb9b87c5 519 __O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
mbed_official 580:3c14cb9b87c5 520 __IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
mbed_official 580:3c14cb9b87c5 521 __O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
mbed_official 580:3c14cb9b87c5 522 __IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
mbed_official 580:3c14cb9b87c5 523 __O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
mbed_official 580:3c14cb9b87c5 524 uint32_t RESERVED0[3];
mbed_official 580:3c14cb9b87c5 525 __IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
mbed_official 580:3c14cb9b87c5 526
mbed_official 580:3c14cb9b87c5 527 } CMSDK_PL230_TypeDef;
mbed_official 580:3c14cb9b87c5 528
mbed_official 580:3c14cb9b87c5 529 #define PL230_DMA_CHNL_BITS 0
mbed_official 580:3c14cb9b87c5 530
mbed_official 580:3c14cb9b87c5 531 #define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
mbed_official 580:3c14cb9b87c5 532 #define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 533
mbed_official 580:3c14cb9b87c5 534 #define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
mbed_official 580:3c14cb9b87c5 535 #define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
mbed_official 580:3c14cb9b87c5 536
mbed_official 580:3c14cb9b87c5 537 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
mbed_official 580:3c14cb9b87c5 538 #define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
mbed_official 580:3c14cb9b87c5 539
mbed_official 580:3c14cb9b87c5 540 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
mbed_official 580:3c14cb9b87c5 541 #define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
mbed_official 580:3c14cb9b87c5 542
mbed_official 580:3c14cb9b87c5 543 #define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
mbed_official 580:3c14cb9b87c5 544 #define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 545
mbed_official 580:3c14cb9b87c5 546 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
mbed_official 580:3c14cb9b87c5 547 #define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
mbed_official 580:3c14cb9b87c5 548
mbed_official 580:3c14cb9b87c5 549 #define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
mbed_official 580:3c14cb9b87c5 550 #define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
mbed_official 580:3c14cb9b87c5 551
mbed_official 580:3c14cb9b87c5 552 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
mbed_official 580:3c14cb9b87c5 553 #define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
mbed_official 580:3c14cb9b87c5 554
mbed_official 580:3c14cb9b87c5 555 #define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
mbed_official 580:3c14cb9b87c5 556 #define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
mbed_official 580:3c14cb9b87c5 557
mbed_official 580:3c14cb9b87c5 558 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
mbed_official 580:3c14cb9b87c5 559 #define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
mbed_official 580:3c14cb9b87c5 560
mbed_official 580:3c14cb9b87c5 561 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
mbed_official 580:3c14cb9b87c5 562 #define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
mbed_official 580:3c14cb9b87c5 563
mbed_official 580:3c14cb9b87c5 564 #define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
mbed_official 580:3c14cb9b87c5 565 #define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
mbed_official 580:3c14cb9b87c5 566
mbed_official 580:3c14cb9b87c5 567 #define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
mbed_official 580:3c14cb9b87c5 568 #define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
mbed_official 580:3c14cb9b87c5 569
mbed_official 580:3c14cb9b87c5 570 #define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
mbed_official 580:3c14cb9b87c5 571 #define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
mbed_official 580:3c14cb9b87c5 572
mbed_official 580:3c14cb9b87c5 573 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
mbed_official 580:3c14cb9b87c5 574 #define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
mbed_official 580:3c14cb9b87c5 575
mbed_official 580:3c14cb9b87c5 576 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
mbed_official 580:3c14cb9b87c5 577 #define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
mbed_official 580:3c14cb9b87c5 578
mbed_official 580:3c14cb9b87c5 579 #define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
mbed_official 580:3c14cb9b87c5 580 #define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
mbed_official 580:3c14cb9b87c5 581
mbed_official 580:3c14cb9b87c5 582 #define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
mbed_official 580:3c14cb9b87c5 583 #define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
mbed_official 580:3c14cb9b87c5 584
mbed_official 580:3c14cb9b87c5 585 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
mbed_official 580:3c14cb9b87c5 586 #define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
mbed_official 580:3c14cb9b87c5 587
mbed_official 580:3c14cb9b87c5 588 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
mbed_official 580:3c14cb9b87c5 589 #define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
mbed_official 580:3c14cb9b87c5 590
mbed_official 580:3c14cb9b87c5 591 #define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
mbed_official 580:3c14cb9b87c5 592 #define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
mbed_official 580:3c14cb9b87c5 593
mbed_official 580:3c14cb9b87c5 594 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
mbed_official 580:3c14cb9b87c5 595 #define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
mbed_official 580:3c14cb9b87c5 596
mbed_official 580:3c14cb9b87c5 597 #define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
mbed_official 580:3c14cb9b87c5 598 #define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
mbed_official 580:3c14cb9b87c5 599
mbed_official 580:3c14cb9b87c5 600
mbed_official 580:3c14cb9b87c5 601 /*------------------- Watchdog ----------------------------------------------*/
mbed_official 580:3c14cb9b87c5 602 typedef struct
mbed_official 580:3c14cb9b87c5 603 {
mbed_official 580:3c14cb9b87c5 604
mbed_official 580:3c14cb9b87c5 605 __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
mbed_official 580:3c14cb9b87c5 606 __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
mbed_official 580:3c14cb9b87c5 607 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
mbed_official 580:3c14cb9b87c5 608 __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
mbed_official 580:3c14cb9b87c5 609 __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 610 __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
mbed_official 580:3c14cb9b87c5 611 uint32_t RESERVED0[762];
mbed_official 580:3c14cb9b87c5 612 __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
mbed_official 580:3c14cb9b87c5 613 uint32_t RESERVED1[191];
mbed_official 580:3c14cb9b87c5 614 __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
mbed_official 580:3c14cb9b87c5 615 __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
mbed_official 580:3c14cb9b87c5 616 }CMSDK_WATCHDOG_TypeDef;
mbed_official 580:3c14cb9b87c5 617
mbed_official 580:3c14cb9b87c5 618 #define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
mbed_official 580:3c14cb9b87c5 619 #define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
mbed_official 580:3c14cb9b87c5 620
mbed_official 580:3c14cb9b87c5 621 #define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
mbed_official 580:3c14cb9b87c5 622 #define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
mbed_official 580:3c14cb9b87c5 623
mbed_official 580:3c14cb9b87c5 624 #define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
mbed_official 580:3c14cb9b87c5 625 #define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
mbed_official 580:3c14cb9b87c5 626
mbed_official 580:3c14cb9b87c5 627 #define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
mbed_official 580:3c14cb9b87c5 628 #define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
mbed_official 580:3c14cb9b87c5 629
mbed_official 580:3c14cb9b87c5 630 #define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
mbed_official 580:3c14cb9b87c5 631 #define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
mbed_official 580:3c14cb9b87c5 632
mbed_official 580:3c14cb9b87c5 633 #define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
mbed_official 580:3c14cb9b87c5 634 #define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
mbed_official 580:3c14cb9b87c5 635
mbed_official 580:3c14cb9b87c5 636 #define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
mbed_official 580:3c14cb9b87c5 637 #define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
mbed_official 580:3c14cb9b87c5 638
mbed_official 580:3c14cb9b87c5 639 #define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
mbed_official 580:3c14cb9b87c5 640 #define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
mbed_official 580:3c14cb9b87c5 641
mbed_official 580:3c14cb9b87c5 642 #define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
mbed_official 580:3c14cb9b87c5 643 #define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
mbed_official 580:3c14cb9b87c5 644
mbed_official 580:3c14cb9b87c5 645 #define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
mbed_official 580:3c14cb9b87c5 646 #define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
mbed_official 580:3c14cb9b87c5 647
mbed_official 580:3c14cb9b87c5 648
mbed_official 580:3c14cb9b87c5 649
mbed_official 580:3c14cb9b87c5 650 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 580:3c14cb9b87c5 651 #if defined ( __CC_ARM )
mbed_official 580:3c14cb9b87c5 652 #pragma pop
mbed_official 580:3c14cb9b87c5 653 #elif defined(__ICCARM__)
mbed_official 580:3c14cb9b87c5 654 /* leave anonymous unions enabled */
mbed_official 580:3c14cb9b87c5 655 #elif defined(__GNUC__)
mbed_official 580:3c14cb9b87c5 656 /* anonymous unions are enabled by default */
mbed_official 580:3c14cb9b87c5 657 #elif defined(__TMS470__)
mbed_official 580:3c14cb9b87c5 658 /* anonymous unions are enabled by default */
mbed_official 580:3c14cb9b87c5 659 #elif defined(__TASKING__)
mbed_official 580:3c14cb9b87c5 660 #pragma warning restore
mbed_official 580:3c14cb9b87c5 661 #else
mbed_official 580:3c14cb9b87c5 662 #warning Not supported compiler type
mbed_official 580:3c14cb9b87c5 663 #endif
mbed_official 580:3c14cb9b87c5 664
mbed_official 580:3c14cb9b87c5 665
mbed_official 580:3c14cb9b87c5 666
mbed_official 580:3c14cb9b87c5 667
mbed_official 580:3c14cb9b87c5 668 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 669 /* ================ Peripheral memory map ================ */
mbed_official 580:3c14cb9b87c5 670 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 671
mbed_official 580:3c14cb9b87c5 672 /* Peripheral and SRAM base address */
mbed_official 580:3c14cb9b87c5 673 #define CMSDK_FLASH_BASE (0x00000000UL)
mbed_official 580:3c14cb9b87c5 674 #define CMSDK_SRAM_BASE (0x20000000UL)
mbed_official 580:3c14cb9b87c5 675 #define CMSDK_PERIPH_BASE (0x40000000UL)
mbed_official 580:3c14cb9b87c5 676
mbed_official 580:3c14cb9b87c5 677 #define CMSDK_RAM_BASE (0x20000000UL)
mbed_official 580:3c14cb9b87c5 678 #define CMSDK_APB_BASE (0x40000000UL)
mbed_official 580:3c14cb9b87c5 679 #define CMSDK_AHB_BASE (0x40010000UL)
mbed_official 580:3c14cb9b87c5 680
mbed_official 580:3c14cb9b87c5 681 /* APB peripherals */
mbed_official 580:3c14cb9b87c5 682 #define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
mbed_official 580:3c14cb9b87c5 683 #define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
mbed_official 580:3c14cb9b87c5 684 #define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
mbed_official 580:3c14cb9b87c5 685 #define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
mbed_official 580:3c14cb9b87c5 686 #define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
mbed_official 580:3c14cb9b87c5 687 #define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL)
mbed_official 580:3c14cb9b87c5 688 #define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL)
mbed_official 580:3c14cb9b87c5 689 #define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
mbed_official 580:3c14cb9b87c5 690 #define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
mbed_official 580:3c14cb9b87c5 691 #define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
mbed_official 580:3c14cb9b87c5 692
mbed_official 580:3c14cb9b87c5 693 /* AHB peripherals */
mbed_official 580:3c14cb9b87c5 694 #define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
mbed_official 580:3c14cb9b87c5 695 #define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
mbed_official 580:3c14cb9b87c5 696 #define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
mbed_official 580:3c14cb9b87c5 697 #define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
mbed_official 580:3c14cb9b87c5 698 #define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
mbed_official 580:3c14cb9b87c5 699
mbed_official 580:3c14cb9b87c5 700
mbed_official 580:3c14cb9b87c5 701 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 702 /* ================ Peripheral declaration ================ */
mbed_official 580:3c14cb9b87c5 703 /* ================================================================================ */
mbed_official 580:3c14cb9b87c5 704
mbed_official 580:3c14cb9b87c5 705 #define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
mbed_official 580:3c14cb9b87c5 706 #define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
mbed_official 580:3c14cb9b87c5 707 #define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
mbed_official 580:3c14cb9b87c5 708 #define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
mbed_official 580:3c14cb9b87c5 709 #define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
mbed_official 580:3c14cb9b87c5 710 #define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
mbed_official 580:3c14cb9b87c5 711 #define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
mbed_official 580:3c14cb9b87c5 712 #define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
mbed_official 580:3c14cb9b87c5 713 #define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
mbed_official 580:3c14cb9b87c5 714 #define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
mbed_official 580:3c14cb9b87c5 715 #define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
mbed_official 580:3c14cb9b87c5 716 #define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
mbed_official 580:3c14cb9b87c5 717 #define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
mbed_official 580:3c14cb9b87c5 718 #define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
mbed_official 580:3c14cb9b87c5 719 #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
mbed_official 580:3c14cb9b87c5 720
mbed_official 580:3c14cb9b87c5 721
mbed_official 580:3c14cb9b87c5 722 #ifdef __cplusplus
mbed_official 580:3c14cb9b87c5 723 }
mbed_official 580:3c14cb9b87c5 724 #endif
mbed_official 580:3c14cb9b87c5 725
mbed_official 580:3c14cb9b87c5 726 #endif /* CMSDK_CM0plus_H */