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Last commit 20 Feb 2019 by 
mbed official
vendor/NXP/LPC4088/cmsis/system_LPC407x_8x_177x_8x.c@10:3bc89ef62ce7, 2013-06-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Jun 14 17:49:17 2013 +0100
- Revision:
- 10:3bc89ef62ce7
Unify mbed library sources
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 10:3bc89ef62ce7 | 1 | /********************************************************************** |
| emilmont | 10:3bc89ef62ce7 | 2 | * $Id$ system_LPC407x_8x_177x_8x.c 2012-01-16 |
| emilmont | 10:3bc89ef62ce7 | 3 | *//** |
| emilmont | 10:3bc89ef62ce7 | 4 | * @file system_LPC407x_8x_177x_8x.c |
| emilmont | 10:3bc89ef62ce7 | 5 | * @brief CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File |
| emilmont | 10:3bc89ef62ce7 | 6 | * for the NXP LPC407x_8x_177x_8x Device Series |
| emilmont | 10:3bc89ef62ce7 | 7 | * |
| emilmont | 10:3bc89ef62ce7 | 8 | * ARM Limited (ARM) is supplying this software for use with |
| emilmont | 10:3bc89ef62ce7 | 9 | * Cortex-M processor based microcontrollers. This file can be |
| emilmont | 10:3bc89ef62ce7 | 10 | * freely distributed within development tools that are supporting |
| emilmont | 10:3bc89ef62ce7 | 11 | * such ARM based processors. |
| emilmont | 10:3bc89ef62ce7 | 12 | * |
| emilmont | 10:3bc89ef62ce7 | 13 | * @version 1.2 |
| emilmont | 10:3bc89ef62ce7 | 14 | * @date 20. June. 2012 |
| emilmont | 10:3bc89ef62ce7 | 15 | * @author NXP MCU SW Application Team |
| emilmont | 10:3bc89ef62ce7 | 16 | * |
| emilmont | 10:3bc89ef62ce7 | 17 | * Copyright(C) 2012, NXP Semiconductor |
| emilmont | 10:3bc89ef62ce7 | 18 | * All rights reserved. |
| emilmont | 10:3bc89ef62ce7 | 19 | * |
| emilmont | 10:3bc89ef62ce7 | 20 | *********************************************************************** |
| emilmont | 10:3bc89ef62ce7 | 21 | * Software that is described herein is for illustrative purposes only |
| emilmont | 10:3bc89ef62ce7 | 22 | * which provides customers with programming information regarding the |
| emilmont | 10:3bc89ef62ce7 | 23 | * products. This software is supplied "AS IS" without any warranties. |
| emilmont | 10:3bc89ef62ce7 | 24 | * NXP Semiconductors assumes no responsibility or liability for the |
| emilmont | 10:3bc89ef62ce7 | 25 | * use of the software, conveys no license or title under any patent, |
| emilmont | 10:3bc89ef62ce7 | 26 | * copyright, or mask work right to the product. NXP Semiconductors |
| emilmont | 10:3bc89ef62ce7 | 27 | * reserves the right to make changes in the software without |
| emilmont | 10:3bc89ef62ce7 | 28 | * notification. NXP Semiconductors also make no representation or |
| emilmont | 10:3bc89ef62ce7 | 29 | * warranty that such application will be suitable for the specified |
| emilmont | 10:3bc89ef62ce7 | 30 | * use without further testing or modification. |
| emilmont | 10:3bc89ef62ce7 | 31 | **********************************************************************/ |
| emilmont | 10:3bc89ef62ce7 | 32 | |
| emilmont | 10:3bc89ef62ce7 | 33 | #include <stdint.h> |
| emilmont | 10:3bc89ef62ce7 | 34 | #include "LPC407x_8x_177x_8x.h" |
| emilmont | 10:3bc89ef62ce7 | 35 | #include "system_LPC407x_8x_177x_8x.h" |
| emilmont | 10:3bc89ef62ce7 | 36 | |
| emilmont | 10:3bc89ef62ce7 | 37 | #define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y)) |
| emilmont | 10:3bc89ef62ce7 | 38 | |
| emilmont | 10:3bc89ef62ce7 | 39 | /* |
| emilmont | 10:3bc89ef62ce7 | 40 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| emilmont | 10:3bc89ef62ce7 | 41 | */ |
| emilmont | 10:3bc89ef62ce7 | 42 | /*--------------------- Clock Configuration ---------------------------------- |
| emilmont | 10:3bc89ef62ce7 | 43 | // |
| emilmont | 10:3bc89ef62ce7 | 44 | // <e> Clock Configuration |
| emilmont | 10:3bc89ef62ce7 | 45 | // <h> System Controls and Status Register (SCS - address 0x400F C1A0) |
| emilmont | 10:3bc89ef62ce7 | 46 | // <o1.0> EMC Shift Control Bit |
| emilmont | 10:3bc89ef62ce7 | 47 | // <i> Controls how addresses are output on the EMC address pins for static memories |
| emilmont | 10:3bc89ef62ce7 | 48 | // <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0) |
| emilmont | 10:3bc89ef62ce7 | 49 | // <1=> Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1) |
| emilmont | 10:3bc89ef62ce7 | 50 | // |
| emilmont | 10:3bc89ef62ce7 | 51 | // <o1.1> EMC Reset Disable Bit |
| emilmont | 10:3bc89ef62ce7 | 52 | // <i> If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition |
| emilmont | 10:3bc89ef62ce7 | 53 | // <i> If 1, EMC is still retained its state through a warm reset |
| emilmont | 10:3bc89ef62ce7 | 54 | // <0=> Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0) |
| emilmont | 10:3bc89ef62ce7 | 55 | // <1=> Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1) |
| emilmont | 10:3bc89ef62ce7 | 56 | // |
| emilmont | 10:3bc89ef62ce7 | 57 | // <o1.2> EMC Burst Control |
| emilmont | 10:3bc89ef62ce7 | 58 | // <i> Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects |
| emilmont | 10:3bc89ef62ce7 | 59 | // <0=> Burst enabled (Bit 2 is 0) |
| emilmont | 10:3bc89ef62ce7 | 60 | // <1=> Bust disbled (Bit 2 is 1) |
| emilmont | 10:3bc89ef62ce7 | 61 | // |
| emilmont | 10:3bc89ef62ce7 | 62 | // <o1.3> MCIPWR Active Level |
| emilmont | 10:3bc89ef62ce7 | 63 | // <i> Selects the active level for the SD card interface signal SD_PWR |
| emilmont | 10:3bc89ef62ce7 | 64 | // <0=> SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0) |
| emilmont | 10:3bc89ef62ce7 | 65 | // <1=> SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1) |
| emilmont | 10:3bc89ef62ce7 | 66 | // |
| emilmont | 10:3bc89ef62ce7 | 67 | // <o1.4> Main Oscillator Range Select |
| emilmont | 10:3bc89ef62ce7 | 68 | // <0=> In Range 1 MHz to 20 MHz (Bit 4 is 0) |
| emilmont | 10:3bc89ef62ce7 | 69 | // <1=> In Range 15 MHz to 25 MHz (Bit 4 is 1) |
| emilmont | 10:3bc89ef62ce7 | 70 | // |
| emilmont | 10:3bc89ef62ce7 | 71 | // <o1.5> Main Oscillator enable |
| emilmont | 10:3bc89ef62ce7 | 72 | // <i> 0 (zero) means disabled, 1 means enable |
| emilmont | 10:3bc89ef62ce7 | 73 | // |
| emilmont | 10:3bc89ef62ce7 | 74 | // <o1.6> Main Oscillator status (Read-Only) |
| emilmont | 10:3bc89ef62ce7 | 75 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 76 | // |
| emilmont | 10:3bc89ef62ce7 | 77 | // <h> Clock Source Select Register (CLKSRCSEL - address 0x400F C10C) |
| emilmont | 10:3bc89ef62ce7 | 78 | // <o2.0> CLKSRC: Select the clock source for sysclk to PLL0 clock |
| emilmont | 10:3bc89ef62ce7 | 79 | // <0=> Internal RC oscillator (Bit 0 is 0) |
| emilmont | 10:3bc89ef62ce7 | 80 | // <1=> Main oscillator (Bit 0 is 1) |
| emilmont | 10:3bc89ef62ce7 | 81 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 82 | // |
| emilmont | 10:3bc89ef62ce7 | 83 | // <e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084) |
| emilmont | 10:3bc89ef62ce7 | 84 | // <i> F_in is in the range of 1 MHz to 25 MHz |
| emilmont | 10:3bc89ef62ce7 | 85 | // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz |
| emilmont | 10:3bc89ef62ce7 | 86 | // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz |
| emilmont | 10:3bc89ef62ce7 | 87 | // |
| emilmont | 10:3bc89ef62ce7 | 88 | // <o4.0..4> MSEL: PLL Multiplier Value |
| emilmont | 10:3bc89ef62ce7 | 89 | // <i> M Value |
| emilmont | 10:3bc89ef62ce7 | 90 | // <1-32><#-1> |
| emilmont | 10:3bc89ef62ce7 | 91 | // |
| emilmont | 10:3bc89ef62ce7 | 92 | // <o4.5..6> PSEL: PLL Divider Value |
| emilmont | 10:3bc89ef62ce7 | 93 | // <i> P Value |
| emilmont | 10:3bc89ef62ce7 | 94 | // <0=> 1 |
| emilmont | 10:3bc89ef62ce7 | 95 | // <1=> 2 |
| emilmont | 10:3bc89ef62ce7 | 96 | // <2=> 4 |
| emilmont | 10:3bc89ef62ce7 | 97 | // <3=> 8 |
| emilmont | 10:3bc89ef62ce7 | 98 | // </e> |
| emilmont | 10:3bc89ef62ce7 | 99 | // |
| emilmont | 10:3bc89ef62ce7 | 100 | // <e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4) |
| emilmont | 10:3bc89ef62ce7 | 101 | // <i> F_in is in the range of 1 MHz to 25 MHz |
| emilmont | 10:3bc89ef62ce7 | 102 | // <i> F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz |
| emilmont | 10:3bc89ef62ce7 | 103 | // <i> PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz |
| emilmont | 10:3bc89ef62ce7 | 104 | // |
| emilmont | 10:3bc89ef62ce7 | 105 | // <o6.0..4> MSEL: PLL Multiplier Value |
| emilmont | 10:3bc89ef62ce7 | 106 | // <i> M Value |
| emilmont | 10:3bc89ef62ce7 | 107 | // <1-32><#-1> |
| emilmont | 10:3bc89ef62ce7 | 108 | // |
| emilmont | 10:3bc89ef62ce7 | 109 | // <o6.5..6> PSEL: PLL Divider Value |
| emilmont | 10:3bc89ef62ce7 | 110 | // <i> P Value |
| emilmont | 10:3bc89ef62ce7 | 111 | // <0=> 1 |
| emilmont | 10:3bc89ef62ce7 | 112 | // <1=> 2 |
| emilmont | 10:3bc89ef62ce7 | 113 | // <2=> 4 |
| emilmont | 10:3bc89ef62ce7 | 114 | // <3=> 8 |
| emilmont | 10:3bc89ef62ce7 | 115 | // </e> |
| emilmont | 10:3bc89ef62ce7 | 116 | // |
| emilmont | 10:3bc89ef62ce7 | 117 | // <h> CPU Clock Selection Register (CCLKSEL - address 0x400F C104) |
| emilmont | 10:3bc89ef62ce7 | 118 | // <o7.0..4> CCLKDIV: Select the value for divider of CPU clock (CCLK) |
| emilmont | 10:3bc89ef62ce7 | 119 | // <i> 0: The divider is turned off. No clock will be provided to the CPU |
| emilmont | 10:3bc89ef62ce7 | 120 | // <i> n: The input clock is divided by n to produce the CPU clock |
| emilmont | 10:3bc89ef62ce7 | 121 | // <0-31> |
| emilmont | 10:3bc89ef62ce7 | 122 | // |
| emilmont | 10:3bc89ef62ce7 | 123 | // <o7.8> CCLKSEL: Select the input to the divider of CPU clock |
| emilmont | 10:3bc89ef62ce7 | 124 | // <0=> sysclk clock is used |
| emilmont | 10:3bc89ef62ce7 | 125 | // <1=> Main PLL0 clock is used |
| emilmont | 10:3bc89ef62ce7 | 126 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 127 | // |
| emilmont | 10:3bc89ef62ce7 | 128 | // <h> USB Clock Selection Register (USBCLKSEL - 0x400F C108) |
| emilmont | 10:3bc89ef62ce7 | 129 | // <o8.0..4> USBDIV: USB clock (source PLL0) divider selection |
| emilmont | 10:3bc89ef62ce7 | 130 | // <0=> Divider is off and no clock provides to USB subsystem |
| emilmont | 10:3bc89ef62ce7 | 131 | // <4=> Divider value is 4 (The source clock is divided by 4) |
| emilmont | 10:3bc89ef62ce7 | 132 | // <6=> Divider value is 6 (The source clock is divided by 6) |
| emilmont | 10:3bc89ef62ce7 | 133 | // |
| emilmont | 10:3bc89ef62ce7 | 134 | // <o8.8..9> USBSEL: Select the source for USB clock divider |
| emilmont | 10:3bc89ef62ce7 | 135 | // <i> When CPU clock is selected, the USB can be accessed |
| emilmont | 10:3bc89ef62ce7 | 136 | // <i> by software but cannot perform USB functions |
| emilmont | 10:3bc89ef62ce7 | 137 | // <0=> sysclk clock (the clock input to PLL0) |
| emilmont | 10:3bc89ef62ce7 | 138 | // <1=> The clock output from PLL0 |
| emilmont | 10:3bc89ef62ce7 | 139 | // <2=> The clock output from PLL1 |
| emilmont | 10:3bc89ef62ce7 | 140 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 141 | // |
| emilmont | 10:3bc89ef62ce7 | 142 | // <h> EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100) |
| emilmont | 10:3bc89ef62ce7 | 143 | // <o9.0> EMCDIV: Set the divider for EMC clock |
| emilmont | 10:3bc89ef62ce7 | 144 | // <0=> Divider value is 1 |
| emilmont | 10:3bc89ef62ce7 | 145 | // <1=> Divider value is 2 (EMC clock is equal a half of input clock) |
| emilmont | 10:3bc89ef62ce7 | 146 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 147 | // |
| emilmont | 10:3bc89ef62ce7 | 148 | // <h> Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8) |
| emilmont | 10:3bc89ef62ce7 | 149 | // <o10.0..4> PCLKDIV: APB Peripheral clock divider |
| emilmont | 10:3bc89ef62ce7 | 150 | // <i> 0: The divider is turned off. No clock will be provided to APB peripherals |
| emilmont | 10:3bc89ef62ce7 | 151 | // <i> n: The input clock is divided by n to produce the APB peripheral clock |
| emilmont | 10:3bc89ef62ce7 | 152 | // <0-31> |
| emilmont | 10:3bc89ef62ce7 | 153 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 154 | // |
| emilmont | 10:3bc89ef62ce7 | 155 | // <h> SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4) |
| emilmont | 10:3bc89ef62ce7 | 156 | // <o11.0..4> SPIFIDIV: Set the divider for SPIFI clock |
| emilmont | 10:3bc89ef62ce7 | 157 | // <i> 0: The divider is turned off. No clock will be provided to the SPIFI |
| emilmont | 10:3bc89ef62ce7 | 158 | // <i> n: The input clock is divided by n to produce the SPIFI clock |
| emilmont | 10:3bc89ef62ce7 | 159 | // <0-31> |
| emilmont | 10:3bc89ef62ce7 | 160 | // |
| emilmont | 10:3bc89ef62ce7 | 161 | // <o11.8..9> SPIFISEL: Select the input clock for SPIFI clock divider |
| emilmont | 10:3bc89ef62ce7 | 162 | // <0=> sysclk clock (the clock input to PLL0) |
| emilmont | 10:3bc89ef62ce7 | 163 | // <1=> The clock output from PLL0 |
| emilmont | 10:3bc89ef62ce7 | 164 | // <2=> The clock output from PLL1 |
| emilmont | 10:3bc89ef62ce7 | 165 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 166 | // |
| emilmont | 10:3bc89ef62ce7 | 167 | // <h> Power Control for Peripherals Register (PCONP - address 0x400F C1C8) |
| emilmont | 10:3bc89ef62ce7 | 168 | // <o12.0> PCLCD: LCD controller power/clock enable (bit 0) |
| emilmont | 10:3bc89ef62ce7 | 169 | // <o12.1> PCTIM0: Timer/Counter 0 power/clock enable (bit 1) |
| emilmont | 10:3bc89ef62ce7 | 170 | // <o12.2> PCTIM1: Timer/Counter 1 power/clock enable (bit 2) |
| emilmont | 10:3bc89ef62ce7 | 171 | // <o12.3> PCUART0: UART 0 power/clock enable (bit 3) |
| emilmont | 10:3bc89ef62ce7 | 172 | // <o12.4> PCUART1: UART 1 power/clock enable (bit 4) |
| emilmont | 10:3bc89ef62ce7 | 173 | // <o12.5> PCPWM0: PWM0 power/clock enable (bit 5) |
| emilmont | 10:3bc89ef62ce7 | 174 | // <o12.6> PCPWM1: PWM1 power/clock enable (bit 6) |
| emilmont | 10:3bc89ef62ce7 | 175 | // <o12.7> PCI2C0: I2C 0 interface power/clock enable (bit 7) |
| emilmont | 10:3bc89ef62ce7 | 176 | // <o12.8> PCUART4: UART 4 power/clock enable (bit 8) |
| emilmont | 10:3bc89ef62ce7 | 177 | // <o12.9> PCRTC: RTC and Event Recorder power/clock enable (bit 9) |
| emilmont | 10:3bc89ef62ce7 | 178 | // <o12.10> PCSSP1: SSP 1 interface power/clock enable (bit 10) |
| emilmont | 10:3bc89ef62ce7 | 179 | // <o12.11> PCEMC: External Memory Controller power/clock enable (bit 11) |
| emilmont | 10:3bc89ef62ce7 | 180 | // <o12.12> PCADC: A/D converter power/clock enable (bit 12) |
| emilmont | 10:3bc89ef62ce7 | 181 | // <o12.13> PCCAN1: CAN controller 1 power/clock enable (bit 13) |
| emilmont | 10:3bc89ef62ce7 | 182 | // <o12.14> PCCAN2: CAN controller 2 power/clock enable (bit 14) |
| emilmont | 10:3bc89ef62ce7 | 183 | // <o12.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15) |
| emilmont | 10:3bc89ef62ce7 | 184 | // <o12.17> PCMCPWM: Motor Control PWM power/clock enable (bit 17) |
| emilmont | 10:3bc89ef62ce7 | 185 | // <o12.18> PCQEI: Quadrature encoder interface power/clock enable (bit 18) |
| emilmont | 10:3bc89ef62ce7 | 186 | // <o12.19> PCI2C1: I2C 1 interface power/clock enable (bit 19) |
| emilmont | 10:3bc89ef62ce7 | 187 | // <o12.20> PCSSP2: SSP 2 interface power/clock enable (bit 20) |
| emilmont | 10:3bc89ef62ce7 | 188 | // <o12.21> PCSSP0: SSP 0 interface power/clock enable (bit 21) |
| emilmont | 10:3bc89ef62ce7 | 189 | // <o12.22> PCTIM2: Timer 2 power/clock enable (bit 22) |
| emilmont | 10:3bc89ef62ce7 | 190 | // <o12.23> PCTIM3: Timer 3 power/clock enable (bit 23) |
| emilmont | 10:3bc89ef62ce7 | 191 | // <o12.24> PCUART2: UART 2 power/clock enable (bit 24) |
| emilmont | 10:3bc89ef62ce7 | 192 | // <o12.25> PCUART3: UART 3 power/clock enable (bit 25) |
| emilmont | 10:3bc89ef62ce7 | 193 | // <o12.26> PCI2C2: I2C 2 interface power/clock enable (bit 26) |
| emilmont | 10:3bc89ef62ce7 | 194 | // <o12.27> PCI2S: I2S interface power/clock enable (bit 27) |
| emilmont | 10:3bc89ef62ce7 | 195 | // <o12.28> PCSDC: SD Card interface power/clock enable (bit 28) |
| emilmont | 10:3bc89ef62ce7 | 196 | // <o12.29> PCGPDMA: GPDMA function power/clock enable (bit 29) |
| emilmont | 10:3bc89ef62ce7 | 197 | // <o12.30> PCENET: Ethernet block power/clock enable (bit 30) |
| emilmont | 10:3bc89ef62ce7 | 198 | // <o12.31> PCUSB: USB interface power/clock enable (bit 31) |
| emilmont | 10:3bc89ef62ce7 | 199 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 200 | // |
| emilmont | 10:3bc89ef62ce7 | 201 | // <h> Clock Output Configuration Register (CLKOUTCFG) |
| emilmont | 10:3bc89ef62ce7 | 202 | // <o13.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection |
| emilmont | 10:3bc89ef62ce7 | 203 | // <0=> CPU clock |
| emilmont | 10:3bc89ef62ce7 | 204 | // <1=> Main Oscillator |
| emilmont | 10:3bc89ef62ce7 | 205 | // <2=> Internal RC Oscillator |
| emilmont | 10:3bc89ef62ce7 | 206 | // <3=> USB clock |
| emilmont | 10:3bc89ef62ce7 | 207 | // <4=> RTC Oscillator |
| emilmont | 10:3bc89ef62ce7 | 208 | // <5=> unused |
| emilmont | 10:3bc89ef62ce7 | 209 | // <6=> Watchdog Oscillator |
| emilmont | 10:3bc89ef62ce7 | 210 | // |
| emilmont | 10:3bc89ef62ce7 | 211 | // <o13.4..7> CLKOUTDIV: Output Clock Divider |
| emilmont | 10:3bc89ef62ce7 | 212 | // <1-16><#-1> |
| emilmont | 10:3bc89ef62ce7 | 213 | // |
| emilmont | 10:3bc89ef62ce7 | 214 | // <o13.8> CLKOUT_EN: CLKOUT enable |
| emilmont | 10:3bc89ef62ce7 | 215 | // </h> |
| emilmont | 10:3bc89ef62ce7 | 216 | // |
| emilmont | 10:3bc89ef62ce7 | 217 | // </e> |
| emilmont | 10:3bc89ef62ce7 | 218 | */ |
| emilmont | 10:3bc89ef62ce7 | 219 | |
| emilmont | 10:3bc89ef62ce7 | 220 | #define CLOCK_SETUP 1 |
| emilmont | 10:3bc89ef62ce7 | 221 | #define SCS_Val 0x00000020 |
| emilmont | 10:3bc89ef62ce7 | 222 | #define CLKSRCSEL_Val 0x00000001 |
| emilmont | 10:3bc89ef62ce7 | 223 | #define PLL0_SETUP 1 |
| emilmont | 10:3bc89ef62ce7 | 224 | #define PLL0CFG_Val 0x00000009 |
| emilmont | 10:3bc89ef62ce7 | 225 | #define PLL1_SETUP 1 |
| emilmont | 10:3bc89ef62ce7 | 226 | #define PLL1CFG_Val 0x00000023 |
| emilmont | 10:3bc89ef62ce7 | 227 | #define CCLKSEL_Val 0x00000101 |
| emilmont | 10:3bc89ef62ce7 | 228 | #define USBCLKSEL_Val 0x00000201 |
| emilmont | 10:3bc89ef62ce7 | 229 | #define EMCCLKSEL_Val 0x00000001 |
| emilmont | 10:3bc89ef62ce7 | 230 | #define PCLKSEL_Val 0x00000002 |
| emilmont | 10:3bc89ef62ce7 | 231 | #define SPIFICLKSEL_Val 0x00000002 |
| emilmont | 10:3bc89ef62ce7 | 232 | #define PCONP_Val 0x042887DE |
| emilmont | 10:3bc89ef62ce7 | 233 | #define CLKOUTCFG_Val 0x00000100 |
| emilmont | 10:3bc89ef62ce7 | 234 | |
| emilmont | 10:3bc89ef62ce7 | 235 | #ifdef CORE_M4 |
| emilmont | 10:3bc89ef62ce7 | 236 | #define LPC_CPACR 0xE000ED88 |
| emilmont | 10:3bc89ef62ce7 | 237 | |
| emilmont | 10:3bc89ef62ce7 | 238 | #define SCB_MVFR0 0xE000EF40 |
| emilmont | 10:3bc89ef62ce7 | 239 | #define SCB_MVFR0_RESET 0x10110021 |
| emilmont | 10:3bc89ef62ce7 | 240 | |
| emilmont | 10:3bc89ef62ce7 | 241 | #define SCB_MVFR1 0xE000EF44 |
| emilmont | 10:3bc89ef62ce7 | 242 | #define SCB_MVFR1_RESET 0x11000011 |
| emilmont | 10:3bc89ef62ce7 | 243 | #endif |
| emilmont | 10:3bc89ef62ce7 | 244 | |
| emilmont | 10:3bc89ef62ce7 | 245 | |
| emilmont | 10:3bc89ef62ce7 | 246 | /*--------------------- Flash Accelerator Configuration ---------------------- |
| emilmont | 10:3bc89ef62ce7 | 247 | // |
| emilmont | 10:3bc89ef62ce7 | 248 | // <e> Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000) |
| emilmont | 10:3bc89ef62ce7 | 249 | // <o1.12..15> FLASHTIM: Flash Access Time |
| emilmont | 10:3bc89ef62ce7 | 250 | // <0=> 1 CPU clock (for CPU clock up to 20 MHz) |
| emilmont | 10:3bc89ef62ce7 | 251 | // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) |
| emilmont | 10:3bc89ef62ce7 | 252 | // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) |
| emilmont | 10:3bc89ef62ce7 | 253 | // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) |
| emilmont | 10:3bc89ef62ce7 | 254 | // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) |
| emilmont | 10:3bc89ef62ce7 | 255 | // <5=> 6 CPU clocks (for any CPU clock) |
| emilmont | 10:3bc89ef62ce7 | 256 | // </e> |
| emilmont | 10:3bc89ef62ce7 | 257 | */ |
| emilmont | 10:3bc89ef62ce7 | 258 | |
| emilmont | 10:3bc89ef62ce7 | 259 | #define FLASH_SETUP 1 |
| emilmont | 10:3bc89ef62ce7 | 260 | #define FLASHCFG_Val 0x00005000 |
| emilmont | 10:3bc89ef62ce7 | 261 | |
| emilmont | 10:3bc89ef62ce7 | 262 | /*---------------------------------------------------------------------------- |
| emilmont | 10:3bc89ef62ce7 | 263 | Check the register settings |
| emilmont | 10:3bc89ef62ce7 | 264 | *----------------------------------------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 265 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
| emilmont | 10:3bc89ef62ce7 | 266 | #define CHECK_RSVD(val, mask) (val & mask) |
| emilmont | 10:3bc89ef62ce7 | 267 | |
| emilmont | 10:3bc89ef62ce7 | 268 | /* Clock Configuration -------------------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 269 | #if (CHECK_RSVD((SCS_Val), ~0x0000003F)) |
| emilmont | 10:3bc89ef62ce7 | 270 | #error "SCS: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 271 | #endif |
| emilmont | 10:3bc89ef62ce7 | 272 | |
| emilmont | 10:3bc89ef62ce7 | 273 | #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1)) |
| emilmont | 10:3bc89ef62ce7 | 274 | #error "CLKSRCSEL: Value out of range!" |
| emilmont | 10:3bc89ef62ce7 | 275 | #endif |
| emilmont | 10:3bc89ef62ce7 | 276 | |
| emilmont | 10:3bc89ef62ce7 | 277 | #if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F)) |
| emilmont | 10:3bc89ef62ce7 | 278 | #error "PLL0CFG: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 279 | #endif |
| emilmont | 10:3bc89ef62ce7 | 280 | |
| emilmont | 10:3bc89ef62ce7 | 281 | #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) |
| emilmont | 10:3bc89ef62ce7 | 282 | #error "PLL1CFG: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 283 | #endif |
| emilmont | 10:3bc89ef62ce7 | 284 | |
| emilmont | 10:3bc89ef62ce7 | 285 | #if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F)) |
| emilmont | 10:3bc89ef62ce7 | 286 | #error "CCLKSEL: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 287 | #endif |
| emilmont | 10:3bc89ef62ce7 | 288 | |
| emilmont | 10:3bc89ef62ce7 | 289 | #if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F)) |
| emilmont | 10:3bc89ef62ce7 | 290 | #error "USBCLKSEL: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 291 | #endif |
| emilmont | 10:3bc89ef62ce7 | 292 | |
| emilmont | 10:3bc89ef62ce7 | 293 | #if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001)) |
| emilmont | 10:3bc89ef62ce7 | 294 | #error "EMCCLKSEL: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 295 | #endif |
| emilmont | 10:3bc89ef62ce7 | 296 | |
| emilmont | 10:3bc89ef62ce7 | 297 | #if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F)) |
| emilmont | 10:3bc89ef62ce7 | 298 | #error "PCLKSEL: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 299 | #endif |
| emilmont | 10:3bc89ef62ce7 | 300 | |
| emilmont | 10:3bc89ef62ce7 | 301 | #if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF)) |
| emilmont | 10:3bc89ef62ce7 | 302 | #error "PCONP: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 303 | #endif |
| emilmont | 10:3bc89ef62ce7 | 304 | |
| emilmont | 10:3bc89ef62ce7 | 305 | #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) |
| emilmont | 10:3bc89ef62ce7 | 306 | #error "CLKOUTCFG: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 307 | #endif |
| emilmont | 10:3bc89ef62ce7 | 308 | |
| emilmont | 10:3bc89ef62ce7 | 309 | /* Flash Accelerator Configuration -------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 310 | #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000)) |
| emilmont | 10:3bc89ef62ce7 | 311 | #warning "FLASHCFG: Invalid values of reserved bits!" |
| emilmont | 10:3bc89ef62ce7 | 312 | #endif |
| emilmont | 10:3bc89ef62ce7 | 313 | |
| emilmont | 10:3bc89ef62ce7 | 314 | |
| emilmont | 10:3bc89ef62ce7 | 315 | /*---------------------------------------------------------------------------- |
| emilmont | 10:3bc89ef62ce7 | 316 | DEFINES |
| emilmont | 10:3bc89ef62ce7 | 317 | *----------------------------------------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 318 | /* pll_out_clk = F_cco / (2 � P) |
| emilmont | 10:3bc89ef62ce7 | 319 | F_cco = pll_in_clk � M � 2 � P */ |
| emilmont | 10:3bc89ef62ce7 | 320 | #define __M ((PLL0CFG_Val & 0x1F) + 1) |
| emilmont | 10:3bc89ef62ce7 | 321 | #define __PLL0_CLK(__F_IN) (__F_IN * __M) |
| emilmont | 10:3bc89ef62ce7 | 322 | #define __CCLK_DIV (CCLKSEL_Val & 0x1F) |
| emilmont | 10:3bc89ef62ce7 | 323 | #define __PCLK_DIV (PCLKSEL_Val & 0x1F) |
| emilmont | 10:3bc89ef62ce7 | 324 | #define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1) |
| emilmont | 10:3bc89ef62ce7 | 325 | |
| emilmont | 10:3bc89ef62ce7 | 326 | /* Determine core clock frequency according to settings */ |
| emilmont | 10:3bc89ef62ce7 | 327 | #if (CLOCK_SETUP) /* Clock Setup */ |
| emilmont | 10:3bc89ef62ce7 | 328 | |
| emilmont | 10:3bc89ef62ce7 | 329 | #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0) |
| emilmont | 10:3bc89ef62ce7 | 330 | #error "Main Oscillator is selected as clock source but is not enabled!" |
| emilmont | 10:3bc89ef62ce7 | 331 | #endif |
| emilmont | 10:3bc89ef62ce7 | 332 | |
| emilmont | 10:3bc89ef62ce7 | 333 | #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0) |
| emilmont | 10:3bc89ef62ce7 | 334 | #error "Main PLL is selected as clock source but is not enabled!" |
| emilmont | 10:3bc89ef62ce7 | 335 | #endif |
| emilmont | 10:3bc89ef62ce7 | 336 | |
| emilmont | 10:3bc89ef62ce7 | 337 | #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */ |
| emilmont | 10:3bc89ef62ce7 | 338 | #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 339 | #define __CORE_CLK (IRC_OSC / __CCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 340 | #define __PER_CLK (IRC_OSC/ __PCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 341 | #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 342 | #else /* sysclk = osc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 343 | #define __CORE_CLK (OSC_CLK / __CCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 344 | #define __PER_CLK (OSC_CLK/ __PCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 345 | #define __EMC_CLK (__CORE_CLK/ __ECLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 346 | #endif |
| emilmont | 10:3bc89ef62ce7 | 347 | #else /* cclk = pll_clk */ |
| emilmont | 10:3bc89ef62ce7 | 348 | #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 349 | #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 350 | #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 351 | #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 352 | #else /* sysclk = osc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 353 | #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 354 | #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 355 | #define __EMC_CLK (__CORE_CLK / __ECLK_DIV) |
| emilmont | 10:3bc89ef62ce7 | 356 | #endif |
| emilmont | 10:3bc89ef62ce7 | 357 | #endif |
| emilmont | 10:3bc89ef62ce7 | 358 | |
| emilmont | 10:3bc89ef62ce7 | 359 | #else |
| emilmont | 10:3bc89ef62ce7 | 360 | #define __CORE_CLK (IRC_OSC) |
| emilmont | 10:3bc89ef62ce7 | 361 | #define __PER_CLK (IRC_OSC) |
| emilmont | 10:3bc89ef62ce7 | 362 | #define __EMC_CLK (__CORE_CLK) |
| emilmont | 10:3bc89ef62ce7 | 363 | #endif |
| emilmont | 10:3bc89ef62ce7 | 364 | |
| emilmont | 10:3bc89ef62ce7 | 365 | /*---------------------------------------------------------------------------- |
| emilmont | 10:3bc89ef62ce7 | 366 | Clock Variable definitions |
| emilmont | 10:3bc89ef62ce7 | 367 | *----------------------------------------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 368 | uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ |
| emilmont | 10:3bc89ef62ce7 | 369 | uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */ |
| emilmont | 10:3bc89ef62ce7 | 370 | uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */ |
| emilmont | 10:3bc89ef62ce7 | 371 | uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will |
| emilmont | 10:3bc89ef62ce7 | 372 | be updated after call SystemCoreClockUpdate, should be 48MHz*/ |
| emilmont | 10:3bc89ef62ce7 | 373 | |
| emilmont | 10:3bc89ef62ce7 | 374 | |
| emilmont | 10:3bc89ef62ce7 | 375 | /*---------------------------------------------------------------------------- |
| emilmont | 10:3bc89ef62ce7 | 376 | Clock functions |
| emilmont | 10:3bc89ef62ce7 | 377 | *----------------------------------------------------------------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 378 | void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ |
| emilmont | 10:3bc89ef62ce7 | 379 | { |
| emilmont | 10:3bc89ef62ce7 | 380 | /* Determine clock frequency according to clock register values */ |
| emilmont | 10:3bc89ef62ce7 | 381 | if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */ |
| emilmont | 10:3bc89ef62ce7 | 382 | if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 383 | SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 384 | PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 385 | EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); |
| emilmont | 10:3bc89ef62ce7 | 386 | } |
| emilmont | 10:3bc89ef62ce7 | 387 | else { /* sysclk = osc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 388 | if ((LPC_SC->SCS & 0x40) == 0) { |
| emilmont | 10:3bc89ef62ce7 | 389 | SystemCoreClock = 0; /* this should never happen! */ |
| emilmont | 10:3bc89ef62ce7 | 390 | PeripheralClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 391 | EMCClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 392 | } |
| emilmont | 10:3bc89ef62ce7 | 393 | else { |
| emilmont | 10:3bc89ef62ce7 | 394 | SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 395 | PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 396 | EMCClock = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1)); |
| emilmont | 10:3bc89ef62ce7 | 397 | } |
| emilmont | 10:3bc89ef62ce7 | 398 | } |
| emilmont | 10:3bc89ef62ce7 | 399 | } |
| emilmont | 10:3bc89ef62ce7 | 400 | else { /* cclk = pll_clk */ |
| emilmont | 10:3bc89ef62ce7 | 401 | if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */ |
| emilmont | 10:3bc89ef62ce7 | 402 | SystemCoreClock = 0; /* this should never happen! */ |
| emilmont | 10:3bc89ef62ce7 | 403 | PeripheralClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 404 | EMCClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 405 | } |
| emilmont | 10:3bc89ef62ce7 | 406 | else { |
| emilmont | 10:3bc89ef62ce7 | 407 | if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 408 | uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); |
| emilmont | 10:3bc89ef62ce7 | 409 | uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); |
| emilmont | 10:3bc89ef62ce7 | 410 | uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); |
| emilmont | 10:3bc89ef62ce7 | 411 | uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; |
| emilmont | 10:3bc89ef62ce7 | 412 | SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div); |
| emilmont | 10:3bc89ef62ce7 | 413 | PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div); |
| emilmont | 10:3bc89ef62ce7 | 414 | EMCClock = SystemCoreClock / emc_div; |
| emilmont | 10:3bc89ef62ce7 | 415 | } |
| emilmont | 10:3bc89ef62ce7 | 416 | else { /* sysclk = osc_clk */ |
| emilmont | 10:3bc89ef62ce7 | 417 | if ((LPC_SC->SCS & 0x40) == 0) { |
| emilmont | 10:3bc89ef62ce7 | 418 | SystemCoreClock = 0; /* this should never happen! */ |
| emilmont | 10:3bc89ef62ce7 | 419 | PeripheralClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 420 | EMCClock = 0; |
| emilmont | 10:3bc89ef62ce7 | 421 | } |
| emilmont | 10:3bc89ef62ce7 | 422 | else { |
| emilmont | 10:3bc89ef62ce7 | 423 | uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); |
| emilmont | 10:3bc89ef62ce7 | 424 | uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F); |
| emilmont | 10:3bc89ef62ce7 | 425 | uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F); |
| emilmont | 10:3bc89ef62ce7 | 426 | uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1; |
| emilmont | 10:3bc89ef62ce7 | 427 | SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div); |
| emilmont | 10:3bc89ef62ce7 | 428 | PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div); |
| emilmont | 10:3bc89ef62ce7 | 429 | EMCClock = SystemCoreClock / emc_div; |
| emilmont | 10:3bc89ef62ce7 | 430 | } |
| emilmont | 10:3bc89ef62ce7 | 431 | } |
| emilmont | 10:3bc89ef62ce7 | 432 | } |
| emilmont | 10:3bc89ef62ce7 | 433 | } |
| emilmont | 10:3bc89ef62ce7 | 434 | /* ---update USBClock------------------*/ |
| emilmont | 10:3bc89ef62ce7 | 435 | if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider |
| emilmont | 10:3bc89ef62ce7 | 436 | { |
| emilmont | 10:3bc89ef62ce7 | 437 | switch (LPC_SC->USBCLKSEL & 0x1F) |
| emilmont | 10:3bc89ef62ce7 | 438 | { |
| emilmont | 10:3bc89ef62ce7 | 439 | case 0: |
| emilmont | 10:3bc89ef62ce7 | 440 | USBClock = 0; //no clock will be provided to the USB subsystem |
| emilmont | 10:3bc89ef62ce7 | 441 | break; |
| emilmont | 10:3bc89ef62ce7 | 442 | case 4: |
| emilmont | 10:3bc89ef62ce7 | 443 | case 6: |
| emilmont | 10:3bc89ef62ce7 | 444 | { |
| emilmont | 10:3bc89ef62ce7 | 445 | uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1); |
| emilmont | 10:3bc89ef62ce7 | 446 | uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F); |
| emilmont | 10:3bc89ef62ce7 | 447 | if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc |
| emilmont | 10:3bc89ef62ce7 | 448 | USBClock = OSC_CLK * mul / usb_div; |
| emilmont | 10:3bc89ef62ce7 | 449 | else //pll_clk_in = irc_clk |
| emilmont | 10:3bc89ef62ce7 | 450 | USBClock = IRC_OSC * mul / usb_div; |
| emilmont | 10:3bc89ef62ce7 | 451 | } |
| emilmont | 10:3bc89ef62ce7 | 452 | break; |
| emilmont | 10:3bc89ef62ce7 | 453 | default: |
| emilmont | 10:3bc89ef62ce7 | 454 | USBClock = 0; /* this should never happen! */ |
| emilmont | 10:3bc89ef62ce7 | 455 | } |
| emilmont | 10:3bc89ef62ce7 | 456 | } |
| emilmont | 10:3bc89ef62ce7 | 457 | else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1) |
| emilmont | 10:3bc89ef62ce7 | 458 | { |
| emilmont | 10:3bc89ef62ce7 | 459 | if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc |
| emilmont | 10:3bc89ef62ce7 | 460 | USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1)); |
| emilmont | 10:3bc89ef62ce7 | 461 | else //pll1_clk_in = irc_clk |
| emilmont | 10:3bc89ef62ce7 | 462 | USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1)); |
| emilmont | 10:3bc89ef62ce7 | 463 | } |
| emilmont | 10:3bc89ef62ce7 | 464 | else |
| emilmont | 10:3bc89ef62ce7 | 465 | USBClock = 0; /* this should never happen! */ |
| emilmont | 10:3bc89ef62ce7 | 466 | } |
| emilmont | 10:3bc89ef62ce7 | 467 | |
| emilmont | 10:3bc89ef62ce7 | 468 | /* Determine clock frequency according to clock register values */ |
| emilmont | 10:3bc89ef62ce7 | 469 | |
| emilmont | 10:3bc89ef62ce7 | 470 | #ifdef CORE_M4 |
| emilmont | 10:3bc89ef62ce7 | 471 | |
| emilmont | 10:3bc89ef62ce7 | 472 | void fpu_init(void) |
| emilmont | 10:3bc89ef62ce7 | 473 | { |
| emilmont | 10:3bc89ef62ce7 | 474 | // from arm trm manual: |
| emilmont | 10:3bc89ef62ce7 | 475 | // ; CPACR is located at address 0xE000ED88 |
| emilmont | 10:3bc89ef62ce7 | 476 | // LDR.W R0, =0xE000ED88 |
| emilmont | 10:3bc89ef62ce7 | 477 | // ; Read CPACR |
| emilmont | 10:3bc89ef62ce7 | 478 | // LDR R1, [R0] |
| emilmont | 10:3bc89ef62ce7 | 479 | // ; Set bits 20-23 to enable CP10 and CP11 coprocessors |
| emilmont | 10:3bc89ef62ce7 | 480 | // ORR R1, R1, #(0xF << 20) |
| emilmont | 10:3bc89ef62ce7 | 481 | // ; Write back the modified value to the CPACR |
| emilmont | 10:3bc89ef62ce7 | 482 | // STR R1, [R0] |
| emilmont | 10:3bc89ef62ce7 | 483 | |
| emilmont | 10:3bc89ef62ce7 | 484 | |
| emilmont | 10:3bc89ef62ce7 | 485 | volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR; |
| emilmont | 10:3bc89ef62ce7 | 486 | volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0; |
| emilmont | 10:3bc89ef62ce7 | 487 | volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1; |
| emilmont | 10:3bc89ef62ce7 | 488 | volatile uint32_t Cpacr; |
| emilmont | 10:3bc89ef62ce7 | 489 | volatile uint32_t Mvfr0; |
| emilmont | 10:3bc89ef62ce7 | 490 | volatile uint32_t Mvfr1; |
| emilmont | 10:3bc89ef62ce7 | 491 | char vfpPresent = 0; |
| emilmont | 10:3bc89ef62ce7 | 492 | |
| emilmont | 10:3bc89ef62ce7 | 493 | Mvfr0 = *regMvfr0; |
| emilmont | 10:3bc89ef62ce7 | 494 | Mvfr1 = *regMvfr1; |
| emilmont | 10:3bc89ef62ce7 | 495 | |
| emilmont | 10:3bc89ef62ce7 | 496 | vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1)); |
| emilmont | 10:3bc89ef62ce7 | 497 | |
| emilmont | 10:3bc89ef62ce7 | 498 | if(vfpPresent) |
| emilmont | 10:3bc89ef62ce7 | 499 | { |
| emilmont | 10:3bc89ef62ce7 | 500 | Cpacr = *regCpacr; |
| emilmont | 10:3bc89ef62ce7 | 501 | Cpacr |= (0xF << 20); |
| emilmont | 10:3bc89ef62ce7 | 502 | *regCpacr = Cpacr; // enable CP10 and CP11 for full access |
| emilmont | 10:3bc89ef62ce7 | 503 | } |
| emilmont | 10:3bc89ef62ce7 | 504 | |
| emilmont | 10:3bc89ef62ce7 | 505 | } |
| emilmont | 10:3bc89ef62ce7 | 506 | #endif |
| emilmont | 10:3bc89ef62ce7 | 507 | |
| emilmont | 10:3bc89ef62ce7 | 508 | /** |
| emilmont | 10:3bc89ef62ce7 | 509 | * Initialize the system |
| emilmont | 10:3bc89ef62ce7 | 510 | * |
| emilmont | 10:3bc89ef62ce7 | 511 | * @param none |
| emilmont | 10:3bc89ef62ce7 | 512 | * @return none |
| emilmont | 10:3bc89ef62ce7 | 513 | * |
| emilmont | 10:3bc89ef62ce7 | 514 | * @brief Setup the microcontroller system. |
| emilmont | 10:3bc89ef62ce7 | 515 | * Initialize the System. |
| emilmont | 10:3bc89ef62ce7 | 516 | */ |
| emilmont | 10:3bc89ef62ce7 | 517 | void SystemInit (void) |
| emilmont | 10:3bc89ef62ce7 | 518 | { |
| emilmont | 10:3bc89ef62ce7 | 519 | #ifndef __CODE_RED |
| emilmont | 10:3bc89ef62ce7 | 520 | #ifdef CORE_M4 |
| emilmont | 10:3bc89ef62ce7 | 521 | fpu_init(); |
| emilmont | 10:3bc89ef62ce7 | 522 | #endif |
| emilmont | 10:3bc89ef62ce7 | 523 | #endif |
| emilmont | 10:3bc89ef62ce7 | 524 | |
| emilmont | 10:3bc89ef62ce7 | 525 | #if (CLOCK_SETUP) /* Clock Setup */ |
| emilmont | 10:3bc89ef62ce7 | 526 | LPC_SC->SCS = SCS_Val; |
| emilmont | 10:3bc89ef62ce7 | 527 | if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ |
| emilmont | 10:3bc89ef62ce7 | 528 | while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ |
| emilmont | 10:3bc89ef62ce7 | 529 | } |
| emilmont | 10:3bc89ef62ce7 | 530 | |
| emilmont | 10:3bc89ef62ce7 | 531 | LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/ |
| emilmont | 10:3bc89ef62ce7 | 532 | |
| emilmont | 10:3bc89ef62ce7 | 533 | #if (PLL0_SETUP) |
| emilmont | 10:3bc89ef62ce7 | 534 | LPC_SC->PLL0CFG = PLL0CFG_Val; |
| emilmont | 10:3bc89ef62ce7 | 535 | LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ |
| emilmont | 10:3bc89ef62ce7 | 536 | LPC_SC->PLL0FEED = 0xAA; |
| emilmont | 10:3bc89ef62ce7 | 537 | LPC_SC->PLL0FEED = 0x55; |
| emilmont | 10:3bc89ef62ce7 | 538 | while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */ |
| emilmont | 10:3bc89ef62ce7 | 539 | #endif |
| emilmont | 10:3bc89ef62ce7 | 540 | |
| emilmont | 10:3bc89ef62ce7 | 541 | #if (PLL1_SETUP) |
| emilmont | 10:3bc89ef62ce7 | 542 | LPC_SC->PLL1CFG = PLL1CFG_Val; |
| emilmont | 10:3bc89ef62ce7 | 543 | LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ |
| emilmont | 10:3bc89ef62ce7 | 544 | LPC_SC->PLL1FEED = 0xAA; |
| emilmont | 10:3bc89ef62ce7 | 545 | LPC_SC->PLL1FEED = 0x55; |
| emilmont | 10:3bc89ef62ce7 | 546 | while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ |
| emilmont | 10:3bc89ef62ce7 | 547 | #endif |
| emilmont | 10:3bc89ef62ce7 | 548 | |
| emilmont | 10:3bc89ef62ce7 | 549 | LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */ |
| emilmont | 10:3bc89ef62ce7 | 550 | LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */ |
| emilmont | 10:3bc89ef62ce7 | 551 | LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */ |
| emilmont | 10:3bc89ef62ce7 | 552 | LPC_SC->SPIFICLKSEL = SPIFICLKSEL_Val; /* SPIFI Clock Selection */ |
| emilmont | 10:3bc89ef62ce7 | 553 | LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */ |
| emilmont | 10:3bc89ef62ce7 | 554 | LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ |
| emilmont | 10:3bc89ef62ce7 | 555 | LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ |
| emilmont | 10:3bc89ef62ce7 | 556 | #endif |
| emilmont | 10:3bc89ef62ce7 | 557 | |
| emilmont | 10:3bc89ef62ce7 | 558 | LPC_SC->PBOOST |= 0x03; /* Power Boost control */ |
| emilmont | 10:3bc89ef62ce7 | 559 | |
| emilmont | 10:3bc89ef62ce7 | 560 | #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ |
| emilmont | 10:3bc89ef62ce7 | 561 | LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; |
| emilmont | 10:3bc89ef62ce7 | 562 | #endif |
| emilmont | 10:3bc89ef62ce7 | 563 | #ifndef __CODE_RED |
| emilmont | 10:3bc89ef62ce7 | 564 | #ifdef __RAM_MODE__ |
| emilmont | 10:3bc89ef62ce7 | 565 | SCB->VTOR = 0x10000000 & 0x3FFFFF80; |
| emilmont | 10:3bc89ef62ce7 | 566 | #else |
| emilmont | 10:3bc89ef62ce7 | 567 | SCB->VTOR = 0x00000000 & 0x3FFFFF80; |
| emilmont | 10:3bc89ef62ce7 | 568 | #endif |
| emilmont | 10:3bc89ef62ce7 | 569 | #endif |
| emilmont | 10:3bc89ef62ce7 | 570 | SystemCoreClockUpdate(); |
| emilmont | 10:3bc89ef62ce7 | 571 | } |
