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Last commit 20 Feb 2019 by mbed official

vendor/NXP/LPC4088/cmsis/core_cmInstr.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file core_cmInstr.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 10:3bc89ef62ce7 4 * @version V3.03
emilmont 10:3bc89ef62ce7 5 * @date 29. August 2012
emilmont 10:3bc89ef62ce7 6 *
emilmont 10:3bc89ef62ce7 7 * @note
emilmont 10:3bc89ef62ce7 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * @par
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * @par
emilmont 10:3bc89ef62ce7 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 21 *
emilmont 10:3bc89ef62ce7 22 ******************************************************************************/
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 #ifndef __CORE_CMINSTR_H
emilmont 10:3bc89ef62ce7 25 #define __CORE_CMINSTR_H
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 /* ########################## Core Instruction Access ######################### */
emilmont 10:3bc89ef62ce7 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 10:3bc89ef62ce7 30 Access to dedicated instructions
emilmont 10:3bc89ef62ce7 31 @{
emilmont 10:3bc89ef62ce7 32 */
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 10:3bc89ef62ce7 35 /* ARM armcc specific functions */
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 #if (__ARMCC_VERSION < 400677)
emilmont 10:3bc89ef62ce7 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 10:3bc89ef62ce7 39 #endif
emilmont 10:3bc89ef62ce7 40
emilmont 10:3bc89ef62ce7 41
emilmont 10:3bc89ef62ce7 42 /** \brief No Operation
emilmont 10:3bc89ef62ce7 43
emilmont 10:3bc89ef62ce7 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 10:3bc89ef62ce7 45 */
emilmont 10:3bc89ef62ce7 46 #define __NOP __nop
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48
emilmont 10:3bc89ef62ce7 49 /** \brief Wait For Interrupt
emilmont 10:3bc89ef62ce7 50
emilmont 10:3bc89ef62ce7 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 10:3bc89ef62ce7 52 until one of a number of events occurs.
emilmont 10:3bc89ef62ce7 53 */
emilmont 10:3bc89ef62ce7 54 #define __WFI __wfi
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 /** \brief Wait For Event
emilmont 10:3bc89ef62ce7 58
emilmont 10:3bc89ef62ce7 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 10:3bc89ef62ce7 60 a low-power state until one of a number of events occurs.
emilmont 10:3bc89ef62ce7 61 */
emilmont 10:3bc89ef62ce7 62 #define __WFE __wfe
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64
emilmont 10:3bc89ef62ce7 65 /** \brief Send Event
emilmont 10:3bc89ef62ce7 66
emilmont 10:3bc89ef62ce7 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 10:3bc89ef62ce7 68 */
emilmont 10:3bc89ef62ce7 69 #define __SEV __sev
emilmont 10:3bc89ef62ce7 70
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 /** \brief Instruction Synchronization Barrier
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 10:3bc89ef62ce7 75 so that all instructions following the ISB are fetched from cache or
emilmont 10:3bc89ef62ce7 76 memory, after the instruction has been completed.
emilmont 10:3bc89ef62ce7 77 */
emilmont 10:3bc89ef62ce7 78 #define __ISB() __isb(0xF)
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80
emilmont 10:3bc89ef62ce7 81 /** \brief Data Synchronization Barrier
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 This function acts as a special kind of Data Memory Barrier.
emilmont 10:3bc89ef62ce7 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 10:3bc89ef62ce7 85 */
emilmont 10:3bc89ef62ce7 86 #define __DSB() __dsb(0xF)
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88
emilmont 10:3bc89ef62ce7 89 /** \brief Data Memory Barrier
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 This function ensures the apparent order of the explicit memory operations before
emilmont 10:3bc89ef62ce7 92 and after the instruction, without ensuring their completion.
emilmont 10:3bc89ef62ce7 93 */
emilmont 10:3bc89ef62ce7 94 #define __DMB() __dmb(0xF)
emilmont 10:3bc89ef62ce7 95
emilmont 10:3bc89ef62ce7 96
emilmont 10:3bc89ef62ce7 97 /** \brief Reverse byte order (32 bit)
emilmont 10:3bc89ef62ce7 98
emilmont 10:3bc89ef62ce7 99 This function reverses the byte order in integer value.
emilmont 10:3bc89ef62ce7 100
emilmont 10:3bc89ef62ce7 101 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 102 \return Reversed value
emilmont 10:3bc89ef62ce7 103 */
emilmont 10:3bc89ef62ce7 104 #define __REV __rev
emilmont 10:3bc89ef62ce7 105
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 /** \brief Reverse byte order (16 bit)
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 This function reverses the byte order in two unsigned short values.
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 112 \return Reversed value
emilmont 10:3bc89ef62ce7 113 */
emilmont 10:3bc89ef62ce7 114 #ifndef __NO_EMBEDDED_ASM
emilmont 10:3bc89ef62ce7 115 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 10:3bc89ef62ce7 116 {
emilmont 10:3bc89ef62ce7 117 rev16 r0, r0
emilmont 10:3bc89ef62ce7 118 bx lr
emilmont 10:3bc89ef62ce7 119 }
emilmont 10:3bc89ef62ce7 120 #endif
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 /** \brief Reverse byte order in signed short value
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 127 \return Reversed value
emilmont 10:3bc89ef62ce7 128 */
emilmont 10:3bc89ef62ce7 129 #ifndef __NO_EMBEDDED_ASM
emilmont 10:3bc89ef62ce7 130 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 10:3bc89ef62ce7 131 {
emilmont 10:3bc89ef62ce7 132 revsh r0, r0
emilmont 10:3bc89ef62ce7 133 bx lr
emilmont 10:3bc89ef62ce7 134 }
emilmont 10:3bc89ef62ce7 135 #endif
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137
emilmont 10:3bc89ef62ce7 138 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 10:3bc89ef62ce7 139
emilmont 10:3bc89ef62ce7 140 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 10:3bc89ef62ce7 141
emilmont 10:3bc89ef62ce7 142 \param [in] value Value to rotate
emilmont 10:3bc89ef62ce7 143 \param [in] value Number of Bits to rotate
emilmont 10:3bc89ef62ce7 144 \return Rotated value
emilmont 10:3bc89ef62ce7 145 */
emilmont 10:3bc89ef62ce7 146 #define __ROR __ror
emilmont 10:3bc89ef62ce7 147
emilmont 10:3bc89ef62ce7 148
emilmont 10:3bc89ef62ce7 149 /** \brief Breakpoint
emilmont 10:3bc89ef62ce7 150
emilmont 10:3bc89ef62ce7 151 This function causes the processor to enter Debug state.
emilmont 10:3bc89ef62ce7 152 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 \param [in] value is ignored by the processor.
emilmont 10:3bc89ef62ce7 155 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 10:3bc89ef62ce7 156 */
emilmont 10:3bc89ef62ce7 157 #define __BKPT(value) __breakpoint(value)
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 #if (__CORTEX_M >= 0x03)
emilmont 10:3bc89ef62ce7 161
emilmont 10:3bc89ef62ce7 162 /** \brief Reverse bit order of value
emilmont 10:3bc89ef62ce7 163
emilmont 10:3bc89ef62ce7 164 This function reverses the bit order of the given value.
emilmont 10:3bc89ef62ce7 165
emilmont 10:3bc89ef62ce7 166 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 167 \return Reversed value
emilmont 10:3bc89ef62ce7 168 */
emilmont 10:3bc89ef62ce7 169 #define __RBIT __rbit
emilmont 10:3bc89ef62ce7 170
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 /** \brief LDR Exclusive (8 bit)
emilmont 10:3bc89ef62ce7 173
emilmont 10:3bc89ef62ce7 174 This function performs a exclusive LDR command for 8 bit value.
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 177 \return value of type uint8_t at (*ptr)
emilmont 10:3bc89ef62ce7 178 */
emilmont 10:3bc89ef62ce7 179 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 180
emilmont 10:3bc89ef62ce7 181
emilmont 10:3bc89ef62ce7 182 /** \brief LDR Exclusive (16 bit)
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 This function performs a exclusive LDR command for 16 bit values.
emilmont 10:3bc89ef62ce7 185
emilmont 10:3bc89ef62ce7 186 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 187 \return value of type uint16_t at (*ptr)
emilmont 10:3bc89ef62ce7 188 */
emilmont 10:3bc89ef62ce7 189 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 190
emilmont 10:3bc89ef62ce7 191
emilmont 10:3bc89ef62ce7 192 /** \brief LDR Exclusive (32 bit)
emilmont 10:3bc89ef62ce7 193
emilmont 10:3bc89ef62ce7 194 This function performs a exclusive LDR command for 32 bit values.
emilmont 10:3bc89ef62ce7 195
emilmont 10:3bc89ef62ce7 196 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 197 \return value of type uint32_t at (*ptr)
emilmont 10:3bc89ef62ce7 198 */
emilmont 10:3bc89ef62ce7 199 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 200
emilmont 10:3bc89ef62ce7 201
emilmont 10:3bc89ef62ce7 202 /** \brief STR Exclusive (8 bit)
emilmont 10:3bc89ef62ce7 203
emilmont 10:3bc89ef62ce7 204 This function performs a exclusive STR command for 8 bit values.
emilmont 10:3bc89ef62ce7 205
emilmont 10:3bc89ef62ce7 206 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 207 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 208 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 209 \return 1 Function failed
emilmont 10:3bc89ef62ce7 210 */
emilmont 10:3bc89ef62ce7 211 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 212
emilmont 10:3bc89ef62ce7 213
emilmont 10:3bc89ef62ce7 214 /** \brief STR Exclusive (16 bit)
emilmont 10:3bc89ef62ce7 215
emilmont 10:3bc89ef62ce7 216 This function performs a exclusive STR command for 16 bit values.
emilmont 10:3bc89ef62ce7 217
emilmont 10:3bc89ef62ce7 218 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 219 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 220 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 221 \return 1 Function failed
emilmont 10:3bc89ef62ce7 222 */
emilmont 10:3bc89ef62ce7 223 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 224
emilmont 10:3bc89ef62ce7 225
emilmont 10:3bc89ef62ce7 226 /** \brief STR Exclusive (32 bit)
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228 This function performs a exclusive STR command for 32 bit values.
emilmont 10:3bc89ef62ce7 229
emilmont 10:3bc89ef62ce7 230 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 231 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 232 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 233 \return 1 Function failed
emilmont 10:3bc89ef62ce7 234 */
emilmont 10:3bc89ef62ce7 235 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 236
emilmont 10:3bc89ef62ce7 237
emilmont 10:3bc89ef62ce7 238 /** \brief Remove the exclusive lock
emilmont 10:3bc89ef62ce7 239
emilmont 10:3bc89ef62ce7 240 This function removes the exclusive lock which is created by LDREX.
emilmont 10:3bc89ef62ce7 241
emilmont 10:3bc89ef62ce7 242 */
emilmont 10:3bc89ef62ce7 243 #define __CLREX __clrex
emilmont 10:3bc89ef62ce7 244
emilmont 10:3bc89ef62ce7 245
emilmont 10:3bc89ef62ce7 246 /** \brief Signed Saturate
emilmont 10:3bc89ef62ce7 247
emilmont 10:3bc89ef62ce7 248 This function saturates a signed value.
emilmont 10:3bc89ef62ce7 249
emilmont 10:3bc89ef62ce7 250 \param [in] value Value to be saturated
emilmont 10:3bc89ef62ce7 251 \param [in] sat Bit position to saturate to (1..32)
emilmont 10:3bc89ef62ce7 252 \return Saturated value
emilmont 10:3bc89ef62ce7 253 */
emilmont 10:3bc89ef62ce7 254 #define __SSAT __ssat
emilmont 10:3bc89ef62ce7 255
emilmont 10:3bc89ef62ce7 256
emilmont 10:3bc89ef62ce7 257 /** \brief Unsigned Saturate
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 This function saturates an unsigned value.
emilmont 10:3bc89ef62ce7 260
emilmont 10:3bc89ef62ce7 261 \param [in] value Value to be saturated
emilmont 10:3bc89ef62ce7 262 \param [in] sat Bit position to saturate to (0..31)
emilmont 10:3bc89ef62ce7 263 \return Saturated value
emilmont 10:3bc89ef62ce7 264 */
emilmont 10:3bc89ef62ce7 265 #define __USAT __usat
emilmont 10:3bc89ef62ce7 266
emilmont 10:3bc89ef62ce7 267
emilmont 10:3bc89ef62ce7 268 /** \brief Count leading zeros
emilmont 10:3bc89ef62ce7 269
emilmont 10:3bc89ef62ce7 270 This function counts the number of leading zeros of a data value.
emilmont 10:3bc89ef62ce7 271
emilmont 10:3bc89ef62ce7 272 \param [in] value Value to count the leading zeros
emilmont 10:3bc89ef62ce7 273 \return number of leading zeros in value
emilmont 10:3bc89ef62ce7 274 */
emilmont 10:3bc89ef62ce7 275 #define __CLZ __clz
emilmont 10:3bc89ef62ce7 276
emilmont 10:3bc89ef62ce7 277 #endif /* (__CORTEX_M >= 0x03) */
emilmont 10:3bc89ef62ce7 278
emilmont 10:3bc89ef62ce7 279
emilmont 10:3bc89ef62ce7 280
emilmont 10:3bc89ef62ce7 281 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 10:3bc89ef62ce7 282 /* IAR iccarm specific functions */
emilmont 10:3bc89ef62ce7 283
emilmont 10:3bc89ef62ce7 284 #include <cmsis_iar.h>
emilmont 10:3bc89ef62ce7 285
emilmont 10:3bc89ef62ce7 286
emilmont 10:3bc89ef62ce7 287 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 10:3bc89ef62ce7 288 /* TI CCS specific functions */
emilmont 10:3bc89ef62ce7 289
emilmont 10:3bc89ef62ce7 290 #include <cmsis_ccs.h>
emilmont 10:3bc89ef62ce7 291
emilmont 10:3bc89ef62ce7 292
emilmont 10:3bc89ef62ce7 293 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 294 /* GNU gcc specific functions */
emilmont 10:3bc89ef62ce7 295
emilmont 10:3bc89ef62ce7 296 /** \brief No Operation
emilmont 10:3bc89ef62ce7 297
emilmont 10:3bc89ef62ce7 298 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 10:3bc89ef62ce7 299 */
emilmont 10:3bc89ef62ce7 300 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 10:3bc89ef62ce7 301 {
emilmont 10:3bc89ef62ce7 302 __ASM volatile ("nop");
emilmont 10:3bc89ef62ce7 303 }
emilmont 10:3bc89ef62ce7 304
emilmont 10:3bc89ef62ce7 305
emilmont 10:3bc89ef62ce7 306 /** \brief Wait For Interrupt
emilmont 10:3bc89ef62ce7 307
emilmont 10:3bc89ef62ce7 308 Wait For Interrupt is a hint instruction that suspends execution
emilmont 10:3bc89ef62ce7 309 until one of a number of events occurs.
emilmont 10:3bc89ef62ce7 310 */
emilmont 10:3bc89ef62ce7 311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 10:3bc89ef62ce7 312 {
emilmont 10:3bc89ef62ce7 313 __ASM volatile ("wfi");
emilmont 10:3bc89ef62ce7 314 }
emilmont 10:3bc89ef62ce7 315
emilmont 10:3bc89ef62ce7 316
emilmont 10:3bc89ef62ce7 317 /** \brief Wait For Event
emilmont 10:3bc89ef62ce7 318
emilmont 10:3bc89ef62ce7 319 Wait For Event is a hint instruction that permits the processor to enter
emilmont 10:3bc89ef62ce7 320 a low-power state until one of a number of events occurs.
emilmont 10:3bc89ef62ce7 321 */
emilmont 10:3bc89ef62ce7 322 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 10:3bc89ef62ce7 323 {
emilmont 10:3bc89ef62ce7 324 __ASM volatile ("wfe");
emilmont 10:3bc89ef62ce7 325 }
emilmont 10:3bc89ef62ce7 326
emilmont 10:3bc89ef62ce7 327
emilmont 10:3bc89ef62ce7 328 /** \brief Send Event
emilmont 10:3bc89ef62ce7 329
emilmont 10:3bc89ef62ce7 330 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 10:3bc89ef62ce7 331 */
emilmont 10:3bc89ef62ce7 332 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 10:3bc89ef62ce7 333 {
emilmont 10:3bc89ef62ce7 334 __ASM volatile ("sev");
emilmont 10:3bc89ef62ce7 335 }
emilmont 10:3bc89ef62ce7 336
emilmont 10:3bc89ef62ce7 337
emilmont 10:3bc89ef62ce7 338 /** \brief Instruction Synchronization Barrier
emilmont 10:3bc89ef62ce7 339
emilmont 10:3bc89ef62ce7 340 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 10:3bc89ef62ce7 341 so that all instructions following the ISB are fetched from cache or
emilmont 10:3bc89ef62ce7 342 memory, after the instruction has been completed.
emilmont 10:3bc89ef62ce7 343 */
emilmont 10:3bc89ef62ce7 344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 10:3bc89ef62ce7 345 {
emilmont 10:3bc89ef62ce7 346 __ASM volatile ("isb");
emilmont 10:3bc89ef62ce7 347 }
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349
emilmont 10:3bc89ef62ce7 350 /** \brief Data Synchronization Barrier
emilmont 10:3bc89ef62ce7 351
emilmont 10:3bc89ef62ce7 352 This function acts as a special kind of Data Memory Barrier.
emilmont 10:3bc89ef62ce7 353 It completes when all explicit memory accesses before this instruction complete.
emilmont 10:3bc89ef62ce7 354 */
emilmont 10:3bc89ef62ce7 355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 10:3bc89ef62ce7 356 {
emilmont 10:3bc89ef62ce7 357 __ASM volatile ("dsb");
emilmont 10:3bc89ef62ce7 358 }
emilmont 10:3bc89ef62ce7 359
emilmont 10:3bc89ef62ce7 360
emilmont 10:3bc89ef62ce7 361 /** \brief Data Memory Barrier
emilmont 10:3bc89ef62ce7 362
emilmont 10:3bc89ef62ce7 363 This function ensures the apparent order of the explicit memory operations before
emilmont 10:3bc89ef62ce7 364 and after the instruction, without ensuring their completion.
emilmont 10:3bc89ef62ce7 365 */
emilmont 10:3bc89ef62ce7 366 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 10:3bc89ef62ce7 367 {
emilmont 10:3bc89ef62ce7 368 __ASM volatile ("dmb");
emilmont 10:3bc89ef62ce7 369 }
emilmont 10:3bc89ef62ce7 370
emilmont 10:3bc89ef62ce7 371
emilmont 10:3bc89ef62ce7 372 /** \brief Reverse byte order (32 bit)
emilmont 10:3bc89ef62ce7 373
emilmont 10:3bc89ef62ce7 374 This function reverses the byte order in integer value.
emilmont 10:3bc89ef62ce7 375
emilmont 10:3bc89ef62ce7 376 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 377 \return Reversed value
emilmont 10:3bc89ef62ce7 378 */
emilmont 10:3bc89ef62ce7 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 10:3bc89ef62ce7 380 {
emilmont 10:3bc89ef62ce7 381 uint32_t result;
emilmont 10:3bc89ef62ce7 382
emilmont 10:3bc89ef62ce7 383 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 10:3bc89ef62ce7 384 return(result);
emilmont 10:3bc89ef62ce7 385 }
emilmont 10:3bc89ef62ce7 386
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 /** \brief Reverse byte order (16 bit)
emilmont 10:3bc89ef62ce7 389
emilmont 10:3bc89ef62ce7 390 This function reverses the byte order in two unsigned short values.
emilmont 10:3bc89ef62ce7 391
emilmont 10:3bc89ef62ce7 392 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 393 \return Reversed value
emilmont 10:3bc89ef62ce7 394 */
emilmont 10:3bc89ef62ce7 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 10:3bc89ef62ce7 396 {
emilmont 10:3bc89ef62ce7 397 uint32_t result;
emilmont 10:3bc89ef62ce7 398
emilmont 10:3bc89ef62ce7 399 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 10:3bc89ef62ce7 400 return(result);
emilmont 10:3bc89ef62ce7 401 }
emilmont 10:3bc89ef62ce7 402
emilmont 10:3bc89ef62ce7 403
emilmont 10:3bc89ef62ce7 404 /** \brief Reverse byte order in signed short value
emilmont 10:3bc89ef62ce7 405
emilmont 10:3bc89ef62ce7 406 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 10:3bc89ef62ce7 407
emilmont 10:3bc89ef62ce7 408 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 409 \return Reversed value
emilmont 10:3bc89ef62ce7 410 */
emilmont 10:3bc89ef62ce7 411 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 10:3bc89ef62ce7 412 {
emilmont 10:3bc89ef62ce7 413 uint32_t result;
emilmont 10:3bc89ef62ce7 414
emilmont 10:3bc89ef62ce7 415 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 10:3bc89ef62ce7 416 return(result);
emilmont 10:3bc89ef62ce7 417 }
emilmont 10:3bc89ef62ce7 418
emilmont 10:3bc89ef62ce7 419
emilmont 10:3bc89ef62ce7 420 /** \brief Rotate Right in unsigned value (32 bit)
emilmont 10:3bc89ef62ce7 421
emilmont 10:3bc89ef62ce7 422 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emilmont 10:3bc89ef62ce7 423
emilmont 10:3bc89ef62ce7 424 \param [in] value Value to rotate
emilmont 10:3bc89ef62ce7 425 \param [in] value Number of Bits to rotate
emilmont 10:3bc89ef62ce7 426 \return Rotated value
emilmont 10:3bc89ef62ce7 427 */
emilmont 10:3bc89ef62ce7 428 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emilmont 10:3bc89ef62ce7 429 {
emilmont 10:3bc89ef62ce7 430
emilmont 10:3bc89ef62ce7 431 __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
emilmont 10:3bc89ef62ce7 432 return(op1);
emilmont 10:3bc89ef62ce7 433 }
emilmont 10:3bc89ef62ce7 434
emilmont 10:3bc89ef62ce7 435
emilmont 10:3bc89ef62ce7 436 /** \brief Breakpoint
emilmont 10:3bc89ef62ce7 437
emilmont 10:3bc89ef62ce7 438 This function causes the processor to enter Debug state.
emilmont 10:3bc89ef62ce7 439 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emilmont 10:3bc89ef62ce7 440
emilmont 10:3bc89ef62ce7 441 \param [in] value is ignored by the processor.
emilmont 10:3bc89ef62ce7 442 If required, a debugger can use it to store additional information about the breakpoint.
emilmont 10:3bc89ef62ce7 443 */
emilmont 10:3bc89ef62ce7 444 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emilmont 10:3bc89ef62ce7 445
emilmont 10:3bc89ef62ce7 446
emilmont 10:3bc89ef62ce7 447 #if (__CORTEX_M >= 0x03)
emilmont 10:3bc89ef62ce7 448
emilmont 10:3bc89ef62ce7 449 /** \brief Reverse bit order of value
emilmont 10:3bc89ef62ce7 450
emilmont 10:3bc89ef62ce7 451 This function reverses the bit order of the given value.
emilmont 10:3bc89ef62ce7 452
emilmont 10:3bc89ef62ce7 453 \param [in] value Value to reverse
emilmont 10:3bc89ef62ce7 454 \return Reversed value
emilmont 10:3bc89ef62ce7 455 */
emilmont 10:3bc89ef62ce7 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 10:3bc89ef62ce7 457 {
emilmont 10:3bc89ef62ce7 458 uint32_t result;
emilmont 10:3bc89ef62ce7 459
emilmont 10:3bc89ef62ce7 460 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 10:3bc89ef62ce7 461 return(result);
emilmont 10:3bc89ef62ce7 462 }
emilmont 10:3bc89ef62ce7 463
emilmont 10:3bc89ef62ce7 464
emilmont 10:3bc89ef62ce7 465 /** \brief LDR Exclusive (8 bit)
emilmont 10:3bc89ef62ce7 466
emilmont 10:3bc89ef62ce7 467 This function performs a exclusive LDR command for 8 bit value.
emilmont 10:3bc89ef62ce7 468
emilmont 10:3bc89ef62ce7 469 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 470 \return value of type uint8_t at (*ptr)
emilmont 10:3bc89ef62ce7 471 */
emilmont 10:3bc89ef62ce7 472 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 10:3bc89ef62ce7 473 {
emilmont 10:3bc89ef62ce7 474 uint8_t result;
emilmont 10:3bc89ef62ce7 475
emilmont 10:3bc89ef62ce7 476 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 10:3bc89ef62ce7 477 return(result);
emilmont 10:3bc89ef62ce7 478 }
emilmont 10:3bc89ef62ce7 479
emilmont 10:3bc89ef62ce7 480
emilmont 10:3bc89ef62ce7 481 /** \brief LDR Exclusive (16 bit)
emilmont 10:3bc89ef62ce7 482
emilmont 10:3bc89ef62ce7 483 This function performs a exclusive LDR command for 16 bit values.
emilmont 10:3bc89ef62ce7 484
emilmont 10:3bc89ef62ce7 485 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 486 \return value of type uint16_t at (*ptr)
emilmont 10:3bc89ef62ce7 487 */
emilmont 10:3bc89ef62ce7 488 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 10:3bc89ef62ce7 489 {
emilmont 10:3bc89ef62ce7 490 uint16_t result;
emilmont 10:3bc89ef62ce7 491
emilmont 10:3bc89ef62ce7 492 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 10:3bc89ef62ce7 493 return(result);
emilmont 10:3bc89ef62ce7 494 }
emilmont 10:3bc89ef62ce7 495
emilmont 10:3bc89ef62ce7 496
emilmont 10:3bc89ef62ce7 497 /** \brief LDR Exclusive (32 bit)
emilmont 10:3bc89ef62ce7 498
emilmont 10:3bc89ef62ce7 499 This function performs a exclusive LDR command for 32 bit values.
emilmont 10:3bc89ef62ce7 500
emilmont 10:3bc89ef62ce7 501 \param [in] ptr Pointer to data
emilmont 10:3bc89ef62ce7 502 \return value of type uint32_t at (*ptr)
emilmont 10:3bc89ef62ce7 503 */
emilmont 10:3bc89ef62ce7 504 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 10:3bc89ef62ce7 505 {
emilmont 10:3bc89ef62ce7 506 uint32_t result;
emilmont 10:3bc89ef62ce7 507
emilmont 10:3bc89ef62ce7 508 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 10:3bc89ef62ce7 509 return(result);
emilmont 10:3bc89ef62ce7 510 }
emilmont 10:3bc89ef62ce7 511
emilmont 10:3bc89ef62ce7 512
emilmont 10:3bc89ef62ce7 513 /** \brief STR Exclusive (8 bit)
emilmont 10:3bc89ef62ce7 514
emilmont 10:3bc89ef62ce7 515 This function performs a exclusive STR command for 8 bit values.
emilmont 10:3bc89ef62ce7 516
emilmont 10:3bc89ef62ce7 517 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 518 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 519 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 520 \return 1 Function failed
emilmont 10:3bc89ef62ce7 521 */
emilmont 10:3bc89ef62ce7 522 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 10:3bc89ef62ce7 523 {
emilmont 10:3bc89ef62ce7 524 uint32_t result;
emilmont 10:3bc89ef62ce7 525
emilmont 10:3bc89ef62ce7 526 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 10:3bc89ef62ce7 527 return(result);
emilmont 10:3bc89ef62ce7 528 }
emilmont 10:3bc89ef62ce7 529
emilmont 10:3bc89ef62ce7 530
emilmont 10:3bc89ef62ce7 531 /** \brief STR Exclusive (16 bit)
emilmont 10:3bc89ef62ce7 532
emilmont 10:3bc89ef62ce7 533 This function performs a exclusive STR command for 16 bit values.
emilmont 10:3bc89ef62ce7 534
emilmont 10:3bc89ef62ce7 535 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 536 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 537 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 538 \return 1 Function failed
emilmont 10:3bc89ef62ce7 539 */
emilmont 10:3bc89ef62ce7 540 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 10:3bc89ef62ce7 541 {
emilmont 10:3bc89ef62ce7 542 uint32_t result;
emilmont 10:3bc89ef62ce7 543
emilmont 10:3bc89ef62ce7 544 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 10:3bc89ef62ce7 545 return(result);
emilmont 10:3bc89ef62ce7 546 }
emilmont 10:3bc89ef62ce7 547
emilmont 10:3bc89ef62ce7 548
emilmont 10:3bc89ef62ce7 549 /** \brief STR Exclusive (32 bit)
emilmont 10:3bc89ef62ce7 550
emilmont 10:3bc89ef62ce7 551 This function performs a exclusive STR command for 32 bit values.
emilmont 10:3bc89ef62ce7 552
emilmont 10:3bc89ef62ce7 553 \param [in] value Value to store
emilmont 10:3bc89ef62ce7 554 \param [in] ptr Pointer to location
emilmont 10:3bc89ef62ce7 555 \return 0 Function succeeded
emilmont 10:3bc89ef62ce7 556 \return 1 Function failed
emilmont 10:3bc89ef62ce7 557 */
emilmont 10:3bc89ef62ce7 558 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 10:3bc89ef62ce7 559 {
emilmont 10:3bc89ef62ce7 560 uint32_t result;
emilmont 10:3bc89ef62ce7 561
emilmont 10:3bc89ef62ce7 562 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 10:3bc89ef62ce7 563 return(result);
emilmont 10:3bc89ef62ce7 564 }
emilmont 10:3bc89ef62ce7 565
emilmont 10:3bc89ef62ce7 566
emilmont 10:3bc89ef62ce7 567 /** \brief Remove the exclusive lock
emilmont 10:3bc89ef62ce7 568
emilmont 10:3bc89ef62ce7 569 This function removes the exclusive lock which is created by LDREX.
emilmont 10:3bc89ef62ce7 570
emilmont 10:3bc89ef62ce7 571 */
emilmont 10:3bc89ef62ce7 572 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 10:3bc89ef62ce7 573 {
emilmont 10:3bc89ef62ce7 574 __ASM volatile ("clrex");
emilmont 10:3bc89ef62ce7 575 }
emilmont 10:3bc89ef62ce7 576
emilmont 10:3bc89ef62ce7 577
emilmont 10:3bc89ef62ce7 578 /** \brief Signed Saturate
emilmont 10:3bc89ef62ce7 579
emilmont 10:3bc89ef62ce7 580 This function saturates a signed value.
emilmont 10:3bc89ef62ce7 581
emilmont 10:3bc89ef62ce7 582 \param [in] value Value to be saturated
emilmont 10:3bc89ef62ce7 583 \param [in] sat Bit position to saturate to (1..32)
emilmont 10:3bc89ef62ce7 584 \return Saturated value
emilmont 10:3bc89ef62ce7 585 */
emilmont 10:3bc89ef62ce7 586 #define __SSAT(ARG1,ARG2) \
emilmont 10:3bc89ef62ce7 587 ({ \
emilmont 10:3bc89ef62ce7 588 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 10:3bc89ef62ce7 589 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 10:3bc89ef62ce7 590 __RES; \
emilmont 10:3bc89ef62ce7 591 })
emilmont 10:3bc89ef62ce7 592
emilmont 10:3bc89ef62ce7 593
emilmont 10:3bc89ef62ce7 594 /** \brief Unsigned Saturate
emilmont 10:3bc89ef62ce7 595
emilmont 10:3bc89ef62ce7 596 This function saturates an unsigned value.
emilmont 10:3bc89ef62ce7 597
emilmont 10:3bc89ef62ce7 598 \param [in] value Value to be saturated
emilmont 10:3bc89ef62ce7 599 \param [in] sat Bit position to saturate to (0..31)
emilmont 10:3bc89ef62ce7 600 \return Saturated value
emilmont 10:3bc89ef62ce7 601 */
emilmont 10:3bc89ef62ce7 602 #define __USAT(ARG1,ARG2) \
emilmont 10:3bc89ef62ce7 603 ({ \
emilmont 10:3bc89ef62ce7 604 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 10:3bc89ef62ce7 605 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 10:3bc89ef62ce7 606 __RES; \
emilmont 10:3bc89ef62ce7 607 })
emilmont 10:3bc89ef62ce7 608
emilmont 10:3bc89ef62ce7 609
emilmont 10:3bc89ef62ce7 610 /** \brief Count leading zeros
emilmont 10:3bc89ef62ce7 611
emilmont 10:3bc89ef62ce7 612 This function counts the number of leading zeros of a data value.
emilmont 10:3bc89ef62ce7 613
emilmont 10:3bc89ef62ce7 614 \param [in] value Value to count the leading zeros
emilmont 10:3bc89ef62ce7 615 \return number of leading zeros in value
emilmont 10:3bc89ef62ce7 616 */
emilmont 10:3bc89ef62ce7 617 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 10:3bc89ef62ce7 618 {
emilmont 10:3bc89ef62ce7 619 uint8_t result;
emilmont 10:3bc89ef62ce7 620
emilmont 10:3bc89ef62ce7 621 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 10:3bc89ef62ce7 622 return(result);
emilmont 10:3bc89ef62ce7 623 }
emilmont 10:3bc89ef62ce7 624
emilmont 10:3bc89ef62ce7 625 #endif /* (__CORTEX_M >= 0x03) */
emilmont 10:3bc89ef62ce7 626
emilmont 10:3bc89ef62ce7 627
emilmont 10:3bc89ef62ce7 628
emilmont 10:3bc89ef62ce7 629
emilmont 10:3bc89ef62ce7 630 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 10:3bc89ef62ce7 631 /* TASKING carm specific functions */
emilmont 10:3bc89ef62ce7 632
emilmont 10:3bc89ef62ce7 633 /*
emilmont 10:3bc89ef62ce7 634 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 10:3bc89ef62ce7 635 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 10:3bc89ef62ce7 636 * Including the CMSIS ones.
emilmont 10:3bc89ef62ce7 637 */
emilmont 10:3bc89ef62ce7 638
emilmont 10:3bc89ef62ce7 639 #endif
emilmont 10:3bc89ef62ce7 640
emilmont 10:3bc89ef62ce7 641 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 10:3bc89ef62ce7 642
emilmont 10:3bc89ef62ce7 643 #endif /* __CORE_CMINSTR_H */