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Last commit 20 Feb 2019 by 
mbed official
vendor/NXP/LPC2368/cmsis/vector_defns.h@10:3bc89ef62ce7, 2013-06-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Jun 14 17:49:17 2013 +0100
- Revision:
- 10:3bc89ef62ce7
Unify mbed library sources
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 10:3bc89ef62ce7 | 1 | /* mbed Microcontroller Library - Vectors |
| emilmont | 10:3bc89ef62ce7 | 2 | * Copyright (c) 2006-2009 ARM Limited. All rights reserved. |
| emilmont | 10:3bc89ef62ce7 | 3 | */ |
| emilmont | 10:3bc89ef62ce7 | 4 | |
| emilmont | 10:3bc89ef62ce7 | 5 | #ifndef MBED_VECTOR_DEFNS_H |
| emilmont | 10:3bc89ef62ce7 | 6 | #define MBED_VECTOR_DEFNS_H |
| emilmont | 10:3bc89ef62ce7 | 7 | |
| emilmont | 10:3bc89ef62ce7 | 8 | // Assember Macros |
| emilmont | 10:3bc89ef62ce7 | 9 | #ifdef __ARMCC_VERSION |
| emilmont | 10:3bc89ef62ce7 | 10 | #define EXPORT(x) EXPORT x |
| emilmont | 10:3bc89ef62ce7 | 11 | #define WEAK_EXPORT(x) EXPORT x [WEAK] |
| emilmont | 10:3bc89ef62ce7 | 12 | #define IMPORT(x) IMPORT x |
| emilmont | 10:3bc89ef62ce7 | 13 | #define LABEL(x) x |
| emilmont | 10:3bc89ef62ce7 | 14 | #else |
| emilmont | 10:3bc89ef62ce7 | 15 | #define EXPORT(x) .global x |
| emilmont | 10:3bc89ef62ce7 | 16 | #define WEAK_EXPORT(x) .weak x |
| emilmont | 10:3bc89ef62ce7 | 17 | #define IMPORT(x) .global x |
| emilmont | 10:3bc89ef62ce7 | 18 | #define LABEL(x) x: |
| emilmont | 10:3bc89ef62ce7 | 19 | #endif |
| emilmont | 10:3bc89ef62ce7 | 20 | |
| emilmont | 10:3bc89ef62ce7 | 21 | // RealMonitor |
| emilmont | 10:3bc89ef62ce7 | 22 | // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker |
| emilmont | 10:3bc89ef62ce7 | 23 | |
| emilmont | 10:3bc89ef62ce7 | 24 | // RealMonitor entry points |
| emilmont | 10:3bc89ef62ce7 | 25 | #define rm_init_entry 0x7fffff91 |
| emilmont | 10:3bc89ef62ce7 | 26 | #define rm_undef_handler 0x7fffffa0 |
| emilmont | 10:3bc89ef62ce7 | 27 | #define rm_prefetchabort_handler 0x7fffffb0 |
| emilmont | 10:3bc89ef62ce7 | 28 | #define rm_dataabort_handler 0x7fffffc0 |
| emilmont | 10:3bc89ef62ce7 | 29 | #define rm_irqhandler2 0x7fffffe0 |
| emilmont | 10:3bc89ef62ce7 | 30 | //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64 |
| emilmont | 10:3bc89ef62ce7 | 31 | #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40 |
| emilmont | 10:3bc89ef62ce7 | 32 | |
| emilmont | 10:3bc89ef62ce7 | 33 | // Unofficial RealMonitor entry points and variables |
| emilmont | 10:3bc89ef62ce7 | 34 | #define RM_MSG_SWI 0x00940000 |
| emilmont | 10:3bc89ef62ce7 | 35 | #define StateP 0x40000040 |
| emilmont | 10:3bc89ef62ce7 | 36 | |
| emilmont | 10:3bc89ef62ce7 | 37 | // VIC register addresses |
| emilmont | 10:3bc89ef62ce7 | 38 | #define VIC_Base 0xfffff000 |
| emilmont | 10:3bc89ef62ce7 | 39 | #define VICAddress_Offset 0xf00 |
| emilmont | 10:3bc89ef62ce7 | 40 | #define VICVectAddr2_Offset 0x108 |
| emilmont | 10:3bc89ef62ce7 | 41 | #define VICVectAddr3_Offset 0x10c |
| emilmont | 10:3bc89ef62ce7 | 42 | #define VICIntEnClr_Offset 0x014 |
| emilmont | 10:3bc89ef62ce7 | 43 | #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014)) |
| emilmont | 10:3bc89ef62ce7 | 44 | #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108)) |
| emilmont | 10:3bc89ef62ce7 | 45 | #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C)) |
| emilmont | 10:3bc89ef62ce7 | 46 | |
| emilmont | 10:3bc89ef62ce7 | 47 | // ARM Mode bits and Interrupt flags in PSRs |
| emilmont | 10:3bc89ef62ce7 | 48 | #define Mode_USR 0x10 |
| emilmont | 10:3bc89ef62ce7 | 49 | #define Mode_FIQ 0x11 |
| emilmont | 10:3bc89ef62ce7 | 50 | #define Mode_IRQ 0x12 |
| emilmont | 10:3bc89ef62ce7 | 51 | #define Mode_SVC 0x13 |
| emilmont | 10:3bc89ef62ce7 | 52 | #define Mode_ABT 0x17 |
| emilmont | 10:3bc89ef62ce7 | 53 | #define Mode_UND 0x1B |
| emilmont | 10:3bc89ef62ce7 | 54 | #define Mode_SYS 0x1F |
| emilmont | 10:3bc89ef62ce7 | 55 | #define I_Bit 0x80 // when I bit is set, IRQ is disabled |
| emilmont | 10:3bc89ef62ce7 | 56 | #define F_Bit 0x40 // when F bit is set, FIQ is disabled |
| emilmont | 10:3bc89ef62ce7 | 57 | |
| emilmont | 10:3bc89ef62ce7 | 58 | // MCU RAM |
| emilmont | 10:3bc89ef62ce7 | 59 | #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base |
| emilmont | 10:3bc89ef62ce7 | 60 | #define LPC2368_RAM_SIZE 0x8000 // 32KB |
| emilmont | 10:3bc89ef62ce7 | 61 | |
| emilmont | 10:3bc89ef62ce7 | 62 | // ISR Stack Allocation |
| emilmont | 10:3bc89ef62ce7 | 63 | #define UND_stack_size 0x00000040 |
| emilmont | 10:3bc89ef62ce7 | 64 | #define SVC_stack_size 0x00000040 |
| emilmont | 10:3bc89ef62ce7 | 65 | #define ABT_stack_size 0x00000040 |
| emilmont | 10:3bc89ef62ce7 | 66 | #define FIQ_stack_size 0x00000000 |
| emilmont | 10:3bc89ef62ce7 | 67 | #define IRQ_stack_size 0x00000040 |
| emilmont | 10:3bc89ef62ce7 | 68 | |
| emilmont | 10:3bc89ef62ce7 | 69 | #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size) |
| emilmont | 10:3bc89ef62ce7 | 70 | |
| emilmont | 10:3bc89ef62ce7 | 71 | // Full Descending Stack, so top-most stack points to just above the top of RAM |
| emilmont | 10:3bc89ef62ce7 | 72 | #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE) |
| emilmont | 10:3bc89ef62ce7 | 73 | #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size) |
| emilmont | 10:3bc89ef62ce7 | 74 | |
| emilmont | 10:3bc89ef62ce7 | 75 | #endif |
