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Last commit 20 Feb 2019 by 
mbed official
vendor/NXP/LPC11U24/cmsis/core_cm0.h@10:3bc89ef62ce7, 2013-06-14 (annotated)
- Committer:
- emilmont
- Date:
- Fri Jun 14 17:49:17 2013 +0100
- Revision:
- 10:3bc89ef62ce7
Unify mbed library sources
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 10:3bc89ef62ce7 | 1 | /**************************************************************************//** |
| emilmont | 10:3bc89ef62ce7 | 2 | * @file core_cm0.h |
| emilmont | 10:3bc89ef62ce7 | 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
| emilmont | 10:3bc89ef62ce7 | 4 | * @version V3.02 |
| emilmont | 10:3bc89ef62ce7 | 5 | * @date 05. November 2012 |
| emilmont | 10:3bc89ef62ce7 | 6 | * |
| emilmont | 10:3bc89ef62ce7 | 7 | * @note |
| emilmont | 10:3bc89ef62ce7 | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
| emilmont | 10:3bc89ef62ce7 | 9 | * |
| emilmont | 10:3bc89ef62ce7 | 10 | * @par |
| emilmont | 10:3bc89ef62ce7 | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| emilmont | 10:3bc89ef62ce7 | 12 | * processor based microcontrollers. This file can be freely distributed |
| emilmont | 10:3bc89ef62ce7 | 13 | * within development tools that are supporting such ARM based processors. |
| emilmont | 10:3bc89ef62ce7 | 14 | * |
| emilmont | 10:3bc89ef62ce7 | 15 | * @par |
| emilmont | 10:3bc89ef62ce7 | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| emilmont | 10:3bc89ef62ce7 | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| emilmont | 10:3bc89ef62ce7 | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| emilmont | 10:3bc89ef62ce7 | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| emilmont | 10:3bc89ef62ce7 | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| emilmont | 10:3bc89ef62ce7 | 21 | * |
| emilmont | 10:3bc89ef62ce7 | 22 | ******************************************************************************/ |
| emilmont | 10:3bc89ef62ce7 | 23 | #if defined ( __ICCARM__ ) |
| emilmont | 10:3bc89ef62ce7 | 24 | #pragma system_include /* treat file as system include file for MISRA check */ |
| emilmont | 10:3bc89ef62ce7 | 25 | #endif |
| emilmont | 10:3bc89ef62ce7 | 26 | |
| emilmont | 10:3bc89ef62ce7 | 27 | #ifdef __cplusplus |
| emilmont | 10:3bc89ef62ce7 | 28 | extern "C" { |
| emilmont | 10:3bc89ef62ce7 | 29 | #endif |
| emilmont | 10:3bc89ef62ce7 | 30 | |
| emilmont | 10:3bc89ef62ce7 | 31 | #ifndef __CORE_CM0_H_GENERIC |
| emilmont | 10:3bc89ef62ce7 | 32 | #define __CORE_CM0_H_GENERIC |
| emilmont | 10:3bc89ef62ce7 | 33 | |
| emilmont | 10:3bc89ef62ce7 | 34 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| emilmont | 10:3bc89ef62ce7 | 35 | CMSIS violates the following MISRA-C:2004 rules: |
| emilmont | 10:3bc89ef62ce7 | 36 | |
| emilmont | 10:3bc89ef62ce7 | 37 | \li Required Rule 8.5, object/function definition in header file.<br> |
| emilmont | 10:3bc89ef62ce7 | 38 | Function definitions in header files are used to allow 'inlining'. |
| emilmont | 10:3bc89ef62ce7 | 39 | |
| emilmont | 10:3bc89ef62ce7 | 40 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| emilmont | 10:3bc89ef62ce7 | 41 | Unions are used for effective representation of core registers. |
| emilmont | 10:3bc89ef62ce7 | 42 | |
| emilmont | 10:3bc89ef62ce7 | 43 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| emilmont | 10:3bc89ef62ce7 | 44 | Function-like macros are used to allow more efficient code. |
| emilmont | 10:3bc89ef62ce7 | 45 | */ |
| emilmont | 10:3bc89ef62ce7 | 46 | |
| emilmont | 10:3bc89ef62ce7 | 47 | |
| emilmont | 10:3bc89ef62ce7 | 48 | /******************************************************************************* |
| emilmont | 10:3bc89ef62ce7 | 49 | * CMSIS definitions |
| emilmont | 10:3bc89ef62ce7 | 50 | ******************************************************************************/ |
| emilmont | 10:3bc89ef62ce7 | 51 | /** \ingroup Cortex_M0 |
| emilmont | 10:3bc89ef62ce7 | 52 | @{ |
| emilmont | 10:3bc89ef62ce7 | 53 | */ |
| emilmont | 10:3bc89ef62ce7 | 54 | |
| emilmont | 10:3bc89ef62ce7 | 55 | /* CMSIS CM0 definitions */ |
| emilmont | 10:3bc89ef62ce7 | 56 | #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
| emilmont | 10:3bc89ef62ce7 | 57 | #define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ |
| emilmont | 10:3bc89ef62ce7 | 58 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ |
| emilmont | 10:3bc89ef62ce7 | 59 | __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| emilmont | 10:3bc89ef62ce7 | 60 | |
| emilmont | 10:3bc89ef62ce7 | 61 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */ |
| emilmont | 10:3bc89ef62ce7 | 62 | |
| emilmont | 10:3bc89ef62ce7 | 63 | |
| emilmont | 10:3bc89ef62ce7 | 64 | #if defined ( __CC_ARM ) |
| emilmont | 10:3bc89ef62ce7 | 65 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 66 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 67 | #define __STATIC_INLINE static __inline |
| emilmont | 10:3bc89ef62ce7 | 68 | |
| emilmont | 10:3bc89ef62ce7 | 69 | #elif defined ( __ICCARM__ ) |
| emilmont | 10:3bc89ef62ce7 | 70 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 71 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
| emilmont | 10:3bc89ef62ce7 | 72 | #define __STATIC_INLINE static inline |
| emilmont | 10:3bc89ef62ce7 | 73 | |
| emilmont | 10:3bc89ef62ce7 | 74 | #elif defined ( __GNUC__ ) |
| emilmont | 10:3bc89ef62ce7 | 75 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 76 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 77 | #define __STATIC_INLINE static inline |
| emilmont | 10:3bc89ef62ce7 | 78 | |
| emilmont | 10:3bc89ef62ce7 | 79 | #elif defined ( __TASKING__ ) |
| emilmont | 10:3bc89ef62ce7 | 80 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 81 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
| emilmont | 10:3bc89ef62ce7 | 82 | #define __STATIC_INLINE static inline |
| emilmont | 10:3bc89ef62ce7 | 83 | |
| emilmont | 10:3bc89ef62ce7 | 84 | #endif |
| emilmont | 10:3bc89ef62ce7 | 85 | |
| emilmont | 10:3bc89ef62ce7 | 86 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
| emilmont | 10:3bc89ef62ce7 | 87 | */ |
| emilmont | 10:3bc89ef62ce7 | 88 | #define __FPU_USED 0 |
| emilmont | 10:3bc89ef62ce7 | 89 | |
| emilmont | 10:3bc89ef62ce7 | 90 | #if defined ( __CC_ARM ) |
| emilmont | 10:3bc89ef62ce7 | 91 | #if defined __TARGET_FPU_VFP |
| emilmont | 10:3bc89ef62ce7 | 92 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 10:3bc89ef62ce7 | 93 | #endif |
| emilmont | 10:3bc89ef62ce7 | 94 | |
| emilmont | 10:3bc89ef62ce7 | 95 | #elif defined ( __ICCARM__ ) |
| emilmont | 10:3bc89ef62ce7 | 96 | #if defined __ARMVFP__ |
| emilmont | 10:3bc89ef62ce7 | 97 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 10:3bc89ef62ce7 | 98 | #endif |
| emilmont | 10:3bc89ef62ce7 | 99 | |
| emilmont | 10:3bc89ef62ce7 | 100 | #elif defined ( __GNUC__ ) |
| emilmont | 10:3bc89ef62ce7 | 101 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| emilmont | 10:3bc89ef62ce7 | 102 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 10:3bc89ef62ce7 | 103 | #endif |
| emilmont | 10:3bc89ef62ce7 | 104 | |
| emilmont | 10:3bc89ef62ce7 | 105 | #elif defined ( __TASKING__ ) |
| emilmont | 10:3bc89ef62ce7 | 106 | #if defined __FPU_VFP__ |
| emilmont | 10:3bc89ef62ce7 | 107 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 10:3bc89ef62ce7 | 108 | #endif |
| emilmont | 10:3bc89ef62ce7 | 109 | #endif |
| emilmont | 10:3bc89ef62ce7 | 110 | |
| emilmont | 10:3bc89ef62ce7 | 111 | #include <stdint.h> /* standard types definitions */ |
| emilmont | 10:3bc89ef62ce7 | 112 | #include <core_cmInstr.h> /* Core Instruction Access */ |
| emilmont | 10:3bc89ef62ce7 | 113 | #include <core_cmFunc.h> /* Core Function Access */ |
| emilmont | 10:3bc89ef62ce7 | 114 | |
| emilmont | 10:3bc89ef62ce7 | 115 | #endif /* __CORE_CM0_H_GENERIC */ |
| emilmont | 10:3bc89ef62ce7 | 116 | |
| emilmont | 10:3bc89ef62ce7 | 117 | #ifndef __CMSIS_GENERIC |
| emilmont | 10:3bc89ef62ce7 | 118 | |
| emilmont | 10:3bc89ef62ce7 | 119 | #ifndef __CORE_CM0_H_DEPENDANT |
| emilmont | 10:3bc89ef62ce7 | 120 | #define __CORE_CM0_H_DEPENDANT |
| emilmont | 10:3bc89ef62ce7 | 121 | |
| emilmont | 10:3bc89ef62ce7 | 122 | /* check device defines and use defaults */ |
| emilmont | 10:3bc89ef62ce7 | 123 | #if defined __CHECK_DEVICE_DEFINES |
| emilmont | 10:3bc89ef62ce7 | 124 | #ifndef __CM0_REV |
| emilmont | 10:3bc89ef62ce7 | 125 | #define __CM0_REV 0x0000 |
| emilmont | 10:3bc89ef62ce7 | 126 | #warning "__CM0_REV not defined in device header file; using default!" |
| emilmont | 10:3bc89ef62ce7 | 127 | #endif |
| emilmont | 10:3bc89ef62ce7 | 128 | |
| emilmont | 10:3bc89ef62ce7 | 129 | #ifndef __NVIC_PRIO_BITS |
| emilmont | 10:3bc89ef62ce7 | 130 | #define __NVIC_PRIO_BITS 2 |
| emilmont | 10:3bc89ef62ce7 | 131 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| emilmont | 10:3bc89ef62ce7 | 132 | #endif |
| emilmont | 10:3bc89ef62ce7 | 133 | |
| emilmont | 10:3bc89ef62ce7 | 134 | #ifndef __Vendor_SysTickConfig |
| emilmont | 10:3bc89ef62ce7 | 135 | #define __Vendor_SysTickConfig 0 |
| emilmont | 10:3bc89ef62ce7 | 136 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| emilmont | 10:3bc89ef62ce7 | 137 | #endif |
| emilmont | 10:3bc89ef62ce7 | 138 | #endif |
| emilmont | 10:3bc89ef62ce7 | 139 | |
| emilmont | 10:3bc89ef62ce7 | 140 | /* IO definitions (access restrictions to peripheral registers) */ |
| emilmont | 10:3bc89ef62ce7 | 141 | /** |
| emilmont | 10:3bc89ef62ce7 | 142 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| emilmont | 10:3bc89ef62ce7 | 143 | |
| emilmont | 10:3bc89ef62ce7 | 144 | <strong>IO Type Qualifiers</strong> are used |
| emilmont | 10:3bc89ef62ce7 | 145 | \li to specify the access to peripheral variables. |
| emilmont | 10:3bc89ef62ce7 | 146 | \li for automatic generation of peripheral register debug information. |
| emilmont | 10:3bc89ef62ce7 | 147 | */ |
| emilmont | 10:3bc89ef62ce7 | 148 | #ifdef __cplusplus |
| emilmont | 10:3bc89ef62ce7 | 149 | #define __I volatile /*!< Defines 'read only' permissions */ |
| emilmont | 10:3bc89ef62ce7 | 150 | #else |
| emilmont | 10:3bc89ef62ce7 | 151 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| emilmont | 10:3bc89ef62ce7 | 152 | #endif |
| emilmont | 10:3bc89ef62ce7 | 153 | #define __O volatile /*!< Defines 'write only' permissions */ |
| emilmont | 10:3bc89ef62ce7 | 154 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| emilmont | 10:3bc89ef62ce7 | 155 | |
| emilmont | 10:3bc89ef62ce7 | 156 | /*@} end of group Cortex_M0 */ |
| emilmont | 10:3bc89ef62ce7 | 157 | |
| emilmont | 10:3bc89ef62ce7 | 158 | |
| emilmont | 10:3bc89ef62ce7 | 159 | |
| emilmont | 10:3bc89ef62ce7 | 160 | /******************************************************************************* |
| emilmont | 10:3bc89ef62ce7 | 161 | * Register Abstraction |
| emilmont | 10:3bc89ef62ce7 | 162 | Core Register contain: |
| emilmont | 10:3bc89ef62ce7 | 163 | - Core Register |
| emilmont | 10:3bc89ef62ce7 | 164 | - Core NVIC Register |
| emilmont | 10:3bc89ef62ce7 | 165 | - Core SCB Register |
| emilmont | 10:3bc89ef62ce7 | 166 | - Core SysTick Register |
| emilmont | 10:3bc89ef62ce7 | 167 | ******************************************************************************/ |
| emilmont | 10:3bc89ef62ce7 | 168 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
| emilmont | 10:3bc89ef62ce7 | 169 | \brief Type definitions and defines for Cortex-M processor based devices. |
| emilmont | 10:3bc89ef62ce7 | 170 | */ |
| emilmont | 10:3bc89ef62ce7 | 171 | |
| emilmont | 10:3bc89ef62ce7 | 172 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 173 | \defgroup CMSIS_CORE Status and Control Registers |
| emilmont | 10:3bc89ef62ce7 | 174 | \brief Core Register type definitions. |
| emilmont | 10:3bc89ef62ce7 | 175 | @{ |
| emilmont | 10:3bc89ef62ce7 | 176 | */ |
| emilmont | 10:3bc89ef62ce7 | 177 | |
| emilmont | 10:3bc89ef62ce7 | 178 | /** \brief Union type to access the Application Program Status Register (APSR). |
| emilmont | 10:3bc89ef62ce7 | 179 | */ |
| emilmont | 10:3bc89ef62ce7 | 180 | typedef union |
| emilmont | 10:3bc89ef62ce7 | 181 | { |
| emilmont | 10:3bc89ef62ce7 | 182 | struct |
| emilmont | 10:3bc89ef62ce7 | 183 | { |
| emilmont | 10:3bc89ef62ce7 | 184 | #if (__CORTEX_M != 0x04) |
| emilmont | 10:3bc89ef62ce7 | 185 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 186 | #else |
| emilmont | 10:3bc89ef62ce7 | 187 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 188 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 10:3bc89ef62ce7 | 189 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 190 | #endif |
| emilmont | 10:3bc89ef62ce7 | 191 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 10:3bc89ef62ce7 | 192 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 193 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 194 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 195 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 196 | } b; /*!< Structure used for bit access */ |
| emilmont | 10:3bc89ef62ce7 | 197 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 10:3bc89ef62ce7 | 198 | } APSR_Type; |
| emilmont | 10:3bc89ef62ce7 | 199 | |
| emilmont | 10:3bc89ef62ce7 | 200 | |
| emilmont | 10:3bc89ef62ce7 | 201 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
| emilmont | 10:3bc89ef62ce7 | 202 | */ |
| emilmont | 10:3bc89ef62ce7 | 203 | typedef union |
| emilmont | 10:3bc89ef62ce7 | 204 | { |
| emilmont | 10:3bc89ef62ce7 | 205 | struct |
| emilmont | 10:3bc89ef62ce7 | 206 | { |
| emilmont | 10:3bc89ef62ce7 | 207 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 10:3bc89ef62ce7 | 208 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 209 | } b; /*!< Structure used for bit access */ |
| emilmont | 10:3bc89ef62ce7 | 210 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 10:3bc89ef62ce7 | 211 | } IPSR_Type; |
| emilmont | 10:3bc89ef62ce7 | 212 | |
| emilmont | 10:3bc89ef62ce7 | 213 | |
| emilmont | 10:3bc89ef62ce7 | 214 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| emilmont | 10:3bc89ef62ce7 | 215 | */ |
| emilmont | 10:3bc89ef62ce7 | 216 | typedef union |
| emilmont | 10:3bc89ef62ce7 | 217 | { |
| emilmont | 10:3bc89ef62ce7 | 218 | struct |
| emilmont | 10:3bc89ef62ce7 | 219 | { |
| emilmont | 10:3bc89ef62ce7 | 220 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 10:3bc89ef62ce7 | 221 | #if (__CORTEX_M != 0x04) |
| emilmont | 10:3bc89ef62ce7 | 222 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 223 | #else |
| emilmont | 10:3bc89ef62ce7 | 224 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 225 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 10:3bc89ef62ce7 | 226 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 227 | #endif |
| emilmont | 10:3bc89ef62ce7 | 228 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| emilmont | 10:3bc89ef62ce7 | 229 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
| emilmont | 10:3bc89ef62ce7 | 230 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 10:3bc89ef62ce7 | 231 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 232 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 233 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 234 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 10:3bc89ef62ce7 | 235 | } b; /*!< Structure used for bit access */ |
| emilmont | 10:3bc89ef62ce7 | 236 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 10:3bc89ef62ce7 | 237 | } xPSR_Type; |
| emilmont | 10:3bc89ef62ce7 | 238 | |
| emilmont | 10:3bc89ef62ce7 | 239 | |
| emilmont | 10:3bc89ef62ce7 | 240 | /** \brief Union type to access the Control Registers (CONTROL). |
| emilmont | 10:3bc89ef62ce7 | 241 | */ |
| emilmont | 10:3bc89ef62ce7 | 242 | typedef union |
| emilmont | 10:3bc89ef62ce7 | 243 | { |
| emilmont | 10:3bc89ef62ce7 | 244 | struct |
| emilmont | 10:3bc89ef62ce7 | 245 | { |
| emilmont | 10:3bc89ef62ce7 | 246 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| emilmont | 10:3bc89ef62ce7 | 247 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| emilmont | 10:3bc89ef62ce7 | 248 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
| emilmont | 10:3bc89ef62ce7 | 249 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
| emilmont | 10:3bc89ef62ce7 | 250 | } b; /*!< Structure used for bit access */ |
| emilmont | 10:3bc89ef62ce7 | 251 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 10:3bc89ef62ce7 | 252 | } CONTROL_Type; |
| emilmont | 10:3bc89ef62ce7 | 253 | |
| emilmont | 10:3bc89ef62ce7 | 254 | /*@} end of group CMSIS_CORE */ |
| emilmont | 10:3bc89ef62ce7 | 255 | |
| emilmont | 10:3bc89ef62ce7 | 256 | |
| emilmont | 10:3bc89ef62ce7 | 257 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 258 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| emilmont | 10:3bc89ef62ce7 | 259 | \brief Type definitions for the NVIC Registers |
| emilmont | 10:3bc89ef62ce7 | 260 | @{ |
| emilmont | 10:3bc89ef62ce7 | 261 | */ |
| emilmont | 10:3bc89ef62ce7 | 262 | |
| emilmont | 10:3bc89ef62ce7 | 263 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| emilmont | 10:3bc89ef62ce7 | 264 | */ |
| emilmont | 10:3bc89ef62ce7 | 265 | typedef struct |
| emilmont | 10:3bc89ef62ce7 | 266 | { |
| emilmont | 10:3bc89ef62ce7 | 267 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| emilmont | 10:3bc89ef62ce7 | 268 | uint32_t RESERVED0[31]; |
| emilmont | 10:3bc89ef62ce7 | 269 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| emilmont | 10:3bc89ef62ce7 | 270 | uint32_t RSERVED1[31]; |
| emilmont | 10:3bc89ef62ce7 | 271 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| emilmont | 10:3bc89ef62ce7 | 272 | uint32_t RESERVED2[31]; |
| emilmont | 10:3bc89ef62ce7 | 273 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| emilmont | 10:3bc89ef62ce7 | 274 | uint32_t RESERVED3[31]; |
| emilmont | 10:3bc89ef62ce7 | 275 | uint32_t RESERVED4[64]; |
| emilmont | 10:3bc89ef62ce7 | 276 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| emilmont | 10:3bc89ef62ce7 | 277 | } NVIC_Type; |
| emilmont | 10:3bc89ef62ce7 | 278 | |
| emilmont | 10:3bc89ef62ce7 | 279 | /*@} end of group CMSIS_NVIC */ |
| emilmont | 10:3bc89ef62ce7 | 280 | |
| emilmont | 10:3bc89ef62ce7 | 281 | |
| emilmont | 10:3bc89ef62ce7 | 282 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 283 | \defgroup CMSIS_SCB System Control Block (SCB) |
| emilmont | 10:3bc89ef62ce7 | 284 | \brief Type definitions for the System Control Block Registers |
| emilmont | 10:3bc89ef62ce7 | 285 | @{ |
| emilmont | 10:3bc89ef62ce7 | 286 | */ |
| emilmont | 10:3bc89ef62ce7 | 287 | |
| emilmont | 10:3bc89ef62ce7 | 288 | /** \brief Structure type to access the System Control Block (SCB). |
| emilmont | 10:3bc89ef62ce7 | 289 | */ |
| emilmont | 10:3bc89ef62ce7 | 290 | typedef struct |
| emilmont | 10:3bc89ef62ce7 | 291 | { |
| emilmont | 10:3bc89ef62ce7 | 292 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| emilmont | 10:3bc89ef62ce7 | 293 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| emilmont | 10:3bc89ef62ce7 | 294 | uint32_t RESERVED0; |
| emilmont | 10:3bc89ef62ce7 | 295 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| emilmont | 10:3bc89ef62ce7 | 296 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| emilmont | 10:3bc89ef62ce7 | 297 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| emilmont | 10:3bc89ef62ce7 | 298 | uint32_t RESERVED1; |
| emilmont | 10:3bc89ef62ce7 | 299 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| emilmont | 10:3bc89ef62ce7 | 300 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| emilmont | 10:3bc89ef62ce7 | 301 | } SCB_Type; |
| emilmont | 10:3bc89ef62ce7 | 302 | |
| emilmont | 10:3bc89ef62ce7 | 303 | /* SCB CPUID Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 304 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
| emilmont | 10:3bc89ef62ce7 | 305 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| emilmont | 10:3bc89ef62ce7 | 306 | |
| emilmont | 10:3bc89ef62ce7 | 307 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
| emilmont | 10:3bc89ef62ce7 | 308 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 309 | |
| emilmont | 10:3bc89ef62ce7 | 310 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
| emilmont | 10:3bc89ef62ce7 | 311 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| emilmont | 10:3bc89ef62ce7 | 312 | |
| emilmont | 10:3bc89ef62ce7 | 313 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
| emilmont | 10:3bc89ef62ce7 | 314 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| emilmont | 10:3bc89ef62ce7 | 315 | |
| emilmont | 10:3bc89ef62ce7 | 316 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
| emilmont | 10:3bc89ef62ce7 | 317 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
| emilmont | 10:3bc89ef62ce7 | 318 | |
| emilmont | 10:3bc89ef62ce7 | 319 | /* SCB Interrupt Control State Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 320 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
| emilmont | 10:3bc89ef62ce7 | 321 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| emilmont | 10:3bc89ef62ce7 | 322 | |
| emilmont | 10:3bc89ef62ce7 | 323 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
| emilmont | 10:3bc89ef62ce7 | 324 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| emilmont | 10:3bc89ef62ce7 | 325 | |
| emilmont | 10:3bc89ef62ce7 | 326 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
| emilmont | 10:3bc89ef62ce7 | 327 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| emilmont | 10:3bc89ef62ce7 | 328 | |
| emilmont | 10:3bc89ef62ce7 | 329 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
| emilmont | 10:3bc89ef62ce7 | 330 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| emilmont | 10:3bc89ef62ce7 | 331 | |
| emilmont | 10:3bc89ef62ce7 | 332 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
| emilmont | 10:3bc89ef62ce7 | 333 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| emilmont | 10:3bc89ef62ce7 | 334 | |
| emilmont | 10:3bc89ef62ce7 | 335 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
| emilmont | 10:3bc89ef62ce7 | 336 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 337 | |
| emilmont | 10:3bc89ef62ce7 | 338 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
| emilmont | 10:3bc89ef62ce7 | 339 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| emilmont | 10:3bc89ef62ce7 | 340 | |
| emilmont | 10:3bc89ef62ce7 | 341 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
| emilmont | 10:3bc89ef62ce7 | 342 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| emilmont | 10:3bc89ef62ce7 | 343 | |
| emilmont | 10:3bc89ef62ce7 | 344 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
| emilmont | 10:3bc89ef62ce7 | 345 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
| emilmont | 10:3bc89ef62ce7 | 346 | |
| emilmont | 10:3bc89ef62ce7 | 347 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 348 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
| emilmont | 10:3bc89ef62ce7 | 349 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| emilmont | 10:3bc89ef62ce7 | 350 | |
| emilmont | 10:3bc89ef62ce7 | 351 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| emilmont | 10:3bc89ef62ce7 | 352 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 353 | |
| emilmont | 10:3bc89ef62ce7 | 354 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
| emilmont | 10:3bc89ef62ce7 | 355 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| emilmont | 10:3bc89ef62ce7 | 356 | |
| emilmont | 10:3bc89ef62ce7 | 357 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
| emilmont | 10:3bc89ef62ce7 | 358 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| emilmont | 10:3bc89ef62ce7 | 359 | |
| emilmont | 10:3bc89ef62ce7 | 360 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| emilmont | 10:3bc89ef62ce7 | 361 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| emilmont | 10:3bc89ef62ce7 | 362 | |
| emilmont | 10:3bc89ef62ce7 | 363 | /* SCB System Control Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 364 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
| emilmont | 10:3bc89ef62ce7 | 365 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| emilmont | 10:3bc89ef62ce7 | 366 | |
| emilmont | 10:3bc89ef62ce7 | 367 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
| emilmont | 10:3bc89ef62ce7 | 368 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| emilmont | 10:3bc89ef62ce7 | 369 | |
| emilmont | 10:3bc89ef62ce7 | 370 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
| emilmont | 10:3bc89ef62ce7 | 371 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 372 | |
| emilmont | 10:3bc89ef62ce7 | 373 | /* SCB Configuration Control Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 374 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
| emilmont | 10:3bc89ef62ce7 | 375 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| emilmont | 10:3bc89ef62ce7 | 376 | |
| emilmont | 10:3bc89ef62ce7 | 377 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
| emilmont | 10:3bc89ef62ce7 | 378 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| emilmont | 10:3bc89ef62ce7 | 379 | |
| emilmont | 10:3bc89ef62ce7 | 380 | /* SCB System Handler Control and State Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 381 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
| emilmont | 10:3bc89ef62ce7 | 382 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| emilmont | 10:3bc89ef62ce7 | 383 | |
| emilmont | 10:3bc89ef62ce7 | 384 | /*@} end of group CMSIS_SCB */ |
| emilmont | 10:3bc89ef62ce7 | 385 | |
| emilmont | 10:3bc89ef62ce7 | 386 | |
| emilmont | 10:3bc89ef62ce7 | 387 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 388 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| emilmont | 10:3bc89ef62ce7 | 389 | \brief Type definitions for the System Timer Registers. |
| emilmont | 10:3bc89ef62ce7 | 390 | @{ |
| emilmont | 10:3bc89ef62ce7 | 391 | */ |
| emilmont | 10:3bc89ef62ce7 | 392 | |
| emilmont | 10:3bc89ef62ce7 | 393 | /** \brief Structure type to access the System Timer (SysTick). |
| emilmont | 10:3bc89ef62ce7 | 394 | */ |
| emilmont | 10:3bc89ef62ce7 | 395 | typedef struct |
| emilmont | 10:3bc89ef62ce7 | 396 | { |
| emilmont | 10:3bc89ef62ce7 | 397 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| emilmont | 10:3bc89ef62ce7 | 398 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| emilmont | 10:3bc89ef62ce7 | 399 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| emilmont | 10:3bc89ef62ce7 | 400 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| emilmont | 10:3bc89ef62ce7 | 401 | } SysTick_Type; |
| emilmont | 10:3bc89ef62ce7 | 402 | |
| emilmont | 10:3bc89ef62ce7 | 403 | /* SysTick Control / Status Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 404 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
| emilmont | 10:3bc89ef62ce7 | 405 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| emilmont | 10:3bc89ef62ce7 | 406 | |
| emilmont | 10:3bc89ef62ce7 | 407 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
| emilmont | 10:3bc89ef62ce7 | 408 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| emilmont | 10:3bc89ef62ce7 | 409 | |
| emilmont | 10:3bc89ef62ce7 | 410 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
| emilmont | 10:3bc89ef62ce7 | 411 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 412 | |
| emilmont | 10:3bc89ef62ce7 | 413 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
| emilmont | 10:3bc89ef62ce7 | 414 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
| emilmont | 10:3bc89ef62ce7 | 415 | |
| emilmont | 10:3bc89ef62ce7 | 416 | /* SysTick Reload Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 417 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
| emilmont | 10:3bc89ef62ce7 | 418 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
| emilmont | 10:3bc89ef62ce7 | 419 | |
| emilmont | 10:3bc89ef62ce7 | 420 | /* SysTick Current Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 421 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
| emilmont | 10:3bc89ef62ce7 | 422 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
| emilmont | 10:3bc89ef62ce7 | 423 | |
| emilmont | 10:3bc89ef62ce7 | 424 | /* SysTick Calibration Register Definitions */ |
| emilmont | 10:3bc89ef62ce7 | 425 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
| emilmont | 10:3bc89ef62ce7 | 426 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| emilmont | 10:3bc89ef62ce7 | 427 | |
| emilmont | 10:3bc89ef62ce7 | 428 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
| emilmont | 10:3bc89ef62ce7 | 429 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| emilmont | 10:3bc89ef62ce7 | 430 | |
| emilmont | 10:3bc89ef62ce7 | 431 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
| emilmont | 10:3bc89ef62ce7 | 432 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
| emilmont | 10:3bc89ef62ce7 | 433 | |
| emilmont | 10:3bc89ef62ce7 | 434 | /*@} end of group CMSIS_SysTick */ |
| emilmont | 10:3bc89ef62ce7 | 435 | |
| emilmont | 10:3bc89ef62ce7 | 436 | |
| emilmont | 10:3bc89ef62ce7 | 437 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 438 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| emilmont | 10:3bc89ef62ce7 | 439 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) |
| emilmont | 10:3bc89ef62ce7 | 440 | are only accessible over DAP and not via processor. Therefore |
| emilmont | 10:3bc89ef62ce7 | 441 | they are not covered by the Cortex-M0 header file. |
| emilmont | 10:3bc89ef62ce7 | 442 | @{ |
| emilmont | 10:3bc89ef62ce7 | 443 | */ |
| emilmont | 10:3bc89ef62ce7 | 444 | /*@} end of group CMSIS_CoreDebug */ |
| emilmont | 10:3bc89ef62ce7 | 445 | |
| emilmont | 10:3bc89ef62ce7 | 446 | |
| emilmont | 10:3bc89ef62ce7 | 447 | /** \ingroup CMSIS_core_register |
| emilmont | 10:3bc89ef62ce7 | 448 | \defgroup CMSIS_core_base Core Definitions |
| emilmont | 10:3bc89ef62ce7 | 449 | \brief Definitions for base addresses, unions, and structures. |
| emilmont | 10:3bc89ef62ce7 | 450 | @{ |
| emilmont | 10:3bc89ef62ce7 | 451 | */ |
| emilmont | 10:3bc89ef62ce7 | 452 | |
| emilmont | 10:3bc89ef62ce7 | 453 | /* Memory mapping of Cortex-M0 Hardware */ |
| emilmont | 10:3bc89ef62ce7 | 454 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| emilmont | 10:3bc89ef62ce7 | 455 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| emilmont | 10:3bc89ef62ce7 | 456 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| emilmont | 10:3bc89ef62ce7 | 457 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| emilmont | 10:3bc89ef62ce7 | 458 | |
| emilmont | 10:3bc89ef62ce7 | 459 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| emilmont | 10:3bc89ef62ce7 | 460 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| emilmont | 10:3bc89ef62ce7 | 461 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| emilmont | 10:3bc89ef62ce7 | 462 | |
| emilmont | 10:3bc89ef62ce7 | 463 | |
| emilmont | 10:3bc89ef62ce7 | 464 | /*@} */ |
| emilmont | 10:3bc89ef62ce7 | 465 | |
| emilmont | 10:3bc89ef62ce7 | 466 | |
| emilmont | 10:3bc89ef62ce7 | 467 | |
| emilmont | 10:3bc89ef62ce7 | 468 | /******************************************************************************* |
| emilmont | 10:3bc89ef62ce7 | 469 | * Hardware Abstraction Layer |
| emilmont | 10:3bc89ef62ce7 | 470 | Core Function Interface contains: |
| emilmont | 10:3bc89ef62ce7 | 471 | - Core NVIC Functions |
| emilmont | 10:3bc89ef62ce7 | 472 | - Core SysTick Functions |
| emilmont | 10:3bc89ef62ce7 | 473 | - Core Register Access Functions |
| emilmont | 10:3bc89ef62ce7 | 474 | ******************************************************************************/ |
| emilmont | 10:3bc89ef62ce7 | 475 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| emilmont | 10:3bc89ef62ce7 | 476 | */ |
| emilmont | 10:3bc89ef62ce7 | 477 | |
| emilmont | 10:3bc89ef62ce7 | 478 | |
| emilmont | 10:3bc89ef62ce7 | 479 | |
| emilmont | 10:3bc89ef62ce7 | 480 | /* ########################## NVIC functions #################################### */ |
| emilmont | 10:3bc89ef62ce7 | 481 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 10:3bc89ef62ce7 | 482 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| emilmont | 10:3bc89ef62ce7 | 483 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| emilmont | 10:3bc89ef62ce7 | 484 | @{ |
| emilmont | 10:3bc89ef62ce7 | 485 | */ |
| emilmont | 10:3bc89ef62ce7 | 486 | |
| emilmont | 10:3bc89ef62ce7 | 487 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| emilmont | 10:3bc89ef62ce7 | 488 | /* The following MACROS handle generation of the register offset and byte masks */ |
| emilmont | 10:3bc89ef62ce7 | 489 | #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) |
| emilmont | 10:3bc89ef62ce7 | 490 | #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) |
| emilmont | 10:3bc89ef62ce7 | 491 | #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) |
| emilmont | 10:3bc89ef62ce7 | 492 | |
| emilmont | 10:3bc89ef62ce7 | 493 | |
| emilmont | 10:3bc89ef62ce7 | 494 | /** \brief Enable External Interrupt |
| emilmont | 10:3bc89ef62ce7 | 495 | |
| emilmont | 10:3bc89ef62ce7 | 496 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 10:3bc89ef62ce7 | 497 | |
| emilmont | 10:3bc89ef62ce7 | 498 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 10:3bc89ef62ce7 | 499 | */ |
| emilmont | 10:3bc89ef62ce7 | 500 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 501 | { |
| emilmont | 10:3bc89ef62ce7 | 502 | NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 503 | } |
| emilmont | 10:3bc89ef62ce7 | 504 | |
| emilmont | 10:3bc89ef62ce7 | 505 | |
| emilmont | 10:3bc89ef62ce7 | 506 | /** \brief Disable External Interrupt |
| emilmont | 10:3bc89ef62ce7 | 507 | |
| emilmont | 10:3bc89ef62ce7 | 508 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 10:3bc89ef62ce7 | 509 | |
| emilmont | 10:3bc89ef62ce7 | 510 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 10:3bc89ef62ce7 | 511 | */ |
| emilmont | 10:3bc89ef62ce7 | 512 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 513 | { |
| emilmont | 10:3bc89ef62ce7 | 514 | NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 515 | } |
| emilmont | 10:3bc89ef62ce7 | 516 | |
| emilmont | 10:3bc89ef62ce7 | 517 | |
| emilmont | 10:3bc89ef62ce7 | 518 | /** \brief Get Pending Interrupt |
| emilmont | 10:3bc89ef62ce7 | 519 | |
| emilmont | 10:3bc89ef62ce7 | 520 | The function reads the pending register in the NVIC and returns the pending bit |
| emilmont | 10:3bc89ef62ce7 | 521 | for the specified interrupt. |
| emilmont | 10:3bc89ef62ce7 | 522 | |
| emilmont | 10:3bc89ef62ce7 | 523 | \param [in] IRQn Interrupt number. |
| emilmont | 10:3bc89ef62ce7 | 524 | |
| emilmont | 10:3bc89ef62ce7 | 525 | \return 0 Interrupt status is not pending. |
| emilmont | 10:3bc89ef62ce7 | 526 | \return 1 Interrupt status is pending. |
| emilmont | 10:3bc89ef62ce7 | 527 | */ |
| emilmont | 10:3bc89ef62ce7 | 528 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 529 | { |
| emilmont | 10:3bc89ef62ce7 | 530 | return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); |
| emilmont | 10:3bc89ef62ce7 | 531 | } |
| emilmont | 10:3bc89ef62ce7 | 532 | |
| emilmont | 10:3bc89ef62ce7 | 533 | |
| emilmont | 10:3bc89ef62ce7 | 534 | /** \brief Set Pending Interrupt |
| emilmont | 10:3bc89ef62ce7 | 535 | |
| emilmont | 10:3bc89ef62ce7 | 536 | The function sets the pending bit of an external interrupt. |
| emilmont | 10:3bc89ef62ce7 | 537 | |
| emilmont | 10:3bc89ef62ce7 | 538 | \param [in] IRQn Interrupt number. Value cannot be negative. |
| emilmont | 10:3bc89ef62ce7 | 539 | */ |
| emilmont | 10:3bc89ef62ce7 | 540 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 541 | { |
| emilmont | 10:3bc89ef62ce7 | 542 | NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 10:3bc89ef62ce7 | 543 | } |
| emilmont | 10:3bc89ef62ce7 | 544 | |
| emilmont | 10:3bc89ef62ce7 | 545 | |
| emilmont | 10:3bc89ef62ce7 | 546 | /** \brief Clear Pending Interrupt |
| emilmont | 10:3bc89ef62ce7 | 547 | |
| emilmont | 10:3bc89ef62ce7 | 548 | The function clears the pending bit of an external interrupt. |
| emilmont | 10:3bc89ef62ce7 | 549 | |
| emilmont | 10:3bc89ef62ce7 | 550 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 10:3bc89ef62ce7 | 551 | */ |
| emilmont | 10:3bc89ef62ce7 | 552 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 553 | { |
| emilmont | 10:3bc89ef62ce7 | 554 | NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
| emilmont | 10:3bc89ef62ce7 | 555 | } |
| emilmont | 10:3bc89ef62ce7 | 556 | |
| emilmont | 10:3bc89ef62ce7 | 557 | |
| emilmont | 10:3bc89ef62ce7 | 558 | /** \brief Set Interrupt Priority |
| emilmont | 10:3bc89ef62ce7 | 559 | |
| emilmont | 10:3bc89ef62ce7 | 560 | The function sets the priority of an interrupt. |
| emilmont | 10:3bc89ef62ce7 | 561 | |
| emilmont | 10:3bc89ef62ce7 | 562 | \note The priority cannot be set for every core interrupt. |
| emilmont | 10:3bc89ef62ce7 | 563 | |
| emilmont | 10:3bc89ef62ce7 | 564 | \param [in] IRQn Interrupt number. |
| emilmont | 10:3bc89ef62ce7 | 565 | \param [in] priority Priority to set. |
| emilmont | 10:3bc89ef62ce7 | 566 | */ |
| emilmont | 10:3bc89ef62ce7 | 567 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| emilmont | 10:3bc89ef62ce7 | 568 | { |
| emilmont | 10:3bc89ef62ce7 | 569 | if(IRQn < 0) { |
| emilmont | 10:3bc89ef62ce7 | 570 | SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 10:3bc89ef62ce7 | 571 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 10:3bc89ef62ce7 | 572 | else { |
| emilmont | 10:3bc89ef62ce7 | 573 | NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 10:3bc89ef62ce7 | 574 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 10:3bc89ef62ce7 | 575 | } |
| emilmont | 10:3bc89ef62ce7 | 576 | |
| emilmont | 10:3bc89ef62ce7 | 577 | |
| emilmont | 10:3bc89ef62ce7 | 578 | /** \brief Get Interrupt Priority |
| emilmont | 10:3bc89ef62ce7 | 579 | |
| emilmont | 10:3bc89ef62ce7 | 580 | The function reads the priority of an interrupt. The interrupt |
| emilmont | 10:3bc89ef62ce7 | 581 | number can be positive to specify an external (device specific) |
| emilmont | 10:3bc89ef62ce7 | 582 | interrupt, or negative to specify an internal (core) interrupt. |
| emilmont | 10:3bc89ef62ce7 | 583 | |
| emilmont | 10:3bc89ef62ce7 | 584 | |
| emilmont | 10:3bc89ef62ce7 | 585 | \param [in] IRQn Interrupt number. |
| emilmont | 10:3bc89ef62ce7 | 586 | \return Interrupt Priority. Value is aligned automatically to the implemented |
| emilmont | 10:3bc89ef62ce7 | 587 | priority bits of the microcontroller. |
| emilmont | 10:3bc89ef62ce7 | 588 | */ |
| emilmont | 10:3bc89ef62ce7 | 589 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
| emilmont | 10:3bc89ef62ce7 | 590 | { |
| emilmont | 10:3bc89ef62ce7 | 591 | |
| emilmont | 10:3bc89ef62ce7 | 592 | if(IRQn < 0) { |
| emilmont | 10:3bc89ef62ce7 | 593 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ |
| emilmont | 10:3bc89ef62ce7 | 594 | else { |
| emilmont | 10:3bc89ef62ce7 | 595 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
| emilmont | 10:3bc89ef62ce7 | 596 | } |
| emilmont | 10:3bc89ef62ce7 | 597 | |
| emilmont | 10:3bc89ef62ce7 | 598 | |
| emilmont | 10:3bc89ef62ce7 | 599 | /** \brief System Reset |
| emilmont | 10:3bc89ef62ce7 | 600 | |
| emilmont | 10:3bc89ef62ce7 | 601 | The function initiates a system reset request to reset the MCU. |
| emilmont | 10:3bc89ef62ce7 | 602 | */ |
| emilmont | 10:3bc89ef62ce7 | 603 | __STATIC_INLINE void NVIC_SystemReset(void) |
| emilmont | 10:3bc89ef62ce7 | 604 | { |
| emilmont | 10:3bc89ef62ce7 | 605 | __DSB(); /* Ensure all outstanding memory accesses included |
| emilmont | 10:3bc89ef62ce7 | 606 | buffered write are completed before reset */ |
| emilmont | 10:3bc89ef62ce7 | 607 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
| emilmont | 10:3bc89ef62ce7 | 608 | SCB_AIRCR_SYSRESETREQ_Msk); |
| emilmont | 10:3bc89ef62ce7 | 609 | __DSB(); /* Ensure completion of memory access */ |
| emilmont | 10:3bc89ef62ce7 | 610 | while(1); /* wait until reset */ |
| emilmont | 10:3bc89ef62ce7 | 611 | } |
| emilmont | 10:3bc89ef62ce7 | 612 | |
| emilmont | 10:3bc89ef62ce7 | 613 | /*@} end of CMSIS_Core_NVICFunctions */ |
| emilmont | 10:3bc89ef62ce7 | 614 | |
| emilmont | 10:3bc89ef62ce7 | 615 | |
| emilmont | 10:3bc89ef62ce7 | 616 | |
| emilmont | 10:3bc89ef62ce7 | 617 | /* ################################## SysTick function ############################################ */ |
| emilmont | 10:3bc89ef62ce7 | 618 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 10:3bc89ef62ce7 | 619 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| emilmont | 10:3bc89ef62ce7 | 620 | \brief Functions that configure the System. |
| emilmont | 10:3bc89ef62ce7 | 621 | @{ |
| emilmont | 10:3bc89ef62ce7 | 622 | */ |
| emilmont | 10:3bc89ef62ce7 | 623 | |
| emilmont | 10:3bc89ef62ce7 | 624 | #if (__Vendor_SysTickConfig == 0) |
| emilmont | 10:3bc89ef62ce7 | 625 | |
| emilmont | 10:3bc89ef62ce7 | 626 | /** \brief System Tick Configuration |
| emilmont | 10:3bc89ef62ce7 | 627 | |
| emilmont | 10:3bc89ef62ce7 | 628 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| emilmont | 10:3bc89ef62ce7 | 629 | Counter is in free running mode to generate periodic interrupts. |
| emilmont | 10:3bc89ef62ce7 | 630 | |
| emilmont | 10:3bc89ef62ce7 | 631 | \param [in] ticks Number of ticks between two interrupts. |
| emilmont | 10:3bc89ef62ce7 | 632 | |
| emilmont | 10:3bc89ef62ce7 | 633 | \return 0 Function succeeded. |
| emilmont | 10:3bc89ef62ce7 | 634 | \return 1 Function failed. |
| emilmont | 10:3bc89ef62ce7 | 635 | |
| emilmont | 10:3bc89ef62ce7 | 636 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| emilmont | 10:3bc89ef62ce7 | 637 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| emilmont | 10:3bc89ef62ce7 | 638 | must contain a vendor-specific implementation of this function. |
| emilmont | 10:3bc89ef62ce7 | 639 | |
| emilmont | 10:3bc89ef62ce7 | 640 | */ |
| emilmont | 10:3bc89ef62ce7 | 641 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| emilmont | 10:3bc89ef62ce7 | 642 | { |
| emilmont | 10:3bc89ef62ce7 | 643 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
| emilmont | 10:3bc89ef62ce7 | 644 | |
| emilmont | 10:3bc89ef62ce7 | 645 | SysTick->LOAD = ticks - 1; /* set reload register */ |
| emilmont | 10:3bc89ef62ce7 | 646 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
| emilmont | 10:3bc89ef62ce7 | 647 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
| emilmont | 10:3bc89ef62ce7 | 648 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| emilmont | 10:3bc89ef62ce7 | 649 | SysTick_CTRL_TICKINT_Msk | |
| emilmont | 10:3bc89ef62ce7 | 650 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| emilmont | 10:3bc89ef62ce7 | 651 | return (0); /* Function successful */ |
| emilmont | 10:3bc89ef62ce7 | 652 | } |
| emilmont | 10:3bc89ef62ce7 | 653 | |
| emilmont | 10:3bc89ef62ce7 | 654 | #endif |
| emilmont | 10:3bc89ef62ce7 | 655 | |
| emilmont | 10:3bc89ef62ce7 | 656 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| emilmont | 10:3bc89ef62ce7 | 657 | |
| emilmont | 10:3bc89ef62ce7 | 658 | |
| emilmont | 10:3bc89ef62ce7 | 659 | |
| emilmont | 10:3bc89ef62ce7 | 660 | |
| emilmont | 10:3bc89ef62ce7 | 661 | #endif /* __CORE_CM0_H_DEPENDANT */ |
| emilmont | 10:3bc89ef62ce7 | 662 | |
| emilmont | 10:3bc89ef62ce7 | 663 | #endif /* __CMSIS_GENERIC */ |
| emilmont | 10:3bc89ef62ce7 | 664 | |
| emilmont | 10:3bc89ef62ce7 | 665 | #ifdef __cplusplus |
| emilmont | 10:3bc89ef62ce7 | 666 | } |
| emilmont | 10:3bc89ef62ce7 | 667 | #endif |
