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Last commit 20 Feb 2019 by mbed official

vendor/NXP/LPC11U24/cmsis/GCC_ARM/startup_LPC11xx.s@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* File: startup_ARMCM0.S
emilmont 10:3bc89ef62ce7 2 * Purpose: startup file for Cortex-M0 devices. Should use with
emilmont 10:3bc89ef62ce7 3 * GCC for ARM Embedded Processors
emilmont 10:3bc89ef62ce7 4 * Version: V1.2
emilmont 10:3bc89ef62ce7 5 * Date: 15 Nov 2011
emilmont 10:3bc89ef62ce7 6 *
emilmont 10:3bc89ef62ce7 7 * Copyright (c) 2011, ARM Limited
emilmont 10:3bc89ef62ce7 8 * All rights reserved.
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Redistribution and use in source and binary forms, with or without
emilmont 10:3bc89ef62ce7 11 * modification, are permitted provided that the following conditions are met:
emilmont 10:3bc89ef62ce7 12 * Redistributions of source code must retain the above copyright
emilmont 10:3bc89ef62ce7 13 notice, this list of conditions and the following disclaimer.
emilmont 10:3bc89ef62ce7 14 * Redistributions in binary form must reproduce the above copyright
emilmont 10:3bc89ef62ce7 15 notice, this list of conditions and the following disclaimer in the
emilmont 10:3bc89ef62ce7 16 documentation and/or other materials provided with the distribution.
emilmont 10:3bc89ef62ce7 17 * Neither the name of the ARM Limited nor the
emilmont 10:3bc89ef62ce7 18 names of its contributors may be used to endorse or promote products
emilmont 10:3bc89ef62ce7 19 derived from this software without specific prior written permission.
emilmont 10:3bc89ef62ce7 20 *
emilmont 10:3bc89ef62ce7 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
emilmont 10:3bc89ef62ce7 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
emilmont 10:3bc89ef62ce7 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 10:3bc89ef62ce7 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
emilmont 10:3bc89ef62ce7 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
emilmont 10:3bc89ef62ce7 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
emilmont 10:3bc89ef62ce7 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
emilmont 10:3bc89ef62ce7 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
emilmont 10:3bc89ef62ce7 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
emilmont 10:3bc89ef62ce7 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 10:3bc89ef62ce7 31 */
emilmont 10:3bc89ef62ce7 32 .syntax unified
emilmont 10:3bc89ef62ce7 33 .arch armv6-m
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 /* Memory Model
emilmont 10:3bc89ef62ce7 36 The HEAP starts at the end of the DATA section and grows upward.
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 The STACK starts at the end of the RAM and grows downward.
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 The HEAP and stack STACK are only checked at compile time:
emilmont 10:3bc89ef62ce7 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 This is just a check for the bare minimum for the Heap+Stack area before
emilmont 10:3bc89ef62ce7 44 aborting compilation, it is not the run time limit:
emilmont 10:3bc89ef62ce7 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
emilmont 10:3bc89ef62ce7 46 */
emilmont 10:3bc89ef62ce7 47 .section .stack
emilmont 10:3bc89ef62ce7 48 .align 3
emilmont 10:3bc89ef62ce7 49 #ifdef __STACK_SIZE
emilmont 10:3bc89ef62ce7 50 .equ Stack_Size, __STACK_SIZE
emilmont 10:3bc89ef62ce7 51 #else
emilmont 10:3bc89ef62ce7 52 .equ Stack_Size, 0x80
emilmont 10:3bc89ef62ce7 53 #endif
emilmont 10:3bc89ef62ce7 54 .globl __StackTop
emilmont 10:3bc89ef62ce7 55 .globl __StackLimit
emilmont 10:3bc89ef62ce7 56 __StackLimit:
emilmont 10:3bc89ef62ce7 57 .space Stack_Size
emilmont 10:3bc89ef62ce7 58 .size __StackLimit, . - __StackLimit
emilmont 10:3bc89ef62ce7 59 __StackTop:
emilmont 10:3bc89ef62ce7 60 .size __StackTop, . - __StackTop
emilmont 10:3bc89ef62ce7 61
emilmont 10:3bc89ef62ce7 62 .section .heap
emilmont 10:3bc89ef62ce7 63 .align 3
emilmont 10:3bc89ef62ce7 64 #ifdef __HEAP_SIZE
emilmont 10:3bc89ef62ce7 65 .equ Heap_Size, __HEAP_SIZE
emilmont 10:3bc89ef62ce7 66 #else
emilmont 10:3bc89ef62ce7 67 .equ Heap_Size, 0x80
emilmont 10:3bc89ef62ce7 68 #endif
emilmont 10:3bc89ef62ce7 69 .globl __HeapBase
emilmont 10:3bc89ef62ce7 70 .globl __HeapLimit
emilmont 10:3bc89ef62ce7 71 __HeapBase:
emilmont 10:3bc89ef62ce7 72 .space Heap_Size
emilmont 10:3bc89ef62ce7 73 .size __HeapBase, . - __HeapBase
emilmont 10:3bc89ef62ce7 74 __HeapLimit:
emilmont 10:3bc89ef62ce7 75 .size __HeapLimit, . - __HeapLimit
emilmont 10:3bc89ef62ce7 76
emilmont 10:3bc89ef62ce7 77 .section .isr_vector
emilmont 10:3bc89ef62ce7 78 .align 2
emilmont 10:3bc89ef62ce7 79 .globl __isr_vector
emilmont 10:3bc89ef62ce7 80 __isr_vector:
emilmont 10:3bc89ef62ce7 81 .long __StackTop /* Top of Stack */
emilmont 10:3bc89ef62ce7 82 .long Reset_Handler /* Reset Handler */
emilmont 10:3bc89ef62ce7 83 .long NMI_Handler /* NMI Handler */
emilmont 10:3bc89ef62ce7 84 .long HardFault_Handler /* Hard Fault Handler */
emilmont 10:3bc89ef62ce7 85 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 86 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 87 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 88 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 89 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 90 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 91 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 92 .long SVC_Handler /* SVCall Handler */
emilmont 10:3bc89ef62ce7 93 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 94 .long 0 /* Reserved */
emilmont 10:3bc89ef62ce7 95 .long PendSV_Handler /* PendSV Handler */
emilmont 10:3bc89ef62ce7 96 .long SysTick_Handler /* SysTick Handler */
emilmont 10:3bc89ef62ce7 97
emilmont 10:3bc89ef62ce7 98 /* LPC11xx interrupts */
emilmont 10:3bc89ef62ce7 99 .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */
emilmont 10:3bc89ef62ce7 100 .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */
emilmont 10:3bc89ef62ce7 101 .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */
emilmont 10:3bc89ef62ce7 102 .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */
emilmont 10:3bc89ef62ce7 103 .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */
emilmont 10:3bc89ef62ce7 104 .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */
emilmont 10:3bc89ef62ce7 105 .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */
emilmont 10:3bc89ef62ce7 106 .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */
emilmont 10:3bc89ef62ce7 107 .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */
emilmont 10:3bc89ef62ce7 108 .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */
emilmont 10:3bc89ef62ce7 109 .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */
emilmont 10:3bc89ef62ce7 110 .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */
emilmont 10:3bc89ef62ce7 111 .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */
emilmont 10:3bc89ef62ce7 112 .long Default_Handler /* 29 13 */
emilmont 10:3bc89ef62ce7 113 .long SSP1_IRQHandler /* 30 14 SSP1 */
emilmont 10:3bc89ef62ce7 114 .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */
emilmont 10:3bc89ef62ce7 115 .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */
emilmont 10:3bc89ef62ce7 116 .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */
emilmont 10:3bc89ef62ce7 117 .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */
emilmont 10:3bc89ef62ce7 118 .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
emilmont 10:3bc89ef62ce7 119 .long SSP0_IRQHandler /* 36 20 SSP */
emilmont 10:3bc89ef62ce7 120 .long UART_IRQHandler /* 37 21 UART */
emilmont 10:3bc89ef62ce7 121 .long Default_Handler /* 38 22 */
emilmont 10:3bc89ef62ce7 122 .long Default_Handler /* 39 23 */
emilmont 10:3bc89ef62ce7 123 .long ADC_IRQHandler /* 40 24 ADC end of conversion */
emilmont 10:3bc89ef62ce7 124 .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
emilmont 10:3bc89ef62ce7 125 .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
emilmont 10:3bc89ef62ce7 126 .long Default_Handler /* 43 27 */
emilmont 10:3bc89ef62ce7 127 .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */
emilmont 10:3bc89ef62ce7 128 .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */
emilmont 10:3bc89ef62ce7 129 .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */
emilmont 10:3bc89ef62ce7 130 .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */
emilmont 10:3bc89ef62ce7 131
emilmont 10:3bc89ef62ce7 132 .size __isr_vector, . - __isr_vector
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134 .section .text.Reset_Handler
emilmont 10:3bc89ef62ce7 135 .thumb
emilmont 10:3bc89ef62ce7 136 .thumb_func
emilmont 10:3bc89ef62ce7 137 .align 2
emilmont 10:3bc89ef62ce7 138 .globl Reset_Handler
emilmont 10:3bc89ef62ce7 139 .type Reset_Handler, %function
emilmont 10:3bc89ef62ce7 140 Reset_Handler:
emilmont 10:3bc89ef62ce7 141 /* Loop to copy data from read only memory to RAM. The ranges
emilmont 10:3bc89ef62ce7 142 * of copy from/to are specified by following symbols evaluated in
emilmont 10:3bc89ef62ce7 143 * linker script.
emilmont 10:3bc89ef62ce7 144 * __etext: End of code section, i.e., begin of data sections to copy from.
emilmont 10:3bc89ef62ce7 145 * __data_start__/__data_end__: RAM address range that data should be
emilmont 10:3bc89ef62ce7 146 * copied to. Both must be aligned to 4 bytes boundary. */
emilmont 10:3bc89ef62ce7 147
emilmont 10:3bc89ef62ce7 148 ldr r1, =__etext
emilmont 10:3bc89ef62ce7 149 ldr r2, =__data_start__
emilmont 10:3bc89ef62ce7 150 ldr r3, =__data_end__
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 subs r3, r2
emilmont 10:3bc89ef62ce7 153 ble .flash_to_ram_loop_end
emilmont 10:3bc89ef62ce7 154
emilmont 10:3bc89ef62ce7 155 movs r4, 0
emilmont 10:3bc89ef62ce7 156 .flash_to_ram_loop:
emilmont 10:3bc89ef62ce7 157 ldr r0, [r1,r4]
emilmont 10:3bc89ef62ce7 158 str r0, [r2,r4]
emilmont 10:3bc89ef62ce7 159 adds r4, 4
emilmont 10:3bc89ef62ce7 160 cmp r4, r3
emilmont 10:3bc89ef62ce7 161 blt .flash_to_ram_loop
emilmont 10:3bc89ef62ce7 162 .flash_to_ram_loop_end:
emilmont 10:3bc89ef62ce7 163
emilmont 10:3bc89ef62ce7 164 ldr r0, =SystemInit
emilmont 10:3bc89ef62ce7 165 blx r0
emilmont 10:3bc89ef62ce7 166 ldr r0, =_start
emilmont 10:3bc89ef62ce7 167 bx r0
emilmont 10:3bc89ef62ce7 168 .pool
emilmont 10:3bc89ef62ce7 169 .size Reset_Handler, . - Reset_Handler
emilmont 10:3bc89ef62ce7 170
emilmont 10:3bc89ef62ce7 171 .text
emilmont 10:3bc89ef62ce7 172 /* Macro to define default handlers. Default handler
emilmont 10:3bc89ef62ce7 173 * will be weak symbol and just dead loops. They can be
emilmont 10:3bc89ef62ce7 174 * overwritten by other handlers */
emilmont 10:3bc89ef62ce7 175 .macro def_default_handler handler_name
emilmont 10:3bc89ef62ce7 176 .align 1
emilmont 10:3bc89ef62ce7 177 .thumb_func
emilmont 10:3bc89ef62ce7 178 .weak \handler_name
emilmont 10:3bc89ef62ce7 179 .type \handler_name, %function
emilmont 10:3bc89ef62ce7 180 \handler_name :
emilmont 10:3bc89ef62ce7 181 b .
emilmont 10:3bc89ef62ce7 182 .size \handler_name, . - \handler_name
emilmont 10:3bc89ef62ce7 183 .endm
emilmont 10:3bc89ef62ce7 184
emilmont 10:3bc89ef62ce7 185 def_default_handler NMI_Handler
emilmont 10:3bc89ef62ce7 186 def_default_handler HardFault_Handler
emilmont 10:3bc89ef62ce7 187 def_default_handler SVC_Handler
emilmont 10:3bc89ef62ce7 188 def_default_handler PendSV_Handler
emilmont 10:3bc89ef62ce7 189 def_default_handler SysTick_Handler
emilmont 10:3bc89ef62ce7 190 def_default_handler Default_Handler
emilmont 10:3bc89ef62ce7 191
emilmont 10:3bc89ef62ce7 192 def_default_handler WAKEUP_IRQHandler
emilmont 10:3bc89ef62ce7 193 def_default_handler SSP1_IRQHandler
emilmont 10:3bc89ef62ce7 194 def_default_handler I2C_IRQHandler
emilmont 10:3bc89ef62ce7 195 def_default_handler TIMER16_0_IRQHandler
emilmont 10:3bc89ef62ce7 196 def_default_handler TIMER16_1_IRQHandler
emilmont 10:3bc89ef62ce7 197 def_default_handler TIMER32_0_IRQHandler
emilmont 10:3bc89ef62ce7 198 def_default_handler TIMER32_1_IRQHandler
emilmont 10:3bc89ef62ce7 199 def_default_handler SSP0_IRQHandler
emilmont 10:3bc89ef62ce7 200 def_default_handler UART_IRQHandler
emilmont 10:3bc89ef62ce7 201 def_default_handler ADC_IRQHandler
emilmont 10:3bc89ef62ce7 202 def_default_handler WDT_IRQHandler
emilmont 10:3bc89ef62ce7 203 def_default_handler BOD_IRQHandler
emilmont 10:3bc89ef62ce7 204 def_default_handler PIOINT3_IRQHandler
emilmont 10:3bc89ef62ce7 205 def_default_handler PIOINT2_IRQHandler
emilmont 10:3bc89ef62ce7 206 def_default_handler PIOINT1_IRQHandler
emilmont 10:3bc89ef62ce7 207 def_default_handler PIOINT0_IRQHandler
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 .weak DEF_IRQHandler
emilmont 10:3bc89ef62ce7 210 .set DEF_IRQHandler, Default_Handler
emilmont 10:3bc89ef62ce7 211
emilmont 10:3bc89ef62ce7 212 .end
emilmont 10:3bc89ef62ce7 213