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Last commit 20 Feb 2019 by mbed official

vendor/Freescale/KL25Z/cmsis/core_cmFunc.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file core_cmFunc.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 10:3bc89ef62ce7 4 * @version V3.02
emilmont 10:3bc89ef62ce7 5 * @date 24. May 2012
emilmont 10:3bc89ef62ce7 6 *
emilmont 10:3bc89ef62ce7 7 * @note
emilmont 10:3bc89ef62ce7 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * @par
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * @par
emilmont 10:3bc89ef62ce7 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 21 *
emilmont 10:3bc89ef62ce7 22 ******************************************************************************/
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 #ifndef __CORE_CMFUNC_H
emilmont 10:3bc89ef62ce7 25 #define __CORE_CMFUNC_H
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 /* ########################### Core Function Access ########################### */
emilmont 10:3bc89ef62ce7 29 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 10:3bc89ef62ce7 31 @{
emilmont 10:3bc89ef62ce7 32 */
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 10:3bc89ef62ce7 35 /* ARM armcc specific functions */
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 #if (__ARMCC_VERSION < 400677)
emilmont 10:3bc89ef62ce7 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 10:3bc89ef62ce7 39 #endif
emilmont 10:3bc89ef62ce7 40
emilmont 10:3bc89ef62ce7 41 /* intrinsic void __enable_irq(); */
emilmont 10:3bc89ef62ce7 42 /* intrinsic void __disable_irq(); */
emilmont 10:3bc89ef62ce7 43
emilmont 10:3bc89ef62ce7 44 /** \brief Get Control Register
emilmont 10:3bc89ef62ce7 45
emilmont 10:3bc89ef62ce7 46 This function returns the content of the Control Register.
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 \return Control Register value
emilmont 10:3bc89ef62ce7 49 */
emilmont 10:3bc89ef62ce7 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 10:3bc89ef62ce7 51 {
emilmont 10:3bc89ef62ce7 52 register uint32_t __regControl __ASM("control");
emilmont 10:3bc89ef62ce7 53 return(__regControl);
emilmont 10:3bc89ef62ce7 54 }
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56
emilmont 10:3bc89ef62ce7 57 /** \brief Set Control Register
emilmont 10:3bc89ef62ce7 58
emilmont 10:3bc89ef62ce7 59 This function writes the given value to the Control Register.
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 \param [in] control Control Register value to set
emilmont 10:3bc89ef62ce7 62 */
emilmont 10:3bc89ef62ce7 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 10:3bc89ef62ce7 64 {
emilmont 10:3bc89ef62ce7 65 register uint32_t __regControl __ASM("control");
emilmont 10:3bc89ef62ce7 66 __regControl = control;
emilmont 10:3bc89ef62ce7 67 }
emilmont 10:3bc89ef62ce7 68
emilmont 10:3bc89ef62ce7 69
emilmont 10:3bc89ef62ce7 70 /** \brief Get IPSR Register
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 This function returns the content of the IPSR Register.
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 \return IPSR Register value
emilmont 10:3bc89ef62ce7 75 */
emilmont 10:3bc89ef62ce7 76 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 10:3bc89ef62ce7 77 {
emilmont 10:3bc89ef62ce7 78 register uint32_t __regIPSR __ASM("ipsr");
emilmont 10:3bc89ef62ce7 79 return(__regIPSR);
emilmont 10:3bc89ef62ce7 80 }
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 /** \brief Get APSR Register
emilmont 10:3bc89ef62ce7 84
emilmont 10:3bc89ef62ce7 85 This function returns the content of the APSR Register.
emilmont 10:3bc89ef62ce7 86
emilmont 10:3bc89ef62ce7 87 \return APSR Register value
emilmont 10:3bc89ef62ce7 88 */
emilmont 10:3bc89ef62ce7 89 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 10:3bc89ef62ce7 90 {
emilmont 10:3bc89ef62ce7 91 register uint32_t __regAPSR __ASM("apsr");
emilmont 10:3bc89ef62ce7 92 return(__regAPSR);
emilmont 10:3bc89ef62ce7 93 }
emilmont 10:3bc89ef62ce7 94
emilmont 10:3bc89ef62ce7 95
emilmont 10:3bc89ef62ce7 96 /** \brief Get xPSR Register
emilmont 10:3bc89ef62ce7 97
emilmont 10:3bc89ef62ce7 98 This function returns the content of the xPSR Register.
emilmont 10:3bc89ef62ce7 99
emilmont 10:3bc89ef62ce7 100 \return xPSR Register value
emilmont 10:3bc89ef62ce7 101 */
emilmont 10:3bc89ef62ce7 102 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 10:3bc89ef62ce7 103 {
emilmont 10:3bc89ef62ce7 104 register uint32_t __regXPSR __ASM("xpsr");
emilmont 10:3bc89ef62ce7 105 return(__regXPSR);
emilmont 10:3bc89ef62ce7 106 }
emilmont 10:3bc89ef62ce7 107
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 /** \brief Get Process Stack Pointer
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 10:3bc89ef62ce7 112
emilmont 10:3bc89ef62ce7 113 \return PSP Register value
emilmont 10:3bc89ef62ce7 114 */
emilmont 10:3bc89ef62ce7 115 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 10:3bc89ef62ce7 116 {
emilmont 10:3bc89ef62ce7 117 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 10:3bc89ef62ce7 118 return(__regProcessStackPointer);
emilmont 10:3bc89ef62ce7 119 }
emilmont 10:3bc89ef62ce7 120
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 /** \brief Set Process Stack Pointer
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 10:3bc89ef62ce7 127 */
emilmont 10:3bc89ef62ce7 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 10:3bc89ef62ce7 129 {
emilmont 10:3bc89ef62ce7 130 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 10:3bc89ef62ce7 131 __regProcessStackPointer = topOfProcStack;
emilmont 10:3bc89ef62ce7 132 }
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134
emilmont 10:3bc89ef62ce7 135 /** \brief Get Main Stack Pointer
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139 \return MSP Register value
emilmont 10:3bc89ef62ce7 140 */
emilmont 10:3bc89ef62ce7 141 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 10:3bc89ef62ce7 142 {
emilmont 10:3bc89ef62ce7 143 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 10:3bc89ef62ce7 144 return(__regMainStackPointer);
emilmont 10:3bc89ef62ce7 145 }
emilmont 10:3bc89ef62ce7 146
emilmont 10:3bc89ef62ce7 147
emilmont 10:3bc89ef62ce7 148 /** \brief Set Main Stack Pointer
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 10:3bc89ef62ce7 153 */
emilmont 10:3bc89ef62ce7 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 10:3bc89ef62ce7 155 {
emilmont 10:3bc89ef62ce7 156 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 10:3bc89ef62ce7 157 __regMainStackPointer = topOfMainStack;
emilmont 10:3bc89ef62ce7 158 }
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 /** \brief Get Priority Mask
emilmont 10:3bc89ef62ce7 162
emilmont 10:3bc89ef62ce7 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 10:3bc89ef62ce7 164
emilmont 10:3bc89ef62ce7 165 \return Priority Mask value
emilmont 10:3bc89ef62ce7 166 */
emilmont 10:3bc89ef62ce7 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 10:3bc89ef62ce7 168 {
emilmont 10:3bc89ef62ce7 169 register uint32_t __regPriMask __ASM("primask");
emilmont 10:3bc89ef62ce7 170 return(__regPriMask);
emilmont 10:3bc89ef62ce7 171 }
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173
emilmont 10:3bc89ef62ce7 174 /** \brief Set Priority Mask
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 This function assigns the given value to the Priority Mask Register.
emilmont 10:3bc89ef62ce7 177
emilmont 10:3bc89ef62ce7 178 \param [in] priMask Priority Mask
emilmont 10:3bc89ef62ce7 179 */
emilmont 10:3bc89ef62ce7 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 10:3bc89ef62ce7 181 {
emilmont 10:3bc89ef62ce7 182 register uint32_t __regPriMask __ASM("primask");
emilmont 10:3bc89ef62ce7 183 __regPriMask = (priMask);
emilmont 10:3bc89ef62ce7 184 }
emilmont 10:3bc89ef62ce7 185
emilmont 10:3bc89ef62ce7 186
emilmont 10:3bc89ef62ce7 187 #if (__CORTEX_M >= 0x03)
emilmont 10:3bc89ef62ce7 188
emilmont 10:3bc89ef62ce7 189 /** \brief Enable FIQ
emilmont 10:3bc89ef62ce7 190
emilmont 10:3bc89ef62ce7 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 10:3bc89ef62ce7 192 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 193 */
emilmont 10:3bc89ef62ce7 194 #define __enable_fault_irq __enable_fiq
emilmont 10:3bc89ef62ce7 195
emilmont 10:3bc89ef62ce7 196
emilmont 10:3bc89ef62ce7 197 /** \brief Disable FIQ
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 10:3bc89ef62ce7 200 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 201 */
emilmont 10:3bc89ef62ce7 202 #define __disable_fault_irq __disable_fiq
emilmont 10:3bc89ef62ce7 203
emilmont 10:3bc89ef62ce7 204
emilmont 10:3bc89ef62ce7 205 /** \brief Get Base Priority
emilmont 10:3bc89ef62ce7 206
emilmont 10:3bc89ef62ce7 207 This function returns the current value of the Base Priority register.
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 \return Base Priority register value
emilmont 10:3bc89ef62ce7 210 */
emilmont 10:3bc89ef62ce7 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 10:3bc89ef62ce7 212 {
emilmont 10:3bc89ef62ce7 213 register uint32_t __regBasePri __ASM("basepri");
emilmont 10:3bc89ef62ce7 214 return(__regBasePri);
emilmont 10:3bc89ef62ce7 215 }
emilmont 10:3bc89ef62ce7 216
emilmont 10:3bc89ef62ce7 217
emilmont 10:3bc89ef62ce7 218 /** \brief Set Base Priority
emilmont 10:3bc89ef62ce7 219
emilmont 10:3bc89ef62ce7 220 This function assigns the given value to the Base Priority register.
emilmont 10:3bc89ef62ce7 221
emilmont 10:3bc89ef62ce7 222 \param [in] basePri Base Priority value to set
emilmont 10:3bc89ef62ce7 223 */
emilmont 10:3bc89ef62ce7 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 10:3bc89ef62ce7 225 {
emilmont 10:3bc89ef62ce7 226 register uint32_t __regBasePri __ASM("basepri");
emilmont 10:3bc89ef62ce7 227 __regBasePri = (basePri & 0xff);
emilmont 10:3bc89ef62ce7 228 }
emilmont 10:3bc89ef62ce7 229
emilmont 10:3bc89ef62ce7 230
emilmont 10:3bc89ef62ce7 231 /** \brief Get Fault Mask
emilmont 10:3bc89ef62ce7 232
emilmont 10:3bc89ef62ce7 233 This function returns the current value of the Fault Mask register.
emilmont 10:3bc89ef62ce7 234
emilmont 10:3bc89ef62ce7 235 \return Fault Mask register value
emilmont 10:3bc89ef62ce7 236 */
emilmont 10:3bc89ef62ce7 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 10:3bc89ef62ce7 238 {
emilmont 10:3bc89ef62ce7 239 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 10:3bc89ef62ce7 240 return(__regFaultMask);
emilmont 10:3bc89ef62ce7 241 }
emilmont 10:3bc89ef62ce7 242
emilmont 10:3bc89ef62ce7 243
emilmont 10:3bc89ef62ce7 244 /** \brief Set Fault Mask
emilmont 10:3bc89ef62ce7 245
emilmont 10:3bc89ef62ce7 246 This function assigns the given value to the Fault Mask register.
emilmont 10:3bc89ef62ce7 247
emilmont 10:3bc89ef62ce7 248 \param [in] faultMask Fault Mask value to set
emilmont 10:3bc89ef62ce7 249 */
emilmont 10:3bc89ef62ce7 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 10:3bc89ef62ce7 251 {
emilmont 10:3bc89ef62ce7 252 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 10:3bc89ef62ce7 253 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 10:3bc89ef62ce7 254 }
emilmont 10:3bc89ef62ce7 255
emilmont 10:3bc89ef62ce7 256 #endif /* (__CORTEX_M >= 0x03) */
emilmont 10:3bc89ef62ce7 257
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 #if (__CORTEX_M == 0x04)
emilmont 10:3bc89ef62ce7 260
emilmont 10:3bc89ef62ce7 261 /** \brief Get FPSCR
emilmont 10:3bc89ef62ce7 262
emilmont 10:3bc89ef62ce7 263 This function returns the current value of the Floating Point Status/Control register.
emilmont 10:3bc89ef62ce7 264
emilmont 10:3bc89ef62ce7 265 \return Floating Point Status/Control register value
emilmont 10:3bc89ef62ce7 266 */
emilmont 10:3bc89ef62ce7 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 10:3bc89ef62ce7 268 {
emilmont 10:3bc89ef62ce7 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 10:3bc89ef62ce7 270 register uint32_t __regfpscr __ASM("fpscr");
emilmont 10:3bc89ef62ce7 271 return(__regfpscr);
emilmont 10:3bc89ef62ce7 272 #else
emilmont 10:3bc89ef62ce7 273 return(0);
emilmont 10:3bc89ef62ce7 274 #endif
emilmont 10:3bc89ef62ce7 275 }
emilmont 10:3bc89ef62ce7 276
emilmont 10:3bc89ef62ce7 277
emilmont 10:3bc89ef62ce7 278 /** \brief Set FPSCR
emilmont 10:3bc89ef62ce7 279
emilmont 10:3bc89ef62ce7 280 This function assigns the given value to the Floating Point Status/Control register.
emilmont 10:3bc89ef62ce7 281
emilmont 10:3bc89ef62ce7 282 \param [in] fpscr Floating Point Status/Control value to set
emilmont 10:3bc89ef62ce7 283 */
emilmont 10:3bc89ef62ce7 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 10:3bc89ef62ce7 285 {
emilmont 10:3bc89ef62ce7 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 10:3bc89ef62ce7 287 register uint32_t __regfpscr __ASM("fpscr");
emilmont 10:3bc89ef62ce7 288 __regfpscr = (fpscr);
emilmont 10:3bc89ef62ce7 289 #endif
emilmont 10:3bc89ef62ce7 290 }
emilmont 10:3bc89ef62ce7 291
emilmont 10:3bc89ef62ce7 292 #endif /* (__CORTEX_M == 0x04) */
emilmont 10:3bc89ef62ce7 293
emilmont 10:3bc89ef62ce7 294
emilmont 10:3bc89ef62ce7 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 10:3bc89ef62ce7 296 /* IAR iccarm specific functions */
emilmont 10:3bc89ef62ce7 297
emilmont 10:3bc89ef62ce7 298 #include <cmsis_iar.h>
emilmont 10:3bc89ef62ce7 299
emilmont 10:3bc89ef62ce7 300
emilmont 10:3bc89ef62ce7 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 10:3bc89ef62ce7 302 /* TI CCS specific functions */
emilmont 10:3bc89ef62ce7 303
emilmont 10:3bc89ef62ce7 304 #include <cmsis_ccs.h>
emilmont 10:3bc89ef62ce7 305
emilmont 10:3bc89ef62ce7 306
emilmont 10:3bc89ef62ce7 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 308 /* GNU gcc specific functions */
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 /** \brief Enable IRQ Interrupts
emilmont 10:3bc89ef62ce7 311
emilmont 10:3bc89ef62ce7 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 10:3bc89ef62ce7 313 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 314 */
emilmont 10:3bc89ef62ce7 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 10:3bc89ef62ce7 316 {
emilmont 10:3bc89ef62ce7 317 __ASM volatile ("cpsie i" : : : "memory");
emilmont 10:3bc89ef62ce7 318 }
emilmont 10:3bc89ef62ce7 319
emilmont 10:3bc89ef62ce7 320
emilmont 10:3bc89ef62ce7 321 /** \brief Disable IRQ Interrupts
emilmont 10:3bc89ef62ce7 322
emilmont 10:3bc89ef62ce7 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 10:3bc89ef62ce7 324 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 325 */
emilmont 10:3bc89ef62ce7 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 10:3bc89ef62ce7 327 {
emilmont 10:3bc89ef62ce7 328 __ASM volatile ("cpsid i" : : : "memory");
emilmont 10:3bc89ef62ce7 329 }
emilmont 10:3bc89ef62ce7 330
emilmont 10:3bc89ef62ce7 331
emilmont 10:3bc89ef62ce7 332 /** \brief Get Control Register
emilmont 10:3bc89ef62ce7 333
emilmont 10:3bc89ef62ce7 334 This function returns the content of the Control Register.
emilmont 10:3bc89ef62ce7 335
emilmont 10:3bc89ef62ce7 336 \return Control Register value
emilmont 10:3bc89ef62ce7 337 */
emilmont 10:3bc89ef62ce7 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 10:3bc89ef62ce7 339 {
emilmont 10:3bc89ef62ce7 340 uint32_t result;
emilmont 10:3bc89ef62ce7 341
emilmont 10:3bc89ef62ce7 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 10:3bc89ef62ce7 343 return(result);
emilmont 10:3bc89ef62ce7 344 }
emilmont 10:3bc89ef62ce7 345
emilmont 10:3bc89ef62ce7 346
emilmont 10:3bc89ef62ce7 347 /** \brief Set Control Register
emilmont 10:3bc89ef62ce7 348
emilmont 10:3bc89ef62ce7 349 This function writes the given value to the Control Register.
emilmont 10:3bc89ef62ce7 350
emilmont 10:3bc89ef62ce7 351 \param [in] control Control Register value to set
emilmont 10:3bc89ef62ce7 352 */
emilmont 10:3bc89ef62ce7 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 10:3bc89ef62ce7 354 {
emilmont 10:3bc89ef62ce7 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 10:3bc89ef62ce7 356 }
emilmont 10:3bc89ef62ce7 357
emilmont 10:3bc89ef62ce7 358
emilmont 10:3bc89ef62ce7 359 /** \brief Get IPSR Register
emilmont 10:3bc89ef62ce7 360
emilmont 10:3bc89ef62ce7 361 This function returns the content of the IPSR Register.
emilmont 10:3bc89ef62ce7 362
emilmont 10:3bc89ef62ce7 363 \return IPSR Register value
emilmont 10:3bc89ef62ce7 364 */
emilmont 10:3bc89ef62ce7 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 10:3bc89ef62ce7 366 {
emilmont 10:3bc89ef62ce7 367 uint32_t result;
emilmont 10:3bc89ef62ce7 368
emilmont 10:3bc89ef62ce7 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 10:3bc89ef62ce7 370 return(result);
emilmont 10:3bc89ef62ce7 371 }
emilmont 10:3bc89ef62ce7 372
emilmont 10:3bc89ef62ce7 373
emilmont 10:3bc89ef62ce7 374 /** \brief Get APSR Register
emilmont 10:3bc89ef62ce7 375
emilmont 10:3bc89ef62ce7 376 This function returns the content of the APSR Register.
emilmont 10:3bc89ef62ce7 377
emilmont 10:3bc89ef62ce7 378 \return APSR Register value
emilmont 10:3bc89ef62ce7 379 */
emilmont 10:3bc89ef62ce7 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 10:3bc89ef62ce7 381 {
emilmont 10:3bc89ef62ce7 382 uint32_t result;
emilmont 10:3bc89ef62ce7 383
emilmont 10:3bc89ef62ce7 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 10:3bc89ef62ce7 385 return(result);
emilmont 10:3bc89ef62ce7 386 }
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388
emilmont 10:3bc89ef62ce7 389 /** \brief Get xPSR Register
emilmont 10:3bc89ef62ce7 390
emilmont 10:3bc89ef62ce7 391 This function returns the content of the xPSR Register.
emilmont 10:3bc89ef62ce7 392
emilmont 10:3bc89ef62ce7 393 \return xPSR Register value
emilmont 10:3bc89ef62ce7 394 */
emilmont 10:3bc89ef62ce7 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 10:3bc89ef62ce7 396 {
emilmont 10:3bc89ef62ce7 397 uint32_t result;
emilmont 10:3bc89ef62ce7 398
emilmont 10:3bc89ef62ce7 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 10:3bc89ef62ce7 400 return(result);
emilmont 10:3bc89ef62ce7 401 }
emilmont 10:3bc89ef62ce7 402
emilmont 10:3bc89ef62ce7 403
emilmont 10:3bc89ef62ce7 404 /** \brief Get Process Stack Pointer
emilmont 10:3bc89ef62ce7 405
emilmont 10:3bc89ef62ce7 406 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 10:3bc89ef62ce7 407
emilmont 10:3bc89ef62ce7 408 \return PSP Register value
emilmont 10:3bc89ef62ce7 409 */
emilmont 10:3bc89ef62ce7 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 10:3bc89ef62ce7 411 {
emilmont 10:3bc89ef62ce7 412 register uint32_t result;
emilmont 10:3bc89ef62ce7 413
emilmont 10:3bc89ef62ce7 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 10:3bc89ef62ce7 415 return(result);
emilmont 10:3bc89ef62ce7 416 }
emilmont 10:3bc89ef62ce7 417
emilmont 10:3bc89ef62ce7 418
emilmont 10:3bc89ef62ce7 419 /** \brief Set Process Stack Pointer
emilmont 10:3bc89ef62ce7 420
emilmont 10:3bc89ef62ce7 421 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 10:3bc89ef62ce7 422
emilmont 10:3bc89ef62ce7 423 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 10:3bc89ef62ce7 424 */
emilmont 10:3bc89ef62ce7 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 10:3bc89ef62ce7 426 {
emilmont 10:3bc89ef62ce7 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 10:3bc89ef62ce7 428 }
emilmont 10:3bc89ef62ce7 429
emilmont 10:3bc89ef62ce7 430
emilmont 10:3bc89ef62ce7 431 /** \brief Get Main Stack Pointer
emilmont 10:3bc89ef62ce7 432
emilmont 10:3bc89ef62ce7 433 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 10:3bc89ef62ce7 434
emilmont 10:3bc89ef62ce7 435 \return MSP Register value
emilmont 10:3bc89ef62ce7 436 */
emilmont 10:3bc89ef62ce7 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 10:3bc89ef62ce7 438 {
emilmont 10:3bc89ef62ce7 439 register uint32_t result;
emilmont 10:3bc89ef62ce7 440
emilmont 10:3bc89ef62ce7 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 10:3bc89ef62ce7 442 return(result);
emilmont 10:3bc89ef62ce7 443 }
emilmont 10:3bc89ef62ce7 444
emilmont 10:3bc89ef62ce7 445
emilmont 10:3bc89ef62ce7 446 /** \brief Set Main Stack Pointer
emilmont 10:3bc89ef62ce7 447
emilmont 10:3bc89ef62ce7 448 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 10:3bc89ef62ce7 449
emilmont 10:3bc89ef62ce7 450 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 10:3bc89ef62ce7 451 */
emilmont 10:3bc89ef62ce7 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 10:3bc89ef62ce7 453 {
emilmont 10:3bc89ef62ce7 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 10:3bc89ef62ce7 455 }
emilmont 10:3bc89ef62ce7 456
emilmont 10:3bc89ef62ce7 457
emilmont 10:3bc89ef62ce7 458 /** \brief Get Priority Mask
emilmont 10:3bc89ef62ce7 459
emilmont 10:3bc89ef62ce7 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 10:3bc89ef62ce7 461
emilmont 10:3bc89ef62ce7 462 \return Priority Mask value
emilmont 10:3bc89ef62ce7 463 */
emilmont 10:3bc89ef62ce7 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 10:3bc89ef62ce7 465 {
emilmont 10:3bc89ef62ce7 466 uint32_t result;
emilmont 10:3bc89ef62ce7 467
emilmont 10:3bc89ef62ce7 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 10:3bc89ef62ce7 469 return(result);
emilmont 10:3bc89ef62ce7 470 }
emilmont 10:3bc89ef62ce7 471
emilmont 10:3bc89ef62ce7 472
emilmont 10:3bc89ef62ce7 473 /** \brief Set Priority Mask
emilmont 10:3bc89ef62ce7 474
emilmont 10:3bc89ef62ce7 475 This function assigns the given value to the Priority Mask Register.
emilmont 10:3bc89ef62ce7 476
emilmont 10:3bc89ef62ce7 477 \param [in] priMask Priority Mask
emilmont 10:3bc89ef62ce7 478 */
emilmont 10:3bc89ef62ce7 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 10:3bc89ef62ce7 480 {
emilmont 10:3bc89ef62ce7 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 10:3bc89ef62ce7 482 }
emilmont 10:3bc89ef62ce7 483
emilmont 10:3bc89ef62ce7 484
emilmont 10:3bc89ef62ce7 485 #if (__CORTEX_M >= 0x03)
emilmont 10:3bc89ef62ce7 486
emilmont 10:3bc89ef62ce7 487 /** \brief Enable FIQ
emilmont 10:3bc89ef62ce7 488
emilmont 10:3bc89ef62ce7 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 10:3bc89ef62ce7 490 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 491 */
emilmont 10:3bc89ef62ce7 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 10:3bc89ef62ce7 493 {
emilmont 10:3bc89ef62ce7 494 __ASM volatile ("cpsie f" : : : "memory");
emilmont 10:3bc89ef62ce7 495 }
emilmont 10:3bc89ef62ce7 496
emilmont 10:3bc89ef62ce7 497
emilmont 10:3bc89ef62ce7 498 /** \brief Disable FIQ
emilmont 10:3bc89ef62ce7 499
emilmont 10:3bc89ef62ce7 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 10:3bc89ef62ce7 501 Can only be executed in Privileged modes.
emilmont 10:3bc89ef62ce7 502 */
emilmont 10:3bc89ef62ce7 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 10:3bc89ef62ce7 504 {
emilmont 10:3bc89ef62ce7 505 __ASM volatile ("cpsid f" : : : "memory");
emilmont 10:3bc89ef62ce7 506 }
emilmont 10:3bc89ef62ce7 507
emilmont 10:3bc89ef62ce7 508
emilmont 10:3bc89ef62ce7 509 /** \brief Get Base Priority
emilmont 10:3bc89ef62ce7 510
emilmont 10:3bc89ef62ce7 511 This function returns the current value of the Base Priority register.
emilmont 10:3bc89ef62ce7 512
emilmont 10:3bc89ef62ce7 513 \return Base Priority register value
emilmont 10:3bc89ef62ce7 514 */
emilmont 10:3bc89ef62ce7 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 10:3bc89ef62ce7 516 {
emilmont 10:3bc89ef62ce7 517 uint32_t result;
emilmont 10:3bc89ef62ce7 518
emilmont 10:3bc89ef62ce7 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 10:3bc89ef62ce7 520 return(result);
emilmont 10:3bc89ef62ce7 521 }
emilmont 10:3bc89ef62ce7 522
emilmont 10:3bc89ef62ce7 523
emilmont 10:3bc89ef62ce7 524 /** \brief Set Base Priority
emilmont 10:3bc89ef62ce7 525
emilmont 10:3bc89ef62ce7 526 This function assigns the given value to the Base Priority register.
emilmont 10:3bc89ef62ce7 527
emilmont 10:3bc89ef62ce7 528 \param [in] basePri Base Priority value to set
emilmont 10:3bc89ef62ce7 529 */
emilmont 10:3bc89ef62ce7 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 10:3bc89ef62ce7 531 {
emilmont 10:3bc89ef62ce7 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 10:3bc89ef62ce7 533 }
emilmont 10:3bc89ef62ce7 534
emilmont 10:3bc89ef62ce7 535
emilmont 10:3bc89ef62ce7 536 /** \brief Get Fault Mask
emilmont 10:3bc89ef62ce7 537
emilmont 10:3bc89ef62ce7 538 This function returns the current value of the Fault Mask register.
emilmont 10:3bc89ef62ce7 539
emilmont 10:3bc89ef62ce7 540 \return Fault Mask register value
emilmont 10:3bc89ef62ce7 541 */
emilmont 10:3bc89ef62ce7 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 10:3bc89ef62ce7 543 {
emilmont 10:3bc89ef62ce7 544 uint32_t result;
emilmont 10:3bc89ef62ce7 545
emilmont 10:3bc89ef62ce7 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 10:3bc89ef62ce7 547 return(result);
emilmont 10:3bc89ef62ce7 548 }
emilmont 10:3bc89ef62ce7 549
emilmont 10:3bc89ef62ce7 550
emilmont 10:3bc89ef62ce7 551 /** \brief Set Fault Mask
emilmont 10:3bc89ef62ce7 552
emilmont 10:3bc89ef62ce7 553 This function assigns the given value to the Fault Mask register.
emilmont 10:3bc89ef62ce7 554
emilmont 10:3bc89ef62ce7 555 \param [in] faultMask Fault Mask value to set
emilmont 10:3bc89ef62ce7 556 */
emilmont 10:3bc89ef62ce7 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 10:3bc89ef62ce7 558 {
emilmont 10:3bc89ef62ce7 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 10:3bc89ef62ce7 560 }
emilmont 10:3bc89ef62ce7 561
emilmont 10:3bc89ef62ce7 562 #endif /* (__CORTEX_M >= 0x03) */
emilmont 10:3bc89ef62ce7 563
emilmont 10:3bc89ef62ce7 564
emilmont 10:3bc89ef62ce7 565 #if (__CORTEX_M == 0x04)
emilmont 10:3bc89ef62ce7 566
emilmont 10:3bc89ef62ce7 567 /** \brief Get FPSCR
emilmont 10:3bc89ef62ce7 568
emilmont 10:3bc89ef62ce7 569 This function returns the current value of the Floating Point Status/Control register.
emilmont 10:3bc89ef62ce7 570
emilmont 10:3bc89ef62ce7 571 \return Floating Point Status/Control register value
emilmont 10:3bc89ef62ce7 572 */
emilmont 10:3bc89ef62ce7 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 10:3bc89ef62ce7 574 {
emilmont 10:3bc89ef62ce7 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 10:3bc89ef62ce7 576 uint32_t result;
emilmont 10:3bc89ef62ce7 577
emilmont 10:3bc89ef62ce7 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 10:3bc89ef62ce7 579 return(result);
emilmont 10:3bc89ef62ce7 580 #else
emilmont 10:3bc89ef62ce7 581 return(0);
emilmont 10:3bc89ef62ce7 582 #endif
emilmont 10:3bc89ef62ce7 583 }
emilmont 10:3bc89ef62ce7 584
emilmont 10:3bc89ef62ce7 585
emilmont 10:3bc89ef62ce7 586 /** \brief Set FPSCR
emilmont 10:3bc89ef62ce7 587
emilmont 10:3bc89ef62ce7 588 This function assigns the given value to the Floating Point Status/Control register.
emilmont 10:3bc89ef62ce7 589
emilmont 10:3bc89ef62ce7 590 \param [in] fpscr Floating Point Status/Control value to set
emilmont 10:3bc89ef62ce7 591 */
emilmont 10:3bc89ef62ce7 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 10:3bc89ef62ce7 593 {
emilmont 10:3bc89ef62ce7 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 10:3bc89ef62ce7 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
emilmont 10:3bc89ef62ce7 596 #endif
emilmont 10:3bc89ef62ce7 597 }
emilmont 10:3bc89ef62ce7 598
emilmont 10:3bc89ef62ce7 599 #endif /* (__CORTEX_M == 0x04) */
emilmont 10:3bc89ef62ce7 600
emilmont 10:3bc89ef62ce7 601
emilmont 10:3bc89ef62ce7 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 10:3bc89ef62ce7 603 /* TASKING carm specific functions */
emilmont 10:3bc89ef62ce7 604
emilmont 10:3bc89ef62ce7 605 /*
emilmont 10:3bc89ef62ce7 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 10:3bc89ef62ce7 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 10:3bc89ef62ce7 608 * Including the CMSIS ones.
emilmont 10:3bc89ef62ce7 609 */
emilmont 10:3bc89ef62ce7 610
emilmont 10:3bc89ef62ce7 611 #endif
emilmont 10:3bc89ef62ce7 612
emilmont 10:3bc89ef62ce7 613 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 10:3bc89ef62ce7 614
emilmont 10:3bc89ef62ce7 615
emilmont 10:3bc89ef62ce7 616 #endif /* __CORE_CMFUNC_H */