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Last commit 20 Feb 2019 by mbed official

vendor/Freescale/KL25Z/cmsis/core_cm0plus.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file core_cm0plus.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
emilmont 10:3bc89ef62ce7 4 * @version V3.02
emilmont 10:3bc89ef62ce7 5 * @date 05. November 2012
emilmont 10:3bc89ef62ce7 6 *
emilmont 10:3bc89ef62ce7 7 * @note
emilmont 10:3bc89ef62ce7 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * @par
emilmont 10:3bc89ef62ce7 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 12 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 13 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 14 *
emilmont 10:3bc89ef62ce7 15 * @par
emilmont 10:3bc89ef62ce7 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 21 *
emilmont 10:3bc89ef62ce7 22 ******************************************************************************/
emilmont 10:3bc89ef62ce7 23 #if defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 10:3bc89ef62ce7 25 #endif
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 28 extern "C" {
emilmont 10:3bc89ef62ce7 29 #endif
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 #ifndef __CORE_CM0PLUS_H_GENERIC
emilmont 10:3bc89ef62ce7 32 #define __CORE_CM0PLUS_H_GENERIC
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 10:3bc89ef62ce7 35 CMSIS violates the following MISRA-C:2004 rules:
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 10:3bc89ef62ce7 38 Function definitions in header files are used to allow 'inlining'.
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 10:3bc89ef62ce7 41 Unions are used for effective representation of core registers.
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 10:3bc89ef62ce7 44 Function-like macros are used to allow more efficient code.
emilmont 10:3bc89ef62ce7 45 */
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47
emilmont 10:3bc89ef62ce7 48 /*******************************************************************************
emilmont 10:3bc89ef62ce7 49 * CMSIS definitions
emilmont 10:3bc89ef62ce7 50 ******************************************************************************/
emilmont 10:3bc89ef62ce7 51 /** \ingroup Cortex-M0+
emilmont 10:3bc89ef62ce7 52 @{
emilmont 10:3bc89ef62ce7 53 */
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 /* CMSIS CM0P definitions */
emilmont 10:3bc89ef62ce7 56 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 10:3bc89ef62ce7 57 #define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
emilmont 10:3bc89ef62ce7 58 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
emilmont 10:3bc89ef62ce7 59 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 67 #define __STATIC_INLINE static __inline
emilmont 10:3bc89ef62ce7 68
emilmont 10:3bc89ef62ce7 69 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 10:3bc89ef62ce7 71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 10:3bc89ef62ce7 72 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 77 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 78
emilmont 10:3bc89ef62ce7 79 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 82 #define __STATIC_INLINE static inline
emilmont 10:3bc89ef62ce7 83
emilmont 10:3bc89ef62ce7 84 #endif
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 10:3bc89ef62ce7 87 */
emilmont 10:3bc89ef62ce7 88 #define __FPU_USED 0
emilmont 10:3bc89ef62ce7 89
emilmont 10:3bc89ef62ce7 90 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 91 #if defined __TARGET_FPU_VFP
emilmont 10:3bc89ef62ce7 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 93 #endif
emilmont 10:3bc89ef62ce7 94
emilmont 10:3bc89ef62ce7 95 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 96 #if defined __ARMVFP__
emilmont 10:3bc89ef62ce7 97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 98 #endif
emilmont 10:3bc89ef62ce7 99
emilmont 10:3bc89ef62ce7 100 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 10:3bc89ef62ce7 102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 103 #endif
emilmont 10:3bc89ef62ce7 104
emilmont 10:3bc89ef62ce7 105 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 106 #if defined __FPU_VFP__
emilmont 10:3bc89ef62ce7 107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 10:3bc89ef62ce7 108 #endif
emilmont 10:3bc89ef62ce7 109 #endif
emilmont 10:3bc89ef62ce7 110
emilmont 10:3bc89ef62ce7 111 #include <stdint.h> /* standard types definitions */
emilmont 10:3bc89ef62ce7 112 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 10:3bc89ef62ce7 113 #include <core_cmFunc.h> /* Core Function Access */
emilmont 10:3bc89ef62ce7 114
emilmont 10:3bc89ef62ce7 115 #endif /* __CORE_CM0PLUS_H_GENERIC */
emilmont 10:3bc89ef62ce7 116
emilmont 10:3bc89ef62ce7 117 #ifndef __CMSIS_GENERIC
emilmont 10:3bc89ef62ce7 118
emilmont 10:3bc89ef62ce7 119 #ifndef __CORE_CM0PLUS_H_DEPENDANT
emilmont 10:3bc89ef62ce7 120 #define __CORE_CM0PLUS_H_DEPENDANT
emilmont 10:3bc89ef62ce7 121
emilmont 10:3bc89ef62ce7 122 /* check device defines and use defaults */
emilmont 10:3bc89ef62ce7 123 #if defined __CHECK_DEVICE_DEFINES
emilmont 10:3bc89ef62ce7 124 #ifndef __CM0PLUS_REV
emilmont 10:3bc89ef62ce7 125 #define __CM0PLUS_REV 0x0000
emilmont 10:3bc89ef62ce7 126 #warning "__CM0PLUS_REV not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 127 #endif
emilmont 10:3bc89ef62ce7 128
emilmont 10:3bc89ef62ce7 129 #ifndef __MPU_PRESENT
emilmont 10:3bc89ef62ce7 130 #define __MPU_PRESENT 0
emilmont 10:3bc89ef62ce7 131 #warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 132 #endif
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134 #ifndef __VTOR_PRESENT
emilmont 10:3bc89ef62ce7 135 #define __VTOR_PRESENT 0
emilmont 10:3bc89ef62ce7 136 #warning "__VTOR_PRESENT not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 137 #endif
emilmont 10:3bc89ef62ce7 138
emilmont 10:3bc89ef62ce7 139 #ifndef __NVIC_PRIO_BITS
emilmont 10:3bc89ef62ce7 140 #define __NVIC_PRIO_BITS 2
emilmont 10:3bc89ef62ce7 141 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 142 #endif
emilmont 10:3bc89ef62ce7 143
emilmont 10:3bc89ef62ce7 144 #ifndef __Vendor_SysTickConfig
emilmont 10:3bc89ef62ce7 145 #define __Vendor_SysTickConfig 0
emilmont 10:3bc89ef62ce7 146 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 10:3bc89ef62ce7 147 #endif
emilmont 10:3bc89ef62ce7 148 #endif
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 /* IO definitions (access restrictions to peripheral registers) */
emilmont 10:3bc89ef62ce7 151 /**
emilmont 10:3bc89ef62ce7 152 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 <strong>IO Type Qualifiers</strong> are used
emilmont 10:3bc89ef62ce7 155 \li to specify the access to peripheral variables.
emilmont 10:3bc89ef62ce7 156 \li for automatic generation of peripheral register debug information.
emilmont 10:3bc89ef62ce7 157 */
emilmont 10:3bc89ef62ce7 158 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 159 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 160 #else
emilmont 10:3bc89ef62ce7 161 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 162 #endif
emilmont 10:3bc89ef62ce7 163 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 10:3bc89ef62ce7 164 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 10:3bc89ef62ce7 165
emilmont 10:3bc89ef62ce7 166 /*@} end of group Cortex-M0+ */
emilmont 10:3bc89ef62ce7 167
emilmont 10:3bc89ef62ce7 168
emilmont 10:3bc89ef62ce7 169
emilmont 10:3bc89ef62ce7 170 /*******************************************************************************
emilmont 10:3bc89ef62ce7 171 * Register Abstraction
emilmont 10:3bc89ef62ce7 172 Core Register contain:
emilmont 10:3bc89ef62ce7 173 - Core Register
emilmont 10:3bc89ef62ce7 174 - Core NVIC Register
emilmont 10:3bc89ef62ce7 175 - Core SCB Register
emilmont 10:3bc89ef62ce7 176 - Core SysTick Register
emilmont 10:3bc89ef62ce7 177 - Core MPU Register
emilmont 10:3bc89ef62ce7 178 ******************************************************************************/
emilmont 10:3bc89ef62ce7 179 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 10:3bc89ef62ce7 180 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 10:3bc89ef62ce7 181 */
emilmont 10:3bc89ef62ce7 182
emilmont 10:3bc89ef62ce7 183 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 184 \defgroup CMSIS_CORE Status and Control Registers
emilmont 10:3bc89ef62ce7 185 \brief Core Register type definitions.
emilmont 10:3bc89ef62ce7 186 @{
emilmont 10:3bc89ef62ce7 187 */
emilmont 10:3bc89ef62ce7 188
emilmont 10:3bc89ef62ce7 189 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 10:3bc89ef62ce7 190 */
emilmont 10:3bc89ef62ce7 191 typedef union
emilmont 10:3bc89ef62ce7 192 {
emilmont 10:3bc89ef62ce7 193 struct
emilmont 10:3bc89ef62ce7 194 {
emilmont 10:3bc89ef62ce7 195 #if (__CORTEX_M != 0x04)
emilmont 10:3bc89ef62ce7 196 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 10:3bc89ef62ce7 197 #else
emilmont 10:3bc89ef62ce7 198 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 10:3bc89ef62ce7 199 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 10:3bc89ef62ce7 200 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 10:3bc89ef62ce7 201 #endif
emilmont 10:3bc89ef62ce7 202 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 10:3bc89ef62ce7 203 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 10:3bc89ef62ce7 204 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 10:3bc89ef62ce7 205 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 10:3bc89ef62ce7 206 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 10:3bc89ef62ce7 207 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 208 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 209 } APSR_Type;
emilmont 10:3bc89ef62ce7 210
emilmont 10:3bc89ef62ce7 211
emilmont 10:3bc89ef62ce7 212 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 10:3bc89ef62ce7 213 */
emilmont 10:3bc89ef62ce7 214 typedef union
emilmont 10:3bc89ef62ce7 215 {
emilmont 10:3bc89ef62ce7 216 struct
emilmont 10:3bc89ef62ce7 217 {
emilmont 10:3bc89ef62ce7 218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 10:3bc89ef62ce7 219 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 10:3bc89ef62ce7 220 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 221 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 222 } IPSR_Type;
emilmont 10:3bc89ef62ce7 223
emilmont 10:3bc89ef62ce7 224
emilmont 10:3bc89ef62ce7 225 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 10:3bc89ef62ce7 226 */
emilmont 10:3bc89ef62ce7 227 typedef union
emilmont 10:3bc89ef62ce7 228 {
emilmont 10:3bc89ef62ce7 229 struct
emilmont 10:3bc89ef62ce7 230 {
emilmont 10:3bc89ef62ce7 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 10:3bc89ef62ce7 232 #if (__CORTEX_M != 0x04)
emilmont 10:3bc89ef62ce7 233 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 10:3bc89ef62ce7 234 #else
emilmont 10:3bc89ef62ce7 235 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 10:3bc89ef62ce7 236 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 10:3bc89ef62ce7 237 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 10:3bc89ef62ce7 238 #endif
emilmont 10:3bc89ef62ce7 239 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 10:3bc89ef62ce7 240 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 10:3bc89ef62ce7 241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 10:3bc89ef62ce7 242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 10:3bc89ef62ce7 243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 10:3bc89ef62ce7 244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 10:3bc89ef62ce7 245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 10:3bc89ef62ce7 246 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 247 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 248 } xPSR_Type;
emilmont 10:3bc89ef62ce7 249
emilmont 10:3bc89ef62ce7 250
emilmont 10:3bc89ef62ce7 251 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 10:3bc89ef62ce7 252 */
emilmont 10:3bc89ef62ce7 253 typedef union
emilmont 10:3bc89ef62ce7 254 {
emilmont 10:3bc89ef62ce7 255 struct
emilmont 10:3bc89ef62ce7 256 {
emilmont 10:3bc89ef62ce7 257 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 10:3bc89ef62ce7 258 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 10:3bc89ef62ce7 259 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 10:3bc89ef62ce7 260 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 10:3bc89ef62ce7 261 } b; /*!< Structure used for bit access */
emilmont 10:3bc89ef62ce7 262 uint32_t w; /*!< Type used for word access */
emilmont 10:3bc89ef62ce7 263 } CONTROL_Type;
emilmont 10:3bc89ef62ce7 264
emilmont 10:3bc89ef62ce7 265 /*@} end of group CMSIS_CORE */
emilmont 10:3bc89ef62ce7 266
emilmont 10:3bc89ef62ce7 267
emilmont 10:3bc89ef62ce7 268 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 269 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 10:3bc89ef62ce7 270 \brief Type definitions for the NVIC Registers
emilmont 10:3bc89ef62ce7 271 @{
emilmont 10:3bc89ef62ce7 272 */
emilmont 10:3bc89ef62ce7 273
emilmont 10:3bc89ef62ce7 274 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 10:3bc89ef62ce7 275 */
emilmont 10:3bc89ef62ce7 276 typedef struct
emilmont 10:3bc89ef62ce7 277 {
emilmont 10:3bc89ef62ce7 278 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 10:3bc89ef62ce7 279 uint32_t RESERVED0[31];
emilmont 10:3bc89ef62ce7 280 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 10:3bc89ef62ce7 281 uint32_t RSERVED1[31];
emilmont 10:3bc89ef62ce7 282 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 10:3bc89ef62ce7 283 uint32_t RESERVED2[31];
emilmont 10:3bc89ef62ce7 284 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 10:3bc89ef62ce7 285 uint32_t RESERVED3[31];
emilmont 10:3bc89ef62ce7 286 uint32_t RESERVED4[64];
emilmont 10:3bc89ef62ce7 287 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 10:3bc89ef62ce7 288 } NVIC_Type;
emilmont 10:3bc89ef62ce7 289
emilmont 10:3bc89ef62ce7 290 /*@} end of group CMSIS_NVIC */
emilmont 10:3bc89ef62ce7 291
emilmont 10:3bc89ef62ce7 292
emilmont 10:3bc89ef62ce7 293 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 294 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 10:3bc89ef62ce7 295 \brief Type definitions for the System Control Block Registers
emilmont 10:3bc89ef62ce7 296 @{
emilmont 10:3bc89ef62ce7 297 */
emilmont 10:3bc89ef62ce7 298
emilmont 10:3bc89ef62ce7 299 /** \brief Structure type to access the System Control Block (SCB).
emilmont 10:3bc89ef62ce7 300 */
emilmont 10:3bc89ef62ce7 301 typedef struct
emilmont 10:3bc89ef62ce7 302 {
emilmont 10:3bc89ef62ce7 303 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 10:3bc89ef62ce7 304 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 10:3bc89ef62ce7 305 #if (__VTOR_PRESENT == 1)
emilmont 10:3bc89ef62ce7 306 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
emilmont 10:3bc89ef62ce7 307 #else
emilmont 10:3bc89ef62ce7 308 uint32_t RESERVED0;
emilmont 10:3bc89ef62ce7 309 #endif
emilmont 10:3bc89ef62ce7 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 10:3bc89ef62ce7 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 10:3bc89ef62ce7 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 10:3bc89ef62ce7 313 uint32_t RESERVED1;
emilmont 10:3bc89ef62ce7 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 10:3bc89ef62ce7 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 10:3bc89ef62ce7 316 } SCB_Type;
emilmont 10:3bc89ef62ce7 317
emilmont 10:3bc89ef62ce7 318 /* SCB CPUID Register Definitions */
emilmont 10:3bc89ef62ce7 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 10:3bc89ef62ce7 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 10:3bc89ef62ce7 321
emilmont 10:3bc89ef62ce7 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 10:3bc89ef62ce7 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 10:3bc89ef62ce7 324
emilmont 10:3bc89ef62ce7 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 10:3bc89ef62ce7 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 10:3bc89ef62ce7 327
emilmont 10:3bc89ef62ce7 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 10:3bc89ef62ce7 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 10:3bc89ef62ce7 330
emilmont 10:3bc89ef62ce7 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 10:3bc89ef62ce7 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 10:3bc89ef62ce7 333
emilmont 10:3bc89ef62ce7 334 /* SCB Interrupt Control State Register Definitions */
emilmont 10:3bc89ef62ce7 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 10:3bc89ef62ce7 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 10:3bc89ef62ce7 337
emilmont 10:3bc89ef62ce7 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 10:3bc89ef62ce7 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 10:3bc89ef62ce7 340
emilmont 10:3bc89ef62ce7 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 10:3bc89ef62ce7 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 10:3bc89ef62ce7 343
emilmont 10:3bc89ef62ce7 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 10:3bc89ef62ce7 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 10:3bc89ef62ce7 346
emilmont 10:3bc89ef62ce7 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 10:3bc89ef62ce7 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 10:3bc89ef62ce7 349
emilmont 10:3bc89ef62ce7 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 10:3bc89ef62ce7 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 10:3bc89ef62ce7 352
emilmont 10:3bc89ef62ce7 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 10:3bc89ef62ce7 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 10:3bc89ef62ce7 355
emilmont 10:3bc89ef62ce7 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 10:3bc89ef62ce7 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 10:3bc89ef62ce7 358
emilmont 10:3bc89ef62ce7 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 10:3bc89ef62ce7 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 10:3bc89ef62ce7 361
emilmont 10:3bc89ef62ce7 362 #if (__VTOR_PRESENT == 1)
emilmont 10:3bc89ef62ce7 363 /* SCB Interrupt Control State Register Definitions */
emilmont 10:3bc89ef62ce7 364 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
emilmont 10:3bc89ef62ce7 365 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
emilmont 10:3bc89ef62ce7 366 #endif
emilmont 10:3bc89ef62ce7 367
emilmont 10:3bc89ef62ce7 368 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 10:3bc89ef62ce7 369 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 10:3bc89ef62ce7 370 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 10:3bc89ef62ce7 371
emilmont 10:3bc89ef62ce7 372 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 10:3bc89ef62ce7 373 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 10:3bc89ef62ce7 374
emilmont 10:3bc89ef62ce7 375 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 10:3bc89ef62ce7 376 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 10:3bc89ef62ce7 377
emilmont 10:3bc89ef62ce7 378 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 10:3bc89ef62ce7 379 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 10:3bc89ef62ce7 380
emilmont 10:3bc89ef62ce7 381 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 10:3bc89ef62ce7 382 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 10:3bc89ef62ce7 383
emilmont 10:3bc89ef62ce7 384 /* SCB System Control Register Definitions */
emilmont 10:3bc89ef62ce7 385 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 10:3bc89ef62ce7 386 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 10:3bc89ef62ce7 389 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 10:3bc89ef62ce7 390
emilmont 10:3bc89ef62ce7 391 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 10:3bc89ef62ce7 392 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 10:3bc89ef62ce7 393
emilmont 10:3bc89ef62ce7 394 /* SCB Configuration Control Register Definitions */
emilmont 10:3bc89ef62ce7 395 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 10:3bc89ef62ce7 396 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 10:3bc89ef62ce7 397
emilmont 10:3bc89ef62ce7 398 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 10:3bc89ef62ce7 399 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 10:3bc89ef62ce7 400
emilmont 10:3bc89ef62ce7 401 /* SCB System Handler Control and State Register Definitions */
emilmont 10:3bc89ef62ce7 402 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 10:3bc89ef62ce7 403 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 10:3bc89ef62ce7 404
emilmont 10:3bc89ef62ce7 405 /*@} end of group CMSIS_SCB */
emilmont 10:3bc89ef62ce7 406
emilmont 10:3bc89ef62ce7 407
emilmont 10:3bc89ef62ce7 408 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 409 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 10:3bc89ef62ce7 410 \brief Type definitions for the System Timer Registers.
emilmont 10:3bc89ef62ce7 411 @{
emilmont 10:3bc89ef62ce7 412 */
emilmont 10:3bc89ef62ce7 413
emilmont 10:3bc89ef62ce7 414 /** \brief Structure type to access the System Timer (SysTick).
emilmont 10:3bc89ef62ce7 415 */
emilmont 10:3bc89ef62ce7 416 typedef struct
emilmont 10:3bc89ef62ce7 417 {
emilmont 10:3bc89ef62ce7 418 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 10:3bc89ef62ce7 419 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 10:3bc89ef62ce7 420 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 10:3bc89ef62ce7 421 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 10:3bc89ef62ce7 422 } SysTick_Type;
emilmont 10:3bc89ef62ce7 423
emilmont 10:3bc89ef62ce7 424 /* SysTick Control / Status Register Definitions */
emilmont 10:3bc89ef62ce7 425 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 10:3bc89ef62ce7 426 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 10:3bc89ef62ce7 427
emilmont 10:3bc89ef62ce7 428 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 10:3bc89ef62ce7 429 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 10:3bc89ef62ce7 430
emilmont 10:3bc89ef62ce7 431 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 10:3bc89ef62ce7 432 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 10:3bc89ef62ce7 433
emilmont 10:3bc89ef62ce7 434 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 10:3bc89ef62ce7 435 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 10:3bc89ef62ce7 436
emilmont 10:3bc89ef62ce7 437 /* SysTick Reload Register Definitions */
emilmont 10:3bc89ef62ce7 438 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 10:3bc89ef62ce7 439 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 10:3bc89ef62ce7 440
emilmont 10:3bc89ef62ce7 441 /* SysTick Current Register Definitions */
emilmont 10:3bc89ef62ce7 442 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 10:3bc89ef62ce7 443 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 10:3bc89ef62ce7 444
emilmont 10:3bc89ef62ce7 445 /* SysTick Calibration Register Definitions */
emilmont 10:3bc89ef62ce7 446 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 10:3bc89ef62ce7 447 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 10:3bc89ef62ce7 448
emilmont 10:3bc89ef62ce7 449 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 10:3bc89ef62ce7 450 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 10:3bc89ef62ce7 451
emilmont 10:3bc89ef62ce7 452 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 10:3bc89ef62ce7 453 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 10:3bc89ef62ce7 454
emilmont 10:3bc89ef62ce7 455 /*@} end of group CMSIS_SysTick */
emilmont 10:3bc89ef62ce7 456
emilmont 10:3bc89ef62ce7 457 #if (__MPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 458 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 459 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont 10:3bc89ef62ce7 460 \brief Type definitions for the Memory Protection Unit (MPU)
emilmont 10:3bc89ef62ce7 461 @{
emilmont 10:3bc89ef62ce7 462 */
emilmont 10:3bc89ef62ce7 463
emilmont 10:3bc89ef62ce7 464 /** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont 10:3bc89ef62ce7 465 */
emilmont 10:3bc89ef62ce7 466 typedef struct
emilmont 10:3bc89ef62ce7 467 {
emilmont 10:3bc89ef62ce7 468 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
emilmont 10:3bc89ef62ce7 469 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
emilmont 10:3bc89ef62ce7 470 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
emilmont 10:3bc89ef62ce7 471 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
emilmont 10:3bc89ef62ce7 472 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 473 } MPU_Type;
emilmont 10:3bc89ef62ce7 474
emilmont 10:3bc89ef62ce7 475 /* MPU Type Register */
emilmont 10:3bc89ef62ce7 476 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
emilmont 10:3bc89ef62ce7 477 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
emilmont 10:3bc89ef62ce7 478
emilmont 10:3bc89ef62ce7 479 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
emilmont 10:3bc89ef62ce7 480 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
emilmont 10:3bc89ef62ce7 481
emilmont 10:3bc89ef62ce7 482 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
emilmont 10:3bc89ef62ce7 483 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
emilmont 10:3bc89ef62ce7 484
emilmont 10:3bc89ef62ce7 485 /* MPU Control Register */
emilmont 10:3bc89ef62ce7 486 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
emilmont 10:3bc89ef62ce7 487 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
emilmont 10:3bc89ef62ce7 488
emilmont 10:3bc89ef62ce7 489 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
emilmont 10:3bc89ef62ce7 490 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
emilmont 10:3bc89ef62ce7 491
emilmont 10:3bc89ef62ce7 492 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
emilmont 10:3bc89ef62ce7 493 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
emilmont 10:3bc89ef62ce7 494
emilmont 10:3bc89ef62ce7 495 /* MPU Region Number Register */
emilmont 10:3bc89ef62ce7 496 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
emilmont 10:3bc89ef62ce7 497 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
emilmont 10:3bc89ef62ce7 498
emilmont 10:3bc89ef62ce7 499 /* MPU Region Base Address Register */
emilmont 10:3bc89ef62ce7 500 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
emilmont 10:3bc89ef62ce7 501 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
emilmont 10:3bc89ef62ce7 502
emilmont 10:3bc89ef62ce7 503 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
emilmont 10:3bc89ef62ce7 504 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
emilmont 10:3bc89ef62ce7 505
emilmont 10:3bc89ef62ce7 506 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
emilmont 10:3bc89ef62ce7 507 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
emilmont 10:3bc89ef62ce7 508
emilmont 10:3bc89ef62ce7 509 /* MPU Region Attribute and Size Register */
emilmont 10:3bc89ef62ce7 510 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
emilmont 10:3bc89ef62ce7 511 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
emilmont 10:3bc89ef62ce7 512
emilmont 10:3bc89ef62ce7 513 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
emilmont 10:3bc89ef62ce7 514 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
emilmont 10:3bc89ef62ce7 515
emilmont 10:3bc89ef62ce7 516 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
emilmont 10:3bc89ef62ce7 517 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
emilmont 10:3bc89ef62ce7 518
emilmont 10:3bc89ef62ce7 519 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
emilmont 10:3bc89ef62ce7 520 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
emilmont 10:3bc89ef62ce7 521
emilmont 10:3bc89ef62ce7 522 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
emilmont 10:3bc89ef62ce7 523 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
emilmont 10:3bc89ef62ce7 524
emilmont 10:3bc89ef62ce7 525 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
emilmont 10:3bc89ef62ce7 526 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
emilmont 10:3bc89ef62ce7 527
emilmont 10:3bc89ef62ce7 528 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
emilmont 10:3bc89ef62ce7 529 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
emilmont 10:3bc89ef62ce7 530
emilmont 10:3bc89ef62ce7 531 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
emilmont 10:3bc89ef62ce7 532 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
emilmont 10:3bc89ef62ce7 533
emilmont 10:3bc89ef62ce7 534 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
emilmont 10:3bc89ef62ce7 535 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
emilmont 10:3bc89ef62ce7 536
emilmont 10:3bc89ef62ce7 537 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
emilmont 10:3bc89ef62ce7 538 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
emilmont 10:3bc89ef62ce7 539
emilmont 10:3bc89ef62ce7 540 /*@} end of group CMSIS_MPU */
emilmont 10:3bc89ef62ce7 541 #endif
emilmont 10:3bc89ef62ce7 542
emilmont 10:3bc89ef62ce7 543
emilmont 10:3bc89ef62ce7 544 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 545 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 10:3bc89ef62ce7 546 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 10:3bc89ef62ce7 547 are only accessible over DAP and not via processor. Therefore
emilmont 10:3bc89ef62ce7 548 they are not covered by the Cortex-M0 header file.
emilmont 10:3bc89ef62ce7 549 @{
emilmont 10:3bc89ef62ce7 550 */
emilmont 10:3bc89ef62ce7 551 /*@} end of group CMSIS_CoreDebug */
emilmont 10:3bc89ef62ce7 552
emilmont 10:3bc89ef62ce7 553
emilmont 10:3bc89ef62ce7 554 /** \ingroup CMSIS_core_register
emilmont 10:3bc89ef62ce7 555 \defgroup CMSIS_core_base Core Definitions
emilmont 10:3bc89ef62ce7 556 \brief Definitions for base addresses, unions, and structures.
emilmont 10:3bc89ef62ce7 557 @{
emilmont 10:3bc89ef62ce7 558 */
emilmont 10:3bc89ef62ce7 559
emilmont 10:3bc89ef62ce7 560 /* Memory mapping of Cortex-M0+ Hardware */
emilmont 10:3bc89ef62ce7 561 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 10:3bc89ef62ce7 562 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 10:3bc89ef62ce7 563 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 10:3bc89ef62ce7 564 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 10:3bc89ef62ce7 565
emilmont 10:3bc89ef62ce7 566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 10:3bc89ef62ce7 567 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 10:3bc89ef62ce7 568 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 10:3bc89ef62ce7 569
emilmont 10:3bc89ef62ce7 570 #if (__MPU_PRESENT == 1)
emilmont 10:3bc89ef62ce7 571 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
emilmont 10:3bc89ef62ce7 572 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
emilmont 10:3bc89ef62ce7 573 #endif
emilmont 10:3bc89ef62ce7 574
emilmont 10:3bc89ef62ce7 575 /*@} */
emilmont 10:3bc89ef62ce7 576
emilmont 10:3bc89ef62ce7 577
emilmont 10:3bc89ef62ce7 578
emilmont 10:3bc89ef62ce7 579 /*******************************************************************************
emilmont 10:3bc89ef62ce7 580 * Hardware Abstraction Layer
emilmont 10:3bc89ef62ce7 581 Core Function Interface contains:
emilmont 10:3bc89ef62ce7 582 - Core NVIC Functions
emilmont 10:3bc89ef62ce7 583 - Core SysTick Functions
emilmont 10:3bc89ef62ce7 584 - Core Register Access Functions
emilmont 10:3bc89ef62ce7 585 ******************************************************************************/
emilmont 10:3bc89ef62ce7 586 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 10:3bc89ef62ce7 587 */
emilmont 10:3bc89ef62ce7 588
emilmont 10:3bc89ef62ce7 589
emilmont 10:3bc89ef62ce7 590
emilmont 10:3bc89ef62ce7 591 /* ########################## NVIC functions #################################### */
emilmont 10:3bc89ef62ce7 592 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 593 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 10:3bc89ef62ce7 594 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 10:3bc89ef62ce7 595 @{
emilmont 10:3bc89ef62ce7 596 */
emilmont 10:3bc89ef62ce7 597
emilmont 10:3bc89ef62ce7 598 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 10:3bc89ef62ce7 599 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 10:3bc89ef62ce7 600 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 10:3bc89ef62ce7 601 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 10:3bc89ef62ce7 602 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 10:3bc89ef62ce7 603
emilmont 10:3bc89ef62ce7 604
emilmont 10:3bc89ef62ce7 605 /** \brief Enable External Interrupt
emilmont 10:3bc89ef62ce7 606
emilmont 10:3bc89ef62ce7 607 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 608
emilmont 10:3bc89ef62ce7 609 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 610 */
emilmont 10:3bc89ef62ce7 611 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 612 {
emilmont 10:3bc89ef62ce7 613 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 10:3bc89ef62ce7 614 }
emilmont 10:3bc89ef62ce7 615
emilmont 10:3bc89ef62ce7 616
emilmont 10:3bc89ef62ce7 617 /** \brief Disable External Interrupt
emilmont 10:3bc89ef62ce7 618
emilmont 10:3bc89ef62ce7 619 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 620
emilmont 10:3bc89ef62ce7 621 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 622 */
emilmont 10:3bc89ef62ce7 623 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 624 {
emilmont 10:3bc89ef62ce7 625 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 10:3bc89ef62ce7 626 }
emilmont 10:3bc89ef62ce7 627
emilmont 10:3bc89ef62ce7 628
emilmont 10:3bc89ef62ce7 629 /** \brief Get Pending Interrupt
emilmont 10:3bc89ef62ce7 630
emilmont 10:3bc89ef62ce7 631 The function reads the pending register in the NVIC and returns the pending bit
emilmont 10:3bc89ef62ce7 632 for the specified interrupt.
emilmont 10:3bc89ef62ce7 633
emilmont 10:3bc89ef62ce7 634 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 635
emilmont 10:3bc89ef62ce7 636 \return 0 Interrupt status is not pending.
emilmont 10:3bc89ef62ce7 637 \return 1 Interrupt status is pending.
emilmont 10:3bc89ef62ce7 638 */
emilmont 10:3bc89ef62ce7 639 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 640 {
emilmont 10:3bc89ef62ce7 641 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 10:3bc89ef62ce7 642 }
emilmont 10:3bc89ef62ce7 643
emilmont 10:3bc89ef62ce7 644
emilmont 10:3bc89ef62ce7 645 /** \brief Set Pending Interrupt
emilmont 10:3bc89ef62ce7 646
emilmont 10:3bc89ef62ce7 647 The function sets the pending bit of an external interrupt.
emilmont 10:3bc89ef62ce7 648
emilmont 10:3bc89ef62ce7 649 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 650 */
emilmont 10:3bc89ef62ce7 651 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 652 {
emilmont 10:3bc89ef62ce7 653 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 10:3bc89ef62ce7 654 }
emilmont 10:3bc89ef62ce7 655
emilmont 10:3bc89ef62ce7 656
emilmont 10:3bc89ef62ce7 657 /** \brief Clear Pending Interrupt
emilmont 10:3bc89ef62ce7 658
emilmont 10:3bc89ef62ce7 659 The function clears the pending bit of an external interrupt.
emilmont 10:3bc89ef62ce7 660
emilmont 10:3bc89ef62ce7 661 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 10:3bc89ef62ce7 662 */
emilmont 10:3bc89ef62ce7 663 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 664 {
emilmont 10:3bc89ef62ce7 665 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 10:3bc89ef62ce7 666 }
emilmont 10:3bc89ef62ce7 667
emilmont 10:3bc89ef62ce7 668
emilmont 10:3bc89ef62ce7 669 /** \brief Set Interrupt Priority
emilmont 10:3bc89ef62ce7 670
emilmont 10:3bc89ef62ce7 671 The function sets the priority of an interrupt.
emilmont 10:3bc89ef62ce7 672
emilmont 10:3bc89ef62ce7 673 \note The priority cannot be set for every core interrupt.
emilmont 10:3bc89ef62ce7 674
emilmont 10:3bc89ef62ce7 675 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 676 \param [in] priority Priority to set.
emilmont 10:3bc89ef62ce7 677 */
emilmont 10:3bc89ef62ce7 678 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 10:3bc89ef62ce7 679 {
emilmont 10:3bc89ef62ce7 680 if(IRQn < 0) {
emilmont 10:3bc89ef62ce7 681 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 10:3bc89ef62ce7 682 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 10:3bc89ef62ce7 683 else {
emilmont 10:3bc89ef62ce7 684 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 10:3bc89ef62ce7 685 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 10:3bc89ef62ce7 686 }
emilmont 10:3bc89ef62ce7 687
emilmont 10:3bc89ef62ce7 688
emilmont 10:3bc89ef62ce7 689 /** \brief Get Interrupt Priority
emilmont 10:3bc89ef62ce7 690
emilmont 10:3bc89ef62ce7 691 The function reads the priority of an interrupt. The interrupt
emilmont 10:3bc89ef62ce7 692 number can be positive to specify an external (device specific)
emilmont 10:3bc89ef62ce7 693 interrupt, or negative to specify an internal (core) interrupt.
emilmont 10:3bc89ef62ce7 694
emilmont 10:3bc89ef62ce7 695
emilmont 10:3bc89ef62ce7 696 \param [in] IRQn Interrupt number.
emilmont 10:3bc89ef62ce7 697 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 10:3bc89ef62ce7 698 priority bits of the microcontroller.
emilmont 10:3bc89ef62ce7 699 */
emilmont 10:3bc89ef62ce7 700 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 701 {
emilmont 10:3bc89ef62ce7 702
emilmont 10:3bc89ef62ce7 703 if(IRQn < 0) {
emilmont 10:3bc89ef62ce7 704 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 10:3bc89ef62ce7 705 else {
emilmont 10:3bc89ef62ce7 706 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 10:3bc89ef62ce7 707 }
emilmont 10:3bc89ef62ce7 708
emilmont 10:3bc89ef62ce7 709
emilmont 10:3bc89ef62ce7 710 /** \brief System Reset
emilmont 10:3bc89ef62ce7 711
emilmont 10:3bc89ef62ce7 712 The function initiates a system reset request to reset the MCU.
emilmont 10:3bc89ef62ce7 713 */
emilmont 10:3bc89ef62ce7 714 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 10:3bc89ef62ce7 715 {
emilmont 10:3bc89ef62ce7 716 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 10:3bc89ef62ce7 717 buffered write are completed before reset */
emilmont 10:3bc89ef62ce7 718 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 10:3bc89ef62ce7 719 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 10:3bc89ef62ce7 720 __DSB(); /* Ensure completion of memory access */
emilmont 10:3bc89ef62ce7 721 while(1); /* wait until reset */
emilmont 10:3bc89ef62ce7 722 }
emilmont 10:3bc89ef62ce7 723
emilmont 10:3bc89ef62ce7 724 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 10:3bc89ef62ce7 725
emilmont 10:3bc89ef62ce7 726
emilmont 10:3bc89ef62ce7 727
emilmont 10:3bc89ef62ce7 728 /* ################################## SysTick function ############################################ */
emilmont 10:3bc89ef62ce7 729 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 10:3bc89ef62ce7 730 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 10:3bc89ef62ce7 731 \brief Functions that configure the System.
emilmont 10:3bc89ef62ce7 732 @{
emilmont 10:3bc89ef62ce7 733 */
emilmont 10:3bc89ef62ce7 734
emilmont 10:3bc89ef62ce7 735 #if (__Vendor_SysTickConfig == 0)
emilmont 10:3bc89ef62ce7 736
emilmont 10:3bc89ef62ce7 737 /** \brief System Tick Configuration
emilmont 10:3bc89ef62ce7 738
emilmont 10:3bc89ef62ce7 739 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 10:3bc89ef62ce7 740 Counter is in free running mode to generate periodic interrupts.
emilmont 10:3bc89ef62ce7 741
emilmont 10:3bc89ef62ce7 742 \param [in] ticks Number of ticks between two interrupts.
emilmont 10:3bc89ef62ce7 743
emilmont 10:3bc89ef62ce7 744 \return 0 Function succeeded.
emilmont 10:3bc89ef62ce7 745 \return 1 Function failed.
emilmont 10:3bc89ef62ce7 746
emilmont 10:3bc89ef62ce7 747 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 10:3bc89ef62ce7 748 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 10:3bc89ef62ce7 749 must contain a vendor-specific implementation of this function.
emilmont 10:3bc89ef62ce7 750
emilmont 10:3bc89ef62ce7 751 */
emilmont 10:3bc89ef62ce7 752 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 10:3bc89ef62ce7 753 {
emilmont 10:3bc89ef62ce7 754 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 10:3bc89ef62ce7 755
emilmont 10:3bc89ef62ce7 756 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 10:3bc89ef62ce7 757 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 10:3bc89ef62ce7 758 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 10:3bc89ef62ce7 759 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 10:3bc89ef62ce7 760 SysTick_CTRL_TICKINT_Msk |
emilmont 10:3bc89ef62ce7 761 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 10:3bc89ef62ce7 762 return (0); /* Function successful */
emilmont 10:3bc89ef62ce7 763 }
emilmont 10:3bc89ef62ce7 764
emilmont 10:3bc89ef62ce7 765 #endif
emilmont 10:3bc89ef62ce7 766
emilmont 10:3bc89ef62ce7 767 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 10:3bc89ef62ce7 768
emilmont 10:3bc89ef62ce7 769
emilmont 10:3bc89ef62ce7 770
emilmont 10:3bc89ef62ce7 771
emilmont 10:3bc89ef62ce7 772 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
emilmont 10:3bc89ef62ce7 773
emilmont 10:3bc89ef62ce7 774 #endif /* __CMSIS_GENERIC */
emilmont 10:3bc89ef62ce7 775
emilmont 10:3bc89ef62ce7 776 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 777 }
emilmont 10:3bc89ef62ce7 778 #endif