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Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

vendor/Freescale/KL25Z/cmsis/ARM/startup_MKL25Z4.s@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 ;/*****************************************************************************
emilmont 10:3bc89ef62ce7 2 ; * @file: startup_MKL25Z4.s
emilmont 10:3bc89ef62ce7 3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
emilmont 10:3bc89ef62ce7 4 ; * MKL25Z4
emilmont 10:3bc89ef62ce7 5 ; * @version: 1.1
emilmont 10:3bc89ef62ce7 6 ; * @date: 2012-6-21
emilmont 10:3bc89ef62ce7 7 ; *
emilmont 10:3bc89ef62ce7 8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
emilmont 10:3bc89ef62ce7 9 ;*
emilmont 10:3bc89ef62ce7 10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
emilmont 10:3bc89ef62ce7 11 ; *
emilmont 10:3bc89ef62ce7 12 ; *****************************************************************************/
emilmont 10:3bc89ef62ce7 13
emilmont 10:3bc89ef62ce7 14
emilmont 10:3bc89ef62ce7 15 __initial_sp EQU 0x20003000 ; Top of RAM
emilmont 10:3bc89ef62ce7 16
emilmont 10:3bc89ef62ce7 17 PRESERVE8
emilmont 10:3bc89ef62ce7 18 THUMB
emilmont 10:3bc89ef62ce7 19
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 ; Vector Table Mapped to Address 0 at Reset
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 AREA RESET, DATA, READONLY
emilmont 10:3bc89ef62ce7 24 EXPORT __Vectors
emilmont 10:3bc89ef62ce7 25 EXPORT __Vectors_End
emilmont 10:3bc89ef62ce7 26 EXPORT __Vectors_Size
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 __Vectors DCD __initial_sp ; Top of Stack
emilmont 10:3bc89ef62ce7 29 DCD Reset_Handler ; Reset Handler
emilmont 10:3bc89ef62ce7 30 DCD NMI_Handler ; NMI Handler
emilmont 10:3bc89ef62ce7 31 DCD HardFault_Handler ; Hard Fault Handler
emilmont 10:3bc89ef62ce7 32 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 33 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 34 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 35 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 36 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 37 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 38 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 39 DCD SVC_Handler ; SVCall Handler
emilmont 10:3bc89ef62ce7 40 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 41 DCD 0 ; Reserved
emilmont 10:3bc89ef62ce7 42 DCD PendSV_Handler ; PendSV Handler
emilmont 10:3bc89ef62ce7 43 DCD SysTick_Handler ; SysTick Handler
emilmont 10:3bc89ef62ce7 44
emilmont 10:3bc89ef62ce7 45 ; External Interrupts
emilmont 10:3bc89ef62ce7 46 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
emilmont 10:3bc89ef62ce7 47 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
emilmont 10:3bc89ef62ce7 48 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
emilmont 10:3bc89ef62ce7 49 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
emilmont 10:3bc89ef62ce7 50 DCD Reserved20_IRQHandler ; Reserved interrupt 20
emilmont 10:3bc89ef62ce7 51 DCD FTFA_IRQHandler ; FTFA interrupt
emilmont 10:3bc89ef62ce7 52 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
emilmont 10:3bc89ef62ce7 53 DCD LLW_IRQHandler ; Low Leakage Wakeup
emilmont 10:3bc89ef62ce7 54 DCD I2C0_IRQHandler ; I2C0 interrupt
emilmont 10:3bc89ef62ce7 55 DCD I2C1_IRQHandler ; I2C0 interrupt 25
emilmont 10:3bc89ef62ce7 56 DCD SPI0_IRQHandler ; SPI0 interrupt
emilmont 10:3bc89ef62ce7 57 DCD SPI1_IRQHandler ; SPI1 interrupt
emilmont 10:3bc89ef62ce7 58 DCD UART0_IRQHandler ; UART0 status/error interrupt
emilmont 10:3bc89ef62ce7 59 DCD UART1_IRQHandler ; UART1 status/error interrupt
emilmont 10:3bc89ef62ce7 60 DCD UART2_IRQHandler ; UART2 status/error interrupt
emilmont 10:3bc89ef62ce7 61 DCD ADC0_IRQHandler ; ADC0 interrupt
emilmont 10:3bc89ef62ce7 62 DCD CMP0_IRQHandler ; CMP0 interrupt
emilmont 10:3bc89ef62ce7 63 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
emilmont 10:3bc89ef62ce7 64 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
emilmont 10:3bc89ef62ce7 65 DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
emilmont 10:3bc89ef62ce7 66 DCD RTC_IRQHandler ; RTC interrupt
emilmont 10:3bc89ef62ce7 67 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
emilmont 10:3bc89ef62ce7 68 DCD PIT_IRQHandler ; PIT timer interrupt
emilmont 10:3bc89ef62ce7 69 DCD Reserved39_IRQHandler ; Reserved interrupt 39
emilmont 10:3bc89ef62ce7 70 DCD USB0_IRQHandler ; USB0 interrupt
emilmont 10:3bc89ef62ce7 71 DCD DAC0_IRQHandler ; DAC interrupt
emilmont 10:3bc89ef62ce7 72 DCD TSI0_IRQHandler ; TSI0 interrupt
emilmont 10:3bc89ef62ce7 73 DCD MCG_IRQHandler ; MCG interrupt
emilmont 10:3bc89ef62ce7 74 DCD LPTimer_IRQHandler ; LPTimer interrupt
emilmont 10:3bc89ef62ce7 75 DCD Reserved45_IRQHandler ; Reserved interrupt 45
emilmont 10:3bc89ef62ce7 76 DCD PORTA_IRQHandler ; Port A interrupt
emilmont 10:3bc89ef62ce7 77 DCD PORTD_IRQHandler ; Port D interrupt
emilmont 10:3bc89ef62ce7 78 __Vectors_End
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 __Vectors_Size EQU __Vectors_End - __Vectors
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 ; <h> Flash Configuration
emilmont 10:3bc89ef62ce7 83 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
emilmont 10:3bc89ef62ce7 84 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
emilmont 10:3bc89ef62ce7 85 ; <h> Backdoor Comparison Key
emilmont 10:3bc89ef62ce7 86 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 87 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 88 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 89 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 90 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 91 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 92 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 93 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
emilmont 10:3bc89ef62ce7 94 BackDoorK0 EQU 0xFF
emilmont 10:3bc89ef62ce7 95 BackDoorK1 EQU 0xFF
emilmont 10:3bc89ef62ce7 96 BackDoorK2 EQU 0xFF
emilmont 10:3bc89ef62ce7 97 BackDoorK3 EQU 0xFF
emilmont 10:3bc89ef62ce7 98 BackDoorK4 EQU 0xFF
emilmont 10:3bc89ef62ce7 99 BackDoorK5 EQU 0xFF
emilmont 10:3bc89ef62ce7 100 BackDoorK6 EQU 0xFF
emilmont 10:3bc89ef62ce7 101 BackDoorK7 EQU 0xFF
emilmont 10:3bc89ef62ce7 102 ; </h>
emilmont 10:3bc89ef62ce7 103 ; <h> Program flash protection bytes (FPROT)
emilmont 10:3bc89ef62ce7 104 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
emilmont 10:3bc89ef62ce7 105 ; <i> Each bit protects a 1/32 region of the program flash memory.
emilmont 10:3bc89ef62ce7 106 ; <h> FPROT0
emilmont 10:3bc89ef62ce7 107 ; <i> Program flash protection bytes
emilmont 10:3bc89ef62ce7 108 ; <i> 1/32 - 8/32 region
emilmont 10:3bc89ef62ce7 109 ; <o.0> FPROT0.0
emilmont 10:3bc89ef62ce7 110 ; <o.1> FPROT0.1
emilmont 10:3bc89ef62ce7 111 ; <o.2> FPROT0.2
emilmont 10:3bc89ef62ce7 112 ; <o.3> FPROT0.3
emilmont 10:3bc89ef62ce7 113 ; <o.4> FPROT0.4
emilmont 10:3bc89ef62ce7 114 ; <o.5> FPROT0.5
emilmont 10:3bc89ef62ce7 115 ; <o.6> FPROT0.6
emilmont 10:3bc89ef62ce7 116 ; <o.7> FPROT0.7
emilmont 10:3bc89ef62ce7 117 nFPROT0 EQU 0x00
emilmont 10:3bc89ef62ce7 118 FPROT0 EQU nFPROT0:EOR:0xFF
emilmont 10:3bc89ef62ce7 119 ; </h>
emilmont 10:3bc89ef62ce7 120 ; <h> FPROT1
emilmont 10:3bc89ef62ce7 121 ; <i> Program Flash Region Protect Register 1
emilmont 10:3bc89ef62ce7 122 ; <i> 9/32 - 16/32 region
emilmont 10:3bc89ef62ce7 123 ; <o.0> FPROT1.0
emilmont 10:3bc89ef62ce7 124 ; <o.1> FPROT1.1
emilmont 10:3bc89ef62ce7 125 ; <o.2> FPROT1.2
emilmont 10:3bc89ef62ce7 126 ; <o.3> FPROT1.3
emilmont 10:3bc89ef62ce7 127 ; <o.4> FPROT1.4
emilmont 10:3bc89ef62ce7 128 ; <o.5> FPROT1.5
emilmont 10:3bc89ef62ce7 129 ; <o.6> FPROT1.6
emilmont 10:3bc89ef62ce7 130 ; <o.7> FPROT1.7
emilmont 10:3bc89ef62ce7 131 nFPROT1 EQU 0x00
emilmont 10:3bc89ef62ce7 132 FPROT1 EQU nFPROT1:EOR:0xFF
emilmont 10:3bc89ef62ce7 133 ; </h>
emilmont 10:3bc89ef62ce7 134 ; <h> FPROT2
emilmont 10:3bc89ef62ce7 135 ; <i> Program Flash Region Protect Register 2
emilmont 10:3bc89ef62ce7 136 ; <i> 17/32 - 24/32 region
emilmont 10:3bc89ef62ce7 137 ; <o.0> FPROT2.0
emilmont 10:3bc89ef62ce7 138 ; <o.1> FPROT2.1
emilmont 10:3bc89ef62ce7 139 ; <o.2> FPROT2.2
emilmont 10:3bc89ef62ce7 140 ; <o.3> FPROT2.3
emilmont 10:3bc89ef62ce7 141 ; <o.4> FPROT2.4
emilmont 10:3bc89ef62ce7 142 ; <o.5> FPROT2.5
emilmont 10:3bc89ef62ce7 143 ; <o.6> FPROT2.6
emilmont 10:3bc89ef62ce7 144 ; <o.7> FPROT2.7
emilmont 10:3bc89ef62ce7 145 nFPROT2 EQU 0x00
emilmont 10:3bc89ef62ce7 146 FPROT2 EQU nFPROT2:EOR:0xFF
emilmont 10:3bc89ef62ce7 147 ; </h>
emilmont 10:3bc89ef62ce7 148 ; <h> FPROT3
emilmont 10:3bc89ef62ce7 149 ; <i> Program Flash Region Protect Register 3
emilmont 10:3bc89ef62ce7 150 ; <i> 25/32 - 32/32 region
emilmont 10:3bc89ef62ce7 151 ; <o.0> FPROT3.0
emilmont 10:3bc89ef62ce7 152 ; <o.1> FPROT3.1
emilmont 10:3bc89ef62ce7 153 ; <o.2> FPROT3.2
emilmont 10:3bc89ef62ce7 154 ; <o.3> FPROT3.3
emilmont 10:3bc89ef62ce7 155 ; <o.4> FPROT3.4
emilmont 10:3bc89ef62ce7 156 ; <o.5> FPROT3.5
emilmont 10:3bc89ef62ce7 157 ; <o.6> FPROT3.6
emilmont 10:3bc89ef62ce7 158 ; <o.7> FPROT3.7
emilmont 10:3bc89ef62ce7 159 nFPROT3 EQU 0x00
emilmont 10:3bc89ef62ce7 160 FPROT3 EQU nFPROT3:EOR:0xFF
emilmont 10:3bc89ef62ce7 161 ; </h>
emilmont 10:3bc89ef62ce7 162 ; </h>
emilmont 10:3bc89ef62ce7 163 ; </h>
emilmont 10:3bc89ef62ce7 164 ; <h> Flash nonvolatile option byte (FOPT)
emilmont 10:3bc89ef62ce7 165 ; <i> Allows the user to customize the operation of the MCU at boot time.
emilmont 10:3bc89ef62ce7 166 ; <o.0> LPBOOT0
emilmont 10:3bc89ef62ce7 167 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
emilmont 10:3bc89ef62ce7 168 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
emilmont 10:3bc89ef62ce7 169 ; <o.4> LPBOOT1
emilmont 10:3bc89ef62ce7 170 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
emilmont 10:3bc89ef62ce7 171 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
emilmont 10:3bc89ef62ce7 172 ; <o.2> NMI_DIS
emilmont 10:3bc89ef62ce7 173 ; <0=> NMI interrupts are always blocked
emilmont 10:3bc89ef62ce7 174 ; <1=> NMI pin/interrupts reset default to enabled
emilmont 10:3bc89ef62ce7 175 ; <o.3> RESET_PIN_CFG
emilmont 10:3bc89ef62ce7 176 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
emilmont 10:3bc89ef62ce7 177 ; <1=> RESET pin is dedicated
emilmont 10:3bc89ef62ce7 178 ; <o.3> FAST_INIT
emilmont 10:3bc89ef62ce7 179 ; <0=> Slower initialization
emilmont 10:3bc89ef62ce7 180 ; <1=> Fast Initialization
emilmont 10:3bc89ef62ce7 181 FOPT EQU 0xFF
emilmont 10:3bc89ef62ce7 182 ; </h>
emilmont 10:3bc89ef62ce7 183 ; <h> Flash security byte (FSEC)
emilmont 10:3bc89ef62ce7 184 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
emilmont 10:3bc89ef62ce7 185 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
emilmont 10:3bc89ef62ce7 186 ; <o.0..1> SEC
emilmont 10:3bc89ef62ce7 187 ; <2=> MCU security status is unsecure
emilmont 10:3bc89ef62ce7 188 ; <3=> MCU security status is secure
emilmont 10:3bc89ef62ce7 189 ; <i> Flash Security
emilmont 10:3bc89ef62ce7 190 ; <i> This bits define the security state of the MCU.
emilmont 10:3bc89ef62ce7 191 ; <o.2..3> FSLACC
emilmont 10:3bc89ef62ce7 192 ; <2=> Freescale factory access denied
emilmont 10:3bc89ef62ce7 193 ; <3=> Freescale factory access granted
emilmont 10:3bc89ef62ce7 194 ; <i> Freescale Failure Analysis Access Code
emilmont 10:3bc89ef62ce7 195 ; <i> This bits define the security state of the MCU.
emilmont 10:3bc89ef62ce7 196 ; <o.4..5> MEEN
emilmont 10:3bc89ef62ce7 197 ; <2=> Mass erase is disabled
emilmont 10:3bc89ef62ce7 198 ; <3=> Mass erase is enabled
emilmont 10:3bc89ef62ce7 199 ; <i> Mass Erase Enable Bits
emilmont 10:3bc89ef62ce7 200 ; <i> Enables and disables mass erase capability of the FTFL module
emilmont 10:3bc89ef62ce7 201 ; <o.6..7> KEYEN
emilmont 10:3bc89ef62ce7 202 ; <2=> Backdoor key access enabled
emilmont 10:3bc89ef62ce7 203 ; <3=> Backdoor key access disabled
emilmont 10:3bc89ef62ce7 204 ; <i> Backdoor key Security Enable
emilmont 10:3bc89ef62ce7 205 ; <i> These bits enable and disable backdoor key access to the FTFL module.
emilmont 10:3bc89ef62ce7 206 FSEC EQU 0xFE
emilmont 10:3bc89ef62ce7 207 ; </h>
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 IF :LNOT::DEF:RAM_TARGET
emilmont 10:3bc89ef62ce7 210 AREA |.ARM.__at_0x400|, CODE, READONLY
emilmont 10:3bc89ef62ce7 211 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
emilmont 10:3bc89ef62ce7 212 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
emilmont 10:3bc89ef62ce7 213 DCB FPROT0, FPROT1, FPROT2, FPROT3
emilmont 10:3bc89ef62ce7 214 DCB FSEC, FOPT, 0xFF, 0xFF
emilmont 10:3bc89ef62ce7 215 ENDIF
emilmont 10:3bc89ef62ce7 216
emilmont 10:3bc89ef62ce7 217 AREA |.text|, CODE, READONLY
emilmont 10:3bc89ef62ce7 218
emilmont 10:3bc89ef62ce7 219
emilmont 10:3bc89ef62ce7 220 ; Reset Handler
emilmont 10:3bc89ef62ce7 221
emilmont 10:3bc89ef62ce7 222 Reset_Handler PROC
emilmont 10:3bc89ef62ce7 223 EXPORT Reset_Handler [WEAK]
emilmont 10:3bc89ef62ce7 224 IMPORT SystemInit
emilmont 10:3bc89ef62ce7 225 IMPORT __main
emilmont 10:3bc89ef62ce7 226 LDR R0, =SystemInit
emilmont 10:3bc89ef62ce7 227 BLX R0
emilmont 10:3bc89ef62ce7 228 LDR R0, =__main
emilmont 10:3bc89ef62ce7 229 BX R0
emilmont 10:3bc89ef62ce7 230 ENDP
emilmont 10:3bc89ef62ce7 231
emilmont 10:3bc89ef62ce7 232
emilmont 10:3bc89ef62ce7 233 ; Dummy Exception Handlers (infinite loops which can be modified)
emilmont 10:3bc89ef62ce7 234
emilmont 10:3bc89ef62ce7 235 NMI_Handler PROC
emilmont 10:3bc89ef62ce7 236 EXPORT NMI_Handler [WEAK]
emilmont 10:3bc89ef62ce7 237 B .
emilmont 10:3bc89ef62ce7 238 ENDP
emilmont 10:3bc89ef62ce7 239 HardFault_Handler\
emilmont 10:3bc89ef62ce7 240 PROC
emilmont 10:3bc89ef62ce7 241 EXPORT HardFault_Handler [WEAK]
emilmont 10:3bc89ef62ce7 242 B .
emilmont 10:3bc89ef62ce7 243 ENDP
emilmont 10:3bc89ef62ce7 244 SVC_Handler PROC
emilmont 10:3bc89ef62ce7 245 EXPORT SVC_Handler [WEAK]
emilmont 10:3bc89ef62ce7 246 B .
emilmont 10:3bc89ef62ce7 247 ENDP
emilmont 10:3bc89ef62ce7 248 PendSV_Handler PROC
emilmont 10:3bc89ef62ce7 249 EXPORT PendSV_Handler [WEAK]
emilmont 10:3bc89ef62ce7 250 B .
emilmont 10:3bc89ef62ce7 251 ENDP
emilmont 10:3bc89ef62ce7 252 SysTick_Handler PROC
emilmont 10:3bc89ef62ce7 253 EXPORT SysTick_Handler [WEAK]
emilmont 10:3bc89ef62ce7 254 B .
emilmont 10:3bc89ef62ce7 255 ENDP
emilmont 10:3bc89ef62ce7 256
emilmont 10:3bc89ef62ce7 257 Default_Handler PROC
emilmont 10:3bc89ef62ce7 258 EXPORT DMA0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 259 EXPORT DMA1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 260 EXPORT DMA2_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 261 EXPORT DMA3_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 262 EXPORT Reserved20_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 263 EXPORT FTFA_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 264 EXPORT LVD_LVW_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 265 EXPORT LLW_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 266 EXPORT I2C0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 267 EXPORT I2C1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 268 EXPORT SPI0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 269 EXPORT SPI1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 270 EXPORT UART0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 271 EXPORT UART1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 272 EXPORT UART2_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 273 EXPORT ADC0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 274 EXPORT CMP0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 275 EXPORT TPM0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 276 EXPORT TPM1_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 277 EXPORT TPM2_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 278 EXPORT RTC_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 279 EXPORT RTC_Seconds_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 280 EXPORT PIT_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 281 EXPORT Reserved39_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 282 EXPORT USB0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 283 EXPORT DAC0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 284 EXPORT TSI0_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 285 EXPORT MCG_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 286 EXPORT LPTimer_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 287 EXPORT Reserved45_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 288 EXPORT PORTA_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 289 EXPORT PORTD_IRQHandler [WEAK]
emilmont 10:3bc89ef62ce7 290 EXPORT DefaultISR [WEAK]
emilmont 10:3bc89ef62ce7 291
emilmont 10:3bc89ef62ce7 292 DMA0_IRQHandler
emilmont 10:3bc89ef62ce7 293 DMA1_IRQHandler
emilmont 10:3bc89ef62ce7 294 DMA2_IRQHandler
emilmont 10:3bc89ef62ce7 295 DMA3_IRQHandler
emilmont 10:3bc89ef62ce7 296 Reserved20_IRQHandler
emilmont 10:3bc89ef62ce7 297 FTFA_IRQHandler
emilmont 10:3bc89ef62ce7 298 LVD_LVW_IRQHandler
emilmont 10:3bc89ef62ce7 299 LLW_IRQHandler
emilmont 10:3bc89ef62ce7 300 I2C0_IRQHandler
emilmont 10:3bc89ef62ce7 301 I2C1_IRQHandler
emilmont 10:3bc89ef62ce7 302 SPI0_IRQHandler
emilmont 10:3bc89ef62ce7 303 SPI1_IRQHandler
emilmont 10:3bc89ef62ce7 304 UART0_IRQHandler
emilmont 10:3bc89ef62ce7 305 UART1_IRQHandler
emilmont 10:3bc89ef62ce7 306 UART2_IRQHandler
emilmont 10:3bc89ef62ce7 307 ADC0_IRQHandler
emilmont 10:3bc89ef62ce7 308 CMP0_IRQHandler
emilmont 10:3bc89ef62ce7 309 TPM0_IRQHandler
emilmont 10:3bc89ef62ce7 310 TPM1_IRQHandler
emilmont 10:3bc89ef62ce7 311 TPM2_IRQHandler
emilmont 10:3bc89ef62ce7 312 RTC_IRQHandler
emilmont 10:3bc89ef62ce7 313 RTC_Seconds_IRQHandler
emilmont 10:3bc89ef62ce7 314 PIT_IRQHandler
emilmont 10:3bc89ef62ce7 315 Reserved39_IRQHandler
emilmont 10:3bc89ef62ce7 316 USB0_IRQHandler
emilmont 10:3bc89ef62ce7 317 DAC0_IRQHandler
emilmont 10:3bc89ef62ce7 318 TSI0_IRQHandler
emilmont 10:3bc89ef62ce7 319 MCG_IRQHandler
emilmont 10:3bc89ef62ce7 320 LPTimer_IRQHandler
emilmont 10:3bc89ef62ce7 321 Reserved45_IRQHandler
emilmont 10:3bc89ef62ce7 322 PORTA_IRQHandler
emilmont 10:3bc89ef62ce7 323 PORTD_IRQHandler
emilmont 10:3bc89ef62ce7 324 DefaultISR
emilmont 10:3bc89ef62ce7 325
emilmont 10:3bc89ef62ce7 326 B .
emilmont 10:3bc89ef62ce7 327
emilmont 10:3bc89ef62ce7 328 ENDP
emilmont 10:3bc89ef62ce7 329
emilmont 10:3bc89ef62ce7 330
emilmont 10:3bc89ef62ce7 331 ALIGN
emilmont 10:3bc89ef62ce7 332 END