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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11XX/cmsis_nvic.c@19:398f4c622e1b, 2013-08-19 (annotated)

Committer:
bogdanm
Date:
Mon Aug 19 18:17:02 2013 +0300
Revision:
19:398f4c622e1b
Sync with official mbed library release 66

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 19:398f4c622e1b 1 /* mbed Microcontroller Library - cmsis_nvic for LPC11U24
bogdanm 19:398f4c622e1b 2 * Copyright (c) 2011 ARM Limited. All rights reserved.
bogdanm 19:398f4c622e1b 3 *
bogdanm 19:398f4c622e1b 4 * CMSIS-style functionality to support dynamic vectors
bogdanm 19:398f4c622e1b 5 */
bogdanm 19:398f4c622e1b 6
bogdanm 19:398f4c622e1b 7 #include "cmsis_nvic.h"
bogdanm 19:398f4c622e1b 8
bogdanm 19:398f4c622e1b 9 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
bogdanm 19:398f4c622e1b 10 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
bogdanm 19:398f4c622e1b 11 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
bogdanm 19:398f4c622e1b 12 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
bogdanm 19:398f4c622e1b 13 *
bogdanm 19:398f4c622e1b 14 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
bogdanm 19:398f4c622e1b 15 * above the vector table before 0x200 will actually go to RAM. So we need to provide
bogdanm 19:398f4c622e1b 16 * a solution where the compiler gets the right results based on the memory map
bogdanm 19:398f4c622e1b 17 *
bogdanm 19:398f4c622e1b 18 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
bogdanm 19:398f4c622e1b 19 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
bogdanm 19:398f4c622e1b 20 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
bogdanm 19:398f4c622e1b 21 *
bogdanm 19:398f4c622e1b 22 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
bogdanm 19:398f4c622e1b 23 * - No flash accesses will go to ram, as there will be nothing there
bogdanm 19:398f4c622e1b 24 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
bogdanm 19:398f4c622e1b 25 * - RAM overhead: 0, FLASH overhead: 320 bytes
bogdanm 19:398f4c622e1b 26 *
bogdanm 19:398f4c622e1b 27 * Option 2 is the one to go for, as RAM is the most valuable resource
bogdanm 19:398f4c622e1b 28 */
bogdanm 19:398f4c622e1b 29
bogdanm 19:398f4c622e1b 30 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
bogdanm 19:398f4c622e1b 31
bogdanm 19:398f4c622e1b 32 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
bogdanm 19:398f4c622e1b 33 int i;
bogdanm 19:398f4c622e1b 34 // Space for dynamic vectors, initialised to allocate in R/W
bogdanm 19:398f4c622e1b 35 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
bogdanm 19:398f4c622e1b 36
bogdanm 19:398f4c622e1b 37 // Copy and switch to dynamic vectors if first time called
bogdanm 19:398f4c622e1b 38 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
bogdanm 19:398f4c622e1b 39 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
bogdanm 19:398f4c622e1b 40 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
bogdanm 19:398f4c622e1b 41 vectors[i] = old_vectors[i];
bogdanm 19:398f4c622e1b 42 }
bogdanm 19:398f4c622e1b 43 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
bogdanm 19:398f4c622e1b 44 }
bogdanm 19:398f4c622e1b 45
bogdanm 19:398f4c622e1b 46 // Set the vector
bogdanm 19:398f4c622e1b 47 vectors[IRQn + 16] = vector;
bogdanm 19:398f4c622e1b 48 }
bogdanm 19:398f4c622e1b 49
bogdanm 19:398f4c622e1b 50 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
bogdanm 19:398f4c622e1b 51 // We can always read vectors at 0x0, as the addresses are remapped
bogdanm 19:398f4c622e1b 52 uint32_t *vectors = (uint32_t*)0;
bogdanm 19:398f4c622e1b 53
bogdanm 19:398f4c622e1b 54 // Return the vector
bogdanm 19:398f4c622e1b 55 return vectors[IRQn + 16];
bogdanm 19:398f4c622e1b 56 }
bogdanm 19:398f4c622e1b 57