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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_GCC_ARM/startup_LPC11xx.s@19:398f4c622e1b, 2013-08-19 (annotated)

Committer:
bogdanm
Date:
Mon Aug 19 18:17:02 2013 +0300
Revision:
19:398f4c622e1b
Sync with official mbed library release 66

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 19:398f4c622e1b 1 /* File: startup_ARMCM0.S
bogdanm 19:398f4c622e1b 2 * Purpose: startup file for Cortex-M0 devices. Should use with
bogdanm 19:398f4c622e1b 3 * GCC for ARM Embedded Processors
bogdanm 19:398f4c622e1b 4 * Version: V1.2
bogdanm 19:398f4c622e1b 5 * Date: 15 Nov 2011
bogdanm 19:398f4c622e1b 6 *
bogdanm 19:398f4c622e1b 7 * Copyright (c) 2011, ARM Limited
bogdanm 19:398f4c622e1b 8 * All rights reserved.
bogdanm 19:398f4c622e1b 9 *
bogdanm 19:398f4c622e1b 10 * Redistribution and use in source and binary forms, with or without
bogdanm 19:398f4c622e1b 11 * modification, are permitted provided that the following conditions are met:
bogdanm 19:398f4c622e1b 12 * Redistributions of source code must retain the above copyright
bogdanm 19:398f4c622e1b 13 notice, this list of conditions and the following disclaimer.
bogdanm 19:398f4c622e1b 14 * Redistributions in binary form must reproduce the above copyright
bogdanm 19:398f4c622e1b 15 notice, this list of conditions and the following disclaimer in the
bogdanm 19:398f4c622e1b 16 documentation and/or other materials provided with the distribution.
bogdanm 19:398f4c622e1b 17 * Neither the name of the ARM Limited nor the
bogdanm 19:398f4c622e1b 18 names of its contributors may be used to endorse or promote products
bogdanm 19:398f4c622e1b 19 derived from this software without specific prior written permission.
bogdanm 19:398f4c622e1b 20 *
bogdanm 19:398f4c622e1b 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 19:398f4c622e1b 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 19:398f4c622e1b 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 19:398f4c622e1b 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
bogdanm 19:398f4c622e1b 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 19:398f4c622e1b 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 19:398f4c622e1b 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
bogdanm 19:398f4c622e1b 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 19:398f4c622e1b 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 19:398f4c622e1b 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 19:398f4c622e1b 31 */
bogdanm 19:398f4c622e1b 32 .syntax unified
bogdanm 19:398f4c622e1b 33 .arch armv6-m
bogdanm 19:398f4c622e1b 34
bogdanm 19:398f4c622e1b 35 /* Memory Model
bogdanm 19:398f4c622e1b 36 The HEAP starts at the end of the DATA section and grows upward.
bogdanm 19:398f4c622e1b 37
bogdanm 19:398f4c622e1b 38 The STACK starts at the end of the RAM and grows downward.
bogdanm 19:398f4c622e1b 39
bogdanm 19:398f4c622e1b 40 The HEAP and stack STACK are only checked at compile time:
bogdanm 19:398f4c622e1b 41 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
bogdanm 19:398f4c622e1b 42
bogdanm 19:398f4c622e1b 43 This is just a check for the bare minimum for the Heap+Stack area before
bogdanm 19:398f4c622e1b 44 aborting compilation, it is not the run time limit:
bogdanm 19:398f4c622e1b 45 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
bogdanm 19:398f4c622e1b 46 */
bogdanm 19:398f4c622e1b 47 .section .stack
bogdanm 19:398f4c622e1b 48 .align 3
bogdanm 19:398f4c622e1b 49 #ifdef __STACK_SIZE
bogdanm 19:398f4c622e1b 50 .equ Stack_Size, __STACK_SIZE
bogdanm 19:398f4c622e1b 51 #else
bogdanm 19:398f4c622e1b 52 .equ Stack_Size, 0x80
bogdanm 19:398f4c622e1b 53 #endif
bogdanm 19:398f4c622e1b 54 .globl __StackTop
bogdanm 19:398f4c622e1b 55 .globl __StackLimit
bogdanm 19:398f4c622e1b 56 __StackLimit:
bogdanm 19:398f4c622e1b 57 .space Stack_Size
bogdanm 19:398f4c622e1b 58 .size __StackLimit, . - __StackLimit
bogdanm 19:398f4c622e1b 59 __StackTop:
bogdanm 19:398f4c622e1b 60 .size __StackTop, . - __StackTop
bogdanm 19:398f4c622e1b 61
bogdanm 19:398f4c622e1b 62 .section .heap
bogdanm 19:398f4c622e1b 63 .align 3
bogdanm 19:398f4c622e1b 64 #ifdef __HEAP_SIZE
bogdanm 19:398f4c622e1b 65 .equ Heap_Size, __HEAP_SIZE
bogdanm 19:398f4c622e1b 66 #else
bogdanm 19:398f4c622e1b 67 .equ Heap_Size, 0x80
bogdanm 19:398f4c622e1b 68 #endif
bogdanm 19:398f4c622e1b 69 .globl __HeapBase
bogdanm 19:398f4c622e1b 70 .globl __HeapLimit
bogdanm 19:398f4c622e1b 71 __HeapBase:
bogdanm 19:398f4c622e1b 72 .space Heap_Size
bogdanm 19:398f4c622e1b 73 .size __HeapBase, . - __HeapBase
bogdanm 19:398f4c622e1b 74 __HeapLimit:
bogdanm 19:398f4c622e1b 75 .size __HeapLimit, . - __HeapLimit
bogdanm 19:398f4c622e1b 76
bogdanm 19:398f4c622e1b 77 .section .isr_vector
bogdanm 19:398f4c622e1b 78 .align 2
bogdanm 19:398f4c622e1b 79 .globl __isr_vector
bogdanm 19:398f4c622e1b 80 __isr_vector:
bogdanm 19:398f4c622e1b 81 .long __StackTop /* Top of Stack */
bogdanm 19:398f4c622e1b 82 .long Reset_Handler /* Reset Handler */
bogdanm 19:398f4c622e1b 83 .long NMI_Handler /* NMI Handler */
bogdanm 19:398f4c622e1b 84 .long HardFault_Handler /* Hard Fault Handler */
bogdanm 19:398f4c622e1b 85 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 86 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 87 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 88 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 89 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 90 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 91 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 92 .long SVC_Handler /* SVCall Handler */
bogdanm 19:398f4c622e1b 93 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 94 .long 0 /* Reserved */
bogdanm 19:398f4c622e1b 95 .long PendSV_Handler /* PendSV Handler */
bogdanm 19:398f4c622e1b 96 .long SysTick_Handler /* SysTick Handler */
bogdanm 19:398f4c622e1b 97
bogdanm 19:398f4c622e1b 98 /* LPC11xx interrupts */
bogdanm 19:398f4c622e1b 99 .long WAKEUP_IRQHandler /* 16 0 Wake-up on pin PIO0_0 */
bogdanm 19:398f4c622e1b 100 .long WAKEUP_IRQHandler /* 17 1 Wake-up on pin PIO0_1 */
bogdanm 19:398f4c622e1b 101 .long WAKEUP_IRQHandler /* 18 2 Wake-up on pin PIO0_2 */
bogdanm 19:398f4c622e1b 102 .long WAKEUP_IRQHandler /* 19 3 Wake-up on pin PIO0_3 */
bogdanm 19:398f4c622e1b 103 .long WAKEUP_IRQHandler /* 20 4 Wake-up on pin PIO0_4 */
bogdanm 19:398f4c622e1b 104 .long WAKEUP_IRQHandler /* 21 5 Wake-up on pin PIO0_5 */
bogdanm 19:398f4c622e1b 105 .long WAKEUP_IRQHandler /* 22 6 Wake-up on pin PIO0_6 */
bogdanm 19:398f4c622e1b 106 .long WAKEUP_IRQHandler /* 23 7 Wake-up on pin PIO0_7 */
bogdanm 19:398f4c622e1b 107 .long WAKEUP_IRQHandler /* 24 8 Wake-up on pin PIO0_8 */
bogdanm 19:398f4c622e1b 108 .long WAKEUP_IRQHandler /* 25 9 Wake-up on pin PIO0_9 */
bogdanm 19:398f4c622e1b 109 .long WAKEUP_IRQHandler /* 26 10 Wake-up on pin PIO0_10 */
bogdanm 19:398f4c622e1b 110 .long WAKEUP_IRQHandler /* 27 11 Wake-up on pin PIO0_11 */
bogdanm 19:398f4c622e1b 111 .long WAKEUP_IRQHandler /* 28 12 Wake-up on pin PIO1_0 */
bogdanm 19:398f4c622e1b 112 .long Default_Handler /* 29 13 */
bogdanm 19:398f4c622e1b 113 .long SSP1_IRQHandler /* 30 14 SSP1 */
bogdanm 19:398f4c622e1b 114 .long I2C_IRQHandler /* 31 15 I2C0 SI (state change) */
bogdanm 19:398f4c622e1b 115 .long TIMER16_0_IRQHandler /* 32 16 CT16B0 16 bit timer 0 */
bogdanm 19:398f4c622e1b 116 .long TIMER16_1_IRQHandler /* 33 17 CT16B1 16 bit timer 1 */
bogdanm 19:398f4c622e1b 117 .long TIMER32_0_IRQHandler /* 34 18 CT32B0 32 bit timer 0 */
bogdanm 19:398f4c622e1b 118 .long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
bogdanm 19:398f4c622e1b 119 .long SSP0_IRQHandler /* 36 20 SSP */
bogdanm 19:398f4c622e1b 120 .long UART_IRQHandler /* 37 21 UART */
bogdanm 19:398f4c622e1b 121 .long Default_Handler /* 38 22 */
bogdanm 19:398f4c622e1b 122 .long Default_Handler /* 39 23 */
bogdanm 19:398f4c622e1b 123 .long ADC_IRQHandler /* 40 24 ADC end of conversion */
bogdanm 19:398f4c622e1b 124 .long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
bogdanm 19:398f4c622e1b 125 .long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
bogdanm 19:398f4c622e1b 126 .long Default_Handler /* 43 27 */
bogdanm 19:398f4c622e1b 127 .long PIOINT3_IRQHandler /* 44 28 PIO_3 GPIO interrupt status of port 3 */
bogdanm 19:398f4c622e1b 128 .long PIOINT2_IRQHandler /* 45 29 PIO_2 GPIO interrupt status of port 2 */
bogdanm 19:398f4c622e1b 129 .long PIOINT1_IRQHandler /* 46 30 PIO_1 GPIO interrupt status of port 1 */
bogdanm 19:398f4c622e1b 130 .long PIOINT0_IRQHandler /* 47 31 PIO_0 GPIO interrupt status of port 0 */
bogdanm 19:398f4c622e1b 131
bogdanm 19:398f4c622e1b 132 .size __isr_vector, . - __isr_vector
bogdanm 19:398f4c622e1b 133
bogdanm 19:398f4c622e1b 134 .section .text.Reset_Handler
bogdanm 19:398f4c622e1b 135 .thumb
bogdanm 19:398f4c622e1b 136 .thumb_func
bogdanm 19:398f4c622e1b 137 .align 2
bogdanm 19:398f4c622e1b 138 .globl Reset_Handler
bogdanm 19:398f4c622e1b 139 .type Reset_Handler, %function
bogdanm 19:398f4c622e1b 140 Reset_Handler:
bogdanm 19:398f4c622e1b 141 /* Loop to copy data from read only memory to RAM. The ranges
bogdanm 19:398f4c622e1b 142 * of copy from/to are specified by following symbols evaluated in
bogdanm 19:398f4c622e1b 143 * linker script.
bogdanm 19:398f4c622e1b 144 * __etext: End of code section, i.e., begin of data sections to copy from.
bogdanm 19:398f4c622e1b 145 * __data_start__/__data_end__: RAM address range that data should be
bogdanm 19:398f4c622e1b 146 * copied to. Both must be aligned to 4 bytes boundary. */
bogdanm 19:398f4c622e1b 147
bogdanm 19:398f4c622e1b 148 ldr r1, =__etext
bogdanm 19:398f4c622e1b 149 ldr r2, =__data_start__
bogdanm 19:398f4c622e1b 150 ldr r3, =__data_end__
bogdanm 19:398f4c622e1b 151
bogdanm 19:398f4c622e1b 152 subs r3, r2
bogdanm 19:398f4c622e1b 153 ble .flash_to_ram_loop_end
bogdanm 19:398f4c622e1b 154
bogdanm 19:398f4c622e1b 155 movs r4, 0
bogdanm 19:398f4c622e1b 156 .flash_to_ram_loop:
bogdanm 19:398f4c622e1b 157 ldr r0, [r1,r4]
bogdanm 19:398f4c622e1b 158 str r0, [r2,r4]
bogdanm 19:398f4c622e1b 159 adds r4, 4
bogdanm 19:398f4c622e1b 160 cmp r4, r3
bogdanm 19:398f4c622e1b 161 blt .flash_to_ram_loop
bogdanm 19:398f4c622e1b 162 .flash_to_ram_loop_end:
bogdanm 19:398f4c622e1b 163
bogdanm 19:398f4c622e1b 164 ldr r0, =SystemInit
bogdanm 19:398f4c622e1b 165 blx r0
bogdanm 19:398f4c622e1b 166 ldr r0, =_start
bogdanm 19:398f4c622e1b 167 bx r0
bogdanm 19:398f4c622e1b 168 .pool
bogdanm 19:398f4c622e1b 169 .size Reset_Handler, . - Reset_Handler
bogdanm 19:398f4c622e1b 170
bogdanm 19:398f4c622e1b 171 .text
bogdanm 19:398f4c622e1b 172 /* Macro to define default handlers. Default handler
bogdanm 19:398f4c622e1b 173 * will be weak symbol and just dead loops. They can be
bogdanm 19:398f4c622e1b 174 * overwritten by other handlers */
bogdanm 19:398f4c622e1b 175 .macro def_default_handler handler_name
bogdanm 19:398f4c622e1b 176 .align 1
bogdanm 19:398f4c622e1b 177 .thumb_func
bogdanm 19:398f4c622e1b 178 .weak \handler_name
bogdanm 19:398f4c622e1b 179 .type \handler_name, %function
bogdanm 19:398f4c622e1b 180 \handler_name :
bogdanm 19:398f4c622e1b 181 b .
bogdanm 19:398f4c622e1b 182 .size \handler_name, . - \handler_name
bogdanm 19:398f4c622e1b 183 .endm
bogdanm 19:398f4c622e1b 184
bogdanm 19:398f4c622e1b 185 def_default_handler NMI_Handler
bogdanm 19:398f4c622e1b 186 def_default_handler HardFault_Handler
bogdanm 19:398f4c622e1b 187 def_default_handler SVC_Handler
bogdanm 19:398f4c622e1b 188 def_default_handler PendSV_Handler
bogdanm 19:398f4c622e1b 189 def_default_handler SysTick_Handler
bogdanm 19:398f4c622e1b 190 def_default_handler Default_Handler
bogdanm 19:398f4c622e1b 191
bogdanm 19:398f4c622e1b 192 def_default_handler WAKEUP_IRQHandler
bogdanm 19:398f4c622e1b 193 def_default_handler SSP1_IRQHandler
bogdanm 19:398f4c622e1b 194 def_default_handler I2C_IRQHandler
bogdanm 19:398f4c622e1b 195 def_default_handler TIMER16_0_IRQHandler
bogdanm 19:398f4c622e1b 196 def_default_handler TIMER16_1_IRQHandler
bogdanm 19:398f4c622e1b 197 def_default_handler TIMER32_0_IRQHandler
bogdanm 19:398f4c622e1b 198 def_default_handler TIMER32_1_IRQHandler
bogdanm 19:398f4c622e1b 199 def_default_handler SSP0_IRQHandler
bogdanm 19:398f4c622e1b 200 def_default_handler UART_IRQHandler
bogdanm 19:398f4c622e1b 201 def_default_handler ADC_IRQHandler
bogdanm 19:398f4c622e1b 202 def_default_handler WDT_IRQHandler
bogdanm 19:398f4c622e1b 203 def_default_handler BOD_IRQHandler
bogdanm 19:398f4c622e1b 204 def_default_handler PIOINT3_IRQHandler
bogdanm 19:398f4c622e1b 205 def_default_handler PIOINT2_IRQHandler
bogdanm 19:398f4c622e1b 206 def_default_handler PIOINT1_IRQHandler
bogdanm 19:398f4c622e1b 207 def_default_handler PIOINT0_IRQHandler
bogdanm 19:398f4c622e1b 208
bogdanm 19:398f4c622e1b 209 .weak DEF_IRQHandler
bogdanm 19:398f4c622e1b 210 .set DEF_IRQHandler, Default_Handler
bogdanm 19:398f4c622e1b 211
bogdanm 19:398f4c622e1b 212 .end
bogdanm 19:398f4c622e1b 213