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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KL46Z/MKL46Z4.h@44:2ce89a25b635, 2013-11-05 (annotated)

Committer:
mbed_official
Date:
Tue Nov 05 21:45:05 2013 +0000
Revision:
44:2ce89a25b635
Parent:
31:42176bc3c368
Child:
69:49e45cb70de1
Synchronized with git revision 887fd2ba3aa83c1c285196ff1cae1341a3e00bec

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 31:42176bc3c368 1 /*
mbed_official 31:42176bc3c368 2 ** ###################################################################
mbed_official 44:2ce89a25b635 3 ** Processors: MKL46Z256VLH4
mbed_official 44:2ce89a25b635 4 ** MKL46Z128VLH4
mbed_official 44:2ce89a25b635 5 ** MKL46Z256VLL4
mbed_official 44:2ce89a25b635 6 ** MKL46Z128VLL4
mbed_official 44:2ce89a25b635 7 ** MKL46Z256VMC4
mbed_official 44:2ce89a25b635 8 ** MKL46Z128VMC4
mbed_official 44:2ce89a25b635 9 **
mbed_official 31:42176bc3c368 10 ** Compilers: ARM Compiler
mbed_official 31:42176bc3c368 11 ** Freescale C/C++ for Embedded ARM
mbed_official 31:42176bc3c368 12 ** GNU C Compiler
mbed_official 31:42176bc3c368 13 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 31:42176bc3c368 14 **
mbed_official 44:2ce89a25b635 15 ** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
mbed_official 44:2ce89a25b635 16 ** Version: rev. 2.0, 2012-12-12
mbed_official 31:42176bc3c368 17 **
mbed_official 31:42176bc3c368 18 ** Abstract:
mbed_official 31:42176bc3c368 19 ** CMSIS Peripheral Access Layer for MKL46Z4
mbed_official 31:42176bc3c368 20 **
mbed_official 44:2ce89a25b635 21 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
mbed_official 31:42176bc3c368 22 **
mbed_official 31:42176bc3c368 23 ** http: www.freescale.com
mbed_official 31:42176bc3c368 24 ** mail: support@freescale.com
mbed_official 31:42176bc3c368 25 **
mbed_official 31:42176bc3c368 26 ** Revisions:
mbed_official 44:2ce89a25b635 27 ** - rev. 1.0 (2012-10-16)
mbed_official 31:42176bc3c368 28 ** Initial version.
mbed_official 44:2ce89a25b635 29 ** - rev. 2.0 (2012-12-12)
mbed_official 44:2ce89a25b635 30 ** Update to reference manual rev. 1.
mbed_official 31:42176bc3c368 31 **
mbed_official 31:42176bc3c368 32 ** ###################################################################
mbed_official 31:42176bc3c368 33 */
mbed_official 31:42176bc3c368 34
mbed_official 31:42176bc3c368 35 /**
mbed_official 31:42176bc3c368 36 * @file MKL46Z4.h
mbed_official 44:2ce89a25b635 37 * @version 2.0
mbed_official 44:2ce89a25b635 38 * @date 2012-12-12
mbed_official 31:42176bc3c368 39 * @brief CMSIS Peripheral Access Layer for MKL46Z4
mbed_official 31:42176bc3c368 40 *
mbed_official 31:42176bc3c368 41 * CMSIS Peripheral Access Layer for MKL46Z4
mbed_official 31:42176bc3c368 42 */
mbed_official 31:42176bc3c368 43
mbed_official 31:42176bc3c368 44 #if !defined(MKL46Z4_H_)
mbed_official 31:42176bc3c368 45 #define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
mbed_official 31:42176bc3c368 46
mbed_official 31:42176bc3c368 47 /** Memory map major version (memory maps with equal major version number are
mbed_official 31:42176bc3c368 48 * compatible) */
mbed_official 44:2ce89a25b635 49 #define MCU_MEM_MAP_VERSION 0x0200u
mbed_official 31:42176bc3c368 50 /** Memory map minor version */
mbed_official 44:2ce89a25b635 51 #define MCU_MEM_MAP_VERSION_MINOR 0x0000u
mbed_official 31:42176bc3c368 52
mbed_official 31:42176bc3c368 53
mbed_official 31:42176bc3c368 54 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 55 -- Interrupt vector numbers
mbed_official 31:42176bc3c368 56 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 57
mbed_official 31:42176bc3c368 58 /**
mbed_official 31:42176bc3c368 59 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 31:42176bc3c368 60 * @{
mbed_official 31:42176bc3c368 61 */
mbed_official 31:42176bc3c368 62
mbed_official 31:42176bc3c368 63 /** Interrupt Number Definitions */
mbed_official 31:42176bc3c368 64 typedef enum IRQn {
mbed_official 31:42176bc3c368 65 /* Core interrupts */
mbed_official 31:42176bc3c368 66 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 31:42176bc3c368 67 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
mbed_official 31:42176bc3c368 68 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
mbed_official 31:42176bc3c368 69 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
mbed_official 31:42176bc3c368 70 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
mbed_official 31:42176bc3c368 71
mbed_official 31:42176bc3c368 72 /* Device specific interrupts */
mbed_official 44:2ce89a25b635 73 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
mbed_official 44:2ce89a25b635 74 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
mbed_official 44:2ce89a25b635 75 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
mbed_official 44:2ce89a25b635 76 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
mbed_official 31:42176bc3c368 77 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
mbed_official 44:2ce89a25b635 78 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
mbed_official 31:42176bc3c368 79 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 31:42176bc3c368 80 LLW_IRQn = 7, /**< Low Leakage Wakeup */
mbed_official 31:42176bc3c368 81 I2C0_IRQn = 8, /**< I2C0 interrupt */
mbed_official 31:42176bc3c368 82 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
mbed_official 31:42176bc3c368 83 SPI0_IRQn = 10, /**< SPI0 interrupt */
mbed_official 31:42176bc3c368 84 SPI1_IRQn = 11, /**< SPI1 interrupt */
mbed_official 31:42176bc3c368 85 UART0_IRQn = 12, /**< UART0 status/error interrupt */
mbed_official 31:42176bc3c368 86 UART1_IRQn = 13, /**< UART1 status/error interrupt */
mbed_official 31:42176bc3c368 87 UART2_IRQn = 14, /**< UART2 status/error interrupt */
mbed_official 31:42176bc3c368 88 ADC0_IRQn = 15, /**< ADC0 interrupt */
mbed_official 31:42176bc3c368 89 CMP0_IRQn = 16, /**< CMP0 interrupt */
mbed_official 31:42176bc3c368 90 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
mbed_official 31:42176bc3c368 91 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
mbed_official 31:42176bc3c368 92 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
mbed_official 31:42176bc3c368 93 RTC_IRQn = 20, /**< RTC interrupt */
mbed_official 31:42176bc3c368 94 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
mbed_official 31:42176bc3c368 95 PIT_IRQn = 22, /**< PIT timer interrupt */
mbed_official 44:2ce89a25b635 96 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
mbed_official 31:42176bc3c368 97 USB0_IRQn = 24, /**< USB0 interrupt */
mbed_official 44:2ce89a25b635 98 DAC0_IRQn = 25, /**< DAC0 interrupt */
mbed_official 31:42176bc3c368 99 TSI0_IRQn = 26, /**< TSI0 interrupt */
mbed_official 31:42176bc3c368 100 MCG_IRQn = 27, /**< MCG interrupt */
mbed_official 31:42176bc3c368 101 LPTimer_IRQn = 28, /**< LPTimer interrupt */
mbed_official 44:2ce89a25b635 102 LCD_IRQn = 29, /**< Segment LCD Interrupt */
mbed_official 31:42176bc3c368 103 PORTA_IRQn = 30, /**< Port A interrupt */
mbed_official 31:42176bc3c368 104 PORTD_IRQn = 31 /**< Port D interrupt */
mbed_official 31:42176bc3c368 105 } IRQn_Type;
mbed_official 31:42176bc3c368 106
mbed_official 31:42176bc3c368 107 /**
mbed_official 31:42176bc3c368 108 * @}
mbed_official 31:42176bc3c368 109 */ /* end of group Interrupt_vector_numbers */
mbed_official 31:42176bc3c368 110
mbed_official 31:42176bc3c368 111
mbed_official 31:42176bc3c368 112 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 113 -- Cortex M0 Core Configuration
mbed_official 31:42176bc3c368 114 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 115
mbed_official 31:42176bc3c368 116 /**
mbed_official 31:42176bc3c368 117 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
mbed_official 31:42176bc3c368 118 * @{
mbed_official 31:42176bc3c368 119 */
mbed_official 31:42176bc3c368 120
mbed_official 31:42176bc3c368 121 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
mbed_official 31:42176bc3c368 122 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 31:42176bc3c368 123 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
mbed_official 31:42176bc3c368 124 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
mbed_official 31:42176bc3c368 125 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 31:42176bc3c368 126
mbed_official 31:42176bc3c368 127 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
mbed_official 31:42176bc3c368 128 #include "system_MKL46Z4.h" /* Device specific configuration file */
mbed_official 31:42176bc3c368 129
mbed_official 31:42176bc3c368 130 /**
mbed_official 31:42176bc3c368 131 * @}
mbed_official 31:42176bc3c368 132 */ /* end of group Cortex_Core_Configuration */
mbed_official 31:42176bc3c368 133
mbed_official 31:42176bc3c368 134
mbed_official 31:42176bc3c368 135 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 136 -- Device Peripheral Access Layer
mbed_official 31:42176bc3c368 137 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 138
mbed_official 31:42176bc3c368 139 /**
mbed_official 31:42176bc3c368 140 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 31:42176bc3c368 141 * @{
mbed_official 31:42176bc3c368 142 */
mbed_official 31:42176bc3c368 143
mbed_official 31:42176bc3c368 144
mbed_official 31:42176bc3c368 145 /*
mbed_official 31:42176bc3c368 146 ** Start of section using anonymous unions
mbed_official 31:42176bc3c368 147 */
mbed_official 31:42176bc3c368 148
mbed_official 31:42176bc3c368 149 #if defined(__ARMCC_VERSION)
mbed_official 31:42176bc3c368 150 #pragma push
mbed_official 31:42176bc3c368 151 #pragma anon_unions
mbed_official 31:42176bc3c368 152 #elif defined(__CWCC__)
mbed_official 31:42176bc3c368 153 #pragma push
mbed_official 31:42176bc3c368 154 #pragma cpp_extensions on
mbed_official 31:42176bc3c368 155 #elif defined(__GNUC__)
mbed_official 31:42176bc3c368 156 /* anonymous unions are enabled by default */
mbed_official 31:42176bc3c368 157 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 31:42176bc3c368 158 #pragma language=extended
mbed_official 31:42176bc3c368 159 #else
mbed_official 31:42176bc3c368 160 #error Not supported compiler type
mbed_official 31:42176bc3c368 161 #endif
mbed_official 31:42176bc3c368 162
mbed_official 31:42176bc3c368 163 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 164 -- ADC Peripheral Access Layer
mbed_official 31:42176bc3c368 165 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 166
mbed_official 31:42176bc3c368 167 /**
mbed_official 31:42176bc3c368 168 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 31:42176bc3c368 169 * @{
mbed_official 31:42176bc3c368 170 */
mbed_official 31:42176bc3c368 171
mbed_official 31:42176bc3c368 172 /** ADC - Register Layout Typedef */
mbed_official 31:42176bc3c368 173 typedef struct {
mbed_official 31:42176bc3c368 174 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 31:42176bc3c368 175 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 31:42176bc3c368 176 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 31:42176bc3c368 177 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 31:42176bc3c368 178 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 31:42176bc3c368 179 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 31:42176bc3c368 180 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 31:42176bc3c368 181 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 31:42176bc3c368 182 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 31:42176bc3c368 183 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 31:42176bc3c368 184 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 31:42176bc3c368 185 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 31:42176bc3c368 186 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 31:42176bc3c368 187 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 31:42176bc3c368 188 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 31:42176bc3c368 189 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 31:42176bc3c368 190 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 31:42176bc3c368 191 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 31:42176bc3c368 192 uint8_t RESERVED_0[4];
mbed_official 31:42176bc3c368 193 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 31:42176bc3c368 194 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 31:42176bc3c368 195 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 31:42176bc3c368 196 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 31:42176bc3c368 197 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 31:42176bc3c368 198 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 31:42176bc3c368 199 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 31:42176bc3c368 200 } ADC_Type;
mbed_official 31:42176bc3c368 201
mbed_official 31:42176bc3c368 202 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 203 -- ADC Register Masks
mbed_official 31:42176bc3c368 204 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 205
mbed_official 31:42176bc3c368 206 /**
mbed_official 31:42176bc3c368 207 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 31:42176bc3c368 208 * @{
mbed_official 31:42176bc3c368 209 */
mbed_official 31:42176bc3c368 210
mbed_official 31:42176bc3c368 211 /* SC1 Bit Fields */
mbed_official 31:42176bc3c368 212 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 31:42176bc3c368 213 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 31:42176bc3c368 214 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 31:42176bc3c368 215 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 31:42176bc3c368 216 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 31:42176bc3c368 217 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 31:42176bc3c368 218 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 31:42176bc3c368 219 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 31:42176bc3c368 220 #define ADC_SC1_COCO_SHIFT 7
mbed_official 31:42176bc3c368 221 /* CFG1 Bit Fields */
mbed_official 31:42176bc3c368 222 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 31:42176bc3c368 223 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 31:42176bc3c368 224 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 31:42176bc3c368 225 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 31:42176bc3c368 226 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 31:42176bc3c368 227 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 31:42176bc3c368 228 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 31:42176bc3c368 229 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 31:42176bc3c368 230 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 31:42176bc3c368 231 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 31:42176bc3c368 232 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 31:42176bc3c368 233 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 31:42176bc3c368 234 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 31:42176bc3c368 235 /* CFG2 Bit Fields */
mbed_official 31:42176bc3c368 236 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 31:42176bc3c368 237 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 31:42176bc3c368 238 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 31:42176bc3c368 239 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 31:42176bc3c368 240 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 31:42176bc3c368 241 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 31:42176bc3c368 242 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 31:42176bc3c368 243 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 31:42176bc3c368 244 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 31:42176bc3c368 245 /* R Bit Fields */
mbed_official 31:42176bc3c368 246 #define ADC_R_D_MASK 0xFFFFu
mbed_official 31:42176bc3c368 247 #define ADC_R_D_SHIFT 0
mbed_official 31:42176bc3c368 248 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 31:42176bc3c368 249 /* CV1 Bit Fields */
mbed_official 31:42176bc3c368 250 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 31:42176bc3c368 251 #define ADC_CV1_CV_SHIFT 0
mbed_official 31:42176bc3c368 252 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 31:42176bc3c368 253 /* CV2 Bit Fields */
mbed_official 31:42176bc3c368 254 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 31:42176bc3c368 255 #define ADC_CV2_CV_SHIFT 0
mbed_official 31:42176bc3c368 256 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 31:42176bc3c368 257 /* SC2 Bit Fields */
mbed_official 31:42176bc3c368 258 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 31:42176bc3c368 259 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 31:42176bc3c368 260 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 31:42176bc3c368 261 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 31:42176bc3c368 262 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 31:42176bc3c368 263 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 31:42176bc3c368 264 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 31:42176bc3c368 265 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 31:42176bc3c368 266 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 31:42176bc3c368 267 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 31:42176bc3c368 268 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 31:42176bc3c368 269 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 31:42176bc3c368 270 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 31:42176bc3c368 271 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 31:42176bc3c368 272 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 31:42176bc3c368 273 /* SC3 Bit Fields */
mbed_official 31:42176bc3c368 274 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 31:42176bc3c368 275 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 31:42176bc3c368 276 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 31:42176bc3c368 277 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 31:42176bc3c368 278 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 31:42176bc3c368 279 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 31:42176bc3c368 280 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 31:42176bc3c368 281 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 31:42176bc3c368 282 #define ADC_SC3_CALF_SHIFT 6
mbed_official 31:42176bc3c368 283 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 31:42176bc3c368 284 #define ADC_SC3_CAL_SHIFT 7
mbed_official 31:42176bc3c368 285 /* OFS Bit Fields */
mbed_official 31:42176bc3c368 286 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 31:42176bc3c368 287 #define ADC_OFS_OFS_SHIFT 0
mbed_official 31:42176bc3c368 288 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 31:42176bc3c368 289 /* PG Bit Fields */
mbed_official 31:42176bc3c368 290 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 31:42176bc3c368 291 #define ADC_PG_PG_SHIFT 0
mbed_official 31:42176bc3c368 292 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 31:42176bc3c368 293 /* MG Bit Fields */
mbed_official 31:42176bc3c368 294 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 31:42176bc3c368 295 #define ADC_MG_MG_SHIFT 0
mbed_official 31:42176bc3c368 296 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 31:42176bc3c368 297 /* CLPD Bit Fields */
mbed_official 31:42176bc3c368 298 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 31:42176bc3c368 299 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 31:42176bc3c368 300 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 31:42176bc3c368 301 /* CLPS Bit Fields */
mbed_official 31:42176bc3c368 302 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 31:42176bc3c368 303 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 31:42176bc3c368 304 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 31:42176bc3c368 305 /* CLP4 Bit Fields */
mbed_official 31:42176bc3c368 306 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 31:42176bc3c368 307 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 31:42176bc3c368 308 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 31:42176bc3c368 309 /* CLP3 Bit Fields */
mbed_official 31:42176bc3c368 310 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 31:42176bc3c368 311 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 31:42176bc3c368 312 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 31:42176bc3c368 313 /* CLP2 Bit Fields */
mbed_official 31:42176bc3c368 314 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 31:42176bc3c368 315 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 31:42176bc3c368 316 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 31:42176bc3c368 317 /* CLP1 Bit Fields */
mbed_official 31:42176bc3c368 318 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 31:42176bc3c368 319 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 31:42176bc3c368 320 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 31:42176bc3c368 321 /* CLP0 Bit Fields */
mbed_official 31:42176bc3c368 322 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 31:42176bc3c368 323 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 31:42176bc3c368 324 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 31:42176bc3c368 325 /* CLMD Bit Fields */
mbed_official 31:42176bc3c368 326 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 31:42176bc3c368 327 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 31:42176bc3c368 328 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 31:42176bc3c368 329 /* CLMS Bit Fields */
mbed_official 31:42176bc3c368 330 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 31:42176bc3c368 331 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 31:42176bc3c368 332 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 31:42176bc3c368 333 /* CLM4 Bit Fields */
mbed_official 31:42176bc3c368 334 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 31:42176bc3c368 335 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 31:42176bc3c368 336 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 31:42176bc3c368 337 /* CLM3 Bit Fields */
mbed_official 31:42176bc3c368 338 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 31:42176bc3c368 339 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 31:42176bc3c368 340 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 31:42176bc3c368 341 /* CLM2 Bit Fields */
mbed_official 31:42176bc3c368 342 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 31:42176bc3c368 343 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 31:42176bc3c368 344 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 31:42176bc3c368 345 /* CLM1 Bit Fields */
mbed_official 31:42176bc3c368 346 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 31:42176bc3c368 347 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 31:42176bc3c368 348 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 31:42176bc3c368 349 /* CLM0 Bit Fields */
mbed_official 31:42176bc3c368 350 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 31:42176bc3c368 351 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 31:42176bc3c368 352 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 31:42176bc3c368 353
mbed_official 31:42176bc3c368 354 /**
mbed_official 31:42176bc3c368 355 * @}
mbed_official 31:42176bc3c368 356 */ /* end of group ADC_Register_Masks */
mbed_official 31:42176bc3c368 357
mbed_official 31:42176bc3c368 358
mbed_official 31:42176bc3c368 359 /* ADC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 360 /** Peripheral ADC0 base address */
mbed_official 31:42176bc3c368 361 #define ADC0_BASE (0x4003B000u)
mbed_official 31:42176bc3c368 362 /** Peripheral ADC0 base pointer */
mbed_official 31:42176bc3c368 363 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 31:42176bc3c368 364 /** Array initializer of ADC peripheral base pointers */
mbed_official 31:42176bc3c368 365 #define ADC_BASES { ADC0 }
mbed_official 31:42176bc3c368 366
mbed_official 31:42176bc3c368 367 /**
mbed_official 31:42176bc3c368 368 * @}
mbed_official 31:42176bc3c368 369 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 370
mbed_official 31:42176bc3c368 371
mbed_official 31:42176bc3c368 372 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 373 -- CMP Peripheral Access Layer
mbed_official 31:42176bc3c368 374 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 375
mbed_official 31:42176bc3c368 376 /**
mbed_official 31:42176bc3c368 377 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 31:42176bc3c368 378 * @{
mbed_official 31:42176bc3c368 379 */
mbed_official 31:42176bc3c368 380
mbed_official 31:42176bc3c368 381 /** CMP - Register Layout Typedef */
mbed_official 31:42176bc3c368 382 typedef struct {
mbed_official 31:42176bc3c368 383 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 31:42176bc3c368 384 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 31:42176bc3c368 385 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 31:42176bc3c368 386 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 31:42176bc3c368 387 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 31:42176bc3c368 388 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 31:42176bc3c368 389 } CMP_Type;
mbed_official 31:42176bc3c368 390
mbed_official 31:42176bc3c368 391 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 392 -- CMP Register Masks
mbed_official 31:42176bc3c368 393 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 394
mbed_official 31:42176bc3c368 395 /**
mbed_official 31:42176bc3c368 396 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 31:42176bc3c368 397 * @{
mbed_official 31:42176bc3c368 398 */
mbed_official 31:42176bc3c368 399
mbed_official 31:42176bc3c368 400 /* CR0 Bit Fields */
mbed_official 31:42176bc3c368 401 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 31:42176bc3c368 402 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 31:42176bc3c368 403 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 31:42176bc3c368 404 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 31:42176bc3c368 405 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 31:42176bc3c368 406 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 31:42176bc3c368 407 /* CR1 Bit Fields */
mbed_official 31:42176bc3c368 408 #define CMP_CR1_EN_MASK 0x1u
mbed_official 31:42176bc3c368 409 #define CMP_CR1_EN_SHIFT 0
mbed_official 31:42176bc3c368 410 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 31:42176bc3c368 411 #define CMP_CR1_OPE_SHIFT 1
mbed_official 31:42176bc3c368 412 #define CMP_CR1_COS_MASK 0x4u
mbed_official 31:42176bc3c368 413 #define CMP_CR1_COS_SHIFT 2
mbed_official 31:42176bc3c368 414 #define CMP_CR1_INV_MASK 0x8u
mbed_official 31:42176bc3c368 415 #define CMP_CR1_INV_SHIFT 3
mbed_official 31:42176bc3c368 416 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 31:42176bc3c368 417 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 31:42176bc3c368 418 #define CMP_CR1_TRIGM_MASK 0x20u
mbed_official 31:42176bc3c368 419 #define CMP_CR1_TRIGM_SHIFT 5
mbed_official 31:42176bc3c368 420 #define CMP_CR1_WE_MASK 0x40u
mbed_official 31:42176bc3c368 421 #define CMP_CR1_WE_SHIFT 6
mbed_official 31:42176bc3c368 422 #define CMP_CR1_SE_MASK 0x80u
mbed_official 31:42176bc3c368 423 #define CMP_CR1_SE_SHIFT 7
mbed_official 31:42176bc3c368 424 /* FPR Bit Fields */
mbed_official 31:42176bc3c368 425 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 31:42176bc3c368 426 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 31:42176bc3c368 427 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 31:42176bc3c368 428 /* SCR Bit Fields */
mbed_official 31:42176bc3c368 429 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 31:42176bc3c368 430 #define CMP_SCR_COUT_SHIFT 0
mbed_official 31:42176bc3c368 431 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 31:42176bc3c368 432 #define CMP_SCR_CFF_SHIFT 1
mbed_official 31:42176bc3c368 433 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 31:42176bc3c368 434 #define CMP_SCR_CFR_SHIFT 2
mbed_official 31:42176bc3c368 435 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 31:42176bc3c368 436 #define CMP_SCR_IEF_SHIFT 3
mbed_official 31:42176bc3c368 437 #define CMP_SCR_IER_MASK 0x10u
mbed_official 31:42176bc3c368 438 #define CMP_SCR_IER_SHIFT 4
mbed_official 31:42176bc3c368 439 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 31:42176bc3c368 440 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 31:42176bc3c368 441 /* DACCR Bit Fields */
mbed_official 31:42176bc3c368 442 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 31:42176bc3c368 443 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 31:42176bc3c368 444 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 31:42176bc3c368 445 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 31:42176bc3c368 446 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 31:42176bc3c368 447 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 31:42176bc3c368 448 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 31:42176bc3c368 449 /* MUXCR Bit Fields */
mbed_official 31:42176bc3c368 450 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 31:42176bc3c368 451 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 31:42176bc3c368 452 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 31:42176bc3c368 453 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 31:42176bc3c368 454 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 31:42176bc3c368 455 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 44:2ce89a25b635 456 #define CMP_MUXCR_PSTM_MASK 0x80u
mbed_official 44:2ce89a25b635 457 #define CMP_MUXCR_PSTM_SHIFT 7
mbed_official 31:42176bc3c368 458
mbed_official 31:42176bc3c368 459 /**
mbed_official 31:42176bc3c368 460 * @}
mbed_official 31:42176bc3c368 461 */ /* end of group CMP_Register_Masks */
mbed_official 31:42176bc3c368 462
mbed_official 31:42176bc3c368 463
mbed_official 31:42176bc3c368 464 /* CMP - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 465 /** Peripheral CMP0 base address */
mbed_official 31:42176bc3c368 466 #define CMP0_BASE (0x40073000u)
mbed_official 31:42176bc3c368 467 /** Peripheral CMP0 base pointer */
mbed_official 31:42176bc3c368 468 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 31:42176bc3c368 469 /** Array initializer of CMP peripheral base pointers */
mbed_official 31:42176bc3c368 470 #define CMP_BASES { CMP0 }
mbed_official 31:42176bc3c368 471
mbed_official 31:42176bc3c368 472 /**
mbed_official 31:42176bc3c368 473 * @}
mbed_official 31:42176bc3c368 474 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 475
mbed_official 31:42176bc3c368 476
mbed_official 31:42176bc3c368 477 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 478 -- DAC Peripheral Access Layer
mbed_official 31:42176bc3c368 479 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 480
mbed_official 31:42176bc3c368 481 /**
mbed_official 31:42176bc3c368 482 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 31:42176bc3c368 483 * @{
mbed_official 31:42176bc3c368 484 */
mbed_official 31:42176bc3c368 485
mbed_official 31:42176bc3c368 486 /** DAC - Register Layout Typedef */
mbed_official 31:42176bc3c368 487 typedef struct {
mbed_official 31:42176bc3c368 488 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 31:42176bc3c368 489 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 31:42176bc3c368 490 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 31:42176bc3c368 491 } DAT[2];
mbed_official 31:42176bc3c368 492 uint8_t RESERVED_0[28];
mbed_official 31:42176bc3c368 493 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 31:42176bc3c368 494 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 31:42176bc3c368 495 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 31:42176bc3c368 496 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 31:42176bc3c368 497 } DAC_Type;
mbed_official 31:42176bc3c368 498
mbed_official 31:42176bc3c368 499 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 500 -- DAC Register Masks
mbed_official 31:42176bc3c368 501 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 502
mbed_official 31:42176bc3c368 503 /**
mbed_official 31:42176bc3c368 504 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 31:42176bc3c368 505 * @{
mbed_official 31:42176bc3c368 506 */
mbed_official 31:42176bc3c368 507
mbed_official 31:42176bc3c368 508 /* DATL Bit Fields */
mbed_official 31:42176bc3c368 509 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 31:42176bc3c368 510 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 31:42176bc3c368 511 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 31:42176bc3c368 512 /* DATH Bit Fields */
mbed_official 31:42176bc3c368 513 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 31:42176bc3c368 514 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 31:42176bc3c368 515 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 31:42176bc3c368 516 /* SR Bit Fields */
mbed_official 31:42176bc3c368 517 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 31:42176bc3c368 518 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 31:42176bc3c368 519 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 31:42176bc3c368 520 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 31:42176bc3c368 521 /* C0 Bit Fields */
mbed_official 31:42176bc3c368 522 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 31:42176bc3c368 523 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 31:42176bc3c368 524 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 31:42176bc3c368 525 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 31:42176bc3c368 526 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 31:42176bc3c368 527 #define DAC_C0_LPEN_SHIFT 3
mbed_official 31:42176bc3c368 528 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 31:42176bc3c368 529 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 31:42176bc3c368 530 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 31:42176bc3c368 531 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 31:42176bc3c368 532 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 31:42176bc3c368 533 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 31:42176bc3c368 534 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 31:42176bc3c368 535 #define DAC_C0_DACEN_SHIFT 7
mbed_official 31:42176bc3c368 536 /* C1 Bit Fields */
mbed_official 31:42176bc3c368 537 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 31:42176bc3c368 538 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 31:42176bc3c368 539 #define DAC_C1_DACBFMD_MASK 0x4u
mbed_official 31:42176bc3c368 540 #define DAC_C1_DACBFMD_SHIFT 2
mbed_official 31:42176bc3c368 541 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 31:42176bc3c368 542 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 31:42176bc3c368 543 /* C2 Bit Fields */
mbed_official 31:42176bc3c368 544 #define DAC_C2_DACBFUP_MASK 0x1u
mbed_official 31:42176bc3c368 545 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 31:42176bc3c368 546 #define DAC_C2_DACBFRP_MASK 0x10u
mbed_official 31:42176bc3c368 547 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 31:42176bc3c368 548
mbed_official 31:42176bc3c368 549 /**
mbed_official 31:42176bc3c368 550 * @}
mbed_official 31:42176bc3c368 551 */ /* end of group DAC_Register_Masks */
mbed_official 31:42176bc3c368 552
mbed_official 31:42176bc3c368 553
mbed_official 31:42176bc3c368 554 /* DAC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 555 /** Peripheral DAC0 base address */
mbed_official 31:42176bc3c368 556 #define DAC0_BASE (0x4003F000u)
mbed_official 31:42176bc3c368 557 /** Peripheral DAC0 base pointer */
mbed_official 31:42176bc3c368 558 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 31:42176bc3c368 559 /** Array initializer of DAC peripheral base pointers */
mbed_official 31:42176bc3c368 560 #define DAC_BASES { DAC0 }
mbed_official 31:42176bc3c368 561
mbed_official 31:42176bc3c368 562 /**
mbed_official 31:42176bc3c368 563 * @}
mbed_official 31:42176bc3c368 564 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 565
mbed_official 31:42176bc3c368 566
mbed_official 31:42176bc3c368 567 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 568 -- DMA Peripheral Access Layer
mbed_official 31:42176bc3c368 569 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 570
mbed_official 31:42176bc3c368 571 /**
mbed_official 31:42176bc3c368 572 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 31:42176bc3c368 573 * @{
mbed_official 31:42176bc3c368 574 */
mbed_official 31:42176bc3c368 575
mbed_official 31:42176bc3c368 576 /** DMA - Register Layout Typedef */
mbed_official 31:42176bc3c368 577 typedef struct {
mbed_official 44:2ce89a25b635 578 uint8_t RESERVED_0[256];
mbed_official 31:42176bc3c368 579 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 31:42176bc3c368 580 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
mbed_official 31:42176bc3c368 581 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
mbed_official 31:42176bc3c368 582 union { /* offset: 0x108, array step: 0x10 */
mbed_official 31:42176bc3c368 583 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
mbed_official 31:42176bc3c368 584 struct { /* offset: 0x108, array step: 0x10 */
mbed_official 31:42176bc3c368 585 uint8_t RESERVED_0[3];
mbed_official 31:42176bc3c368 586 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
mbed_official 31:42176bc3c368 587 } DMA_DSR_ACCESS8BIT;
mbed_official 31:42176bc3c368 588 };
mbed_official 31:42176bc3c368 589 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
mbed_official 31:42176bc3c368 590 } DMA[4];
mbed_official 31:42176bc3c368 591 } DMA_Type;
mbed_official 31:42176bc3c368 592
mbed_official 31:42176bc3c368 593 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 594 -- DMA Register Masks
mbed_official 31:42176bc3c368 595 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 596
mbed_official 31:42176bc3c368 597 /**
mbed_official 31:42176bc3c368 598 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 31:42176bc3c368 599 * @{
mbed_official 31:42176bc3c368 600 */
mbed_official 31:42176bc3c368 601
mbed_official 31:42176bc3c368 602 /* SAR Bit Fields */
mbed_official 31:42176bc3c368 603 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 604 #define DMA_SAR_SAR_SHIFT 0
mbed_official 31:42176bc3c368 605 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
mbed_official 31:42176bc3c368 606 /* DAR Bit Fields */
mbed_official 31:42176bc3c368 607 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 608 #define DMA_DAR_DAR_SHIFT 0
mbed_official 31:42176bc3c368 609 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
mbed_official 31:42176bc3c368 610 /* DSR_BCR Bit Fields */
mbed_official 31:42176bc3c368 611 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
mbed_official 31:42176bc3c368 612 #define DMA_DSR_BCR_BCR_SHIFT 0
mbed_official 31:42176bc3c368 613 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
mbed_official 31:42176bc3c368 614 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
mbed_official 31:42176bc3c368 615 #define DMA_DSR_BCR_DONE_SHIFT 24
mbed_official 31:42176bc3c368 616 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
mbed_official 31:42176bc3c368 617 #define DMA_DSR_BCR_BSY_SHIFT 25
mbed_official 31:42176bc3c368 618 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
mbed_official 31:42176bc3c368 619 #define DMA_DSR_BCR_REQ_SHIFT 26
mbed_official 31:42176bc3c368 620 #define DMA_DSR_BCR_BED_MASK 0x10000000u
mbed_official 31:42176bc3c368 621 #define DMA_DSR_BCR_BED_SHIFT 28
mbed_official 31:42176bc3c368 622 #define DMA_DSR_BCR_BES_MASK 0x20000000u
mbed_official 31:42176bc3c368 623 #define DMA_DSR_BCR_BES_SHIFT 29
mbed_official 31:42176bc3c368 624 #define DMA_DSR_BCR_CE_MASK 0x40000000u
mbed_official 31:42176bc3c368 625 #define DMA_DSR_BCR_CE_SHIFT 30
mbed_official 31:42176bc3c368 626 /* DCR Bit Fields */
mbed_official 31:42176bc3c368 627 #define DMA_DCR_LCH2_MASK 0x3u
mbed_official 31:42176bc3c368 628 #define DMA_DCR_LCH2_SHIFT 0
mbed_official 31:42176bc3c368 629 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
mbed_official 31:42176bc3c368 630 #define DMA_DCR_LCH1_MASK 0xCu
mbed_official 31:42176bc3c368 631 #define DMA_DCR_LCH1_SHIFT 2
mbed_official 31:42176bc3c368 632 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
mbed_official 31:42176bc3c368 633 #define DMA_DCR_LINKCC_MASK 0x30u
mbed_official 31:42176bc3c368 634 #define DMA_DCR_LINKCC_SHIFT 4
mbed_official 31:42176bc3c368 635 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
mbed_official 31:42176bc3c368 636 #define DMA_DCR_D_REQ_MASK 0x80u
mbed_official 31:42176bc3c368 637 #define DMA_DCR_D_REQ_SHIFT 7
mbed_official 31:42176bc3c368 638 #define DMA_DCR_DMOD_MASK 0xF00u
mbed_official 31:42176bc3c368 639 #define DMA_DCR_DMOD_SHIFT 8
mbed_official 31:42176bc3c368 640 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
mbed_official 31:42176bc3c368 641 #define DMA_DCR_SMOD_MASK 0xF000u
mbed_official 31:42176bc3c368 642 #define DMA_DCR_SMOD_SHIFT 12
mbed_official 31:42176bc3c368 643 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
mbed_official 31:42176bc3c368 644 #define DMA_DCR_START_MASK 0x10000u
mbed_official 31:42176bc3c368 645 #define DMA_DCR_START_SHIFT 16
mbed_official 31:42176bc3c368 646 #define DMA_DCR_DSIZE_MASK 0x60000u
mbed_official 31:42176bc3c368 647 #define DMA_DCR_DSIZE_SHIFT 17
mbed_official 31:42176bc3c368 648 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
mbed_official 31:42176bc3c368 649 #define DMA_DCR_DINC_MASK 0x80000u
mbed_official 31:42176bc3c368 650 #define DMA_DCR_DINC_SHIFT 19
mbed_official 31:42176bc3c368 651 #define DMA_DCR_SSIZE_MASK 0x300000u
mbed_official 31:42176bc3c368 652 #define DMA_DCR_SSIZE_SHIFT 20
mbed_official 31:42176bc3c368 653 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
mbed_official 31:42176bc3c368 654 #define DMA_DCR_SINC_MASK 0x400000u
mbed_official 31:42176bc3c368 655 #define DMA_DCR_SINC_SHIFT 22
mbed_official 31:42176bc3c368 656 #define DMA_DCR_EADREQ_MASK 0x800000u
mbed_official 31:42176bc3c368 657 #define DMA_DCR_EADREQ_SHIFT 23
mbed_official 31:42176bc3c368 658 #define DMA_DCR_AA_MASK 0x10000000u
mbed_official 31:42176bc3c368 659 #define DMA_DCR_AA_SHIFT 28
mbed_official 31:42176bc3c368 660 #define DMA_DCR_CS_MASK 0x20000000u
mbed_official 31:42176bc3c368 661 #define DMA_DCR_CS_SHIFT 29
mbed_official 31:42176bc3c368 662 #define DMA_DCR_ERQ_MASK 0x40000000u
mbed_official 31:42176bc3c368 663 #define DMA_DCR_ERQ_SHIFT 30
mbed_official 31:42176bc3c368 664 #define DMA_DCR_EINT_MASK 0x80000000u
mbed_official 31:42176bc3c368 665 #define DMA_DCR_EINT_SHIFT 31
mbed_official 31:42176bc3c368 666
mbed_official 31:42176bc3c368 667 /**
mbed_official 31:42176bc3c368 668 * @}
mbed_official 31:42176bc3c368 669 */ /* end of group DMA_Register_Masks */
mbed_official 31:42176bc3c368 670
mbed_official 31:42176bc3c368 671
mbed_official 31:42176bc3c368 672 /* DMA - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 673 /** Peripheral DMA base address */
mbed_official 31:42176bc3c368 674 #define DMA_BASE (0x40008000u)
mbed_official 31:42176bc3c368 675 /** Peripheral DMA base pointer */
mbed_official 31:42176bc3c368 676 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 31:42176bc3c368 677 /** Array initializer of DMA peripheral base pointers */
mbed_official 31:42176bc3c368 678 #define DMA_BASES { DMA0 }
mbed_official 31:42176bc3c368 679
mbed_official 31:42176bc3c368 680 /**
mbed_official 31:42176bc3c368 681 * @}
mbed_official 31:42176bc3c368 682 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 683
mbed_official 31:42176bc3c368 684
mbed_official 31:42176bc3c368 685 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 686 -- DMAMUX Peripheral Access Layer
mbed_official 31:42176bc3c368 687 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 688
mbed_official 31:42176bc3c368 689 /**
mbed_official 31:42176bc3c368 690 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 31:42176bc3c368 691 * @{
mbed_official 31:42176bc3c368 692 */
mbed_official 31:42176bc3c368 693
mbed_official 31:42176bc3c368 694 /** DMAMUX - Register Layout Typedef */
mbed_official 31:42176bc3c368 695 typedef struct {
mbed_official 31:42176bc3c368 696 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 31:42176bc3c368 697 } DMAMUX_Type;
mbed_official 31:42176bc3c368 698
mbed_official 31:42176bc3c368 699 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 700 -- DMAMUX Register Masks
mbed_official 31:42176bc3c368 701 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 702
mbed_official 31:42176bc3c368 703 /**
mbed_official 31:42176bc3c368 704 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 31:42176bc3c368 705 * @{
mbed_official 31:42176bc3c368 706 */
mbed_official 31:42176bc3c368 707
mbed_official 31:42176bc3c368 708 /* CHCFG Bit Fields */
mbed_official 31:42176bc3c368 709 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 31:42176bc3c368 710 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 31:42176bc3c368 711 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 31:42176bc3c368 712 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 31:42176bc3c368 713 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 31:42176bc3c368 714 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 31:42176bc3c368 715 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 31:42176bc3c368 716
mbed_official 31:42176bc3c368 717 /**
mbed_official 31:42176bc3c368 718 * @}
mbed_official 31:42176bc3c368 719 */ /* end of group DMAMUX_Register_Masks */
mbed_official 31:42176bc3c368 720
mbed_official 31:42176bc3c368 721
mbed_official 31:42176bc3c368 722 /* DMAMUX - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 723 /** Peripheral DMAMUX0 base address */
mbed_official 31:42176bc3c368 724 #define DMAMUX0_BASE (0x40021000u)
mbed_official 31:42176bc3c368 725 /** Peripheral DMAMUX0 base pointer */
mbed_official 31:42176bc3c368 726 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
mbed_official 31:42176bc3c368 727 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 31:42176bc3c368 728 #define DMAMUX_BASES { DMAMUX0 }
mbed_official 31:42176bc3c368 729
mbed_official 31:42176bc3c368 730 /**
mbed_official 31:42176bc3c368 731 * @}
mbed_official 31:42176bc3c368 732 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 733
mbed_official 31:42176bc3c368 734
mbed_official 31:42176bc3c368 735 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 736 -- FGPIO Peripheral Access Layer
mbed_official 31:42176bc3c368 737 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 738
mbed_official 31:42176bc3c368 739 /**
mbed_official 31:42176bc3c368 740 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
mbed_official 31:42176bc3c368 741 * @{
mbed_official 31:42176bc3c368 742 */
mbed_official 31:42176bc3c368 743
mbed_official 31:42176bc3c368 744 /** FGPIO - Register Layout Typedef */
mbed_official 31:42176bc3c368 745 typedef struct {
mbed_official 31:42176bc3c368 746 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 31:42176bc3c368 747 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 31:42176bc3c368 748 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 31:42176bc3c368 749 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 31:42176bc3c368 750 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 31:42176bc3c368 751 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 31:42176bc3c368 752 } FGPIO_Type;
mbed_official 31:42176bc3c368 753
mbed_official 31:42176bc3c368 754 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 755 -- FGPIO Register Masks
mbed_official 31:42176bc3c368 756 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 757
mbed_official 31:42176bc3c368 758 /**
mbed_official 31:42176bc3c368 759 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
mbed_official 31:42176bc3c368 760 * @{
mbed_official 31:42176bc3c368 761 */
mbed_official 31:42176bc3c368 762
mbed_official 31:42176bc3c368 763 /* PDOR Bit Fields */
mbed_official 31:42176bc3c368 764 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 765 #define FGPIO_PDOR_PDO_SHIFT 0
mbed_official 31:42176bc3c368 766 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
mbed_official 31:42176bc3c368 767 /* PSOR Bit Fields */
mbed_official 31:42176bc3c368 768 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 769 #define FGPIO_PSOR_PTSO_SHIFT 0
mbed_official 31:42176bc3c368 770 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
mbed_official 31:42176bc3c368 771 /* PCOR Bit Fields */
mbed_official 31:42176bc3c368 772 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 773 #define FGPIO_PCOR_PTCO_SHIFT 0
mbed_official 31:42176bc3c368 774 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
mbed_official 31:42176bc3c368 775 /* PTOR Bit Fields */
mbed_official 31:42176bc3c368 776 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 777 #define FGPIO_PTOR_PTTO_SHIFT 0
mbed_official 31:42176bc3c368 778 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
mbed_official 31:42176bc3c368 779 /* PDIR Bit Fields */
mbed_official 31:42176bc3c368 780 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 781 #define FGPIO_PDIR_PDI_SHIFT 0
mbed_official 31:42176bc3c368 782 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
mbed_official 31:42176bc3c368 783 /* PDDR Bit Fields */
mbed_official 31:42176bc3c368 784 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 785 #define FGPIO_PDDR_PDD_SHIFT 0
mbed_official 31:42176bc3c368 786 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
mbed_official 31:42176bc3c368 787
mbed_official 31:42176bc3c368 788 /**
mbed_official 31:42176bc3c368 789 * @}
mbed_official 31:42176bc3c368 790 */ /* end of group FGPIO_Register_Masks */
mbed_official 31:42176bc3c368 791
mbed_official 31:42176bc3c368 792
mbed_official 31:42176bc3c368 793 /* FGPIO - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 794 /** Peripheral FPTA base address */
mbed_official 31:42176bc3c368 795 #define FPTA_BASE (0xF80FF000u)
mbed_official 31:42176bc3c368 796 /** Peripheral FPTA base pointer */
mbed_official 31:42176bc3c368 797 #define FPTA ((FGPIO_Type *)FPTA_BASE)
mbed_official 31:42176bc3c368 798 /** Peripheral FPTB base address */
mbed_official 31:42176bc3c368 799 #define FPTB_BASE (0xF80FF040u)
mbed_official 31:42176bc3c368 800 /** Peripheral FPTB base pointer */
mbed_official 31:42176bc3c368 801 #define FPTB ((FGPIO_Type *)FPTB_BASE)
mbed_official 31:42176bc3c368 802 /** Peripheral FPTC base address */
mbed_official 31:42176bc3c368 803 #define FPTC_BASE (0xF80FF080u)
mbed_official 31:42176bc3c368 804 /** Peripheral FPTC base pointer */
mbed_official 31:42176bc3c368 805 #define FPTC ((FGPIO_Type *)FPTC_BASE)
mbed_official 31:42176bc3c368 806 /** Peripheral FPTD base address */
mbed_official 31:42176bc3c368 807 #define FPTD_BASE (0xF80FF0C0u)
mbed_official 31:42176bc3c368 808 /** Peripheral FPTD base pointer */
mbed_official 31:42176bc3c368 809 #define FPTD ((FGPIO_Type *)FPTD_BASE)
mbed_official 31:42176bc3c368 810 /** Peripheral FPTE base address */
mbed_official 31:42176bc3c368 811 #define FPTE_BASE (0xF80FF100u)
mbed_official 31:42176bc3c368 812 /** Peripheral FPTE base pointer */
mbed_official 31:42176bc3c368 813 #define FPTE ((FGPIO_Type *)FPTE_BASE)
mbed_official 31:42176bc3c368 814 /** Array initializer of FGPIO peripheral base pointers */
mbed_official 31:42176bc3c368 815 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
mbed_official 31:42176bc3c368 816
mbed_official 31:42176bc3c368 817 /**
mbed_official 31:42176bc3c368 818 * @}
mbed_official 31:42176bc3c368 819 */ /* end of group FGPIO_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 820
mbed_official 31:42176bc3c368 821
mbed_official 31:42176bc3c368 822 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 823 -- FTFA Peripheral Access Layer
mbed_official 31:42176bc3c368 824 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 825
mbed_official 31:42176bc3c368 826 /**
mbed_official 31:42176bc3c368 827 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mbed_official 31:42176bc3c368 828 * @{
mbed_official 31:42176bc3c368 829 */
mbed_official 31:42176bc3c368 830
mbed_official 31:42176bc3c368 831 /** FTFA - Register Layout Typedef */
mbed_official 31:42176bc3c368 832 typedef struct {
mbed_official 31:42176bc3c368 833 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 31:42176bc3c368 834 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 31:42176bc3c368 835 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 31:42176bc3c368 836 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 31:42176bc3c368 837 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 31:42176bc3c368 838 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 31:42176bc3c368 839 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 31:42176bc3c368 840 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 31:42176bc3c368 841 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 31:42176bc3c368 842 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 31:42176bc3c368 843 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 31:42176bc3c368 844 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 31:42176bc3c368 845 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 31:42176bc3c368 846 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 31:42176bc3c368 847 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 31:42176bc3c368 848 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 31:42176bc3c368 849 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 31:42176bc3c368 850 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 31:42176bc3c368 851 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 31:42176bc3c368 852 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 31:42176bc3c368 853 } FTFA_Type;
mbed_official 31:42176bc3c368 854
mbed_official 31:42176bc3c368 855 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 856 -- FTFA Register Masks
mbed_official 31:42176bc3c368 857 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 858
mbed_official 31:42176bc3c368 859 /**
mbed_official 31:42176bc3c368 860 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mbed_official 31:42176bc3c368 861 * @{
mbed_official 31:42176bc3c368 862 */
mbed_official 31:42176bc3c368 863
mbed_official 31:42176bc3c368 864 /* FSTAT Bit Fields */
mbed_official 31:42176bc3c368 865 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 31:42176bc3c368 866 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mbed_official 31:42176bc3c368 867 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mbed_official 31:42176bc3c368 868 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mbed_official 31:42176bc3c368 869 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mbed_official 31:42176bc3c368 870 #define FTFA_FSTAT_ACCERR_SHIFT 5
mbed_official 31:42176bc3c368 871 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 31:42176bc3c368 872 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mbed_official 31:42176bc3c368 873 #define FTFA_FSTAT_CCIF_MASK 0x80u
mbed_official 31:42176bc3c368 874 #define FTFA_FSTAT_CCIF_SHIFT 7
mbed_official 31:42176bc3c368 875 /* FCNFG Bit Fields */
mbed_official 31:42176bc3c368 876 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 31:42176bc3c368 877 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mbed_official 31:42176bc3c368 878 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 31:42176bc3c368 879 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mbed_official 31:42176bc3c368 880 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 31:42176bc3c368 881 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 31:42176bc3c368 882 #define FTFA_FCNFG_CCIE_MASK 0x80u
mbed_official 31:42176bc3c368 883 #define FTFA_FCNFG_CCIE_SHIFT 7
mbed_official 31:42176bc3c368 884 /* FSEC Bit Fields */
mbed_official 31:42176bc3c368 885 #define FTFA_FSEC_SEC_MASK 0x3u
mbed_official 31:42176bc3c368 886 #define FTFA_FSEC_SEC_SHIFT 0
mbed_official 31:42176bc3c368 887 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mbed_official 31:42176bc3c368 888 #define FTFA_FSEC_FSLACC_MASK 0xCu
mbed_official 31:42176bc3c368 889 #define FTFA_FSEC_FSLACC_SHIFT 2
mbed_official 31:42176bc3c368 890 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mbed_official 31:42176bc3c368 891 #define FTFA_FSEC_MEEN_MASK 0x30u
mbed_official 31:42176bc3c368 892 #define FTFA_FSEC_MEEN_SHIFT 4
mbed_official 31:42176bc3c368 893 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mbed_official 31:42176bc3c368 894 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mbed_official 31:42176bc3c368 895 #define FTFA_FSEC_KEYEN_SHIFT 6
mbed_official 31:42176bc3c368 896 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mbed_official 31:42176bc3c368 897 /* FOPT Bit Fields */
mbed_official 31:42176bc3c368 898 #define FTFA_FOPT_OPT_MASK 0xFFu
mbed_official 31:42176bc3c368 899 #define FTFA_FOPT_OPT_SHIFT 0
mbed_official 31:42176bc3c368 900 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mbed_official 31:42176bc3c368 901 /* FCCOB3 Bit Fields */
mbed_official 31:42176bc3c368 902 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 903 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 904 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mbed_official 31:42176bc3c368 905 /* FCCOB2 Bit Fields */
mbed_official 31:42176bc3c368 906 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 907 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 908 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mbed_official 31:42176bc3c368 909 /* FCCOB1 Bit Fields */
mbed_official 31:42176bc3c368 910 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 911 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 912 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mbed_official 31:42176bc3c368 913 /* FCCOB0 Bit Fields */
mbed_official 31:42176bc3c368 914 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 915 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 916 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mbed_official 31:42176bc3c368 917 /* FCCOB7 Bit Fields */
mbed_official 31:42176bc3c368 918 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 919 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 920 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mbed_official 31:42176bc3c368 921 /* FCCOB6 Bit Fields */
mbed_official 31:42176bc3c368 922 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 923 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 924 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mbed_official 31:42176bc3c368 925 /* FCCOB5 Bit Fields */
mbed_official 31:42176bc3c368 926 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 927 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 928 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mbed_official 31:42176bc3c368 929 /* FCCOB4 Bit Fields */
mbed_official 31:42176bc3c368 930 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 931 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 932 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mbed_official 31:42176bc3c368 933 /* FCCOBB Bit Fields */
mbed_official 31:42176bc3c368 934 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 935 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 936 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mbed_official 31:42176bc3c368 937 /* FCCOBA Bit Fields */
mbed_official 31:42176bc3c368 938 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 939 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 940 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mbed_official 31:42176bc3c368 941 /* FCCOB9 Bit Fields */
mbed_official 31:42176bc3c368 942 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 943 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 944 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mbed_official 31:42176bc3c368 945 /* FCCOB8 Bit Fields */
mbed_official 31:42176bc3c368 946 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 31:42176bc3c368 947 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mbed_official 31:42176bc3c368 948 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mbed_official 31:42176bc3c368 949 /* FPROT3 Bit Fields */
mbed_official 31:42176bc3c368 950 #define FTFA_FPROT3_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 951 #define FTFA_FPROT3_PROT_SHIFT 0
mbed_official 31:42176bc3c368 952 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mbed_official 31:42176bc3c368 953 /* FPROT2 Bit Fields */
mbed_official 31:42176bc3c368 954 #define FTFA_FPROT2_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 955 #define FTFA_FPROT2_PROT_SHIFT 0
mbed_official 31:42176bc3c368 956 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mbed_official 31:42176bc3c368 957 /* FPROT1 Bit Fields */
mbed_official 31:42176bc3c368 958 #define FTFA_FPROT1_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 959 #define FTFA_FPROT1_PROT_SHIFT 0
mbed_official 31:42176bc3c368 960 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mbed_official 31:42176bc3c368 961 /* FPROT0 Bit Fields */
mbed_official 31:42176bc3c368 962 #define FTFA_FPROT0_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 963 #define FTFA_FPROT0_PROT_SHIFT 0
mbed_official 31:42176bc3c368 964 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mbed_official 31:42176bc3c368 965
mbed_official 31:42176bc3c368 966 /**
mbed_official 31:42176bc3c368 967 * @}
mbed_official 31:42176bc3c368 968 */ /* end of group FTFA_Register_Masks */
mbed_official 31:42176bc3c368 969
mbed_official 31:42176bc3c368 970
mbed_official 31:42176bc3c368 971 /* FTFA - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 972 /** Peripheral FTFA base address */
mbed_official 31:42176bc3c368 973 #define FTFA_BASE (0x40020000u)
mbed_official 31:42176bc3c368 974 /** Peripheral FTFA base pointer */
mbed_official 31:42176bc3c368 975 #define FTFA ((FTFA_Type *)FTFA_BASE)
mbed_official 31:42176bc3c368 976 /** Array initializer of FTFA peripheral base pointers */
mbed_official 31:42176bc3c368 977 #define FTFA_BASES { FTFA }
mbed_official 31:42176bc3c368 978
mbed_official 31:42176bc3c368 979 /**
mbed_official 31:42176bc3c368 980 * @}
mbed_official 31:42176bc3c368 981 */ /* end of group FTFA_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 982
mbed_official 31:42176bc3c368 983
mbed_official 31:42176bc3c368 984 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 985 -- GPIO Peripheral Access Layer
mbed_official 31:42176bc3c368 986 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 987
mbed_official 31:42176bc3c368 988 /**
mbed_official 31:42176bc3c368 989 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 31:42176bc3c368 990 * @{
mbed_official 31:42176bc3c368 991 */
mbed_official 31:42176bc3c368 992
mbed_official 31:42176bc3c368 993 /** GPIO - Register Layout Typedef */
mbed_official 31:42176bc3c368 994 typedef struct {
mbed_official 31:42176bc3c368 995 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 31:42176bc3c368 996 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 31:42176bc3c368 997 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 31:42176bc3c368 998 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 31:42176bc3c368 999 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 31:42176bc3c368 1000 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 31:42176bc3c368 1001 } GPIO_Type;
mbed_official 31:42176bc3c368 1002
mbed_official 31:42176bc3c368 1003 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 1004 -- GPIO Register Masks
mbed_official 31:42176bc3c368 1005 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 1006
mbed_official 31:42176bc3c368 1007 /**
mbed_official 31:42176bc3c368 1008 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 31:42176bc3c368 1009 * @{
mbed_official 31:42176bc3c368 1010 */
mbed_official 31:42176bc3c368 1011
mbed_official 31:42176bc3c368 1012 /* PDOR Bit Fields */
mbed_official 31:42176bc3c368 1013 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1014 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 31:42176bc3c368 1015 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 31:42176bc3c368 1016 /* PSOR Bit Fields */
mbed_official 31:42176bc3c368 1017 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1018 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 31:42176bc3c368 1019 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 31:42176bc3c368 1020 /* PCOR Bit Fields */
mbed_official 31:42176bc3c368 1021 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1022 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 31:42176bc3c368 1023 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 31:42176bc3c368 1024 /* PTOR Bit Fields */
mbed_official 31:42176bc3c368 1025 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1026 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 31:42176bc3c368 1027 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 31:42176bc3c368 1028 /* PDIR Bit Fields */
mbed_official 31:42176bc3c368 1029 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1030 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 31:42176bc3c368 1031 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 31:42176bc3c368 1032 /* PDDR Bit Fields */
mbed_official 31:42176bc3c368 1033 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 1034 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 31:42176bc3c368 1035 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 31:42176bc3c368 1036
mbed_official 31:42176bc3c368 1037 /**
mbed_official 31:42176bc3c368 1038 * @}
mbed_official 31:42176bc3c368 1039 */ /* end of group GPIO_Register_Masks */
mbed_official 31:42176bc3c368 1040
mbed_official 31:42176bc3c368 1041
mbed_official 31:42176bc3c368 1042 /* GPIO - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 1043 /** Peripheral PTA base address */
mbed_official 31:42176bc3c368 1044 #define PTA_BASE (0x400FF000u)
mbed_official 31:42176bc3c368 1045 /** Peripheral PTA base pointer */
mbed_official 31:42176bc3c368 1046 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 31:42176bc3c368 1047 /** Peripheral PTB base address */
mbed_official 31:42176bc3c368 1048 #define PTB_BASE (0x400FF040u)
mbed_official 31:42176bc3c368 1049 /** Peripheral PTB base pointer */
mbed_official 31:42176bc3c368 1050 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 31:42176bc3c368 1051 /** Peripheral PTC base address */
mbed_official 31:42176bc3c368 1052 #define PTC_BASE (0x400FF080u)
mbed_official 31:42176bc3c368 1053 /** Peripheral PTC base pointer */
mbed_official 31:42176bc3c368 1054 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 31:42176bc3c368 1055 /** Peripheral PTD base address */
mbed_official 31:42176bc3c368 1056 #define PTD_BASE (0x400FF0C0u)
mbed_official 31:42176bc3c368 1057 /** Peripheral PTD base pointer */
mbed_official 31:42176bc3c368 1058 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 31:42176bc3c368 1059 /** Peripheral PTE base address */
mbed_official 31:42176bc3c368 1060 #define PTE_BASE (0x400FF100u)
mbed_official 31:42176bc3c368 1061 /** Peripheral PTE base pointer */
mbed_official 31:42176bc3c368 1062 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 31:42176bc3c368 1063 /** Array initializer of GPIO peripheral base pointers */
mbed_official 31:42176bc3c368 1064 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
mbed_official 31:42176bc3c368 1065
mbed_official 31:42176bc3c368 1066 /**
mbed_official 31:42176bc3c368 1067 * @}
mbed_official 31:42176bc3c368 1068 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 1069
mbed_official 31:42176bc3c368 1070
mbed_official 31:42176bc3c368 1071 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 1072 -- I2C Peripheral Access Layer
mbed_official 31:42176bc3c368 1073 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 1074
mbed_official 31:42176bc3c368 1075 /**
mbed_official 31:42176bc3c368 1076 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 31:42176bc3c368 1077 * @{
mbed_official 31:42176bc3c368 1078 */
mbed_official 31:42176bc3c368 1079
mbed_official 31:42176bc3c368 1080 /** I2C - Register Layout Typedef */
mbed_official 31:42176bc3c368 1081 typedef struct {
mbed_official 31:42176bc3c368 1082 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 31:42176bc3c368 1083 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 31:42176bc3c368 1084 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 31:42176bc3c368 1085 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 31:42176bc3c368 1086 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 31:42176bc3c368 1087 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 31:42176bc3c368 1088 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 31:42176bc3c368 1089 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 31:42176bc3c368 1090 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 31:42176bc3c368 1091 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 31:42176bc3c368 1092 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 31:42176bc3c368 1093 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 31:42176bc3c368 1094 } I2C_Type;
mbed_official 31:42176bc3c368 1095
mbed_official 31:42176bc3c368 1096 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 1097 -- I2C Register Masks
mbed_official 31:42176bc3c368 1098 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 1099
mbed_official 31:42176bc3c368 1100 /**
mbed_official 31:42176bc3c368 1101 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 31:42176bc3c368 1102 * @{
mbed_official 31:42176bc3c368 1103 */
mbed_official 31:42176bc3c368 1104
mbed_official 31:42176bc3c368 1105 /* A1 Bit Fields */
mbed_official 31:42176bc3c368 1106 #define I2C_A1_AD_MASK 0xFEu
mbed_official 31:42176bc3c368 1107 #define I2C_A1_AD_SHIFT 1
mbed_official 31:42176bc3c368 1108 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 31:42176bc3c368 1109 /* F Bit Fields */
mbed_official 31:42176bc3c368 1110 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 31:42176bc3c368 1111 #define I2C_F_ICR_SHIFT 0
mbed_official 31:42176bc3c368 1112 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 31:42176bc3c368 1113 #define I2C_F_MULT_MASK 0xC0u
mbed_official 31:42176bc3c368 1114 #define I2C_F_MULT_SHIFT 6
mbed_official 31:42176bc3c368 1115 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 31:42176bc3c368 1116 /* C1 Bit Fields */
mbed_official 31:42176bc3c368 1117 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 31:42176bc3c368 1118 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 31:42176bc3c368 1119 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 31:42176bc3c368 1120 #define I2C_C1_WUEN_SHIFT 1
mbed_official 31:42176bc3c368 1121 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 31:42176bc3c368 1122 #define I2C_C1_RSTA_SHIFT 2
mbed_official 31:42176bc3c368 1123 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 31:42176bc3c368 1124 #define I2C_C1_TXAK_SHIFT 3
mbed_official 31:42176bc3c368 1125 #define I2C_C1_TX_MASK 0x10u
mbed_official 31:42176bc3c368 1126 #define I2C_C1_TX_SHIFT 4
mbed_official 31:42176bc3c368 1127 #define I2C_C1_MST_MASK 0x20u
mbed_official 31:42176bc3c368 1128 #define I2C_C1_MST_SHIFT 5
mbed_official 31:42176bc3c368 1129 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 31:42176bc3c368 1130 #define I2C_C1_IICIE_SHIFT 6
mbed_official 31:42176bc3c368 1131 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 31:42176bc3c368 1132 #define I2C_C1_IICEN_SHIFT 7
mbed_official 31:42176bc3c368 1133 /* S Bit Fields */
mbed_official 31:42176bc3c368 1134 #define I2C_S_RXAK_MASK 0x1u
mbed_official 31:42176bc3c368 1135 #define I2C_S_RXAK_SHIFT 0
mbed_official 31:42176bc3c368 1136 #define I2C_S_IICIF_MASK 0x2u
mbed_official 31:42176bc3c368 1137 #define I2C_S_IICIF_SHIFT 1
mbed_official 31:42176bc3c368 1138 #define I2C_S_SRW_MASK 0x4u
mbed_official 31:42176bc3c368 1139 #define I2C_S_SRW_SHIFT 2
mbed_official 31:42176bc3c368 1140 #define I2C_S_RAM_MASK 0x8u
mbed_official 31:42176bc3c368 1141 #define I2C_S_RAM_SHIFT 3
mbed_official 31:42176bc3c368 1142 #define I2C_S_ARBL_MASK 0x10u
mbed_official 31:42176bc3c368 1143 #define I2C_S_ARBL_SHIFT 4
mbed_official 31:42176bc3c368 1144 #define I2C_S_BUSY_MASK 0x20u
mbed_official 31:42176bc3c368 1145 #define I2C_S_BUSY_SHIFT 5
mbed_official 31:42176bc3c368 1146 #define I2C_S_IAAS_MASK 0x40u
mbed_official 31:42176bc3c368 1147 #define I2C_S_IAAS_SHIFT 6
mbed_official 31:42176bc3c368 1148 #define I2C_S_TCF_MASK 0x80u
mbed_official 31:42176bc3c368 1149 #define I2C_S_TCF_SHIFT 7
mbed_official 31:42176bc3c368 1150 /* D Bit Fields */
mbed_official 31:42176bc3c368 1151 #define I2C_D_DATA_MASK 0xFFu
mbed_official 31:42176bc3c368 1152 #define I2C_D_DATA_SHIFT 0
mbed_official 31:42176bc3c368 1153 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 31:42176bc3c368 1154 /* C2 Bit Fields */
mbed_official 31:42176bc3c368 1155 #define I2C_C2_AD_MASK 0x7u
mbed_official 31:42176bc3c368 1156 #define I2C_C2_AD_SHIFT 0
mbed_official 31:42176bc3c368 1157 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 31:42176bc3c368 1158 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 31:42176bc3c368 1159 #define I2C_C2_RMEN_SHIFT 3
mbed_official 31:42176bc3c368 1160 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 31:42176bc3c368 1161 #define I2C_C2_SBRC_SHIFT 4
mbed_official 31:42176bc3c368 1162 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 31:42176bc3c368 1163 #define I2C_C2_HDRS_SHIFT 5
mbed_official 31:42176bc3c368 1164 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 31:42176bc3c368 1165 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 31:42176bc3c368 1166 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 31:42176bc3c368 1167 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 31:42176bc3c368 1168 /* FLT Bit Fields */
mbed_official 31:42176bc3c368 1169 #define I2C_FLT_FLT_MASK 0x1Fu
mbed_official 31:42176bc3c368 1170 #define I2C_FLT_FLT_SHIFT 0
mbed_official 31:42176bc3c368 1171 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 31:42176bc3c368 1172 #define I2C_FLT_STOPIE_MASK 0x20u
mbed_official 31:42176bc3c368 1173 #define I2C_FLT_STOPIE_SHIFT 5
mbed_official 31:42176bc3c368 1174 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 31:42176bc3c368 1175 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 31:42176bc3c368 1176 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 31:42176bc3c368 1177 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 31:42176bc3c368 1178 /* RA Bit Fields */
mbed_official 31:42176bc3c368 1179 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 31:42176bc3c368 1180 #define I2C_RA_RAD_SHIFT 1
mbed_official 31:42176bc3c368 1181 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 31:42176bc3c368 1182 /* SMB Bit Fields */
mbed_official 31:42176bc3c368 1183 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 31:42176bc3c368 1184 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 31:42176bc3c368 1185 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 31:42176bc3c368 1186 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 31:42176bc3c368 1187 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 31:42176bc3c368 1188 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 31:42176bc3c368 1189 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 31:42176bc3c368 1190 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 31:42176bc3c368 1191 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 31:42176bc3c368 1192 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 31:42176bc3c368 1193 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 31:42176bc3c368 1194 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 31:42176bc3c368 1195 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 31:42176bc3c368 1196 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 31:42176bc3c368 1197 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 31:42176bc3c368 1198 #define I2C_SMB_FACK_SHIFT 7
mbed_official 31:42176bc3c368 1199 /* A2 Bit Fields */
mbed_official 31:42176bc3c368 1200 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 31:42176bc3c368 1201 #define I2C_A2_SAD_SHIFT 1
mbed_official 31:42176bc3c368 1202 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 31:42176bc3c368 1203 /* SLTH Bit Fields */
mbed_official 31:42176bc3c368 1204 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 31:42176bc3c368 1205 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 31:42176bc3c368 1206 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 31:42176bc3c368 1207 /* SLTL Bit Fields */
mbed_official 31:42176bc3c368 1208 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 31:42176bc3c368 1209 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 31:42176bc3c368 1210 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 31:42176bc3c368 1211
mbed_official 31:42176bc3c368 1212 /**
mbed_official 31:42176bc3c368 1213 * @}
mbed_official 31:42176bc3c368 1214 */ /* end of group I2C_Register_Masks */
mbed_official 31:42176bc3c368 1215
mbed_official 31:42176bc3c368 1216
mbed_official 31:42176bc3c368 1217 /* I2C - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 1218 /** Peripheral I2C0 base address */
mbed_official 31:42176bc3c368 1219 #define I2C0_BASE (0x40066000u)
mbed_official 31:42176bc3c368 1220 /** Peripheral I2C0 base pointer */
mbed_official 31:42176bc3c368 1221 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 31:42176bc3c368 1222 /** Peripheral I2C1 base address */
mbed_official 31:42176bc3c368 1223 #define I2C1_BASE (0x40067000u)
mbed_official 31:42176bc3c368 1224 /** Peripheral I2C1 base pointer */
mbed_official 31:42176bc3c368 1225 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 31:42176bc3c368 1226 /** Array initializer of I2C peripheral base pointers */
mbed_official 31:42176bc3c368 1227 #define I2C_BASES { I2C0, I2C1 }
mbed_official 31:42176bc3c368 1228
mbed_official 31:42176bc3c368 1229 /**
mbed_official 31:42176bc3c368 1230 * @}
mbed_official 31:42176bc3c368 1231 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 1232
mbed_official 31:42176bc3c368 1233
mbed_official 31:42176bc3c368 1234 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 1235 -- I2S Peripheral Access Layer
mbed_official 44:2ce89a25b635 1236 ---------------------------------------------------------------------------- */
mbed_official 44:2ce89a25b635 1237
mbed_official 44:2ce89a25b635 1238 /**
mbed_official 44:2ce89a25b635 1239 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 44:2ce89a25b635 1240 * @{
mbed_official 44:2ce89a25b635 1241 */
mbed_official 44:2ce89a25b635 1242
mbed_official 44:2ce89a25b635 1243 /** I2S - Register Layout Typedef */
mbed_official 44:2ce89a25b635 1244 typedef struct {
mbed_official 44:2ce89a25b635 1245 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 44:2ce89a25b635 1246 uint8_t RESERVED_0[4];
mbed_official 44:2ce89a25b635 1247 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 44:2ce89a25b635 1248 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 44:2ce89a25b635 1249 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 44:2ce89a25b635 1250 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 44:2ce89a25b635 1251 uint8_t RESERVED_1[8];
mbed_official 44:2ce89a25b635 1252 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 44:2ce89a25b635 1253 uint8_t RESERVED_2[60];
mbed_official 44:2ce89a25b635 1254 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 44:2ce89a25b635 1255 uint8_t RESERVED_3[28];
mbed_official 44:2ce89a25b635 1256 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 44:2ce89a25b635 1257 uint8_t RESERVED_4[4];
mbed_official 44:2ce89a25b635 1258 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 44:2ce89a25b635 1259 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 44:2ce89a25b635 1260 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 44:2ce89a25b635 1261 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 44:2ce89a25b635 1262 uint8_t RESERVED_5[8];
mbed_official 44:2ce89a25b635 1263 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 44:2ce89a25b635 1264 uint8_t RESERVED_6[60];
mbed_official 44:2ce89a25b635 1265 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 44:2ce89a25b635 1266 uint8_t RESERVED_7[28];
mbed_official 44:2ce89a25b635 1267 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 44:2ce89a25b635 1268 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mbed_official 44:2ce89a25b635 1269 } I2S_Type;
mbed_official 44:2ce89a25b635 1270
mbed_official 44:2ce89a25b635 1271 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 1272 -- I2S Register Masks
mbed_official 44:2ce89a25b635 1273 ---------------------------------------------------------------------------- */
mbed_official 44:2ce89a25b635 1274
mbed_official 44:2ce89a25b635 1275 /**
mbed_official 44:2ce89a25b635 1276 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 44:2ce89a25b635 1277 * @{
mbed_official 44:2ce89a25b635 1278 */
mbed_official 44:2ce89a25b635 1279
mbed_official 44:2ce89a25b635 1280 /* TCSR Bit Fields */
mbed_official 44:2ce89a25b635 1281 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 44:2ce89a25b635 1282 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 44:2ce89a25b635 1283 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 44:2ce89a25b635 1284 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 44:2ce89a25b635 1285 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 44:2ce89a25b635 1286 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 44:2ce89a25b635 1287 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 44:2ce89a25b635 1288 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 44:2ce89a25b635 1289 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 44:2ce89a25b635 1290 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 44:2ce89a25b635 1291 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 44:2ce89a25b635 1292 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 44:2ce89a25b635 1293 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 44:2ce89a25b635 1294 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 44:2ce89a25b635 1295 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 44:2ce89a25b635 1296 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 44:2ce89a25b635 1297 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 44:2ce89a25b635 1298 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 44:2ce89a25b635 1299 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 44:2ce89a25b635 1300 #define I2S_TCSR_SR_SHIFT 24
mbed_official 44:2ce89a25b635 1301 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 44:2ce89a25b635 1302 #define I2S_TCSR_FR_SHIFT 25
mbed_official 44:2ce89a25b635 1303 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 44:2ce89a25b635 1304 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 44:2ce89a25b635 1305 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 44:2ce89a25b635 1306 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 44:2ce89a25b635 1307 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 44:2ce89a25b635 1308 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 44:2ce89a25b635 1309 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 44:2ce89a25b635 1310 #define I2S_TCSR_TE_SHIFT 31
mbed_official 44:2ce89a25b635 1311 /* TCR2 Bit Fields */
mbed_official 44:2ce89a25b635 1312 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 44:2ce89a25b635 1313 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 44:2ce89a25b635 1314 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 44:2ce89a25b635 1315 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 44:2ce89a25b635 1316 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 44:2ce89a25b635 1317 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 44:2ce89a25b635 1318 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 44:2ce89a25b635 1319 #define I2S_TCR2_CLKMODE_MASK 0xC000000u
mbed_official 44:2ce89a25b635 1320 #define I2S_TCR2_CLKMODE_SHIFT 26
mbed_official 44:2ce89a25b635 1321 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
mbed_official 44:2ce89a25b635 1322 /* TCR3 Bit Fields */
mbed_official 44:2ce89a25b635 1323 #define I2S_TCR3_WDFL_MASK 0x1u
mbed_official 44:2ce89a25b635 1324 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 44:2ce89a25b635 1325 #define I2S_TCR3_TCE_MASK 0x10000u
mbed_official 44:2ce89a25b635 1326 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 44:2ce89a25b635 1327 /* TCR4 Bit Fields */
mbed_official 44:2ce89a25b635 1328 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 44:2ce89a25b635 1329 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 44:2ce89a25b635 1330 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 44:2ce89a25b635 1331 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 44:2ce89a25b635 1332 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 44:2ce89a25b635 1333 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 44:2ce89a25b635 1334 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 44:2ce89a25b635 1335 #define I2S_TCR4_MF_SHIFT 4
mbed_official 44:2ce89a25b635 1336 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 44:2ce89a25b635 1337 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 44:2ce89a25b635 1338 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 44:2ce89a25b635 1339 #define I2S_TCR4_FRSZ_MASK 0x10000u
mbed_official 44:2ce89a25b635 1340 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 44:2ce89a25b635 1341 /* TCR5 Bit Fields */
mbed_official 44:2ce89a25b635 1342 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 44:2ce89a25b635 1343 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 44:2ce89a25b635 1344 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 44:2ce89a25b635 1345 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 44:2ce89a25b635 1346 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 44:2ce89a25b635 1347 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 44:2ce89a25b635 1348 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 44:2ce89a25b635 1349 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 44:2ce89a25b635 1350 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 44:2ce89a25b635 1351 /* TDR Bit Fields */
mbed_official 44:2ce89a25b635 1352 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 44:2ce89a25b635 1353 #define I2S_TDR_TDR_SHIFT 0
mbed_official 44:2ce89a25b635 1354 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 44:2ce89a25b635 1355 /* TMR Bit Fields */
mbed_official 44:2ce89a25b635 1356 #define I2S_TMR_TWM_MASK 0x3u
mbed_official 44:2ce89a25b635 1357 #define I2S_TMR_TWM_SHIFT 0
mbed_official 44:2ce89a25b635 1358 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 44:2ce89a25b635 1359 /* RCSR Bit Fields */
mbed_official 44:2ce89a25b635 1360 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 44:2ce89a25b635 1361 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 44:2ce89a25b635 1362 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 44:2ce89a25b635 1363 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 44:2ce89a25b635 1364 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 44:2ce89a25b635 1365 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 44:2ce89a25b635 1366 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 44:2ce89a25b635 1367 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 44:2ce89a25b635 1368 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 44:2ce89a25b635 1369 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 44:2ce89a25b635 1370 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 44:2ce89a25b635 1371 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 44:2ce89a25b635 1372 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 44:2ce89a25b635 1373 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 44:2ce89a25b635 1374 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 44:2ce89a25b635 1375 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 44:2ce89a25b635 1376 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 44:2ce89a25b635 1377 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 44:2ce89a25b635 1378 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 44:2ce89a25b635 1379 #define I2S_RCSR_SR_SHIFT 24
mbed_official 44:2ce89a25b635 1380 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 44:2ce89a25b635 1381 #define I2S_RCSR_FR_SHIFT 25
mbed_official 44:2ce89a25b635 1382 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 44:2ce89a25b635 1383 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 44:2ce89a25b635 1384 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 44:2ce89a25b635 1385 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 44:2ce89a25b635 1386 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 44:2ce89a25b635 1387 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 44:2ce89a25b635 1388 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 44:2ce89a25b635 1389 #define I2S_RCSR_RE_SHIFT 31
mbed_official 44:2ce89a25b635 1390 /* RCR2 Bit Fields */
mbed_official 44:2ce89a25b635 1391 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 44:2ce89a25b635 1392 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 44:2ce89a25b635 1393 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 44:2ce89a25b635 1394 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 44:2ce89a25b635 1395 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 44:2ce89a25b635 1396 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 44:2ce89a25b635 1397 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 44:2ce89a25b635 1398 #define I2S_RCR2_CLKMODE_MASK 0xC000000u
mbed_official 44:2ce89a25b635 1399 #define I2S_RCR2_CLKMODE_SHIFT 26
mbed_official 44:2ce89a25b635 1400 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
mbed_official 44:2ce89a25b635 1401 /* RCR3 Bit Fields */
mbed_official 44:2ce89a25b635 1402 #define I2S_RCR3_WDFL_MASK 0x1u
mbed_official 44:2ce89a25b635 1403 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 44:2ce89a25b635 1404 #define I2S_RCR3_RCE_MASK 0x10000u
mbed_official 44:2ce89a25b635 1405 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 44:2ce89a25b635 1406 /* RCR4 Bit Fields */
mbed_official 44:2ce89a25b635 1407 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 44:2ce89a25b635 1408 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 44:2ce89a25b635 1409 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 44:2ce89a25b635 1410 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 44:2ce89a25b635 1411 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 44:2ce89a25b635 1412 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 44:2ce89a25b635 1413 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 44:2ce89a25b635 1414 #define I2S_RCR4_MF_SHIFT 4
mbed_official 44:2ce89a25b635 1415 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 44:2ce89a25b635 1416 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 44:2ce89a25b635 1417 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 44:2ce89a25b635 1418 #define I2S_RCR4_FRSZ_MASK 0x10000u
mbed_official 44:2ce89a25b635 1419 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 44:2ce89a25b635 1420 /* RCR5 Bit Fields */
mbed_official 44:2ce89a25b635 1421 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 44:2ce89a25b635 1422 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 44:2ce89a25b635 1423 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 44:2ce89a25b635 1424 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 44:2ce89a25b635 1425 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 44:2ce89a25b635 1426 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 44:2ce89a25b635 1427 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 44:2ce89a25b635 1428 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 44:2ce89a25b635 1429 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 44:2ce89a25b635 1430 /* RDR Bit Fields */
mbed_official 44:2ce89a25b635 1431 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 44:2ce89a25b635 1432 #define I2S_RDR_RDR_SHIFT 0
mbed_official 44:2ce89a25b635 1433 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 44:2ce89a25b635 1434 /* RMR Bit Fields */
mbed_official 44:2ce89a25b635 1435 #define I2S_RMR_RWM_MASK 0x3u
mbed_official 44:2ce89a25b635 1436 #define I2S_RMR_RWM_SHIFT 0
mbed_official 44:2ce89a25b635 1437 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 44:2ce89a25b635 1438 /* MCR Bit Fields */
mbed_official 44:2ce89a25b635 1439 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 44:2ce89a25b635 1440 #define I2S_MCR_MICS_SHIFT 24
mbed_official 44:2ce89a25b635 1441 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 44:2ce89a25b635 1442 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 44:2ce89a25b635 1443 #define I2S_MCR_MOE_SHIFT 30
mbed_official 44:2ce89a25b635 1444 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 44:2ce89a25b635 1445 #define I2S_MCR_DUF_SHIFT 31
mbed_official 44:2ce89a25b635 1446 /* MDR Bit Fields */
mbed_official 44:2ce89a25b635 1447 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mbed_official 44:2ce89a25b635 1448 #define I2S_MDR_DIVIDE_SHIFT 0
mbed_official 44:2ce89a25b635 1449 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mbed_official 44:2ce89a25b635 1450 #define I2S_MDR_FRACT_MASK 0xFF000u
mbed_official 44:2ce89a25b635 1451 #define I2S_MDR_FRACT_SHIFT 12
mbed_official 44:2ce89a25b635 1452 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mbed_official 44:2ce89a25b635 1453
mbed_official 44:2ce89a25b635 1454 /**
mbed_official 44:2ce89a25b635 1455 * @}
mbed_official 44:2ce89a25b635 1456 */ /* end of group I2S_Register_Masks */
mbed_official 44:2ce89a25b635 1457
mbed_official 44:2ce89a25b635 1458
mbed_official 44:2ce89a25b635 1459 /* I2S - Peripheral instance base addresses */
mbed_official 44:2ce89a25b635 1460 /** Peripheral I2S0 base address */
mbed_official 44:2ce89a25b635 1461 #define I2S0_BASE (0x4002F000u)
mbed_official 44:2ce89a25b635 1462 /** Peripheral I2S0 base pointer */
mbed_official 44:2ce89a25b635 1463 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 44:2ce89a25b635 1464 /** Array initializer of I2S peripheral base pointers */
mbed_official 44:2ce89a25b635 1465 #define I2S_BASES { I2S0 }
mbed_official 44:2ce89a25b635 1466
mbed_official 44:2ce89a25b635 1467 /**
mbed_official 44:2ce89a25b635 1468 * @}
mbed_official 44:2ce89a25b635 1469 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 44:2ce89a25b635 1470
mbed_official 44:2ce89a25b635 1471
mbed_official 44:2ce89a25b635 1472 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 1473 -- LCD Peripheral Access Layer
mbed_official 44:2ce89a25b635 1474 ---------------------------------------------------------------------------- */
mbed_official 44:2ce89a25b635 1475
mbed_official 44:2ce89a25b635 1476 /**
mbed_official 44:2ce89a25b635 1477 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
mbed_official 44:2ce89a25b635 1478 * @{
mbed_official 44:2ce89a25b635 1479 */
mbed_official 44:2ce89a25b635 1480
mbed_official 44:2ce89a25b635 1481 /** LCD - Register Layout Typedef */
mbed_official 44:2ce89a25b635 1482 typedef struct {
mbed_official 44:2ce89a25b635 1483 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
mbed_official 44:2ce89a25b635 1484 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
mbed_official 44:2ce89a25b635 1485 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
mbed_official 44:2ce89a25b635 1486 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
mbed_official 44:2ce89a25b635 1487 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
mbed_official 44:2ce89a25b635 1488 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
mbed_official 44:2ce89a25b635 1489 union { /* offset: 0x20 */
mbed_official 44:2ce89a25b635 1490 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
mbed_official 44:2ce89a25b635 1491 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
mbed_official 44:2ce89a25b635 1492 };
mbed_official 44:2ce89a25b635 1493 } LCD_Type;
mbed_official 44:2ce89a25b635 1494
mbed_official 44:2ce89a25b635 1495 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 1496 -- LCD Register Masks
mbed_official 44:2ce89a25b635 1497 ---------------------------------------------------------------------------- */
mbed_official 44:2ce89a25b635 1498
mbed_official 44:2ce89a25b635 1499 /**
mbed_official 44:2ce89a25b635 1500 * @addtogroup LCD_Register_Masks LCD Register Masks
mbed_official 44:2ce89a25b635 1501 * @{
mbed_official 44:2ce89a25b635 1502 */
mbed_official 44:2ce89a25b635 1503
mbed_official 44:2ce89a25b635 1504 /* GCR Bit Fields */
mbed_official 44:2ce89a25b635 1505 #define LCD_GCR_DUTY_MASK 0x7u
mbed_official 44:2ce89a25b635 1506 #define LCD_GCR_DUTY_SHIFT 0
mbed_official 44:2ce89a25b635 1507 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
mbed_official 44:2ce89a25b635 1508 #define LCD_GCR_LCLK_MASK 0x38u
mbed_official 44:2ce89a25b635 1509 #define LCD_GCR_LCLK_SHIFT 3
mbed_official 44:2ce89a25b635 1510 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
mbed_official 44:2ce89a25b635 1511 #define LCD_GCR_SOURCE_MASK 0x40u
mbed_official 44:2ce89a25b635 1512 #define LCD_GCR_SOURCE_SHIFT 6
mbed_official 44:2ce89a25b635 1513 #define LCD_GCR_LCDEN_MASK 0x80u
mbed_official 44:2ce89a25b635 1514 #define LCD_GCR_LCDEN_SHIFT 7
mbed_official 44:2ce89a25b635 1515 #define LCD_GCR_LCDSTP_MASK 0x100u
mbed_official 44:2ce89a25b635 1516 #define LCD_GCR_LCDSTP_SHIFT 8
mbed_official 44:2ce89a25b635 1517 #define LCD_GCR_LCDDOZE_MASK 0x200u
mbed_official 44:2ce89a25b635 1518 #define LCD_GCR_LCDDOZE_SHIFT 9
mbed_official 44:2ce89a25b635 1519 #define LCD_GCR_FFR_MASK 0x400u
mbed_official 44:2ce89a25b635 1520 #define LCD_GCR_FFR_SHIFT 10
mbed_official 44:2ce89a25b635 1521 #define LCD_GCR_ALTSOURCE_MASK 0x800u
mbed_official 44:2ce89a25b635 1522 #define LCD_GCR_ALTSOURCE_SHIFT 11
mbed_official 44:2ce89a25b635 1523 #define LCD_GCR_ALTDIV_MASK 0x3000u
mbed_official 44:2ce89a25b635 1524 #define LCD_GCR_ALTDIV_SHIFT 12
mbed_official 44:2ce89a25b635 1525 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
mbed_official 44:2ce89a25b635 1526 #define LCD_GCR_FDCIEN_MASK 0x4000u
mbed_official 44:2ce89a25b635 1527 #define LCD_GCR_FDCIEN_SHIFT 14
mbed_official 44:2ce89a25b635 1528 #define LCD_GCR_PADSAFE_MASK 0x8000u
mbed_official 44:2ce89a25b635 1529 #define LCD_GCR_PADSAFE_SHIFT 15
mbed_official 44:2ce89a25b635 1530 #define LCD_GCR_VSUPPLY_MASK 0x20000u
mbed_official 44:2ce89a25b635 1531 #define LCD_GCR_VSUPPLY_SHIFT 17
mbed_official 44:2ce89a25b635 1532 #define LCD_GCR_LADJ_MASK 0x300000u
mbed_official 44:2ce89a25b635 1533 #define LCD_GCR_LADJ_SHIFT 20
mbed_official 44:2ce89a25b635 1534 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
mbed_official 44:2ce89a25b635 1535 #define LCD_GCR_CPSEL_MASK 0x800000u
mbed_official 44:2ce89a25b635 1536 #define LCD_GCR_CPSEL_SHIFT 23
mbed_official 44:2ce89a25b635 1537 #define LCD_GCR_RVTRIM_MASK 0xF000000u
mbed_official 44:2ce89a25b635 1538 #define LCD_GCR_RVTRIM_SHIFT 24
mbed_official 44:2ce89a25b635 1539 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
mbed_official 44:2ce89a25b635 1540 #define LCD_GCR_RVEN_MASK 0x80000000u
mbed_official 44:2ce89a25b635 1541 #define LCD_GCR_RVEN_SHIFT 31
mbed_official 44:2ce89a25b635 1542 /* AR Bit Fields */
mbed_official 44:2ce89a25b635 1543 #define LCD_AR_BRATE_MASK 0x7u
mbed_official 44:2ce89a25b635 1544 #define LCD_AR_BRATE_SHIFT 0
mbed_official 44:2ce89a25b635 1545 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
mbed_official 44:2ce89a25b635 1546 #define LCD_AR_BMODE_MASK 0x8u
mbed_official 44:2ce89a25b635 1547 #define LCD_AR_BMODE_SHIFT 3
mbed_official 44:2ce89a25b635 1548 #define LCD_AR_BLANK_MASK 0x20u
mbed_official 44:2ce89a25b635 1549 #define LCD_AR_BLANK_SHIFT 5
mbed_official 44:2ce89a25b635 1550 #define LCD_AR_ALT_MASK 0x40u
mbed_official 44:2ce89a25b635 1551 #define LCD_AR_ALT_SHIFT 6
mbed_official 44:2ce89a25b635 1552 #define LCD_AR_BLINK_MASK 0x80u
mbed_official 44:2ce89a25b635 1553 #define LCD_AR_BLINK_SHIFT 7
mbed_official 44:2ce89a25b635 1554 /* FDCR Bit Fields */
mbed_official 44:2ce89a25b635 1555 #define LCD_FDCR_FDPINID_MASK 0x3Fu
mbed_official 44:2ce89a25b635 1556 #define LCD_FDCR_FDPINID_SHIFT 0
mbed_official 44:2ce89a25b635 1557 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
mbed_official 44:2ce89a25b635 1558 #define LCD_FDCR_FDBPEN_MASK 0x40u
mbed_official 44:2ce89a25b635 1559 #define LCD_FDCR_FDBPEN_SHIFT 6
mbed_official 44:2ce89a25b635 1560 #define LCD_FDCR_FDEN_MASK 0x80u
mbed_official 44:2ce89a25b635 1561 #define LCD_FDCR_FDEN_SHIFT 7
mbed_official 44:2ce89a25b635 1562 #define LCD_FDCR_FDSWW_MASK 0xE00u
mbed_official 44:2ce89a25b635 1563 #define LCD_FDCR_FDSWW_SHIFT 9
mbed_official 44:2ce89a25b635 1564 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
mbed_official 44:2ce89a25b635 1565 #define LCD_FDCR_FDPRS_MASK 0x7000u
mbed_official 44:2ce89a25b635 1566 #define LCD_FDCR_FDPRS_SHIFT 12
mbed_official 44:2ce89a25b635 1567 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
mbed_official 44:2ce89a25b635 1568 /* FDSR Bit Fields */
mbed_official 44:2ce89a25b635 1569 #define LCD_FDSR_FDCNT_MASK 0xFFu
mbed_official 44:2ce89a25b635 1570 #define LCD_FDSR_FDCNT_SHIFT 0
mbed_official 44:2ce89a25b635 1571 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
mbed_official 44:2ce89a25b635 1572 #define LCD_FDSR_FDCF_MASK 0x8000u
mbed_official 44:2ce89a25b635 1573 #define LCD_FDSR_FDCF_SHIFT 15
mbed_official 44:2ce89a25b635 1574 /* PEN Bit Fields */
mbed_official 44:2ce89a25b635 1575 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
mbed_official 44:2ce89a25b635 1576 #define LCD_PEN_PEN_SHIFT 0
mbed_official 44:2ce89a25b635 1577 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
mbed_official 44:2ce89a25b635 1578 /* BPEN Bit Fields */
mbed_official 44:2ce89a25b635 1579 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
mbed_official 44:2ce89a25b635 1580 #define LCD_BPEN_BPEN_SHIFT 0
mbed_official 44:2ce89a25b635 1581 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
mbed_official 44:2ce89a25b635 1582 /* WF Bit Fields */
mbed_official 44:2ce89a25b635 1583 #define LCD_WF_WF0_MASK 0xFFu
mbed_official 44:2ce89a25b635 1584 #define LCD_WF_WF0_SHIFT 0
mbed_official 44:2ce89a25b635 1585 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
mbed_official 44:2ce89a25b635 1586 #define LCD_WF_WF60_MASK 0xFFu
mbed_official 44:2ce89a25b635 1587 #define LCD_WF_WF60_SHIFT 0
mbed_official 44:2ce89a25b635 1588 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
mbed_official 44:2ce89a25b635 1589 #define LCD_WF_WF56_MASK 0xFFu
mbed_official 44:2ce89a25b635 1590 #define LCD_WF_WF56_SHIFT 0
mbed_official 44:2ce89a25b635 1591 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
mbed_official 44:2ce89a25b635 1592 #define LCD_WF_WF52_MASK 0xFFu
mbed_official 44:2ce89a25b635 1593 #define LCD_WF_WF52_SHIFT 0
mbed_official 44:2ce89a25b635 1594 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
mbed_official 44:2ce89a25b635 1595 #define LCD_WF_WF4_MASK 0xFFu
mbed_official 44:2ce89a25b635 1596 #define LCD_WF_WF4_SHIFT 0
mbed_official 44:2ce89a25b635 1597 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
mbed_official 44:2ce89a25b635 1598 #define LCD_WF_WF48_MASK 0xFFu
mbed_official 44:2ce89a25b635 1599 #define LCD_WF_WF48_SHIFT 0
mbed_official 44:2ce89a25b635 1600 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
mbed_official 44:2ce89a25b635 1601 #define LCD_WF_WF44_MASK 0xFFu
mbed_official 44:2ce89a25b635 1602 #define LCD_WF_WF44_SHIFT 0
mbed_official 44:2ce89a25b635 1603 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
mbed_official 44:2ce89a25b635 1604 #define LCD_WF_WF40_MASK 0xFFu
mbed_official 44:2ce89a25b635 1605 #define LCD_WF_WF40_SHIFT 0
mbed_official 44:2ce89a25b635 1606 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
mbed_official 44:2ce89a25b635 1607 #define LCD_WF_WF8_MASK 0xFFu
mbed_official 44:2ce89a25b635 1608 #define LCD_WF_WF8_SHIFT 0
mbed_official 44:2ce89a25b635 1609 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
mbed_official 44:2ce89a25b635 1610 #define LCD_WF_WF36_MASK 0xFFu
mbed_official 44:2ce89a25b635 1611 #define LCD_WF_WF36_SHIFT 0
mbed_official 44:2ce89a25b635 1612 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
mbed_official 44:2ce89a25b635 1613 #define LCD_WF_WF32_MASK 0xFFu
mbed_official 44:2ce89a25b635 1614 #define LCD_WF_WF32_SHIFT 0
mbed_official 44:2ce89a25b635 1615 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
mbed_official 44:2ce89a25b635 1616 #define LCD_WF_WF28_MASK 0xFFu
mbed_official 44:2ce89a25b635 1617 #define LCD_WF_WF28_SHIFT 0
mbed_official 44:2ce89a25b635 1618 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
mbed_official 44:2ce89a25b635 1619 #define LCD_WF_WF12_MASK 0xFFu
mbed_official 44:2ce89a25b635 1620 #define LCD_WF_WF12_SHIFT 0
mbed_official 44:2ce89a25b635 1621 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
mbed_official 44:2ce89a25b635 1622 #define LCD_WF_WF24_MASK 0xFFu
mbed_official 44:2ce89a25b635 1623 #define LCD_WF_WF24_SHIFT 0
mbed_official 44:2ce89a25b635 1624 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
mbed_official 44:2ce89a25b635 1625 #define LCD_WF_WF20_MASK 0xFFu
mbed_official 44:2ce89a25b635 1626 #define LCD_WF_WF20_SHIFT 0
mbed_official 44:2ce89a25b635 1627 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
mbed_official 44:2ce89a25b635 1628 #define LCD_WF_WF16_MASK 0xFFu
mbed_official 44:2ce89a25b635 1629 #define LCD_WF_WF16_SHIFT 0
mbed_official 44:2ce89a25b635 1630 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
mbed_official 44:2ce89a25b635 1631 #define LCD_WF_WF5_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1632 #define LCD_WF_WF5_SHIFT 8
mbed_official 44:2ce89a25b635 1633 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
mbed_official 44:2ce89a25b635 1634 #define LCD_WF_WF49_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1635 #define LCD_WF_WF49_SHIFT 8
mbed_official 44:2ce89a25b635 1636 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
mbed_official 44:2ce89a25b635 1637 #define LCD_WF_WF45_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1638 #define LCD_WF_WF45_SHIFT 8
mbed_official 44:2ce89a25b635 1639 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
mbed_official 44:2ce89a25b635 1640 #define LCD_WF_WF61_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1641 #define LCD_WF_WF61_SHIFT 8
mbed_official 44:2ce89a25b635 1642 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
mbed_official 44:2ce89a25b635 1643 #define LCD_WF_WF25_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1644 #define LCD_WF_WF25_SHIFT 8
mbed_official 44:2ce89a25b635 1645 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
mbed_official 44:2ce89a25b635 1646 #define LCD_WF_WF17_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1647 #define LCD_WF_WF17_SHIFT 8
mbed_official 44:2ce89a25b635 1648 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
mbed_official 44:2ce89a25b635 1649 #define LCD_WF_WF41_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1650 #define LCD_WF_WF41_SHIFT 8
mbed_official 44:2ce89a25b635 1651 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
mbed_official 44:2ce89a25b635 1652 #define LCD_WF_WF13_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1653 #define LCD_WF_WF13_SHIFT 8
mbed_official 44:2ce89a25b635 1654 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
mbed_official 44:2ce89a25b635 1655 #define LCD_WF_WF57_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1656 #define LCD_WF_WF57_SHIFT 8
mbed_official 44:2ce89a25b635 1657 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
mbed_official 44:2ce89a25b635 1658 #define LCD_WF_WF53_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1659 #define LCD_WF_WF53_SHIFT 8
mbed_official 44:2ce89a25b635 1660 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
mbed_official 44:2ce89a25b635 1661 #define LCD_WF_WF37_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1662 #define LCD_WF_WF37_SHIFT 8
mbed_official 44:2ce89a25b635 1663 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
mbed_official 44:2ce89a25b635 1664 #define LCD_WF_WF9_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1665 #define LCD_WF_WF9_SHIFT 8
mbed_official 44:2ce89a25b635 1666 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
mbed_official 44:2ce89a25b635 1667 #define LCD_WF_WF1_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1668 #define LCD_WF_WF1_SHIFT 8
mbed_official 44:2ce89a25b635 1669 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
mbed_official 44:2ce89a25b635 1670 #define LCD_WF_WF29_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1671 #define LCD_WF_WF29_SHIFT 8
mbed_official 44:2ce89a25b635 1672 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
mbed_official 44:2ce89a25b635 1673 #define LCD_WF_WF33_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1674 #define LCD_WF_WF33_SHIFT 8
mbed_official 44:2ce89a25b635 1675 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
mbed_official 44:2ce89a25b635 1676 #define LCD_WF_WF21_MASK 0xFF00u
mbed_official 44:2ce89a25b635 1677 #define LCD_WF_WF21_SHIFT 8
mbed_official 44:2ce89a25b635 1678 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
mbed_official 44:2ce89a25b635 1679 #define LCD_WF_WF26_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1680 #define LCD_WF_WF26_SHIFT 16
mbed_official 44:2ce89a25b635 1681 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
mbed_official 44:2ce89a25b635 1682 #define LCD_WF_WF46_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1683 #define LCD_WF_WF46_SHIFT 16
mbed_official 44:2ce89a25b635 1684 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
mbed_official 44:2ce89a25b635 1685 #define LCD_WF_WF6_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1686 #define LCD_WF_WF6_SHIFT 16
mbed_official 44:2ce89a25b635 1687 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
mbed_official 44:2ce89a25b635 1688 #define LCD_WF_WF42_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1689 #define LCD_WF_WF42_SHIFT 16
mbed_official 44:2ce89a25b635 1690 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
mbed_official 44:2ce89a25b635 1691 #define LCD_WF_WF18_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1692 #define LCD_WF_WF18_SHIFT 16
mbed_official 44:2ce89a25b635 1693 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
mbed_official 44:2ce89a25b635 1694 #define LCD_WF_WF38_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1695 #define LCD_WF_WF38_SHIFT 16
mbed_official 44:2ce89a25b635 1696 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
mbed_official 44:2ce89a25b635 1697 #define LCD_WF_WF22_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1698 #define LCD_WF_WF22_SHIFT 16
mbed_official 44:2ce89a25b635 1699 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
mbed_official 44:2ce89a25b635 1700 #define LCD_WF_WF34_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1701 #define LCD_WF_WF34_SHIFT 16
mbed_official 44:2ce89a25b635 1702 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
mbed_official 44:2ce89a25b635 1703 #define LCD_WF_WF50_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1704 #define LCD_WF_WF50_SHIFT 16
mbed_official 44:2ce89a25b635 1705 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
mbed_official 44:2ce89a25b635 1706 #define LCD_WF_WF14_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1707 #define LCD_WF_WF14_SHIFT 16
mbed_official 44:2ce89a25b635 1708 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
mbed_official 44:2ce89a25b635 1709 #define LCD_WF_WF54_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1710 #define LCD_WF_WF54_SHIFT 16
mbed_official 44:2ce89a25b635 1711 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
mbed_official 44:2ce89a25b635 1712 #define LCD_WF_WF2_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1713 #define LCD_WF_WF2_SHIFT 16
mbed_official 44:2ce89a25b635 1714 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
mbed_official 44:2ce89a25b635 1715 #define LCD_WF_WF58_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1716 #define LCD_WF_WF58_SHIFT 16
mbed_official 44:2ce89a25b635 1717 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
mbed_official 44:2ce89a25b635 1718 #define LCD_WF_WF30_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1719 #define LCD_WF_WF30_SHIFT 16
mbed_official 44:2ce89a25b635 1720 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
mbed_official 44:2ce89a25b635 1721 #define LCD_WF_WF62_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1722 #define LCD_WF_WF62_SHIFT 16
mbed_official 44:2ce89a25b635 1723 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
mbed_official 44:2ce89a25b635 1724 #define LCD_WF_WF10_MASK 0xFF0000u
mbed_official 44:2ce89a25b635 1725 #define LCD_WF_WF10_SHIFT 16
mbed_official 44:2ce89a25b635 1726 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
mbed_official 44:2ce89a25b635 1727 #define LCD_WF_WF63_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1728 #define LCD_WF_WF63_SHIFT 24
mbed_official 44:2ce89a25b635 1729 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
mbed_official 44:2ce89a25b635 1730 #define LCD_WF_WF59_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1731 #define LCD_WF_WF59_SHIFT 24
mbed_official 44:2ce89a25b635 1732 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
mbed_official 44:2ce89a25b635 1733 #define LCD_WF_WF55_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1734 #define LCD_WF_WF55_SHIFT 24
mbed_official 44:2ce89a25b635 1735 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
mbed_official 44:2ce89a25b635 1736 #define LCD_WF_WF3_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1737 #define LCD_WF_WF3_SHIFT 24
mbed_official 44:2ce89a25b635 1738 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
mbed_official 44:2ce89a25b635 1739 #define LCD_WF_WF51_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1740 #define LCD_WF_WF51_SHIFT 24
mbed_official 44:2ce89a25b635 1741 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
mbed_official 44:2ce89a25b635 1742 #define LCD_WF_WF47_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1743 #define LCD_WF_WF47_SHIFT 24
mbed_official 44:2ce89a25b635 1744 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
mbed_official 44:2ce89a25b635 1745 #define LCD_WF_WF43_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1746 #define LCD_WF_WF43_SHIFT 24
mbed_official 44:2ce89a25b635 1747 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
mbed_official 44:2ce89a25b635 1748 #define LCD_WF_WF7_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1749 #define LCD_WF_WF7_SHIFT 24
mbed_official 44:2ce89a25b635 1750 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
mbed_official 44:2ce89a25b635 1751 #define LCD_WF_WF39_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1752 #define LCD_WF_WF39_SHIFT 24
mbed_official 44:2ce89a25b635 1753 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
mbed_official 44:2ce89a25b635 1754 #define LCD_WF_WF35_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1755 #define LCD_WF_WF35_SHIFT 24
mbed_official 44:2ce89a25b635 1756 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
mbed_official 44:2ce89a25b635 1757 #define LCD_WF_WF31_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1758 #define LCD_WF_WF31_SHIFT 24
mbed_official 44:2ce89a25b635 1759 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
mbed_official 44:2ce89a25b635 1760 #define LCD_WF_WF11_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1761 #define LCD_WF_WF11_SHIFT 24
mbed_official 44:2ce89a25b635 1762 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
mbed_official 44:2ce89a25b635 1763 #define LCD_WF_WF27_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1764 #define LCD_WF_WF27_SHIFT 24
mbed_official 44:2ce89a25b635 1765 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
mbed_official 44:2ce89a25b635 1766 #define LCD_WF_WF23_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1767 #define LCD_WF_WF23_SHIFT 24
mbed_official 44:2ce89a25b635 1768 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
mbed_official 44:2ce89a25b635 1769 #define LCD_WF_WF19_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1770 #define LCD_WF_WF19_SHIFT 24
mbed_official 44:2ce89a25b635 1771 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
mbed_official 44:2ce89a25b635 1772 #define LCD_WF_WF15_MASK 0xFF000000u
mbed_official 44:2ce89a25b635 1773 #define LCD_WF_WF15_SHIFT 24
mbed_official 44:2ce89a25b635 1774 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
mbed_official 44:2ce89a25b635 1775 /* WF8B Bit Fields */
mbed_official 44:2ce89a25b635 1776 #define LCD_WF8B_BPALCD0_MASK 0x1u
mbed_official 44:2ce89a25b635 1777 #define LCD_WF8B_BPALCD0_SHIFT 0
mbed_official 44:2ce89a25b635 1778 #define LCD_WF8B_BPALCD63_MASK 0x1u
mbed_official 44:2ce89a25b635 1779 #define LCD_WF8B_BPALCD63_SHIFT 0
mbed_official 44:2ce89a25b635 1780 #define LCD_WF8B_BPALCD62_MASK 0x1u
mbed_official 44:2ce89a25b635 1781 #define LCD_WF8B_BPALCD62_SHIFT 0
mbed_official 44:2ce89a25b635 1782 #define LCD_WF8B_BPALCD61_MASK 0x1u
mbed_official 44:2ce89a25b635 1783 #define LCD_WF8B_BPALCD61_SHIFT 0
mbed_official 44:2ce89a25b635 1784 #define LCD_WF8B_BPALCD60_MASK 0x1u
mbed_official 44:2ce89a25b635 1785 #define LCD_WF8B_BPALCD60_SHIFT 0
mbed_official 44:2ce89a25b635 1786 #define LCD_WF8B_BPALCD59_MASK 0x1u
mbed_official 44:2ce89a25b635 1787 #define LCD_WF8B_BPALCD59_SHIFT 0
mbed_official 44:2ce89a25b635 1788 #define LCD_WF8B_BPALCD58_MASK 0x1u
mbed_official 44:2ce89a25b635 1789 #define LCD_WF8B_BPALCD58_SHIFT 0
mbed_official 44:2ce89a25b635 1790 #define LCD_WF8B_BPALCD57_MASK 0x1u
mbed_official 44:2ce89a25b635 1791 #define LCD_WF8B_BPALCD57_SHIFT 0
mbed_official 44:2ce89a25b635 1792 #define LCD_WF8B_BPALCD1_MASK 0x1u
mbed_official 44:2ce89a25b635 1793 #define LCD_WF8B_BPALCD1_SHIFT 0
mbed_official 44:2ce89a25b635 1794 #define LCD_WF8B_BPALCD56_MASK 0x1u
mbed_official 44:2ce89a25b635 1795 #define LCD_WF8B_BPALCD56_SHIFT 0
mbed_official 44:2ce89a25b635 1796 #define LCD_WF8B_BPALCD55_MASK 0x1u
mbed_official 44:2ce89a25b635 1797 #define LCD_WF8B_BPALCD55_SHIFT 0
mbed_official 44:2ce89a25b635 1798 #define LCD_WF8B_BPALCD54_MASK 0x1u
mbed_official 44:2ce89a25b635 1799 #define LCD_WF8B_BPALCD54_SHIFT 0
mbed_official 44:2ce89a25b635 1800 #define LCD_WF8B_BPALCD53_MASK 0x1u
mbed_official 44:2ce89a25b635 1801 #define LCD_WF8B_BPALCD53_SHIFT 0
mbed_official 44:2ce89a25b635 1802 #define LCD_WF8B_BPALCD52_MASK 0x1u
mbed_official 44:2ce89a25b635 1803 #define LCD_WF8B_BPALCD52_SHIFT 0
mbed_official 44:2ce89a25b635 1804 #define LCD_WF8B_BPALCD51_MASK 0x1u
mbed_official 44:2ce89a25b635 1805 #define LCD_WF8B_BPALCD51_SHIFT 0
mbed_official 44:2ce89a25b635 1806 #define LCD_WF8B_BPALCD50_MASK 0x1u
mbed_official 44:2ce89a25b635 1807 #define LCD_WF8B_BPALCD50_SHIFT 0
mbed_official 44:2ce89a25b635 1808 #define LCD_WF8B_BPALCD2_MASK 0x1u
mbed_official 44:2ce89a25b635 1809 #define LCD_WF8B_BPALCD2_SHIFT 0
mbed_official 44:2ce89a25b635 1810 #define LCD_WF8B_BPALCD49_MASK 0x1u
mbed_official 44:2ce89a25b635 1811 #define LCD_WF8B_BPALCD49_SHIFT 0
mbed_official 44:2ce89a25b635 1812 #define LCD_WF8B_BPALCD48_MASK 0x1u
mbed_official 44:2ce89a25b635 1813 #define LCD_WF8B_BPALCD48_SHIFT 0
mbed_official 44:2ce89a25b635 1814 #define LCD_WF8B_BPALCD47_MASK 0x1u
mbed_official 44:2ce89a25b635 1815 #define LCD_WF8B_BPALCD47_SHIFT 0
mbed_official 44:2ce89a25b635 1816 #define LCD_WF8B_BPALCD46_MASK 0x1u
mbed_official 44:2ce89a25b635 1817 #define LCD_WF8B_BPALCD46_SHIFT 0
mbed_official 44:2ce89a25b635 1818 #define LCD_WF8B_BPALCD45_MASK 0x1u
mbed_official 44:2ce89a25b635 1819 #define LCD_WF8B_BPALCD45_SHIFT 0
mbed_official 44:2ce89a25b635 1820 #define LCD_WF8B_BPALCD44_MASK 0x1u
mbed_official 44:2ce89a25b635 1821 #define LCD_WF8B_BPALCD44_SHIFT 0
mbed_official 44:2ce89a25b635 1822 #define LCD_WF8B_BPALCD43_MASK 0x1u
mbed_official 44:2ce89a25b635 1823 #define LCD_WF8B_BPALCD43_SHIFT 0
mbed_official 44:2ce89a25b635 1824 #define LCD_WF8B_BPALCD3_MASK 0x1u
mbed_official 44:2ce89a25b635 1825 #define LCD_WF8B_BPALCD3_SHIFT 0
mbed_official 44:2ce89a25b635 1826 #define LCD_WF8B_BPALCD42_MASK 0x1u
mbed_official 44:2ce89a25b635 1827 #define LCD_WF8B_BPALCD42_SHIFT 0
mbed_official 44:2ce89a25b635 1828 #define LCD_WF8B_BPALCD41_MASK 0x1u
mbed_official 44:2ce89a25b635 1829 #define LCD_WF8B_BPALCD41_SHIFT 0
mbed_official 44:2ce89a25b635 1830 #define LCD_WF8B_BPALCD40_MASK 0x1u
mbed_official 44:2ce89a25b635 1831 #define LCD_WF8B_BPALCD40_SHIFT 0
mbed_official 44:2ce89a25b635 1832 #define LCD_WF8B_BPALCD39_MASK 0x1u
mbed_official 44:2ce89a25b635 1833 #define LCD_WF8B_BPALCD39_SHIFT 0
mbed_official 44:2ce89a25b635 1834 #define LCD_WF8B_BPALCD38_MASK 0x1u
mbed_official 44:2ce89a25b635 1835 #define LCD_WF8B_BPALCD38_SHIFT 0
mbed_official 44:2ce89a25b635 1836 #define LCD_WF8B_BPALCD37_MASK 0x1u
mbed_official 44:2ce89a25b635 1837 #define LCD_WF8B_BPALCD37_SHIFT 0
mbed_official 44:2ce89a25b635 1838 #define LCD_WF8B_BPALCD36_MASK 0x1u
mbed_official 44:2ce89a25b635 1839 #define LCD_WF8B_BPALCD36_SHIFT 0
mbed_official 44:2ce89a25b635 1840 #define LCD_WF8B_BPALCD4_MASK 0x1u
mbed_official 44:2ce89a25b635 1841 #define LCD_WF8B_BPALCD4_SHIFT 0
mbed_official 44:2ce89a25b635 1842 #define LCD_WF8B_BPALCD35_MASK 0x1u
mbed_official 44:2ce89a25b635 1843 #define LCD_WF8B_BPALCD35_SHIFT 0
mbed_official 44:2ce89a25b635 1844 #define LCD_WF8B_BPALCD34_MASK 0x1u
mbed_official 44:2ce89a25b635 1845 #define LCD_WF8B_BPALCD34_SHIFT 0
mbed_official 44:2ce89a25b635 1846 #define LCD_WF8B_BPALCD33_MASK 0x1u
mbed_official 44:2ce89a25b635 1847 #define LCD_WF8B_BPALCD33_SHIFT 0
mbed_official 44:2ce89a25b635 1848 #define LCD_WF8B_BPALCD32_MASK 0x1u
mbed_official 44:2ce89a25b635 1849 #define LCD_WF8B_BPALCD32_SHIFT 0
mbed_official 44:2ce89a25b635 1850 #define LCD_WF8B_BPALCD31_MASK 0x1u
mbed_official 44:2ce89a25b635 1851 #define LCD_WF8B_BPALCD31_SHIFT 0
mbed_official 44:2ce89a25b635 1852 #define LCD_WF8B_BPALCD30_MASK 0x1u
mbed_official 44:2ce89a25b635 1853 #define LCD_WF8B_BPALCD30_SHIFT 0
mbed_official 44:2ce89a25b635 1854 #define LCD_WF8B_BPALCD29_MASK 0x1u
mbed_official 44:2ce89a25b635 1855 #define LCD_WF8B_BPALCD29_SHIFT 0
mbed_official 44:2ce89a25b635 1856 #define LCD_WF8B_BPALCD5_MASK 0x1u
mbed_official 44:2ce89a25b635 1857 #define LCD_WF8B_BPALCD5_SHIFT 0
mbed_official 44:2ce89a25b635 1858 #define LCD_WF8B_BPALCD28_MASK 0x1u
mbed_official 44:2ce89a25b635 1859 #define LCD_WF8B_BPALCD28_SHIFT 0
mbed_official 44:2ce89a25b635 1860 #define LCD_WF8B_BPALCD27_MASK 0x1u
mbed_official 44:2ce89a25b635 1861 #define LCD_WF8B_BPALCD27_SHIFT 0
mbed_official 44:2ce89a25b635 1862 #define LCD_WF8B_BPALCD26_MASK 0x1u
mbed_official 44:2ce89a25b635 1863 #define LCD_WF8B_BPALCD26_SHIFT 0
mbed_official 44:2ce89a25b635 1864 #define LCD_WF8B_BPALCD25_MASK 0x1u
mbed_official 44:2ce89a25b635 1865 #define LCD_WF8B_BPALCD25_SHIFT 0
mbed_official 44:2ce89a25b635 1866 #define LCD_WF8B_BPALCD24_MASK 0x1u
mbed_official 44:2ce89a25b635 1867 #define LCD_WF8B_BPALCD24_SHIFT 0
mbed_official 44:2ce89a25b635 1868 #define LCD_WF8B_BPALCD23_MASK 0x1u
mbed_official 44:2ce89a25b635 1869 #define LCD_WF8B_BPALCD23_SHIFT 0
mbed_official 44:2ce89a25b635 1870 #define LCD_WF8B_BPALCD22_MASK 0x1u
mbed_official 44:2ce89a25b635 1871 #define LCD_WF8B_BPALCD22_SHIFT 0
mbed_official 44:2ce89a25b635 1872 #define LCD_WF8B_BPALCD6_MASK 0x1u
mbed_official 44:2ce89a25b635 1873 #define LCD_WF8B_BPALCD6_SHIFT 0
mbed_official 44:2ce89a25b635 1874 #define LCD_WF8B_BPALCD21_MASK 0x1u
mbed_official 44:2ce89a25b635 1875 #define LCD_WF8B_BPALCD21_SHIFT 0
mbed_official 44:2ce89a25b635 1876 #define LCD_WF8B_BPALCD20_MASK 0x1u
mbed_official 44:2ce89a25b635 1877 #define LCD_WF8B_BPALCD20_SHIFT 0
mbed_official 44:2ce89a25b635 1878 #define LCD_WF8B_BPALCD19_MASK 0x1u
mbed_official 44:2ce89a25b635 1879 #define LCD_WF8B_BPALCD19_SHIFT 0
mbed_official 44:2ce89a25b635 1880 #define LCD_WF8B_BPALCD18_MASK 0x1u
mbed_official 44:2ce89a25b635 1881 #define LCD_WF8B_BPALCD18_SHIFT 0
mbed_official 44:2ce89a25b635 1882 #define LCD_WF8B_BPALCD17_MASK 0x1u
mbed_official 44:2ce89a25b635 1883 #define LCD_WF8B_BPALCD17_SHIFT 0
mbed_official 44:2ce89a25b635 1884 #define LCD_WF8B_BPALCD16_MASK 0x1u
mbed_official 44:2ce89a25b635 1885 #define LCD_WF8B_BPALCD16_SHIFT 0
mbed_official 44:2ce89a25b635 1886 #define LCD_WF8B_BPALCD15_MASK 0x1u
mbed_official 44:2ce89a25b635 1887 #define LCD_WF8B_BPALCD15_SHIFT 0
mbed_official 44:2ce89a25b635 1888 #define LCD_WF8B_BPALCD7_MASK 0x1u
mbed_official 44:2ce89a25b635 1889 #define LCD_WF8B_BPALCD7_SHIFT 0
mbed_official 44:2ce89a25b635 1890 #define LCD_WF8B_BPALCD14_MASK 0x1u
mbed_official 44:2ce89a25b635 1891 #define LCD_WF8B_BPALCD14_SHIFT 0
mbed_official 44:2ce89a25b635 1892 #define LCD_WF8B_BPALCD13_MASK 0x1u
mbed_official 44:2ce89a25b635 1893 #define LCD_WF8B_BPALCD13_SHIFT 0
mbed_official 44:2ce89a25b635 1894 #define LCD_WF8B_BPALCD12_MASK 0x1u
mbed_official 44:2ce89a25b635 1895 #define LCD_WF8B_BPALCD12_SHIFT 0
mbed_official 44:2ce89a25b635 1896 #define LCD_WF8B_BPALCD11_MASK 0x1u
mbed_official 44:2ce89a25b635 1897 #define LCD_WF8B_BPALCD11_SHIFT 0
mbed_official 44:2ce89a25b635 1898 #define LCD_WF8B_BPALCD10_MASK 0x1u
mbed_official 44:2ce89a25b635 1899 #define LCD_WF8B_BPALCD10_SHIFT 0
mbed_official 44:2ce89a25b635 1900 #define LCD_WF8B_BPALCD9_MASK 0x1u
mbed_official 44:2ce89a25b635 1901 #define LCD_WF8B_BPALCD9_SHIFT 0
mbed_official 44:2ce89a25b635 1902 #define LCD_WF8B_BPALCD8_MASK 0x1u
mbed_official 44:2ce89a25b635 1903 #define LCD_WF8B_BPALCD8_SHIFT 0
mbed_official 44:2ce89a25b635 1904 #define LCD_WF8B_BPBLCD1_MASK 0x2u
mbed_official 44:2ce89a25b635 1905 #define LCD_WF8B_BPBLCD1_SHIFT 1
mbed_official 44:2ce89a25b635 1906 #define LCD_WF8B_BPBLCD32_MASK 0x2u
mbed_official 44:2ce89a25b635 1907 #define LCD_WF8B_BPBLCD32_SHIFT 1
mbed_official 44:2ce89a25b635 1908 #define LCD_WF8B_BPBLCD30_MASK 0x2u
mbed_official 44:2ce89a25b635 1909 #define LCD_WF8B_BPBLCD30_SHIFT 1
mbed_official 44:2ce89a25b635 1910 #define LCD_WF8B_BPBLCD60_MASK 0x2u
mbed_official 44:2ce89a25b635 1911 #define LCD_WF8B_BPBLCD60_SHIFT 1
mbed_official 44:2ce89a25b635 1912 #define LCD_WF8B_BPBLCD24_MASK 0x2u
mbed_official 44:2ce89a25b635 1913 #define LCD_WF8B_BPBLCD24_SHIFT 1
mbed_official 44:2ce89a25b635 1914 #define LCD_WF8B_BPBLCD28_MASK 0x2u
mbed_official 44:2ce89a25b635 1915 #define LCD_WF8B_BPBLCD28_SHIFT 1
mbed_official 44:2ce89a25b635 1916 #define LCD_WF8B_BPBLCD23_MASK 0x2u
mbed_official 44:2ce89a25b635 1917 #define LCD_WF8B_BPBLCD23_SHIFT 1
mbed_official 44:2ce89a25b635 1918 #define LCD_WF8B_BPBLCD48_MASK 0x2u
mbed_official 44:2ce89a25b635 1919 #define LCD_WF8B_BPBLCD48_SHIFT 1
mbed_official 44:2ce89a25b635 1920 #define LCD_WF8B_BPBLCD10_MASK 0x2u
mbed_official 44:2ce89a25b635 1921 #define LCD_WF8B_BPBLCD10_SHIFT 1
mbed_official 44:2ce89a25b635 1922 #define LCD_WF8B_BPBLCD15_MASK 0x2u
mbed_official 44:2ce89a25b635 1923 #define LCD_WF8B_BPBLCD15_SHIFT 1
mbed_official 44:2ce89a25b635 1924 #define LCD_WF8B_BPBLCD36_MASK 0x2u
mbed_official 44:2ce89a25b635 1925 #define LCD_WF8B_BPBLCD36_SHIFT 1
mbed_official 44:2ce89a25b635 1926 #define LCD_WF8B_BPBLCD44_MASK 0x2u
mbed_official 44:2ce89a25b635 1927 #define LCD_WF8B_BPBLCD44_SHIFT 1
mbed_official 44:2ce89a25b635 1928 #define LCD_WF8B_BPBLCD62_MASK 0x2u
mbed_official 44:2ce89a25b635 1929 #define LCD_WF8B_BPBLCD62_SHIFT 1
mbed_official 44:2ce89a25b635 1930 #define LCD_WF8B_BPBLCD53_MASK 0x2u
mbed_official 44:2ce89a25b635 1931 #define LCD_WF8B_BPBLCD53_SHIFT 1
mbed_official 44:2ce89a25b635 1932 #define LCD_WF8B_BPBLCD22_MASK 0x2u
mbed_official 44:2ce89a25b635 1933 #define LCD_WF8B_BPBLCD22_SHIFT 1
mbed_official 44:2ce89a25b635 1934 #define LCD_WF8B_BPBLCD47_MASK 0x2u
mbed_official 44:2ce89a25b635 1935 #define LCD_WF8B_BPBLCD47_SHIFT 1
mbed_official 44:2ce89a25b635 1936 #define LCD_WF8B_BPBLCD33_MASK 0x2u
mbed_official 44:2ce89a25b635 1937 #define LCD_WF8B_BPBLCD33_SHIFT 1
mbed_official 44:2ce89a25b635 1938 #define LCD_WF8B_BPBLCD2_MASK 0x2u
mbed_official 44:2ce89a25b635 1939 #define LCD_WF8B_BPBLCD2_SHIFT 1
mbed_official 44:2ce89a25b635 1940 #define LCD_WF8B_BPBLCD49_MASK 0x2u
mbed_official 44:2ce89a25b635 1941 #define LCD_WF8B_BPBLCD49_SHIFT 1
mbed_official 44:2ce89a25b635 1942 #define LCD_WF8B_BPBLCD0_MASK 0x2u
mbed_official 44:2ce89a25b635 1943 #define LCD_WF8B_BPBLCD0_SHIFT 1
mbed_official 44:2ce89a25b635 1944 #define LCD_WF8B_BPBLCD55_MASK 0x2u
mbed_official 44:2ce89a25b635 1945 #define LCD_WF8B_BPBLCD55_SHIFT 1
mbed_official 44:2ce89a25b635 1946 #define LCD_WF8B_BPBLCD56_MASK 0x2u
mbed_official 44:2ce89a25b635 1947 #define LCD_WF8B_BPBLCD56_SHIFT 1
mbed_official 44:2ce89a25b635 1948 #define LCD_WF8B_BPBLCD21_MASK 0x2u
mbed_official 44:2ce89a25b635 1949 #define LCD_WF8B_BPBLCD21_SHIFT 1
mbed_official 44:2ce89a25b635 1950 #define LCD_WF8B_BPBLCD6_MASK 0x2u
mbed_official 44:2ce89a25b635 1951 #define LCD_WF8B_BPBLCD6_SHIFT 1
mbed_official 44:2ce89a25b635 1952 #define LCD_WF8B_BPBLCD29_MASK 0x2u
mbed_official 44:2ce89a25b635 1953 #define LCD_WF8B_BPBLCD29_SHIFT 1
mbed_official 44:2ce89a25b635 1954 #define LCD_WF8B_BPBLCD25_MASK 0x2u
mbed_official 44:2ce89a25b635 1955 #define LCD_WF8B_BPBLCD25_SHIFT 1
mbed_official 44:2ce89a25b635 1956 #define LCD_WF8B_BPBLCD8_MASK 0x2u
mbed_official 44:2ce89a25b635 1957 #define LCD_WF8B_BPBLCD8_SHIFT 1
mbed_official 44:2ce89a25b635 1958 #define LCD_WF8B_BPBLCD54_MASK 0x2u
mbed_official 44:2ce89a25b635 1959 #define LCD_WF8B_BPBLCD54_SHIFT 1
mbed_official 44:2ce89a25b635 1960 #define LCD_WF8B_BPBLCD38_MASK 0x2u
mbed_official 44:2ce89a25b635 1961 #define LCD_WF8B_BPBLCD38_SHIFT 1
mbed_official 44:2ce89a25b635 1962 #define LCD_WF8B_BPBLCD43_MASK 0x2u
mbed_official 44:2ce89a25b635 1963 #define LCD_WF8B_BPBLCD43_SHIFT 1
mbed_official 44:2ce89a25b635 1964 #define LCD_WF8B_BPBLCD20_MASK 0x2u
mbed_official 44:2ce89a25b635 1965 #define LCD_WF8B_BPBLCD20_SHIFT 1
mbed_official 44:2ce89a25b635 1966 #define LCD_WF8B_BPBLCD9_MASK 0x2u
mbed_official 44:2ce89a25b635 1967 #define LCD_WF8B_BPBLCD9_SHIFT 1
mbed_official 44:2ce89a25b635 1968 #define LCD_WF8B_BPBLCD7_MASK 0x2u
mbed_official 44:2ce89a25b635 1969 #define LCD_WF8B_BPBLCD7_SHIFT 1
mbed_official 44:2ce89a25b635 1970 #define LCD_WF8B_BPBLCD50_MASK 0x2u
mbed_official 44:2ce89a25b635 1971 #define LCD_WF8B_BPBLCD50_SHIFT 1
mbed_official 44:2ce89a25b635 1972 #define LCD_WF8B_BPBLCD40_MASK 0x2u
mbed_official 44:2ce89a25b635 1973 #define LCD_WF8B_BPBLCD40_SHIFT 1
mbed_official 44:2ce89a25b635 1974 #define LCD_WF8B_BPBLCD63_MASK 0x2u
mbed_official 44:2ce89a25b635 1975 #define LCD_WF8B_BPBLCD63_SHIFT 1
mbed_official 44:2ce89a25b635 1976 #define LCD_WF8B_BPBLCD26_MASK 0x2u
mbed_official 44:2ce89a25b635 1977 #define LCD_WF8B_BPBLCD26_SHIFT 1
mbed_official 44:2ce89a25b635 1978 #define LCD_WF8B_BPBLCD12_MASK 0x2u
mbed_official 44:2ce89a25b635 1979 #define LCD_WF8B_BPBLCD12_SHIFT 1
mbed_official 44:2ce89a25b635 1980 #define LCD_WF8B_BPBLCD19_MASK 0x2u
mbed_official 44:2ce89a25b635 1981 #define LCD_WF8B_BPBLCD19_SHIFT 1
mbed_official 44:2ce89a25b635 1982 #define LCD_WF8B_BPBLCD34_MASK 0x2u
mbed_official 44:2ce89a25b635 1983 #define LCD_WF8B_BPBLCD34_SHIFT 1
mbed_official 44:2ce89a25b635 1984 #define LCD_WF8B_BPBLCD39_MASK 0x2u
mbed_official 44:2ce89a25b635 1985 #define LCD_WF8B_BPBLCD39_SHIFT 1
mbed_official 44:2ce89a25b635 1986 #define LCD_WF8B_BPBLCD59_MASK 0x2u
mbed_official 44:2ce89a25b635 1987 #define LCD_WF8B_BPBLCD59_SHIFT 1
mbed_official 44:2ce89a25b635 1988 #define LCD_WF8B_BPBLCD61_MASK 0x2u
mbed_official 44:2ce89a25b635 1989 #define LCD_WF8B_BPBLCD61_SHIFT 1
mbed_official 44:2ce89a25b635 1990 #define LCD_WF8B_BPBLCD37_MASK 0x2u
mbed_official 44:2ce89a25b635 1991 #define LCD_WF8B_BPBLCD37_SHIFT 1
mbed_official 44:2ce89a25b635 1992 #define LCD_WF8B_BPBLCD31_MASK 0x2u
mbed_official 44:2ce89a25b635 1993 #define LCD_WF8B_BPBLCD31_SHIFT 1
mbed_official 44:2ce89a25b635 1994 #define LCD_WF8B_BPBLCD58_MASK 0x2u
mbed_official 44:2ce89a25b635 1995 #define LCD_WF8B_BPBLCD58_SHIFT 1
mbed_official 44:2ce89a25b635 1996 #define LCD_WF8B_BPBLCD18_MASK 0x2u
mbed_official 44:2ce89a25b635 1997 #define LCD_WF8B_BPBLCD18_SHIFT 1
mbed_official 44:2ce89a25b635 1998 #define LCD_WF8B_BPBLCD45_MASK 0x2u
mbed_official 44:2ce89a25b635 1999 #define LCD_WF8B_BPBLCD45_SHIFT 1
mbed_official 44:2ce89a25b635 2000 #define LCD_WF8B_BPBLCD27_MASK 0x2u
mbed_official 44:2ce89a25b635 2001 #define LCD_WF8B_BPBLCD27_SHIFT 1
mbed_official 44:2ce89a25b635 2002 #define LCD_WF8B_BPBLCD14_MASK 0x2u
mbed_official 44:2ce89a25b635 2003 #define LCD_WF8B_BPBLCD14_SHIFT 1
mbed_official 44:2ce89a25b635 2004 #define LCD_WF8B_BPBLCD51_MASK 0x2u
mbed_official 44:2ce89a25b635 2005 #define LCD_WF8B_BPBLCD51_SHIFT 1
mbed_official 44:2ce89a25b635 2006 #define LCD_WF8B_BPBLCD52_MASK 0x2u
mbed_official 44:2ce89a25b635 2007 #define LCD_WF8B_BPBLCD52_SHIFT 1
mbed_official 44:2ce89a25b635 2008 #define LCD_WF8B_BPBLCD4_MASK 0x2u
mbed_official 44:2ce89a25b635 2009 #define LCD_WF8B_BPBLCD4_SHIFT 1
mbed_official 44:2ce89a25b635 2010 #define LCD_WF8B_BPBLCD35_MASK 0x2u
mbed_official 44:2ce89a25b635 2011 #define LCD_WF8B_BPBLCD35_SHIFT 1
mbed_official 44:2ce89a25b635 2012 #define LCD_WF8B_BPBLCD17_MASK 0x2u
mbed_official 44:2ce89a25b635 2013 #define LCD_WF8B_BPBLCD17_SHIFT 1
mbed_official 44:2ce89a25b635 2014 #define LCD_WF8B_BPBLCD41_MASK 0x2u
mbed_official 44:2ce89a25b635 2015 #define LCD_WF8B_BPBLCD41_SHIFT 1
mbed_official 44:2ce89a25b635 2016 #define LCD_WF8B_BPBLCD11_MASK 0x2u
mbed_official 44:2ce89a25b635 2017 #define LCD_WF8B_BPBLCD11_SHIFT 1
mbed_official 44:2ce89a25b635 2018 #define LCD_WF8B_BPBLCD46_MASK 0x2u
mbed_official 44:2ce89a25b635 2019 #define LCD_WF8B_BPBLCD46_SHIFT 1
mbed_official 44:2ce89a25b635 2020 #define LCD_WF8B_BPBLCD57_MASK 0x2u
mbed_official 44:2ce89a25b635 2021 #define LCD_WF8B_BPBLCD57_SHIFT 1
mbed_official 44:2ce89a25b635 2022 #define LCD_WF8B_BPBLCD42_MASK 0x2u
mbed_official 44:2ce89a25b635 2023 #define LCD_WF8B_BPBLCD42_SHIFT 1
mbed_official 44:2ce89a25b635 2024 #define LCD_WF8B_BPBLCD5_MASK 0x2u
mbed_official 44:2ce89a25b635 2025 #define LCD_WF8B_BPBLCD5_SHIFT 1
mbed_official 44:2ce89a25b635 2026 #define LCD_WF8B_BPBLCD3_MASK 0x2u
mbed_official 44:2ce89a25b635 2027 #define LCD_WF8B_BPBLCD3_SHIFT 1
mbed_official 44:2ce89a25b635 2028 #define LCD_WF8B_BPBLCD16_MASK 0x2u
mbed_official 44:2ce89a25b635 2029 #define LCD_WF8B_BPBLCD16_SHIFT 1
mbed_official 44:2ce89a25b635 2030 #define LCD_WF8B_BPBLCD13_MASK 0x2u
mbed_official 44:2ce89a25b635 2031 #define LCD_WF8B_BPBLCD13_SHIFT 1
mbed_official 44:2ce89a25b635 2032 #define LCD_WF8B_BPCLCD10_MASK 0x4u
mbed_official 44:2ce89a25b635 2033 #define LCD_WF8B_BPCLCD10_SHIFT 2
mbed_official 44:2ce89a25b635 2034 #define LCD_WF8B_BPCLCD55_MASK 0x4u
mbed_official 44:2ce89a25b635 2035 #define LCD_WF8B_BPCLCD55_SHIFT 2
mbed_official 44:2ce89a25b635 2036 #define LCD_WF8B_BPCLCD2_MASK 0x4u
mbed_official 44:2ce89a25b635 2037 #define LCD_WF8B_BPCLCD2_SHIFT 2
mbed_official 44:2ce89a25b635 2038 #define LCD_WF8B_BPCLCD23_MASK 0x4u
mbed_official 44:2ce89a25b635 2039 #define LCD_WF8B_BPCLCD23_SHIFT 2
mbed_official 44:2ce89a25b635 2040 #define LCD_WF8B_BPCLCD48_MASK 0x4u
mbed_official 44:2ce89a25b635 2041 #define LCD_WF8B_BPCLCD48_SHIFT 2
mbed_official 44:2ce89a25b635 2042 #define LCD_WF8B_BPCLCD24_MASK 0x4u
mbed_official 44:2ce89a25b635 2043 #define LCD_WF8B_BPCLCD24_SHIFT 2
mbed_official 44:2ce89a25b635 2044 #define LCD_WF8B_BPCLCD60_MASK 0x4u
mbed_official 44:2ce89a25b635 2045 #define LCD_WF8B_BPCLCD60_SHIFT 2
mbed_official 44:2ce89a25b635 2046 #define LCD_WF8B_BPCLCD47_MASK 0x4u
mbed_official 44:2ce89a25b635 2047 #define LCD_WF8B_BPCLCD47_SHIFT 2
mbed_official 44:2ce89a25b635 2048 #define LCD_WF8B_BPCLCD22_MASK 0x4u
mbed_official 44:2ce89a25b635 2049 #define LCD_WF8B_BPCLCD22_SHIFT 2
mbed_official 44:2ce89a25b635 2050 #define LCD_WF8B_BPCLCD8_MASK 0x4u
mbed_official 44:2ce89a25b635 2051 #define LCD_WF8B_BPCLCD8_SHIFT 2
mbed_official 44:2ce89a25b635 2052 #define LCD_WF8B_BPCLCD21_MASK 0x4u
mbed_official 44:2ce89a25b635 2053 #define LCD_WF8B_BPCLCD21_SHIFT 2
mbed_official 44:2ce89a25b635 2054 #define LCD_WF8B_BPCLCD49_MASK 0x4u
mbed_official 44:2ce89a25b635 2055 #define LCD_WF8B_BPCLCD49_SHIFT 2
mbed_official 44:2ce89a25b635 2056 #define LCD_WF8B_BPCLCD25_MASK 0x4u
mbed_official 44:2ce89a25b635 2057 #define LCD_WF8B_BPCLCD25_SHIFT 2
mbed_official 44:2ce89a25b635 2058 #define LCD_WF8B_BPCLCD1_MASK 0x4u
mbed_official 44:2ce89a25b635 2059 #define LCD_WF8B_BPCLCD1_SHIFT 2
mbed_official 44:2ce89a25b635 2060 #define LCD_WF8B_BPCLCD20_MASK 0x4u
mbed_official 44:2ce89a25b635 2061 #define LCD_WF8B_BPCLCD20_SHIFT 2
mbed_official 44:2ce89a25b635 2062 #define LCD_WF8B_BPCLCD50_MASK 0x4u
mbed_official 44:2ce89a25b635 2063 #define LCD_WF8B_BPCLCD50_SHIFT 2
mbed_official 44:2ce89a25b635 2064 #define LCD_WF8B_BPCLCD19_MASK 0x4u
mbed_official 44:2ce89a25b635 2065 #define LCD_WF8B_BPCLCD19_SHIFT 2
mbed_official 44:2ce89a25b635 2066 #define LCD_WF8B_BPCLCD26_MASK 0x4u
mbed_official 44:2ce89a25b635 2067 #define LCD_WF8B_BPCLCD26_SHIFT 2
mbed_official 44:2ce89a25b635 2068 #define LCD_WF8B_BPCLCD59_MASK 0x4u
mbed_official 44:2ce89a25b635 2069 #define LCD_WF8B_BPCLCD59_SHIFT 2
mbed_official 44:2ce89a25b635 2070 #define LCD_WF8B_BPCLCD61_MASK 0x4u
mbed_official 44:2ce89a25b635 2071 #define LCD_WF8B_BPCLCD61_SHIFT 2
mbed_official 44:2ce89a25b635 2072 #define LCD_WF8B_BPCLCD46_MASK 0x4u
mbed_official 44:2ce89a25b635 2073 #define LCD_WF8B_BPCLCD46_SHIFT 2
mbed_official 44:2ce89a25b635 2074 #define LCD_WF8B_BPCLCD18_MASK 0x4u
mbed_official 44:2ce89a25b635 2075 #define LCD_WF8B_BPCLCD18_SHIFT 2
mbed_official 44:2ce89a25b635 2076 #define LCD_WF8B_BPCLCD5_MASK 0x4u
mbed_official 44:2ce89a25b635 2077 #define LCD_WF8B_BPCLCD5_SHIFT 2
mbed_official 44:2ce89a25b635 2078 #define LCD_WF8B_BPCLCD63_MASK 0x4u
mbed_official 44:2ce89a25b635 2079 #define LCD_WF8B_BPCLCD63_SHIFT 2
mbed_official 44:2ce89a25b635 2080 #define LCD_WF8B_BPCLCD27_MASK 0x4u
mbed_official 44:2ce89a25b635 2081 #define LCD_WF8B_BPCLCD27_SHIFT 2
mbed_official 44:2ce89a25b635 2082 #define LCD_WF8B_BPCLCD17_MASK 0x4u
mbed_official 44:2ce89a25b635 2083 #define LCD_WF8B_BPCLCD17_SHIFT 2
mbed_official 44:2ce89a25b635 2084 #define LCD_WF8B_BPCLCD51_MASK 0x4u
mbed_official 44:2ce89a25b635 2085 #define LCD_WF8B_BPCLCD51_SHIFT 2
mbed_official 44:2ce89a25b635 2086 #define LCD_WF8B_BPCLCD9_MASK 0x4u
mbed_official 44:2ce89a25b635 2087 #define LCD_WF8B_BPCLCD9_SHIFT 2
mbed_official 44:2ce89a25b635 2088 #define LCD_WF8B_BPCLCD54_MASK 0x4u
mbed_official 44:2ce89a25b635 2089 #define LCD_WF8B_BPCLCD54_SHIFT 2
mbed_official 44:2ce89a25b635 2090 #define LCD_WF8B_BPCLCD15_MASK 0x4u
mbed_official 44:2ce89a25b635 2091 #define LCD_WF8B_BPCLCD15_SHIFT 2
mbed_official 44:2ce89a25b635 2092 #define LCD_WF8B_BPCLCD16_MASK 0x4u
mbed_official 44:2ce89a25b635 2093 #define LCD_WF8B_BPCLCD16_SHIFT 2
mbed_official 44:2ce89a25b635 2094 #define LCD_WF8B_BPCLCD14_MASK 0x4u
mbed_official 44:2ce89a25b635 2095 #define LCD_WF8B_BPCLCD14_SHIFT 2
mbed_official 44:2ce89a25b635 2096 #define LCD_WF8B_BPCLCD32_MASK 0x4u
mbed_official 44:2ce89a25b635 2097 #define LCD_WF8B_BPCLCD32_SHIFT 2
mbed_official 44:2ce89a25b635 2098 #define LCD_WF8B_BPCLCD28_MASK 0x4u
mbed_official 44:2ce89a25b635 2099 #define LCD_WF8B_BPCLCD28_SHIFT 2
mbed_official 44:2ce89a25b635 2100 #define LCD_WF8B_BPCLCD53_MASK 0x4u
mbed_official 44:2ce89a25b635 2101 #define LCD_WF8B_BPCLCD53_SHIFT 2
mbed_official 44:2ce89a25b635 2102 #define LCD_WF8B_BPCLCD33_MASK 0x4u
mbed_official 44:2ce89a25b635 2103 #define LCD_WF8B_BPCLCD33_SHIFT 2
mbed_official 44:2ce89a25b635 2104 #define LCD_WF8B_BPCLCD0_MASK 0x4u
mbed_official 44:2ce89a25b635 2105 #define LCD_WF8B_BPCLCD0_SHIFT 2
mbed_official 44:2ce89a25b635 2106 #define LCD_WF8B_BPCLCD43_MASK 0x4u
mbed_official 44:2ce89a25b635 2107 #define LCD_WF8B_BPCLCD43_SHIFT 2
mbed_official 44:2ce89a25b635 2108 #define LCD_WF8B_BPCLCD7_MASK 0x4u
mbed_official 44:2ce89a25b635 2109 #define LCD_WF8B_BPCLCD7_SHIFT 2
mbed_official 44:2ce89a25b635 2110 #define LCD_WF8B_BPCLCD4_MASK 0x4u
mbed_official 44:2ce89a25b635 2111 #define LCD_WF8B_BPCLCD4_SHIFT 2
mbed_official 44:2ce89a25b635 2112 #define LCD_WF8B_BPCLCD34_MASK 0x4u
mbed_official 44:2ce89a25b635 2113 #define LCD_WF8B_BPCLCD34_SHIFT 2
mbed_official 44:2ce89a25b635 2114 #define LCD_WF8B_BPCLCD29_MASK 0x4u
mbed_official 44:2ce89a25b635 2115 #define LCD_WF8B_BPCLCD29_SHIFT 2
mbed_official 44:2ce89a25b635 2116 #define LCD_WF8B_BPCLCD45_MASK 0x4u
mbed_official 44:2ce89a25b635 2117 #define LCD_WF8B_BPCLCD45_SHIFT 2
mbed_official 44:2ce89a25b635 2118 #define LCD_WF8B_BPCLCD57_MASK 0x4u
mbed_official 44:2ce89a25b635 2119 #define LCD_WF8B_BPCLCD57_SHIFT 2
mbed_official 44:2ce89a25b635 2120 #define LCD_WF8B_BPCLCD42_MASK 0x4u
mbed_official 44:2ce89a25b635 2121 #define LCD_WF8B_BPCLCD42_SHIFT 2
mbed_official 44:2ce89a25b635 2122 #define LCD_WF8B_BPCLCD35_MASK 0x4u
mbed_official 44:2ce89a25b635 2123 #define LCD_WF8B_BPCLCD35_SHIFT 2
mbed_official 44:2ce89a25b635 2124 #define LCD_WF8B_BPCLCD13_MASK 0x4u
mbed_official 44:2ce89a25b635 2125 #define LCD_WF8B_BPCLCD13_SHIFT 2
mbed_official 44:2ce89a25b635 2126 #define LCD_WF8B_BPCLCD36_MASK 0x4u
mbed_official 44:2ce89a25b635 2127 #define LCD_WF8B_BPCLCD36_SHIFT 2
mbed_official 44:2ce89a25b635 2128 #define LCD_WF8B_BPCLCD30_MASK 0x4u
mbed_official 44:2ce89a25b635 2129 #define LCD_WF8B_BPCLCD30_SHIFT 2
mbed_official 44:2ce89a25b635 2130 #define LCD_WF8B_BPCLCD52_MASK 0x4u
mbed_official 44:2ce89a25b635 2131 #define LCD_WF8B_BPCLCD52_SHIFT 2
mbed_official 44:2ce89a25b635 2132 #define LCD_WF8B_BPCLCD58_MASK 0x4u
mbed_official 44:2ce89a25b635 2133 #define LCD_WF8B_BPCLCD58_SHIFT 2
mbed_official 44:2ce89a25b635 2134 #define LCD_WF8B_BPCLCD41_MASK 0x4u
mbed_official 44:2ce89a25b635 2135 #define LCD_WF8B_BPCLCD41_SHIFT 2
mbed_official 44:2ce89a25b635 2136 #define LCD_WF8B_BPCLCD37_MASK 0x4u
mbed_official 44:2ce89a25b635 2137 #define LCD_WF8B_BPCLCD37_SHIFT 2
mbed_official 44:2ce89a25b635 2138 #define LCD_WF8B_BPCLCD3_MASK 0x4u
mbed_official 44:2ce89a25b635 2139 #define LCD_WF8B_BPCLCD3_SHIFT 2
mbed_official 44:2ce89a25b635 2140 #define LCD_WF8B_BPCLCD12_MASK 0x4u
mbed_official 44:2ce89a25b635 2141 #define LCD_WF8B_BPCLCD12_SHIFT 2
mbed_official 44:2ce89a25b635 2142 #define LCD_WF8B_BPCLCD11_MASK 0x4u
mbed_official 44:2ce89a25b635 2143 #define LCD_WF8B_BPCLCD11_SHIFT 2
mbed_official 44:2ce89a25b635 2144 #define LCD_WF8B_BPCLCD38_MASK 0x4u
mbed_official 44:2ce89a25b635 2145 #define LCD_WF8B_BPCLCD38_SHIFT 2
mbed_official 44:2ce89a25b635 2146 #define LCD_WF8B_BPCLCD44_MASK 0x4u
mbed_official 44:2ce89a25b635 2147 #define LCD_WF8B_BPCLCD44_SHIFT 2
mbed_official 44:2ce89a25b635 2148 #define LCD_WF8B_BPCLCD31_MASK 0x4u
mbed_official 44:2ce89a25b635 2149 #define LCD_WF8B_BPCLCD31_SHIFT 2
mbed_official 44:2ce89a25b635 2150 #define LCD_WF8B_BPCLCD40_MASK 0x4u
mbed_official 44:2ce89a25b635 2151 #define LCD_WF8B_BPCLCD40_SHIFT 2
mbed_official 44:2ce89a25b635 2152 #define LCD_WF8B_BPCLCD62_MASK 0x4u
mbed_official 44:2ce89a25b635 2153 #define LCD_WF8B_BPCLCD62_SHIFT 2
mbed_official 44:2ce89a25b635 2154 #define LCD_WF8B_BPCLCD56_MASK 0x4u
mbed_official 44:2ce89a25b635 2155 #define LCD_WF8B_BPCLCD56_SHIFT 2
mbed_official 44:2ce89a25b635 2156 #define LCD_WF8B_BPCLCD39_MASK 0x4u
mbed_official 44:2ce89a25b635 2157 #define LCD_WF8B_BPCLCD39_SHIFT 2
mbed_official 44:2ce89a25b635 2158 #define LCD_WF8B_BPCLCD6_MASK 0x4u
mbed_official 44:2ce89a25b635 2159 #define LCD_WF8B_BPCLCD6_SHIFT 2
mbed_official 44:2ce89a25b635 2160 #define LCD_WF8B_BPDLCD47_MASK 0x8u
mbed_official 44:2ce89a25b635 2161 #define LCD_WF8B_BPDLCD47_SHIFT 3
mbed_official 44:2ce89a25b635 2162 #define LCD_WF8B_BPDLCD23_MASK 0x8u
mbed_official 44:2ce89a25b635 2163 #define LCD_WF8B_BPDLCD23_SHIFT 3
mbed_official 44:2ce89a25b635 2164 #define LCD_WF8B_BPDLCD48_MASK 0x8u
mbed_official 44:2ce89a25b635 2165 #define LCD_WF8B_BPDLCD48_SHIFT 3
mbed_official 44:2ce89a25b635 2166 #define LCD_WF8B_BPDLCD24_MASK 0x8u
mbed_official 44:2ce89a25b635 2167 #define LCD_WF8B_BPDLCD24_SHIFT 3
mbed_official 44:2ce89a25b635 2168 #define LCD_WF8B_BPDLCD15_MASK 0x8u
mbed_official 44:2ce89a25b635 2169 #define LCD_WF8B_BPDLCD15_SHIFT 3
mbed_official 44:2ce89a25b635 2170 #define LCD_WF8B_BPDLCD22_MASK 0x8u
mbed_official 44:2ce89a25b635 2171 #define LCD_WF8B_BPDLCD22_SHIFT 3
mbed_official 44:2ce89a25b635 2172 #define LCD_WF8B_BPDLCD60_MASK 0x8u
mbed_official 44:2ce89a25b635 2173 #define LCD_WF8B_BPDLCD60_SHIFT 3
mbed_official 44:2ce89a25b635 2174 #define LCD_WF8B_BPDLCD10_MASK 0x8u
mbed_official 44:2ce89a25b635 2175 #define LCD_WF8B_BPDLCD10_SHIFT 3
mbed_official 44:2ce89a25b635 2176 #define LCD_WF8B_BPDLCD21_MASK 0x8u
mbed_official 44:2ce89a25b635 2177 #define LCD_WF8B_BPDLCD21_SHIFT 3
mbed_official 44:2ce89a25b635 2178 #define LCD_WF8B_BPDLCD49_MASK 0x8u
mbed_official 44:2ce89a25b635 2179 #define LCD_WF8B_BPDLCD49_SHIFT 3
mbed_official 44:2ce89a25b635 2180 #define LCD_WF8B_BPDLCD1_MASK 0x8u
mbed_official 44:2ce89a25b635 2181 #define LCD_WF8B_BPDLCD1_SHIFT 3
mbed_official 44:2ce89a25b635 2182 #define LCD_WF8B_BPDLCD25_MASK 0x8u
mbed_official 44:2ce89a25b635 2183 #define LCD_WF8B_BPDLCD25_SHIFT 3
mbed_official 44:2ce89a25b635 2184 #define LCD_WF8B_BPDLCD20_MASK 0x8u
mbed_official 44:2ce89a25b635 2185 #define LCD_WF8B_BPDLCD20_SHIFT 3
mbed_official 44:2ce89a25b635 2186 #define LCD_WF8B_BPDLCD2_MASK 0x8u
mbed_official 44:2ce89a25b635 2187 #define LCD_WF8B_BPDLCD2_SHIFT 3
mbed_official 44:2ce89a25b635 2188 #define LCD_WF8B_BPDLCD55_MASK 0x8u
mbed_official 44:2ce89a25b635 2189 #define LCD_WF8B_BPDLCD55_SHIFT 3
mbed_official 44:2ce89a25b635 2190 #define LCD_WF8B_BPDLCD59_MASK 0x8u
mbed_official 44:2ce89a25b635 2191 #define LCD_WF8B_BPDLCD59_SHIFT 3
mbed_official 44:2ce89a25b635 2192 #define LCD_WF8B_BPDLCD5_MASK 0x8u
mbed_official 44:2ce89a25b635 2193 #define LCD_WF8B_BPDLCD5_SHIFT 3
mbed_official 44:2ce89a25b635 2194 #define LCD_WF8B_BPDLCD19_MASK 0x8u
mbed_official 44:2ce89a25b635 2195 #define LCD_WF8B_BPDLCD19_SHIFT 3
mbed_official 44:2ce89a25b635 2196 #define LCD_WF8B_BPDLCD6_MASK 0x8u
mbed_official 44:2ce89a25b635 2197 #define LCD_WF8B_BPDLCD6_SHIFT 3
mbed_official 44:2ce89a25b635 2198 #define LCD_WF8B_BPDLCD26_MASK 0x8u
mbed_official 44:2ce89a25b635 2199 #define LCD_WF8B_BPDLCD26_SHIFT 3
mbed_official 44:2ce89a25b635 2200 #define LCD_WF8B_BPDLCD0_MASK 0x8u
mbed_official 44:2ce89a25b635 2201 #define LCD_WF8B_BPDLCD0_SHIFT 3
mbed_official 44:2ce89a25b635 2202 #define LCD_WF8B_BPDLCD50_MASK 0x8u
mbed_official 44:2ce89a25b635 2203 #define LCD_WF8B_BPDLCD50_SHIFT 3
mbed_official 44:2ce89a25b635 2204 #define LCD_WF8B_BPDLCD46_MASK 0x8u
mbed_official 44:2ce89a25b635 2205 #define LCD_WF8B_BPDLCD46_SHIFT 3
mbed_official 44:2ce89a25b635 2206 #define LCD_WF8B_BPDLCD18_MASK 0x8u
mbed_official 44:2ce89a25b635 2207 #define LCD_WF8B_BPDLCD18_SHIFT 3
mbed_official 44:2ce89a25b635 2208 #define LCD_WF8B_BPDLCD61_MASK 0x8u
mbed_official 44:2ce89a25b635 2209 #define LCD_WF8B_BPDLCD61_SHIFT 3
mbed_official 44:2ce89a25b635 2210 #define LCD_WF8B_BPDLCD9_MASK 0x8u
mbed_official 44:2ce89a25b635 2211 #define LCD_WF8B_BPDLCD9_SHIFT 3
mbed_official 44:2ce89a25b635 2212 #define LCD_WF8B_BPDLCD17_MASK 0x8u
mbed_official 44:2ce89a25b635 2213 #define LCD_WF8B_BPDLCD17_SHIFT 3
mbed_official 44:2ce89a25b635 2214 #define LCD_WF8B_BPDLCD27_MASK 0x8u
mbed_official 44:2ce89a25b635 2215 #define LCD_WF8B_BPDLCD27_SHIFT 3
mbed_official 44:2ce89a25b635 2216 #define LCD_WF8B_BPDLCD53_MASK 0x8u
mbed_official 44:2ce89a25b635 2217 #define LCD_WF8B_BPDLCD53_SHIFT 3
mbed_official 44:2ce89a25b635 2218 #define LCD_WF8B_BPDLCD51_MASK 0x8u
mbed_official 44:2ce89a25b635 2219 #define LCD_WF8B_BPDLCD51_SHIFT 3
mbed_official 44:2ce89a25b635 2220 #define LCD_WF8B_BPDLCD54_MASK 0x8u
mbed_official 44:2ce89a25b635 2221 #define LCD_WF8B_BPDLCD54_SHIFT 3
mbed_official 44:2ce89a25b635 2222 #define LCD_WF8B_BPDLCD13_MASK 0x8u
mbed_official 44:2ce89a25b635 2223 #define LCD_WF8B_BPDLCD13_SHIFT 3
mbed_official 44:2ce89a25b635 2224 #define LCD_WF8B_BPDLCD16_MASK 0x8u
mbed_official 44:2ce89a25b635 2225 #define LCD_WF8B_BPDLCD16_SHIFT 3
mbed_official 44:2ce89a25b635 2226 #define LCD_WF8B_BPDLCD32_MASK 0x8u
mbed_official 44:2ce89a25b635 2227 #define LCD_WF8B_BPDLCD32_SHIFT 3
mbed_official 44:2ce89a25b635 2228 #define LCD_WF8B_BPDLCD14_MASK 0x8u
mbed_official 44:2ce89a25b635 2229 #define LCD_WF8B_BPDLCD14_SHIFT 3
mbed_official 44:2ce89a25b635 2230 #define LCD_WF8B_BPDLCD28_MASK 0x8u
mbed_official 44:2ce89a25b635 2231 #define LCD_WF8B_BPDLCD28_SHIFT 3
mbed_official 44:2ce89a25b635 2232 #define LCD_WF8B_BPDLCD43_MASK 0x8u
mbed_official 44:2ce89a25b635 2233 #define LCD_WF8B_BPDLCD43_SHIFT 3
mbed_official 44:2ce89a25b635 2234 #define LCD_WF8B_BPDLCD4_MASK 0x8u
mbed_official 44:2ce89a25b635 2235 #define LCD_WF8B_BPDLCD4_SHIFT 3
mbed_official 44:2ce89a25b635 2236 #define LCD_WF8B_BPDLCD45_MASK 0x8u
mbed_official 44:2ce89a25b635 2237 #define LCD_WF8B_BPDLCD45_SHIFT 3
mbed_official 44:2ce89a25b635 2238 #define LCD_WF8B_BPDLCD8_MASK 0x8u
mbed_official 44:2ce89a25b635 2239 #define LCD_WF8B_BPDLCD8_SHIFT 3
mbed_official 44:2ce89a25b635 2240 #define LCD_WF8B_BPDLCD62_MASK 0x8u
mbed_official 44:2ce89a25b635 2241 #define LCD_WF8B_BPDLCD62_SHIFT 3
mbed_official 44:2ce89a25b635 2242 #define LCD_WF8B_BPDLCD33_MASK 0x8u
mbed_official 44:2ce89a25b635 2243 #define LCD_WF8B_BPDLCD33_SHIFT 3
mbed_official 44:2ce89a25b635 2244 #define LCD_WF8B_BPDLCD34_MASK 0x8u
mbed_official 44:2ce89a25b635 2245 #define LCD_WF8B_BPDLCD34_SHIFT 3
mbed_official 44:2ce89a25b635 2246 #define LCD_WF8B_BPDLCD29_MASK 0x8u
mbed_official 44:2ce89a25b635 2247 #define LCD_WF8B_BPDLCD29_SHIFT 3
mbed_official 44:2ce89a25b635 2248 #define LCD_WF8B_BPDLCD58_MASK 0x8u
mbed_official 44:2ce89a25b635 2249 #define LCD_WF8B_BPDLCD58_SHIFT 3
mbed_official 44:2ce89a25b635 2250 #define LCD_WF8B_BPDLCD57_MASK 0x8u
mbed_official 44:2ce89a25b635 2251 #define LCD_WF8B_BPDLCD57_SHIFT 3
mbed_official 44:2ce89a25b635 2252 #define LCD_WF8B_BPDLCD42_MASK 0x8u
mbed_official 44:2ce89a25b635 2253 #define LCD_WF8B_BPDLCD42_SHIFT 3
mbed_official 44:2ce89a25b635 2254 #define LCD_WF8B_BPDLCD35_MASK 0x8u
mbed_official 44:2ce89a25b635 2255 #define LCD_WF8B_BPDLCD35_SHIFT 3
mbed_official 44:2ce89a25b635 2256 #define LCD_WF8B_BPDLCD52_MASK 0x8u
mbed_official 44:2ce89a25b635 2257 #define LCD_WF8B_BPDLCD52_SHIFT 3
mbed_official 44:2ce89a25b635 2258 #define LCD_WF8B_BPDLCD7_MASK 0x8u
mbed_official 44:2ce89a25b635 2259 #define LCD_WF8B_BPDLCD7_SHIFT 3
mbed_official 44:2ce89a25b635 2260 #define LCD_WF8B_BPDLCD36_MASK 0x8u
mbed_official 44:2ce89a25b635 2261 #define LCD_WF8B_BPDLCD36_SHIFT 3
mbed_official 44:2ce89a25b635 2262 #define LCD_WF8B_BPDLCD30_MASK 0x8u
mbed_official 44:2ce89a25b635 2263 #define LCD_WF8B_BPDLCD30_SHIFT 3
mbed_official 44:2ce89a25b635 2264 #define LCD_WF8B_BPDLCD41_MASK 0x8u
mbed_official 44:2ce89a25b635 2265 #define LCD_WF8B_BPDLCD41_SHIFT 3
mbed_official 44:2ce89a25b635 2266 #define LCD_WF8B_BPDLCD37_MASK 0x8u
mbed_official 44:2ce89a25b635 2267 #define LCD_WF8B_BPDLCD37_SHIFT 3
mbed_official 44:2ce89a25b635 2268 #define LCD_WF8B_BPDLCD44_MASK 0x8u
mbed_official 44:2ce89a25b635 2269 #define LCD_WF8B_BPDLCD44_SHIFT 3
mbed_official 44:2ce89a25b635 2270 #define LCD_WF8B_BPDLCD63_MASK 0x8u
mbed_official 44:2ce89a25b635 2271 #define LCD_WF8B_BPDLCD63_SHIFT 3
mbed_official 44:2ce89a25b635 2272 #define LCD_WF8B_BPDLCD38_MASK 0x8u
mbed_official 44:2ce89a25b635 2273 #define LCD_WF8B_BPDLCD38_SHIFT 3
mbed_official 44:2ce89a25b635 2274 #define LCD_WF8B_BPDLCD56_MASK 0x8u
mbed_official 44:2ce89a25b635 2275 #define LCD_WF8B_BPDLCD56_SHIFT 3
mbed_official 44:2ce89a25b635 2276 #define LCD_WF8B_BPDLCD40_MASK 0x8u
mbed_official 44:2ce89a25b635 2277 #define LCD_WF8B_BPDLCD40_SHIFT 3
mbed_official 44:2ce89a25b635 2278 #define LCD_WF8B_BPDLCD31_MASK 0x8u
mbed_official 44:2ce89a25b635 2279 #define LCD_WF8B_BPDLCD31_SHIFT 3
mbed_official 44:2ce89a25b635 2280 #define LCD_WF8B_BPDLCD12_MASK 0x8u
mbed_official 44:2ce89a25b635 2281 #define LCD_WF8B_BPDLCD12_SHIFT 3
mbed_official 44:2ce89a25b635 2282 #define LCD_WF8B_BPDLCD39_MASK 0x8u
mbed_official 44:2ce89a25b635 2283 #define LCD_WF8B_BPDLCD39_SHIFT 3
mbed_official 44:2ce89a25b635 2284 #define LCD_WF8B_BPDLCD3_MASK 0x8u
mbed_official 44:2ce89a25b635 2285 #define LCD_WF8B_BPDLCD3_SHIFT 3
mbed_official 44:2ce89a25b635 2286 #define LCD_WF8B_BPDLCD11_MASK 0x8u
mbed_official 44:2ce89a25b635 2287 #define LCD_WF8B_BPDLCD11_SHIFT 3
mbed_official 44:2ce89a25b635 2288 #define LCD_WF8B_BPELCD12_MASK 0x10u
mbed_official 44:2ce89a25b635 2289 #define LCD_WF8B_BPELCD12_SHIFT 4
mbed_official 44:2ce89a25b635 2290 #define LCD_WF8B_BPELCD39_MASK 0x10u
mbed_official 44:2ce89a25b635 2291 #define LCD_WF8B_BPELCD39_SHIFT 4
mbed_official 44:2ce89a25b635 2292 #define LCD_WF8B_BPELCD3_MASK 0x10u
mbed_official 44:2ce89a25b635 2293 #define LCD_WF8B_BPELCD3_SHIFT 4
mbed_official 44:2ce89a25b635 2294 #define LCD_WF8B_BPELCD38_MASK 0x10u
mbed_official 44:2ce89a25b635 2295 #define LCD_WF8B_BPELCD38_SHIFT 4
mbed_official 44:2ce89a25b635 2296 #define LCD_WF8B_BPELCD40_MASK 0x10u
mbed_official 44:2ce89a25b635 2297 #define LCD_WF8B_BPELCD40_SHIFT 4
mbed_official 44:2ce89a25b635 2298 #define LCD_WF8B_BPELCD37_MASK 0x10u
mbed_official 44:2ce89a25b635 2299 #define LCD_WF8B_BPELCD37_SHIFT 4
mbed_official 44:2ce89a25b635 2300 #define LCD_WF8B_BPELCD41_MASK 0x10u
mbed_official 44:2ce89a25b635 2301 #define LCD_WF8B_BPELCD41_SHIFT 4
mbed_official 44:2ce89a25b635 2302 #define LCD_WF8B_BPELCD36_MASK 0x10u
mbed_official 44:2ce89a25b635 2303 #define LCD_WF8B_BPELCD36_SHIFT 4
mbed_official 44:2ce89a25b635 2304 #define LCD_WF8B_BPELCD8_MASK 0x10u
mbed_official 44:2ce89a25b635 2305 #define LCD_WF8B_BPELCD8_SHIFT 4
mbed_official 44:2ce89a25b635 2306 #define LCD_WF8B_BPELCD35_MASK 0x10u
mbed_official 44:2ce89a25b635 2307 #define LCD_WF8B_BPELCD35_SHIFT 4
mbed_official 44:2ce89a25b635 2308 #define LCD_WF8B_BPELCD42_MASK 0x10u
mbed_official 44:2ce89a25b635 2309 #define LCD_WF8B_BPELCD42_SHIFT 4
mbed_official 44:2ce89a25b635 2310 #define LCD_WF8B_BPELCD34_MASK 0x10u
mbed_official 44:2ce89a25b635 2311 #define LCD_WF8B_BPELCD34_SHIFT 4
mbed_official 44:2ce89a25b635 2312 #define LCD_WF8B_BPELCD33_MASK 0x10u
mbed_official 44:2ce89a25b635 2313 #define LCD_WF8B_BPELCD33_SHIFT 4
mbed_official 44:2ce89a25b635 2314 #define LCD_WF8B_BPELCD11_MASK 0x10u
mbed_official 44:2ce89a25b635 2315 #define LCD_WF8B_BPELCD11_SHIFT 4
mbed_official 44:2ce89a25b635 2316 #define LCD_WF8B_BPELCD43_MASK 0x10u
mbed_official 44:2ce89a25b635 2317 #define LCD_WF8B_BPELCD43_SHIFT 4
mbed_official 44:2ce89a25b635 2318 #define LCD_WF8B_BPELCD32_MASK 0x10u
mbed_official 44:2ce89a25b635 2319 #define LCD_WF8B_BPELCD32_SHIFT 4
mbed_official 44:2ce89a25b635 2320 #define LCD_WF8B_BPELCD31_MASK 0x10u
mbed_official 44:2ce89a25b635 2321 #define LCD_WF8B_BPELCD31_SHIFT 4
mbed_official 44:2ce89a25b635 2322 #define LCD_WF8B_BPELCD44_MASK 0x10u
mbed_official 44:2ce89a25b635 2323 #define LCD_WF8B_BPELCD44_SHIFT 4
mbed_official 44:2ce89a25b635 2324 #define LCD_WF8B_BPELCD30_MASK 0x10u
mbed_official 44:2ce89a25b635 2325 #define LCD_WF8B_BPELCD30_SHIFT 4
mbed_official 44:2ce89a25b635 2326 #define LCD_WF8B_BPELCD29_MASK 0x10u
mbed_official 44:2ce89a25b635 2327 #define LCD_WF8B_BPELCD29_SHIFT 4
mbed_official 44:2ce89a25b635 2328 #define LCD_WF8B_BPELCD7_MASK 0x10u
mbed_official 44:2ce89a25b635 2329 #define LCD_WF8B_BPELCD7_SHIFT 4
mbed_official 44:2ce89a25b635 2330 #define LCD_WF8B_BPELCD45_MASK 0x10u
mbed_official 44:2ce89a25b635 2331 #define LCD_WF8B_BPELCD45_SHIFT 4
mbed_official 44:2ce89a25b635 2332 #define LCD_WF8B_BPELCD28_MASK 0x10u
mbed_official 44:2ce89a25b635 2333 #define LCD_WF8B_BPELCD28_SHIFT 4
mbed_official 44:2ce89a25b635 2334 #define LCD_WF8B_BPELCD2_MASK 0x10u
mbed_official 44:2ce89a25b635 2335 #define LCD_WF8B_BPELCD2_SHIFT 4
mbed_official 44:2ce89a25b635 2336 #define LCD_WF8B_BPELCD27_MASK 0x10u
mbed_official 44:2ce89a25b635 2337 #define LCD_WF8B_BPELCD27_SHIFT 4
mbed_official 44:2ce89a25b635 2338 #define LCD_WF8B_BPELCD46_MASK 0x10u
mbed_official 44:2ce89a25b635 2339 #define LCD_WF8B_BPELCD46_SHIFT 4
mbed_official 44:2ce89a25b635 2340 #define LCD_WF8B_BPELCD26_MASK 0x10u
mbed_official 44:2ce89a25b635 2341 #define LCD_WF8B_BPELCD26_SHIFT 4
mbed_official 44:2ce89a25b635 2342 #define LCD_WF8B_BPELCD10_MASK 0x10u
mbed_official 44:2ce89a25b635 2343 #define LCD_WF8B_BPELCD10_SHIFT 4
mbed_official 44:2ce89a25b635 2344 #define LCD_WF8B_BPELCD13_MASK 0x10u
mbed_official 44:2ce89a25b635 2345 #define LCD_WF8B_BPELCD13_SHIFT 4
mbed_official 44:2ce89a25b635 2346 #define LCD_WF8B_BPELCD25_MASK 0x10u
mbed_official 44:2ce89a25b635 2347 #define LCD_WF8B_BPELCD25_SHIFT 4
mbed_official 44:2ce89a25b635 2348 #define LCD_WF8B_BPELCD5_MASK 0x10u
mbed_official 44:2ce89a25b635 2349 #define LCD_WF8B_BPELCD5_SHIFT 4
mbed_official 44:2ce89a25b635 2350 #define LCD_WF8B_BPELCD24_MASK 0x10u
mbed_official 44:2ce89a25b635 2351 #define LCD_WF8B_BPELCD24_SHIFT 4
mbed_official 44:2ce89a25b635 2352 #define LCD_WF8B_BPELCD47_MASK 0x10u
mbed_official 44:2ce89a25b635 2353 #define LCD_WF8B_BPELCD47_SHIFT 4
mbed_official 44:2ce89a25b635 2354 #define LCD_WF8B_BPELCD23_MASK 0x10u
mbed_official 44:2ce89a25b635 2355 #define LCD_WF8B_BPELCD23_SHIFT 4
mbed_official 44:2ce89a25b635 2356 #define LCD_WF8B_BPELCD22_MASK 0x10u
mbed_official 44:2ce89a25b635 2357 #define LCD_WF8B_BPELCD22_SHIFT 4
mbed_official 44:2ce89a25b635 2358 #define LCD_WF8B_BPELCD48_MASK 0x10u
mbed_official 44:2ce89a25b635 2359 #define LCD_WF8B_BPELCD48_SHIFT 4
mbed_official 44:2ce89a25b635 2360 #define LCD_WF8B_BPELCD21_MASK 0x10u
mbed_official 44:2ce89a25b635 2361 #define LCD_WF8B_BPELCD21_SHIFT 4
mbed_official 44:2ce89a25b635 2362 #define LCD_WF8B_BPELCD49_MASK 0x10u
mbed_official 44:2ce89a25b635 2363 #define LCD_WF8B_BPELCD49_SHIFT 4
mbed_official 44:2ce89a25b635 2364 #define LCD_WF8B_BPELCD20_MASK 0x10u
mbed_official 44:2ce89a25b635 2365 #define LCD_WF8B_BPELCD20_SHIFT 4
mbed_official 44:2ce89a25b635 2366 #define LCD_WF8B_BPELCD19_MASK 0x10u
mbed_official 44:2ce89a25b635 2367 #define LCD_WF8B_BPELCD19_SHIFT 4
mbed_official 44:2ce89a25b635 2368 #define LCD_WF8B_BPELCD9_MASK 0x10u
mbed_official 44:2ce89a25b635 2369 #define LCD_WF8B_BPELCD9_SHIFT 4
mbed_official 44:2ce89a25b635 2370 #define LCD_WF8B_BPELCD50_MASK 0x10u
mbed_official 44:2ce89a25b635 2371 #define LCD_WF8B_BPELCD50_SHIFT 4
mbed_official 44:2ce89a25b635 2372 #define LCD_WF8B_BPELCD18_MASK 0x10u
mbed_official 44:2ce89a25b635 2373 #define LCD_WF8B_BPELCD18_SHIFT 4
mbed_official 44:2ce89a25b635 2374 #define LCD_WF8B_BPELCD6_MASK 0x10u
mbed_official 44:2ce89a25b635 2375 #define LCD_WF8B_BPELCD6_SHIFT 4
mbed_official 44:2ce89a25b635 2376 #define LCD_WF8B_BPELCD17_MASK 0x10u
mbed_official 44:2ce89a25b635 2377 #define LCD_WF8B_BPELCD17_SHIFT 4
mbed_official 44:2ce89a25b635 2378 #define LCD_WF8B_BPELCD51_MASK 0x10u
mbed_official 44:2ce89a25b635 2379 #define LCD_WF8B_BPELCD51_SHIFT 4
mbed_official 44:2ce89a25b635 2380 #define LCD_WF8B_BPELCD16_MASK 0x10u
mbed_official 44:2ce89a25b635 2381 #define LCD_WF8B_BPELCD16_SHIFT 4
mbed_official 44:2ce89a25b635 2382 #define LCD_WF8B_BPELCD56_MASK 0x10u
mbed_official 44:2ce89a25b635 2383 #define LCD_WF8B_BPELCD56_SHIFT 4
mbed_official 44:2ce89a25b635 2384 #define LCD_WF8B_BPELCD57_MASK 0x10u
mbed_official 44:2ce89a25b635 2385 #define LCD_WF8B_BPELCD57_SHIFT 4
mbed_official 44:2ce89a25b635 2386 #define LCD_WF8B_BPELCD52_MASK 0x10u
mbed_official 44:2ce89a25b635 2387 #define LCD_WF8B_BPELCD52_SHIFT 4
mbed_official 44:2ce89a25b635 2388 #define LCD_WF8B_BPELCD1_MASK 0x10u
mbed_official 44:2ce89a25b635 2389 #define LCD_WF8B_BPELCD1_SHIFT 4
mbed_official 44:2ce89a25b635 2390 #define LCD_WF8B_BPELCD58_MASK 0x10u
mbed_official 44:2ce89a25b635 2391 #define LCD_WF8B_BPELCD58_SHIFT 4
mbed_official 44:2ce89a25b635 2392 #define LCD_WF8B_BPELCD59_MASK 0x10u
mbed_official 44:2ce89a25b635 2393 #define LCD_WF8B_BPELCD59_SHIFT 4
mbed_official 44:2ce89a25b635 2394 #define LCD_WF8B_BPELCD53_MASK 0x10u
mbed_official 44:2ce89a25b635 2395 #define LCD_WF8B_BPELCD53_SHIFT 4
mbed_official 44:2ce89a25b635 2396 #define LCD_WF8B_BPELCD14_MASK 0x10u
mbed_official 44:2ce89a25b635 2397 #define LCD_WF8B_BPELCD14_SHIFT 4
mbed_official 44:2ce89a25b635 2398 #define LCD_WF8B_BPELCD0_MASK 0x10u
mbed_official 44:2ce89a25b635 2399 #define LCD_WF8B_BPELCD0_SHIFT 4
mbed_official 44:2ce89a25b635 2400 #define LCD_WF8B_BPELCD60_MASK 0x10u
mbed_official 44:2ce89a25b635 2401 #define LCD_WF8B_BPELCD60_SHIFT 4
mbed_official 44:2ce89a25b635 2402 #define LCD_WF8B_BPELCD15_MASK 0x10u
mbed_official 44:2ce89a25b635 2403 #define LCD_WF8B_BPELCD15_SHIFT 4
mbed_official 44:2ce89a25b635 2404 #define LCD_WF8B_BPELCD61_MASK 0x10u
mbed_official 44:2ce89a25b635 2405 #define LCD_WF8B_BPELCD61_SHIFT 4
mbed_official 44:2ce89a25b635 2406 #define LCD_WF8B_BPELCD54_MASK 0x10u
mbed_official 44:2ce89a25b635 2407 #define LCD_WF8B_BPELCD54_SHIFT 4
mbed_official 44:2ce89a25b635 2408 #define LCD_WF8B_BPELCD62_MASK 0x10u
mbed_official 44:2ce89a25b635 2409 #define LCD_WF8B_BPELCD62_SHIFT 4
mbed_official 44:2ce89a25b635 2410 #define LCD_WF8B_BPELCD63_MASK 0x10u
mbed_official 44:2ce89a25b635 2411 #define LCD_WF8B_BPELCD63_SHIFT 4
mbed_official 44:2ce89a25b635 2412 #define LCD_WF8B_BPELCD55_MASK 0x10u
mbed_official 44:2ce89a25b635 2413 #define LCD_WF8B_BPELCD55_SHIFT 4
mbed_official 44:2ce89a25b635 2414 #define LCD_WF8B_BPELCD4_MASK 0x10u
mbed_official 44:2ce89a25b635 2415 #define LCD_WF8B_BPELCD4_SHIFT 4
mbed_official 44:2ce89a25b635 2416 #define LCD_WF8B_BPFLCD13_MASK 0x20u
mbed_official 44:2ce89a25b635 2417 #define LCD_WF8B_BPFLCD13_SHIFT 5
mbed_official 44:2ce89a25b635 2418 #define LCD_WF8B_BPFLCD39_MASK 0x20u
mbed_official 44:2ce89a25b635 2419 #define LCD_WF8B_BPFLCD39_SHIFT 5
mbed_official 44:2ce89a25b635 2420 #define LCD_WF8B_BPFLCD55_MASK 0x20u
mbed_official 44:2ce89a25b635 2421 #define LCD_WF8B_BPFLCD55_SHIFT 5
mbed_official 44:2ce89a25b635 2422 #define LCD_WF8B_BPFLCD47_MASK 0x20u
mbed_official 44:2ce89a25b635 2423 #define LCD_WF8B_BPFLCD47_SHIFT 5
mbed_official 44:2ce89a25b635 2424 #define LCD_WF8B_BPFLCD63_MASK 0x20u
mbed_official 44:2ce89a25b635 2425 #define LCD_WF8B_BPFLCD63_SHIFT 5
mbed_official 44:2ce89a25b635 2426 #define LCD_WF8B_BPFLCD43_MASK 0x20u
mbed_official 44:2ce89a25b635 2427 #define LCD_WF8B_BPFLCD43_SHIFT 5
mbed_official 44:2ce89a25b635 2428 #define LCD_WF8B_BPFLCD5_MASK 0x20u
mbed_official 44:2ce89a25b635 2429 #define LCD_WF8B_BPFLCD5_SHIFT 5
mbed_official 44:2ce89a25b635 2430 #define LCD_WF8B_BPFLCD62_MASK 0x20u
mbed_official 44:2ce89a25b635 2431 #define LCD_WF8B_BPFLCD62_SHIFT 5
mbed_official 44:2ce89a25b635 2432 #define LCD_WF8B_BPFLCD14_MASK 0x20u
mbed_official 44:2ce89a25b635 2433 #define LCD_WF8B_BPFLCD14_SHIFT 5
mbed_official 44:2ce89a25b635 2434 #define LCD_WF8B_BPFLCD24_MASK 0x20u
mbed_official 44:2ce89a25b635 2435 #define LCD_WF8B_BPFLCD24_SHIFT 5
mbed_official 44:2ce89a25b635 2436 #define LCD_WF8B_BPFLCD54_MASK 0x20u
mbed_official 44:2ce89a25b635 2437 #define LCD_WF8B_BPFLCD54_SHIFT 5
mbed_official 44:2ce89a25b635 2438 #define LCD_WF8B_BPFLCD15_MASK 0x20u
mbed_official 44:2ce89a25b635 2439 #define LCD_WF8B_BPFLCD15_SHIFT 5
mbed_official 44:2ce89a25b635 2440 #define LCD_WF8B_BPFLCD32_MASK 0x20u
mbed_official 44:2ce89a25b635 2441 #define LCD_WF8B_BPFLCD32_SHIFT 5
mbed_official 44:2ce89a25b635 2442 #define LCD_WF8B_BPFLCD61_MASK 0x20u
mbed_official 44:2ce89a25b635 2443 #define LCD_WF8B_BPFLCD61_SHIFT 5
mbed_official 44:2ce89a25b635 2444 #define LCD_WF8B_BPFLCD25_MASK 0x20u
mbed_official 44:2ce89a25b635 2445 #define LCD_WF8B_BPFLCD25_SHIFT 5
mbed_official 44:2ce89a25b635 2446 #define LCD_WF8B_BPFLCD60_MASK 0x20u
mbed_official 44:2ce89a25b635 2447 #define LCD_WF8B_BPFLCD60_SHIFT 5
mbed_official 44:2ce89a25b635 2448 #define LCD_WF8B_BPFLCD41_MASK 0x20u
mbed_official 44:2ce89a25b635 2449 #define LCD_WF8B_BPFLCD41_SHIFT 5
mbed_official 44:2ce89a25b635 2450 #define LCD_WF8B_BPFLCD33_MASK 0x20u
mbed_official 44:2ce89a25b635 2451 #define LCD_WF8B_BPFLCD33_SHIFT 5
mbed_official 44:2ce89a25b635 2452 #define LCD_WF8B_BPFLCD53_MASK 0x20u
mbed_official 44:2ce89a25b635 2453 #define LCD_WF8B_BPFLCD53_SHIFT 5
mbed_official 44:2ce89a25b635 2454 #define LCD_WF8B_BPFLCD59_MASK 0x20u
mbed_official 44:2ce89a25b635 2455 #define LCD_WF8B_BPFLCD59_SHIFT 5
mbed_official 44:2ce89a25b635 2456 #define LCD_WF8B_BPFLCD0_MASK 0x20u
mbed_official 44:2ce89a25b635 2457 #define LCD_WF8B_BPFLCD0_SHIFT 5
mbed_official 44:2ce89a25b635 2458 #define LCD_WF8B_BPFLCD46_MASK 0x20u
mbed_official 44:2ce89a25b635 2459 #define LCD_WF8B_BPFLCD46_SHIFT 5
mbed_official 44:2ce89a25b635 2460 #define LCD_WF8B_BPFLCD58_MASK 0x20u
mbed_official 44:2ce89a25b635 2461 #define LCD_WF8B_BPFLCD58_SHIFT 5
mbed_official 44:2ce89a25b635 2462 #define LCD_WF8B_BPFLCD26_MASK 0x20u
mbed_official 44:2ce89a25b635 2463 #define LCD_WF8B_BPFLCD26_SHIFT 5
mbed_official 44:2ce89a25b635 2464 #define LCD_WF8B_BPFLCD36_MASK 0x20u
mbed_official 44:2ce89a25b635 2465 #define LCD_WF8B_BPFLCD36_SHIFT 5
mbed_official 44:2ce89a25b635 2466 #define LCD_WF8B_BPFLCD10_MASK 0x20u
mbed_official 44:2ce89a25b635 2467 #define LCD_WF8B_BPFLCD10_SHIFT 5
mbed_official 44:2ce89a25b635 2468 #define LCD_WF8B_BPFLCD52_MASK 0x20u
mbed_official 44:2ce89a25b635 2469 #define LCD_WF8B_BPFLCD52_SHIFT 5
mbed_official 44:2ce89a25b635 2470 #define LCD_WF8B_BPFLCD57_MASK 0x20u
mbed_official 44:2ce89a25b635 2471 #define LCD_WF8B_BPFLCD57_SHIFT 5
mbed_official 44:2ce89a25b635 2472 #define LCD_WF8B_BPFLCD27_MASK 0x20u
mbed_official 44:2ce89a25b635 2473 #define LCD_WF8B_BPFLCD27_SHIFT 5
mbed_official 44:2ce89a25b635 2474 #define LCD_WF8B_BPFLCD11_MASK 0x20u
mbed_official 44:2ce89a25b635 2475 #define LCD_WF8B_BPFLCD11_SHIFT 5
mbed_official 44:2ce89a25b635 2476 #define LCD_WF8B_BPFLCD56_MASK 0x20u
mbed_official 44:2ce89a25b635 2477 #define LCD_WF8B_BPFLCD56_SHIFT 5
mbed_official 44:2ce89a25b635 2478 #define LCD_WF8B_BPFLCD1_MASK 0x20u
mbed_official 44:2ce89a25b635 2479 #define LCD_WF8B_BPFLCD1_SHIFT 5
mbed_official 44:2ce89a25b635 2480 #define LCD_WF8B_BPFLCD8_MASK 0x20u
mbed_official 44:2ce89a25b635 2481 #define LCD_WF8B_BPFLCD8_SHIFT 5
mbed_official 44:2ce89a25b635 2482 #define LCD_WF8B_BPFLCD40_MASK 0x20u
mbed_official 44:2ce89a25b635 2483 #define LCD_WF8B_BPFLCD40_SHIFT 5
mbed_official 44:2ce89a25b635 2484 #define LCD_WF8B_BPFLCD51_MASK 0x20u
mbed_official 44:2ce89a25b635 2485 #define LCD_WF8B_BPFLCD51_SHIFT 5
mbed_official 44:2ce89a25b635 2486 #define LCD_WF8B_BPFLCD16_MASK 0x20u
mbed_official 44:2ce89a25b635 2487 #define LCD_WF8B_BPFLCD16_SHIFT 5
mbed_official 44:2ce89a25b635 2488 #define LCD_WF8B_BPFLCD45_MASK 0x20u
mbed_official 44:2ce89a25b635 2489 #define LCD_WF8B_BPFLCD45_SHIFT 5
mbed_official 44:2ce89a25b635 2490 #define LCD_WF8B_BPFLCD6_MASK 0x20u
mbed_official 44:2ce89a25b635 2491 #define LCD_WF8B_BPFLCD6_SHIFT 5
mbed_official 44:2ce89a25b635 2492 #define LCD_WF8B_BPFLCD17_MASK 0x20u
mbed_official 44:2ce89a25b635 2493 #define LCD_WF8B_BPFLCD17_SHIFT 5
mbed_official 44:2ce89a25b635 2494 #define LCD_WF8B_BPFLCD28_MASK 0x20u
mbed_official 44:2ce89a25b635 2495 #define LCD_WF8B_BPFLCD28_SHIFT 5
mbed_official 44:2ce89a25b635 2496 #define LCD_WF8B_BPFLCD42_MASK 0x20u
mbed_official 44:2ce89a25b635 2497 #define LCD_WF8B_BPFLCD42_SHIFT 5
mbed_official 44:2ce89a25b635 2498 #define LCD_WF8B_BPFLCD29_MASK 0x20u
mbed_official 44:2ce89a25b635 2499 #define LCD_WF8B_BPFLCD29_SHIFT 5
mbed_official 44:2ce89a25b635 2500 #define LCD_WF8B_BPFLCD50_MASK 0x20u
mbed_official 44:2ce89a25b635 2501 #define LCD_WF8B_BPFLCD50_SHIFT 5
mbed_official 44:2ce89a25b635 2502 #define LCD_WF8B_BPFLCD18_MASK 0x20u
mbed_official 44:2ce89a25b635 2503 #define LCD_WF8B_BPFLCD18_SHIFT 5
mbed_official 44:2ce89a25b635 2504 #define LCD_WF8B_BPFLCD34_MASK 0x20u
mbed_official 44:2ce89a25b635 2505 #define LCD_WF8B_BPFLCD34_SHIFT 5
mbed_official 44:2ce89a25b635 2506 #define LCD_WF8B_BPFLCD19_MASK 0x20u
mbed_official 44:2ce89a25b635 2507 #define LCD_WF8B_BPFLCD19_SHIFT 5
mbed_official 44:2ce89a25b635 2508 #define LCD_WF8B_BPFLCD2_MASK 0x20u
mbed_official 44:2ce89a25b635 2509 #define LCD_WF8B_BPFLCD2_SHIFT 5
mbed_official 44:2ce89a25b635 2510 #define LCD_WF8B_BPFLCD9_MASK 0x20u
mbed_official 44:2ce89a25b635 2511 #define LCD_WF8B_BPFLCD9_SHIFT 5
mbed_official 44:2ce89a25b635 2512 #define LCD_WF8B_BPFLCD3_MASK 0x20u
mbed_official 44:2ce89a25b635 2513 #define LCD_WF8B_BPFLCD3_SHIFT 5
mbed_official 44:2ce89a25b635 2514 #define LCD_WF8B_BPFLCD37_MASK 0x20u
mbed_official 44:2ce89a25b635 2515 #define LCD_WF8B_BPFLCD37_SHIFT 5
mbed_official 44:2ce89a25b635 2516 #define LCD_WF8B_BPFLCD49_MASK 0x20u
mbed_official 44:2ce89a25b635 2517 #define LCD_WF8B_BPFLCD49_SHIFT 5
mbed_official 44:2ce89a25b635 2518 #define LCD_WF8B_BPFLCD20_MASK 0x20u
mbed_official 44:2ce89a25b635 2519 #define LCD_WF8B_BPFLCD20_SHIFT 5
mbed_official 44:2ce89a25b635 2520 #define LCD_WF8B_BPFLCD44_MASK 0x20u
mbed_official 44:2ce89a25b635 2521 #define LCD_WF8B_BPFLCD44_SHIFT 5
mbed_official 44:2ce89a25b635 2522 #define LCD_WF8B_BPFLCD30_MASK 0x20u
mbed_official 44:2ce89a25b635 2523 #define LCD_WF8B_BPFLCD30_SHIFT 5
mbed_official 44:2ce89a25b635 2524 #define LCD_WF8B_BPFLCD21_MASK 0x20u
mbed_official 44:2ce89a25b635 2525 #define LCD_WF8B_BPFLCD21_SHIFT 5
mbed_official 44:2ce89a25b635 2526 #define LCD_WF8B_BPFLCD35_MASK 0x20u
mbed_official 44:2ce89a25b635 2527 #define LCD_WF8B_BPFLCD35_SHIFT 5
mbed_official 44:2ce89a25b635 2528 #define LCD_WF8B_BPFLCD4_MASK 0x20u
mbed_official 44:2ce89a25b635 2529 #define LCD_WF8B_BPFLCD4_SHIFT 5
mbed_official 44:2ce89a25b635 2530 #define LCD_WF8B_BPFLCD31_MASK 0x20u
mbed_official 44:2ce89a25b635 2531 #define LCD_WF8B_BPFLCD31_SHIFT 5
mbed_official 44:2ce89a25b635 2532 #define LCD_WF8B_BPFLCD48_MASK 0x20u
mbed_official 44:2ce89a25b635 2533 #define LCD_WF8B_BPFLCD48_SHIFT 5
mbed_official 44:2ce89a25b635 2534 #define LCD_WF8B_BPFLCD7_MASK 0x20u
mbed_official 44:2ce89a25b635 2535 #define LCD_WF8B_BPFLCD7_SHIFT 5
mbed_official 44:2ce89a25b635 2536 #define LCD_WF8B_BPFLCD22_MASK 0x20u
mbed_official 44:2ce89a25b635 2537 #define LCD_WF8B_BPFLCD22_SHIFT 5
mbed_official 44:2ce89a25b635 2538 #define LCD_WF8B_BPFLCD38_MASK 0x20u
mbed_official 44:2ce89a25b635 2539 #define LCD_WF8B_BPFLCD38_SHIFT 5
mbed_official 44:2ce89a25b635 2540 #define LCD_WF8B_BPFLCD12_MASK 0x20u
mbed_official 44:2ce89a25b635 2541 #define LCD_WF8B_BPFLCD12_SHIFT 5
mbed_official 44:2ce89a25b635 2542 #define LCD_WF8B_BPFLCD23_MASK 0x20u
mbed_official 44:2ce89a25b635 2543 #define LCD_WF8B_BPFLCD23_SHIFT 5
mbed_official 44:2ce89a25b635 2544 #define LCD_WF8B_BPGLCD14_MASK 0x40u
mbed_official 44:2ce89a25b635 2545 #define LCD_WF8B_BPGLCD14_SHIFT 6
mbed_official 44:2ce89a25b635 2546 #define LCD_WF8B_BPGLCD55_MASK 0x40u
mbed_official 44:2ce89a25b635 2547 #define LCD_WF8B_BPGLCD55_SHIFT 6
mbed_official 44:2ce89a25b635 2548 #define LCD_WF8B_BPGLCD63_MASK 0x40u
mbed_official 44:2ce89a25b635 2549 #define LCD_WF8B_BPGLCD63_SHIFT 6
mbed_official 44:2ce89a25b635 2550 #define LCD_WF8B_BPGLCD15_MASK 0x40u
mbed_official 44:2ce89a25b635 2551 #define LCD_WF8B_BPGLCD15_SHIFT 6
mbed_official 44:2ce89a25b635 2552 #define LCD_WF8B_BPGLCD62_MASK 0x40u
mbed_official 44:2ce89a25b635 2553 #define LCD_WF8B_BPGLCD62_SHIFT 6
mbed_official 44:2ce89a25b635 2554 #define LCD_WF8B_BPGLCD54_MASK 0x40u
mbed_official 44:2ce89a25b635 2555 #define LCD_WF8B_BPGLCD54_SHIFT 6
mbed_official 44:2ce89a25b635 2556 #define LCD_WF8B_BPGLCD61_MASK 0x40u
mbed_official 44:2ce89a25b635 2557 #define LCD_WF8B_BPGLCD61_SHIFT 6
mbed_official 44:2ce89a25b635 2558 #define LCD_WF8B_BPGLCD60_MASK 0x40u
mbed_official 44:2ce89a25b635 2559 #define LCD_WF8B_BPGLCD60_SHIFT 6
mbed_official 44:2ce89a25b635 2560 #define LCD_WF8B_BPGLCD59_MASK 0x40u
mbed_official 44:2ce89a25b635 2561 #define LCD_WF8B_BPGLCD59_SHIFT 6
mbed_official 44:2ce89a25b635 2562 #define LCD_WF8B_BPGLCD53_MASK 0x40u
mbed_official 44:2ce89a25b635 2563 #define LCD_WF8B_BPGLCD53_SHIFT 6
mbed_official 44:2ce89a25b635 2564 #define LCD_WF8B_BPGLCD58_MASK 0x40u
mbed_official 44:2ce89a25b635 2565 #define LCD_WF8B_BPGLCD58_SHIFT 6
mbed_official 44:2ce89a25b635 2566 #define LCD_WF8B_BPGLCD0_MASK 0x40u
mbed_official 44:2ce89a25b635 2567 #define LCD_WF8B_BPGLCD0_SHIFT 6
mbed_official 44:2ce89a25b635 2568 #define LCD_WF8B_BPGLCD57_MASK 0x40u
mbed_official 44:2ce89a25b635 2569 #define LCD_WF8B_BPGLCD57_SHIFT 6
mbed_official 44:2ce89a25b635 2570 #define LCD_WF8B_BPGLCD52_MASK 0x40u
mbed_official 44:2ce89a25b635 2571 #define LCD_WF8B_BPGLCD52_SHIFT 6
mbed_official 44:2ce89a25b635 2572 #define LCD_WF8B_BPGLCD7_MASK 0x40u
mbed_official 44:2ce89a25b635 2573 #define LCD_WF8B_BPGLCD7_SHIFT 6
mbed_official 44:2ce89a25b635 2574 #define LCD_WF8B_BPGLCD56_MASK 0x40u
mbed_official 44:2ce89a25b635 2575 #define LCD_WF8B_BPGLCD56_SHIFT 6
mbed_official 44:2ce89a25b635 2576 #define LCD_WF8B_BPGLCD6_MASK 0x40u
mbed_official 44:2ce89a25b635 2577 #define LCD_WF8B_BPGLCD6_SHIFT 6
mbed_official 44:2ce89a25b635 2578 #define LCD_WF8B_BPGLCD51_MASK 0x40u
mbed_official 44:2ce89a25b635 2579 #define LCD_WF8B_BPGLCD51_SHIFT 6
mbed_official 44:2ce89a25b635 2580 #define LCD_WF8B_BPGLCD16_MASK 0x40u
mbed_official 44:2ce89a25b635 2581 #define LCD_WF8B_BPGLCD16_SHIFT 6
mbed_official 44:2ce89a25b635 2582 #define LCD_WF8B_BPGLCD1_MASK 0x40u
mbed_official 44:2ce89a25b635 2583 #define LCD_WF8B_BPGLCD1_SHIFT 6
mbed_official 44:2ce89a25b635 2584 #define LCD_WF8B_BPGLCD17_MASK 0x40u
mbed_official 44:2ce89a25b635 2585 #define LCD_WF8B_BPGLCD17_SHIFT 6
mbed_official 44:2ce89a25b635 2586 #define LCD_WF8B_BPGLCD50_MASK 0x40u
mbed_official 44:2ce89a25b635 2587 #define LCD_WF8B_BPGLCD50_SHIFT 6
mbed_official 44:2ce89a25b635 2588 #define LCD_WF8B_BPGLCD18_MASK 0x40u
mbed_official 44:2ce89a25b635 2589 #define LCD_WF8B_BPGLCD18_SHIFT 6
mbed_official 44:2ce89a25b635 2590 #define LCD_WF8B_BPGLCD19_MASK 0x40u
mbed_official 44:2ce89a25b635 2591 #define LCD_WF8B_BPGLCD19_SHIFT 6
mbed_official 44:2ce89a25b635 2592 #define LCD_WF8B_BPGLCD8_MASK 0x40u
mbed_official 44:2ce89a25b635 2593 #define LCD_WF8B_BPGLCD8_SHIFT 6
mbed_official 44:2ce89a25b635 2594 #define LCD_WF8B_BPGLCD49_MASK 0x40u
mbed_official 44:2ce89a25b635 2595 #define LCD_WF8B_BPGLCD49_SHIFT 6
mbed_official 44:2ce89a25b635 2596 #define LCD_WF8B_BPGLCD20_MASK 0x40u
mbed_official 44:2ce89a25b635 2597 #define LCD_WF8B_BPGLCD20_SHIFT 6
mbed_official 44:2ce89a25b635 2598 #define LCD_WF8B_BPGLCD9_MASK 0x40u
mbed_official 44:2ce89a25b635 2599 #define LCD_WF8B_BPGLCD9_SHIFT 6
mbed_official 44:2ce89a25b635 2600 #define LCD_WF8B_BPGLCD21_MASK 0x40u
mbed_official 44:2ce89a25b635 2601 #define LCD_WF8B_BPGLCD21_SHIFT 6
mbed_official 44:2ce89a25b635 2602 #define LCD_WF8B_BPGLCD13_MASK 0x40u
mbed_official 44:2ce89a25b635 2603 #define LCD_WF8B_BPGLCD13_SHIFT 6
mbed_official 44:2ce89a25b635 2604 #define LCD_WF8B_BPGLCD48_MASK 0x40u
mbed_official 44:2ce89a25b635 2605 #define LCD_WF8B_BPGLCD48_SHIFT 6
mbed_official 44:2ce89a25b635 2606 #define LCD_WF8B_BPGLCD22_MASK 0x40u
mbed_official 44:2ce89a25b635 2607 #define LCD_WF8B_BPGLCD22_SHIFT 6
mbed_official 44:2ce89a25b635 2608 #define LCD_WF8B_BPGLCD5_MASK 0x40u
mbed_official 44:2ce89a25b635 2609 #define LCD_WF8B_BPGLCD5_SHIFT 6
mbed_official 44:2ce89a25b635 2610 #define LCD_WF8B_BPGLCD47_MASK 0x40u
mbed_official 44:2ce89a25b635 2611 #define LCD_WF8B_BPGLCD47_SHIFT 6
mbed_official 44:2ce89a25b635 2612 #define LCD_WF8B_BPGLCD23_MASK 0x40u
mbed_official 44:2ce89a25b635 2613 #define LCD_WF8B_BPGLCD23_SHIFT 6
mbed_official 44:2ce89a25b635 2614 #define LCD_WF8B_BPGLCD24_MASK 0x40u
mbed_official 44:2ce89a25b635 2615 #define LCD_WF8B_BPGLCD24_SHIFT 6
mbed_official 44:2ce89a25b635 2616 #define LCD_WF8B_BPGLCD25_MASK 0x40u
mbed_official 44:2ce89a25b635 2617 #define LCD_WF8B_BPGLCD25_SHIFT 6
mbed_official 44:2ce89a25b635 2618 #define LCD_WF8B_BPGLCD46_MASK 0x40u
mbed_official 44:2ce89a25b635 2619 #define LCD_WF8B_BPGLCD46_SHIFT 6
mbed_official 44:2ce89a25b635 2620 #define LCD_WF8B_BPGLCD26_MASK 0x40u
mbed_official 44:2ce89a25b635 2621 #define LCD_WF8B_BPGLCD26_SHIFT 6
mbed_official 44:2ce89a25b635 2622 #define LCD_WF8B_BPGLCD27_MASK 0x40u
mbed_official 44:2ce89a25b635 2623 #define LCD_WF8B_BPGLCD27_SHIFT 6
mbed_official 44:2ce89a25b635 2624 #define LCD_WF8B_BPGLCD10_MASK 0x40u
mbed_official 44:2ce89a25b635 2625 #define LCD_WF8B_BPGLCD10_SHIFT 6
mbed_official 44:2ce89a25b635 2626 #define LCD_WF8B_BPGLCD45_MASK 0x40u
mbed_official 44:2ce89a25b635 2627 #define LCD_WF8B_BPGLCD45_SHIFT 6
mbed_official 44:2ce89a25b635 2628 #define LCD_WF8B_BPGLCD28_MASK 0x40u
mbed_official 44:2ce89a25b635 2629 #define LCD_WF8B_BPGLCD28_SHIFT 6
mbed_official 44:2ce89a25b635 2630 #define LCD_WF8B_BPGLCD29_MASK 0x40u
mbed_official 44:2ce89a25b635 2631 #define LCD_WF8B_BPGLCD29_SHIFT 6
mbed_official 44:2ce89a25b635 2632 #define LCD_WF8B_BPGLCD4_MASK 0x40u
mbed_official 44:2ce89a25b635 2633 #define LCD_WF8B_BPGLCD4_SHIFT 6
mbed_official 44:2ce89a25b635 2634 #define LCD_WF8B_BPGLCD44_MASK 0x40u
mbed_official 44:2ce89a25b635 2635 #define LCD_WF8B_BPGLCD44_SHIFT 6
mbed_official 44:2ce89a25b635 2636 #define LCD_WF8B_BPGLCD30_MASK 0x40u
mbed_official 44:2ce89a25b635 2637 #define LCD_WF8B_BPGLCD30_SHIFT 6
mbed_official 44:2ce89a25b635 2638 #define LCD_WF8B_BPGLCD2_MASK 0x40u
mbed_official 44:2ce89a25b635 2639 #define LCD_WF8B_BPGLCD2_SHIFT 6
mbed_official 44:2ce89a25b635 2640 #define LCD_WF8B_BPGLCD31_MASK 0x40u
mbed_official 44:2ce89a25b635 2641 #define LCD_WF8B_BPGLCD31_SHIFT 6
mbed_official 44:2ce89a25b635 2642 #define LCD_WF8B_BPGLCD43_MASK 0x40u
mbed_official 44:2ce89a25b635 2643 #define LCD_WF8B_BPGLCD43_SHIFT 6
mbed_official 44:2ce89a25b635 2644 #define LCD_WF8B_BPGLCD32_MASK 0x40u
mbed_official 44:2ce89a25b635 2645 #define LCD_WF8B_BPGLCD32_SHIFT 6
mbed_official 44:2ce89a25b635 2646 #define LCD_WF8B_BPGLCD33_MASK 0x40u
mbed_official 44:2ce89a25b635 2647 #define LCD_WF8B_BPGLCD33_SHIFT 6
mbed_official 44:2ce89a25b635 2648 #define LCD_WF8B_BPGLCD42_MASK 0x40u
mbed_official 44:2ce89a25b635 2649 #define LCD_WF8B_BPGLCD42_SHIFT 6
mbed_official 44:2ce89a25b635 2650 #define LCD_WF8B_BPGLCD34_MASK 0x40u
mbed_official 44:2ce89a25b635 2651 #define LCD_WF8B_BPGLCD34_SHIFT 6
mbed_official 44:2ce89a25b635 2652 #define LCD_WF8B_BPGLCD11_MASK 0x40u
mbed_official 44:2ce89a25b635 2653 #define LCD_WF8B_BPGLCD11_SHIFT 6
mbed_official 44:2ce89a25b635 2654 #define LCD_WF8B_BPGLCD35_MASK 0x40u
mbed_official 44:2ce89a25b635 2655 #define LCD_WF8B_BPGLCD35_SHIFT 6
mbed_official 44:2ce89a25b635 2656 #define LCD_WF8B_BPGLCD12_MASK 0x40u
mbed_official 44:2ce89a25b635 2657 #define LCD_WF8B_BPGLCD12_SHIFT 6
mbed_official 44:2ce89a25b635 2658 #define LCD_WF8B_BPGLCD41_MASK 0x40u
mbed_official 44:2ce89a25b635 2659 #define LCD_WF8B_BPGLCD41_SHIFT 6
mbed_official 44:2ce89a25b635 2660 #define LCD_WF8B_BPGLCD36_MASK 0x40u
mbed_official 44:2ce89a25b635 2661 #define LCD_WF8B_BPGLCD36_SHIFT 6
mbed_official 44:2ce89a25b635 2662 #define LCD_WF8B_BPGLCD3_MASK 0x40u
mbed_official 44:2ce89a25b635 2663 #define LCD_WF8B_BPGLCD3_SHIFT 6
mbed_official 44:2ce89a25b635 2664 #define LCD_WF8B_BPGLCD37_MASK 0x40u
mbed_official 44:2ce89a25b635 2665 #define LCD_WF8B_BPGLCD37_SHIFT 6
mbed_official 44:2ce89a25b635 2666 #define LCD_WF8B_BPGLCD40_MASK 0x40u
mbed_official 44:2ce89a25b635 2667 #define LCD_WF8B_BPGLCD40_SHIFT 6
mbed_official 44:2ce89a25b635 2668 #define LCD_WF8B_BPGLCD38_MASK 0x40u
mbed_official 44:2ce89a25b635 2669 #define LCD_WF8B_BPGLCD38_SHIFT 6
mbed_official 44:2ce89a25b635 2670 #define LCD_WF8B_BPGLCD39_MASK 0x40u
mbed_official 44:2ce89a25b635 2671 #define LCD_WF8B_BPGLCD39_SHIFT 6
mbed_official 44:2ce89a25b635 2672 #define LCD_WF8B_BPHLCD63_MASK 0x80u
mbed_official 44:2ce89a25b635 2673 #define LCD_WF8B_BPHLCD63_SHIFT 7
mbed_official 44:2ce89a25b635 2674 #define LCD_WF8B_BPHLCD62_MASK 0x80u
mbed_official 44:2ce89a25b635 2675 #define LCD_WF8B_BPHLCD62_SHIFT 7
mbed_official 44:2ce89a25b635 2676 #define LCD_WF8B_BPHLCD61_MASK 0x80u
mbed_official 44:2ce89a25b635 2677 #define LCD_WF8B_BPHLCD61_SHIFT 7
mbed_official 44:2ce89a25b635 2678 #define LCD_WF8B_BPHLCD60_MASK 0x80u
mbed_official 44:2ce89a25b635 2679 #define LCD_WF8B_BPHLCD60_SHIFT 7
mbed_official 44:2ce89a25b635 2680 #define LCD_WF8B_BPHLCD59_MASK 0x80u
mbed_official 44:2ce89a25b635 2681 #define LCD_WF8B_BPHLCD59_SHIFT 7
mbed_official 44:2ce89a25b635 2682 #define LCD_WF8B_BPHLCD58_MASK 0x80u
mbed_official 44:2ce89a25b635 2683 #define LCD_WF8B_BPHLCD58_SHIFT 7
mbed_official 44:2ce89a25b635 2684 #define LCD_WF8B_BPHLCD57_MASK 0x80u
mbed_official 44:2ce89a25b635 2685 #define LCD_WF8B_BPHLCD57_SHIFT 7
mbed_official 44:2ce89a25b635 2686 #define LCD_WF8B_BPHLCD0_MASK 0x80u
mbed_official 44:2ce89a25b635 2687 #define LCD_WF8B_BPHLCD0_SHIFT 7
mbed_official 44:2ce89a25b635 2688 #define LCD_WF8B_BPHLCD56_MASK 0x80u
mbed_official 44:2ce89a25b635 2689 #define LCD_WF8B_BPHLCD56_SHIFT 7
mbed_official 44:2ce89a25b635 2690 #define LCD_WF8B_BPHLCD55_MASK 0x80u
mbed_official 44:2ce89a25b635 2691 #define LCD_WF8B_BPHLCD55_SHIFT 7
mbed_official 44:2ce89a25b635 2692 #define LCD_WF8B_BPHLCD54_MASK 0x80u
mbed_official 44:2ce89a25b635 2693 #define LCD_WF8B_BPHLCD54_SHIFT 7
mbed_official 44:2ce89a25b635 2694 #define LCD_WF8B_BPHLCD53_MASK 0x80u
mbed_official 44:2ce89a25b635 2695 #define LCD_WF8B_BPHLCD53_SHIFT 7
mbed_official 44:2ce89a25b635 2696 #define LCD_WF8B_BPHLCD52_MASK 0x80u
mbed_official 44:2ce89a25b635 2697 #define LCD_WF8B_BPHLCD52_SHIFT 7
mbed_official 44:2ce89a25b635 2698 #define LCD_WF8B_BPHLCD51_MASK 0x80u
mbed_official 44:2ce89a25b635 2699 #define LCD_WF8B_BPHLCD51_SHIFT 7
mbed_official 44:2ce89a25b635 2700 #define LCD_WF8B_BPHLCD50_MASK 0x80u
mbed_official 44:2ce89a25b635 2701 #define LCD_WF8B_BPHLCD50_SHIFT 7
mbed_official 44:2ce89a25b635 2702 #define LCD_WF8B_BPHLCD1_MASK 0x80u
mbed_official 44:2ce89a25b635 2703 #define LCD_WF8B_BPHLCD1_SHIFT 7
mbed_official 44:2ce89a25b635 2704 #define LCD_WF8B_BPHLCD49_MASK 0x80u
mbed_official 44:2ce89a25b635 2705 #define LCD_WF8B_BPHLCD49_SHIFT 7
mbed_official 44:2ce89a25b635 2706 #define LCD_WF8B_BPHLCD48_MASK 0x80u
mbed_official 44:2ce89a25b635 2707 #define LCD_WF8B_BPHLCD48_SHIFT 7
mbed_official 44:2ce89a25b635 2708 #define LCD_WF8B_BPHLCD47_MASK 0x80u
mbed_official 44:2ce89a25b635 2709 #define LCD_WF8B_BPHLCD47_SHIFT 7
mbed_official 44:2ce89a25b635 2710 #define LCD_WF8B_BPHLCD46_MASK 0x80u
mbed_official 44:2ce89a25b635 2711 #define LCD_WF8B_BPHLCD46_SHIFT 7
mbed_official 44:2ce89a25b635 2712 #define LCD_WF8B_BPHLCD45_MASK 0x80u
mbed_official 44:2ce89a25b635 2713 #define LCD_WF8B_BPHLCD45_SHIFT 7
mbed_official 44:2ce89a25b635 2714 #define LCD_WF8B_BPHLCD44_MASK 0x80u
mbed_official 44:2ce89a25b635 2715 #define LCD_WF8B_BPHLCD44_SHIFT 7
mbed_official 44:2ce89a25b635 2716 #define LCD_WF8B_BPHLCD43_MASK 0x80u
mbed_official 44:2ce89a25b635 2717 #define LCD_WF8B_BPHLCD43_SHIFT 7
mbed_official 44:2ce89a25b635 2718 #define LCD_WF8B_BPHLCD2_MASK 0x80u
mbed_official 44:2ce89a25b635 2719 #define LCD_WF8B_BPHLCD2_SHIFT 7
mbed_official 44:2ce89a25b635 2720 #define LCD_WF8B_BPHLCD42_MASK 0x80u
mbed_official 44:2ce89a25b635 2721 #define LCD_WF8B_BPHLCD42_SHIFT 7
mbed_official 44:2ce89a25b635 2722 #define LCD_WF8B_BPHLCD41_MASK 0x80u
mbed_official 44:2ce89a25b635 2723 #define LCD_WF8B_BPHLCD41_SHIFT 7
mbed_official 44:2ce89a25b635 2724 #define LCD_WF8B_BPHLCD40_MASK 0x80u
mbed_official 44:2ce89a25b635 2725 #define LCD_WF8B_BPHLCD40_SHIFT 7
mbed_official 44:2ce89a25b635 2726 #define LCD_WF8B_BPHLCD39_MASK 0x80u
mbed_official 44:2ce89a25b635 2727 #define LCD_WF8B_BPHLCD39_SHIFT 7
mbed_official 44:2ce89a25b635 2728 #define LCD_WF8B_BPHLCD38_MASK 0x80u
mbed_official 44:2ce89a25b635 2729 #define LCD_WF8B_BPHLCD38_SHIFT 7
mbed_official 44:2ce89a25b635 2730 #define LCD_WF8B_BPHLCD37_MASK 0x80u
mbed_official 44:2ce89a25b635 2731 #define LCD_WF8B_BPHLCD37_SHIFT 7
mbed_official 44:2ce89a25b635 2732 #define LCD_WF8B_BPHLCD36_MASK 0x80u
mbed_official 44:2ce89a25b635 2733 #define LCD_WF8B_BPHLCD36_SHIFT 7
mbed_official 44:2ce89a25b635 2734 #define LCD_WF8B_BPHLCD3_MASK 0x80u
mbed_official 44:2ce89a25b635 2735 #define LCD_WF8B_BPHLCD3_SHIFT 7
mbed_official 44:2ce89a25b635 2736 #define LCD_WF8B_BPHLCD35_MASK 0x80u
mbed_official 44:2ce89a25b635 2737 #define LCD_WF8B_BPHLCD35_SHIFT 7
mbed_official 44:2ce89a25b635 2738 #define LCD_WF8B_BPHLCD34_MASK 0x80u
mbed_official 44:2ce89a25b635 2739 #define LCD_WF8B_BPHLCD34_SHIFT 7
mbed_official 44:2ce89a25b635 2740 #define LCD_WF8B_BPHLCD33_MASK 0x80u
mbed_official 44:2ce89a25b635 2741 #define LCD_WF8B_BPHLCD33_SHIFT 7
mbed_official 44:2ce89a25b635 2742 #define LCD_WF8B_BPHLCD32_MASK 0x80u
mbed_official 44:2ce89a25b635 2743 #define LCD_WF8B_BPHLCD32_SHIFT 7
mbed_official 44:2ce89a25b635 2744 #define LCD_WF8B_BPHLCD31_MASK 0x80u
mbed_official 44:2ce89a25b635 2745 #define LCD_WF8B_BPHLCD31_SHIFT 7
mbed_official 44:2ce89a25b635 2746 #define LCD_WF8B_BPHLCD30_MASK 0x80u
mbed_official 44:2ce89a25b635 2747 #define LCD_WF8B_BPHLCD30_SHIFT 7
mbed_official 44:2ce89a25b635 2748 #define LCD_WF8B_BPHLCD29_MASK 0x80u
mbed_official 44:2ce89a25b635 2749 #define LCD_WF8B_BPHLCD29_SHIFT 7
mbed_official 44:2ce89a25b635 2750 #define LCD_WF8B_BPHLCD4_MASK 0x80u
mbed_official 44:2ce89a25b635 2751 #define LCD_WF8B_BPHLCD4_SHIFT 7
mbed_official 44:2ce89a25b635 2752 #define LCD_WF8B_BPHLCD28_MASK 0x80u
mbed_official 44:2ce89a25b635 2753 #define LCD_WF8B_BPHLCD28_SHIFT 7
mbed_official 44:2ce89a25b635 2754 #define LCD_WF8B_BPHLCD27_MASK 0x80u
mbed_official 44:2ce89a25b635 2755 #define LCD_WF8B_BPHLCD27_SHIFT 7
mbed_official 44:2ce89a25b635 2756 #define LCD_WF8B_BPHLCD26_MASK 0x80u
mbed_official 44:2ce89a25b635 2757 #define LCD_WF8B_BPHLCD26_SHIFT 7
mbed_official 44:2ce89a25b635 2758 #define LCD_WF8B_BPHLCD25_MASK 0x80u
mbed_official 44:2ce89a25b635 2759 #define LCD_WF8B_BPHLCD25_SHIFT 7
mbed_official 44:2ce89a25b635 2760 #define LCD_WF8B_BPHLCD24_MASK 0x80u
mbed_official 44:2ce89a25b635 2761 #define LCD_WF8B_BPHLCD24_SHIFT 7
mbed_official 44:2ce89a25b635 2762 #define LCD_WF8B_BPHLCD23_MASK 0x80u
mbed_official 44:2ce89a25b635 2763 #define LCD_WF8B_BPHLCD23_SHIFT 7
mbed_official 44:2ce89a25b635 2764 #define LCD_WF8B_BPHLCD22_MASK 0x80u
mbed_official 44:2ce89a25b635 2765 #define LCD_WF8B_BPHLCD22_SHIFT 7
mbed_official 44:2ce89a25b635 2766 #define LCD_WF8B_BPHLCD5_MASK 0x80u
mbed_official 44:2ce89a25b635 2767 #define LCD_WF8B_BPHLCD5_SHIFT 7
mbed_official 44:2ce89a25b635 2768 #define LCD_WF8B_BPHLCD21_MASK 0x80u
mbed_official 44:2ce89a25b635 2769 #define LCD_WF8B_BPHLCD21_SHIFT 7
mbed_official 44:2ce89a25b635 2770 #define LCD_WF8B_BPHLCD20_MASK 0x80u
mbed_official 44:2ce89a25b635 2771 #define LCD_WF8B_BPHLCD20_SHIFT 7
mbed_official 44:2ce89a25b635 2772 #define LCD_WF8B_BPHLCD19_MASK 0x80u
mbed_official 44:2ce89a25b635 2773 #define LCD_WF8B_BPHLCD19_SHIFT 7
mbed_official 44:2ce89a25b635 2774 #define LCD_WF8B_BPHLCD18_MASK 0x80u
mbed_official 44:2ce89a25b635 2775 #define LCD_WF8B_BPHLCD18_SHIFT 7
mbed_official 44:2ce89a25b635 2776 #define LCD_WF8B_BPHLCD17_MASK 0x80u
mbed_official 44:2ce89a25b635 2777 #define LCD_WF8B_BPHLCD17_SHIFT 7
mbed_official 44:2ce89a25b635 2778 #define LCD_WF8B_BPHLCD16_MASK 0x80u
mbed_official 44:2ce89a25b635 2779 #define LCD_WF8B_BPHLCD16_SHIFT 7
mbed_official 44:2ce89a25b635 2780 #define LCD_WF8B_BPHLCD15_MASK 0x80u
mbed_official 44:2ce89a25b635 2781 #define LCD_WF8B_BPHLCD15_SHIFT 7
mbed_official 44:2ce89a25b635 2782 #define LCD_WF8B_BPHLCD6_MASK 0x80u
mbed_official 44:2ce89a25b635 2783 #define LCD_WF8B_BPHLCD6_SHIFT 7
mbed_official 44:2ce89a25b635 2784 #define LCD_WF8B_BPHLCD14_MASK 0x80u
mbed_official 44:2ce89a25b635 2785 #define LCD_WF8B_BPHLCD14_SHIFT 7
mbed_official 44:2ce89a25b635 2786 #define LCD_WF8B_BPHLCD13_MASK 0x80u
mbed_official 44:2ce89a25b635 2787 #define LCD_WF8B_BPHLCD13_SHIFT 7
mbed_official 44:2ce89a25b635 2788 #define LCD_WF8B_BPHLCD12_MASK 0x80u
mbed_official 44:2ce89a25b635 2789 #define LCD_WF8B_BPHLCD12_SHIFT 7
mbed_official 44:2ce89a25b635 2790 #define LCD_WF8B_BPHLCD11_MASK 0x80u
mbed_official 44:2ce89a25b635 2791 #define LCD_WF8B_BPHLCD11_SHIFT 7
mbed_official 44:2ce89a25b635 2792 #define LCD_WF8B_BPHLCD10_MASK 0x80u
mbed_official 44:2ce89a25b635 2793 #define LCD_WF8B_BPHLCD10_SHIFT 7
mbed_official 44:2ce89a25b635 2794 #define LCD_WF8B_BPHLCD9_MASK 0x80u
mbed_official 44:2ce89a25b635 2795 #define LCD_WF8B_BPHLCD9_SHIFT 7
mbed_official 44:2ce89a25b635 2796 #define LCD_WF8B_BPHLCD8_MASK 0x80u
mbed_official 44:2ce89a25b635 2797 #define LCD_WF8B_BPHLCD8_SHIFT 7
mbed_official 44:2ce89a25b635 2798 #define LCD_WF8B_BPHLCD7_MASK 0x80u
mbed_official 44:2ce89a25b635 2799 #define LCD_WF8B_BPHLCD7_SHIFT 7
mbed_official 44:2ce89a25b635 2800
mbed_official 44:2ce89a25b635 2801 /**
mbed_official 44:2ce89a25b635 2802 * @}
mbed_official 44:2ce89a25b635 2803 */ /* end of group LCD_Register_Masks */
mbed_official 44:2ce89a25b635 2804
mbed_official 44:2ce89a25b635 2805
mbed_official 44:2ce89a25b635 2806 /* LCD - Peripheral instance base addresses */
mbed_official 44:2ce89a25b635 2807 /** Peripheral LCD base address */
mbed_official 44:2ce89a25b635 2808 #define LCD_BASE (0x40053000u)
mbed_official 44:2ce89a25b635 2809 /** Peripheral LCD base pointer */
mbed_official 44:2ce89a25b635 2810 #define LCD ((LCD_Type *)LCD_BASE)
mbed_official 44:2ce89a25b635 2811 /** Array initializer of LCD peripheral base pointers */
mbed_official 44:2ce89a25b635 2812 #define LCD_BASES { LCD }
mbed_official 44:2ce89a25b635 2813
mbed_official 44:2ce89a25b635 2814 /**
mbed_official 44:2ce89a25b635 2815 * @}
mbed_official 44:2ce89a25b635 2816 */ /* end of group LCD_Peripheral_Access_Layer */
mbed_official 44:2ce89a25b635 2817
mbed_official 44:2ce89a25b635 2818
mbed_official 44:2ce89a25b635 2819 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 2820 -- LLWU Peripheral Access Layer
mbed_official 31:42176bc3c368 2821 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 2822
mbed_official 31:42176bc3c368 2823 /**
mbed_official 31:42176bc3c368 2824 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 31:42176bc3c368 2825 * @{
mbed_official 31:42176bc3c368 2826 */
mbed_official 31:42176bc3c368 2827
mbed_official 31:42176bc3c368 2828 /** LLWU - Register Layout Typedef */
mbed_official 31:42176bc3c368 2829 typedef struct {
mbed_official 31:42176bc3c368 2830 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 31:42176bc3c368 2831 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 31:42176bc3c368 2832 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 31:42176bc3c368 2833 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 31:42176bc3c368 2834 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 31:42176bc3c368 2835 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 31:42176bc3c368 2836 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 31:42176bc3c368 2837 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 31:42176bc3c368 2838 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 31:42176bc3c368 2839 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 31:42176bc3c368 2840 } LLWU_Type;
mbed_official 31:42176bc3c368 2841
mbed_official 31:42176bc3c368 2842 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 2843 -- LLWU Register Masks
mbed_official 31:42176bc3c368 2844 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 2845
mbed_official 31:42176bc3c368 2846 /**
mbed_official 31:42176bc3c368 2847 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 31:42176bc3c368 2848 * @{
mbed_official 31:42176bc3c368 2849 */
mbed_official 31:42176bc3c368 2850
mbed_official 31:42176bc3c368 2851 /* PE1 Bit Fields */
mbed_official 31:42176bc3c368 2852 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 31:42176bc3c368 2853 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 31:42176bc3c368 2854 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 31:42176bc3c368 2855 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 31:42176bc3c368 2856 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 31:42176bc3c368 2857 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 31:42176bc3c368 2858 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 31:42176bc3c368 2859 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 31:42176bc3c368 2860 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 31:42176bc3c368 2861 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 31:42176bc3c368 2862 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 31:42176bc3c368 2863 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 31:42176bc3c368 2864 /* PE2 Bit Fields */
mbed_official 31:42176bc3c368 2865 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 31:42176bc3c368 2866 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 31:42176bc3c368 2867 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 31:42176bc3c368 2868 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 31:42176bc3c368 2869 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 31:42176bc3c368 2870 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 31:42176bc3c368 2871 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 31:42176bc3c368 2872 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 31:42176bc3c368 2873 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 31:42176bc3c368 2874 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 31:42176bc3c368 2875 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 31:42176bc3c368 2876 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 31:42176bc3c368 2877 /* PE3 Bit Fields */
mbed_official 31:42176bc3c368 2878 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 31:42176bc3c368 2879 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 31:42176bc3c368 2880 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 31:42176bc3c368 2881 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 31:42176bc3c368 2882 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 31:42176bc3c368 2883 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 31:42176bc3c368 2884 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 31:42176bc3c368 2885 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 31:42176bc3c368 2886 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 31:42176bc3c368 2887 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 31:42176bc3c368 2888 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 31:42176bc3c368 2889 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 31:42176bc3c368 2890 /* PE4 Bit Fields */
mbed_official 31:42176bc3c368 2891 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 31:42176bc3c368 2892 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 31:42176bc3c368 2893 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 31:42176bc3c368 2894 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 31:42176bc3c368 2895 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 31:42176bc3c368 2896 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 31:42176bc3c368 2897 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 31:42176bc3c368 2898 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 31:42176bc3c368 2899 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 31:42176bc3c368 2900 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 31:42176bc3c368 2901 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 31:42176bc3c368 2902 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 31:42176bc3c368 2903 /* ME Bit Fields */
mbed_official 31:42176bc3c368 2904 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 31:42176bc3c368 2905 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 31:42176bc3c368 2906 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 31:42176bc3c368 2907 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 31:42176bc3c368 2908 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 31:42176bc3c368 2909 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 31:42176bc3c368 2910 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 31:42176bc3c368 2911 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 31:42176bc3c368 2912 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 31:42176bc3c368 2913 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 31:42176bc3c368 2914 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 31:42176bc3c368 2915 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 31:42176bc3c368 2916 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 31:42176bc3c368 2917 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 31:42176bc3c368 2918 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 31:42176bc3c368 2919 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 31:42176bc3c368 2920 /* F1 Bit Fields */
mbed_official 31:42176bc3c368 2921 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 31:42176bc3c368 2922 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 31:42176bc3c368 2923 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 31:42176bc3c368 2924 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 31:42176bc3c368 2925 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 31:42176bc3c368 2926 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 31:42176bc3c368 2927 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 31:42176bc3c368 2928 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 31:42176bc3c368 2929 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 31:42176bc3c368 2930 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 31:42176bc3c368 2931 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 31:42176bc3c368 2932 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 31:42176bc3c368 2933 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 31:42176bc3c368 2934 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 31:42176bc3c368 2935 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 31:42176bc3c368 2936 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 31:42176bc3c368 2937 /* F2 Bit Fields */
mbed_official 31:42176bc3c368 2938 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 31:42176bc3c368 2939 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 31:42176bc3c368 2940 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 31:42176bc3c368 2941 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 31:42176bc3c368 2942 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 31:42176bc3c368 2943 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 31:42176bc3c368 2944 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 31:42176bc3c368 2945 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 31:42176bc3c368 2946 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 31:42176bc3c368 2947 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 31:42176bc3c368 2948 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 31:42176bc3c368 2949 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 31:42176bc3c368 2950 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 31:42176bc3c368 2951 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 31:42176bc3c368 2952 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 31:42176bc3c368 2953 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 31:42176bc3c368 2954 /* F3 Bit Fields */
mbed_official 31:42176bc3c368 2955 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 31:42176bc3c368 2956 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 31:42176bc3c368 2957 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 31:42176bc3c368 2958 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 31:42176bc3c368 2959 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 31:42176bc3c368 2960 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 31:42176bc3c368 2961 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 31:42176bc3c368 2962 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 31:42176bc3c368 2963 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 31:42176bc3c368 2964 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 31:42176bc3c368 2965 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 31:42176bc3c368 2966 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 31:42176bc3c368 2967 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 31:42176bc3c368 2968 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 31:42176bc3c368 2969 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 31:42176bc3c368 2970 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 31:42176bc3c368 2971 /* FILT1 Bit Fields */
mbed_official 31:42176bc3c368 2972 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 31:42176bc3c368 2973 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 31:42176bc3c368 2974 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 31:42176bc3c368 2975 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 31:42176bc3c368 2976 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 31:42176bc3c368 2977 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 31:42176bc3c368 2978 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 31:42176bc3c368 2979 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 31:42176bc3c368 2980 /* FILT2 Bit Fields */
mbed_official 31:42176bc3c368 2981 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 31:42176bc3c368 2982 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 31:42176bc3c368 2983 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 31:42176bc3c368 2984 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 31:42176bc3c368 2985 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 31:42176bc3c368 2986 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 31:42176bc3c368 2987 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 31:42176bc3c368 2988 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 31:42176bc3c368 2989
mbed_official 31:42176bc3c368 2990 /**
mbed_official 31:42176bc3c368 2991 * @}
mbed_official 31:42176bc3c368 2992 */ /* end of group LLWU_Register_Masks */
mbed_official 31:42176bc3c368 2993
mbed_official 31:42176bc3c368 2994
mbed_official 31:42176bc3c368 2995 /* LLWU - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 2996 /** Peripheral LLWU base address */
mbed_official 31:42176bc3c368 2997 #define LLWU_BASE (0x4007C000u)
mbed_official 31:42176bc3c368 2998 /** Peripheral LLWU base pointer */
mbed_official 31:42176bc3c368 2999 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 31:42176bc3c368 3000 /** Array initializer of LLWU peripheral base pointers */
mbed_official 31:42176bc3c368 3001 #define LLWU_BASES { LLWU }
mbed_official 31:42176bc3c368 3002
mbed_official 31:42176bc3c368 3003 /**
mbed_official 31:42176bc3c368 3004 * @}
mbed_official 31:42176bc3c368 3005 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3006
mbed_official 31:42176bc3c368 3007
mbed_official 31:42176bc3c368 3008 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3009 -- LPTMR Peripheral Access Layer
mbed_official 31:42176bc3c368 3010 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3011
mbed_official 31:42176bc3c368 3012 /**
mbed_official 31:42176bc3c368 3013 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 31:42176bc3c368 3014 * @{
mbed_official 31:42176bc3c368 3015 */
mbed_official 31:42176bc3c368 3016
mbed_official 31:42176bc3c368 3017 /** LPTMR - Register Layout Typedef */
mbed_official 31:42176bc3c368 3018 typedef struct {
mbed_official 31:42176bc3c368 3019 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3020 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 31:42176bc3c368 3021 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 31:42176bc3c368 3022 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 31:42176bc3c368 3023 } LPTMR_Type;
mbed_official 31:42176bc3c368 3024
mbed_official 31:42176bc3c368 3025 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3026 -- LPTMR Register Masks
mbed_official 31:42176bc3c368 3027 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3028
mbed_official 31:42176bc3c368 3029 /**
mbed_official 31:42176bc3c368 3030 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 31:42176bc3c368 3031 * @{
mbed_official 31:42176bc3c368 3032 */
mbed_official 31:42176bc3c368 3033
mbed_official 31:42176bc3c368 3034 /* CSR Bit Fields */
mbed_official 31:42176bc3c368 3035 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 31:42176bc3c368 3036 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 31:42176bc3c368 3037 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 31:42176bc3c368 3038 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 31:42176bc3c368 3039 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 31:42176bc3c368 3040 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 31:42176bc3c368 3041 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 31:42176bc3c368 3042 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 31:42176bc3c368 3043 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 31:42176bc3c368 3044 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 31:42176bc3c368 3045 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 31:42176bc3c368 3046 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 31:42176bc3c368 3047 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 31:42176bc3c368 3048 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 31:42176bc3c368 3049 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 31:42176bc3c368 3050 /* PSR Bit Fields */
mbed_official 31:42176bc3c368 3051 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 31:42176bc3c368 3052 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 31:42176bc3c368 3053 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 31:42176bc3c368 3054 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 31:42176bc3c368 3055 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 31:42176bc3c368 3056 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 31:42176bc3c368 3057 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 31:42176bc3c368 3058 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 31:42176bc3c368 3059 /* CMR Bit Fields */
mbed_official 31:42176bc3c368 3060 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 31:42176bc3c368 3061 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 31:42176bc3c368 3062 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 31:42176bc3c368 3063 /* CNR Bit Fields */
mbed_official 31:42176bc3c368 3064 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 31:42176bc3c368 3065 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 31:42176bc3c368 3066 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 31:42176bc3c368 3067
mbed_official 31:42176bc3c368 3068 /**
mbed_official 31:42176bc3c368 3069 * @}
mbed_official 31:42176bc3c368 3070 */ /* end of group LPTMR_Register_Masks */
mbed_official 31:42176bc3c368 3071
mbed_official 31:42176bc3c368 3072
mbed_official 31:42176bc3c368 3073 /* LPTMR - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3074 /** Peripheral LPTMR0 base address */
mbed_official 31:42176bc3c368 3075 #define LPTMR0_BASE (0x40040000u)
mbed_official 31:42176bc3c368 3076 /** Peripheral LPTMR0 base pointer */
mbed_official 31:42176bc3c368 3077 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 31:42176bc3c368 3078 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 31:42176bc3c368 3079 #define LPTMR_BASES { LPTMR0 }
mbed_official 31:42176bc3c368 3080
mbed_official 31:42176bc3c368 3081 /**
mbed_official 31:42176bc3c368 3082 * @}
mbed_official 31:42176bc3c368 3083 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3084
mbed_official 31:42176bc3c368 3085
mbed_official 31:42176bc3c368 3086 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3087 -- MCG Peripheral Access Layer
mbed_official 31:42176bc3c368 3088 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3089
mbed_official 31:42176bc3c368 3090 /**
mbed_official 31:42176bc3c368 3091 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 31:42176bc3c368 3092 * @{
mbed_official 31:42176bc3c368 3093 */
mbed_official 31:42176bc3c368 3094
mbed_official 31:42176bc3c368 3095 /** MCG - Register Layout Typedef */
mbed_official 31:42176bc3c368 3096 typedef struct {
mbed_official 31:42176bc3c368 3097 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3098 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 31:42176bc3c368 3099 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 31:42176bc3c368 3100 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 31:42176bc3c368 3101 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 31:42176bc3c368 3102 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 31:42176bc3c368 3103 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 31:42176bc3c368 3104 uint8_t RESERVED_0[1];
mbed_official 31:42176bc3c368 3105 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 31:42176bc3c368 3106 uint8_t RESERVED_1[1];
mbed_official 31:42176bc3c368 3107 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 31:42176bc3c368 3108 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 31:42176bc3c368 3109 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 31:42176bc3c368 3110 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 31:42176bc3c368 3111 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
mbed_official 31:42176bc3c368 3112 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
mbed_official 31:42176bc3c368 3113 } MCG_Type;
mbed_official 31:42176bc3c368 3114
mbed_official 31:42176bc3c368 3115 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3116 -- MCG Register Masks
mbed_official 31:42176bc3c368 3117 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3118
mbed_official 31:42176bc3c368 3119 /**
mbed_official 31:42176bc3c368 3120 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 31:42176bc3c368 3121 * @{
mbed_official 31:42176bc3c368 3122 */
mbed_official 31:42176bc3c368 3123
mbed_official 31:42176bc3c368 3124 /* C1 Bit Fields */
mbed_official 31:42176bc3c368 3125 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 31:42176bc3c368 3126 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 31:42176bc3c368 3127 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 31:42176bc3c368 3128 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 31:42176bc3c368 3129 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 31:42176bc3c368 3130 #define MCG_C1_IREFS_SHIFT 2
mbed_official 31:42176bc3c368 3131 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 31:42176bc3c368 3132 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 31:42176bc3c368 3133 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 31:42176bc3c368 3134 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 31:42176bc3c368 3135 #define MCG_C1_CLKS_SHIFT 6
mbed_official 31:42176bc3c368 3136 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 31:42176bc3c368 3137 /* C2 Bit Fields */
mbed_official 31:42176bc3c368 3138 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 31:42176bc3c368 3139 #define MCG_C2_IRCS_SHIFT 0
mbed_official 31:42176bc3c368 3140 #define MCG_C2_LP_MASK 0x2u
mbed_official 31:42176bc3c368 3141 #define MCG_C2_LP_SHIFT 1
mbed_official 31:42176bc3c368 3142 #define MCG_C2_EREFS0_MASK 0x4u
mbed_official 31:42176bc3c368 3143 #define MCG_C2_EREFS0_SHIFT 2
mbed_official 31:42176bc3c368 3144 #define MCG_C2_HGO0_MASK 0x8u
mbed_official 31:42176bc3c368 3145 #define MCG_C2_HGO0_SHIFT 3
mbed_official 31:42176bc3c368 3146 #define MCG_C2_RANGE0_MASK 0x30u
mbed_official 31:42176bc3c368 3147 #define MCG_C2_RANGE0_SHIFT 4
mbed_official 31:42176bc3c368 3148 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mbed_official 44:2ce89a25b635 3149 #define MCG_C2_FCFTRIM_MASK 0x40u
mbed_official 44:2ce89a25b635 3150 #define MCG_C2_FCFTRIM_SHIFT 6
mbed_official 31:42176bc3c368 3151 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 31:42176bc3c368 3152 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 31:42176bc3c368 3153 /* C3 Bit Fields */
mbed_official 31:42176bc3c368 3154 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 31:42176bc3c368 3155 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 31:42176bc3c368 3156 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 31:42176bc3c368 3157 /* C4 Bit Fields */
mbed_official 31:42176bc3c368 3158 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 31:42176bc3c368 3159 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 31:42176bc3c368 3160 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 31:42176bc3c368 3161 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 31:42176bc3c368 3162 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 31:42176bc3c368 3163 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 31:42176bc3c368 3164 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 31:42176bc3c368 3165 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 31:42176bc3c368 3166 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 31:42176bc3c368 3167 #define MCG_C4_DMX32_SHIFT 7
mbed_official 31:42176bc3c368 3168 /* C5 Bit Fields */
mbed_official 31:42176bc3c368 3169 #define MCG_C5_PRDIV0_MASK 0x1Fu
mbed_official 31:42176bc3c368 3170 #define MCG_C5_PRDIV0_SHIFT 0
mbed_official 31:42176bc3c368 3171 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mbed_official 31:42176bc3c368 3172 #define MCG_C5_PLLSTEN0_MASK 0x20u
mbed_official 31:42176bc3c368 3173 #define MCG_C5_PLLSTEN0_SHIFT 5
mbed_official 31:42176bc3c368 3174 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mbed_official 31:42176bc3c368 3175 #define MCG_C5_PLLCLKEN0_SHIFT 6
mbed_official 31:42176bc3c368 3176 /* C6 Bit Fields */
mbed_official 31:42176bc3c368 3177 #define MCG_C6_VDIV0_MASK 0x1Fu
mbed_official 31:42176bc3c368 3178 #define MCG_C6_VDIV0_SHIFT 0
mbed_official 31:42176bc3c368 3179 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mbed_official 31:42176bc3c368 3180 #define MCG_C6_CME0_MASK 0x20u
mbed_official 31:42176bc3c368 3181 #define MCG_C6_CME0_SHIFT 5
mbed_official 31:42176bc3c368 3182 #define MCG_C6_PLLS_MASK 0x40u
mbed_official 31:42176bc3c368 3183 #define MCG_C6_PLLS_SHIFT 6
mbed_official 31:42176bc3c368 3184 #define MCG_C6_LOLIE0_MASK 0x80u
mbed_official 31:42176bc3c368 3185 #define MCG_C6_LOLIE0_SHIFT 7
mbed_official 31:42176bc3c368 3186 /* S Bit Fields */
mbed_official 31:42176bc3c368 3187 #define MCG_S_IRCST_MASK 0x1u
mbed_official 31:42176bc3c368 3188 #define MCG_S_IRCST_SHIFT 0
mbed_official 31:42176bc3c368 3189 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 31:42176bc3c368 3190 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 31:42176bc3c368 3191 #define MCG_S_CLKST_MASK 0xCu
mbed_official 31:42176bc3c368 3192 #define MCG_S_CLKST_SHIFT 2
mbed_official 31:42176bc3c368 3193 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 31:42176bc3c368 3194 #define MCG_S_IREFST_MASK 0x10u
mbed_official 31:42176bc3c368 3195 #define MCG_S_IREFST_SHIFT 4
mbed_official 31:42176bc3c368 3196 #define MCG_S_PLLST_MASK 0x20u
mbed_official 31:42176bc3c368 3197 #define MCG_S_PLLST_SHIFT 5
mbed_official 31:42176bc3c368 3198 #define MCG_S_LOCK0_MASK 0x40u
mbed_official 31:42176bc3c368 3199 #define MCG_S_LOCK0_SHIFT 6
mbed_official 31:42176bc3c368 3200 #define MCG_S_LOLS_MASK 0x80u
mbed_official 31:42176bc3c368 3201 #define MCG_S_LOLS_SHIFT 7
mbed_official 31:42176bc3c368 3202 /* SC Bit Fields */
mbed_official 31:42176bc3c368 3203 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 31:42176bc3c368 3204 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 31:42176bc3c368 3205 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 31:42176bc3c368 3206 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 31:42176bc3c368 3207 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 31:42176bc3c368 3208 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 31:42176bc3c368 3209 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 31:42176bc3c368 3210 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 31:42176bc3c368 3211 #define MCG_SC_ATMF_SHIFT 5
mbed_official 31:42176bc3c368 3212 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 31:42176bc3c368 3213 #define MCG_SC_ATMS_SHIFT 6
mbed_official 31:42176bc3c368 3214 #define MCG_SC_ATME_MASK 0x80u
mbed_official 31:42176bc3c368 3215 #define MCG_SC_ATME_SHIFT 7
mbed_official 31:42176bc3c368 3216 /* ATCVH Bit Fields */
mbed_official 31:42176bc3c368 3217 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 31:42176bc3c368 3218 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 31:42176bc3c368 3219 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 31:42176bc3c368 3220 /* ATCVL Bit Fields */
mbed_official 31:42176bc3c368 3221 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 31:42176bc3c368 3222 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 31:42176bc3c368 3223 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 31:42176bc3c368 3224 /* C8 Bit Fields */
mbed_official 31:42176bc3c368 3225 #define MCG_C8_LOLRE_MASK 0x40u
mbed_official 31:42176bc3c368 3226 #define MCG_C8_LOLRE_SHIFT 6
mbed_official 31:42176bc3c368 3227
mbed_official 31:42176bc3c368 3228 /**
mbed_official 31:42176bc3c368 3229 * @}
mbed_official 31:42176bc3c368 3230 */ /* end of group MCG_Register_Masks */
mbed_official 31:42176bc3c368 3231
mbed_official 31:42176bc3c368 3232
mbed_official 31:42176bc3c368 3233 /* MCG - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3234 /** Peripheral MCG base address */
mbed_official 31:42176bc3c368 3235 #define MCG_BASE (0x40064000u)
mbed_official 31:42176bc3c368 3236 /** Peripheral MCG base pointer */
mbed_official 31:42176bc3c368 3237 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 31:42176bc3c368 3238 /** Array initializer of MCG peripheral base pointers */
mbed_official 31:42176bc3c368 3239 #define MCG_BASES { MCG }
mbed_official 31:42176bc3c368 3240
mbed_official 31:42176bc3c368 3241 /**
mbed_official 31:42176bc3c368 3242 * @}
mbed_official 31:42176bc3c368 3243 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3244
mbed_official 31:42176bc3c368 3245
mbed_official 31:42176bc3c368 3246 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3247 -- MCM Peripheral Access Layer
mbed_official 31:42176bc3c368 3248 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3249
mbed_official 31:42176bc3c368 3250 /**
mbed_official 31:42176bc3c368 3251 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 31:42176bc3c368 3252 * @{
mbed_official 31:42176bc3c368 3253 */
mbed_official 31:42176bc3c368 3254
mbed_official 31:42176bc3c368 3255 /** MCM - Register Layout Typedef */
mbed_official 31:42176bc3c368 3256 typedef struct {
mbed_official 31:42176bc3c368 3257 uint8_t RESERVED_0[8];
mbed_official 31:42176bc3c368 3258 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 31:42176bc3c368 3259 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 31:42176bc3c368 3260 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
mbed_official 31:42176bc3c368 3261 uint8_t RESERVED_1[48];
mbed_official 31:42176bc3c368 3262 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mbed_official 31:42176bc3c368 3263 } MCM_Type;
mbed_official 31:42176bc3c368 3264
mbed_official 31:42176bc3c368 3265 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3266 -- MCM Register Masks
mbed_official 31:42176bc3c368 3267 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3268
mbed_official 31:42176bc3c368 3269 /**
mbed_official 31:42176bc3c368 3270 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 31:42176bc3c368 3271 * @{
mbed_official 31:42176bc3c368 3272 */
mbed_official 31:42176bc3c368 3273
mbed_official 31:42176bc3c368 3274 /* PLASC Bit Fields */
mbed_official 31:42176bc3c368 3275 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 31:42176bc3c368 3276 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 31:42176bc3c368 3277 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 31:42176bc3c368 3278 /* PLAMC Bit Fields */
mbed_official 31:42176bc3c368 3279 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 31:42176bc3c368 3280 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 31:42176bc3c368 3281 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 31:42176bc3c368 3282 /* PLACR Bit Fields */
mbed_official 31:42176bc3c368 3283 #define MCM_PLACR_ARB_MASK 0x200u
mbed_official 31:42176bc3c368 3284 #define MCM_PLACR_ARB_SHIFT 9
mbed_official 31:42176bc3c368 3285 #define MCM_PLACR_CFCC_MASK 0x400u
mbed_official 31:42176bc3c368 3286 #define MCM_PLACR_CFCC_SHIFT 10
mbed_official 31:42176bc3c368 3287 #define MCM_PLACR_DFCDA_MASK 0x800u
mbed_official 31:42176bc3c368 3288 #define MCM_PLACR_DFCDA_SHIFT 11
mbed_official 31:42176bc3c368 3289 #define MCM_PLACR_DFCIC_MASK 0x1000u
mbed_official 31:42176bc3c368 3290 #define MCM_PLACR_DFCIC_SHIFT 12
mbed_official 31:42176bc3c368 3291 #define MCM_PLACR_DFCC_MASK 0x2000u
mbed_official 31:42176bc3c368 3292 #define MCM_PLACR_DFCC_SHIFT 13
mbed_official 31:42176bc3c368 3293 #define MCM_PLACR_EFDS_MASK 0x4000u
mbed_official 31:42176bc3c368 3294 #define MCM_PLACR_EFDS_SHIFT 14
mbed_official 31:42176bc3c368 3295 #define MCM_PLACR_DFCS_MASK 0x8000u
mbed_official 31:42176bc3c368 3296 #define MCM_PLACR_DFCS_SHIFT 15
mbed_official 31:42176bc3c368 3297 #define MCM_PLACR_ESFC_MASK 0x10000u
mbed_official 31:42176bc3c368 3298 #define MCM_PLACR_ESFC_SHIFT 16
mbed_official 31:42176bc3c368 3299 /* CPO Bit Fields */
mbed_official 31:42176bc3c368 3300 #define MCM_CPO_CPOREQ_MASK 0x1u
mbed_official 31:42176bc3c368 3301 #define MCM_CPO_CPOREQ_SHIFT 0
mbed_official 31:42176bc3c368 3302 #define MCM_CPO_CPOACK_MASK 0x2u
mbed_official 31:42176bc3c368 3303 #define MCM_CPO_CPOACK_SHIFT 1
mbed_official 31:42176bc3c368 3304 #define MCM_CPO_CPOWOI_MASK 0x4u
mbed_official 31:42176bc3c368 3305 #define MCM_CPO_CPOWOI_SHIFT 2
mbed_official 31:42176bc3c368 3306
mbed_official 31:42176bc3c368 3307 /**
mbed_official 31:42176bc3c368 3308 * @}
mbed_official 31:42176bc3c368 3309 */ /* end of group MCM_Register_Masks */
mbed_official 31:42176bc3c368 3310
mbed_official 31:42176bc3c368 3311
mbed_official 31:42176bc3c368 3312 /* MCM - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3313 /** Peripheral MCM base address */
mbed_official 31:42176bc3c368 3314 #define MCM_BASE (0xF0003000u)
mbed_official 31:42176bc3c368 3315 /** Peripheral MCM base pointer */
mbed_official 31:42176bc3c368 3316 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 31:42176bc3c368 3317 /** Array initializer of MCM peripheral base pointers */
mbed_official 31:42176bc3c368 3318 #define MCM_BASES { MCM }
mbed_official 31:42176bc3c368 3319
mbed_official 31:42176bc3c368 3320 /**
mbed_official 31:42176bc3c368 3321 * @}
mbed_official 31:42176bc3c368 3322 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3323
mbed_official 31:42176bc3c368 3324
mbed_official 31:42176bc3c368 3325 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3326 -- MTB Peripheral Access Layer
mbed_official 31:42176bc3c368 3327 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3328
mbed_official 31:42176bc3c368 3329 /**
mbed_official 31:42176bc3c368 3330 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
mbed_official 31:42176bc3c368 3331 * @{
mbed_official 31:42176bc3c368 3332 */
mbed_official 31:42176bc3c368 3333
mbed_official 31:42176bc3c368 3334 /** MTB - Register Layout Typedef */
mbed_official 31:42176bc3c368 3335 typedef struct {
mbed_official 31:42176bc3c368 3336 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3337 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
mbed_official 31:42176bc3c368 3338 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
mbed_official 31:42176bc3c368 3339 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
mbed_official 31:42176bc3c368 3340 uint8_t RESERVED_0[3824];
mbed_official 31:42176bc3c368 3341 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
mbed_official 31:42176bc3c368 3342 uint8_t RESERVED_1[156];
mbed_official 31:42176bc3c368 3343 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
mbed_official 31:42176bc3c368 3344 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
mbed_official 31:42176bc3c368 3345 uint8_t RESERVED_2[8];
mbed_official 31:42176bc3c368 3346 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
mbed_official 31:42176bc3c368 3347 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
mbed_official 31:42176bc3c368 3348 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
mbed_official 31:42176bc3c368 3349 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
mbed_official 31:42176bc3c368 3350 uint8_t RESERVED_3[8];
mbed_official 31:42176bc3c368 3351 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 31:42176bc3c368 3352 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 31:42176bc3c368 3353 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 31:42176bc3c368 3354 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 31:42176bc3c368 3355 } MTB_Type;
mbed_official 31:42176bc3c368 3356
mbed_official 31:42176bc3c368 3357 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3358 -- MTB Register Masks
mbed_official 31:42176bc3c368 3359 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3360
mbed_official 31:42176bc3c368 3361 /**
mbed_official 31:42176bc3c368 3362 * @addtogroup MTB_Register_Masks MTB Register Masks
mbed_official 31:42176bc3c368 3363 * @{
mbed_official 31:42176bc3c368 3364 */
mbed_official 31:42176bc3c368 3365
mbed_official 31:42176bc3c368 3366 /* POSITION Bit Fields */
mbed_official 31:42176bc3c368 3367 #define MTB_POSITION_WRAP_MASK 0x4u
mbed_official 31:42176bc3c368 3368 #define MTB_POSITION_WRAP_SHIFT 2
mbed_official 31:42176bc3c368 3369 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
mbed_official 31:42176bc3c368 3370 #define MTB_POSITION_POINTER_SHIFT 3
mbed_official 31:42176bc3c368 3371 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
mbed_official 31:42176bc3c368 3372 /* MASTER Bit Fields */
mbed_official 31:42176bc3c368 3373 #define MTB_MASTER_MASK_MASK 0x1Fu
mbed_official 31:42176bc3c368 3374 #define MTB_MASTER_MASK_SHIFT 0
mbed_official 31:42176bc3c368 3375 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
mbed_official 31:42176bc3c368 3376 #define MTB_MASTER_TSTARTEN_MASK 0x20u
mbed_official 31:42176bc3c368 3377 #define MTB_MASTER_TSTARTEN_SHIFT 5
mbed_official 31:42176bc3c368 3378 #define MTB_MASTER_TSTOPEN_MASK 0x40u
mbed_official 31:42176bc3c368 3379 #define MTB_MASTER_TSTOPEN_SHIFT 6
mbed_official 31:42176bc3c368 3380 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
mbed_official 31:42176bc3c368 3381 #define MTB_MASTER_SFRWPRIV_SHIFT 7
mbed_official 31:42176bc3c368 3382 #define MTB_MASTER_RAMPRIV_MASK 0x100u
mbed_official 31:42176bc3c368 3383 #define MTB_MASTER_RAMPRIV_SHIFT 8
mbed_official 31:42176bc3c368 3384 #define MTB_MASTER_HALTREQ_MASK 0x200u
mbed_official 31:42176bc3c368 3385 #define MTB_MASTER_HALTREQ_SHIFT 9
mbed_official 31:42176bc3c368 3386 #define MTB_MASTER_EN_MASK 0x80000000u
mbed_official 31:42176bc3c368 3387 #define MTB_MASTER_EN_SHIFT 31
mbed_official 31:42176bc3c368 3388 /* FLOW Bit Fields */
mbed_official 31:42176bc3c368 3389 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
mbed_official 31:42176bc3c368 3390 #define MTB_FLOW_AUTOSTOP_SHIFT 0
mbed_official 31:42176bc3c368 3391 #define MTB_FLOW_AUTOHALT_MASK 0x2u
mbed_official 31:42176bc3c368 3392 #define MTB_FLOW_AUTOHALT_SHIFT 1
mbed_official 31:42176bc3c368 3393 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
mbed_official 31:42176bc3c368 3394 #define MTB_FLOW_WATERMARK_SHIFT 3
mbed_official 31:42176bc3c368 3395 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
mbed_official 31:42176bc3c368 3396 /* BASE Bit Fields */
mbed_official 31:42176bc3c368 3397 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3398 #define MTB_BASE_BASEADDR_SHIFT 0
mbed_official 31:42176bc3c368 3399 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
mbed_official 31:42176bc3c368 3400 /* MODECTRL Bit Fields */
mbed_official 31:42176bc3c368 3401 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3402 #define MTB_MODECTRL_MODECTRL_SHIFT 0
mbed_official 31:42176bc3c368 3403 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
mbed_official 31:42176bc3c368 3404 /* TAGSET Bit Fields */
mbed_official 31:42176bc3c368 3405 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3406 #define MTB_TAGSET_TAGSET_SHIFT 0
mbed_official 31:42176bc3c368 3407 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
mbed_official 31:42176bc3c368 3408 /* TAGCLEAR Bit Fields */
mbed_official 31:42176bc3c368 3409 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3410 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
mbed_official 31:42176bc3c368 3411 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
mbed_official 31:42176bc3c368 3412 /* LOCKACCESS Bit Fields */
mbed_official 31:42176bc3c368 3413 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3414 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
mbed_official 31:42176bc3c368 3415 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
mbed_official 31:42176bc3c368 3416 /* LOCKSTAT Bit Fields */
mbed_official 31:42176bc3c368 3417 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3418 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
mbed_official 31:42176bc3c368 3419 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
mbed_official 31:42176bc3c368 3420 /* AUTHSTAT Bit Fields */
mbed_official 31:42176bc3c368 3421 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
mbed_official 31:42176bc3c368 3422 #define MTB_AUTHSTAT_BIT0_SHIFT 0
mbed_official 31:42176bc3c368 3423 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
mbed_official 31:42176bc3c368 3424 #define MTB_AUTHSTAT_BIT1_SHIFT 1
mbed_official 31:42176bc3c368 3425 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
mbed_official 31:42176bc3c368 3426 #define MTB_AUTHSTAT_BIT2_SHIFT 2
mbed_official 31:42176bc3c368 3427 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
mbed_official 31:42176bc3c368 3428 #define MTB_AUTHSTAT_BIT3_SHIFT 3
mbed_official 31:42176bc3c368 3429 /* DEVICEARCH Bit Fields */
mbed_official 31:42176bc3c368 3430 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3431 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
mbed_official 31:42176bc3c368 3432 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
mbed_official 31:42176bc3c368 3433 /* DEVICECFG Bit Fields */
mbed_official 31:42176bc3c368 3434 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3435 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 31:42176bc3c368 3436 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
mbed_official 31:42176bc3c368 3437 /* DEVICETYPID Bit Fields */
mbed_official 31:42176bc3c368 3438 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3439 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 31:42176bc3c368 3440 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 31:42176bc3c368 3441 /* PERIPHID Bit Fields */
mbed_official 31:42176bc3c368 3442 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3443 #define MTB_PERIPHID_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 3444 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
mbed_official 31:42176bc3c368 3445 /* COMPID Bit Fields */
mbed_official 31:42176bc3c368 3446 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3447 #define MTB_COMPID_COMPID_SHIFT 0
mbed_official 31:42176bc3c368 3448 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
mbed_official 31:42176bc3c368 3449
mbed_official 31:42176bc3c368 3450 /**
mbed_official 31:42176bc3c368 3451 * @}
mbed_official 31:42176bc3c368 3452 */ /* end of group MTB_Register_Masks */
mbed_official 31:42176bc3c368 3453
mbed_official 31:42176bc3c368 3454
mbed_official 31:42176bc3c368 3455 /* MTB - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3456 /** Peripheral MTB base address */
mbed_official 31:42176bc3c368 3457 #define MTB_BASE (0xF0000000u)
mbed_official 31:42176bc3c368 3458 /** Peripheral MTB base pointer */
mbed_official 31:42176bc3c368 3459 #define MTB ((MTB_Type *)MTB_BASE)
mbed_official 31:42176bc3c368 3460 /** Array initializer of MTB peripheral base pointers */
mbed_official 31:42176bc3c368 3461 #define MTB_BASES { MTB }
mbed_official 31:42176bc3c368 3462
mbed_official 31:42176bc3c368 3463 /**
mbed_official 31:42176bc3c368 3464 * @}
mbed_official 31:42176bc3c368 3465 */ /* end of group MTB_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3466
mbed_official 31:42176bc3c368 3467
mbed_official 31:42176bc3c368 3468 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3469 -- MTBDWT Peripheral Access Layer
mbed_official 31:42176bc3c368 3470 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3471
mbed_official 31:42176bc3c368 3472 /**
mbed_official 31:42176bc3c368 3473 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
mbed_official 31:42176bc3c368 3474 * @{
mbed_official 31:42176bc3c368 3475 */
mbed_official 31:42176bc3c368 3476
mbed_official 31:42176bc3c368 3477 /** MTBDWT - Register Layout Typedef */
mbed_official 31:42176bc3c368 3478 typedef struct {
mbed_official 31:42176bc3c368 3479 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3480 uint8_t RESERVED_0[28];
mbed_official 31:42176bc3c368 3481 struct { /* offset: 0x20, array step: 0x10 */
mbed_official 31:42176bc3c368 3482 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
mbed_official 31:42176bc3c368 3483 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
mbed_official 31:42176bc3c368 3484 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
mbed_official 31:42176bc3c368 3485 uint8_t RESERVED_0[4];
mbed_official 31:42176bc3c368 3486 } COMPARATOR[2];
mbed_official 31:42176bc3c368 3487 uint8_t RESERVED_1[448];
mbed_official 31:42176bc3c368 3488 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
mbed_official 31:42176bc3c368 3489 uint8_t RESERVED_2[3524];
mbed_official 31:42176bc3c368 3490 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 31:42176bc3c368 3491 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 31:42176bc3c368 3492 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 31:42176bc3c368 3493 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 31:42176bc3c368 3494 } MTBDWT_Type;
mbed_official 31:42176bc3c368 3495
mbed_official 31:42176bc3c368 3496 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3497 -- MTBDWT Register Masks
mbed_official 31:42176bc3c368 3498 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3499
mbed_official 31:42176bc3c368 3500 /**
mbed_official 31:42176bc3c368 3501 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
mbed_official 31:42176bc3c368 3502 * @{
mbed_official 31:42176bc3c368 3503 */
mbed_official 31:42176bc3c368 3504
mbed_official 31:42176bc3c368 3505 /* CTRL Bit Fields */
mbed_official 31:42176bc3c368 3506 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
mbed_official 31:42176bc3c368 3507 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
mbed_official 31:42176bc3c368 3508 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
mbed_official 31:42176bc3c368 3509 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
mbed_official 31:42176bc3c368 3510 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
mbed_official 31:42176bc3c368 3511 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
mbed_official 31:42176bc3c368 3512 /* COMP Bit Fields */
mbed_official 31:42176bc3c368 3513 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3514 #define MTBDWT_COMP_COMP_SHIFT 0
mbed_official 31:42176bc3c368 3515 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
mbed_official 31:42176bc3c368 3516 /* MASK Bit Fields */
mbed_official 31:42176bc3c368 3517 #define MTBDWT_MASK_MASK_MASK 0x1Fu
mbed_official 31:42176bc3c368 3518 #define MTBDWT_MASK_MASK_SHIFT 0
mbed_official 31:42176bc3c368 3519 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
mbed_official 31:42176bc3c368 3520 /* FCT Bit Fields */
mbed_official 31:42176bc3c368 3521 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
mbed_official 31:42176bc3c368 3522 #define MTBDWT_FCT_FUNCTION_SHIFT 0
mbed_official 31:42176bc3c368 3523 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
mbed_official 31:42176bc3c368 3524 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
mbed_official 31:42176bc3c368 3525 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
mbed_official 31:42176bc3c368 3526 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
mbed_official 31:42176bc3c368 3527 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
mbed_official 31:42176bc3c368 3528 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
mbed_official 31:42176bc3c368 3529 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
mbed_official 31:42176bc3c368 3530 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
mbed_official 31:42176bc3c368 3531 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
mbed_official 31:42176bc3c368 3532 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
mbed_official 31:42176bc3c368 3533 #define MTBDWT_FCT_MATCHED_SHIFT 24
mbed_official 31:42176bc3c368 3534 /* TBCTRL Bit Fields */
mbed_official 31:42176bc3c368 3535 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
mbed_official 31:42176bc3c368 3536 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
mbed_official 31:42176bc3c368 3537 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
mbed_official 31:42176bc3c368 3538 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
mbed_official 31:42176bc3c368 3539 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
mbed_official 31:42176bc3c368 3540 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
mbed_official 31:42176bc3c368 3541 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
mbed_official 31:42176bc3c368 3542 /* DEVICECFG Bit Fields */
mbed_official 31:42176bc3c368 3543 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3544 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 31:42176bc3c368 3545 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
mbed_official 31:42176bc3c368 3546 /* DEVICETYPID Bit Fields */
mbed_official 31:42176bc3c368 3547 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3548 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 31:42176bc3c368 3549 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 31:42176bc3c368 3550 /* PERIPHID Bit Fields */
mbed_official 31:42176bc3c368 3551 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3552 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 3553 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
mbed_official 31:42176bc3c368 3554 /* COMPID Bit Fields */
mbed_official 31:42176bc3c368 3555 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3556 #define MTBDWT_COMPID_COMPID_SHIFT 0
mbed_official 31:42176bc3c368 3557 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
mbed_official 31:42176bc3c368 3558
mbed_official 31:42176bc3c368 3559 /**
mbed_official 31:42176bc3c368 3560 * @}
mbed_official 31:42176bc3c368 3561 */ /* end of group MTBDWT_Register_Masks */
mbed_official 31:42176bc3c368 3562
mbed_official 31:42176bc3c368 3563
mbed_official 31:42176bc3c368 3564 /* MTBDWT - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3565 /** Peripheral MTBDWT base address */
mbed_official 31:42176bc3c368 3566 #define MTBDWT_BASE (0xF0001000u)
mbed_official 31:42176bc3c368 3567 /** Peripheral MTBDWT base pointer */
mbed_official 31:42176bc3c368 3568 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
mbed_official 31:42176bc3c368 3569 /** Array initializer of MTBDWT peripheral base pointers */
mbed_official 31:42176bc3c368 3570 #define MTBDWT_BASES { MTBDWT }
mbed_official 31:42176bc3c368 3571
mbed_official 31:42176bc3c368 3572 /**
mbed_official 31:42176bc3c368 3573 * @}
mbed_official 31:42176bc3c368 3574 */ /* end of group MTBDWT_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3575
mbed_official 31:42176bc3c368 3576
mbed_official 31:42176bc3c368 3577 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3578 -- NV Peripheral Access Layer
mbed_official 31:42176bc3c368 3579 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3580
mbed_official 31:42176bc3c368 3581 /**
mbed_official 31:42176bc3c368 3582 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 31:42176bc3c368 3583 * @{
mbed_official 31:42176bc3c368 3584 */
mbed_official 31:42176bc3c368 3585
mbed_official 31:42176bc3c368 3586 /** NV - Register Layout Typedef */
mbed_official 31:42176bc3c368 3587 typedef struct {
mbed_official 31:42176bc3c368 3588 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 31:42176bc3c368 3589 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 31:42176bc3c368 3590 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 31:42176bc3c368 3591 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 31:42176bc3c368 3592 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 31:42176bc3c368 3593 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 31:42176bc3c368 3594 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 31:42176bc3c368 3595 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 31:42176bc3c368 3596 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 31:42176bc3c368 3597 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 31:42176bc3c368 3598 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 31:42176bc3c368 3599 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 31:42176bc3c368 3600 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 31:42176bc3c368 3601 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 31:42176bc3c368 3602 } NV_Type;
mbed_official 31:42176bc3c368 3603
mbed_official 31:42176bc3c368 3604 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3605 -- NV Register Masks
mbed_official 31:42176bc3c368 3606 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3607
mbed_official 31:42176bc3c368 3608 /**
mbed_official 31:42176bc3c368 3609 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 31:42176bc3c368 3610 * @{
mbed_official 31:42176bc3c368 3611 */
mbed_official 31:42176bc3c368 3612
mbed_official 31:42176bc3c368 3613 /* BACKKEY3 Bit Fields */
mbed_official 31:42176bc3c368 3614 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3615 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3616 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 31:42176bc3c368 3617 /* BACKKEY2 Bit Fields */
mbed_official 31:42176bc3c368 3618 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3619 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3620 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 31:42176bc3c368 3621 /* BACKKEY1 Bit Fields */
mbed_official 31:42176bc3c368 3622 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3623 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3624 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 31:42176bc3c368 3625 /* BACKKEY0 Bit Fields */
mbed_official 31:42176bc3c368 3626 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3627 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3628 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 31:42176bc3c368 3629 /* BACKKEY7 Bit Fields */
mbed_official 31:42176bc3c368 3630 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3631 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3632 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 31:42176bc3c368 3633 /* BACKKEY6 Bit Fields */
mbed_official 31:42176bc3c368 3634 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3635 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3636 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 31:42176bc3c368 3637 /* BACKKEY5 Bit Fields */
mbed_official 31:42176bc3c368 3638 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3639 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3640 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 31:42176bc3c368 3641 /* BACKKEY4 Bit Fields */
mbed_official 31:42176bc3c368 3642 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 31:42176bc3c368 3643 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 31:42176bc3c368 3644 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 31:42176bc3c368 3645 /* FPROT3 Bit Fields */
mbed_official 31:42176bc3c368 3646 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 3647 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 31:42176bc3c368 3648 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 31:42176bc3c368 3649 /* FPROT2 Bit Fields */
mbed_official 31:42176bc3c368 3650 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 3651 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 31:42176bc3c368 3652 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 31:42176bc3c368 3653 /* FPROT1 Bit Fields */
mbed_official 31:42176bc3c368 3654 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 3655 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 31:42176bc3c368 3656 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 31:42176bc3c368 3657 /* FPROT0 Bit Fields */
mbed_official 31:42176bc3c368 3658 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 31:42176bc3c368 3659 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 31:42176bc3c368 3660 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 31:42176bc3c368 3661 /* FSEC Bit Fields */
mbed_official 31:42176bc3c368 3662 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 31:42176bc3c368 3663 #define NV_FSEC_SEC_SHIFT 0
mbed_official 31:42176bc3c368 3664 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 31:42176bc3c368 3665 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 31:42176bc3c368 3666 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 31:42176bc3c368 3667 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 31:42176bc3c368 3668 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 31:42176bc3c368 3669 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 31:42176bc3c368 3670 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 31:42176bc3c368 3671 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 31:42176bc3c368 3672 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 31:42176bc3c368 3673 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 31:42176bc3c368 3674 /* FOPT Bit Fields */
mbed_official 31:42176bc3c368 3675 #define NV_FOPT_LPBOOT0_MASK 0x1u
mbed_official 31:42176bc3c368 3676 #define NV_FOPT_LPBOOT0_SHIFT 0
mbed_official 31:42176bc3c368 3677 #define NV_FOPT_NMI_DIS_MASK 0x4u
mbed_official 31:42176bc3c368 3678 #define NV_FOPT_NMI_DIS_SHIFT 2
mbed_official 31:42176bc3c368 3679 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
mbed_official 31:42176bc3c368 3680 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
mbed_official 31:42176bc3c368 3681 #define NV_FOPT_LPBOOT1_MASK 0x10u
mbed_official 31:42176bc3c368 3682 #define NV_FOPT_LPBOOT1_SHIFT 4
mbed_official 31:42176bc3c368 3683 #define NV_FOPT_FAST_INIT_MASK 0x20u
mbed_official 31:42176bc3c368 3684 #define NV_FOPT_FAST_INIT_SHIFT 5
mbed_official 31:42176bc3c368 3685
mbed_official 31:42176bc3c368 3686 /**
mbed_official 31:42176bc3c368 3687 * @}
mbed_official 31:42176bc3c368 3688 */ /* end of group NV_Register_Masks */
mbed_official 31:42176bc3c368 3689
mbed_official 31:42176bc3c368 3690
mbed_official 31:42176bc3c368 3691 /* NV - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3692 /** Peripheral FTFA_FlashConfig base address */
mbed_official 31:42176bc3c368 3693 #define FTFA_FlashConfig_BASE (0x400u)
mbed_official 31:42176bc3c368 3694 /** Peripheral FTFA_FlashConfig base pointer */
mbed_official 31:42176bc3c368 3695 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mbed_official 31:42176bc3c368 3696 /** Array initializer of NV peripheral base pointers */
mbed_official 31:42176bc3c368 3697 #define NV_BASES { FTFA_FlashConfig }
mbed_official 31:42176bc3c368 3698
mbed_official 31:42176bc3c368 3699 /**
mbed_official 31:42176bc3c368 3700 * @}
mbed_official 31:42176bc3c368 3701 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3702
mbed_official 31:42176bc3c368 3703
mbed_official 31:42176bc3c368 3704 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3705 -- OSC Peripheral Access Layer
mbed_official 31:42176bc3c368 3706 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3707
mbed_official 31:42176bc3c368 3708 /**
mbed_official 31:42176bc3c368 3709 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 31:42176bc3c368 3710 * @{
mbed_official 31:42176bc3c368 3711 */
mbed_official 31:42176bc3c368 3712
mbed_official 31:42176bc3c368 3713 /** OSC - Register Layout Typedef */
mbed_official 31:42176bc3c368 3714 typedef struct {
mbed_official 31:42176bc3c368 3715 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3716 } OSC_Type;
mbed_official 31:42176bc3c368 3717
mbed_official 31:42176bc3c368 3718 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3719 -- OSC Register Masks
mbed_official 31:42176bc3c368 3720 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3721
mbed_official 31:42176bc3c368 3722 /**
mbed_official 31:42176bc3c368 3723 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 31:42176bc3c368 3724 * @{
mbed_official 31:42176bc3c368 3725 */
mbed_official 31:42176bc3c368 3726
mbed_official 31:42176bc3c368 3727 /* CR Bit Fields */
mbed_official 31:42176bc3c368 3728 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 31:42176bc3c368 3729 #define OSC_CR_SC16P_SHIFT 0
mbed_official 31:42176bc3c368 3730 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 31:42176bc3c368 3731 #define OSC_CR_SC8P_SHIFT 1
mbed_official 31:42176bc3c368 3732 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 31:42176bc3c368 3733 #define OSC_CR_SC4P_SHIFT 2
mbed_official 31:42176bc3c368 3734 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 31:42176bc3c368 3735 #define OSC_CR_SC2P_SHIFT 3
mbed_official 31:42176bc3c368 3736 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 31:42176bc3c368 3737 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 31:42176bc3c368 3738 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 31:42176bc3c368 3739 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 31:42176bc3c368 3740
mbed_official 31:42176bc3c368 3741 /**
mbed_official 31:42176bc3c368 3742 * @}
mbed_official 31:42176bc3c368 3743 */ /* end of group OSC_Register_Masks */
mbed_official 31:42176bc3c368 3744
mbed_official 31:42176bc3c368 3745
mbed_official 31:42176bc3c368 3746 /* OSC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3747 /** Peripheral OSC0 base address */
mbed_official 31:42176bc3c368 3748 #define OSC0_BASE (0x40065000u)
mbed_official 31:42176bc3c368 3749 /** Peripheral OSC0 base pointer */
mbed_official 31:42176bc3c368 3750 #define OSC0 ((OSC_Type *)OSC0_BASE)
mbed_official 31:42176bc3c368 3751 /** Array initializer of OSC peripheral base pointers */
mbed_official 31:42176bc3c368 3752 #define OSC_BASES { OSC0 }
mbed_official 31:42176bc3c368 3753
mbed_official 31:42176bc3c368 3754 /**
mbed_official 31:42176bc3c368 3755 * @}
mbed_official 31:42176bc3c368 3756 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3757
mbed_official 31:42176bc3c368 3758
mbed_official 31:42176bc3c368 3759 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3760 -- PIT Peripheral Access Layer
mbed_official 31:42176bc3c368 3761 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3762
mbed_official 31:42176bc3c368 3763 /**
mbed_official 31:42176bc3c368 3764 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 31:42176bc3c368 3765 * @{
mbed_official 31:42176bc3c368 3766 */
mbed_official 31:42176bc3c368 3767
mbed_official 31:42176bc3c368 3768 /** PIT - Register Layout Typedef */
mbed_official 31:42176bc3c368 3769 typedef struct {
mbed_official 31:42176bc3c368 3770 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 31:42176bc3c368 3771 uint8_t RESERVED_0[220];
mbed_official 31:42176bc3c368 3772 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
mbed_official 31:42176bc3c368 3773 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
mbed_official 31:42176bc3c368 3774 uint8_t RESERVED_1[24];
mbed_official 31:42176bc3c368 3775 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 31:42176bc3c368 3776 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 31:42176bc3c368 3777 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 31:42176bc3c368 3778 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 31:42176bc3c368 3779 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 31:42176bc3c368 3780 } CHANNEL[2];
mbed_official 31:42176bc3c368 3781 } PIT_Type;
mbed_official 31:42176bc3c368 3782
mbed_official 31:42176bc3c368 3783 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3784 -- PIT Register Masks
mbed_official 31:42176bc3c368 3785 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3786
mbed_official 31:42176bc3c368 3787 /**
mbed_official 31:42176bc3c368 3788 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 31:42176bc3c368 3789 * @{
mbed_official 31:42176bc3c368 3790 */
mbed_official 31:42176bc3c368 3791
mbed_official 31:42176bc3c368 3792 /* MCR Bit Fields */
mbed_official 31:42176bc3c368 3793 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 31:42176bc3c368 3794 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 31:42176bc3c368 3795 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 31:42176bc3c368 3796 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 31:42176bc3c368 3797 /* LTMR64H Bit Fields */
mbed_official 31:42176bc3c368 3798 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3799 #define PIT_LTMR64H_LTH_SHIFT 0
mbed_official 31:42176bc3c368 3800 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
mbed_official 31:42176bc3c368 3801 /* LTMR64L Bit Fields */
mbed_official 31:42176bc3c368 3802 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3803 #define PIT_LTMR64L_LTL_SHIFT 0
mbed_official 31:42176bc3c368 3804 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
mbed_official 31:42176bc3c368 3805 /* LDVAL Bit Fields */
mbed_official 31:42176bc3c368 3806 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3807 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 31:42176bc3c368 3808 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 31:42176bc3c368 3809 /* CVAL Bit Fields */
mbed_official 31:42176bc3c368 3810 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3811 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 31:42176bc3c368 3812 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 31:42176bc3c368 3813 /* TCTRL Bit Fields */
mbed_official 31:42176bc3c368 3814 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 31:42176bc3c368 3815 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 31:42176bc3c368 3816 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 31:42176bc3c368 3817 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 31:42176bc3c368 3818 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 31:42176bc3c368 3819 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 31:42176bc3c368 3820 /* TFLG Bit Fields */
mbed_official 31:42176bc3c368 3821 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 31:42176bc3c368 3822 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 31:42176bc3c368 3823
mbed_official 31:42176bc3c368 3824 /**
mbed_official 31:42176bc3c368 3825 * @}
mbed_official 31:42176bc3c368 3826 */ /* end of group PIT_Register_Masks */
mbed_official 31:42176bc3c368 3827
mbed_official 31:42176bc3c368 3828
mbed_official 31:42176bc3c368 3829 /* PIT - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3830 /** Peripheral PIT base address */
mbed_official 31:42176bc3c368 3831 #define PIT_BASE (0x40037000u)
mbed_official 31:42176bc3c368 3832 /** Peripheral PIT base pointer */
mbed_official 31:42176bc3c368 3833 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 31:42176bc3c368 3834 /** Array initializer of PIT peripheral base pointers */
mbed_official 31:42176bc3c368 3835 #define PIT_BASES { PIT }
mbed_official 31:42176bc3c368 3836
mbed_official 31:42176bc3c368 3837 /**
mbed_official 31:42176bc3c368 3838 * @}
mbed_official 31:42176bc3c368 3839 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3840
mbed_official 31:42176bc3c368 3841
mbed_official 31:42176bc3c368 3842 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3843 -- PMC Peripheral Access Layer
mbed_official 31:42176bc3c368 3844 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3845
mbed_official 31:42176bc3c368 3846 /**
mbed_official 31:42176bc3c368 3847 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 31:42176bc3c368 3848 * @{
mbed_official 31:42176bc3c368 3849 */
mbed_official 31:42176bc3c368 3850
mbed_official 31:42176bc3c368 3851 /** PMC - Register Layout Typedef */
mbed_official 31:42176bc3c368 3852 typedef struct {
mbed_official 31:42176bc3c368 3853 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 31:42176bc3c368 3854 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 31:42176bc3c368 3855 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 31:42176bc3c368 3856 } PMC_Type;
mbed_official 31:42176bc3c368 3857
mbed_official 31:42176bc3c368 3858 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3859 -- PMC Register Masks
mbed_official 31:42176bc3c368 3860 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3861
mbed_official 31:42176bc3c368 3862 /**
mbed_official 31:42176bc3c368 3863 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 31:42176bc3c368 3864 * @{
mbed_official 31:42176bc3c368 3865 */
mbed_official 31:42176bc3c368 3866
mbed_official 31:42176bc3c368 3867 /* LVDSC1 Bit Fields */
mbed_official 31:42176bc3c368 3868 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 31:42176bc3c368 3869 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 31:42176bc3c368 3870 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 31:42176bc3c368 3871 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 31:42176bc3c368 3872 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 31:42176bc3c368 3873 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 31:42176bc3c368 3874 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 31:42176bc3c368 3875 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 31:42176bc3c368 3876 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 31:42176bc3c368 3877 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 31:42176bc3c368 3878 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 31:42176bc3c368 3879 /* LVDSC2 Bit Fields */
mbed_official 31:42176bc3c368 3880 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 31:42176bc3c368 3881 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 31:42176bc3c368 3882 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 31:42176bc3c368 3883 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 31:42176bc3c368 3884 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 31:42176bc3c368 3885 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 31:42176bc3c368 3886 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 31:42176bc3c368 3887 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 31:42176bc3c368 3888 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 31:42176bc3c368 3889 /* REGSC Bit Fields */
mbed_official 31:42176bc3c368 3890 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 31:42176bc3c368 3891 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 31:42176bc3c368 3892 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 31:42176bc3c368 3893 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 31:42176bc3c368 3894 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 31:42176bc3c368 3895 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 31:42176bc3c368 3896 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 31:42176bc3c368 3897 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 31:42176bc3c368 3898
mbed_official 31:42176bc3c368 3899 /**
mbed_official 31:42176bc3c368 3900 * @}
mbed_official 31:42176bc3c368 3901 */ /* end of group PMC_Register_Masks */
mbed_official 31:42176bc3c368 3902
mbed_official 31:42176bc3c368 3903
mbed_official 31:42176bc3c368 3904 /* PMC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3905 /** Peripheral PMC base address */
mbed_official 31:42176bc3c368 3906 #define PMC_BASE (0x4007D000u)
mbed_official 31:42176bc3c368 3907 /** Peripheral PMC base pointer */
mbed_official 31:42176bc3c368 3908 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 31:42176bc3c368 3909 /** Array initializer of PMC peripheral base pointers */
mbed_official 31:42176bc3c368 3910 #define PMC_BASES { PMC }
mbed_official 31:42176bc3c368 3911
mbed_official 31:42176bc3c368 3912 /**
mbed_official 31:42176bc3c368 3913 * @}
mbed_official 31:42176bc3c368 3914 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 3915
mbed_official 31:42176bc3c368 3916
mbed_official 31:42176bc3c368 3917 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3918 -- PORT Peripheral Access Layer
mbed_official 31:42176bc3c368 3919 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3920
mbed_official 31:42176bc3c368 3921 /**
mbed_official 31:42176bc3c368 3922 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 31:42176bc3c368 3923 * @{
mbed_official 31:42176bc3c368 3924 */
mbed_official 31:42176bc3c368 3925
mbed_official 31:42176bc3c368 3926 /** PORT - Register Layout Typedef */
mbed_official 31:42176bc3c368 3927 typedef struct {
mbed_official 31:42176bc3c368 3928 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 31:42176bc3c368 3929 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 31:42176bc3c368 3930 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 31:42176bc3c368 3931 uint8_t RESERVED_0[24];
mbed_official 31:42176bc3c368 3932 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 31:42176bc3c368 3933 } PORT_Type;
mbed_official 31:42176bc3c368 3934
mbed_official 31:42176bc3c368 3935 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 3936 -- PORT Register Masks
mbed_official 31:42176bc3c368 3937 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 3938
mbed_official 31:42176bc3c368 3939 /**
mbed_official 31:42176bc3c368 3940 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 31:42176bc3c368 3941 * @{
mbed_official 31:42176bc3c368 3942 */
mbed_official 31:42176bc3c368 3943
mbed_official 31:42176bc3c368 3944 /* PCR Bit Fields */
mbed_official 31:42176bc3c368 3945 #define PORT_PCR_PS_MASK 0x1u
mbed_official 31:42176bc3c368 3946 #define PORT_PCR_PS_SHIFT 0
mbed_official 31:42176bc3c368 3947 #define PORT_PCR_PE_MASK 0x2u
mbed_official 31:42176bc3c368 3948 #define PORT_PCR_PE_SHIFT 1
mbed_official 31:42176bc3c368 3949 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 31:42176bc3c368 3950 #define PORT_PCR_SRE_SHIFT 2
mbed_official 31:42176bc3c368 3951 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 31:42176bc3c368 3952 #define PORT_PCR_PFE_SHIFT 4
mbed_official 31:42176bc3c368 3953 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 31:42176bc3c368 3954 #define PORT_PCR_DSE_SHIFT 6
mbed_official 31:42176bc3c368 3955 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 31:42176bc3c368 3956 #define PORT_PCR_MUX_SHIFT 8
mbed_official 31:42176bc3c368 3957 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 31:42176bc3c368 3958 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 31:42176bc3c368 3959 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 31:42176bc3c368 3960 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 31:42176bc3c368 3961 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 31:42176bc3c368 3962 #define PORT_PCR_ISF_SHIFT 24
mbed_official 31:42176bc3c368 3963 /* GPCLR Bit Fields */
mbed_official 31:42176bc3c368 3964 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 31:42176bc3c368 3965 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 31:42176bc3c368 3966 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 31:42176bc3c368 3967 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 31:42176bc3c368 3968 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 31:42176bc3c368 3969 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 31:42176bc3c368 3970 /* GPCHR Bit Fields */
mbed_official 31:42176bc3c368 3971 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 31:42176bc3c368 3972 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 31:42176bc3c368 3973 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 31:42176bc3c368 3974 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 31:42176bc3c368 3975 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 31:42176bc3c368 3976 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 31:42176bc3c368 3977 /* ISFR Bit Fields */
mbed_official 31:42176bc3c368 3978 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 3979 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 31:42176bc3c368 3980 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 31:42176bc3c368 3981
mbed_official 31:42176bc3c368 3982 /**
mbed_official 31:42176bc3c368 3983 * @}
mbed_official 31:42176bc3c368 3984 */ /* end of group PORT_Register_Masks */
mbed_official 31:42176bc3c368 3985
mbed_official 31:42176bc3c368 3986
mbed_official 31:42176bc3c368 3987 /* PORT - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 3988 /** Peripheral PORTA base address */
mbed_official 31:42176bc3c368 3989 #define PORTA_BASE (0x40049000u)
mbed_official 31:42176bc3c368 3990 /** Peripheral PORTA base pointer */
mbed_official 31:42176bc3c368 3991 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 31:42176bc3c368 3992 /** Peripheral PORTB base address */
mbed_official 31:42176bc3c368 3993 #define PORTB_BASE (0x4004A000u)
mbed_official 31:42176bc3c368 3994 /** Peripheral PORTB base pointer */
mbed_official 31:42176bc3c368 3995 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 31:42176bc3c368 3996 /** Peripheral PORTC base address */
mbed_official 31:42176bc3c368 3997 #define PORTC_BASE (0x4004B000u)
mbed_official 31:42176bc3c368 3998 /** Peripheral PORTC base pointer */
mbed_official 31:42176bc3c368 3999 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 31:42176bc3c368 4000 /** Peripheral PORTD base address */
mbed_official 31:42176bc3c368 4001 #define PORTD_BASE (0x4004C000u)
mbed_official 31:42176bc3c368 4002 /** Peripheral PORTD base pointer */
mbed_official 31:42176bc3c368 4003 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 31:42176bc3c368 4004 /** Peripheral PORTE base address */
mbed_official 31:42176bc3c368 4005 #define PORTE_BASE (0x4004D000u)
mbed_official 31:42176bc3c368 4006 /** Peripheral PORTE base pointer */
mbed_official 31:42176bc3c368 4007 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 31:42176bc3c368 4008 /** Array initializer of PORT peripheral base pointers */
mbed_official 31:42176bc3c368 4009 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 31:42176bc3c368 4010
mbed_official 31:42176bc3c368 4011 /**
mbed_official 31:42176bc3c368 4012 * @}
mbed_official 31:42176bc3c368 4013 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4014
mbed_official 31:42176bc3c368 4015
mbed_official 31:42176bc3c368 4016 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4017 -- RCM Peripheral Access Layer
mbed_official 31:42176bc3c368 4018 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4019
mbed_official 31:42176bc3c368 4020 /**
mbed_official 31:42176bc3c368 4021 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 31:42176bc3c368 4022 * @{
mbed_official 31:42176bc3c368 4023 */
mbed_official 31:42176bc3c368 4024
mbed_official 31:42176bc3c368 4025 /** RCM - Register Layout Typedef */
mbed_official 31:42176bc3c368 4026 typedef struct {
mbed_official 31:42176bc3c368 4027 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 31:42176bc3c368 4028 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 31:42176bc3c368 4029 uint8_t RESERVED_0[2];
mbed_official 31:42176bc3c368 4030 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 31:42176bc3c368 4031 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 31:42176bc3c368 4032 } RCM_Type;
mbed_official 31:42176bc3c368 4033
mbed_official 31:42176bc3c368 4034 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4035 -- RCM Register Masks
mbed_official 31:42176bc3c368 4036 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4037
mbed_official 31:42176bc3c368 4038 /**
mbed_official 31:42176bc3c368 4039 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 31:42176bc3c368 4040 * @{
mbed_official 31:42176bc3c368 4041 */
mbed_official 31:42176bc3c368 4042
mbed_official 31:42176bc3c368 4043 /* SRS0 Bit Fields */
mbed_official 31:42176bc3c368 4044 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 31:42176bc3c368 4045 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 31:42176bc3c368 4046 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 31:42176bc3c368 4047 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 31:42176bc3c368 4048 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 31:42176bc3c368 4049 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 31:42176bc3c368 4050 #define RCM_SRS0_LOL_MASK 0x8u
mbed_official 31:42176bc3c368 4051 #define RCM_SRS0_LOL_SHIFT 3
mbed_official 31:42176bc3c368 4052 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 31:42176bc3c368 4053 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 31:42176bc3c368 4054 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 31:42176bc3c368 4055 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 31:42176bc3c368 4056 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 31:42176bc3c368 4057 #define RCM_SRS0_POR_SHIFT 7
mbed_official 31:42176bc3c368 4058 /* SRS1 Bit Fields */
mbed_official 31:42176bc3c368 4059 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 31:42176bc3c368 4060 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 31:42176bc3c368 4061 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 31:42176bc3c368 4062 #define RCM_SRS1_SW_SHIFT 2
mbed_official 31:42176bc3c368 4063 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 31:42176bc3c368 4064 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 31:42176bc3c368 4065 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 31:42176bc3c368 4066 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 31:42176bc3c368 4067 /* RPFC Bit Fields */
mbed_official 31:42176bc3c368 4068 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 31:42176bc3c368 4069 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 31:42176bc3c368 4070 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 31:42176bc3c368 4071 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 31:42176bc3c368 4072 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 31:42176bc3c368 4073 /* RPFW Bit Fields */
mbed_official 31:42176bc3c368 4074 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 31:42176bc3c368 4075 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 31:42176bc3c368 4076 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 31:42176bc3c368 4077
mbed_official 31:42176bc3c368 4078 /**
mbed_official 31:42176bc3c368 4079 * @}
mbed_official 31:42176bc3c368 4080 */ /* end of group RCM_Register_Masks */
mbed_official 31:42176bc3c368 4081
mbed_official 31:42176bc3c368 4082
mbed_official 31:42176bc3c368 4083 /* RCM - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4084 /** Peripheral RCM base address */
mbed_official 31:42176bc3c368 4085 #define RCM_BASE (0x4007F000u)
mbed_official 31:42176bc3c368 4086 /** Peripheral RCM base pointer */
mbed_official 31:42176bc3c368 4087 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 31:42176bc3c368 4088 /** Array initializer of RCM peripheral base pointers */
mbed_official 31:42176bc3c368 4089 #define RCM_BASES { RCM }
mbed_official 31:42176bc3c368 4090
mbed_official 31:42176bc3c368 4091 /**
mbed_official 31:42176bc3c368 4092 * @}
mbed_official 31:42176bc3c368 4093 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4094
mbed_official 31:42176bc3c368 4095
mbed_official 31:42176bc3c368 4096 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4097 -- ROM Peripheral Access Layer
mbed_official 31:42176bc3c368 4098 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4099
mbed_official 31:42176bc3c368 4100 /**
mbed_official 31:42176bc3c368 4101 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
mbed_official 31:42176bc3c368 4102 * @{
mbed_official 31:42176bc3c368 4103 */
mbed_official 31:42176bc3c368 4104
mbed_official 31:42176bc3c368 4105 /** ROM - Register Layout Typedef */
mbed_official 31:42176bc3c368 4106 typedef struct {
mbed_official 31:42176bc3c368 4107 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
mbed_official 31:42176bc3c368 4108 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
mbed_official 31:42176bc3c368 4109 uint8_t RESERVED_0[4028];
mbed_official 31:42176bc3c368 4110 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
mbed_official 31:42176bc3c368 4111 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
mbed_official 31:42176bc3c368 4112 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
mbed_official 31:42176bc3c368 4113 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
mbed_official 31:42176bc3c368 4114 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
mbed_official 31:42176bc3c368 4115 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
mbed_official 31:42176bc3c368 4116 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
mbed_official 31:42176bc3c368 4117 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
mbed_official 31:42176bc3c368 4118 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
mbed_official 31:42176bc3c368 4119 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 31:42176bc3c368 4120 } ROM_Type;
mbed_official 31:42176bc3c368 4121
mbed_official 31:42176bc3c368 4122 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4123 -- ROM Register Masks
mbed_official 31:42176bc3c368 4124 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4125
mbed_official 31:42176bc3c368 4126 /**
mbed_official 31:42176bc3c368 4127 * @addtogroup ROM_Register_Masks ROM Register Masks
mbed_official 31:42176bc3c368 4128 * @{
mbed_official 31:42176bc3c368 4129 */
mbed_official 31:42176bc3c368 4130
mbed_official 31:42176bc3c368 4131 /* ENTRY Bit Fields */
mbed_official 31:42176bc3c368 4132 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4133 #define ROM_ENTRY_ENTRY_SHIFT 0
mbed_official 31:42176bc3c368 4134 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
mbed_official 31:42176bc3c368 4135 /* TABLEMARK Bit Fields */
mbed_official 31:42176bc3c368 4136 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4137 #define ROM_TABLEMARK_MARK_SHIFT 0
mbed_official 31:42176bc3c368 4138 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
mbed_official 31:42176bc3c368 4139 /* SYSACCESS Bit Fields */
mbed_official 31:42176bc3c368 4140 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4141 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
mbed_official 31:42176bc3c368 4142 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
mbed_official 31:42176bc3c368 4143 /* PERIPHID4 Bit Fields */
mbed_official 31:42176bc3c368 4144 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4145 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4146 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4147 /* PERIPHID5 Bit Fields */
mbed_official 31:42176bc3c368 4148 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4149 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4150 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4151 /* PERIPHID6 Bit Fields */
mbed_official 31:42176bc3c368 4152 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4153 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4154 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4155 /* PERIPHID7 Bit Fields */
mbed_official 31:42176bc3c368 4156 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4157 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4158 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4159 /* PERIPHID0 Bit Fields */
mbed_official 31:42176bc3c368 4160 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4161 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4162 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4163 /* PERIPHID1 Bit Fields */
mbed_official 31:42176bc3c368 4164 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4165 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4166 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4167 /* PERIPHID2 Bit Fields */
mbed_official 31:42176bc3c368 4168 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4169 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4170 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4171 /* PERIPHID3 Bit Fields */
mbed_official 31:42176bc3c368 4172 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4173 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
mbed_official 31:42176bc3c368 4174 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
mbed_official 31:42176bc3c368 4175 /* COMPID Bit Fields */
mbed_official 31:42176bc3c368 4176 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4177 #define ROM_COMPID_COMPID_SHIFT 0
mbed_official 31:42176bc3c368 4178 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
mbed_official 31:42176bc3c368 4179
mbed_official 31:42176bc3c368 4180 /**
mbed_official 31:42176bc3c368 4181 * @}
mbed_official 31:42176bc3c368 4182 */ /* end of group ROM_Register_Masks */
mbed_official 31:42176bc3c368 4183
mbed_official 31:42176bc3c368 4184
mbed_official 31:42176bc3c368 4185 /* ROM - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4186 /** Peripheral ROM base address */
mbed_official 31:42176bc3c368 4187 #define ROM_BASE (0xF0002000u)
mbed_official 31:42176bc3c368 4188 /** Peripheral ROM base pointer */
mbed_official 31:42176bc3c368 4189 #define ROM ((ROM_Type *)ROM_BASE)
mbed_official 31:42176bc3c368 4190 /** Array initializer of ROM peripheral base pointers */
mbed_official 31:42176bc3c368 4191 #define ROM_BASES { ROM }
mbed_official 31:42176bc3c368 4192
mbed_official 31:42176bc3c368 4193 /**
mbed_official 31:42176bc3c368 4194 * @}
mbed_official 31:42176bc3c368 4195 */ /* end of group ROM_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4196
mbed_official 31:42176bc3c368 4197
mbed_official 31:42176bc3c368 4198 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4199 -- RTC Peripheral Access Layer
mbed_official 31:42176bc3c368 4200 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4201
mbed_official 31:42176bc3c368 4202 /**
mbed_official 31:42176bc3c368 4203 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 31:42176bc3c368 4204 * @{
mbed_official 31:42176bc3c368 4205 */
mbed_official 31:42176bc3c368 4206
mbed_official 31:42176bc3c368 4207 /** RTC - Register Layout Typedef */
mbed_official 31:42176bc3c368 4208 typedef struct {
mbed_official 31:42176bc3c368 4209 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 31:42176bc3c368 4210 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 31:42176bc3c368 4211 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 31:42176bc3c368 4212 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 31:42176bc3c368 4213 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 31:42176bc3c368 4214 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 31:42176bc3c368 4215 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 31:42176bc3c368 4216 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 31:42176bc3c368 4217 } RTC_Type;
mbed_official 31:42176bc3c368 4218
mbed_official 31:42176bc3c368 4219 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4220 -- RTC Register Masks
mbed_official 31:42176bc3c368 4221 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4222
mbed_official 31:42176bc3c368 4223 /**
mbed_official 31:42176bc3c368 4224 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 31:42176bc3c368 4225 * @{
mbed_official 31:42176bc3c368 4226 */
mbed_official 31:42176bc3c368 4227
mbed_official 31:42176bc3c368 4228 /* TSR Bit Fields */
mbed_official 31:42176bc3c368 4229 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4230 #define RTC_TSR_TSR_SHIFT 0
mbed_official 31:42176bc3c368 4231 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 31:42176bc3c368 4232 /* TPR Bit Fields */
mbed_official 31:42176bc3c368 4233 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 31:42176bc3c368 4234 #define RTC_TPR_TPR_SHIFT 0
mbed_official 31:42176bc3c368 4235 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 31:42176bc3c368 4236 /* TAR Bit Fields */
mbed_official 31:42176bc3c368 4237 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4238 #define RTC_TAR_TAR_SHIFT 0
mbed_official 31:42176bc3c368 4239 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 31:42176bc3c368 4240 /* TCR Bit Fields */
mbed_official 31:42176bc3c368 4241 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 31:42176bc3c368 4242 #define RTC_TCR_TCR_SHIFT 0
mbed_official 31:42176bc3c368 4243 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 31:42176bc3c368 4244 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 31:42176bc3c368 4245 #define RTC_TCR_CIR_SHIFT 8
mbed_official 31:42176bc3c368 4246 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 31:42176bc3c368 4247 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 31:42176bc3c368 4248 #define RTC_TCR_TCV_SHIFT 16
mbed_official 31:42176bc3c368 4249 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 31:42176bc3c368 4250 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 31:42176bc3c368 4251 #define RTC_TCR_CIC_SHIFT 24
mbed_official 31:42176bc3c368 4252 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 31:42176bc3c368 4253 /* CR Bit Fields */
mbed_official 31:42176bc3c368 4254 #define RTC_CR_SWR_MASK 0x1u
mbed_official 31:42176bc3c368 4255 #define RTC_CR_SWR_SHIFT 0
mbed_official 31:42176bc3c368 4256 #define RTC_CR_WPE_MASK 0x2u
mbed_official 31:42176bc3c368 4257 #define RTC_CR_WPE_SHIFT 1
mbed_official 31:42176bc3c368 4258 #define RTC_CR_SUP_MASK 0x4u
mbed_official 31:42176bc3c368 4259 #define RTC_CR_SUP_SHIFT 2
mbed_official 31:42176bc3c368 4260 #define RTC_CR_UM_MASK 0x8u
mbed_official 31:42176bc3c368 4261 #define RTC_CR_UM_SHIFT 3
mbed_official 31:42176bc3c368 4262 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 31:42176bc3c368 4263 #define RTC_CR_OSCE_SHIFT 8
mbed_official 31:42176bc3c368 4264 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 31:42176bc3c368 4265 #define RTC_CR_CLKO_SHIFT 9
mbed_official 31:42176bc3c368 4266 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 31:42176bc3c368 4267 #define RTC_CR_SC16P_SHIFT 10
mbed_official 31:42176bc3c368 4268 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 31:42176bc3c368 4269 #define RTC_CR_SC8P_SHIFT 11
mbed_official 31:42176bc3c368 4270 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 31:42176bc3c368 4271 #define RTC_CR_SC4P_SHIFT 12
mbed_official 31:42176bc3c368 4272 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 31:42176bc3c368 4273 #define RTC_CR_SC2P_SHIFT 13
mbed_official 31:42176bc3c368 4274 /* SR Bit Fields */
mbed_official 31:42176bc3c368 4275 #define RTC_SR_TIF_MASK 0x1u
mbed_official 31:42176bc3c368 4276 #define RTC_SR_TIF_SHIFT 0
mbed_official 31:42176bc3c368 4277 #define RTC_SR_TOF_MASK 0x2u
mbed_official 31:42176bc3c368 4278 #define RTC_SR_TOF_SHIFT 1
mbed_official 31:42176bc3c368 4279 #define RTC_SR_TAF_MASK 0x4u
mbed_official 31:42176bc3c368 4280 #define RTC_SR_TAF_SHIFT 2
mbed_official 31:42176bc3c368 4281 #define RTC_SR_TCE_MASK 0x10u
mbed_official 31:42176bc3c368 4282 #define RTC_SR_TCE_SHIFT 4
mbed_official 31:42176bc3c368 4283 /* LR Bit Fields */
mbed_official 31:42176bc3c368 4284 #define RTC_LR_TCL_MASK 0x8u
mbed_official 31:42176bc3c368 4285 #define RTC_LR_TCL_SHIFT 3
mbed_official 31:42176bc3c368 4286 #define RTC_LR_CRL_MASK 0x10u
mbed_official 31:42176bc3c368 4287 #define RTC_LR_CRL_SHIFT 4
mbed_official 31:42176bc3c368 4288 #define RTC_LR_SRL_MASK 0x20u
mbed_official 31:42176bc3c368 4289 #define RTC_LR_SRL_SHIFT 5
mbed_official 31:42176bc3c368 4290 #define RTC_LR_LRL_MASK 0x40u
mbed_official 31:42176bc3c368 4291 #define RTC_LR_LRL_SHIFT 6
mbed_official 31:42176bc3c368 4292 /* IER Bit Fields */
mbed_official 31:42176bc3c368 4293 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 31:42176bc3c368 4294 #define RTC_IER_TIIE_SHIFT 0
mbed_official 31:42176bc3c368 4295 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 31:42176bc3c368 4296 #define RTC_IER_TOIE_SHIFT 1
mbed_official 31:42176bc3c368 4297 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 31:42176bc3c368 4298 #define RTC_IER_TAIE_SHIFT 2
mbed_official 31:42176bc3c368 4299 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 31:42176bc3c368 4300 #define RTC_IER_TSIE_SHIFT 4
mbed_official 31:42176bc3c368 4301 #define RTC_IER_WPON_MASK 0x80u
mbed_official 31:42176bc3c368 4302 #define RTC_IER_WPON_SHIFT 7
mbed_official 31:42176bc3c368 4303
mbed_official 31:42176bc3c368 4304 /**
mbed_official 31:42176bc3c368 4305 * @}
mbed_official 31:42176bc3c368 4306 */ /* end of group RTC_Register_Masks */
mbed_official 31:42176bc3c368 4307
mbed_official 31:42176bc3c368 4308
mbed_official 31:42176bc3c368 4309 /* RTC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4310 /** Peripheral RTC base address */
mbed_official 31:42176bc3c368 4311 #define RTC_BASE (0x4003D000u)
mbed_official 31:42176bc3c368 4312 /** Peripheral RTC base pointer */
mbed_official 31:42176bc3c368 4313 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 31:42176bc3c368 4314 /** Array initializer of RTC peripheral base pointers */
mbed_official 31:42176bc3c368 4315 #define RTC_BASES { RTC }
mbed_official 31:42176bc3c368 4316
mbed_official 31:42176bc3c368 4317 /**
mbed_official 31:42176bc3c368 4318 * @}
mbed_official 31:42176bc3c368 4319 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4320
mbed_official 31:42176bc3c368 4321
mbed_official 31:42176bc3c368 4322 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4323 -- SIM Peripheral Access Layer
mbed_official 31:42176bc3c368 4324 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4325
mbed_official 31:42176bc3c368 4326 /**
mbed_official 31:42176bc3c368 4327 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 31:42176bc3c368 4328 * @{
mbed_official 31:42176bc3c368 4329 */
mbed_official 31:42176bc3c368 4330
mbed_official 31:42176bc3c368 4331 /** SIM - Register Layout Typedef */
mbed_official 31:42176bc3c368 4332 typedef struct {
mbed_official 31:42176bc3c368 4333 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 31:42176bc3c368 4334 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 31:42176bc3c368 4335 uint8_t RESERVED_0[4092];
mbed_official 31:42176bc3c368 4336 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 31:42176bc3c368 4337 uint8_t RESERVED_1[4];
mbed_official 31:42176bc3c368 4338 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 31:42176bc3c368 4339 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 31:42176bc3c368 4340 uint8_t RESERVED_2[4];
mbed_official 31:42176bc3c368 4341 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 31:42176bc3c368 4342 uint8_t RESERVED_3[8];
mbed_official 31:42176bc3c368 4343 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 31:42176bc3c368 4344 uint8_t RESERVED_4[12];
mbed_official 31:42176bc3c368 4345 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 31:42176bc3c368 4346 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 31:42176bc3c368 4347 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 31:42176bc3c368 4348 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 31:42176bc3c368 4349 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 31:42176bc3c368 4350 uint8_t RESERVED_5[4];
mbed_official 31:42176bc3c368 4351 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 31:42176bc3c368 4352 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 31:42176bc3c368 4353 uint8_t RESERVED_6[4];
mbed_official 31:42176bc3c368 4354 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 31:42176bc3c368 4355 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 31:42176bc3c368 4356 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 31:42176bc3c368 4357 uint8_t RESERVED_7[156];
mbed_official 31:42176bc3c368 4358 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
mbed_official 31:42176bc3c368 4359 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
mbed_official 31:42176bc3c368 4360 } SIM_Type;
mbed_official 31:42176bc3c368 4361
mbed_official 31:42176bc3c368 4362 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4363 -- SIM Register Masks
mbed_official 31:42176bc3c368 4364 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4365
mbed_official 31:42176bc3c368 4366 /**
mbed_official 31:42176bc3c368 4367 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 31:42176bc3c368 4368 * @{
mbed_official 31:42176bc3c368 4369 */
mbed_official 31:42176bc3c368 4370
mbed_official 31:42176bc3c368 4371 /* SOPT1 Bit Fields */
mbed_official 31:42176bc3c368 4372 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 31:42176bc3c368 4373 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 31:42176bc3c368 4374 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 31:42176bc3c368 4375 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 31:42176bc3c368 4376 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 31:42176bc3c368 4377 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 31:42176bc3c368 4378 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 31:42176bc3c368 4379 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 31:42176bc3c368 4380 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 31:42176bc3c368 4381 /* SOPT1CFG Bit Fields */
mbed_official 31:42176bc3c368 4382 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 31:42176bc3c368 4383 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 31:42176bc3c368 4384 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 31:42176bc3c368 4385 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 31:42176bc3c368 4386 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 31:42176bc3c368 4387 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 31:42176bc3c368 4388 /* SOPT2 Bit Fields */
mbed_official 31:42176bc3c368 4389 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 31:42176bc3c368 4390 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 31:42176bc3c368 4391 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 31:42176bc3c368 4392 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 31:42176bc3c368 4393 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 31:42176bc3c368 4394 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
mbed_official 31:42176bc3c368 4395 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mbed_official 31:42176bc3c368 4396 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 31:42176bc3c368 4397 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 31:42176bc3c368 4398 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
mbed_official 31:42176bc3c368 4399 #define SIM_SOPT2_TPMSRC_SHIFT 24
mbed_official 31:42176bc3c368 4400 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
mbed_official 31:42176bc3c368 4401 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
mbed_official 31:42176bc3c368 4402 #define SIM_SOPT2_UART0SRC_SHIFT 26
mbed_official 31:42176bc3c368 4403 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
mbed_official 31:42176bc3c368 4404 /* SOPT4 Bit Fields */
mbed_official 44:2ce89a25b635 4405 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
mbed_official 31:42176bc3c368 4406 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
mbed_official 44:2ce89a25b635 4407 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
mbed_official 31:42176bc3c368 4408 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
mbed_official 31:42176bc3c368 4409 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
mbed_official 31:42176bc3c368 4410 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
mbed_official 31:42176bc3c368 4411 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
mbed_official 31:42176bc3c368 4412 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
mbed_official 31:42176bc3c368 4413 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
mbed_official 31:42176bc3c368 4414 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
mbed_official 31:42176bc3c368 4415 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
mbed_official 31:42176bc3c368 4416 /* SOPT5 Bit Fields */
mbed_official 31:42176bc3c368 4417 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
mbed_official 31:42176bc3c368 4418 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 31:42176bc3c368 4419 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
mbed_official 31:42176bc3c368 4420 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
mbed_official 31:42176bc3c368 4421 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 31:42176bc3c368 4422 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
mbed_official 31:42176bc3c368 4423 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mbed_official 31:42176bc3c368 4424 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
mbed_official 31:42176bc3c368 4425 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u
mbed_official 31:42176bc3c368 4426 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mbed_official 31:42176bc3c368 4427 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
mbed_official 31:42176bc3c368 4428 #define SIM_SOPT5_UART0ODE_SHIFT 16
mbed_official 31:42176bc3c368 4429 #define SIM_SOPT5_UART1ODE_MASK 0x20000u
mbed_official 31:42176bc3c368 4430 #define SIM_SOPT5_UART1ODE_SHIFT 17
mbed_official 31:42176bc3c368 4431 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
mbed_official 31:42176bc3c368 4432 #define SIM_SOPT5_UART2ODE_SHIFT 18
mbed_official 31:42176bc3c368 4433 /* SOPT7 Bit Fields */
mbed_official 31:42176bc3c368 4434 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 31:42176bc3c368 4435 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 31:42176bc3c368 4436 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 31:42176bc3c368 4437 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 31:42176bc3c368 4438 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 31:42176bc3c368 4439 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 31:42176bc3c368 4440 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 31:42176bc3c368 4441 /* SDID Bit Fields */
mbed_official 31:42176bc3c368 4442 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 31:42176bc3c368 4443 #define SIM_SDID_PINID_SHIFT 0
mbed_official 31:42176bc3c368 4444 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 31:42176bc3c368 4445 #define SIM_SDID_DIEID_MASK 0xF80u
mbed_official 31:42176bc3c368 4446 #define SIM_SDID_DIEID_SHIFT 7
mbed_official 31:42176bc3c368 4447 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mbed_official 31:42176bc3c368 4448 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 31:42176bc3c368 4449 #define SIM_SDID_REVID_SHIFT 12
mbed_official 31:42176bc3c368 4450 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 31:42176bc3c368 4451 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
mbed_official 31:42176bc3c368 4452 #define SIM_SDID_SRAMSIZE_SHIFT 16
mbed_official 31:42176bc3c368 4453 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
mbed_official 31:42176bc3c368 4454 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 31:42176bc3c368 4455 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 31:42176bc3c368 4456 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 31:42176bc3c368 4457 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 31:42176bc3c368 4458 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 31:42176bc3c368 4459 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 31:42176bc3c368 4460 #define SIM_SDID_FAMID_MASK 0xF0000000u
mbed_official 31:42176bc3c368 4461 #define SIM_SDID_FAMID_SHIFT 28
mbed_official 31:42176bc3c368 4462 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 31:42176bc3c368 4463 /* SCGC4 Bit Fields */
mbed_official 31:42176bc3c368 4464 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 31:42176bc3c368 4465 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 31:42176bc3c368 4466 #define SIM_SCGC4_I2C1_MASK 0x80u
mbed_official 31:42176bc3c368 4467 #define SIM_SCGC4_I2C1_SHIFT 7
mbed_official 31:42176bc3c368 4468 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 31:42176bc3c368 4469 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 31:42176bc3c368 4470 #define SIM_SCGC4_UART1_MASK 0x800u
mbed_official 31:42176bc3c368 4471 #define SIM_SCGC4_UART1_SHIFT 11
mbed_official 31:42176bc3c368 4472 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 31:42176bc3c368 4473 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 31:42176bc3c368 4474 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mbed_official 31:42176bc3c368 4475 #define SIM_SCGC4_USBOTG_SHIFT 18
mbed_official 31:42176bc3c368 4476 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 31:42176bc3c368 4477 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 31:42176bc3c368 4478 #define SIM_SCGC4_SPI0_MASK 0x400000u
mbed_official 31:42176bc3c368 4479 #define SIM_SCGC4_SPI0_SHIFT 22
mbed_official 31:42176bc3c368 4480 #define SIM_SCGC4_SPI1_MASK 0x800000u
mbed_official 31:42176bc3c368 4481 #define SIM_SCGC4_SPI1_SHIFT 23
mbed_official 31:42176bc3c368 4482 /* SCGC5 Bit Fields */
mbed_official 31:42176bc3c368 4483 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 31:42176bc3c368 4484 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 31:42176bc3c368 4485 #define SIM_SCGC5_TSI_MASK 0x20u
mbed_official 31:42176bc3c368 4486 #define SIM_SCGC5_TSI_SHIFT 5
mbed_official 31:42176bc3c368 4487 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 31:42176bc3c368 4488 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 31:42176bc3c368 4489 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 31:42176bc3c368 4490 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 31:42176bc3c368 4491 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 31:42176bc3c368 4492 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 31:42176bc3c368 4493 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 31:42176bc3c368 4494 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 31:42176bc3c368 4495 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 31:42176bc3c368 4496 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 44:2ce89a25b635 4497 #define SIM_SCGC5_SLCD_MASK 0x80000u
mbed_official 44:2ce89a25b635 4498 #define SIM_SCGC5_SLCD_SHIFT 19
mbed_official 31:42176bc3c368 4499 /* SCGC6 Bit Fields */
mbed_official 31:42176bc3c368 4500 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 31:42176bc3c368 4501 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 31:42176bc3c368 4502 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 31:42176bc3c368 4503 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 44:2ce89a25b635 4504 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 44:2ce89a25b635 4505 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 31:42176bc3c368 4506 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 31:42176bc3c368 4507 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 31:42176bc3c368 4508 #define SIM_SCGC6_TPM0_MASK 0x1000000u
mbed_official 31:42176bc3c368 4509 #define SIM_SCGC6_TPM0_SHIFT 24
mbed_official 31:42176bc3c368 4510 #define SIM_SCGC6_TPM1_MASK 0x2000000u
mbed_official 31:42176bc3c368 4511 #define SIM_SCGC6_TPM1_SHIFT 25
mbed_official 31:42176bc3c368 4512 #define SIM_SCGC6_TPM2_MASK 0x4000000u
mbed_official 31:42176bc3c368 4513 #define SIM_SCGC6_TPM2_SHIFT 26
mbed_official 31:42176bc3c368 4514 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 31:42176bc3c368 4515 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 31:42176bc3c368 4516 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 31:42176bc3c368 4517 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 31:42176bc3c368 4518 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 31:42176bc3c368 4519 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 31:42176bc3c368 4520 /* SCGC7 Bit Fields */
mbed_official 31:42176bc3c368 4521 #define SIM_SCGC7_DMA_MASK 0x100u
mbed_official 31:42176bc3c368 4522 #define SIM_SCGC7_DMA_SHIFT 8
mbed_official 31:42176bc3c368 4523 /* CLKDIV1 Bit Fields */
mbed_official 31:42176bc3c368 4524 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
mbed_official 31:42176bc3c368 4525 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 31:42176bc3c368 4526 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 31:42176bc3c368 4527 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 31:42176bc3c368 4528 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 31:42176bc3c368 4529 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 31:42176bc3c368 4530 /* FCFG1 Bit Fields */
mbed_official 31:42176bc3c368 4531 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 31:42176bc3c368 4532 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 31:42176bc3c368 4533 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 31:42176bc3c368 4534 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 31:42176bc3c368 4535 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 31:42176bc3c368 4536 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 31:42176bc3c368 4537 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 31:42176bc3c368 4538 /* FCFG2 Bit Fields */
mbed_official 44:2ce89a25b635 4539 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 44:2ce89a25b635 4540 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 44:2ce89a25b635 4541 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 44:2ce89a25b635 4542 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 44:2ce89a25b635 4543 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 44:2ce89a25b635 4544 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 31:42176bc3c368 4545 /* UIDMH Bit Fields */
mbed_official 31:42176bc3c368 4546 #define SIM_UIDMH_UID_MASK 0xFFFFu
mbed_official 31:42176bc3c368 4547 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 31:42176bc3c368 4548 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 31:42176bc3c368 4549 /* UIDML Bit Fields */
mbed_official 31:42176bc3c368 4550 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4551 #define SIM_UIDML_UID_SHIFT 0
mbed_official 31:42176bc3c368 4552 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 31:42176bc3c368 4553 /* UIDL Bit Fields */
mbed_official 31:42176bc3c368 4554 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 31:42176bc3c368 4555 #define SIM_UIDL_UID_SHIFT 0
mbed_official 31:42176bc3c368 4556 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 31:42176bc3c368 4557 /* COPC Bit Fields */
mbed_official 31:42176bc3c368 4558 #define SIM_COPC_COPW_MASK 0x1u
mbed_official 31:42176bc3c368 4559 #define SIM_COPC_COPW_SHIFT 0
mbed_official 31:42176bc3c368 4560 #define SIM_COPC_COPCLKS_MASK 0x2u
mbed_official 31:42176bc3c368 4561 #define SIM_COPC_COPCLKS_SHIFT 1
mbed_official 31:42176bc3c368 4562 #define SIM_COPC_COPT_MASK 0xCu
mbed_official 31:42176bc3c368 4563 #define SIM_COPC_COPT_SHIFT 2
mbed_official 31:42176bc3c368 4564 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
mbed_official 31:42176bc3c368 4565 /* SRVCOP Bit Fields */
mbed_official 31:42176bc3c368 4566 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
mbed_official 31:42176bc3c368 4567 #define SIM_SRVCOP_SRVCOP_SHIFT 0
mbed_official 31:42176bc3c368 4568 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
mbed_official 31:42176bc3c368 4569
mbed_official 31:42176bc3c368 4570 /**
mbed_official 31:42176bc3c368 4571 * @}
mbed_official 31:42176bc3c368 4572 */ /* end of group SIM_Register_Masks */
mbed_official 31:42176bc3c368 4573
mbed_official 31:42176bc3c368 4574
mbed_official 31:42176bc3c368 4575 /* SIM - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4576 /** Peripheral SIM base address */
mbed_official 31:42176bc3c368 4577 #define SIM_BASE (0x40047000u)
mbed_official 31:42176bc3c368 4578 /** Peripheral SIM base pointer */
mbed_official 31:42176bc3c368 4579 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 31:42176bc3c368 4580 /** Array initializer of SIM peripheral base pointers */
mbed_official 31:42176bc3c368 4581 #define SIM_BASES { SIM }
mbed_official 31:42176bc3c368 4582
mbed_official 31:42176bc3c368 4583 /**
mbed_official 31:42176bc3c368 4584 * @}
mbed_official 31:42176bc3c368 4585 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4586
mbed_official 31:42176bc3c368 4587
mbed_official 31:42176bc3c368 4588 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4589 -- SMC Peripheral Access Layer
mbed_official 31:42176bc3c368 4590 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4591
mbed_official 31:42176bc3c368 4592 /**
mbed_official 31:42176bc3c368 4593 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 31:42176bc3c368 4594 * @{
mbed_official 31:42176bc3c368 4595 */
mbed_official 31:42176bc3c368 4596
mbed_official 31:42176bc3c368 4597 /** SMC - Register Layout Typedef */
mbed_official 31:42176bc3c368 4598 typedef struct {
mbed_official 31:42176bc3c368 4599 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 31:42176bc3c368 4600 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 31:42176bc3c368 4601 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mbed_official 31:42176bc3c368 4602 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 31:42176bc3c368 4603 } SMC_Type;
mbed_official 31:42176bc3c368 4604
mbed_official 31:42176bc3c368 4605 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4606 -- SMC Register Masks
mbed_official 31:42176bc3c368 4607 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4608
mbed_official 31:42176bc3c368 4609 /**
mbed_official 31:42176bc3c368 4610 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 31:42176bc3c368 4611 * @{
mbed_official 31:42176bc3c368 4612 */
mbed_official 31:42176bc3c368 4613
mbed_official 31:42176bc3c368 4614 /* PMPROT Bit Fields */
mbed_official 31:42176bc3c368 4615 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 31:42176bc3c368 4616 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 31:42176bc3c368 4617 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 31:42176bc3c368 4618 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 31:42176bc3c368 4619 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 31:42176bc3c368 4620 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 31:42176bc3c368 4621 /* PMCTRL Bit Fields */
mbed_official 31:42176bc3c368 4622 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 31:42176bc3c368 4623 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 31:42176bc3c368 4624 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 31:42176bc3c368 4625 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 31:42176bc3c368 4626 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 31:42176bc3c368 4627 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 31:42176bc3c368 4628 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 31:42176bc3c368 4629 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 31:42176bc3c368 4630 /* STOPCTRL Bit Fields */
mbed_official 31:42176bc3c368 4631 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
mbed_official 31:42176bc3c368 4632 #define SMC_STOPCTRL_VLLSM_SHIFT 0
mbed_official 31:42176bc3c368 4633 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
mbed_official 31:42176bc3c368 4634 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mbed_official 31:42176bc3c368 4635 #define SMC_STOPCTRL_PORPO_SHIFT 5
mbed_official 31:42176bc3c368 4636 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mbed_official 31:42176bc3c368 4637 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mbed_official 31:42176bc3c368 4638 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mbed_official 31:42176bc3c368 4639 /* PMSTAT Bit Fields */
mbed_official 31:42176bc3c368 4640 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mbed_official 31:42176bc3c368 4641 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 31:42176bc3c368 4642 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 31:42176bc3c368 4643
mbed_official 31:42176bc3c368 4644 /**
mbed_official 31:42176bc3c368 4645 * @}
mbed_official 31:42176bc3c368 4646 */ /* end of group SMC_Register_Masks */
mbed_official 31:42176bc3c368 4647
mbed_official 31:42176bc3c368 4648
mbed_official 31:42176bc3c368 4649 /* SMC - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4650 /** Peripheral SMC base address */
mbed_official 31:42176bc3c368 4651 #define SMC_BASE (0x4007E000u)
mbed_official 31:42176bc3c368 4652 /** Peripheral SMC base pointer */
mbed_official 31:42176bc3c368 4653 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 31:42176bc3c368 4654 /** Array initializer of SMC peripheral base pointers */
mbed_official 31:42176bc3c368 4655 #define SMC_BASES { SMC }
mbed_official 31:42176bc3c368 4656
mbed_official 31:42176bc3c368 4657 /**
mbed_official 31:42176bc3c368 4658 * @}
mbed_official 31:42176bc3c368 4659 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4660
mbed_official 31:42176bc3c368 4661
mbed_official 31:42176bc3c368 4662 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4663 -- SPI Peripheral Access Layer
mbed_official 31:42176bc3c368 4664 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4665
mbed_official 31:42176bc3c368 4666 /**
mbed_official 31:42176bc3c368 4667 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 31:42176bc3c368 4668 * @{
mbed_official 31:42176bc3c368 4669 */
mbed_official 31:42176bc3c368 4670
mbed_official 31:42176bc3c368 4671 /** SPI - Register Layout Typedef */
mbed_official 31:42176bc3c368 4672 typedef struct {
mbed_official 44:2ce89a25b635 4673 __I uint8_t S; /**< SPI status register, offset: 0x0 */
mbed_official 44:2ce89a25b635 4674 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
mbed_official 44:2ce89a25b635 4675 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
mbed_official 44:2ce89a25b635 4676 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
mbed_official 44:2ce89a25b635 4677 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
mbed_official 44:2ce89a25b635 4678 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
mbed_official 44:2ce89a25b635 4679 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
mbed_official 44:2ce89a25b635 4680 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
mbed_official 44:2ce89a25b635 4681 uint8_t RESERVED_0[2];
mbed_official 44:2ce89a25b635 4682 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
mbed_official 44:2ce89a25b635 4683 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
mbed_official 31:42176bc3c368 4684 } SPI_Type;
mbed_official 31:42176bc3c368 4685
mbed_official 31:42176bc3c368 4686 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4687 -- SPI Register Masks
mbed_official 31:42176bc3c368 4688 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4689
mbed_official 31:42176bc3c368 4690 /**
mbed_official 31:42176bc3c368 4691 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 31:42176bc3c368 4692 * @{
mbed_official 31:42176bc3c368 4693 */
mbed_official 31:42176bc3c368 4694
mbed_official 44:2ce89a25b635 4695 /* S Bit Fields */
mbed_official 44:2ce89a25b635 4696 #define SPI_S_RFIFOEF_MASK 0x1u
mbed_official 44:2ce89a25b635 4697 #define SPI_S_RFIFOEF_SHIFT 0
mbed_official 44:2ce89a25b635 4698 #define SPI_S_TXFULLF_MASK 0x2u
mbed_official 44:2ce89a25b635 4699 #define SPI_S_TXFULLF_SHIFT 1
mbed_official 44:2ce89a25b635 4700 #define SPI_S_TNEAREF_MASK 0x4u
mbed_official 44:2ce89a25b635 4701 #define SPI_S_TNEAREF_SHIFT 2
mbed_official 44:2ce89a25b635 4702 #define SPI_S_RNFULLF_MASK 0x8u
mbed_official 44:2ce89a25b635 4703 #define SPI_S_RNFULLF_SHIFT 3
mbed_official 44:2ce89a25b635 4704 #define SPI_S_MODF_MASK 0x10u
mbed_official 44:2ce89a25b635 4705 #define SPI_S_MODF_SHIFT 4
mbed_official 44:2ce89a25b635 4706 #define SPI_S_SPTEF_MASK 0x20u
mbed_official 44:2ce89a25b635 4707 #define SPI_S_SPTEF_SHIFT 5
mbed_official 44:2ce89a25b635 4708 #define SPI_S_SPMF_MASK 0x40u
mbed_official 44:2ce89a25b635 4709 #define SPI_S_SPMF_SHIFT 6
mbed_official 44:2ce89a25b635 4710 #define SPI_S_SPRF_MASK 0x80u
mbed_official 44:2ce89a25b635 4711 #define SPI_S_SPRF_SHIFT 7
mbed_official 44:2ce89a25b635 4712 /* BR Bit Fields */
mbed_official 44:2ce89a25b635 4713 #define SPI_BR_SPR_MASK 0xFu
mbed_official 44:2ce89a25b635 4714 #define SPI_BR_SPR_SHIFT 0
mbed_official 44:2ce89a25b635 4715 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
mbed_official 44:2ce89a25b635 4716 #define SPI_BR_SPPR_MASK 0x70u
mbed_official 44:2ce89a25b635 4717 #define SPI_BR_SPPR_SHIFT 4
mbed_official 44:2ce89a25b635 4718 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
mbed_official 44:2ce89a25b635 4719 /* C2 Bit Fields */
mbed_official 44:2ce89a25b635 4720 #define SPI_C2_SPC0_MASK 0x1u
mbed_official 44:2ce89a25b635 4721 #define SPI_C2_SPC0_SHIFT 0
mbed_official 44:2ce89a25b635 4722 #define SPI_C2_SPISWAI_MASK 0x2u
mbed_official 44:2ce89a25b635 4723 #define SPI_C2_SPISWAI_SHIFT 1
mbed_official 44:2ce89a25b635 4724 #define SPI_C2_RXDMAE_MASK 0x4u
mbed_official 44:2ce89a25b635 4725 #define SPI_C2_RXDMAE_SHIFT 2
mbed_official 44:2ce89a25b635 4726 #define SPI_C2_BIDIROE_MASK 0x8u
mbed_official 44:2ce89a25b635 4727 #define SPI_C2_BIDIROE_SHIFT 3
mbed_official 44:2ce89a25b635 4728 #define SPI_C2_MODFEN_MASK 0x10u
mbed_official 44:2ce89a25b635 4729 #define SPI_C2_MODFEN_SHIFT 4
mbed_official 44:2ce89a25b635 4730 #define SPI_C2_TXDMAE_MASK 0x20u
mbed_official 44:2ce89a25b635 4731 #define SPI_C2_TXDMAE_SHIFT 5
mbed_official 44:2ce89a25b635 4732 #define SPI_C2_SPIMODE_MASK 0x40u
mbed_official 44:2ce89a25b635 4733 #define SPI_C2_SPIMODE_SHIFT 6
mbed_official 44:2ce89a25b635 4734 #define SPI_C2_SPMIE_MASK 0x80u
mbed_official 44:2ce89a25b635 4735 #define SPI_C2_SPMIE_SHIFT 7
mbed_official 31:42176bc3c368 4736 /* C1 Bit Fields */
mbed_official 31:42176bc3c368 4737 #define SPI_C1_LSBFE_MASK 0x1u
mbed_official 31:42176bc3c368 4738 #define SPI_C1_LSBFE_SHIFT 0
mbed_official 31:42176bc3c368 4739 #define SPI_C1_SSOE_MASK 0x2u
mbed_official 31:42176bc3c368 4740 #define SPI_C1_SSOE_SHIFT 1
mbed_official 31:42176bc3c368 4741 #define SPI_C1_CPHA_MASK 0x4u
mbed_official 31:42176bc3c368 4742 #define SPI_C1_CPHA_SHIFT 2
mbed_official 31:42176bc3c368 4743 #define SPI_C1_CPOL_MASK 0x8u
mbed_official 31:42176bc3c368 4744 #define SPI_C1_CPOL_SHIFT 3
mbed_official 31:42176bc3c368 4745 #define SPI_C1_MSTR_MASK 0x10u
mbed_official 31:42176bc3c368 4746 #define SPI_C1_MSTR_SHIFT 4
mbed_official 31:42176bc3c368 4747 #define SPI_C1_SPTIE_MASK 0x20u
mbed_official 31:42176bc3c368 4748 #define SPI_C1_SPTIE_SHIFT 5
mbed_official 31:42176bc3c368 4749 #define SPI_C1_SPE_MASK 0x40u
mbed_official 31:42176bc3c368 4750 #define SPI_C1_SPE_SHIFT 6
mbed_official 31:42176bc3c368 4751 #define SPI_C1_SPIE_MASK 0x80u
mbed_official 31:42176bc3c368 4752 #define SPI_C1_SPIE_SHIFT 7
mbed_official 44:2ce89a25b635 4753 /* ML Bit Fields */
mbed_official 44:2ce89a25b635 4754 #define SPI_ML_Bits_MASK 0xFFu
mbed_official 44:2ce89a25b635 4755 #define SPI_ML_Bits_SHIFT 0
mbed_official 44:2ce89a25b635 4756 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
mbed_official 44:2ce89a25b635 4757 /* MH Bit Fields */
mbed_official 44:2ce89a25b635 4758 #define SPI_MH_Bits_MASK 0xFFu
mbed_official 44:2ce89a25b635 4759 #define SPI_MH_Bits_SHIFT 0
mbed_official 44:2ce89a25b635 4760 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
mbed_official 44:2ce89a25b635 4761 /* DL Bit Fields */
mbed_official 44:2ce89a25b635 4762 #define SPI_DL_Bits_MASK 0xFFu
mbed_official 44:2ce89a25b635 4763 #define SPI_DL_Bits_SHIFT 0
mbed_official 44:2ce89a25b635 4764 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
mbed_official 44:2ce89a25b635 4765 /* DH Bit Fields */
mbed_official 44:2ce89a25b635 4766 #define SPI_DH_Bits_MASK 0xFFu
mbed_official 44:2ce89a25b635 4767 #define SPI_DH_Bits_SHIFT 0
mbed_official 44:2ce89a25b635 4768 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
mbed_official 44:2ce89a25b635 4769 /* CI Bit Fields */
mbed_official 44:2ce89a25b635 4770 #define SPI_CI_SPRFCI_MASK 0x1u
mbed_official 44:2ce89a25b635 4771 #define SPI_CI_SPRFCI_SHIFT 0
mbed_official 44:2ce89a25b635 4772 #define SPI_CI_SPTEFCI_MASK 0x2u
mbed_official 44:2ce89a25b635 4773 #define SPI_CI_SPTEFCI_SHIFT 1
mbed_official 44:2ce89a25b635 4774 #define SPI_CI_RNFULLFCI_MASK 0x4u
mbed_official 44:2ce89a25b635 4775 #define SPI_CI_RNFULLFCI_SHIFT 2
mbed_official 44:2ce89a25b635 4776 #define SPI_CI_TNEAREFCI_MASK 0x8u
mbed_official 44:2ce89a25b635 4777 #define SPI_CI_TNEAREFCI_SHIFT 3
mbed_official 44:2ce89a25b635 4778 #define SPI_CI_RXFOF_MASK 0x10u
mbed_official 44:2ce89a25b635 4779 #define SPI_CI_RXFOF_SHIFT 4
mbed_official 44:2ce89a25b635 4780 #define SPI_CI_TXFOF_MASK 0x20u
mbed_official 44:2ce89a25b635 4781 #define SPI_CI_TXFOF_SHIFT 5
mbed_official 44:2ce89a25b635 4782 #define SPI_CI_RXFERR_MASK 0x40u
mbed_official 44:2ce89a25b635 4783 #define SPI_CI_RXFERR_SHIFT 6
mbed_official 44:2ce89a25b635 4784 #define SPI_CI_TXFERR_MASK 0x80u
mbed_official 44:2ce89a25b635 4785 #define SPI_CI_TXFERR_SHIFT 7
mbed_official 44:2ce89a25b635 4786 /* C3 Bit Fields */
mbed_official 44:2ce89a25b635 4787 #define SPI_C3_FIFOMODE_MASK 0x1u
mbed_official 44:2ce89a25b635 4788 #define SPI_C3_FIFOMODE_SHIFT 0
mbed_official 44:2ce89a25b635 4789 #define SPI_C3_RNFULLIEN_MASK 0x2u
mbed_official 44:2ce89a25b635 4790 #define SPI_C3_RNFULLIEN_SHIFT 1
mbed_official 44:2ce89a25b635 4791 #define SPI_C3_TNEARIEN_MASK 0x4u
mbed_official 44:2ce89a25b635 4792 #define SPI_C3_TNEARIEN_SHIFT 2
mbed_official 44:2ce89a25b635 4793 #define SPI_C3_INTCLR_MASK 0x8u
mbed_official 44:2ce89a25b635 4794 #define SPI_C3_INTCLR_SHIFT 3
mbed_official 44:2ce89a25b635 4795 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
mbed_official 44:2ce89a25b635 4796 #define SPI_C3_RNFULLF_MARK_SHIFT 4
mbed_official 44:2ce89a25b635 4797 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
mbed_official 44:2ce89a25b635 4798 #define SPI_C3_TNEAREF_MARK_SHIFT 5
mbed_official 31:42176bc3c368 4799
mbed_official 31:42176bc3c368 4800 /**
mbed_official 31:42176bc3c368 4801 * @}
mbed_official 31:42176bc3c368 4802 */ /* end of group SPI_Register_Masks */
mbed_official 31:42176bc3c368 4803
mbed_official 31:42176bc3c368 4804
mbed_official 31:42176bc3c368 4805 /* SPI - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4806 /** Peripheral SPI0 base address */
mbed_official 31:42176bc3c368 4807 #define SPI0_BASE (0x40076000u)
mbed_official 31:42176bc3c368 4808 /** Peripheral SPI0 base pointer */
mbed_official 31:42176bc3c368 4809 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 31:42176bc3c368 4810 /** Peripheral SPI1 base address */
mbed_official 31:42176bc3c368 4811 #define SPI1_BASE (0x40077000u)
mbed_official 31:42176bc3c368 4812 /** Peripheral SPI1 base pointer */
mbed_official 31:42176bc3c368 4813 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 31:42176bc3c368 4814 /** Array initializer of SPI peripheral base pointers */
mbed_official 31:42176bc3c368 4815 #define SPI_BASES { SPI0, SPI1 }
mbed_official 31:42176bc3c368 4816
mbed_official 31:42176bc3c368 4817 /**
mbed_official 31:42176bc3c368 4818 * @}
mbed_official 31:42176bc3c368 4819 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4820
mbed_official 31:42176bc3c368 4821
mbed_official 31:42176bc3c368 4822 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4823 -- TPM Peripheral Access Layer
mbed_official 31:42176bc3c368 4824 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4825
mbed_official 31:42176bc3c368 4826 /**
mbed_official 31:42176bc3c368 4827 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
mbed_official 31:42176bc3c368 4828 * @{
mbed_official 31:42176bc3c368 4829 */
mbed_official 31:42176bc3c368 4830
mbed_official 31:42176bc3c368 4831 /** TPM - Register Layout Typedef */
mbed_official 31:42176bc3c368 4832 typedef struct {
mbed_official 31:42176bc3c368 4833 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mbed_official 31:42176bc3c368 4834 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 31:42176bc3c368 4835 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 31:42176bc3c368 4836 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 31:42176bc3c368 4837 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mbed_official 31:42176bc3c368 4838 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 31:42176bc3c368 4839 } CONTROLS[6];
mbed_official 31:42176bc3c368 4840 uint8_t RESERVED_0[20];
mbed_official 31:42176bc3c368 4841 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mbed_official 31:42176bc3c368 4842 uint8_t RESERVED_1[48];
mbed_official 31:42176bc3c368 4843 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 31:42176bc3c368 4844 } TPM_Type;
mbed_official 31:42176bc3c368 4845
mbed_official 31:42176bc3c368 4846 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4847 -- TPM Register Masks
mbed_official 31:42176bc3c368 4848 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4849
mbed_official 31:42176bc3c368 4850 /**
mbed_official 31:42176bc3c368 4851 * @addtogroup TPM_Register_Masks TPM Register Masks
mbed_official 31:42176bc3c368 4852 * @{
mbed_official 31:42176bc3c368 4853 */
mbed_official 31:42176bc3c368 4854
mbed_official 31:42176bc3c368 4855 /* SC Bit Fields */
mbed_official 31:42176bc3c368 4856 #define TPM_SC_PS_MASK 0x7u
mbed_official 31:42176bc3c368 4857 #define TPM_SC_PS_SHIFT 0
mbed_official 31:42176bc3c368 4858 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
mbed_official 31:42176bc3c368 4859 #define TPM_SC_CMOD_MASK 0x18u
mbed_official 31:42176bc3c368 4860 #define TPM_SC_CMOD_SHIFT 3
mbed_official 31:42176bc3c368 4861 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
mbed_official 31:42176bc3c368 4862 #define TPM_SC_CPWMS_MASK 0x20u
mbed_official 31:42176bc3c368 4863 #define TPM_SC_CPWMS_SHIFT 5
mbed_official 31:42176bc3c368 4864 #define TPM_SC_TOIE_MASK 0x40u
mbed_official 31:42176bc3c368 4865 #define TPM_SC_TOIE_SHIFT 6
mbed_official 31:42176bc3c368 4866 #define TPM_SC_TOF_MASK 0x80u
mbed_official 31:42176bc3c368 4867 #define TPM_SC_TOF_SHIFT 7
mbed_official 31:42176bc3c368 4868 #define TPM_SC_DMA_MASK 0x100u
mbed_official 31:42176bc3c368 4869 #define TPM_SC_DMA_SHIFT 8
mbed_official 31:42176bc3c368 4870 /* CNT Bit Fields */
mbed_official 31:42176bc3c368 4871 #define TPM_CNT_COUNT_MASK 0xFFFFu
mbed_official 31:42176bc3c368 4872 #define TPM_CNT_COUNT_SHIFT 0
mbed_official 31:42176bc3c368 4873 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
mbed_official 31:42176bc3c368 4874 /* MOD Bit Fields */
mbed_official 31:42176bc3c368 4875 #define TPM_MOD_MOD_MASK 0xFFFFu
mbed_official 31:42176bc3c368 4876 #define TPM_MOD_MOD_SHIFT 0
mbed_official 31:42176bc3c368 4877 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
mbed_official 31:42176bc3c368 4878 /* CnSC Bit Fields */
mbed_official 31:42176bc3c368 4879 #define TPM_CnSC_DMA_MASK 0x1u
mbed_official 31:42176bc3c368 4880 #define TPM_CnSC_DMA_SHIFT 0
mbed_official 31:42176bc3c368 4881 #define TPM_CnSC_ELSA_MASK 0x4u
mbed_official 31:42176bc3c368 4882 #define TPM_CnSC_ELSA_SHIFT 2
mbed_official 31:42176bc3c368 4883 #define TPM_CnSC_ELSB_MASK 0x8u
mbed_official 31:42176bc3c368 4884 #define TPM_CnSC_ELSB_SHIFT 3
mbed_official 31:42176bc3c368 4885 #define TPM_CnSC_MSA_MASK 0x10u
mbed_official 31:42176bc3c368 4886 #define TPM_CnSC_MSA_SHIFT 4
mbed_official 31:42176bc3c368 4887 #define TPM_CnSC_MSB_MASK 0x20u
mbed_official 31:42176bc3c368 4888 #define TPM_CnSC_MSB_SHIFT 5
mbed_official 31:42176bc3c368 4889 #define TPM_CnSC_CHIE_MASK 0x40u
mbed_official 31:42176bc3c368 4890 #define TPM_CnSC_CHIE_SHIFT 6
mbed_official 31:42176bc3c368 4891 #define TPM_CnSC_CHF_MASK 0x80u
mbed_official 31:42176bc3c368 4892 #define TPM_CnSC_CHF_SHIFT 7
mbed_official 31:42176bc3c368 4893 /* CnV Bit Fields */
mbed_official 31:42176bc3c368 4894 #define TPM_CnV_VAL_MASK 0xFFFFu
mbed_official 31:42176bc3c368 4895 #define TPM_CnV_VAL_SHIFT 0
mbed_official 31:42176bc3c368 4896 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
mbed_official 31:42176bc3c368 4897 /* STATUS Bit Fields */
mbed_official 31:42176bc3c368 4898 #define TPM_STATUS_CH0F_MASK 0x1u
mbed_official 31:42176bc3c368 4899 #define TPM_STATUS_CH0F_SHIFT 0
mbed_official 31:42176bc3c368 4900 #define TPM_STATUS_CH1F_MASK 0x2u
mbed_official 31:42176bc3c368 4901 #define TPM_STATUS_CH1F_SHIFT 1
mbed_official 31:42176bc3c368 4902 #define TPM_STATUS_CH2F_MASK 0x4u
mbed_official 31:42176bc3c368 4903 #define TPM_STATUS_CH2F_SHIFT 2
mbed_official 31:42176bc3c368 4904 #define TPM_STATUS_CH3F_MASK 0x8u
mbed_official 31:42176bc3c368 4905 #define TPM_STATUS_CH3F_SHIFT 3
mbed_official 31:42176bc3c368 4906 #define TPM_STATUS_CH4F_MASK 0x10u
mbed_official 31:42176bc3c368 4907 #define TPM_STATUS_CH4F_SHIFT 4
mbed_official 31:42176bc3c368 4908 #define TPM_STATUS_CH5F_MASK 0x20u
mbed_official 31:42176bc3c368 4909 #define TPM_STATUS_CH5F_SHIFT 5
mbed_official 31:42176bc3c368 4910 #define TPM_STATUS_TOF_MASK 0x100u
mbed_official 31:42176bc3c368 4911 #define TPM_STATUS_TOF_SHIFT 8
mbed_official 31:42176bc3c368 4912 /* CONF Bit Fields */
mbed_official 31:42176bc3c368 4913 #define TPM_CONF_DOZEEN_MASK 0x20u
mbed_official 31:42176bc3c368 4914 #define TPM_CONF_DOZEEN_SHIFT 5
mbed_official 31:42176bc3c368 4915 #define TPM_CONF_DBGMODE_MASK 0xC0u
mbed_official 31:42176bc3c368 4916 #define TPM_CONF_DBGMODE_SHIFT 6
mbed_official 31:42176bc3c368 4917 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
mbed_official 31:42176bc3c368 4918 #define TPM_CONF_GTBEEN_MASK 0x200u
mbed_official 31:42176bc3c368 4919 #define TPM_CONF_GTBEEN_SHIFT 9
mbed_official 31:42176bc3c368 4920 #define TPM_CONF_CSOT_MASK 0x10000u
mbed_official 31:42176bc3c368 4921 #define TPM_CONF_CSOT_SHIFT 16
mbed_official 31:42176bc3c368 4922 #define TPM_CONF_CSOO_MASK 0x20000u
mbed_official 31:42176bc3c368 4923 #define TPM_CONF_CSOO_SHIFT 17
mbed_official 31:42176bc3c368 4924 #define TPM_CONF_CROT_MASK 0x40000u
mbed_official 31:42176bc3c368 4925 #define TPM_CONF_CROT_SHIFT 18
mbed_official 31:42176bc3c368 4926 #define TPM_CONF_TRGSEL_MASK 0xF000000u
mbed_official 31:42176bc3c368 4927 #define TPM_CONF_TRGSEL_SHIFT 24
mbed_official 31:42176bc3c368 4928 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
mbed_official 31:42176bc3c368 4929
mbed_official 31:42176bc3c368 4930 /**
mbed_official 31:42176bc3c368 4931 * @}
mbed_official 31:42176bc3c368 4932 */ /* end of group TPM_Register_Masks */
mbed_official 31:42176bc3c368 4933
mbed_official 31:42176bc3c368 4934
mbed_official 31:42176bc3c368 4935 /* TPM - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 4936 /** Peripheral TPM0 base address */
mbed_official 31:42176bc3c368 4937 #define TPM0_BASE (0x40038000u)
mbed_official 31:42176bc3c368 4938 /** Peripheral TPM0 base pointer */
mbed_official 31:42176bc3c368 4939 #define TPM0 ((TPM_Type *)TPM0_BASE)
mbed_official 31:42176bc3c368 4940 /** Peripheral TPM1 base address */
mbed_official 31:42176bc3c368 4941 #define TPM1_BASE (0x40039000u)
mbed_official 31:42176bc3c368 4942 /** Peripheral TPM1 base pointer */
mbed_official 31:42176bc3c368 4943 #define TPM1 ((TPM_Type *)TPM1_BASE)
mbed_official 31:42176bc3c368 4944 /** Peripheral TPM2 base address */
mbed_official 31:42176bc3c368 4945 #define TPM2_BASE (0x4003A000u)
mbed_official 31:42176bc3c368 4946 /** Peripheral TPM2 base pointer */
mbed_official 31:42176bc3c368 4947 #define TPM2 ((TPM_Type *)TPM2_BASE)
mbed_official 31:42176bc3c368 4948 /** Array initializer of TPM peripheral base pointers */
mbed_official 31:42176bc3c368 4949 #define TPM_BASES { TPM0, TPM1, TPM2 }
mbed_official 31:42176bc3c368 4950
mbed_official 31:42176bc3c368 4951 /**
mbed_official 31:42176bc3c368 4952 * @}
mbed_official 31:42176bc3c368 4953 */ /* end of group TPM_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 4954
mbed_official 31:42176bc3c368 4955
mbed_official 31:42176bc3c368 4956 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4957 -- TSI Peripheral Access Layer
mbed_official 31:42176bc3c368 4958 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4959
mbed_official 31:42176bc3c368 4960 /**
mbed_official 31:42176bc3c368 4961 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
mbed_official 31:42176bc3c368 4962 * @{
mbed_official 31:42176bc3c368 4963 */
mbed_official 31:42176bc3c368 4964
mbed_official 31:42176bc3c368 4965 /** TSI - Register Layout Typedef */
mbed_official 31:42176bc3c368 4966 typedef struct {
mbed_official 31:42176bc3c368 4967 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
mbed_official 31:42176bc3c368 4968 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
mbed_official 31:42176bc3c368 4969 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
mbed_official 31:42176bc3c368 4970 } TSI_Type;
mbed_official 31:42176bc3c368 4971
mbed_official 31:42176bc3c368 4972 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 4973 -- TSI Register Masks
mbed_official 31:42176bc3c368 4974 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 4975
mbed_official 31:42176bc3c368 4976 /**
mbed_official 31:42176bc3c368 4977 * @addtogroup TSI_Register_Masks TSI Register Masks
mbed_official 31:42176bc3c368 4978 * @{
mbed_official 31:42176bc3c368 4979 */
mbed_official 31:42176bc3c368 4980
mbed_official 31:42176bc3c368 4981 /* GENCS Bit Fields */
mbed_official 31:42176bc3c368 4982 #define TSI_GENCS_CURSW_MASK 0x2u
mbed_official 31:42176bc3c368 4983 #define TSI_GENCS_CURSW_SHIFT 1
mbed_official 31:42176bc3c368 4984 #define TSI_GENCS_EOSF_MASK 0x4u
mbed_official 31:42176bc3c368 4985 #define TSI_GENCS_EOSF_SHIFT 2
mbed_official 31:42176bc3c368 4986 #define TSI_GENCS_SCNIP_MASK 0x8u
mbed_official 31:42176bc3c368 4987 #define TSI_GENCS_SCNIP_SHIFT 3
mbed_official 31:42176bc3c368 4988 #define TSI_GENCS_STM_MASK 0x10u
mbed_official 31:42176bc3c368 4989 #define TSI_GENCS_STM_SHIFT 4
mbed_official 31:42176bc3c368 4990 #define TSI_GENCS_STPE_MASK 0x20u
mbed_official 31:42176bc3c368 4991 #define TSI_GENCS_STPE_SHIFT 5
mbed_official 31:42176bc3c368 4992 #define TSI_GENCS_TSIIEN_MASK 0x40u
mbed_official 31:42176bc3c368 4993 #define TSI_GENCS_TSIIEN_SHIFT 6
mbed_official 31:42176bc3c368 4994 #define TSI_GENCS_TSIEN_MASK 0x80u
mbed_official 31:42176bc3c368 4995 #define TSI_GENCS_TSIEN_SHIFT 7
mbed_official 31:42176bc3c368 4996 #define TSI_GENCS_NSCN_MASK 0x1F00u
mbed_official 31:42176bc3c368 4997 #define TSI_GENCS_NSCN_SHIFT 8
mbed_official 31:42176bc3c368 4998 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
mbed_official 31:42176bc3c368 4999 #define TSI_GENCS_PS_MASK 0xE000u
mbed_official 31:42176bc3c368 5000 #define TSI_GENCS_PS_SHIFT 13
mbed_official 31:42176bc3c368 5001 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
mbed_official 31:42176bc3c368 5002 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
mbed_official 31:42176bc3c368 5003 #define TSI_GENCS_EXTCHRG_SHIFT 16
mbed_official 31:42176bc3c368 5004 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
mbed_official 31:42176bc3c368 5005 #define TSI_GENCS_DVOLT_MASK 0x180000u
mbed_official 31:42176bc3c368 5006 #define TSI_GENCS_DVOLT_SHIFT 19
mbed_official 31:42176bc3c368 5007 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
mbed_official 31:42176bc3c368 5008 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
mbed_official 31:42176bc3c368 5009 #define TSI_GENCS_REFCHRG_SHIFT 21
mbed_official 31:42176bc3c368 5010 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
mbed_official 31:42176bc3c368 5011 #define TSI_GENCS_MODE_MASK 0xF000000u
mbed_official 31:42176bc3c368 5012 #define TSI_GENCS_MODE_SHIFT 24
mbed_official 31:42176bc3c368 5013 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
mbed_official 31:42176bc3c368 5014 #define TSI_GENCS_ESOR_MASK 0x10000000u
mbed_official 31:42176bc3c368 5015 #define TSI_GENCS_ESOR_SHIFT 28
mbed_official 31:42176bc3c368 5016 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
mbed_official 31:42176bc3c368 5017 #define TSI_GENCS_OUTRGF_SHIFT 31
mbed_official 31:42176bc3c368 5018 /* DATA Bit Fields */
mbed_official 31:42176bc3c368 5019 #define TSI_DATA_TSICNT_MASK 0xFFFFu
mbed_official 31:42176bc3c368 5020 #define TSI_DATA_TSICNT_SHIFT 0
mbed_official 31:42176bc3c368 5021 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
mbed_official 31:42176bc3c368 5022 #define TSI_DATA_SWTS_MASK 0x400000u
mbed_official 31:42176bc3c368 5023 #define TSI_DATA_SWTS_SHIFT 22
mbed_official 31:42176bc3c368 5024 #define TSI_DATA_DMAEN_MASK 0x800000u
mbed_official 31:42176bc3c368 5025 #define TSI_DATA_DMAEN_SHIFT 23
mbed_official 31:42176bc3c368 5026 #define TSI_DATA_TSICH_MASK 0xF0000000u
mbed_official 31:42176bc3c368 5027 #define TSI_DATA_TSICH_SHIFT 28
mbed_official 31:42176bc3c368 5028 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
mbed_official 31:42176bc3c368 5029 /* TSHD Bit Fields */
mbed_official 31:42176bc3c368 5030 #define TSI_TSHD_THRESL_MASK 0xFFFFu
mbed_official 31:42176bc3c368 5031 #define TSI_TSHD_THRESL_SHIFT 0
mbed_official 31:42176bc3c368 5032 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
mbed_official 31:42176bc3c368 5033 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
mbed_official 31:42176bc3c368 5034 #define TSI_TSHD_THRESH_SHIFT 16
mbed_official 31:42176bc3c368 5035 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
mbed_official 31:42176bc3c368 5036
mbed_official 31:42176bc3c368 5037 /**
mbed_official 31:42176bc3c368 5038 * @}
mbed_official 31:42176bc3c368 5039 */ /* end of group TSI_Register_Masks */
mbed_official 31:42176bc3c368 5040
mbed_official 31:42176bc3c368 5041
mbed_official 31:42176bc3c368 5042 /* TSI - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 5043 /** Peripheral TSI0 base address */
mbed_official 31:42176bc3c368 5044 #define TSI0_BASE (0x40045000u)
mbed_official 31:42176bc3c368 5045 /** Peripheral TSI0 base pointer */
mbed_official 31:42176bc3c368 5046 #define TSI0 ((TSI_Type *)TSI0_BASE)
mbed_official 31:42176bc3c368 5047 /** Array initializer of TSI peripheral base pointers */
mbed_official 31:42176bc3c368 5048 #define TSI_BASES { TSI0 }
mbed_official 31:42176bc3c368 5049
mbed_official 31:42176bc3c368 5050 /**
mbed_official 31:42176bc3c368 5051 * @}
mbed_official 31:42176bc3c368 5052 */ /* end of group TSI_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 5053
mbed_official 31:42176bc3c368 5054
mbed_official 31:42176bc3c368 5055 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 5056 -- UART Peripheral Access Layer
mbed_official 31:42176bc3c368 5057 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5058
mbed_official 31:42176bc3c368 5059 /**
mbed_official 31:42176bc3c368 5060 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 31:42176bc3c368 5061 * @{
mbed_official 31:42176bc3c368 5062 */
mbed_official 31:42176bc3c368 5063
mbed_official 31:42176bc3c368 5064 /** UART - Register Layout Typedef */
mbed_official 31:42176bc3c368 5065 typedef struct {
mbed_official 31:42176bc3c368 5066 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
mbed_official 31:42176bc3c368 5067 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
mbed_official 31:42176bc3c368 5068 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 31:42176bc3c368 5069 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 31:42176bc3c368 5070 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 31:42176bc3c368 5071 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 31:42176bc3c368 5072 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 31:42176bc3c368 5073 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 31:42176bc3c368 5074 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
mbed_official 31:42176bc3c368 5075 } UART_Type;
mbed_official 31:42176bc3c368 5076
mbed_official 31:42176bc3c368 5077 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 5078 -- UART Register Masks
mbed_official 31:42176bc3c368 5079 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5080
mbed_official 31:42176bc3c368 5081 /**
mbed_official 31:42176bc3c368 5082 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 31:42176bc3c368 5083 * @{
mbed_official 31:42176bc3c368 5084 */
mbed_official 31:42176bc3c368 5085
mbed_official 31:42176bc3c368 5086 /* BDH Bit Fields */
mbed_official 31:42176bc3c368 5087 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 31:42176bc3c368 5088 #define UART_BDH_SBR_SHIFT 0
mbed_official 31:42176bc3c368 5089 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 31:42176bc3c368 5090 #define UART_BDH_SBNS_MASK 0x20u
mbed_official 31:42176bc3c368 5091 #define UART_BDH_SBNS_SHIFT 5
mbed_official 31:42176bc3c368 5092 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 31:42176bc3c368 5093 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 31:42176bc3c368 5094 #define UART_BDH_LBKDIE_MASK 0x80u
mbed_official 31:42176bc3c368 5095 #define UART_BDH_LBKDIE_SHIFT 7
mbed_official 31:42176bc3c368 5096 /* BDL Bit Fields */
mbed_official 31:42176bc3c368 5097 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 31:42176bc3c368 5098 #define UART_BDL_SBR_SHIFT 0
mbed_official 31:42176bc3c368 5099 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 31:42176bc3c368 5100 /* C1 Bit Fields */
mbed_official 31:42176bc3c368 5101 #define UART_C1_PT_MASK 0x1u
mbed_official 31:42176bc3c368 5102 #define UART_C1_PT_SHIFT 0
mbed_official 31:42176bc3c368 5103 #define UART_C1_PE_MASK 0x2u
mbed_official 31:42176bc3c368 5104 #define UART_C1_PE_SHIFT 1
mbed_official 31:42176bc3c368 5105 #define UART_C1_ILT_MASK 0x4u
mbed_official 31:42176bc3c368 5106 #define UART_C1_ILT_SHIFT 2
mbed_official 31:42176bc3c368 5107 #define UART_C1_WAKE_MASK 0x8u
mbed_official 31:42176bc3c368 5108 #define UART_C1_WAKE_SHIFT 3
mbed_official 31:42176bc3c368 5109 #define UART_C1_M_MASK 0x10u
mbed_official 31:42176bc3c368 5110 #define UART_C1_M_SHIFT 4
mbed_official 31:42176bc3c368 5111 #define UART_C1_RSRC_MASK 0x20u
mbed_official 31:42176bc3c368 5112 #define UART_C1_RSRC_SHIFT 5
mbed_official 31:42176bc3c368 5113 #define UART_C1_UARTSWAI_MASK 0x40u
mbed_official 31:42176bc3c368 5114 #define UART_C1_UARTSWAI_SHIFT 6
mbed_official 31:42176bc3c368 5115 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 31:42176bc3c368 5116 #define UART_C1_LOOPS_SHIFT 7
mbed_official 31:42176bc3c368 5117 /* C2 Bit Fields */
mbed_official 31:42176bc3c368 5118 #define UART_C2_SBK_MASK 0x1u
mbed_official 31:42176bc3c368 5119 #define UART_C2_SBK_SHIFT 0
mbed_official 31:42176bc3c368 5120 #define UART_C2_RWU_MASK 0x2u
mbed_official 31:42176bc3c368 5121 #define UART_C2_RWU_SHIFT 1
mbed_official 31:42176bc3c368 5122 #define UART_C2_RE_MASK 0x4u
mbed_official 31:42176bc3c368 5123 #define UART_C2_RE_SHIFT 2
mbed_official 31:42176bc3c368 5124 #define UART_C2_TE_MASK 0x8u
mbed_official 31:42176bc3c368 5125 #define UART_C2_TE_SHIFT 3
mbed_official 31:42176bc3c368 5126 #define UART_C2_ILIE_MASK 0x10u
mbed_official 31:42176bc3c368 5127 #define UART_C2_ILIE_SHIFT 4
mbed_official 31:42176bc3c368 5128 #define UART_C2_RIE_MASK 0x20u
mbed_official 31:42176bc3c368 5129 #define UART_C2_RIE_SHIFT 5
mbed_official 31:42176bc3c368 5130 #define UART_C2_TCIE_MASK 0x40u
mbed_official 31:42176bc3c368 5131 #define UART_C2_TCIE_SHIFT 6
mbed_official 31:42176bc3c368 5132 #define UART_C2_TIE_MASK 0x80u
mbed_official 31:42176bc3c368 5133 #define UART_C2_TIE_SHIFT 7
mbed_official 31:42176bc3c368 5134 /* S1 Bit Fields */
mbed_official 31:42176bc3c368 5135 #define UART_S1_PF_MASK 0x1u
mbed_official 31:42176bc3c368 5136 #define UART_S1_PF_SHIFT 0
mbed_official 31:42176bc3c368 5137 #define UART_S1_FE_MASK 0x2u
mbed_official 31:42176bc3c368 5138 #define UART_S1_FE_SHIFT 1
mbed_official 31:42176bc3c368 5139 #define UART_S1_NF_MASK 0x4u
mbed_official 31:42176bc3c368 5140 #define UART_S1_NF_SHIFT 2
mbed_official 31:42176bc3c368 5141 #define UART_S1_OR_MASK 0x8u
mbed_official 31:42176bc3c368 5142 #define UART_S1_OR_SHIFT 3
mbed_official 31:42176bc3c368 5143 #define UART_S1_IDLE_MASK 0x10u
mbed_official 31:42176bc3c368 5144 #define UART_S1_IDLE_SHIFT 4
mbed_official 31:42176bc3c368 5145 #define UART_S1_RDRF_MASK 0x20u
mbed_official 31:42176bc3c368 5146 #define UART_S1_RDRF_SHIFT 5
mbed_official 31:42176bc3c368 5147 #define UART_S1_TC_MASK 0x40u
mbed_official 31:42176bc3c368 5148 #define UART_S1_TC_SHIFT 6
mbed_official 31:42176bc3c368 5149 #define UART_S1_TDRE_MASK 0x80u
mbed_official 31:42176bc3c368 5150 #define UART_S1_TDRE_SHIFT 7
mbed_official 31:42176bc3c368 5151 /* S2 Bit Fields */
mbed_official 31:42176bc3c368 5152 #define UART_S2_RAF_MASK 0x1u
mbed_official 31:42176bc3c368 5153 #define UART_S2_RAF_SHIFT 0
mbed_official 31:42176bc3c368 5154 #define UART_S2_LBKDE_MASK 0x2u
mbed_official 31:42176bc3c368 5155 #define UART_S2_LBKDE_SHIFT 1
mbed_official 31:42176bc3c368 5156 #define UART_S2_BRK13_MASK 0x4u
mbed_official 31:42176bc3c368 5157 #define UART_S2_BRK13_SHIFT 2
mbed_official 31:42176bc3c368 5158 #define UART_S2_RWUID_MASK 0x8u
mbed_official 31:42176bc3c368 5159 #define UART_S2_RWUID_SHIFT 3
mbed_official 31:42176bc3c368 5160 #define UART_S2_RXINV_MASK 0x10u
mbed_official 31:42176bc3c368 5161 #define UART_S2_RXINV_SHIFT 4
mbed_official 31:42176bc3c368 5162 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 31:42176bc3c368 5163 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 31:42176bc3c368 5164 #define UART_S2_LBKDIF_MASK 0x80u
mbed_official 31:42176bc3c368 5165 #define UART_S2_LBKDIF_SHIFT 7
mbed_official 31:42176bc3c368 5166 /* C3 Bit Fields */
mbed_official 31:42176bc3c368 5167 #define UART_C3_PEIE_MASK 0x1u
mbed_official 31:42176bc3c368 5168 #define UART_C3_PEIE_SHIFT 0
mbed_official 31:42176bc3c368 5169 #define UART_C3_FEIE_MASK 0x2u
mbed_official 31:42176bc3c368 5170 #define UART_C3_FEIE_SHIFT 1
mbed_official 31:42176bc3c368 5171 #define UART_C3_NEIE_MASK 0x4u
mbed_official 31:42176bc3c368 5172 #define UART_C3_NEIE_SHIFT 2
mbed_official 31:42176bc3c368 5173 #define UART_C3_ORIE_MASK 0x8u
mbed_official 31:42176bc3c368 5174 #define UART_C3_ORIE_SHIFT 3
mbed_official 31:42176bc3c368 5175 #define UART_C3_TXINV_MASK 0x10u
mbed_official 31:42176bc3c368 5176 #define UART_C3_TXINV_SHIFT 4
mbed_official 31:42176bc3c368 5177 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 31:42176bc3c368 5178 #define UART_C3_TXDIR_SHIFT 5
mbed_official 31:42176bc3c368 5179 #define UART_C3_T8_MASK 0x40u
mbed_official 31:42176bc3c368 5180 #define UART_C3_T8_SHIFT 6
mbed_official 31:42176bc3c368 5181 #define UART_C3_R8_MASK 0x80u
mbed_official 31:42176bc3c368 5182 #define UART_C3_R8_SHIFT 7
mbed_official 31:42176bc3c368 5183 /* D Bit Fields */
mbed_official 31:42176bc3c368 5184 #define UART_D_R0T0_MASK 0x1u
mbed_official 31:42176bc3c368 5185 #define UART_D_R0T0_SHIFT 0
mbed_official 31:42176bc3c368 5186 #define UART_D_R1T1_MASK 0x2u
mbed_official 31:42176bc3c368 5187 #define UART_D_R1T1_SHIFT 1
mbed_official 31:42176bc3c368 5188 #define UART_D_R2T2_MASK 0x4u
mbed_official 31:42176bc3c368 5189 #define UART_D_R2T2_SHIFT 2
mbed_official 31:42176bc3c368 5190 #define UART_D_R3T3_MASK 0x8u
mbed_official 31:42176bc3c368 5191 #define UART_D_R3T3_SHIFT 3
mbed_official 31:42176bc3c368 5192 #define UART_D_R4T4_MASK 0x10u
mbed_official 31:42176bc3c368 5193 #define UART_D_R4T4_SHIFT 4
mbed_official 31:42176bc3c368 5194 #define UART_D_R5T5_MASK 0x20u
mbed_official 31:42176bc3c368 5195 #define UART_D_R5T5_SHIFT 5
mbed_official 31:42176bc3c368 5196 #define UART_D_R6T6_MASK 0x40u
mbed_official 31:42176bc3c368 5197 #define UART_D_R6T6_SHIFT 6
mbed_official 31:42176bc3c368 5198 #define UART_D_R7T7_MASK 0x80u
mbed_official 31:42176bc3c368 5199 #define UART_D_R7T7_SHIFT 7
mbed_official 31:42176bc3c368 5200 /* C4 Bit Fields */
mbed_official 31:42176bc3c368 5201 #define UART_C4_RDMAS_MASK 0x20u
mbed_official 31:42176bc3c368 5202 #define UART_C4_RDMAS_SHIFT 5
mbed_official 31:42176bc3c368 5203 #define UART_C4_TDMAS_MASK 0x80u
mbed_official 31:42176bc3c368 5204 #define UART_C4_TDMAS_SHIFT 7
mbed_official 31:42176bc3c368 5205
mbed_official 31:42176bc3c368 5206 /**
mbed_official 31:42176bc3c368 5207 * @}
mbed_official 31:42176bc3c368 5208 */ /* end of group UART_Register_Masks */
mbed_official 31:42176bc3c368 5209
mbed_official 31:42176bc3c368 5210
mbed_official 31:42176bc3c368 5211 /* UART - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 5212 /** Peripheral UART1 base address */
mbed_official 31:42176bc3c368 5213 #define UART1_BASE (0x4006B000u)
mbed_official 31:42176bc3c368 5214 /** Peripheral UART1 base pointer */
mbed_official 31:42176bc3c368 5215 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 31:42176bc3c368 5216 /** Peripheral UART2 base address */
mbed_official 31:42176bc3c368 5217 #define UART2_BASE (0x4006C000u)
mbed_official 31:42176bc3c368 5218 /** Peripheral UART2 base pointer */
mbed_official 31:42176bc3c368 5219 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 31:42176bc3c368 5220 /** Array initializer of UART peripheral base pointers */
mbed_official 31:42176bc3c368 5221 #define UART_BASES { UART1, UART2 }
mbed_official 31:42176bc3c368 5222
mbed_official 31:42176bc3c368 5223 /**
mbed_official 31:42176bc3c368 5224 * @}
mbed_official 31:42176bc3c368 5225 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 5226
mbed_official 31:42176bc3c368 5227
mbed_official 31:42176bc3c368 5228 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 5229 -- UART0 Peripheral Access Layer
mbed_official 31:42176bc3c368 5230 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5231
mbed_official 31:42176bc3c368 5232 /**
mbed_official 44:2ce89a25b635 5233 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
mbed_official 31:42176bc3c368 5234 * @{
mbed_official 31:42176bc3c368 5235 */
mbed_official 31:42176bc3c368 5236
mbed_official 44:2ce89a25b635 5237 /** UART0 - Register Layout Typedef */
mbed_official 31:42176bc3c368 5238 typedef struct {
mbed_official 31:42176bc3c368 5239 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
mbed_official 31:42176bc3c368 5240 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
mbed_official 31:42176bc3c368 5241 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 31:42176bc3c368 5242 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 31:42176bc3c368 5243 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 31:42176bc3c368 5244 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 31:42176bc3c368 5245 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 31:42176bc3c368 5246 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 31:42176bc3c368 5247 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 31:42176bc3c368 5248 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 31:42176bc3c368 5249 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 31:42176bc3c368 5250 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 44:2ce89a25b635 5251 } UART0_Type;
mbed_official 31:42176bc3c368 5252
mbed_official 31:42176bc3c368 5253 /* ----------------------------------------------------------------------------
mbed_official 44:2ce89a25b635 5254 -- UART0 Register Masks
mbed_official 31:42176bc3c368 5255 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5256
mbed_official 31:42176bc3c368 5257 /**
mbed_official 44:2ce89a25b635 5258 * @addtogroup UART0_Register_Masks UART0 Register Masks
mbed_official 31:42176bc3c368 5259 * @{
mbed_official 31:42176bc3c368 5260 */
mbed_official 31:42176bc3c368 5261
mbed_official 31:42176bc3c368 5262 /* BDH Bit Fields */
mbed_official 44:2ce89a25b635 5263 #define UART0_BDH_SBR_MASK 0x1Fu
mbed_official 44:2ce89a25b635 5264 #define UART0_BDH_SBR_SHIFT 0
mbed_official 44:2ce89a25b635 5265 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
mbed_official 44:2ce89a25b635 5266 #define UART0_BDH_SBNS_MASK 0x20u
mbed_official 44:2ce89a25b635 5267 #define UART0_BDH_SBNS_SHIFT 5
mbed_official 44:2ce89a25b635 5268 #define UART0_BDH_RXEDGIE_MASK 0x40u
mbed_official 44:2ce89a25b635 5269 #define UART0_BDH_RXEDGIE_SHIFT 6
mbed_official 44:2ce89a25b635 5270 #define UART0_BDH_LBKDIE_MASK 0x80u
mbed_official 44:2ce89a25b635 5271 #define UART0_BDH_LBKDIE_SHIFT 7
mbed_official 31:42176bc3c368 5272 /* BDL Bit Fields */
mbed_official 44:2ce89a25b635 5273 #define UART0_BDL_SBR_MASK 0xFFu
mbed_official 44:2ce89a25b635 5274 #define UART0_BDL_SBR_SHIFT 0
mbed_official 44:2ce89a25b635 5275 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
mbed_official 31:42176bc3c368 5276 /* C1 Bit Fields */
mbed_official 44:2ce89a25b635 5277 #define UART0_C1_PT_MASK 0x1u
mbed_official 44:2ce89a25b635 5278 #define UART0_C1_PT_SHIFT 0
mbed_official 44:2ce89a25b635 5279 #define UART0_C1_PE_MASK 0x2u
mbed_official 44:2ce89a25b635 5280 #define UART0_C1_PE_SHIFT 1
mbed_official 44:2ce89a25b635 5281 #define UART0_C1_ILT_MASK 0x4u
mbed_official 44:2ce89a25b635 5282 #define UART0_C1_ILT_SHIFT 2
mbed_official 44:2ce89a25b635 5283 #define UART0_C1_WAKE_MASK 0x8u
mbed_official 44:2ce89a25b635 5284 #define UART0_C1_WAKE_SHIFT 3
mbed_official 44:2ce89a25b635 5285 #define UART0_C1_M_MASK 0x10u
mbed_official 44:2ce89a25b635 5286 #define UART0_C1_M_SHIFT 4
mbed_official 44:2ce89a25b635 5287 #define UART0_C1_RSRC_MASK 0x20u
mbed_official 44:2ce89a25b635 5288 #define UART0_C1_RSRC_SHIFT 5
mbed_official 44:2ce89a25b635 5289 #define UART0_C1_DOZEEN_MASK 0x40u
mbed_official 44:2ce89a25b635 5290 #define UART0_C1_DOZEEN_SHIFT 6
mbed_official 44:2ce89a25b635 5291 #define UART0_C1_LOOPS_MASK 0x80u
mbed_official 44:2ce89a25b635 5292 #define UART0_C1_LOOPS_SHIFT 7
mbed_official 31:42176bc3c368 5293 /* C2 Bit Fields */
mbed_official 44:2ce89a25b635 5294 #define UART0_C2_SBK_MASK 0x1u
mbed_official 44:2ce89a25b635 5295 #define UART0_C2_SBK_SHIFT 0
mbed_official 44:2ce89a25b635 5296 #define UART0_C2_RWU_MASK 0x2u
mbed_official 44:2ce89a25b635 5297 #define UART0_C2_RWU_SHIFT 1
mbed_official 44:2ce89a25b635 5298 #define UART0_C2_RE_MASK 0x4u
mbed_official 44:2ce89a25b635 5299 #define UART0_C2_RE_SHIFT 2
mbed_official 44:2ce89a25b635 5300 #define UART0_C2_TE_MASK 0x8u
mbed_official 44:2ce89a25b635 5301 #define UART0_C2_TE_SHIFT 3
mbed_official 44:2ce89a25b635 5302 #define UART0_C2_ILIE_MASK 0x10u
mbed_official 44:2ce89a25b635 5303 #define UART0_C2_ILIE_SHIFT 4
mbed_official 44:2ce89a25b635 5304 #define UART0_C2_RIE_MASK 0x20u
mbed_official 44:2ce89a25b635 5305 #define UART0_C2_RIE_SHIFT 5
mbed_official 44:2ce89a25b635 5306 #define UART0_C2_TCIE_MASK 0x40u
mbed_official 44:2ce89a25b635 5307 #define UART0_C2_TCIE_SHIFT 6
mbed_official 44:2ce89a25b635 5308 #define UART0_C2_TIE_MASK 0x80u
mbed_official 44:2ce89a25b635 5309 #define UART0_C2_TIE_SHIFT 7
mbed_official 31:42176bc3c368 5310 /* S1 Bit Fields */
mbed_official 44:2ce89a25b635 5311 #define UART0_S1_PF_MASK 0x1u
mbed_official 44:2ce89a25b635 5312 #define UART0_S1_PF_SHIFT 0
mbed_official 44:2ce89a25b635 5313 #define UART0_S1_FE_MASK 0x2u
mbed_official 44:2ce89a25b635 5314 #define UART0_S1_FE_SHIFT 1
mbed_official 44:2ce89a25b635 5315 #define UART0_S1_NF_MASK 0x4u
mbed_official 44:2ce89a25b635 5316 #define UART0_S1_NF_SHIFT 2
mbed_official 44:2ce89a25b635 5317 #define UART0_S1_OR_MASK 0x8u
mbed_official 44:2ce89a25b635 5318 #define UART0_S1_OR_SHIFT 3
mbed_official 44:2ce89a25b635 5319 #define UART0_S1_IDLE_MASK 0x10u
mbed_official 44:2ce89a25b635 5320 #define UART0_S1_IDLE_SHIFT 4
mbed_official 44:2ce89a25b635 5321 #define UART0_S1_RDRF_MASK 0x20u
mbed_official 44:2ce89a25b635 5322 #define UART0_S1_RDRF_SHIFT 5
mbed_official 44:2ce89a25b635 5323 #define UART0_S1_TC_MASK 0x40u
mbed_official 44:2ce89a25b635 5324 #define UART0_S1_TC_SHIFT 6
mbed_official 44:2ce89a25b635 5325 #define UART0_S1_TDRE_MASK 0x80u
mbed_official 44:2ce89a25b635 5326 #define UART0_S1_TDRE_SHIFT 7
mbed_official 31:42176bc3c368 5327 /* S2 Bit Fields */
mbed_official 44:2ce89a25b635 5328 #define UART0_S2_RAF_MASK 0x1u
mbed_official 44:2ce89a25b635 5329 #define UART0_S2_RAF_SHIFT 0
mbed_official 44:2ce89a25b635 5330 #define UART0_S2_LBKDE_MASK 0x2u
mbed_official 44:2ce89a25b635 5331 #define UART0_S2_LBKDE_SHIFT 1
mbed_official 44:2ce89a25b635 5332 #define UART0_S2_BRK13_MASK 0x4u
mbed_official 44:2ce89a25b635 5333 #define UART0_S2_BRK13_SHIFT 2
mbed_official 44:2ce89a25b635 5334 #define UART0_S2_RWUID_MASK 0x8u
mbed_official 44:2ce89a25b635 5335 #define UART0_S2_RWUID_SHIFT 3
mbed_official 44:2ce89a25b635 5336 #define UART0_S2_RXINV_MASK 0x10u
mbed_official 44:2ce89a25b635 5337 #define UART0_S2_RXINV_SHIFT 4
mbed_official 44:2ce89a25b635 5338 #define UART0_S2_MSBF_MASK 0x20u
mbed_official 44:2ce89a25b635 5339 #define UART0_S2_MSBF_SHIFT 5
mbed_official 44:2ce89a25b635 5340 #define UART0_S2_RXEDGIF_MASK 0x40u
mbed_official 44:2ce89a25b635 5341 #define UART0_S2_RXEDGIF_SHIFT 6
mbed_official 44:2ce89a25b635 5342 #define UART0_S2_LBKDIF_MASK 0x80u
mbed_official 44:2ce89a25b635 5343 #define UART0_S2_LBKDIF_SHIFT 7
mbed_official 31:42176bc3c368 5344 /* C3 Bit Fields */
mbed_official 44:2ce89a25b635 5345 #define UART0_C3_PEIE_MASK 0x1u
mbed_official 44:2ce89a25b635 5346 #define UART0_C3_PEIE_SHIFT 0
mbed_official 44:2ce89a25b635 5347 #define UART0_C3_FEIE_MASK 0x2u
mbed_official 44:2ce89a25b635 5348 #define UART0_C3_FEIE_SHIFT 1
mbed_official 44:2ce89a25b635 5349 #define UART0_C3_NEIE_MASK 0x4u
mbed_official 44:2ce89a25b635 5350 #define UART0_C3_NEIE_SHIFT 2
mbed_official 44:2ce89a25b635 5351 #define UART0_C3_ORIE_MASK 0x8u
mbed_official 44:2ce89a25b635 5352 #define UART0_C3_ORIE_SHIFT 3
mbed_official 44:2ce89a25b635 5353 #define UART0_C3_TXINV_MASK 0x10u
mbed_official 44:2ce89a25b635 5354 #define UART0_C3_TXINV_SHIFT 4
mbed_official 44:2ce89a25b635 5355 #define UART0_C3_TXDIR_MASK 0x20u
mbed_official 44:2ce89a25b635 5356 #define UART0_C3_TXDIR_SHIFT 5
mbed_official 44:2ce89a25b635 5357 #define UART0_C3_R9T8_MASK 0x40u
mbed_official 44:2ce89a25b635 5358 #define UART0_C3_R9T8_SHIFT 6
mbed_official 44:2ce89a25b635 5359 #define UART0_C3_R8T9_MASK 0x80u
mbed_official 44:2ce89a25b635 5360 #define UART0_C3_R8T9_SHIFT 7
mbed_official 31:42176bc3c368 5361 /* D Bit Fields */
mbed_official 44:2ce89a25b635 5362 #define UART0_D_R0T0_MASK 0x1u
mbed_official 44:2ce89a25b635 5363 #define UART0_D_R0T0_SHIFT 0
mbed_official 44:2ce89a25b635 5364 #define UART0_D_R1T1_MASK 0x2u
mbed_official 44:2ce89a25b635 5365 #define UART0_D_R1T1_SHIFT 1
mbed_official 44:2ce89a25b635 5366 #define UART0_D_R2T2_MASK 0x4u
mbed_official 44:2ce89a25b635 5367 #define UART0_D_R2T2_SHIFT 2
mbed_official 44:2ce89a25b635 5368 #define UART0_D_R3T3_MASK 0x8u
mbed_official 44:2ce89a25b635 5369 #define UART0_D_R3T3_SHIFT 3
mbed_official 44:2ce89a25b635 5370 #define UART0_D_R4T4_MASK 0x10u
mbed_official 44:2ce89a25b635 5371 #define UART0_D_R4T4_SHIFT 4
mbed_official 44:2ce89a25b635 5372 #define UART0_D_R5T5_MASK 0x20u
mbed_official 44:2ce89a25b635 5373 #define UART0_D_R5T5_SHIFT 5
mbed_official 44:2ce89a25b635 5374 #define UART0_D_R6T6_MASK 0x40u
mbed_official 44:2ce89a25b635 5375 #define UART0_D_R6T6_SHIFT 6
mbed_official 44:2ce89a25b635 5376 #define UART0_D_R7T7_MASK 0x80u
mbed_official 44:2ce89a25b635 5377 #define UART0_D_R7T7_SHIFT 7
mbed_official 31:42176bc3c368 5378 /* MA1 Bit Fields */
mbed_official 44:2ce89a25b635 5379 #define UART0_MA1_MA_MASK 0xFFu
mbed_official 44:2ce89a25b635 5380 #define UART0_MA1_MA_SHIFT 0
mbed_official 44:2ce89a25b635 5381 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
mbed_official 31:42176bc3c368 5382 /* MA2 Bit Fields */
mbed_official 44:2ce89a25b635 5383 #define UART0_MA2_MA_MASK 0xFFu
mbed_official 44:2ce89a25b635 5384 #define UART0_MA2_MA_SHIFT 0
mbed_official 44:2ce89a25b635 5385 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
mbed_official 31:42176bc3c368 5386 /* C4 Bit Fields */
mbed_official 44:2ce89a25b635 5387 #define UART0_C4_OSR_MASK 0x1Fu
mbed_official 44:2ce89a25b635 5388 #define UART0_C4_OSR_SHIFT 0
mbed_official 44:2ce89a25b635 5389 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
mbed_official 44:2ce89a25b635 5390 #define UART0_C4_M10_MASK 0x20u
mbed_official 44:2ce89a25b635 5391 #define UART0_C4_M10_SHIFT 5
mbed_official 44:2ce89a25b635 5392 #define UART0_C4_MAEN2_MASK 0x40u
mbed_official 44:2ce89a25b635 5393 #define UART0_C4_MAEN2_SHIFT 6
mbed_official 44:2ce89a25b635 5394 #define UART0_C4_MAEN1_MASK 0x80u
mbed_official 44:2ce89a25b635 5395 #define UART0_C4_MAEN1_SHIFT 7
mbed_official 31:42176bc3c368 5396 /* C5 Bit Fields */
mbed_official 44:2ce89a25b635 5397 #define UART0_C5_RESYNCDIS_MASK 0x1u
mbed_official 44:2ce89a25b635 5398 #define UART0_C5_RESYNCDIS_SHIFT 0
mbed_official 44:2ce89a25b635 5399 #define UART0_C5_BOTHEDGE_MASK 0x2u
mbed_official 44:2ce89a25b635 5400 #define UART0_C5_BOTHEDGE_SHIFT 1
mbed_official 44:2ce89a25b635 5401 #define UART0_C5_RDMAE_MASK 0x20u
mbed_official 44:2ce89a25b635 5402 #define UART0_C5_RDMAE_SHIFT 5
mbed_official 44:2ce89a25b635 5403 #define UART0_C5_TDMAE_MASK 0x80u
mbed_official 44:2ce89a25b635 5404 #define UART0_C5_TDMAE_SHIFT 7
mbed_official 31:42176bc3c368 5405
mbed_official 31:42176bc3c368 5406 /**
mbed_official 31:42176bc3c368 5407 * @}
mbed_official 44:2ce89a25b635 5408 */ /* end of group UART0_Register_Masks */
mbed_official 44:2ce89a25b635 5409
mbed_official 44:2ce89a25b635 5410
mbed_official 44:2ce89a25b635 5411 /* UART0 - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 5412 /** Peripheral UART0 base address */
mbed_official 31:42176bc3c368 5413 #define UART0_BASE (0x4006A000u)
mbed_official 31:42176bc3c368 5414 /** Peripheral UART0 base pointer */
mbed_official 44:2ce89a25b635 5415 #define UART0 ((UART0_Type *)UART0_BASE)
mbed_official 44:2ce89a25b635 5416 /** Array initializer of UART0 peripheral base pointers */
mbed_official 44:2ce89a25b635 5417 #define UART0_BASES { UART0 }
mbed_official 31:42176bc3c368 5418
mbed_official 31:42176bc3c368 5419 /**
mbed_official 31:42176bc3c368 5420 * @}
mbed_official 44:2ce89a25b635 5421 */ /* end of group UART0_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 5422
mbed_official 31:42176bc3c368 5423
mbed_official 31:42176bc3c368 5424 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 5425 -- USB Peripheral Access Layer
mbed_official 31:42176bc3c368 5426 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5427
mbed_official 31:42176bc3c368 5428 /**
mbed_official 31:42176bc3c368 5429 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 31:42176bc3c368 5430 * @{
mbed_official 31:42176bc3c368 5431 */
mbed_official 31:42176bc3c368 5432
mbed_official 31:42176bc3c368 5433 /** USB - Register Layout Typedef */
mbed_official 31:42176bc3c368 5434 typedef struct {
mbed_official 31:42176bc3c368 5435 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 31:42176bc3c368 5436 uint8_t RESERVED_0[3];
mbed_official 31:42176bc3c368 5437 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 31:42176bc3c368 5438 uint8_t RESERVED_1[3];
mbed_official 31:42176bc3c368 5439 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 31:42176bc3c368 5440 uint8_t RESERVED_2[3];
mbed_official 31:42176bc3c368 5441 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 31:42176bc3c368 5442 uint8_t RESERVED_3[3];
mbed_official 31:42176bc3c368 5443 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mbed_official 31:42176bc3c368 5444 uint8_t RESERVED_4[3];
mbed_official 31:42176bc3c368 5445 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
mbed_official 31:42176bc3c368 5446 uint8_t RESERVED_5[3];
mbed_official 31:42176bc3c368 5447 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mbed_official 31:42176bc3c368 5448 uint8_t RESERVED_6[3];
mbed_official 31:42176bc3c368 5449 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 31:42176bc3c368 5450 uint8_t RESERVED_7[99];
mbed_official 31:42176bc3c368 5451 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 31:42176bc3c368 5452 uint8_t RESERVED_8[3];
mbed_official 31:42176bc3c368 5453 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 31:42176bc3c368 5454 uint8_t RESERVED_9[3];
mbed_official 31:42176bc3c368 5455 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 31:42176bc3c368 5456 uint8_t RESERVED_10[3];
mbed_official 31:42176bc3c368 5457 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 31:42176bc3c368 5458 uint8_t RESERVED_11[3];
mbed_official 31:42176bc3c368 5459 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 31:42176bc3c368 5460 uint8_t RESERVED_12[3];
mbed_official 31:42176bc3c368 5461 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 31:42176bc3c368 5462 uint8_t RESERVED_13[3];
mbed_official 31:42176bc3c368 5463 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 31:42176bc3c368 5464 uint8_t RESERVED_14[3];
mbed_official 31:42176bc3c368 5465 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
mbed_official 31:42176bc3c368 5466 uint8_t RESERVED_15[3];
mbed_official 31:42176bc3c368 5467 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
mbed_official 31:42176bc3c368 5468 uint8_t RESERVED_16[3];
mbed_official 31:42176bc3c368 5469 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
mbed_official 31:42176bc3c368 5470 uint8_t RESERVED_17[3];
mbed_official 31:42176bc3c368 5471 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mbed_official 31:42176bc3c368 5472 uint8_t RESERVED_18[3];
mbed_official 31:42176bc3c368 5473 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
mbed_official 31:42176bc3c368 5474 uint8_t RESERVED_19[3];
mbed_official 31:42176bc3c368 5475 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 31:42176bc3c368 5476 uint8_t RESERVED_20[3];
mbed_official 31:42176bc3c368 5477 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 31:42176bc3c368 5478 uint8_t RESERVED_21[11];
mbed_official 31:42176bc3c368 5479 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 31:42176bc3c368 5480 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 31:42176bc3c368 5481 uint8_t RESERVED_0[3];
mbed_official 31:42176bc3c368 5482 } ENDPOINT[16];
mbed_official 31:42176bc3c368 5483 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 31:42176bc3c368 5484 uint8_t RESERVED_22[3];
mbed_official 31:42176bc3c368 5485 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 31:42176bc3c368 5486 uint8_t RESERVED_23[3];
mbed_official 31:42176bc3c368 5487 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 31:42176bc3c368 5488 uint8_t RESERVED_24[3];
mbed_official 31:42176bc3c368 5489 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
mbed_official 44:2ce89a25b635 5490 uint8_t RESERVED_25[7];
mbed_official 44:2ce89a25b635 5491 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 31:42176bc3c368 5492 } USB_Type;
mbed_official 31:42176bc3c368 5493
mbed_official 31:42176bc3c368 5494 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 5495 -- USB Register Masks
mbed_official 31:42176bc3c368 5496 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5497
mbed_official 31:42176bc3c368 5498 /**
mbed_official 31:42176bc3c368 5499 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 31:42176bc3c368 5500 * @{
mbed_official 31:42176bc3c368 5501 */
mbed_official 31:42176bc3c368 5502
mbed_official 31:42176bc3c368 5503 /* PERID Bit Fields */
mbed_official 31:42176bc3c368 5504 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 31:42176bc3c368 5505 #define USB_PERID_ID_SHIFT 0
mbed_official 31:42176bc3c368 5506 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 31:42176bc3c368 5507 /* IDCOMP Bit Fields */
mbed_official 31:42176bc3c368 5508 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 31:42176bc3c368 5509 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 31:42176bc3c368 5510 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 31:42176bc3c368 5511 /* REV Bit Fields */
mbed_official 31:42176bc3c368 5512 #define USB_REV_REV_MASK 0xFFu
mbed_official 31:42176bc3c368 5513 #define USB_REV_REV_SHIFT 0
mbed_official 31:42176bc3c368 5514 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 31:42176bc3c368 5515 /* ADDINFO Bit Fields */
mbed_official 31:42176bc3c368 5516 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 31:42176bc3c368 5517 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 31:42176bc3c368 5518 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
mbed_official 31:42176bc3c368 5519 #define USB_ADDINFO_IRQNUM_SHIFT 3
mbed_official 31:42176bc3c368 5520 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
mbed_official 31:42176bc3c368 5521 /* OTGISTAT Bit Fields */
mbed_official 31:42176bc3c368 5522 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mbed_official 31:42176bc3c368 5523 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mbed_official 31:42176bc3c368 5524 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mbed_official 31:42176bc3c368 5525 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mbed_official 31:42176bc3c368 5526 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mbed_official 31:42176bc3c368 5527 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mbed_official 31:42176bc3c368 5528 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mbed_official 31:42176bc3c368 5529 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mbed_official 31:42176bc3c368 5530 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mbed_official 31:42176bc3c368 5531 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mbed_official 31:42176bc3c368 5532 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mbed_official 31:42176bc3c368 5533 #define USB_OTGISTAT_IDCHG_SHIFT 7
mbed_official 31:42176bc3c368 5534 /* OTGICR Bit Fields */
mbed_official 31:42176bc3c368 5535 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mbed_official 31:42176bc3c368 5536 #define USB_OTGICR_AVBUSEN_SHIFT 0
mbed_official 31:42176bc3c368 5537 #define USB_OTGICR_BSESSEN_MASK 0x4u
mbed_official 31:42176bc3c368 5538 #define USB_OTGICR_BSESSEN_SHIFT 2
mbed_official 31:42176bc3c368 5539 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mbed_official 31:42176bc3c368 5540 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mbed_official 31:42176bc3c368 5541 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mbed_official 31:42176bc3c368 5542 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mbed_official 31:42176bc3c368 5543 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mbed_official 31:42176bc3c368 5544 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mbed_official 31:42176bc3c368 5545 #define USB_OTGICR_IDEN_MASK 0x80u
mbed_official 31:42176bc3c368 5546 #define USB_OTGICR_IDEN_SHIFT 7
mbed_official 31:42176bc3c368 5547 /* OTGSTAT Bit Fields */
mbed_official 31:42176bc3c368 5548 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mbed_official 31:42176bc3c368 5549 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mbed_official 31:42176bc3c368 5550 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mbed_official 31:42176bc3c368 5551 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mbed_official 31:42176bc3c368 5552 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mbed_official 31:42176bc3c368 5553 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mbed_official 31:42176bc3c368 5554 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mbed_official 31:42176bc3c368 5555 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mbed_official 31:42176bc3c368 5556 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mbed_official 31:42176bc3c368 5557 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mbed_official 31:42176bc3c368 5558 #define USB_OTGSTAT_ID_MASK 0x80u
mbed_official 31:42176bc3c368 5559 #define USB_OTGSTAT_ID_SHIFT 7
mbed_official 31:42176bc3c368 5560 /* OTGCTL Bit Fields */
mbed_official 31:42176bc3c368 5561 #define USB_OTGCTL_OTGEN_MASK 0x4u
mbed_official 31:42176bc3c368 5562 #define USB_OTGCTL_OTGEN_SHIFT 2
mbed_official 31:42176bc3c368 5563 #define USB_OTGCTL_DMLOW_MASK 0x10u
mbed_official 31:42176bc3c368 5564 #define USB_OTGCTL_DMLOW_SHIFT 4
mbed_official 31:42176bc3c368 5565 #define USB_OTGCTL_DPLOW_MASK 0x20u
mbed_official 31:42176bc3c368 5566 #define USB_OTGCTL_DPLOW_SHIFT 5
mbed_official 31:42176bc3c368 5567 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 31:42176bc3c368 5568 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 31:42176bc3c368 5569 /* ISTAT Bit Fields */
mbed_official 31:42176bc3c368 5570 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 31:42176bc3c368 5571 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 31:42176bc3c368 5572 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 31:42176bc3c368 5573 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 31:42176bc3c368 5574 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 31:42176bc3c368 5575 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 31:42176bc3c368 5576 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 31:42176bc3c368 5577 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 31:42176bc3c368 5578 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 31:42176bc3c368 5579 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 31:42176bc3c368 5580 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 31:42176bc3c368 5581 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 31:42176bc3c368 5582 #define USB_ISTAT_ATTACH_MASK 0x40u
mbed_official 31:42176bc3c368 5583 #define USB_ISTAT_ATTACH_SHIFT 6
mbed_official 31:42176bc3c368 5584 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 31:42176bc3c368 5585 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 31:42176bc3c368 5586 /* INTEN Bit Fields */
mbed_official 31:42176bc3c368 5587 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 31:42176bc3c368 5588 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 31:42176bc3c368 5589 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 31:42176bc3c368 5590 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 31:42176bc3c368 5591 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 31:42176bc3c368 5592 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 31:42176bc3c368 5593 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 31:42176bc3c368 5594 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 31:42176bc3c368 5595 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 31:42176bc3c368 5596 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 31:42176bc3c368 5597 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 31:42176bc3c368 5598 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 31:42176bc3c368 5599 #define USB_INTEN_ATTACHEN_MASK 0x40u
mbed_official 31:42176bc3c368 5600 #define USB_INTEN_ATTACHEN_SHIFT 6
mbed_official 31:42176bc3c368 5601 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 31:42176bc3c368 5602 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 31:42176bc3c368 5603 /* ERRSTAT Bit Fields */
mbed_official 31:42176bc3c368 5604 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 31:42176bc3c368 5605 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 31:42176bc3c368 5606 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mbed_official 31:42176bc3c368 5607 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mbed_official 31:42176bc3c368 5608 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 31:42176bc3c368 5609 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 31:42176bc3c368 5610 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 31:42176bc3c368 5611 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 31:42176bc3c368 5612 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 31:42176bc3c368 5613 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 31:42176bc3c368 5614 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 31:42176bc3c368 5615 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 31:42176bc3c368 5616 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 31:42176bc3c368 5617 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 31:42176bc3c368 5618 /* ERREN Bit Fields */
mbed_official 31:42176bc3c368 5619 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 31:42176bc3c368 5620 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 31:42176bc3c368 5621 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 31:42176bc3c368 5622 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 31:42176bc3c368 5623 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 31:42176bc3c368 5624 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 31:42176bc3c368 5625 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 31:42176bc3c368 5626 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 31:42176bc3c368 5627 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 31:42176bc3c368 5628 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 31:42176bc3c368 5629 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 31:42176bc3c368 5630 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 31:42176bc3c368 5631 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 31:42176bc3c368 5632 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 31:42176bc3c368 5633 /* STAT Bit Fields */
mbed_official 31:42176bc3c368 5634 #define USB_STAT_ODD_MASK 0x4u
mbed_official 31:42176bc3c368 5635 #define USB_STAT_ODD_SHIFT 2
mbed_official 31:42176bc3c368 5636 #define USB_STAT_TX_MASK 0x8u
mbed_official 31:42176bc3c368 5637 #define USB_STAT_TX_SHIFT 3
mbed_official 31:42176bc3c368 5638 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 31:42176bc3c368 5639 #define USB_STAT_ENDP_SHIFT 4
mbed_official 31:42176bc3c368 5640 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 31:42176bc3c368 5641 /* CTL Bit Fields */
mbed_official 31:42176bc3c368 5642 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 31:42176bc3c368 5643 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 31:42176bc3c368 5644 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 31:42176bc3c368 5645 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 31:42176bc3c368 5646 #define USB_CTL_RESUME_MASK 0x4u
mbed_official 31:42176bc3c368 5647 #define USB_CTL_RESUME_SHIFT 2
mbed_official 31:42176bc3c368 5648 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mbed_official 31:42176bc3c368 5649 #define USB_CTL_HOSTMODEEN_SHIFT 3
mbed_official 31:42176bc3c368 5650 #define USB_CTL_RESET_MASK 0x10u
mbed_official 31:42176bc3c368 5651 #define USB_CTL_RESET_SHIFT 4
mbed_official 31:42176bc3c368 5652 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 31:42176bc3c368 5653 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 31:42176bc3c368 5654 #define USB_CTL_SE0_MASK 0x40u
mbed_official 31:42176bc3c368 5655 #define USB_CTL_SE0_SHIFT 6
mbed_official 31:42176bc3c368 5656 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 31:42176bc3c368 5657 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 31:42176bc3c368 5658 /* ADDR Bit Fields */
mbed_official 31:42176bc3c368 5659 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 31:42176bc3c368 5660 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 31:42176bc3c368 5661 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 31:42176bc3c368 5662 #define USB_ADDR_LSEN_MASK 0x80u
mbed_official 31:42176bc3c368 5663 #define USB_ADDR_LSEN_SHIFT 7
mbed_official 31:42176bc3c368 5664 /* BDTPAGE1 Bit Fields */
mbed_official 31:42176bc3c368 5665 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 31:42176bc3c368 5666 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 31:42176bc3c368 5667 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 31:42176bc3c368 5668 /* FRMNUML Bit Fields */
mbed_official 31:42176bc3c368 5669 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 31:42176bc3c368 5670 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 31:42176bc3c368 5671 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 31:42176bc3c368 5672 /* FRMNUMH Bit Fields */
mbed_official 31:42176bc3c368 5673 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 31:42176bc3c368 5674 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 31:42176bc3c368 5675 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 31:42176bc3c368 5676 /* TOKEN Bit Fields */
mbed_official 31:42176bc3c368 5677 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mbed_official 31:42176bc3c368 5678 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mbed_official 31:42176bc3c368 5679 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mbed_official 31:42176bc3c368 5680 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mbed_official 31:42176bc3c368 5681 #define USB_TOKEN_TOKENPID_SHIFT 4
mbed_official 31:42176bc3c368 5682 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mbed_official 31:42176bc3c368 5683 /* SOFTHLD Bit Fields */
mbed_official 31:42176bc3c368 5684 #define USB_SOFTHLD_CNT_MASK 0xFFu
mbed_official 31:42176bc3c368 5685 #define USB_SOFTHLD_CNT_SHIFT 0
mbed_official 31:42176bc3c368 5686 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mbed_official 31:42176bc3c368 5687 /* BDTPAGE2 Bit Fields */
mbed_official 31:42176bc3c368 5688 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 31:42176bc3c368 5689 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 31:42176bc3c368 5690 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 31:42176bc3c368 5691 /* BDTPAGE3 Bit Fields */
mbed_official 31:42176bc3c368 5692 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 31:42176bc3c368 5693 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 31:42176bc3c368 5694 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 31:42176bc3c368 5695 /* ENDPT Bit Fields */
mbed_official 31:42176bc3c368 5696 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 31:42176bc3c368 5697 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 31:42176bc3c368 5698 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 31:42176bc3c368 5699 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 31:42176bc3c368 5700 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 31:42176bc3c368 5701 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 31:42176bc3c368 5702 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 31:42176bc3c368 5703 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 31:42176bc3c368 5704 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 31:42176bc3c368 5705 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 31:42176bc3c368 5706 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mbed_official 31:42176bc3c368 5707 #define USB_ENDPT_RETRYDIS_SHIFT 6
mbed_official 31:42176bc3c368 5708 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mbed_official 31:42176bc3c368 5709 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mbed_official 31:42176bc3c368 5710 /* USBCTRL Bit Fields */
mbed_official 31:42176bc3c368 5711 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 31:42176bc3c368 5712 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 31:42176bc3c368 5713 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 31:42176bc3c368 5714 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 31:42176bc3c368 5715 /* OBSERVE Bit Fields */
mbed_official 31:42176bc3c368 5716 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 31:42176bc3c368 5717 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 31:42176bc3c368 5718 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 31:42176bc3c368 5719 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 31:42176bc3c368 5720 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 31:42176bc3c368 5721 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 31:42176bc3c368 5722 /* CONTROL Bit Fields */
mbed_official 31:42176bc3c368 5723 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 31:42176bc3c368 5724 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 31:42176bc3c368 5725 /* USBTRC0 Bit Fields */
mbed_official 31:42176bc3c368 5726 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 31:42176bc3c368 5727 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 31:42176bc3c368 5728 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 31:42176bc3c368 5729 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 31:42176bc3c368 5730 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 31:42176bc3c368 5731 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 31:42176bc3c368 5732 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 31:42176bc3c368 5733 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 44:2ce89a25b635 5734 /* USBFRMADJUST Bit Fields */
mbed_official 44:2ce89a25b635 5735 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 44:2ce89a25b635 5736 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 44:2ce89a25b635 5737 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 31:42176bc3c368 5738
mbed_official 31:42176bc3c368 5739 /**
mbed_official 31:42176bc3c368 5740 * @}
mbed_official 31:42176bc3c368 5741 */ /* end of group USB_Register_Masks */
mbed_official 31:42176bc3c368 5742
mbed_official 31:42176bc3c368 5743
mbed_official 31:42176bc3c368 5744 /* USB - Peripheral instance base addresses */
mbed_official 31:42176bc3c368 5745 /** Peripheral USB0 base address */
mbed_official 31:42176bc3c368 5746 #define USB0_BASE (0x40072000u)
mbed_official 31:42176bc3c368 5747 /** Peripheral USB0 base pointer */
mbed_official 31:42176bc3c368 5748 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 31:42176bc3c368 5749 /** Array initializer of USB peripheral base pointers */
mbed_official 31:42176bc3c368 5750 #define USB_BASES { USB0 }
mbed_official 31:42176bc3c368 5751
mbed_official 31:42176bc3c368 5752 /**
mbed_official 31:42176bc3c368 5753 * @}
mbed_official 31:42176bc3c368 5754 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 31:42176bc3c368 5755
mbed_official 31:42176bc3c368 5756
mbed_official 31:42176bc3c368 5757 /*
mbed_official 31:42176bc3c368 5758 ** End of section using anonymous unions
mbed_official 31:42176bc3c368 5759 */
mbed_official 31:42176bc3c368 5760
mbed_official 31:42176bc3c368 5761 #if defined(__ARMCC_VERSION)
mbed_official 31:42176bc3c368 5762 #pragma pop
mbed_official 31:42176bc3c368 5763 #elif defined(__CWCC__)
mbed_official 31:42176bc3c368 5764 #pragma pop
mbed_official 31:42176bc3c368 5765 #elif defined(__GNUC__)
mbed_official 31:42176bc3c368 5766 /* leave anonymous unions enabled */
mbed_official 31:42176bc3c368 5767 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 31:42176bc3c368 5768 #pragma language=default
mbed_official 31:42176bc3c368 5769 #else
mbed_official 31:42176bc3c368 5770 #error Not supported compiler type
mbed_official 31:42176bc3c368 5771 #endif
mbed_official 31:42176bc3c368 5772
mbed_official 31:42176bc3c368 5773 /**
mbed_official 31:42176bc3c368 5774 * @}
mbed_official 31:42176bc3c368 5775 */ /* end of group Peripheral_access_layer */
mbed_official 31:42176bc3c368 5776
mbed_official 31:42176bc3c368 5777
mbed_official 31:42176bc3c368 5778 /* ----------------------------------------------------------------------------
mbed_official 31:42176bc3c368 5779 -- Backward Compatibility
mbed_official 31:42176bc3c368 5780 ---------------------------------------------------------------------------- */
mbed_official 31:42176bc3c368 5781
mbed_official 31:42176bc3c368 5782 /**
mbed_official 31:42176bc3c368 5783 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 31:42176bc3c368 5784 * @{
mbed_official 31:42176bc3c368 5785 */
mbed_official 31:42176bc3c368 5786
mbed_official 31:42176bc3c368 5787 /* No backward compatibility issues. */
mbed_official 31:42176bc3c368 5788
mbed_official 31:42176bc3c368 5789 /**
mbed_official 31:42176bc3c368 5790 * @}
mbed_official 31:42176bc3c368 5791 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 31:42176bc3c368 5792
mbed_official 31:42176bc3c368 5793
mbed_official 31:42176bc3c368 5794 #endif /* #if !defined(MKL46Z4_H_) */
mbed_official 31:42176bc3c368 5795
mbed_official 31:42176bc3c368 5796 /* MKL46Z4.h, eof. */