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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/uart/fsl_uart_features.h@146:f64d43ff0c18
- Child:
- 324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. |
| mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
| mbed_official | 146:f64d43ff0c18 | 4 | * |
| mbed_official | 146:f64d43ff0c18 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 146:f64d43ff0c18 | 6 | * are permitted provided that the following conditions are met: |
| mbed_official | 146:f64d43ff0c18 | 7 | * |
| mbed_official | 146:f64d43ff0c18 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 146:f64d43ff0c18 | 9 | * of conditions and the following disclaimer. |
| mbed_official | 146:f64d43ff0c18 | 10 | * |
| mbed_official | 146:f64d43ff0c18 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 146:f64d43ff0c18 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 146:f64d43ff0c18 | 13 | * other materials provided with the distribution. |
| mbed_official | 146:f64d43ff0c18 | 14 | * |
| mbed_official | 146:f64d43ff0c18 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 146:f64d43ff0c18 | 16 | * contributors may be used to endorse or promote products derived from this |
| mbed_official | 146:f64d43ff0c18 | 17 | * software without specific prior written permission. |
| mbed_official | 146:f64d43ff0c18 | 18 | * |
| mbed_official | 146:f64d43ff0c18 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 146:f64d43ff0c18 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 146:f64d43ff0c18 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 146:f64d43ff0c18 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 146:f64d43ff0c18 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 146:f64d43ff0c18 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 146:f64d43ff0c18 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 146:f64d43ff0c18 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 146:f64d43ff0c18 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 146:f64d43ff0c18 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 146:f64d43ff0c18 | 29 | */ |
| mbed_official | 146:f64d43ff0c18 | 30 | #if !defined(__FSL_UART_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 31 | #define __FSL_UART_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 32 | |
| mbed_official | 146:f64d43ff0c18 | 33 | /* For getting uart instance count from uart.h*/ |
| mbed_official | 146:f64d43ff0c18 | 34 | #include "device/fsl_device_registers.h" |
| mbed_official | 146:f64d43ff0c18 | 35 | |
| mbed_official | 146:f64d43ff0c18 | 36 | #if defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 37 | defined(CPU_MK10DN512VLQ10) || defined(CPU_MK10DN512VMB10) || defined(CPU_MK10DN512VMC10) || defined(CPU_MK10DX128VMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 38 | defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || defined(CPU_MK10FN1M0VLQ12) || defined(CPU_MK10FX512VLQ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 39 | defined(CPU_MK10FN1M0VMD12) || defined(CPU_MK10FX512VMD12) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DN512VLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 40 | defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || defined(CPU_MK20DN512VMB10) || \ |
| mbed_official | 146:f64d43ff0c18 | 41 | defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 42 | defined(CPU_MK20DN512VMD10) || defined(CPU_MK20FN1M0VLQ12) || defined(CPU_MK20FX512VLQ12) || defined(CPU_MK20FN1M0VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 43 | defined(CPU_MK20FX512VMD12) || defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VLL10) || defined(CPU_MK30DX128VLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 44 | defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMB10) || defined(CPU_MK30DN512VMC10) || \ |
| mbed_official | 146:f64d43ff0c18 | 45 | defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK40DN512VLK10) || \ |
| mbed_official | 146:f64d43ff0c18 | 46 | defined(CPU_MK40DN512VLL10) || defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 47 | defined(CPU_MK40DN512VMB10) || defined(CPU_MK40DN512VMC10) || defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 48 | defined(CPU_MK40DN512VMD10) || defined(CPU_MK50DX256CLL10) || defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 49 | defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 50 | defined(CPU_MK50DX256CLK10) || defined(CPU_MK50DX256CMB10) || defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 51 | defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \ |
| mbed_official | 146:f64d43ff0c18 | 52 | defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLK10) || defined(CPU_MK51DX256CMB10) || \ |
| mbed_official | 146:f64d43ff0c18 | 53 | defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 54 | defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 55 | defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN256VLQ10) || defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 56 | defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN256VMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 57 | defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10) || defined(CPU_MK60FN1M0VLQ12) || defined(CPU_MK60FX512VLQ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 58 | defined(CPU_MK60FN1M0VLQ15) || defined(CPU_MK60FX512VLQ15) || defined(CPU_MK60FN1M0VMD12) || defined(CPU_MK60FX512VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 59 | defined(CPU_MK60FN1M0VMD15) || defined(CPU_MK60FX512VMD15) || defined(CPU_MK61FN1M0VMD12) || defined(CPU_MK61FX512VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 60 | defined(CPU_MK61FN1M0VMD15) || defined(CPU_MK61FX512VMD15) || defined(CPU_MK61FN1M0VMD12WS) || defined(CPU_MK61FX512VMD12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 61 | defined(CPU_MK61FN1M0VMD15WS) || defined(CPU_MK61FX512VMD15WS) || defined(CPU_MK61FN1M0VMF12) || defined(CPU_MK61FX512VMF12) || \ |
| mbed_official | 146:f64d43ff0c18 | 62 | defined(CPU_MK61FN1M0VMF15) || defined(CPU_MK61FX512VMF15) || defined(CPU_MK61FN1M0VMJ12) || defined(CPU_MK61FX512VMJ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 63 | defined(CPU_MK61FN1M0VMJ15) || defined(CPU_MK61FX512VMJ15) || defined(CPU_MK61FN1M0VMJ12WS) || defined(CPU_MK61FX512VMJ12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 64 | defined(CPU_MK61FN1M0VMJ15WS) || defined(CPU_MK61FX512VMJ15WS) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 65 | defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \ |
| mbed_official | 146:f64d43ff0c18 | 66 | defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 67 | defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 68 | defined(CPU_MK70FN1M0VMJ15WS) || defined(CPU_MK70FX512VMJ15WS) |
| mbed_official | 146:f64d43ff0c18 | 69 | /* @brief Redefine instance count */ |
| mbed_official | 146:f64d43ff0c18 | 70 | #define UART_INSTANCE_COUNT (HW_UART_INSTANCE_COUNT) |
| mbed_official | 146:f64d43ff0c18 | 71 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 72 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 146:f64d43ff0c18 | 73 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 74 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 75 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 76 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 146:f64d43ff0c18 | 77 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 78 | #define FSL_FEATURE_UART_HAS_FIFO (1) |
| mbed_official | 146:f64d43ff0c18 | 79 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 80 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 81 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 82 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 83 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 84 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 85 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 86 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 87 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 88 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 89 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 90 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 91 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 92 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 93 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 94 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 95 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 96 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 97 | ((x) == 0 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 98 | ((x) == 1 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 99 | ((x) == 2 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 100 | ((x) == 3 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 101 | ((x) == 4 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 102 | ((x) == 5 ? (1) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 103 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 104 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 105 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 106 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 107 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 108 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 146:f64d43ff0c18 | 109 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 110 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 111 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 112 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 113 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 114 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 115 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support.*/ |
| mbed_official | 146:f64d43ff0c18 | 116 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 117 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 118 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 119 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 120 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 121 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 122 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 123 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 124 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 125 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 126 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 127 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 128 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 129 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 130 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 131 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 132 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 133 | #elif defined(CPU_MK10DX128VMP5) || defined(CPU_MK10DN128VMP5) || defined(CPU_MK10DX64VMP5) || defined(CPU_MK10DN64VMP5) || \ |
| mbed_official | 146:f64d43ff0c18 | 134 | defined(CPU_MK10DX32VMP5) || defined(CPU_MK10DN32VMP5) || defined(CPU_MK10DX128VLH5) || defined(CPU_MK10DN128VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 135 | defined(CPU_MK10DX64VLH5) || defined(CPU_MK10DN64VLH5) || defined(CPU_MK10DX32VLH5) || defined(CPU_MK10DN32VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 136 | defined(CPU_MK10DX128VFM5) || defined(CPU_MK10DN128VFM5) || defined(CPU_MK10DX64VFM5) || defined(CPU_MK10DN64VFM5) || \ |
| mbed_official | 146:f64d43ff0c18 | 137 | defined(CPU_MK10DX32VFM5) || defined(CPU_MK10DN32VFM5) || defined(CPU_MK10DX128VFT5) || defined(CPU_MK10DN128VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 138 | defined(CPU_MK10DX64VFT5) || defined(CPU_MK10DN64VFT5) || defined(CPU_MK10DX32VFT5) || defined(CPU_MK10DN32VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 139 | defined(CPU_MK10DX128VLF5) || defined(CPU_MK10DN128VLF5) || defined(CPU_MK10DX64VLF5) || defined(CPU_MK10DN64VLF5) || \ |
| mbed_official | 146:f64d43ff0c18 | 140 | defined(CPU_MK10DX32VLF5) || defined(CPU_MK10DN32VLF5) || defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || \ |
| mbed_official | 146:f64d43ff0c18 | 141 | defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || \ |
| mbed_official | 146:f64d43ff0c18 | 142 | defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 143 | defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ |
| mbed_official | 146:f64d43ff0c18 | 144 | defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || \ |
| mbed_official | 146:f64d43ff0c18 | 145 | defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 146 | defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \ |
| mbed_official | 146:f64d43ff0c18 | 147 | defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) |
| mbed_official | 146:f64d43ff0c18 | 148 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 149 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
| mbed_official | 146:f64d43ff0c18 | 150 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 151 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 152 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 153 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 146:f64d43ff0c18 | 154 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 155 | #define FSL_FEATURE_UART_HAS_FIFO (1) |
| mbed_official | 146:f64d43ff0c18 | 156 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 157 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 158 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 159 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 160 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 161 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 162 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 163 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 164 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 165 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 166 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 167 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 168 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 169 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 170 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 171 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 172 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 173 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 174 | ((x) == 0 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 175 | ((x) == 1 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 176 | ((x) == 2 ? (1) : (-1)))) |
| mbed_official | 146:f64d43ff0c18 | 177 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 178 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 179 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 180 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 181 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 182 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 146:f64d43ff0c18 | 183 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 184 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 185 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 186 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 187 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 188 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 189 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support.*/ |
| mbed_official | 146:f64d43ff0c18 | 190 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 191 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 192 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 193 | ((x) == 2 ? (0) : (-1)))) |
| mbed_official | 146:f64d43ff0c18 | 194 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 195 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 196 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 197 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 198 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 199 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 200 | ((x) == 2 ? (0) : (-1)))) |
| mbed_official | 146:f64d43ff0c18 | 201 | #elif defined(CPU_MK10DX64VLH7) || defined(CPU_MK10DX128VLH7) || defined(CPU_MK10DX256VLH7) || defined(CPU_MK10DX64VLK7) || \ |
| mbed_official | 146:f64d43ff0c18 | 202 | defined(CPU_MK10DX128VLK7) || defined(CPU_MK10DX256VLK7) || defined(CPU_MK10DX128VLL7) || defined(CPU_MK10DX256VLL7) || \ |
| mbed_official | 146:f64d43ff0c18 | 203 | defined(CPU_MK10DX64VMB7) || defined(CPU_MK10DX128VMB7) || defined(CPU_MK10DX256VMB7) || defined(CPU_MK10DX128VML7) || \ |
| mbed_official | 146:f64d43ff0c18 | 204 | defined(CPU_MK10DX256VML7) || defined(CPU_MK10DN512ZVLK10) || defined(CPU_MK10DN512ZVLL10) || defined(CPU_MK10DN512ZVLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 205 | defined(CPU_MK10DX256ZVLQ10) || defined(CPU_MK10DX128ZVLQ10) || defined(CPU_MK10DN512ZVMB10) || defined(CPU_MK10DN512ZVMC10) || \ |
| mbed_official | 146:f64d43ff0c18 | 206 | defined(CPU_MK10DN512ZVMD10) || defined(CPU_MK10DX256ZVMD10) || defined(CPU_MK10DX128ZVMD10) || defined(CPU_MK20DX64VLH7) || \ |
| mbed_official | 146:f64d43ff0c18 | 207 | defined(CPU_MK20DX128VLH7) || defined(CPU_MK20DX256VLH7) || defined(CPU_MK20DX64VLK7) || defined(CPU_MK20DX128VLK7) || \ |
| mbed_official | 146:f64d43ff0c18 | 208 | defined(CPU_MK20DX256VLK7) || defined(CPU_MK20DX128VLL7) || defined(CPU_MK20DX256VLL7) || defined(CPU_MK20DX64VMB7) || \ |
| mbed_official | 146:f64d43ff0c18 | 209 | defined(CPU_MK20DX128VMB7) || defined(CPU_MK20DX256VMB7) || defined(CPU_MK20DX128VML7) || defined(CPU_MK20DX256VML7) || \ |
| mbed_official | 146:f64d43ff0c18 | 210 | defined(CPU_MK20DN512ZVLK10) || defined(CPU_MK20DX256ZVLK10) || defined(CPU_MK20DN512ZVLL10) || defined(CPU_MK20DX256ZVLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 211 | defined(CPU_MK20DN512ZVLQ10) || defined(CPU_MK20DX256ZVLQ10) || defined(CPU_MK20DX128ZVLQ10) || defined(CPU_MK20DN512ZVMB10) || \ |
| mbed_official | 146:f64d43ff0c18 | 212 | defined(CPU_MK20DX256ZVMB10) || defined(CPU_MK20DN512ZVMC10) || defined(CPU_MK20DX256ZVMC10) || defined(CPU_MK20DN512ZVMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 213 | defined(CPU_MK20DX256ZVMD10) || defined(CPU_MK20DX128ZVMD10) || defined(CPU_MK30DX64VLH7) || defined(CPU_MK30DX128VLH7) || \ |
| mbed_official | 146:f64d43ff0c18 | 214 | defined(CPU_MK30DX256VLH7) || defined(CPU_MK30DX64VLK7) || defined(CPU_MK30DX128VLK7) || defined(CPU_MK30DX256VLK7) || \ |
| mbed_official | 146:f64d43ff0c18 | 215 | defined(CPU_MK30DX128VLL7) || defined(CPU_MK30DX256VLL7) || defined(CPU_MK30DX64VMB7) || defined(CPU_MK30DX128VMB7) || \ |
| mbed_official | 146:f64d43ff0c18 | 216 | defined(CPU_MK30DX256VMB7) || defined(CPU_MK30DX128VML7) || defined(CPU_MK30DX256VML7) || defined(CPU_MK30DN512ZVLK10) || \ |
| mbed_official | 146:f64d43ff0c18 | 217 | defined(CPU_MK30DN512ZVLL10) || defined(CPU_MK30DN512ZVLQ10) || defined(CPU_MK30DX256ZVLQ10) || defined(CPU_MK30DX128ZVLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 218 | defined(CPU_MK30DN512ZVMB10) || defined(CPU_MK30DN512ZVMC10) || defined(CPU_MK30DN512ZVMD10) || defined(CPU_MK30DX256ZVMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 219 | defined(CPU_MK30DX128ZVMD10) || defined(CPU_MK40DX64VLH7) || defined(CPU_MK40DX128VLH7) || defined(CPU_MK40DX256VLH7) || \ |
| mbed_official | 146:f64d43ff0c18 | 220 | defined(CPU_MK40DX64VLK7) || defined(CPU_MK40DX128VLK7) || defined(CPU_MK40DX256VLK7) || defined(CPU_MK40DX128VLL7) || \ |
| mbed_official | 146:f64d43ff0c18 | 221 | defined(CPU_MK40DX256VLL7) || defined(CPU_MK40DX64VMB7) || defined(CPU_MK40DX128VMB7) || defined(CPU_MK40DX256VMB7) || \ |
| mbed_official | 146:f64d43ff0c18 | 222 | defined(CPU_MK40DX128VML7) || defined(CPU_MK40DX256VML7) || defined(CPU_MK40DN512ZVLK10) || defined(CPU_MK40DN512ZVLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 223 | defined(CPU_MK40DN512ZVLQ10) || defined(CPU_MK40DX256ZVLQ10) || defined(CPU_MK40DX128ZVLQ10) || defined(CPU_MK40DN512ZVMB10) || \ |
| mbed_official | 146:f64d43ff0c18 | 224 | defined(CPU_MK40DN512ZVMC10) || defined(CPU_MK40DN512ZVMD10) || defined(CPU_MK40DX256ZVMD10) || defined(CPU_MK40DX128ZVMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 225 | defined(CPU_MK50DX128CLH7) || defined(CPU_MK50DX128CLK7) || defined(CPU_MK50DX256CLK7) || defined(CPU_MK50DX256CLL7) || \ |
| mbed_official | 146:f64d43ff0c18 | 226 | defined(CPU_MK50DX128CMB7) || defined(CPU_MK50DX256CMB7) || defined(CPU_MK50DX256CML7) || defined(CPU_MK50DN512ZCLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 227 | defined(CPU_MK50DX256ZCLL10) || defined(CPU_MK50DN512ZCLQ10) || defined(CPU_MK50DN512ZCMC10) || defined(CPU_MK50DX256ZCMC10) || \ |
| mbed_official | 146:f64d43ff0c18 | 228 | defined(CPU_MK50DN512ZCMD10) || defined(CPU_MK50DX256ZCLK10) || defined(CPU_MK50DX256ZCMB10) || defined(CPU_MK51DX128CLH7) || \ |
| mbed_official | 146:f64d43ff0c18 | 229 | defined(CPU_MK51DX128CLK7) || defined(CPU_MK51DX256CLK7) || defined(CPU_MK51DX256CLL7) || defined(CPU_MK51DX128CMB7) || \ |
| mbed_official | 146:f64d43ff0c18 | 230 | defined(CPU_MK51DX256CMB7) || defined(CPU_MK51DX256CML7) || defined(CPU_MK51DN512ZCLL10) || defined(CPU_MK51DX256ZCLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 231 | defined(CPU_MK51DN512ZCLQ10) || defined(CPU_MK51DN256ZCLQ10) || defined(CPU_MK51DN512ZCMC10) || defined(CPU_MK51DX256ZCMC10) || \ |
| mbed_official | 146:f64d43ff0c18 | 232 | defined(CPU_MK51DN512ZCMD10) || defined(CPU_MK51DN256ZCMD10) || defined(CPU_MK51DX256ZCLK10) || defined(CPU_MK51DX256ZCMB10) || \ |
| mbed_official | 146:f64d43ff0c18 | 233 | defined(CPU_MK52DN512ZCLQ10) || defined(CPU_MK52DN512ZCMD10) || defined(CPU_MK53DN512ZCLQ10) || defined(CPU_MK53DX256ZCLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 234 | defined(CPU_MK53DN512ZCMD10) || defined(CPU_MK53DX256ZCMD10) || defined(CPU_MK60DN512ZVLL10) || defined(CPU_MK60DX256ZVLL10) || \ |
| mbed_official | 146:f64d43ff0c18 | 235 | defined(CPU_MK60DN256ZVLL10) || defined(CPU_MK60DN512ZVLQ10) || defined(CPU_MK60DX256ZVLQ10) || defined(CPU_MK60DN256ZVLQ10) || \ |
| mbed_official | 146:f64d43ff0c18 | 236 | defined(CPU_MK60DN512ZVMC10) || defined(CPU_MK60DX256ZVMC10) || defined(CPU_MK60DN256ZVMC10) || defined(CPU_MK60DN512ZVMD10) || \ |
| mbed_official | 146:f64d43ff0c18 | 237 | defined(CPU_MK60DX256ZVMD10) || defined(CPU_MK60DN256ZVMD10) |
| mbed_official | 146:f64d43ff0c18 | 238 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 239 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
| mbed_official | 146:f64d43ff0c18 | 240 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 241 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 242 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 243 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 146:f64d43ff0c18 | 244 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 245 | #define FSL_FEATURE_UART_HAS_FIFO (1) |
| mbed_official | 146:f64d43ff0c18 | 246 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 247 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 248 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 249 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 250 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 251 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 252 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 253 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 254 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 255 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 256 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 257 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 258 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 259 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 260 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 261 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 262 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 263 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 264 | ((x) == 0 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 265 | ((x) == 1 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 266 | ((x) == 2 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 267 | ((x) == 3 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 268 | ((x) == 4 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 269 | ((x) == 5 ? (1) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 270 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 271 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 272 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 273 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 274 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 275 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 146:f64d43ff0c18 | 276 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 277 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 278 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 279 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 280 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 281 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 282 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support.*/ |
| mbed_official | 146:f64d43ff0c18 | 283 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 284 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 285 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 286 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 287 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 288 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 289 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 290 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 291 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 292 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 293 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 294 | #elif defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || defined(CPU_MK11DX128VLK5WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 295 | defined(CPU_MK11DX256VLK5WS) || defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || \ |
| mbed_official | 146:f64d43ff0c18 | 296 | defined(CPU_MK11DN512VMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || defined(CPU_MK11DN512VMC5WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 297 | defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK12DX128VLK5) || \ |
| mbed_official | 146:f64d43ff0c18 | 298 | defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || defined(CPU_MK12DX256VMC5) || \ |
| mbed_official | 146:f64d43ff0c18 | 299 | defined(CPU_MK12DN512VMC5) || defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK21DX128VLK5) || \ |
| mbed_official | 146:f64d43ff0c18 | 300 | defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 301 | defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VMC5) || defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || \ |
| mbed_official | 146:f64d43ff0c18 | 302 | defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK22DX128VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 303 | defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \ |
| mbed_official | 146:f64d43ff0c18 | 304 | defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5) || \ |
| mbed_official | 146:f64d43ff0c18 | 305 | defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5) || defined(CPU_MK22FN512VDC12) |
| mbed_official | 146:f64d43ff0c18 | 306 | /* @brief Redefine instance count */ |
| mbed_official | 146:f64d43ff0c18 | 307 | #define UART_INSTANCE_COUNT (HW_UART_INSTANCE_COUNT) |
| mbed_official | 146:f64d43ff0c18 | 308 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 309 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 146:f64d43ff0c18 | 310 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 311 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 312 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 313 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 146:f64d43ff0c18 | 314 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 315 | #define FSL_FEATURE_UART_HAS_FIFO (1) |
| mbed_official | 146:f64d43ff0c18 | 316 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 317 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 318 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 319 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 320 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 321 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 322 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 323 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 324 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 325 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 326 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 327 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 328 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 329 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 330 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 331 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 332 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 333 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 334 | ((x) == 0 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 335 | ((x) == 1 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 336 | ((x) == 2 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 337 | ((x) == 3 ? (1) : (-1))))) |
| mbed_official | 146:f64d43ff0c18 | 338 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 339 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 340 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 341 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 342 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 343 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 146:f64d43ff0c18 | 344 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 345 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 346 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 347 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 348 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 349 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 350 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support.*/ |
| mbed_official | 146:f64d43ff0c18 | 351 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 352 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 353 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 354 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 355 | ((x) == 3 ? (0) : (-1))))) |
| mbed_official | 146:f64d43ff0c18 | 356 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 357 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 358 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 359 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 360 | #elif defined(CPU_MK21FX512VLQ12) || defined(CPU_MK21FN1M0VLQ12) || defined(CPU_MK21FX512VLQ12WS) || defined(CPU_MK21FN1M0VLQ12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 361 | defined(CPU_MK21FX512VMC12) || defined(CPU_MK21FN1M0VMC12) || defined(CPU_MK21FX512VMC12WS) || defined(CPU_MK21FN1M0VMC12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 362 | defined(CPU_MK21FX512VMD12) || defined(CPU_MK21FN1M0VMD12) || defined(CPU_MK21FX512VMD12WS) || defined(CPU_MK21FN1M0VMD12WS) || \ |
| mbed_official | 146:f64d43ff0c18 | 363 | defined(CPU_MK22FX512VLH12) || defined(CPU_MK22FN1M0VLH12) || defined(CPU_MK22FX512VLK12) || defined(CPU_MK22FN1M0VLK12) || \ |
| mbed_official | 146:f64d43ff0c18 | 364 | defined(CPU_MK22FX512VLL12) || defined(CPU_MK22FN1M0VLL12) || defined(CPU_MK22FX512VLQ12) || defined(CPU_MK22FN1M0VLQ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 365 | defined(CPU_MK22FX512VMC12) || defined(CPU_MK22FN1M0VMC12) || defined(CPU_MK22FX512VMD12) || defined(CPU_MK22FN1M0VMD12) |
| mbed_official | 146:f64d43ff0c18 | 366 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 367 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) |
| mbed_official | 146:f64d43ff0c18 | 368 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 369 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 370 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 371 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) |
| mbed_official | 146:f64d43ff0c18 | 372 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 373 | #define FSL_FEATURE_UART_HAS_FIFO (1) |
| mbed_official | 146:f64d43ff0c18 | 374 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 375 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 376 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 377 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 378 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 379 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 380 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 381 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 382 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 383 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 384 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 385 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 386 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 387 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 388 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 389 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 390 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 391 | #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 392 | ((x) == 0 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 393 | ((x) == 1 ? (8) : \ |
| mbed_official | 146:f64d43ff0c18 | 394 | ((x) == 2 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 395 | ((x) == 3 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 396 | ((x) == 4 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 397 | ((x) == 5 ? (1) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 398 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 399 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 400 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 401 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 402 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 403 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) |
| mbed_official | 146:f64d43ff0c18 | 404 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 405 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 406 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 407 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 408 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 409 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 410 | /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support.*/ |
| mbed_official | 146:f64d43ff0c18 | 411 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 412 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 413 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 414 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 415 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 416 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 417 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 418 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 419 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 420 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 421 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 422 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 423 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 424 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 425 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 426 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 427 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \ |
| mbed_official | 146:f64d43ff0c18 | 428 | ((x) == 0 ? (1) : \ |
| mbed_official | 146:f64d43ff0c18 | 429 | ((x) == 1 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 430 | ((x) == 2 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 431 | ((x) == 3 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 432 | ((x) == 4 ? (0) : \ |
| mbed_official | 146:f64d43ff0c18 | 433 | ((x) == 5 ? (0) : (-1))))))) |
| mbed_official | 146:f64d43ff0c18 | 434 | #elif defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || defined(CPU_MKE02Z64VLD2) || \ |
| mbed_official | 146:f64d43ff0c18 | 435 | defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || \ |
| mbed_official | 146:f64d43ff0c18 | 436 | defined(CPU_MKE02Z32VLH2) || defined(CPU_MKE02Z32VQH2) || defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || \ |
| mbed_official | 146:f64d43ff0c18 | 437 | defined(CPU_MKE04Z8VWJ4) || defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || defined(CPU_MKL14Z32VFT4) || \ |
| mbed_official | 146:f64d43ff0c18 | 438 | defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || defined(CPU_MKL14Z32VLK4) || \ |
| mbed_official | 146:f64d43ff0c18 | 439 | defined(CPU_MKL14Z64VLK4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || defined(CPU_MKL15Z128VFM4) || \ |
| mbed_official | 146:f64d43ff0c18 | 440 | defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || defined(CPU_MKL15Z32VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 441 | defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || defined(CPU_MKL15Z64VLK4) || \ |
| mbed_official | 146:f64d43ff0c18 | 442 | defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || \ |
| mbed_official | 146:f64d43ff0c18 | 443 | defined(CPU_MKL16Z32VFT4) || defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 444 | defined(CPU_MKL16Z64VLH4) || defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VLK4) || \ |
| mbed_official | 146:f64d43ff0c18 | 445 | defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || \ |
| mbed_official | 146:f64d43ff0c18 | 446 | defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4) || \ |
| mbed_official | 146:f64d43ff0c18 | 447 | defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \ |
| mbed_official | 146:f64d43ff0c18 | 448 | defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 449 | defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \ |
| mbed_official | 146:f64d43ff0c18 | 450 | defined(CPU_MKL26Z32VFM4) || defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || \ |
| mbed_official | 146:f64d43ff0c18 | 451 | defined(CPU_MKL26Z64VFT4) || defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 452 | defined(CPU_MKL26Z128VLH4) || defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || \ |
| mbed_official | 146:f64d43ff0c18 | 453 | defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL34Z64VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 454 | defined(CPU_MKL34Z64VLL4) || defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 455 | defined(CPU_MKL36Z64VLL4) || defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || \ |
| mbed_official | 146:f64d43ff0c18 | 456 | defined(CPU_MKL36Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \ |
| mbed_official | 146:f64d43ff0c18 | 457 | defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
| mbed_official | 146:f64d43ff0c18 | 458 | /* @brief Uart0 was not counted as part of instance count, hence add 1 to instance count*/ |
| mbed_official | 146:f64d43ff0c18 | 459 | #define UART_INSTANCE_COUNT (HW_UART_INSTANCE_COUNT + 1) |
| mbed_official | 146:f64d43ff0c18 | 460 | /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 461 | #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0) |
| mbed_official | 146:f64d43ff0c18 | 462 | /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN]).*/ |
| mbed_official | 146:f64d43ff0c18 | 463 | #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 464 | /* @brief Has extended data register ED.*/ |
| mbed_official | 146:f64d43ff0c18 | 465 | #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) |
| mbed_official | 146:f64d43ff0c18 | 466 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 467 | #define FSL_FEATURE_UART_HAS_FIFO (0) |
| mbed_official | 146:f64d43ff0c18 | 468 | /* @brief Hardware flow control (RTS, CTS) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 469 | #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 470 | /* @brief Infrared (modulation) is supported.*/ |
| mbed_official | 146:f64d43ff0c18 | 471 | #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 472 | /* @brief 2 bits long stop bit is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 473 | #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 474 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 475 | #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 476 | /* @brief Baud rate fine adjustment is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 477 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 478 | /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS]).*/ |
| mbed_official | 146:f64d43ff0c18 | 479 | #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 480 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 481 | #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 482 | /* @brief Baud rate oversampling is available.*/ |
| mbed_official | 146:f64d43ff0c18 | 483 | #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) |
| mbed_official | 146:f64d43ff0c18 | 484 | /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available).*/ |
| mbed_official | 146:f64d43ff0c18 | 485 | #define FSL_FEATURE_UART_FIFO_SIZE (0) |
| mbed_official | 146:f64d43ff0c18 | 486 | /* @brief Maximal data width without parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 487 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) |
| mbed_official | 146:f64d43ff0c18 | 488 | /* @brief Maximal data width with parity bit.*/ |
| mbed_official | 146:f64d43ff0c18 | 489 | #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (8) |
| mbed_official | 146:f64d43ff0c18 | 490 | /* @brief Supports two match addresses to filter incoming frames.*/ |
| mbed_official | 146:f64d43ff0c18 | 491 | #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0) |
| mbed_official | 146:f64d43ff0c18 | 492 | /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE].*/ |
| mbed_official | 146:f64d43ff0c18 | 493 | #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) |
| mbed_official | 146:f64d43ff0c18 | 494 | /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS].*/ |
| mbed_official | 146:f64d43ff0c18 | 495 | #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) |
| mbed_official | 146:f64d43ff0c18 | 496 | /* @brief Data character bit order selection is supported (bit field S2[MSBF]).*/ |
| mbed_official | 146:f64d43ff0c18 | 497 | #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0) |
| mbed_official | 146:f64d43ff0c18 | 498 | /* @brief Has smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 499 | #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 500 | /* @brief Has improved smart card (ISO7816 protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 501 | #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 502 | /* @brief Has local operation network (CEA709.1-B protocol) support.*/ |
| mbed_official | 146:f64d43ff0c18 | 503 | #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 504 | #else |
| mbed_official | 146:f64d43ff0c18 | 505 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 506 | #endif |
| mbed_official | 146:f64d43ff0c18 | 507 | |
| mbed_official | 146:f64d43ff0c18 | 508 | #endif /* __FSL_UART_FEATURES_H__*/ |
| mbed_official | 146:f64d43ff0c18 | 509 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 510 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 511 | ******************************************************************************/ |
| mbed_official | 146:f64d43ff0c18 | 512 |
