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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/rtc/fsl_rtc_hal_access_control.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/rtc/fsl_rtc_hal_access_control.h@146:f64d43ff0c18 
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_RTC_HAL_ACCESS_CONTROL_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_RTC_HAL_ACCESS_CONTROL_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33
mbed_official 146:f64d43ff0c18 34 #include "fsl_rtc_features.h"
mbed_official 146:f64d43ff0c18 35 #include "fsl_device_registers.h"
mbed_official 146:f64d43ff0c18 36 #include <stdint.h>
mbed_official 146:f64d43ff0c18 37 #include <stdbool.h>
mbed_official 146:f64d43ff0c18 38
mbed_official 146:f64d43ff0c18 39
mbed_official 146:f64d43ff0c18 40
mbed_official 146:f64d43ff0c18 41 /*! @addtogroup rtc_hal*/
mbed_official 146:f64d43ff0c18 42 /*! @{*/
mbed_official 146:f64d43ff0c18 43
mbed_official 146:f64d43ff0c18 44
mbed_official 146:f64d43ff0c18 45 /*******************************************************************************
mbed_official 146:f64d43ff0c18 46 * Definitions
mbed_official 146:f64d43ff0c18 47 ******************************************************************************/
mbed_official 146:f64d43ff0c18 48
mbed_official 146:f64d43ff0c18 49 typedef struct rtc_hal_access_control_config
mbed_official 146:f64d43ff0c18 50 {
mbed_official 146:f64d43ff0c18 51 /*! Set/clear any of the following bitfields to enable/disable the
mbed_official 146:f64d43ff0c18 52 * respective interrupts.\n\n
mbed_official 146:f64d43ff0c18 53 * IERW: Interrupt Enable Register Write \n
mbed_official 146:f64d43ff0c18 54 * LRW: Lock Register Write \n
mbed_official 146:f64d43ff0c18 55 * SRW: Status Register Write \n
mbed_official 146:f64d43ff0c18 56 * CRW: Control Register Write \n
mbed_official 146:f64d43ff0c18 57 * TCRW: Time Compensation Register Write \n
mbed_official 146:f64d43ff0c18 58 * TARW: Time Alarm Register Write \n
mbed_official 146:f64d43ff0c18 59 * TPRW: Time Prescaler Register Write \n
mbed_official 146:f64d43ff0c18 60 * TSRW: Time Seconds Register Write \n
mbed_official 146:f64d43ff0c18 61 * \n
mbed_official 146:f64d43ff0c18 62 * For MCUs that have Tamper feature: \n
mbed_official 146:f64d43ff0c18 63 * TIRW: Tamper Interrupt Register Write \n
mbed_official 146:f64d43ff0c18 64 * TTRW: Tamper Trim Register Write \n
mbed_official 146:f64d43ff0c18 65 * TDRW: Tamper Detect Register Write \n
mbed_official 146:f64d43ff0c18 66 * TERW: Tamper Enable Register Write \n
mbed_official 146:f64d43ff0c18 67 * TTSW: Tamper Time Seconds Write \n
mbed_official 146:f64d43ff0c18 68 * \n
mbed_official 146:f64d43ff0c18 69 * For MCUs that have Monotonic Counter: \n
mbed_official 146:f64d43ff0c18 70 * MCHW: Monotonic Counter High Write \n
mbed_official 146:f64d43ff0c18 71 * MCLW: Monotonic Counter Low Write \n
mbed_official 146:f64d43ff0c18 72 * MERW: Monotonic Enable Register Write \n
mbed_official 146:f64d43ff0c18 73 */
mbed_official 146:f64d43ff0c18 74 hw_rtc_war_t writeFlags;
mbed_official 146:f64d43ff0c18 75
mbed_official 146:f64d43ff0c18 76 /*! Set/clear any of the following bitfields to enable/disable the
mbed_official 146:f64d43ff0c18 77 * respective interrupts.\n\n
mbed_official 146:f64d43ff0c18 78 * IERR: Interrupt Enable Register Read \n
mbed_official 146:f64d43ff0c18 79 * LRR: Lock Register Read \n
mbed_official 146:f64d43ff0c18 80 * SRR: Status Register Read \n
mbed_official 146:f64d43ff0c18 81 * CRR: Control Register Read \n
mbed_official 146:f64d43ff0c18 82 * TCRR: Time Compensation Register Read \n
mbed_official 146:f64d43ff0c18 83 * TARR: Time Alarm Register Read \n
mbed_official 146:f64d43ff0c18 84 * TPRR: Time Prescaler Register Read \n
mbed_official 146:f64d43ff0c18 85 * TSRR: Time Seconds Register Read \n
mbed_official 146:f64d43ff0c18 86 * \n
mbed_official 146:f64d43ff0c18 87 * For MCUs that have Tamper feature: \n
mbed_official 146:f64d43ff0c18 88 * TIRR: Tamper Interrupt Register Read \n
mbed_official 146:f64d43ff0c18 89 * TTRR: Tamper Trim Register Read \n
mbed_official 146:f64d43ff0c18 90 * TDRR: Tamper Detect Register Read \n
mbed_official 146:f64d43ff0c18 91 * TERR: Tamper Enable Register Read \n
mbed_official 146:f64d43ff0c18 92 * TTSR: Tamper Time Seconds Read \n
mbed_official 146:f64d43ff0c18 93 * \n
mbed_official 146:f64d43ff0c18 94 * For MCUs that have Monotonic Counter: \n
mbed_official 146:f64d43ff0c18 95 * MCHR: Monotonic Counter High Read \n
mbed_official 146:f64d43ff0c18 96 * MCLR: Monotonic Counter Low Read \n
mbed_official 146:f64d43ff0c18 97 * MERR: Monotonic Enable Register Read \n
mbed_official 146:f64d43ff0c18 98 */
mbed_official 146:f64d43ff0c18 99 hw_rtc_rar_t readFlags;
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 } rtc_hal_access_control_config_t;
mbed_official 146:f64d43ff0c18 102
mbed_official 146:f64d43ff0c18 103
mbed_official 146:f64d43ff0c18 104 /*******************************************************************************
mbed_official 146:f64d43ff0c18 105 * API
mbed_official 146:f64d43ff0c18 106 ******************************************************************************/
mbed_official 146:f64d43ff0c18 107
mbed_official 146:f64d43ff0c18 108 #if FSL_FEATURE_RTC_HAS_ACCESS_CONTROL
mbed_official 146:f64d43ff0c18 109
mbed_official 146:f64d43ff0c18 110 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 111 extern "C" {
mbed_official 146:f64d43ff0c18 112 #endif
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114
mbed_official 146:f64d43ff0c18 115 /*-------------------------------------------------------------------------------------------*/
mbed_official 146:f64d43ff0c18 116 /* RTC Access Control Register Reset Functions*/
mbed_official 146:f64d43ff0c18 117 /*-------------------------------------------------------------------------------------------*/
mbed_official 146:f64d43ff0c18 118
mbed_official 146:f64d43ff0c18 119 /*! @brief Resets the RTC Write Access Register (RTC_WAR).*/
mbed_official 146:f64d43ff0c18 120 static inline void rtc_hal_reset_reg_WAR(void)
mbed_official 146:f64d43ff0c18 121 {
mbed_official 146:f64d43ff0c18 122 HW_RTC_WAR_WR((uint32_t)0x0000FFFFU);
mbed_official 146:f64d43ff0c18 123 }
mbed_official 146:f64d43ff0c18 124
mbed_official 146:f64d43ff0c18 125 /*! @brief Resets the RTC Read Access Register (RTC_RAR).*/
mbed_official 146:f64d43ff0c18 126 static inline void rtc_hal_reset_reg_RAR(void)
mbed_official 146:f64d43ff0c18 127 {
mbed_official 146:f64d43ff0c18 128 HW_RTC_RAR_WR((uint32_t)0x0000FFFFU);
mbed_official 146:f64d43ff0c18 129 }
mbed_official 146:f64d43ff0c18 130
mbed_official 146:f64d43ff0c18 131 /*-------------------------------------------------------------------------------------------*/
mbed_official 146:f64d43ff0c18 132 /* RTC Access Control Configuration*/
mbed_official 146:f64d43ff0c18 133 /*-------------------------------------------------------------------------------------------*/
mbed_official 146:f64d43ff0c18 134
mbed_official 146:f64d43ff0c18 135 /*! @brief Configures the read and write access controls to other module fields
mbed_official 146:f64d43ff0c18 136 * @param flags [in] pointer to structure where configuration flags are
mbed_official 146:f64d43ff0c18 137 * found. See the related structure for details.
mbed_official 146:f64d43ff0c18 138 */
mbed_official 146:f64d43ff0c18 139 static inline void rtc_hal_access_control_configuration(const rtc_hal_access_control_config_t * flags)
mbed_official 146:f64d43ff0c18 140 {
mbed_official 146:f64d43ff0c18 141 /* check for null pointer*/
mbed_official 146:f64d43ff0c18 142 if(NULL == flags)
mbed_official 146:f64d43ff0c18 143 {
mbed_official 146:f64d43ff0c18 144 return;
mbed_official 146:f64d43ff0c18 145 }
mbed_official 146:f64d43ff0c18 146
mbed_official 146:f64d43ff0c18 147 uint32_t valid_flags;
mbed_official 146:f64d43ff0c18 148
mbed_official 146:f64d43ff0c18 149 /* Set/clear any of the following bitfields to enable/disable the
mbed_official 146:f64d43ff0c18 150 * respective interrupts.\n\n
mbed_official 146:f64d43ff0c18 151 * IERW: Interrupt Enable Register Write \n
mbed_official 146:f64d43ff0c18 152 * LRW: Lock Register Write \n
mbed_official 146:f64d43ff0c18 153 * SRW: Status Register Write \n
mbed_official 146:f64d43ff0c18 154 * CRW: Control Register Write \n
mbed_official 146:f64d43ff0c18 155 * TCRW: Time Compensation Register Write \n
mbed_official 146:f64d43ff0c18 156 * TARW: Time Alarm Register Write \n
mbed_official 146:f64d43ff0c18 157 * TPRW: Time Prescaler Register Write \n
mbed_official 146:f64d43ff0c18 158 * TSRW: Time Seconds Register Write \n
mbed_official 146:f64d43ff0c18 159 * \n
mbed_official 146:f64d43ff0c18 160 * For MCUs that have Tamper feature: \n
mbed_official 146:f64d43ff0c18 161 * TIRW: Tamper Interrupt Register Write \n
mbed_official 146:f64d43ff0c18 162 * TTRW: Tamper Trim Register Write \n
mbed_official 146:f64d43ff0c18 163 * TDRW: Tamper Detect Register Write \n
mbed_official 146:f64d43ff0c18 164 * TERW: Tamper Enable Register Write \n
mbed_official 146:f64d43ff0c18 165 * TTSW: Tamper Time Seconds Write \n
mbed_official 146:f64d43ff0c18 166 * \n
mbed_official 146:f64d43ff0c18 167 * For MCUs that have Monotonic Counter: \n
mbed_official 146:f64d43ff0c18 168 * MCHW: Monotonic Counter High Write \n
mbed_official 146:f64d43ff0c18 169 * MCLW: Monotonic Counter Low Write \n
mbed_official 146:f64d43ff0c18 170 * MERW: Monotonic Enable Register Write \n
mbed_official 146:f64d43ff0c18 171 */
mbed_official 146:f64d43ff0c18 172 valid_flags = 0;
mbed_official 146:f64d43ff0c18 173
mbed_official 146:f64d43ff0c18 174 #if FSL_FEATURE_RTC_HAS_MONOTONIC
mbed_official 146:f64d43ff0c18 175 valid_flags |= (BM_RTC_WAR_MCHW | BM_RTC_WAR_MCLW | BM_RTC_WAR_MERW);
mbed_official 146:f64d43ff0c18 176 #endif
mbed_official 146:f64d43ff0c18 177 valid_flags |= (BM_RTC_WAR_IERW | BM_RTC_WAR_LRW | BM_RTC_WAR_SRW |
mbed_official 146:f64d43ff0c18 178 BM_RTC_WAR_CRW | BM_RTC_WAR_TCRW | BM_RTC_WAR_TARW | BM_RTC_WAR_TPRW |
mbed_official 146:f64d43ff0c18 179 BM_RTC_WAR_TSRW);
mbed_official 146:f64d43ff0c18 180
mbed_official 146:f64d43ff0c18 181 HW_RTC_WAR_WR((flags->writeFlags.U) & valid_flags);
mbed_official 146:f64d43ff0c18 182
mbed_official 146:f64d43ff0c18 183 /* Set/clear any of the following bitfields to enable/disable the
mbed_official 146:f64d43ff0c18 184 * respective interrupts.\n\n
mbed_official 146:f64d43ff0c18 185 * IERR: Interrupt Enable Register Read \n
mbed_official 146:f64d43ff0c18 186 * LRR: Lock Register Read \n
mbed_official 146:f64d43ff0c18 187 * SRR: Status Register Read \n
mbed_official 146:f64d43ff0c18 188 * CRR: Control Register Read \n
mbed_official 146:f64d43ff0c18 189 * TCRR: Time Compensation Register Read \n
mbed_official 146:f64d43ff0c18 190 * TARR: Time Alarm Register Read \n
mbed_official 146:f64d43ff0c18 191 * TPRR: Time Prescaler Register Read \n
mbed_official 146:f64d43ff0c18 192 * TSRR: Time Seconds Register Read \n
mbed_official 146:f64d43ff0c18 193 * \n
mbed_official 146:f64d43ff0c18 194 * For MCUs that have Tamper feature: \n
mbed_official 146:f64d43ff0c18 195 * TIRR: Tamper Interrupt Register Read \n
mbed_official 146:f64d43ff0c18 196 * TTRR: Tamper Trim Register Read \n
mbed_official 146:f64d43ff0c18 197 * TDRR: Tamper Detect Register Read \n
mbed_official 146:f64d43ff0c18 198 * TERR: Tamper Enable Register Read \n
mbed_official 146:f64d43ff0c18 199 * TTSR: Tamper Time Seconds Read \n
mbed_official 146:f64d43ff0c18 200 * \n
mbed_official 146:f64d43ff0c18 201 * For MCUs that have Monotonic Counter: \n
mbed_official 146:f64d43ff0c18 202 * MCHR: Monotonic Counter High Read \n
mbed_official 146:f64d43ff0c18 203 * MCLR: Monotonic Counter Low Read \n
mbed_official 146:f64d43ff0c18 204 * MERR: Monotonic Enable Register Read \n
mbed_official 146:f64d43ff0c18 205 */
mbed_official 146:f64d43ff0c18 206 valid_flags = 0;
mbed_official 146:f64d43ff0c18 207
mbed_official 146:f64d43ff0c18 208 #if FSL_FEATURE_RTC_HAS_MONOTONIC
mbed_official 146:f64d43ff0c18 209 valid_flags |= (BM_RTC_RAR_MCHR | BM_RTC_RAR_MCLR | BM_RTC_RAR_MERR);
mbed_official 146:f64d43ff0c18 210 #endif
mbed_official 146:f64d43ff0c18 211 valid_flags |= (BM_RTC_RAR_IERR | BM_RTC_RAR_LRR | BM_RTC_RAR_SRR |
mbed_official 146:f64d43ff0c18 212 BM_RTC_RAR_CRR | BM_RTC_RAR_TCRR | BM_RTC_RAR_TARR | BM_RTC_RAR_TPRR |
mbed_official 146:f64d43ff0c18 213 BM_RTC_RAR_TSRR);
mbed_official 146:f64d43ff0c18 214
mbed_official 146:f64d43ff0c18 215 HW_RTC_RAR_WR((flags->readFlags.U) & valid_flags);
mbed_official 146:f64d43ff0c18 216
mbed_official 146:f64d43ff0c18 217 }
mbed_official 146:f64d43ff0c18 218
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 #if FSL_FEATURE_RTC_HAS_MONOTONIC
mbed_official 146:f64d43ff0c18 221 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 222 * field Monotonic Counter High Write (MCHW). Once cleared,
mbed_official 146:f64d43ff0c18 223 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 224 * VBAT POR or by the software reset.
mbed_official 146:f64d43ff0c18 225 * @return true: Writes to the monotonic counter high register complete normally.
mbed_official 146:f64d43ff0c18 226 * false: Writes to the monotonic counter high register are ignored.
mbed_official 146:f64d43ff0c18 227 */
mbed_official 146:f64d43ff0c18 228 static inline bool rtc_hal_get_monotonic_hcount_wreg(void)
mbed_official 146:f64d43ff0c18 229 {
mbed_official 146:f64d43ff0c18 230 return (bool)BR_RTC_WAR_MCHW;
mbed_official 146:f64d43ff0c18 231 }
mbed_official 146:f64d43ff0c18 232
mbed_official 146:f64d43ff0c18 233 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 234 * field Monotonic Counter High Write (MCHW). Once cleared,
mbed_official 146:f64d43ff0c18 235 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 236 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 237 * @param enable true: Writes to the monotonic counter high register complete normally.
mbed_official 146:f64d43ff0c18 238 * false: Writes to the monotonic counter high register are ignored.
mbed_official 146:f64d43ff0c18 239 */
mbed_official 146:f64d43ff0c18 240 static inline void rtc_hal_set_monotonic_hcount_wreg(bool enable)
mbed_official 146:f64d43ff0c18 241 {
mbed_official 146:f64d43ff0c18 242 BW_RTC_WAR_MCHW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 243 }
mbed_official 146:f64d43ff0c18 244
mbed_official 146:f64d43ff0c18 245 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 246 * field Monotonic Counter Low Write (MCLW). Once cleared,
mbed_official 146:f64d43ff0c18 247 * this bit is only set by system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 248 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 249 * @return true: Writes to the monotonic counter low register complete normally.
mbed_official 146:f64d43ff0c18 250 * false: Writes to the monotonic counter low register are ignored.
mbed_official 146:f64d43ff0c18 251 */
mbed_official 146:f64d43ff0c18 252 static inline bool rtc_hal_get_monotonic_lcount_wreg(void)
mbed_official 146:f64d43ff0c18 253 {
mbed_official 146:f64d43ff0c18 254 return (bool)BR_RTC_WAR_MCLW;
mbed_official 146:f64d43ff0c18 255 }
mbed_official 146:f64d43ff0c18 256
mbed_official 146:f64d43ff0c18 257 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 258 * field Monotonic Counter Low Write (MCLW). Once cleared,
mbed_official 146:f64d43ff0c18 259 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 260 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 261 * @param enable true: Writes to the monotonic counter low register complete normally.
mbed_official 146:f64d43ff0c18 262 * false: Writes to the monotonic counter low register are ignored.
mbed_official 146:f64d43ff0c18 263 */
mbed_official 146:f64d43ff0c18 264 static inline void rtc_hal_set_monotonic_lcount_wreg(bool enable)
mbed_official 146:f64d43ff0c18 265 {
mbed_official 146:f64d43ff0c18 266 BW_RTC_WAR_MCLW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 267 }
mbed_official 146:f64d43ff0c18 268
mbed_official 146:f64d43ff0c18 269 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 270 * field Monotonic Enable Register Write (MERW). Once cleared,
mbed_official 146:f64d43ff0c18 271 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 272 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 273 * @return true: Writes to the monotonic enable register complete normally.
mbed_official 146:f64d43ff0c18 274 * false: Writes to the monotonic enable register are ignored.
mbed_official 146:f64d43ff0c18 275 */
mbed_official 146:f64d43ff0c18 276 static inline bool rtc_hal_get_monotonic_enable_wreg(void)
mbed_official 146:f64d43ff0c18 277 {
mbed_official 146:f64d43ff0c18 278 return (bool)BR_RTC_WAR_MERW;
mbed_official 146:f64d43ff0c18 279 }
mbed_official 146:f64d43ff0c18 280
mbed_official 146:f64d43ff0c18 281 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 282 * field Monotonic Enable Register Write (MERW). Once cleared,
mbed_official 146:f64d43ff0c18 283 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 284 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 285 * @param enable true: Writes to the monotonic enable register complete normally.
mbed_official 146:f64d43ff0c18 286 * false: Writes to the monotonic enable register are ignored.
mbed_official 146:f64d43ff0c18 287 */
mbed_official 146:f64d43ff0c18 288 static inline void rtc_hal_set_monotonic_enable_wreg(bool enable)
mbed_official 146:f64d43ff0c18 289 {
mbed_official 146:f64d43ff0c18 290 BW_RTC_WAR_MERW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 291 }
mbed_official 146:f64d43ff0c18 292 #endif
mbed_official 146:f64d43ff0c18 293
mbed_official 146:f64d43ff0c18 294 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 295 * field Interrupt Enable Register Write (IERW). Once cleared,
mbed_official 146:f64d43ff0c18 296 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 297 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 298 * @return true: Writes to the interrupt enable register complete normally.
mbed_official 146:f64d43ff0c18 299 * false: Writes to the interrupt enable register are ignored.
mbed_official 146:f64d43ff0c18 300 */
mbed_official 146:f64d43ff0c18 301 static inline bool rtc_hal_get_interrupt_enable_wreg(void)
mbed_official 146:f64d43ff0c18 302 {
mbed_official 146:f64d43ff0c18 303 return (bool)BR_RTC_WAR_IERW;
mbed_official 146:f64d43ff0c18 304 }
mbed_official 146:f64d43ff0c18 305
mbed_official 146:f64d43ff0c18 306 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 307 * field Interrupt Enable Register Write (IERW). Once cleared,
mbed_official 146:f64d43ff0c18 308 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 309 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 310 * @param enable true: Writes to the interrupt enable register complete normally.
mbed_official 146:f64d43ff0c18 311 * false: Writes to the interrupt enable register are ignored.
mbed_official 146:f64d43ff0c18 312 */
mbed_official 146:f64d43ff0c18 313 static inline void rtc_hal_set_interrupt_enable_wreg(bool enable)
mbed_official 146:f64d43ff0c18 314 {
mbed_official 146:f64d43ff0c18 315 BW_RTC_WAR_IERW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 316 }
mbed_official 146:f64d43ff0c18 317
mbed_official 146:f64d43ff0c18 318 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 319 * field Lock Register Write (LRW).
mbed_official 146:f64d43ff0c18 320 * @return true: Writes to the lock register complete normally.
mbed_official 146:f64d43ff0c18 321 * false: Writes to the lock register are ignored.
mbed_official 146:f64d43ff0c18 322 */
mbed_official 146:f64d43ff0c18 323 static inline bool rtc_hal_get_lock_wreg(void)
mbed_official 146:f64d43ff0c18 324 {
mbed_official 146:f64d43ff0c18 325 return (bool)BR_RTC_WAR_LRW;
mbed_official 146:f64d43ff0c18 326 }
mbed_official 146:f64d43ff0c18 327
mbed_official 146:f64d43ff0c18 328 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 329 * field Lock Register Write (LRW). Once cleared,
mbed_official 146:f64d43ff0c18 330 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 331 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 332 * @param enable true: Writes to the lock register complete normally.
mbed_official 146:f64d43ff0c18 333 * false: Writes to the lock register are ignored.
mbed_official 146:f64d43ff0c18 334 */
mbed_official 146:f64d43ff0c18 335 static inline void rtc_hal_set_lock_wreg(bool enable)
mbed_official 146:f64d43ff0c18 336 {
mbed_official 146:f64d43ff0c18 337 BW_RTC_WAR_LRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 338 }
mbed_official 146:f64d43ff0c18 339
mbed_official 146:f64d43ff0c18 340 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 341 * field Status Register Write (SRW). Once cleared,
mbed_official 146:f64d43ff0c18 342 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 343 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 344 * @return true: Writes to the status register complete normally.
mbed_official 146:f64d43ff0c18 345 * false: Writes to the status register are ignored.
mbed_official 146:f64d43ff0c18 346 */
mbed_official 146:f64d43ff0c18 347 static inline bool rtc_hal_get_status_wreg(void)
mbed_official 146:f64d43ff0c18 348 {
mbed_official 146:f64d43ff0c18 349 return (bool)BR_RTC_WAR_SRW;
mbed_official 146:f64d43ff0c18 350 }
mbed_official 146:f64d43ff0c18 351
mbed_official 146:f64d43ff0c18 352 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 353 * field Status Register Write (SRW). Once cleared,
mbed_official 146:f64d43ff0c18 354 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 355 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 356 * @param enable true: Writes to the status register complete normally.
mbed_official 146:f64d43ff0c18 357 * false: Writes to the status register are ignored.
mbed_official 146:f64d43ff0c18 358 */
mbed_official 146:f64d43ff0c18 359 static inline void rtc_hal_set_status_wreg(bool enable)
mbed_official 146:f64d43ff0c18 360 {
mbed_official 146:f64d43ff0c18 361 BW_RTC_WAR_SRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 362 }
mbed_official 146:f64d43ff0c18 363
mbed_official 146:f64d43ff0c18 364 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 365 * field Control Register Write (CRW). Once cleared,
mbed_official 146:f64d43ff0c18 366 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 367 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 368 * @return true: Writes to the control register complete normally.
mbed_official 146:f64d43ff0c18 369 * false: Writes to the control register are ignored.
mbed_official 146:f64d43ff0c18 370 */
mbed_official 146:f64d43ff0c18 371 static inline bool rtc_hal_get_control_wreg(void)
mbed_official 146:f64d43ff0c18 372 {
mbed_official 146:f64d43ff0c18 373 return (bool)BR_RTC_WAR_CRW;
mbed_official 146:f64d43ff0c18 374 }
mbed_official 146:f64d43ff0c18 375
mbed_official 146:f64d43ff0c18 376 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 377 * field Control Register Write (CRW). Once cleared,
mbed_official 146:f64d43ff0c18 378 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 379 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 380 * @param enable true: Writes to the control register complete normally.
mbed_official 146:f64d43ff0c18 381 * false: Writes to the control register are ignored.
mbed_official 146:f64d43ff0c18 382 */
mbed_official 146:f64d43ff0c18 383 static inline void rtc_hal_set_control_wreg(bool enable)
mbed_official 146:f64d43ff0c18 384 {
mbed_official 146:f64d43ff0c18 385 BW_RTC_WAR_CRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 386 }
mbed_official 146:f64d43ff0c18 387
mbed_official 146:f64d43ff0c18 388 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 389 * field Time Compensation Register Write (TCRW).
mbed_official 146:f64d43ff0c18 390 * @return true: Writes to the time compensation register complete normally.
mbed_official 146:f64d43ff0c18 391 * false: Writes to the time compensation register are ignored.
mbed_official 146:f64d43ff0c18 392 */
mbed_official 146:f64d43ff0c18 393 static inline bool rtc_hal_get_compensation_wreg(void)
mbed_official 146:f64d43ff0c18 394 {
mbed_official 146:f64d43ff0c18 395 return (bool)BR_RTC_WAR_TCRW;
mbed_official 146:f64d43ff0c18 396 }
mbed_official 146:f64d43ff0c18 397
mbed_official 146:f64d43ff0c18 398 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 399 * field Time Compensation Register Write (TCRW). Once cleared,
mbed_official 146:f64d43ff0c18 400 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 401 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 402 * @param enable true: Writes to the time compensation register complete normally.
mbed_official 146:f64d43ff0c18 403 * false: Writes to the time compensation register are ignored.
mbed_official 146:f64d43ff0c18 404 */
mbed_official 146:f64d43ff0c18 405 static inline void rtc_hal_set_compensation_wreg(bool enable)
mbed_official 146:f64d43ff0c18 406 {
mbed_official 146:f64d43ff0c18 407 BW_RTC_WAR_TCRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 408 }
mbed_official 146:f64d43ff0c18 409
mbed_official 146:f64d43ff0c18 410 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 411 * field Time Alarm Register Write (TARW). Once cleared,
mbed_official 146:f64d43ff0c18 412 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 413 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 414 * @return true: Writes to the time alarm register complete normally.
mbed_official 146:f64d43ff0c18 415 * false: Writes to the time alarm register are ignored.
mbed_official 146:f64d43ff0c18 416 */
mbed_official 146:f64d43ff0c18 417 static inline bool rtc_hal_get_alarm_wreg(void)
mbed_official 146:f64d43ff0c18 418 {
mbed_official 146:f64d43ff0c18 419 return (bool)BR_RTC_WAR_TARW;
mbed_official 146:f64d43ff0c18 420 }
mbed_official 146:f64d43ff0c18 421
mbed_official 146:f64d43ff0c18 422 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 423 * field Time Alarm Register Write (TARW). Once cleared,
mbed_official 146:f64d43ff0c18 424 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 425 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 426 * @param enable true: Writes to the time alarm register complete normally.
mbed_official 146:f64d43ff0c18 427 * false: Writes to the time alarm register are ignored.
mbed_official 146:f64d43ff0c18 428 */
mbed_official 146:f64d43ff0c18 429 static inline void rtc_hal_set_alarm_wreg(bool enable)
mbed_official 146:f64d43ff0c18 430 {
mbed_official 146:f64d43ff0c18 431 BW_RTC_WAR_TARW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 432 }
mbed_official 146:f64d43ff0c18 433
mbed_official 146:f64d43ff0c18 434 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 435 * field Time Prescaler Register Write (TPRW).
mbed_official 146:f64d43ff0c18 436 * @return true: Writes to the time prescaler register complete normally.
mbed_official 146:f64d43ff0c18 437 * false: Writes to the time prescaler register are ignored.
mbed_official 146:f64d43ff0c18 438 */
mbed_official 146:f64d43ff0c18 439 static inline bool rtc_hal_get_prescaler_wreg(void)
mbed_official 146:f64d43ff0c18 440 {
mbed_official 146:f64d43ff0c18 441 return (bool)BR_RTC_WAR_TPRW;
mbed_official 146:f64d43ff0c18 442 }
mbed_official 146:f64d43ff0c18 443
mbed_official 146:f64d43ff0c18 444 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 445 * field Time Prescaler Register Write (TPRW). Once cleared,
mbed_official 146:f64d43ff0c18 446 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 447 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 448 * @param enable true: Writes to the time prescaler register complete normally.
mbed_official 146:f64d43ff0c18 449 * false: Writes to the time prescaler register are ignored.
mbed_official 146:f64d43ff0c18 450 */
mbed_official 146:f64d43ff0c18 451 static inline void rtc_hal_set_prescaler_wreg(bool enable)
mbed_official 146:f64d43ff0c18 452 {
mbed_official 146:f64d43ff0c18 453 BW_RTC_WAR_TPRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 454 }
mbed_official 146:f64d43ff0c18 455
mbed_official 146:f64d43ff0c18 456 /*! @brief Reads the value of the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 457 * field Time Seconds Register Write (TSRW). Once cleared,
mbed_official 146:f64d43ff0c18 458 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 459 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 460 * @return true: Writes to the time seconds register complete normally.
mbed_official 146:f64d43ff0c18 461 * false: Writes to the time seconds register are ignored.
mbed_official 146:f64d43ff0c18 462 */
mbed_official 146:f64d43ff0c18 463 static inline bool rtc_hal_get_seconds_wreg(void)
mbed_official 146:f64d43ff0c18 464 {
mbed_official 146:f64d43ff0c18 465 return (bool)BR_RTC_WAR_TSRW;
mbed_official 146:f64d43ff0c18 466 }
mbed_official 146:f64d43ff0c18 467
mbed_official 146:f64d43ff0c18 468 /*! @brief Writes to the RTC Write Access Register (RTC_WAR),
mbed_official 146:f64d43ff0c18 469 * field Time Seconds Register Write (TSRW). Once cleared,
mbed_official 146:f64d43ff0c18 470 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 471 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 472 * @param enable true: Writes to the time seconds register complete normally.
mbed_official 146:f64d43ff0c18 473 * false: Writes to the time seconds register are ignored.
mbed_official 146:f64d43ff0c18 474 */
mbed_official 146:f64d43ff0c18 475 static inline void rtc_hal_set_seconds_wreg(bool enable)
mbed_official 146:f64d43ff0c18 476 {
mbed_official 146:f64d43ff0c18 477 BW_RTC_WAR_TSRW((uint32_t) enable);
mbed_official 146:f64d43ff0c18 478 }
mbed_official 146:f64d43ff0c18 479
mbed_official 146:f64d43ff0c18 480 #if (FSL_FEATURE_RTC_HAS_MONOTONIC == 1)
mbed_official 146:f64d43ff0c18 481 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 482 * field Monotonic Counter High Read (MCHR). Once cleared,
mbed_official 146:f64d43ff0c18 483 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 484 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 485 * @return true: Reads to the monotonic counter high register complete normally.
mbed_official 146:f64d43ff0c18 486 * false: Reads to the monotonic counter high register are ignored.
mbed_official 146:f64d43ff0c18 487 */
mbed_official 146:f64d43ff0c18 488 static inline bool rtc_hal_get_monotonic_hcount_rreg(void)
mbed_official 146:f64d43ff0c18 489 {
mbed_official 146:f64d43ff0c18 490 return (bool)BR_RTC_RAR_MCHR;
mbed_official 146:f64d43ff0c18 491 }
mbed_official 146:f64d43ff0c18 492
mbed_official 146:f64d43ff0c18 493 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 494 * field Monotonic Counter High Read (MCHR). Once cleared,
mbed_official 146:f64d43ff0c18 495 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 496 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 497 * @param enable true: Reads to the monotonic counter high register complete normally.
mbed_official 146:f64d43ff0c18 498 * false: Reads to the monotonic counter high register are ignored.
mbed_official 146:f64d43ff0c18 499 */
mbed_official 146:f64d43ff0c18 500 static inline void rtc_hal_set_monotonic_hcount_rreg(bool enable)
mbed_official 146:f64d43ff0c18 501 {
mbed_official 146:f64d43ff0c18 502 BW_RTC_RAR_MCHR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 503 }
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 506 * field Monotonic Counter Low Read (MCLR). Once cleared,
mbed_official 146:f64d43ff0c18 507 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 508 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 509 * @return true: Reads to the monotonic counter low register complete normally.
mbed_official 146:f64d43ff0c18 510 * false: Reads to the monotonic counter low register are ignored.
mbed_official 146:f64d43ff0c18 511 */
mbed_official 146:f64d43ff0c18 512 static inline bool rtc_hal_get_monotonic_lcount_rreg(void)
mbed_official 146:f64d43ff0c18 513 {
mbed_official 146:f64d43ff0c18 514 return (bool)BR_RTC_RAR_MCLR;
mbed_official 146:f64d43ff0c18 515 }
mbed_official 146:f64d43ff0c18 516
mbed_official 146:f64d43ff0c18 517 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 518 * field Monotonic Counter Low Read (MCLR). Once cleared,
mbed_official 146:f64d43ff0c18 519 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 520 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 521 * @param enable true: Reads to the monotonic counter low register complete normally.
mbed_official 146:f64d43ff0c18 522 * false: Reads to the monotonic counter low register are ignored.
mbed_official 146:f64d43ff0c18 523 */
mbed_official 146:f64d43ff0c18 524 static inline void rtc_hal_set_monotonic_lcount_rreg(bool enable)
mbed_official 146:f64d43ff0c18 525 {
mbed_official 146:f64d43ff0c18 526 BW_RTC_RAR_MCLR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 527 }
mbed_official 146:f64d43ff0c18 528
mbed_official 146:f64d43ff0c18 529 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 530 * field Monotonic Enable Register Read (MERR). Once cleared,
mbed_official 146:f64d43ff0c18 531 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 532 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 533 * @return true: Reads to the monotonic enable register complete normally.
mbed_official 146:f64d43ff0c18 534 * false: Reads to the monotonic enable register are ignored.
mbed_official 146:f64d43ff0c18 535 */
mbed_official 146:f64d43ff0c18 536 static inline bool rtc_hal_get_monotonic_enable_rreg(void)
mbed_official 146:f64d43ff0c18 537 {
mbed_official 146:f64d43ff0c18 538 return (bool)BR_RTC_RAR_MERR;
mbed_official 146:f64d43ff0c18 539 }
mbed_official 146:f64d43ff0c18 540
mbed_official 146:f64d43ff0c18 541 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 542 * field Monotonic Enable Register Read (MERR). Once cleared,
mbed_official 146:f64d43ff0c18 543 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 544 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 545 * @param enable true: Reads to the monotonic enable register complete normally.
mbed_official 146:f64d43ff0c18 546 * false: Reads to the monotonic enable register are ignored.
mbed_official 146:f64d43ff0c18 547 */
mbed_official 146:f64d43ff0c18 548 static inline void rtc_hal_set_monotonic_enable_rreg(bool enable)
mbed_official 146:f64d43ff0c18 549 {
mbed_official 146:f64d43ff0c18 550 BW_RTC_RAR_MERR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 551 }
mbed_official 146:f64d43ff0c18 552 #endif
mbed_official 146:f64d43ff0c18 553
mbed_official 146:f64d43ff0c18 554 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 555 * field Interrupt Enable Register Read (IERR). Once cleared,
mbed_official 146:f64d43ff0c18 556 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 557 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 558 * @return true: Reads to the interrupt enable register complete normally.
mbed_official 146:f64d43ff0c18 559 * false: Reads to the interrupt enable register are ignored.
mbed_official 146:f64d43ff0c18 560 */
mbed_official 146:f64d43ff0c18 561 static inline bool rtc_hal_get_interrupt_enable_rreg(void)
mbed_official 146:f64d43ff0c18 562 {
mbed_official 146:f64d43ff0c18 563 return (bool)BR_RTC_RAR_IERR;
mbed_official 146:f64d43ff0c18 564 }
mbed_official 146:f64d43ff0c18 565
mbed_official 146:f64d43ff0c18 566 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 567 * field Interrupt Enable Register Read (IERR). Once cleared,
mbed_official 146:f64d43ff0c18 568 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 569 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 570 * @param enable true: Reads to the interrupt enable register complete normally.
mbed_official 146:f64d43ff0c18 571 * false: Reads to the interrupt enable register are ignored.
mbed_official 146:f64d43ff0c18 572 */
mbed_official 146:f64d43ff0c18 573 static inline void rtc_hal_set_interrupt_enable_rreg(bool enable)
mbed_official 146:f64d43ff0c18 574 {
mbed_official 146:f64d43ff0c18 575 BW_RTC_RAR_IERR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 576 }
mbed_official 146:f64d43ff0c18 577
mbed_official 146:f64d43ff0c18 578 /*! @brief reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 579 * field Lock Register Read (LRR). Once cleared,
mbed_official 146:f64d43ff0c18 580 * this bit is only set by system reset. It is not affected by
mbed_official 146:f64d43ff0c18 581 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 582 * @return true: Reads to the lock register complete as normal.
mbed_official 146:f64d43ff0c18 583 * false: Reads to the lock register are ignored.
mbed_official 146:f64d43ff0c18 584 */
mbed_official 146:f64d43ff0c18 585 static inline bool rtc_hal_get_lock_rreg(void)
mbed_official 146:f64d43ff0c18 586 {
mbed_official 146:f64d43ff0c18 587 return (bool)BR_RTC_RAR_LRR;
mbed_official 146:f64d43ff0c18 588 }
mbed_official 146:f64d43ff0c18 589
mbed_official 146:f64d43ff0c18 590 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 591 * field Lock Register Read (LRR). Once cleared,
mbed_official 146:f64d43ff0c18 592 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 593 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 594 * @param enable true: Reads to the lock register complete normally.
mbed_official 146:f64d43ff0c18 595 * false: Reads to the lock register are ignored.
mbed_official 146:f64d43ff0c18 596 */
mbed_official 146:f64d43ff0c18 597 static inline void rtc_hal_set_lock_rreg(bool enable)
mbed_official 146:f64d43ff0c18 598 {
mbed_official 146:f64d43ff0c18 599 BW_RTC_RAR_LRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 600 }
mbed_official 146:f64d43ff0c18 601
mbed_official 146:f64d43ff0c18 602 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 603 * field Status Register Read (SRR). Once cleared,
mbed_official 146:f64d43ff0c18 604 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 605 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 606 * @return true: Reads to the status register complete normally.
mbed_official 146:f64d43ff0c18 607 * false: Reads to the status register are ignored.
mbed_official 146:f64d43ff0c18 608 */
mbed_official 146:f64d43ff0c18 609 static inline bool rtc_hal_get_status_rreg(void)
mbed_official 146:f64d43ff0c18 610 {
mbed_official 146:f64d43ff0c18 611 return (bool)BR_RTC_RAR_SRR;
mbed_official 146:f64d43ff0c18 612 }
mbed_official 146:f64d43ff0c18 613
mbed_official 146:f64d43ff0c18 614 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 615 * field Status Register Read (SRR). Once cleared,
mbed_official 146:f64d43ff0c18 616 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 617 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 618 * @param enable true: Reads to the status register complete normally.
mbed_official 146:f64d43ff0c18 619 * false: Reads to the status register are ignored.
mbed_official 146:f64d43ff0c18 620 */
mbed_official 146:f64d43ff0c18 621 static inline void rtc_hal_set_status_rreg(bool enable)
mbed_official 146:f64d43ff0c18 622 {
mbed_official 146:f64d43ff0c18 623 BW_RTC_RAR_SRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 624 }
mbed_official 146:f64d43ff0c18 625
mbed_official 146:f64d43ff0c18 626 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 627 * field Control Register Read (CRR). Once cleared,
mbed_official 146:f64d43ff0c18 628 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 629 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 630 * @return true: Reads to the control register complete normally.
mbed_official 146:f64d43ff0c18 631 * false: Reads to the control register are ignored.
mbed_official 146:f64d43ff0c18 632 */
mbed_official 146:f64d43ff0c18 633 static inline bool rtc_hal_get_control_rreg(void)
mbed_official 146:f64d43ff0c18 634 {
mbed_official 146:f64d43ff0c18 635 return (bool)BR_RTC_RAR_CRR;
mbed_official 146:f64d43ff0c18 636 }
mbed_official 146:f64d43ff0c18 637
mbed_official 146:f64d43ff0c18 638 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 639 * field Control Register Read (CRR). Once cleared,
mbed_official 146:f64d43ff0c18 640 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 641 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 642 * @param enable true: Reads to the control register complete normally.
mbed_official 146:f64d43ff0c18 643 * false: Reads to the control register are ignored.
mbed_official 146:f64d43ff0c18 644 */
mbed_official 146:f64d43ff0c18 645 static inline void rtc_hal_set_control_rreg(bool enable)
mbed_official 146:f64d43ff0c18 646 {
mbed_official 146:f64d43ff0c18 647 BW_RTC_RAR_CRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 648 }
mbed_official 146:f64d43ff0c18 649
mbed_official 146:f64d43ff0c18 650 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 651 * field Time Compensation Register Read (TCRR). Once cleared,
mbed_official 146:f64d43ff0c18 652 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 653 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 654 * @return true: Reads to the time compensation register complete normally.
mbed_official 146:f64d43ff0c18 655 * false: Reads to the time compensation register are ignored.
mbed_official 146:f64d43ff0c18 656 */
mbed_official 146:f64d43ff0c18 657 static inline bool rtc_hal_get_compensation_rreg(void)
mbed_official 146:f64d43ff0c18 658 {
mbed_official 146:f64d43ff0c18 659 return (bool)BR_RTC_RAR_TCRR;
mbed_official 146:f64d43ff0c18 660 }
mbed_official 146:f64d43ff0c18 661
mbed_official 146:f64d43ff0c18 662 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 663 * field Time Compensation Register Read (TCRR). Once cleared,
mbed_official 146:f64d43ff0c18 664 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 665 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 666 * @param enable true: Reads to the time compensation register complete normally.
mbed_official 146:f64d43ff0c18 667 * false: Reads to the time compensation register are ignored.
mbed_official 146:f64d43ff0c18 668 */
mbed_official 146:f64d43ff0c18 669 static inline void rtc_hal_set_compensation_rreg(bool enable)
mbed_official 146:f64d43ff0c18 670 {
mbed_official 146:f64d43ff0c18 671 BW_RTC_RAR_TCRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 672 }
mbed_official 146:f64d43ff0c18 673
mbed_official 146:f64d43ff0c18 674 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 675 * field Time Alarm Register Read (TARR). Once cleared,
mbed_official 146:f64d43ff0c18 676 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 677 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 678 * @return true: Reads to the time alarm register complete normally.
mbed_official 146:f64d43ff0c18 679 * false: Reads to the time alarm register are ignored.
mbed_official 146:f64d43ff0c18 680 */
mbed_official 146:f64d43ff0c18 681 static inline bool rtc_hal_get_alarm_rreg(void)
mbed_official 146:f64d43ff0c18 682 {
mbed_official 146:f64d43ff0c18 683 return (bool)BR_RTC_RAR_TARR;
mbed_official 146:f64d43ff0c18 684 }
mbed_official 146:f64d43ff0c18 685
mbed_official 146:f64d43ff0c18 686 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 687 * field Time Alarm Register Read (TARR). Once cleared,
mbed_official 146:f64d43ff0c18 688 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 689 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 690 * @param enable true: Reads to the time alarm register complete normally.
mbed_official 146:f64d43ff0c18 691 * false: Reads to the time alarm register are ignored.
mbed_official 146:f64d43ff0c18 692 */
mbed_official 146:f64d43ff0c18 693 static inline void rtc_hal_set_alarm_rreg(bool enable)
mbed_official 146:f64d43ff0c18 694 {
mbed_official 146:f64d43ff0c18 695 BW_RTC_RAR_TARR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 696 }
mbed_official 146:f64d43ff0c18 697
mbed_official 146:f64d43ff0c18 698 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 699 * field Time Prescaler Register Read (TPRR). Once cleared,
mbed_official 146:f64d43ff0c18 700 * this bit is only set by the system reset. It is not affected by
mbed_official 146:f64d43ff0c18 701 * VBAT POR or software reset.
mbed_official 146:f64d43ff0c18 702 * @return true: Reads to the time prescaler register complete normally.
mbed_official 146:f64d43ff0c18 703 * false: Reads to the time prescaler register are ignored.
mbed_official 146:f64d43ff0c18 704 */
mbed_official 146:f64d43ff0c18 705 static inline bool rtc_hal_get_prescaler_rreg(void)
mbed_official 146:f64d43ff0c18 706 {
mbed_official 146:f64d43ff0c18 707 return (bool)BR_RTC_RAR_TPRR;
mbed_official 146:f64d43ff0c18 708 }
mbed_official 146:f64d43ff0c18 709
mbed_official 146:f64d43ff0c18 710 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 711 * field Time Prescaler Register Read (TPRR). Once cleared,
mbed_official 146:f64d43ff0c18 712 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 713 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 714 * @param enable true: Reads to the time prescaler register complete normally.
mbed_official 146:f64d43ff0c18 715 * false: Reads to the time prescaler register are ignored.
mbed_official 146:f64d43ff0c18 716 */
mbed_official 146:f64d43ff0c18 717 static inline void rtc_hal_set_prescaler_rreg(bool enable)
mbed_official 146:f64d43ff0c18 718 {
mbed_official 146:f64d43ff0c18 719
mbed_official 146:f64d43ff0c18 720 BW_RTC_RAR_TPRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 721 }
mbed_official 146:f64d43ff0c18 722
mbed_official 146:f64d43ff0c18 723 /*! @brief Reads the value of the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 724 * field Time Seconds Register Read (TSRR). Once cleared,
mbed_official 146:f64d43ff0c18 725 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 726 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 727 * @return true: Reads to the time seconds register complete normally.
mbed_official 146:f64d43ff0c18 728 * false: Reads to the time seconds register are ignored.
mbed_official 146:f64d43ff0c18 729 */
mbed_official 146:f64d43ff0c18 730 static inline bool rtc_hal_get_seconds_rreg(void)
mbed_official 146:f64d43ff0c18 731 {
mbed_official 146:f64d43ff0c18 732 return (bool)BR_RTC_RAR_TSRR;
mbed_official 146:f64d43ff0c18 733 }
mbed_official 146:f64d43ff0c18 734
mbed_official 146:f64d43ff0c18 735 /*! @brief Writes to the RTC Read Access Register (RTC_RAR),
mbed_official 146:f64d43ff0c18 736 * field Time Seconds Register Read (TSRR). Once cleared,
mbed_official 146:f64d43ff0c18 737 * this bit is only set by the system reset. It is not affected by the
mbed_official 146:f64d43ff0c18 738 * VBAT POR or the software reset.
mbed_official 146:f64d43ff0c18 739 * @param enable true: Reads to the time seconds register complete normally.
mbed_official 146:f64d43ff0c18 740 * false: Reads to the time seconds register are ignored.
mbed_official 146:f64d43ff0c18 741 */
mbed_official 146:f64d43ff0c18 742 static inline void rtc_hal_set_seconds_rreg(bool enable)
mbed_official 146:f64d43ff0c18 743 {
mbed_official 146:f64d43ff0c18 744 BW_RTC_RAR_TSRR((uint32_t) enable);
mbed_official 146:f64d43ff0c18 745 }
mbed_official 146:f64d43ff0c18 746
mbed_official 146:f64d43ff0c18 747
mbed_official 146:f64d43ff0c18 748 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 749 }
mbed_official 146:f64d43ff0c18 750 #endif
mbed_official 146:f64d43ff0c18 751
mbed_official 146:f64d43ff0c18 752 #endif
mbed_official 146:f64d43ff0c18 753
mbed_official 146:f64d43ff0c18 754 /*! @}*/
mbed_official 146:f64d43ff0c18 755
mbed_official 146:f64d43ff0c18 756 #endif /* __FSL_RTC_HAL_MONOTONIC_H__*/
mbed_official 146:f64d43ff0c18 757
mbed_official 146:f64d43ff0c18 758 /*******************************************************************************
mbed_official 146:f64d43ff0c18 759 * EOF
mbed_official 146:f64d43ff0c18 760 ******************************************************************************/