mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/mcg/fsl_mcg_hal.h@146:f64d43ff0c18
Child:
324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30
mbed_official 146:f64d43ff0c18 31 #if !defined(__FSL_MCG_HAL_H__)
mbed_official 146:f64d43ff0c18 32 #define __FSL_MCG_HAL_H__
mbed_official 146:f64d43ff0c18 33
mbed_official 146:f64d43ff0c18 34 #include <stdint.h>
mbed_official 146:f64d43ff0c18 35 #include <stdbool.h>
mbed_official 146:f64d43ff0c18 36 #include <assert.h>
mbed_official 146:f64d43ff0c18 37 #include "fsl_device_registers.h"
mbed_official 146:f64d43ff0c18 38 #include "fsl_mcg_features.h"
mbed_official 146:f64d43ff0c18 39
mbed_official 146:f64d43ff0c18 40 /*! @addtogroup mcg_hal*/
mbed_official 146:f64d43ff0c18 41 /*! @{*/
mbed_official 146:f64d43ff0c18 42
mbed_official 146:f64d43ff0c18 43 /*! @file fsl_mcg_hal.h */
mbed_official 146:f64d43ff0c18 44
mbed_official 146:f64d43ff0c18 45 /*******************************************************************************
mbed_official 146:f64d43ff0c18 46 * Definitions
mbed_official 146:f64d43ff0c18 47 ******************************************************************************/
mbed_official 146:f64d43ff0c18 48 /*! @brief MCG constant definitions*/
mbed_official 146:f64d43ff0c18 49 enum _mcg_constant
mbed_official 146:f64d43ff0c18 50 {
mbed_official 146:f64d43ff0c18 51 kMcgConstant1 = (1u),
mbed_official 146:f64d43ff0c18 52 kMcgConstant5 = (5u),
mbed_official 146:f64d43ff0c18 53
mbed_official 146:f64d43ff0c18 54 kMcgConstant640 = (640u),
mbed_official 146:f64d43ff0c18 55 kMcgConstant1280 = (1280u),
mbed_official 146:f64d43ff0c18 56 kMcgConstant1920 = (1920u),
mbed_official 146:f64d43ff0c18 57 kMcgConstant2560 = (2560u),
mbed_official 146:f64d43ff0c18 58 kMcgConstant732 = (732u),
mbed_official 146:f64d43ff0c18 59 kMcgConstant1464 = (1464u),
mbed_official 146:f64d43ff0c18 60 kMcgConstant2197 = (2197u),
mbed_official 146:f64d43ff0c18 61 kMcgConstant2929 = (2929u),
mbed_official 146:f64d43ff0c18 62
mbed_official 146:f64d43ff0c18 63 kMcgConstantHex20 = (0x20u),
mbed_official 146:f64d43ff0c18 64 kMcgConstantHex40 = (0x40u),
mbed_official 146:f64d43ff0c18 65 kMcgConstantHex60 = (0x60u),
mbed_official 146:f64d43ff0c18 66 kMcgConstantHex80 = (0x80u),
mbed_official 146:f64d43ff0c18 67 kMcgConstantHexA0 = (0xA0u),
mbed_official 146:f64d43ff0c18 68 kMcgConstantHexC0 = (0xC0u),
mbed_official 146:f64d43ff0c18 69 kMcgConstantHexE0 = (0xE0u)
mbed_official 146:f64d43ff0c18 70 };
mbed_official 146:f64d43ff0c18 71
mbed_official 146:f64d43ff0c18 72 /*! @brief MCG clock source select */
mbed_official 146:f64d43ff0c18 73 typedef enum _mcg_clock_select
mbed_official 146:f64d43ff0c18 74 {
mbed_official 146:f64d43ff0c18 75 kMcgClockSelectOut, /* Output of FLL or PLLCS is selected(depends on PLLS bit) */
mbed_official 146:f64d43ff0c18 76 kMcgClockSelectIn, /* Internal reference clock is selected */
mbed_official 146:f64d43ff0c18 77 kMcgClockSelectExt, /* External reference clock is selected */
mbed_official 146:f64d43ff0c18 78 kMcgClockSelectReserved
mbed_official 146:f64d43ff0c18 79 } mcg_clock_select_t;
mbed_official 146:f64d43ff0c18 80
mbed_official 146:f64d43ff0c18 81 /*! @brief MCG internal reference clock source select */
mbed_official 146:f64d43ff0c18 82 typedef enum _mcg_iref_clock_source
mbed_official 146:f64d43ff0c18 83 {
mbed_official 146:f64d43ff0c18 84 kMcgIrefClockSourceExt, /* External reference clock is selected */
mbed_official 146:f64d43ff0c18 85 kMcgIrefClockSourceSlow /* The slow internal reference clock is selected */
mbed_official 146:f64d43ff0c18 86 } mcg_iref_clock_source_t;
mbed_official 146:f64d43ff0c18 87
mbed_official 146:f64d43ff0c18 88 /*! @brief MCG frequency range select */
mbed_official 146:f64d43ff0c18 89 typedef enum _mcg_freq_range_select
mbed_official 146:f64d43ff0c18 90 {
mbed_official 146:f64d43ff0c18 91 kMcgFreqRangeSelectLow, /* Low frequency range selected for the crystal OSC */
mbed_official 146:f64d43ff0c18 92 kMcgFreqRangeSelectHigh, /* High frequency range selected for the crystal OSC */
mbed_official 146:f64d43ff0c18 93 kMcgFreqRangeSelectVeryHigh, /* Very High frequency range selected for the crystal OSC */
mbed_official 146:f64d43ff0c18 94 kMcgFreqRangeSelectVeryHigh1 /* Very High frequency range selected for the crystal OSC */
mbed_official 146:f64d43ff0c18 95 } mcg_freq_range_select_t;
mbed_official 146:f64d43ff0c18 96
mbed_official 146:f64d43ff0c18 97 /*! @brief MCG high gain oscillator select */
mbed_official 146:f64d43ff0c18 98 typedef enum _mcg_hgo_select
mbed_official 146:f64d43ff0c18 99 {
mbed_official 146:f64d43ff0c18 100 kMcgHgoSelectLow, /* Configure crystal oscillator for low-power operation */
mbed_official 146:f64d43ff0c18 101 kMcgHgoSelectHigh /* Configure crystal oscillator for high-gain operation */
mbed_official 146:f64d43ff0c18 102 } mcg_hgo_select_t;
mbed_official 146:f64d43ff0c18 103
mbed_official 146:f64d43ff0c18 104 /*! @brief MCG high gain oscillator select */
mbed_official 146:f64d43ff0c18 105 typedef enum _mcg_eref_clock_select
mbed_official 146:f64d43ff0c18 106 {
mbed_official 146:f64d43ff0c18 107 kMcgErefClockSelectExt, /* External reference clock requested */
mbed_official 146:f64d43ff0c18 108 kMcgErefClockSelectOsc /* Oscillator requested */
mbed_official 146:f64d43ff0c18 109 } mcg_eref_clock_select_t;
mbed_official 146:f64d43ff0c18 110
mbed_official 146:f64d43ff0c18 111 /*! @brief MCG low power select */
mbed_official 146:f64d43ff0c18 112 typedef enum _mcg_lp_select
mbed_official 146:f64d43ff0c18 113 {
mbed_official 146:f64d43ff0c18 114 kMcgLpSelectNormal, /* FLL (or PLL) is not disabled in bypass modes */
mbed_official 146:f64d43ff0c18 115 kMcgLpSelectLowPower /* FLL (or PLL) is disabled in bypass modes (lower power) */
mbed_official 146:f64d43ff0c18 116 } mcg_lp_select_t;
mbed_official 146:f64d43ff0c18 117
mbed_official 146:f64d43ff0c18 118 /*! @brief MCG internal reference clock select */
mbed_official 146:f64d43ff0c18 119 typedef enum _mcg_iref_clock_select
mbed_official 146:f64d43ff0c18 120 {
mbed_official 146:f64d43ff0c18 121 kMcgIrefClockSelectSlow, /* Slow internal reference clock selected */
mbed_official 146:f64d43ff0c18 122 kMcgIrefClockSelectFast /* Fast internal reference clock selected */
mbed_official 146:f64d43ff0c18 123 } mcg_iref_clock_select_t;
mbed_official 146:f64d43ff0c18 124
mbed_official 146:f64d43ff0c18 125 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
mbed_official 146:f64d43ff0c18 126 typedef enum _mcg_dmx32_select
mbed_official 146:f64d43ff0c18 127 {
mbed_official 146:f64d43ff0c18 128 kMcgDmx32Default, /* DCO has a default range of 25% */
mbed_official 146:f64d43ff0c18 129 kMcgDmx32Fine /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
mbed_official 146:f64d43ff0c18 130 } mcg_dmx32_select_t;
mbed_official 146:f64d43ff0c18 131
mbed_official 146:f64d43ff0c18 132 /*! @brief MCG DCO range select */
mbed_official 146:f64d43ff0c18 133 typedef enum _mcg_dco_range_select
mbed_official 146:f64d43ff0c18 134 {
mbed_official 146:f64d43ff0c18 135 kMcgDcoRangeSelectLow, /* Low frequency range */
mbed_official 146:f64d43ff0c18 136 kMcgDcoRangeSelectMid, /* Mid frequency range*/
mbed_official 146:f64d43ff0c18 137 kMcgDcoRangeSelectMidHigh, /* Mid-High frequency range */
mbed_official 146:f64d43ff0c18 138 kMcgDcoRangeSelectHigh /* High frequency range */
mbed_official 146:f64d43ff0c18 139 } mcg_dco_range_select_t;
mbed_official 146:f64d43ff0c18 140
mbed_official 146:f64d43ff0c18 141 /*! @brief MCG PLL external reference clock select */
mbed_official 146:f64d43ff0c18 142 typedef enum _mcg_pll_eref_clock_select
mbed_official 146:f64d43ff0c18 143 {
mbed_official 146:f64d43ff0c18 144 kMcgPllErefClockSelectOsc0, /* Selects OSC0 clock source as its external reference clock */
mbed_official 146:f64d43ff0c18 145 kMcgPllErefClockSelectOsc1 /* Selects OSC1 clock source as its external reference clock */
mbed_official 146:f64d43ff0c18 146 } mcg_pll_eref_clock_select_t;
mbed_official 146:f64d43ff0c18 147
mbed_official 146:f64d43ff0c18 148 /*! @brief MCG PLL select */
mbed_official 146:f64d43ff0c18 149 typedef enum _mcg_pll_select
mbed_official 146:f64d43ff0c18 150 {
mbed_official 146:f64d43ff0c18 151 kMcgPllSelectFll, /* FLL is selected */
mbed_official 146:f64d43ff0c18 152 kMcgPllSelectPllcs /* PLLCS output clock is selected */
mbed_official 146:f64d43ff0c18 153 } mcg_pll_select_t;
mbed_official 146:f64d43ff0c18 154
mbed_official 146:f64d43ff0c18 155 /*! @brief MCG loss of lock status */
mbed_official 146:f64d43ff0c18 156 typedef enum _mcg_lols_status
mbed_official 146:f64d43ff0c18 157 {
mbed_official 146:f64d43ff0c18 158 kMcgLolsNotLostLock, /* PLL has not lost lock since LOLS 0 was last cleared */
mbed_official 146:f64d43ff0c18 159 kMcgLolsLostLock /* PLL has lost lock since LOLS 0 was last cleared */
mbed_official 146:f64d43ff0c18 160 } mcg_lols_status_t;
mbed_official 146:f64d43ff0c18 161
mbed_official 146:f64d43ff0c18 162 /*! @brief MCG lock status */
mbed_official 146:f64d43ff0c18 163 typedef enum _mcg_lock_status
mbed_official 146:f64d43ff0c18 164 {
mbed_official 146:f64d43ff0c18 165 kMcgLockUnlocked, /* PLL is currently unlocked */
mbed_official 146:f64d43ff0c18 166 kMcgLockLocked /* PLL is currently locked */
mbed_official 146:f64d43ff0c18 167 } mcg_lock_status_t;
mbed_official 146:f64d43ff0c18 168
mbed_official 146:f64d43ff0c18 169 /*! @brief MCG clock status */
mbed_official 146:f64d43ff0c18 170 typedef enum _mcg_pllst_status
mbed_official 146:f64d43ff0c18 171 {
mbed_official 146:f64d43ff0c18 172 kMcgPllstFll, /* Source of PLLS clock is FLL clock */
mbed_official 146:f64d43ff0c18 173 kMcgPllstPllcs /* Source of PLLS clock is PLLCS output clock */
mbed_official 146:f64d43ff0c18 174 } mcg_pllst_status_t;
mbed_official 146:f64d43ff0c18 175
mbed_official 146:f64d43ff0c18 176 /*! @brief MCG iref status */
mbed_official 146:f64d43ff0c18 177 typedef enum _mcg_irefst_status
mbed_official 146:f64d43ff0c18 178 {
mbed_official 146:f64d43ff0c18 179 kMcgIrefstExt, /* FLL reference clock is the external reference clock */
mbed_official 146:f64d43ff0c18 180 kMcgIrefstInt /* FLL reference clock is the internal reference clock */
mbed_official 146:f64d43ff0c18 181 } mcg_irefst_status_t;
mbed_official 146:f64d43ff0c18 182
mbed_official 146:f64d43ff0c18 183 /*! @brief MCG clock mode status */
mbed_official 146:f64d43ff0c18 184 typedef enum _mcg_clkst_status
mbed_official 146:f64d43ff0c18 185 {
mbed_official 146:f64d43ff0c18 186 kMcgClkstFll, /* Output of the FLL is selected (reset default) */
mbed_official 146:f64d43ff0c18 187 kMcgClkstIref, /* Internal reference clock is selected */
mbed_official 146:f64d43ff0c18 188 kMcgClkstEref, /* External reference clock is selected */
mbed_official 146:f64d43ff0c18 189 kMcgClkstPll /* Output of the PLL is selected */
mbed_official 146:f64d43ff0c18 190 } mcg_clkst_status_t;
mbed_official 146:f64d43ff0c18 191
mbed_official 146:f64d43ff0c18 192 /*! @brief MCG ircst status */
mbed_official 146:f64d43ff0c18 193 typedef enum _mcg_ircst_status
mbed_official 146:f64d43ff0c18 194 {
mbed_official 146:f64d43ff0c18 195 kMcgIrcstSlow, /* internal reference clock is the slow clock (32 kHz IRC) */
mbed_official 146:f64d43ff0c18 196 kMcgIrcstFast /* internal reference clock is the fast clock (2 MHz IRC) */
mbed_official 146:f64d43ff0c18 197 } mcg_ircst_status_t;
mbed_official 146:f64d43ff0c18 198
mbed_official 146:f64d43ff0c18 199 /*! @brief MCG auto trim fail status */
mbed_official 146:f64d43ff0c18 200 typedef enum _mcg_atmf_status
mbed_official 146:f64d43ff0c18 201 {
mbed_official 146:f64d43ff0c18 202 kMcgAtmfNormal, /* Automatic Trim Machine completed normally */
mbed_official 146:f64d43ff0c18 203 kMcgAtmfFail /* Automatic Trim Machine failed */
mbed_official 146:f64d43ff0c18 204 } mcg_atmf_status_t;
mbed_official 146:f64d43ff0c18 205
mbed_official 146:f64d43ff0c18 206 /*! @brief MCG loss of clock status */
mbed_official 146:f64d43ff0c18 207 typedef enum _mcg_locs0_status
mbed_official 146:f64d43ff0c18 208 {
mbed_official 146:f64d43ff0c18 209 kMcgLocs0NotOccured, /* Loss of OSC0 has not occurred */
mbed_official 146:f64d43ff0c18 210 kMcgLocs0Occured /* Loss of OSC0 has occurred */
mbed_official 146:f64d43ff0c18 211 } mcg_locs0_status_t;
mbed_official 146:f64d43ff0c18 212
mbed_official 146:f64d43ff0c18 213 /*! @brief MCG Automatic Trim Machine Select */
mbed_official 146:f64d43ff0c18 214 typedef enum _mcg_atms_select
mbed_official 146:f64d43ff0c18 215 {
mbed_official 146:f64d43ff0c18 216 kMcgAtmsSelect32k, /* 32 kHz Internal Reference Clock selected */
mbed_official 146:f64d43ff0c18 217 kMcgAtmsSelect4m /* 4 MHz Internal Reference Clock selected */
mbed_official 146:f64d43ff0c18 218 } mcg_atms_select_t;
mbed_official 146:f64d43ff0c18 219
mbed_official 146:f64d43ff0c18 220 /*! @brief MCG OSC Clock Select */
mbed_official 146:f64d43ff0c18 221 typedef enum _mcg_oscsel_select
mbed_official 146:f64d43ff0c18 222 {
mbed_official 146:f64d43ff0c18 223 kMcgOscselOsc, /* Selects System Oscillator (OSCCLK) */
mbed_official 146:f64d43ff0c18 224 kMcgOscselRtc, /* Selects 32 kHz RTC Oscillator */
mbed_official 146:f64d43ff0c18 225 kMcgOscselIrc /* Selects 48 MkHz IRC Oscillator */
mbed_official 146:f64d43ff0c18 226 } mcg_oscsel_select_t;
mbed_official 146:f64d43ff0c18 227
mbed_official 146:f64d43ff0c18 228 /*! @brief MCG loss of clock status */
mbed_official 146:f64d43ff0c18 229 typedef enum _mcg_locs1_status
mbed_official 146:f64d43ff0c18 230 {
mbed_official 146:f64d43ff0c18 231 kMcgLocs1NotOccured, /* Loss of RTC has not occurred */
mbed_official 146:f64d43ff0c18 232 kMcgLocs1Occured /* Loss of RTC has occurred */
mbed_official 146:f64d43ff0c18 233 } mcg_locs1_status_t;
mbed_official 146:f64d43ff0c18 234
mbed_official 146:f64d43ff0c18 235 /*! @brief MCG PLLCS select */
mbed_official 146:f64d43ff0c18 236 typedef enum _mcg_pllcs_select
mbed_official 146:f64d43ff0c18 237 {
mbed_official 146:f64d43ff0c18 238 kMcgPllcsSelectPll0, /* PLL0 output clock is selected */
mbed_official 146:f64d43ff0c18 239 kMcgPllcsSelectPll1, /* PLL1 output clock is selected */
mbed_official 146:f64d43ff0c18 240 } mcg_pllcs_select_t;
mbed_official 146:f64d43ff0c18 241
mbed_official 146:f64d43ff0c18 242 /*! @brief MCG loss of clock status */
mbed_official 146:f64d43ff0c18 243 typedef enum _mcg_locs2_status
mbed_official 146:f64d43ff0c18 244 {
mbed_official 146:f64d43ff0c18 245 kMcgLocs2NotOccured, /* Loss of OSC1 has not occurred */
mbed_official 146:f64d43ff0c18 246 kMcgLocs2Occured /* Loss of OSC1 has occurred */
mbed_official 146:f64d43ff0c18 247 } mcg_locs2_status_t;
mbed_official 146:f64d43ff0c18 248
mbed_official 146:f64d43ff0c18 249 /*******************************************************************************
mbed_official 146:f64d43ff0c18 250 * API
mbed_official 146:f64d43ff0c18 251 ******************************************************************************/
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 254 extern "C" {
mbed_official 146:f64d43ff0c18 255 #endif /* __cplusplus*/
mbed_official 146:f64d43ff0c18 256
mbed_official 146:f64d43ff0c18 257 /*! @name MCG out clock access API*/
mbed_official 146:f64d43ff0c18 258 /*@{*/
mbed_official 146:f64d43ff0c18 259
mbed_official 146:f64d43ff0c18 260 /*!
mbed_official 146:f64d43ff0c18 261 * @brief Gets the current MCG FLL clock.
mbed_official 146:f64d43ff0c18 262 *
mbed_official 146:f64d43ff0c18 263 * This function returns the mcgfllclk value in frequency(Hertz) based on the
mbed_official 146:f64d43ff0c18 264 * current MCG configurations and settings. FLL should be properly configured
mbed_official 146:f64d43ff0c18 265 * in order to get the valid value.
mbed_official 146:f64d43ff0c18 266 *
mbed_official 146:f64d43ff0c18 267 * @param none
mbed_official 146:f64d43ff0c18 268 * @return value Frequency value in Hertz of the mcgpllclk.
mbed_official 146:f64d43ff0c18 269 */
mbed_official 146:f64d43ff0c18 270 uint32_t clock_hal_get_fllclk(void);
mbed_official 146:f64d43ff0c18 271
mbed_official 146:f64d43ff0c18 272 /*!
mbed_official 146:f64d43ff0c18 273 * @brief Gets the current MCG PLL/PLL0 clock.
mbed_official 146:f64d43ff0c18 274 *
mbed_official 146:f64d43ff0c18 275 * This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based
mbed_official 146:f64d43ff0c18 276 * on the current MCG configurations and settings. PLL/PLL0 should be properly
mbed_official 146:f64d43ff0c18 277 * configured in order to get the valid value.
mbed_official 146:f64d43ff0c18 278 *
mbed_official 146:f64d43ff0c18 279 * @param none
mbed_official 146:f64d43ff0c18 280 * @return value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.
mbed_official 146:f64d43ff0c18 281 */
mbed_official 146:f64d43ff0c18 282 uint32_t clock_hal_get_pll0clk(void);
mbed_official 146:f64d43ff0c18 283
mbed_official 146:f64d43ff0c18 284 #if FSL_FEATURE_MCG_HAS_PLL1
mbed_official 146:f64d43ff0c18 285 /*!
mbed_official 146:f64d43ff0c18 286 * @brief Gets the current MCG PLL1 clock.
mbed_official 146:f64d43ff0c18 287 *
mbed_official 146:f64d43ff0c18 288 * This function returns the mcgpll1clk value in frequency (Hertz) based
mbed_official 146:f64d43ff0c18 289 * on the current MCG configurations and settings. PLL1 should be properly configured
mbed_official 146:f64d43ff0c18 290 * in order to get the valid value.
mbed_official 146:f64d43ff0c18 291 *
mbed_official 146:f64d43ff0c18 292 * @param none
mbed_official 146:f64d43ff0c18 293 * @return value Frequency value in Hertz of mcgpll1clk.
mbed_official 146:f64d43ff0c18 294 */
mbed_official 146:f64d43ff0c18 295 uint32_t clock_hal_get_pll1clk(void);
mbed_official 146:f64d43ff0c18 296 #endif
mbed_official 146:f64d43ff0c18 297
mbed_official 146:f64d43ff0c18 298 /*!
mbed_official 146:f64d43ff0c18 299 * @brief Gets the current MCG IR clock.
mbed_official 146:f64d43ff0c18 300 *
mbed_official 146:f64d43ff0c18 301 * This function returns the mcgirclk value in frequency (Hertz) based
mbed_official 146:f64d43ff0c18 302 * on the current MCG configurations and settings. It does not check if the
mbed_official 146:f64d43ff0c18 303 * mcgirclk is enabled or not, just calculate and return the value.
mbed_official 146:f64d43ff0c18 304 *
mbed_official 146:f64d43ff0c18 305 * @param none
mbed_official 146:f64d43ff0c18 306 * @return value Frequency value in Hertz of the mcgirclk.
mbed_official 146:f64d43ff0c18 307 */
mbed_official 146:f64d43ff0c18 308 uint32_t clock_hal_get_irclk(void);
mbed_official 146:f64d43ff0c18 309
mbed_official 146:f64d43ff0c18 310 /*!
mbed_official 146:f64d43ff0c18 311 * @brief Gets the current MCG out clock.
mbed_official 146:f64d43ff0c18 312 *
mbed_official 146:f64d43ff0c18 313 * This function returns the mcgoutclk value in frequency (Hertz) based on the
mbed_official 146:f64d43ff0c18 314 * current MCG configurations and settings. The configuration should be
mbed_official 146:f64d43ff0c18 315 * properly done in order to get the valid value.
mbed_official 146:f64d43ff0c18 316 *
mbed_official 146:f64d43ff0c18 317 * @param none
mbed_official 146:f64d43ff0c18 318 * @return value Frequency value in Hertz of mcgoutclk.
mbed_official 146:f64d43ff0c18 319 */
mbed_official 146:f64d43ff0c18 320 uint32_t clock_hal_get_outclk(void);
mbed_official 146:f64d43ff0c18 321
mbed_official 146:f64d43ff0c18 322 /*@}*/
mbed_official 146:f64d43ff0c18 323
mbed_official 146:f64d43ff0c18 324 /*! @name MCG control register access API*/
mbed_official 146:f64d43ff0c18 325 /*@{*/
mbed_official 146:f64d43ff0c18 326
mbed_official 146:f64d43ff0c18 327 /*!
mbed_official 146:f64d43ff0c18 328 * @brief Sets the Clock Source Select
mbed_official 146:f64d43ff0c18 329 *
mbed_official 146:f64d43ff0c18 330 * This function selects the clock source for the MCGOUTCLK.
mbed_official 146:f64d43ff0c18 331 *
mbed_official 146:f64d43ff0c18 332 * @param select Clock source selection
mbed_official 146:f64d43ff0c18 333 * - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
mbed_official 146:f64d43ff0c18 334 * - 01: Internal reference clock is selected.
mbed_official 146:f64d43ff0c18 335 * - 10: External reference clock is selected.
mbed_official 146:f64d43ff0c18 336 * - 11: Reserved.
mbed_official 146:f64d43ff0c18 337 */
mbed_official 146:f64d43ff0c18 338 static inline void clock_set_clks(mcg_clock_select_t select)
mbed_official 146:f64d43ff0c18 339 {
mbed_official 146:f64d43ff0c18 340 BW_MCG_C1_CLKS(select);
mbed_official 146:f64d43ff0c18 341 }
mbed_official 146:f64d43ff0c18 342
mbed_official 146:f64d43ff0c18 343 /*!
mbed_official 146:f64d43ff0c18 344 * @brief Gets the Clock Source Select.
mbed_official 146:f64d43ff0c18 345 *
mbed_official 146:f64d43ff0c18 346 * This function gets the select of the clock source for the MCGOUTCLK.
mbed_official 146:f64d43ff0c18 347 *
mbed_official 146:f64d43ff0c18 348 * @return select Clock source selection
mbed_official 146:f64d43ff0c18 349 */
mbed_official 146:f64d43ff0c18 350 static inline mcg_clock_select_t clock_get_clks(void)
mbed_official 146:f64d43ff0c18 351 {
mbed_official 146:f64d43ff0c18 352 return (mcg_clock_select_t)BR_MCG_C1_CLKS;
mbed_official 146:f64d43ff0c18 353 }
mbed_official 146:f64d43ff0c18 354
mbed_official 146:f64d43ff0c18 355 /*!
mbed_official 146:f64d43ff0c18 356 * @brief Sets the FLL External Reference Divider.
mbed_official 146:f64d43ff0c18 357 *
mbed_official 146:f64d43ff0c18 358 * This function sets the FLL External Reference Divider.
mbed_official 146:f64d43ff0c18 359 *
mbed_official 146:f64d43ff0c18 360 * @param setting Divider setting
mbed_official 146:f64d43ff0c18 361 */
mbed_official 146:f64d43ff0c18 362 static inline void clock_set_frdiv(uint8_t setting)
mbed_official 146:f64d43ff0c18 363 {
mbed_official 146:f64d43ff0c18 364 BW_MCG_C1_FRDIV(setting);
mbed_official 146:f64d43ff0c18 365 }
mbed_official 146:f64d43ff0c18 366
mbed_official 146:f64d43ff0c18 367 /*!
mbed_official 146:f64d43ff0c18 368 * @brief Gets the FLL External Reference Divider.
mbed_official 146:f64d43ff0c18 369 *
mbed_official 146:f64d43ff0c18 370 * This function gets the FLL External Reference Divider.
mbed_official 146:f64d43ff0c18 371 *
mbed_official 146:f64d43ff0c18 372 * @return setting Divider setting
mbed_official 146:f64d43ff0c18 373 */
mbed_official 146:f64d43ff0c18 374 static inline uint8_t clock_get_frdiv(void)
mbed_official 146:f64d43ff0c18 375 {
mbed_official 146:f64d43ff0c18 376 return BR_MCG_C1_FRDIV;
mbed_official 146:f64d43ff0c18 377 }
mbed_official 146:f64d43ff0c18 378
mbed_official 146:f64d43ff0c18 379 /*!
mbed_official 146:f64d43ff0c18 380 * @brief Sets the Internal Reference Select.
mbed_official 146:f64d43ff0c18 381 *
mbed_official 146:f64d43ff0c18 382 * This function selects the reference clock source for the FLL.
mbed_official 146:f64d43ff0c18 383 *
mbed_official 146:f64d43ff0c18 384 * @param select Clock source select
mbed_official 146:f64d43ff0c18 385 * - 0: External reference clock is selected
mbed_official 146:f64d43ff0c18 386 * - 1: The slow internal reference clock is selected
mbed_official 146:f64d43ff0c18 387 */
mbed_official 146:f64d43ff0c18 388 static inline void clock_set_irefs(mcg_iref_clock_source_t select)
mbed_official 146:f64d43ff0c18 389 {
mbed_official 146:f64d43ff0c18 390 BW_MCG_C1_IREFS(select);
mbed_official 146:f64d43ff0c18 391 }
mbed_official 146:f64d43ff0c18 392
mbed_official 146:f64d43ff0c18 393 /*!
mbed_official 146:f64d43ff0c18 394 * @brief Gets the Internal Reference Select
mbed_official 146:f64d43ff0c18 395 *
mbed_official 146:f64d43ff0c18 396 * This function gets the reference clock source for the FLL.
mbed_official 146:f64d43ff0c18 397 *
mbed_official 146:f64d43ff0c18 398 * @return select Clock source select
mbed_official 146:f64d43ff0c18 399 */
mbed_official 146:f64d43ff0c18 400 static inline mcg_iref_clock_source_t clock_get_irefs(void)
mbed_official 146:f64d43ff0c18 401 {
mbed_official 146:f64d43ff0c18 402 return (mcg_iref_clock_source_t)BR_MCG_C1_IREFS;
mbed_official 146:f64d43ff0c18 403 }
mbed_official 146:f64d43ff0c18 404
mbed_official 146:f64d43ff0c18 405 /*!
mbed_official 146:f64d43ff0c18 406 * @brief Sets the CLKS, FRDIV and IREFS at the same time.
mbed_official 146:f64d43ff0c18 407 *
mbed_official 146:f64d43ff0c18 408 * This function sets the CLKS, FRDIV, and IREFS settings at the same time
mbed_official 146:f64d43ff0c18 409 * in order keep the integrity of the clock switching.
mbed_official 146:f64d43ff0c18 410 *
mbed_official 146:f64d43ff0c18 411 * @param clks Clock source select
mbed_official 146:f64d43ff0c18 412 * @param frdiv FLL external reference divider select
mbed_official 146:f64d43ff0c18 413 * @param irefs Internal reference select
mbed_official 146:f64d43ff0c18 414 */
mbed_official 146:f64d43ff0c18 415 static inline void clock_set_clks_frdiv_irefs(mcg_clock_select_t clks,
mbed_official 146:f64d43ff0c18 416 uint8_t frdiv,
mbed_official 146:f64d43ff0c18 417 mcg_iref_clock_source_t irefs)
mbed_official 146:f64d43ff0c18 418 {
mbed_official 146:f64d43ff0c18 419 /* Set the required CLKS , FRDIV and IREFS values */
mbed_official 146:f64d43ff0c18 420 HW_MCG_C1_WR((HW_MCG_C1_RD() & ~(BM_MCG_C1_CLKS | BM_MCG_C1_FRDIV | BM_MCG_C1_IREFS))
mbed_official 146:f64d43ff0c18 421 | (BF_MCG_C1_CLKS(clks) | BF_MCG_C1_FRDIV(frdiv) | BF_MCG_C1_IREFS(irefs)));
mbed_official 146:f64d43ff0c18 422 }
mbed_official 146:f64d43ff0c18 423
mbed_official 146:f64d43ff0c18 424 /*!
mbed_official 146:f64d43ff0c18 425 * @brief Sets the Enable Internal Reference Clock setting.
mbed_official 146:f64d43ff0c18 426 *
mbed_official 146:f64d43ff0c18 427 * This function enables/disables the internal reference clock to use as the MCGIRCLK.
mbed_official 146:f64d43ff0c18 428 *
mbed_official 146:f64d43ff0c18 429 * @params enable Enable or disable internal reference clock.
mbed_official 146:f64d43ff0c18 430 * - true: MCGIRCLK active
mbed_official 146:f64d43ff0c18 431 * - false: MCGIRCLK inactive
mbed_official 146:f64d43ff0c18 432 */
mbed_official 146:f64d43ff0c18 433 static inline void clock_set_irclken(bool enable)
mbed_official 146:f64d43ff0c18 434 {
mbed_official 146:f64d43ff0c18 435 BW_MCG_C1_IRCLKEN(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 436 }
mbed_official 146:f64d43ff0c18 437
mbed_official 146:f64d43ff0c18 438 /*!
mbed_official 146:f64d43ff0c18 439 * @brief Gets the enable Internal Reference Clock setting.
mbed_official 146:f64d43ff0c18 440 *
mbed_official 146:f64d43ff0c18 441 * This function gets the reference clock enable setting.
mbed_official 146:f64d43ff0c18 442 *
mbed_official 146:f64d43ff0c18 443 * @return enabled True if the internal reference clock is enabled.
mbed_official 146:f64d43ff0c18 444 */
mbed_official 146:f64d43ff0c18 445 static inline bool clock_get_irclken(void)
mbed_official 146:f64d43ff0c18 446 {
mbed_official 146:f64d43ff0c18 447 return BR_MCG_C1_IRCLKEN;
mbed_official 146:f64d43ff0c18 448 }
mbed_official 146:f64d43ff0c18 449
mbed_official 146:f64d43ff0c18 450 /*!
mbed_official 146:f64d43ff0c18 451 * @brief Sets the Internal Reference Clock Stop Enable setting.
mbed_official 146:f64d43ff0c18 452 *
mbed_official 146:f64d43ff0c18 453 * This function controls whether or not the internal reference clock remains
mbed_official 146:f64d43ff0c18 454 * enabled when the MCG enters Stop mode.
mbed_official 146:f64d43ff0c18 455 *
mbed_official 146:f64d43ff0c18 456 * @params enable Enable or disable the internal reference clock stop setting.
mbed_official 146:f64d43ff0c18 457 * - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set
mbed_official 146:f64d43ff0c18 458 or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
mbed_official 146:f64d43ff0c18 459 * - false: Internal reference clock is disabled in Stop mode
mbed_official 146:f64d43ff0c18 460 */
mbed_official 146:f64d43ff0c18 461 static inline void clock_set_irefsten(bool enable)
mbed_official 146:f64d43ff0c18 462 {
mbed_official 146:f64d43ff0c18 463 BW_MCG_C1_IREFSTEN(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 464 }
mbed_official 146:f64d43ff0c18 465
mbed_official 146:f64d43ff0c18 466 /*!
mbed_official 146:f64d43ff0c18 467 * @brief Gets the Enable Internal Reference Clock setting.
mbed_official 146:f64d43ff0c18 468 *
mbed_official 146:f64d43ff0c18 469 * This function gets the Internal Reference Clock Stop Enable setting.
mbed_official 146:f64d43ff0c18 470 *
mbed_official 146:f64d43ff0c18 471 * @return enabled True if internal reference clock stop is enabled.
mbed_official 146:f64d43ff0c18 472 */
mbed_official 146:f64d43ff0c18 473 static inline bool clock_get_irefsten(void)
mbed_official 146:f64d43ff0c18 474 {
mbed_official 146:f64d43ff0c18 475 return BR_MCG_C1_IREFSTEN;
mbed_official 146:f64d43ff0c18 476 }
mbed_official 146:f64d43ff0c18 477
mbed_official 146:f64d43ff0c18 478 /*!
mbed_official 146:f64d43ff0c18 479 * @brief Sets the Loss of Clock Reset Enable setting.
mbed_official 146:f64d43ff0c18 480 *
mbed_official 146:f64d43ff0c18 481 * This function determines whether an interrupt or a reset request is made following a loss
mbed_official 146:f64d43ff0c18 482 * of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
mbed_official 146:f64d43ff0c18 483 *
mbed_official 146:f64d43ff0c18 484 * @params enable Loss of Clock Reset Enable setting
mbed_official 146:f64d43ff0c18 485 * - true: Generate a reset request on a loss of OSC0 external reference clock
mbed_official 146:f64d43ff0c18 486 * - false: Interrupt request is generated on a loss of OSC0 external reference clock
mbed_official 146:f64d43ff0c18 487 */
mbed_official 146:f64d43ff0c18 488 static inline void clock_set_locre0(bool enable)
mbed_official 146:f64d43ff0c18 489 {
mbed_official 146:f64d43ff0c18 490 BW_MCG_C2_LOCRE0(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 491 }
mbed_official 146:f64d43ff0c18 492
mbed_official 146:f64d43ff0c18 493 /*!
mbed_official 146:f64d43ff0c18 494 * @brief Gets the Loss of Clock Reset Enable setting.
mbed_official 146:f64d43ff0c18 495 *
mbed_official 146:f64d43ff0c18 496 * This function gets the Loss of Clock Reset Enable setting.
mbed_official 146:f64d43ff0c18 497 *
mbed_official 146:f64d43ff0c18 498 * @return enabled True if Loss of Clock Reset is enabled.
mbed_official 146:f64d43ff0c18 499 */
mbed_official 146:f64d43ff0c18 500 static inline bool clock_get_locre0(void)
mbed_official 146:f64d43ff0c18 501 {
mbed_official 146:f64d43ff0c18 502 return BR_MCG_C2_LOCRE0;
mbed_official 146:f64d43ff0c18 503 }
mbed_official 146:f64d43ff0c18 504
mbed_official 146:f64d43ff0c18 505 #if FSL_FEATURE_MCG_HAS_FCFTRIM
mbed_official 146:f64d43ff0c18 506 /*!
mbed_official 146:f64d43ff0c18 507 * @brief Sets the Fast Internal Reference Clock Fine Trim setting.
mbed_official 146:f64d43ff0c18 508 *
mbed_official 146:f64d43ff0c18 509 * This function sets the Fast Internal Reference Clock Fine Trim setting. FCFTRIM
mbed_official 146:f64d43ff0c18 510 * controls the smallest adjustment of the fast internal reference clock frequency.
mbed_official 146:f64d43ff0c18 511 * Setting the FCFTRIM increases the period and clearing FCFTRIM decreases the period
mbed_official 146:f64d43ff0c18 512 * by the smallest amount possible. If an FCFTRIM value is stored and non-volatile
mbed_official 146:f64d43ff0c18 513 * memory is to be used, it is the user's responsibility to copy that value from the
mbed_official 146:f64d43ff0c18 514 * non-volatile memory location to this bit.
mbed_official 146:f64d43ff0c18 515 *
mbed_official 146:f64d43ff0c18 516 * @params setting Fast Internal Reference Clock Fine Trim setting
mbed_official 146:f64d43ff0c18 517 */
mbed_official 146:f64d43ff0c18 518 static inline void clock_set_fcftrim(uint8_t setting)
mbed_official 146:f64d43ff0c18 519 {
mbed_official 146:f64d43ff0c18 520 BW_MCG_C2_FCFTRIM(setting);
mbed_official 146:f64d43ff0c18 521 }
mbed_official 146:f64d43ff0c18 522
mbed_official 146:f64d43ff0c18 523 /*!
mbed_official 146:f64d43ff0c18 524 * @brief Gets the Fast Internal Reference Clock Fine Trim setting.
mbed_official 146:f64d43ff0c18 525 *
mbed_official 146:f64d43ff0c18 526 * This function gets the Fast Internal Reference Clock Fine Trim setting.
mbed_official 146:f64d43ff0c18 527 *
mbed_official 146:f64d43ff0c18 528 * @return setting Fast Internal Reference Clock Fine Trim setting
mbed_official 146:f64d43ff0c18 529 */
mbed_official 146:f64d43ff0c18 530 static inline uint8_t clock_get_fcftrim(void)
mbed_official 146:f64d43ff0c18 531 {
mbed_official 146:f64d43ff0c18 532 return BR_MCG_C2_FCFTRIM;
mbed_official 146:f64d43ff0c18 533 }
mbed_official 146:f64d43ff0c18 534 #endif /* FSL_FEATURE_MCG_HAS_FCFTRIM */
mbed_official 146:f64d43ff0c18 535
mbed_official 146:f64d43ff0c18 536 /*!
mbed_official 146:f64d43ff0c18 537 * @brief Sets the Frequency Range Select.
mbed_official 146:f64d43ff0c18 538 *
mbed_official 146:f64d43ff0c18 539 * This function selects the frequency range for the crystal oscillator or an external
mbed_official 146:f64d43ff0c18 540 * clock source. See the Oscillator (OSC) chapter for more details and the device
mbed_official 146:f64d43ff0c18 541 * data sheet for the frequency ranges used.
mbed_official 146:f64d43ff0c18 542 *
mbed_official 146:f64d43ff0c18 543 * @params select Frequency Range Select
mbed_official 146:f64d43ff0c18 544 * - 00: Low frequency range selected for the crystal oscillator
mbed_official 146:f64d43ff0c18 545 * - 01: High frequency range selected for the crystal oscillator
mbed_official 146:f64d43ff0c18 546 * - 1X: Very high frequency range selected for the crystal oscillator
mbed_official 146:f64d43ff0c18 547 */
mbed_official 146:f64d43ff0c18 548 static inline void clock_set_range0(mcg_freq_range_select_t select)
mbed_official 146:f64d43ff0c18 549 {
mbed_official 146:f64d43ff0c18 550 BW_MCG_C2_RANGE(select);
mbed_official 146:f64d43ff0c18 551 }
mbed_official 146:f64d43ff0c18 552
mbed_official 146:f64d43ff0c18 553 /*!
mbed_official 146:f64d43ff0c18 554 * @brief Gets the Frequency Range Select.
mbed_official 146:f64d43ff0c18 555 *
mbed_official 146:f64d43ff0c18 556 * This function gets the Frequency Range Select.
mbed_official 146:f64d43ff0c18 557 *
mbed_official 146:f64d43ff0c18 558 * @return select Frequency Range Select
mbed_official 146:f64d43ff0c18 559 */
mbed_official 146:f64d43ff0c18 560 static inline mcg_freq_range_select_t clock_get_range0(void)
mbed_official 146:f64d43ff0c18 561 {
mbed_official 146:f64d43ff0c18 562 return (mcg_freq_range_select_t)BR_MCG_C2_RANGE;
mbed_official 146:f64d43ff0c18 563 }
mbed_official 146:f64d43ff0c18 564
mbed_official 146:f64d43ff0c18 565 /*!
mbed_official 146:f64d43ff0c18 566 * @brief Sets the High Gain Oscillator Select.
mbed_official 146:f64d43ff0c18 567 *
mbed_official 146:f64d43ff0c18 568 * This function controls the crystal oscillator mode of operation. See the
mbed_official 146:f64d43ff0c18 569 * Oscillator (OSC) chapter for more details.
mbed_official 146:f64d43ff0c18 570 *
mbed_official 146:f64d43ff0c18 571 * @params select High Gain Oscillator Select.
mbed_official 146:f64d43ff0c18 572 * - 0: Configure crystal oscillator for low-power operation
mbed_official 146:f64d43ff0c18 573 * - 1: Configure crystal oscillator for high-gain operation
mbed_official 146:f64d43ff0c18 574 */
mbed_official 146:f64d43ff0c18 575 static inline void clock_set_hgo0(mcg_hgo_select_t select)
mbed_official 146:f64d43ff0c18 576 {
mbed_official 146:f64d43ff0c18 577 BW_MCG_C2_HGO(select);
mbed_official 146:f64d43ff0c18 578 }
mbed_official 146:f64d43ff0c18 579
mbed_official 146:f64d43ff0c18 580 /*!
mbed_official 146:f64d43ff0c18 581 * @brief Gets the High Gain Oscillator Select.
mbed_official 146:f64d43ff0c18 582 *
mbed_official 146:f64d43ff0c18 583 * This function gets the High Gain Oscillator Select.
mbed_official 146:f64d43ff0c18 584 *
mbed_official 146:f64d43ff0c18 585 * @return select High Gain Oscillator Select
mbed_official 146:f64d43ff0c18 586 */
mbed_official 146:f64d43ff0c18 587 static inline mcg_hgo_select_t clock_get_hgo0(void)
mbed_official 146:f64d43ff0c18 588 {
mbed_official 146:f64d43ff0c18 589 return (mcg_hgo_select_t)BR_MCG_C2_HGO;
mbed_official 146:f64d43ff0c18 590 }
mbed_official 146:f64d43ff0c18 591
mbed_official 146:f64d43ff0c18 592 /*!
mbed_official 146:f64d43ff0c18 593 * @brief Sets the External Reference Select.
mbed_official 146:f64d43ff0c18 594 *
mbed_official 146:f64d43ff0c18 595 * This function selects the source for the external reference clock.
mbed_official 146:f64d43ff0c18 596 * See the Oscillator (OSC) chapter for more details.
mbed_official 146:f64d43ff0c18 597 *
mbed_official 146:f64d43ff0c18 598 * @params select External Reference Select
mbed_official 146:f64d43ff0c18 599 * - 0: External reference clock requested
mbed_official 146:f64d43ff0c18 600 * - 1: Oscillator requested
mbed_official 146:f64d43ff0c18 601 */
mbed_official 146:f64d43ff0c18 602 static inline void clock_set_erefs0(mcg_eref_clock_select_t select)
mbed_official 146:f64d43ff0c18 603 {
mbed_official 146:f64d43ff0c18 604 BW_MCG_C2_EREFS(select);
mbed_official 146:f64d43ff0c18 605 }
mbed_official 146:f64d43ff0c18 606
mbed_official 146:f64d43ff0c18 607 /*!
mbed_official 146:f64d43ff0c18 608 * @brief Gets the External Reference Select.
mbed_official 146:f64d43ff0c18 609 *
mbed_official 146:f64d43ff0c18 610 * This function gets the External Reference Select.
mbed_official 146:f64d43ff0c18 611 *
mbed_official 146:f64d43ff0c18 612 * @return select External Reference Select
mbed_official 146:f64d43ff0c18 613 */
mbed_official 146:f64d43ff0c18 614 static inline mcg_eref_clock_select_t clock_get_erefs0(void)
mbed_official 146:f64d43ff0c18 615 {
mbed_official 146:f64d43ff0c18 616 return (mcg_eref_clock_select_t)BR_MCG_C2_EREFS;
mbed_official 146:f64d43ff0c18 617 }
mbed_official 146:f64d43ff0c18 618
mbed_official 146:f64d43ff0c18 619 /*!
mbed_official 146:f64d43ff0c18 620 * @brief Sets the Low Power Select.
mbed_official 146:f64d43ff0c18 621 *
mbed_official 146:f64d43ff0c18 622 * This function controls whether the FLL (or PLL) is disabled in the BLPI and the
mbed_official 146:f64d43ff0c18 623 * BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG
mbed_official 146:f64d43ff0c18 624 * into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into
mbed_official 146:f64d43ff0c18 625 * the BLPI mode. In any other MCG mode, the LP bit has no affect..
mbed_official 146:f64d43ff0c18 626 *
mbed_official 146:f64d43ff0c18 627 * @params select Low Power Select
mbed_official 146:f64d43ff0c18 628 * - 0: FLL (or PLL) is not disabled in bypass modes
mbed_official 146:f64d43ff0c18 629 * - 1: FLL (or PLL) is disabled in bypass modes (lower power)
mbed_official 146:f64d43ff0c18 630 */
mbed_official 146:f64d43ff0c18 631 static inline void clock_set_lp(mcg_lp_select_t select)
mbed_official 146:f64d43ff0c18 632 {
mbed_official 146:f64d43ff0c18 633 BW_MCG_C2_LP(select);
mbed_official 146:f64d43ff0c18 634 }
mbed_official 146:f64d43ff0c18 635
mbed_official 146:f64d43ff0c18 636 /*!
mbed_official 146:f64d43ff0c18 637 * @brief Gets the Low Power Select.
mbed_official 146:f64d43ff0c18 638 *
mbed_official 146:f64d43ff0c18 639 * This function gets the Low Power Select.
mbed_official 146:f64d43ff0c18 640 *
mbed_official 146:f64d43ff0c18 641 * @return select Low Power Select
mbed_official 146:f64d43ff0c18 642 */
mbed_official 146:f64d43ff0c18 643 static inline mcg_lp_select_t clock_get_lp(void)
mbed_official 146:f64d43ff0c18 644 {
mbed_official 146:f64d43ff0c18 645 return (mcg_lp_select_t)BR_MCG_C2_LP;
mbed_official 146:f64d43ff0c18 646 }
mbed_official 146:f64d43ff0c18 647
mbed_official 146:f64d43ff0c18 648 /*!
mbed_official 146:f64d43ff0c18 649 * @brief Sets the Internal Reference Clock Select.
mbed_official 146:f64d43ff0c18 650 *
mbed_official 146:f64d43ff0c18 651 * This function selects between the fast or slow internal reference clock source.
mbed_official 146:f64d43ff0c18 652 *
mbed_official 146:f64d43ff0c18 653 * @params select Low Power Select
mbed_official 146:f64d43ff0c18 654 * - 0: Slow internal reference clock selected.
mbed_official 146:f64d43ff0c18 655 * - 1: Fast internal reference clock selected.
mbed_official 146:f64d43ff0c18 656 */
mbed_official 146:f64d43ff0c18 657 static inline void clock_set_ircs(mcg_iref_clock_select_t select)
mbed_official 146:f64d43ff0c18 658 {
mbed_official 146:f64d43ff0c18 659 BW_MCG_C2_IRCS(select);
mbed_official 146:f64d43ff0c18 660 }
mbed_official 146:f64d43ff0c18 661
mbed_official 146:f64d43ff0c18 662 /*!
mbed_official 146:f64d43ff0c18 663 * @brief Gets the Internal Reference Clock Select.
mbed_official 146:f64d43ff0c18 664 *
mbed_official 146:f64d43ff0c18 665 * This function gets the Internal Reference Clock Select.
mbed_official 146:f64d43ff0c18 666 *
mbed_official 146:f64d43ff0c18 667 * @return select Internal Reference Clock Select
mbed_official 146:f64d43ff0c18 668 */
mbed_official 146:f64d43ff0c18 669 static inline mcg_iref_clock_select_t clock_get_ircs(void)
mbed_official 146:f64d43ff0c18 670 {
mbed_official 146:f64d43ff0c18 671 return (mcg_iref_clock_select_t)BR_MCG_C2_IRCS;
mbed_official 146:f64d43ff0c18 672 }
mbed_official 146:f64d43ff0c18 673
mbed_official 146:f64d43ff0c18 674 /*!
mbed_official 146:f64d43ff0c18 675 * @brief Sets the Slow Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 676 *
mbed_official 146:f64d43ff0c18 677 * This function controls the slow internal reference clock frequency by
mbed_official 146:f64d43ff0c18 678 * controlling the slow internal reference clock period. The SCTRIM bits are
mbed_official 146:f64d43ff0c18 679 * binary weighted (that is, bit 1 adjusts twice as much as bit 0).
mbed_official 146:f64d43ff0c18 680 * Increasing the binary value increases the period, and decreasing the value
mbed_official 146:f64d43ff0c18 681 * decreases the period.
mbed_official 146:f64d43ff0c18 682 * An additional fine trim bit is available in the C4 register as the SCFTRIM bit.
mbed_official 146:f64d43ff0c18 683 * Upon reset, this value is loaded with a factory trim value.
mbed_official 146:f64d43ff0c18 684 * If an SCTRIM value stored in non-volatile memory is to be used, it is the user's
mbed_official 146:f64d43ff0c18 685 * responsibility to copy that value from the non-volatile memory location to
mbed_official 146:f64d43ff0c18 686 * this register.
mbed_official 146:f64d43ff0c18 687 *
mbed_official 146:f64d43ff0c18 688 * @params setting Slow Internal Reference Clock Trim Setting
mbed_official 146:f64d43ff0c18 689 */
mbed_official 146:f64d43ff0c18 690 static inline void clock_set_sctrim(uint8_t setting)
mbed_official 146:f64d43ff0c18 691 {
mbed_official 146:f64d43ff0c18 692 BW_MCG_C3_SCTRIM(setting);
mbed_official 146:f64d43ff0c18 693 }
mbed_official 146:f64d43ff0c18 694
mbed_official 146:f64d43ff0c18 695 /*!
mbed_official 146:f64d43ff0c18 696 * @brief Gets the Slow Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 697 *
mbed_official 146:f64d43ff0c18 698 * This function gets the Slow Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 699 *
mbed_official 146:f64d43ff0c18 700 * @return setting Slow Internal Reference Clock Trim Setting
mbed_official 146:f64d43ff0c18 701 */
mbed_official 146:f64d43ff0c18 702 static inline uint8_t clock_get_sctrim(void)
mbed_official 146:f64d43ff0c18 703 {
mbed_official 146:f64d43ff0c18 704 return BR_MCG_C3_SCTRIM;
mbed_official 146:f64d43ff0c18 705 }
mbed_official 146:f64d43ff0c18 706
mbed_official 146:f64d43ff0c18 707 /*!
mbed_official 146:f64d43ff0c18 708 * @brief Sets the DCO Maximum Frequency with 32.768 kHz Reference.
mbed_official 146:f64d43ff0c18 709 *
mbed_official 146:f64d43ff0c18 710 * This function controls whether or not the DCO frequency range
mbed_official 146:f64d43ff0c18 711 * is narrowed to its maximum frequency with a 32.768 kHz reference.
mbed_official 146:f64d43ff0c18 712 *
mbed_official 146:f64d43ff0c18 713 * @params setting DCO Maximum Frequency with 32.768 kHz Reference Setting
mbed_official 146:f64d43ff0c18 714 * - 0: DCO has a default range of 25%.
mbed_official 146:f64d43ff0c18 715 * - 1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
mbed_official 146:f64d43ff0c18 716 */
mbed_official 146:f64d43ff0c18 717 static inline void clock_set_dmx32(mcg_dmx32_select_t setting)
mbed_official 146:f64d43ff0c18 718 {
mbed_official 146:f64d43ff0c18 719 BW_MCG_C4_DMX32(setting);
mbed_official 146:f64d43ff0c18 720 }
mbed_official 146:f64d43ff0c18 721
mbed_official 146:f64d43ff0c18 722 /*!
mbed_official 146:f64d43ff0c18 723 * @brief Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting.
mbed_official 146:f64d43ff0c18 724 *
mbed_official 146:f64d43ff0c18 725 * This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting.
mbed_official 146:f64d43ff0c18 726 *
mbed_official 146:f64d43ff0c18 727 * @return setting DCO Maximum Frequency with 32.768 kHz Reference Setting
mbed_official 146:f64d43ff0c18 728 */
mbed_official 146:f64d43ff0c18 729 static inline mcg_dmx32_select_t clock_get_dmx32(void)
mbed_official 146:f64d43ff0c18 730 {
mbed_official 146:f64d43ff0c18 731 return (mcg_dmx32_select_t)BR_MCG_C4_DMX32;
mbed_official 146:f64d43ff0c18 732 }
mbed_official 146:f64d43ff0c18 733
mbed_official 146:f64d43ff0c18 734 /*!
mbed_official 146:f64d43ff0c18 735 * @brief Sets the DCO Range Select.
mbed_official 146:f64d43ff0c18 736 *
mbed_official 146:f64d43ff0c18 737 * This function selects the frequency range for the FLL output, DCOOUT.
mbed_official 146:f64d43ff0c18 738 * When the LP bit is set, the writes to the DRS bits are ignored. The DRST read
mbed_official 146:f64d43ff0c18 739 * field indicates the current frequency range for the DCOOUT. The DRST field does
mbed_official 146:f64d43ff0c18 740 * not update immediately after a write to the DRS field due to internal
mbed_official 146:f64d43ff0c18 741 * synchronization between the clock domains. See the DCO Frequency Range table
mbed_official 146:f64d43ff0c18 742 * for more details.
mbed_official 146:f64d43ff0c18 743 *
mbed_official 146:f64d43ff0c18 744 * @params setting DCO Range Select Setting
mbed_official 146:f64d43ff0c18 745 * - 00: Low range (reset default).
mbed_official 146:f64d43ff0c18 746 * - 01: Mid range.
mbed_official 146:f64d43ff0c18 747 * - 10: Mid-high range.
mbed_official 146:f64d43ff0c18 748 * - 11: High range.
mbed_official 146:f64d43ff0c18 749 */
mbed_official 146:f64d43ff0c18 750 static inline void clock_set_drst_drs(mcg_dco_range_select_t setting)
mbed_official 146:f64d43ff0c18 751 {
mbed_official 146:f64d43ff0c18 752 BW_MCG_C4_DRST_DRS(setting);
mbed_official 146:f64d43ff0c18 753 }
mbed_official 146:f64d43ff0c18 754
mbed_official 146:f64d43ff0c18 755 /*!
mbed_official 146:f64d43ff0c18 756 * @brief Gets the DCO Range Select Setting.
mbed_official 146:f64d43ff0c18 757 *
mbed_official 146:f64d43ff0c18 758 * This function gets the DCO Range Select Setting.
mbed_official 146:f64d43ff0c18 759 *
mbed_official 146:f64d43ff0c18 760 * @return setting DCO Range Select Setting
mbed_official 146:f64d43ff0c18 761 */
mbed_official 146:f64d43ff0c18 762 static inline mcg_dco_range_select_t clock_get_drst_drs(void)
mbed_official 146:f64d43ff0c18 763 {
mbed_official 146:f64d43ff0c18 764 return (mcg_dco_range_select_t)BR_MCG_C4_DRST_DRS;
mbed_official 146:f64d43ff0c18 765 }
mbed_official 146:f64d43ff0c18 766
mbed_official 146:f64d43ff0c18 767 /*!
mbed_official 146:f64d43ff0c18 768 * @brief Sets the Fast Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 769 *
mbed_official 146:f64d43ff0c18 770 * This function controls the fast internal reference clock frequency
mbed_official 146:f64d43ff0c18 771 * by controlling the fast internal reference clock period. The FCTRIM
mbed_official 146:f64d43ff0c18 772 * bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
mbed_official 146:f64d43ff0c18 773 * Increasing the binary value increases the period, and decreasing the
mbed_official 146:f64d43ff0c18 774 * value decreases the period.
mbed_official 146:f64d43ff0c18 775 * If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is
mbed_official 146:f64d43ff0c18 776 * the user's responsibility to copy that value from the non-volatile memory location
mbed_official 146:f64d43ff0c18 777 * to this register.
mbed_official 146:f64d43ff0c18 778 *
mbed_official 146:f64d43ff0c18 779 * @params setting Fast Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 780 */
mbed_official 146:f64d43ff0c18 781 static inline void clock_set_fctrim(uint8_t setting)
mbed_official 146:f64d43ff0c18 782 {
mbed_official 146:f64d43ff0c18 783 BW_MCG_C4_FCTRIM(setting);
mbed_official 146:f64d43ff0c18 784 }
mbed_official 146:f64d43ff0c18 785
mbed_official 146:f64d43ff0c18 786 /*!
mbed_official 146:f64d43ff0c18 787 * @brief Gets the Fast Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 788 *
mbed_official 146:f64d43ff0c18 789 * This function gets the Fast Internal Reference Clock Trim Setting.
mbed_official 146:f64d43ff0c18 790 *
mbed_official 146:f64d43ff0c18 791 * @return setting Fast Internal Reference Clock Trim Setting
mbed_official 146:f64d43ff0c18 792 */
mbed_official 146:f64d43ff0c18 793 static inline uint8_t clock_get_fctrim(void)
mbed_official 146:f64d43ff0c18 794 {
mbed_official 146:f64d43ff0c18 795 return BR_MCG_C4_FCTRIM;
mbed_official 146:f64d43ff0c18 796 }
mbed_official 146:f64d43ff0c18 797
mbed_official 146:f64d43ff0c18 798 /*!
mbed_official 146:f64d43ff0c18 799 * @brief Sets the Slow Internal Reference Clock Fine Trim Setting.
mbed_official 146:f64d43ff0c18 800 *
mbed_official 146:f64d43ff0c18 801 * This function controls the smallest adjustment of the slow internal
mbed_official 146:f64d43ff0c18 802 * reference clock frequency. Setting the SCFTRIM increases the period and
mbed_official 146:f64d43ff0c18 803 * clearing the SCFTRIM decreases the period by the smallest amount possible.
mbed_official 146:f64d43ff0c18 804 * If an SCFTRIM value, stored in non-volatile memory, is to be used, it is
mbed_official 146:f64d43ff0c18 805 * the user's responsibility to copy that value from the non-volatile memory
mbed_official 146:f64d43ff0c18 806 * location to this bit.
mbed_official 146:f64d43ff0c18 807 *
mbed_official 146:f64d43ff0c18 808 * @params setting Slow Internal Reference Clock Fine Trim Setting
mbed_official 146:f64d43ff0c18 809 */
mbed_official 146:f64d43ff0c18 810 static inline void clock_set_scftrim(uint8_t setting)
mbed_official 146:f64d43ff0c18 811 {
mbed_official 146:f64d43ff0c18 812 BW_MCG_C4_SCFTRIM(setting);
mbed_official 146:f64d43ff0c18 813 }
mbed_official 146:f64d43ff0c18 814
mbed_official 146:f64d43ff0c18 815 /*!
mbed_official 146:f64d43ff0c18 816 * @brief Gets the Slow Internal Reference Clock Fine Trim Setting.
mbed_official 146:f64d43ff0c18 817 *
mbed_official 146:f64d43ff0c18 818 * This function gets the Slow Internal Reference Clock Fine Trim Setting.
mbed_official 146:f64d43ff0c18 819 *
mbed_official 146:f64d43ff0c18 820 * @return setting Slow Internal Reference Clock Fine Trim Setting
mbed_official 146:f64d43ff0c18 821 */
mbed_official 146:f64d43ff0c18 822 static inline uint8_t clock_get_scftrim(void)
mbed_official 146:f64d43ff0c18 823 {
mbed_official 146:f64d43ff0c18 824 return BR_MCG_C4_SCFTRIM;
mbed_official 146:f64d43ff0c18 825 }
mbed_official 146:f64d43ff0c18 826
mbed_official 146:f64d43ff0c18 827 #if FSL_FEATURE_MCG_USE_PLLREFSEL
mbed_official 146:f64d43ff0c18 828 /*!
mbed_official 146:f64d43ff0c18 829 * @brief Sets the PLL0 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 830 *
mbed_official 146:f64d43ff0c18 831 * This function selects the PLL0 external reference clock source.
mbed_official 146:f64d43ff0c18 832 *
mbed_official 146:f64d43ff0c18 833 * @params setting PLL0 External Reference Select Setting
mbed_official 146:f64d43ff0c18 834 * - 0: Selects OSC0 clock source as its external reference clock
mbed_official 146:f64d43ff0c18 835 * - 1: Selects OSC1 clock source as its external reference clock
mbed_official 146:f64d43ff0c18 836 */
mbed_official 146:f64d43ff0c18 837 static inline void clock_set_pllrefsel0(mcg_pll_eref_clock_select_t setting)
mbed_official 146:f64d43ff0c18 838 {
mbed_official 146:f64d43ff0c18 839 BW_MCG_C5_PLLREFSEL0(setting);
mbed_official 146:f64d43ff0c18 840 }
mbed_official 146:f64d43ff0c18 841
mbed_official 146:f64d43ff0c18 842 /*!
mbed_official 146:f64d43ff0c18 843 * @brief Gets the PLL0 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 844 *
mbed_official 146:f64d43ff0c18 845 * This function gets the PLL0 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 846 *
mbed_official 146:f64d43ff0c18 847 * @return setting PLL0 External Reference Select Setting
mbed_official 146:f64d43ff0c18 848 */
mbed_official 146:f64d43ff0c18 849 static inline mcg_pll_eref_clock_select_t clock_get_pllrefsel0(void)
mbed_official 146:f64d43ff0c18 850 {
mbed_official 146:f64d43ff0c18 851 return (mcg_pll_eref_clock_select_t)BR_MCG_C5_PLLREFSEL0;
mbed_official 146:f64d43ff0c18 852 }
mbed_official 146:f64d43ff0c18 853 #endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
mbed_official 146:f64d43ff0c18 854
mbed_official 146:f64d43ff0c18 855 /*!
mbed_official 146:f64d43ff0c18 856 * @brief Sets the PLL Clock Enable Setting.
mbed_official 146:f64d43ff0c18 857 *
mbed_official 146:f64d43ff0c18 858 * This function enables/disables the PLL0 independent of the PLLS and enables the PLL0
mbed_official 146:f64d43ff0c18 859 * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to
mbed_official 146:f64d43ff0c18 860 * the correct divider to generate a PLL1 reference clock in a valid reference range
mbed_official 146:f64d43ff0c18 861 * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external
mbed_official 146:f64d43ff0c18 862 * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being
mbed_official 146:f64d43ff0c18 863 * enabled with the PLLCLKEN0 bit, and the external oscillator is being used
mbed_official 146:f64d43ff0c18 864 * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
mbed_official 146:f64d43ff0c18 865 *
mbed_official 146:f64d43ff0c18 866 * @params enable PLL Clock Enable Setting
mbed_official 146:f64d43ff0c18 867 * - true: MCGPLL0CLK and MCGPLL0CLK2X are active
mbed_official 146:f64d43ff0c18 868 * - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive
mbed_official 146:f64d43ff0c18 869 */
mbed_official 146:f64d43ff0c18 870 static inline void clock_set_pllclken0(bool enable)
mbed_official 146:f64d43ff0c18 871 {
mbed_official 146:f64d43ff0c18 872 BW_MCG_C5_PLLCLKEN0(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 873 }
mbed_official 146:f64d43ff0c18 874
mbed_official 146:f64d43ff0c18 875 /*!
mbed_official 146:f64d43ff0c18 876 * @brief Gets the PLL Clock Enable Setting.
mbed_official 146:f64d43ff0c18 877 *
mbed_official 146:f64d43ff0c18 878 * This function gets the PLL Clock Enable Setting.
mbed_official 146:f64d43ff0c18 879 *
mbed_official 146:f64d43ff0c18 880 * @return enabled True if PLL0 PLL Clock is enabled.
mbed_official 146:f64d43ff0c18 881 */
mbed_official 146:f64d43ff0c18 882 static inline bool clock_get_pllclken0(void)
mbed_official 146:f64d43ff0c18 883 {
mbed_official 146:f64d43ff0c18 884 return BR_MCG_C5_PLLCLKEN0;
mbed_official 146:f64d43ff0c18 885 }
mbed_official 146:f64d43ff0c18 886
mbed_official 146:f64d43ff0c18 887 /*!
mbed_official 146:f64d43ff0c18 888 * @brief Sets the PLL0 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 889 *
mbed_official 146:f64d43ff0c18 890 * This function enables/disables the PLL0 Clock during a Normal Stop (In Low
mbed_official 146:f64d43ff0c18 891 * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other
mbed_official 146:f64d43ff0c18 892 * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock
mbed_official 146:f64d43ff0c18 893 * to run if it is written to 1.
mbed_official 146:f64d43ff0c18 894 *
mbed_official 146:f64d43ff0c18 895 * @params enable PLL0 Stop Enable Setting
mbed_official 146:f64d43ff0c18 896 * - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in
mbed_official 146:f64d43ff0c18 897 * Normal Stop mode.
mbed_official 146:f64d43ff0c18 898 * - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the
mbed_official 146:f64d43ff0c18 899 * Stop modes.
mbed_official 146:f64d43ff0c18 900 */
mbed_official 146:f64d43ff0c18 901 static inline void clock_set_pllsten0(bool enable)
mbed_official 146:f64d43ff0c18 902 {
mbed_official 146:f64d43ff0c18 903 BW_MCG_C5_PLLSTEN0(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 904 }
mbed_official 146:f64d43ff0c18 905
mbed_official 146:f64d43ff0c18 906 /*!
mbed_official 146:f64d43ff0c18 907 * @brief Gets the PLL0 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 908 *
mbed_official 146:f64d43ff0c18 909 * This function gets the PLL0 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 910 *
mbed_official 146:f64d43ff0c18 911 * @return enabled True if the PLL0 Stop is enabled.
mbed_official 146:f64d43ff0c18 912 */
mbed_official 146:f64d43ff0c18 913 static inline bool clock_get_pllsten0(void)
mbed_official 146:f64d43ff0c18 914 {
mbed_official 146:f64d43ff0c18 915 return BR_MCG_C5_PLLSTEN0;
mbed_official 146:f64d43ff0c18 916 }
mbed_official 146:f64d43ff0c18 917
mbed_official 146:f64d43ff0c18 918 /*!
mbed_official 146:f64d43ff0c18 919 * @brief Sets the PLL0 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 920 *
mbed_official 146:f64d43ff0c18 921 * This function selects the amount to divide down the external reference
mbed_official 146:f64d43ff0c18 922 * clock for the PLL0. The resulting frequency must be in a valid reference
mbed_official 146:f64d43ff0c18 923 * range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the
mbed_official 146:f64d43ff0c18 924 * PRDIV0 value must not be changed when LOCK0 is zero.
mbed_official 146:f64d43ff0c18 925 *
mbed_official 146:f64d43ff0c18 926 * @params setting PLL0 External Reference Divider Setting
mbed_official 146:f64d43ff0c18 927 */
mbed_official 146:f64d43ff0c18 928 static inline void clock_set_prdiv0(uint8_t setting)
mbed_official 146:f64d43ff0c18 929 {
mbed_official 146:f64d43ff0c18 930 BW_MCG_C5_PRDIV0(setting);
mbed_official 146:f64d43ff0c18 931 }
mbed_official 146:f64d43ff0c18 932
mbed_official 146:f64d43ff0c18 933 /*!
mbed_official 146:f64d43ff0c18 934 * @brief Gets the PLL0 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 935 *
mbed_official 146:f64d43ff0c18 936 * This function gets the PLL0 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 937 *
mbed_official 146:f64d43ff0c18 938 * @return setting PLL0 External Reference Divider Setting
mbed_official 146:f64d43ff0c18 939 */
mbed_official 146:f64d43ff0c18 940 static inline uint8_t clock_get_prdiv0(void)
mbed_official 146:f64d43ff0c18 941 {
mbed_official 146:f64d43ff0c18 942 return BR_MCG_C5_PRDIV0;
mbed_official 146:f64d43ff0c18 943 }
mbed_official 146:f64d43ff0c18 944
mbed_official 146:f64d43ff0c18 945 /*!
mbed_official 146:f64d43ff0c18 946 * @brief Sets the Loss of Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 947 *
mbed_official 146:f64d43ff0c18 948 * This function determine whether an interrupt request is made following a loss
mbed_official 146:f64d43ff0c18 949 * of lock indication. This bit only has an effect when LOLS 0 is set.
mbed_official 146:f64d43ff0c18 950 *
mbed_official 146:f64d43ff0c18 951 * @params enable Loss of Lock Interrupt Enable Setting
mbed_official 146:f64d43ff0c18 952 * - true: Generate an interrupt request on loss of lock.
mbed_official 146:f64d43ff0c18 953 * - false: No interrupt request is generated on loss of lock.
mbed_official 146:f64d43ff0c18 954 */
mbed_official 146:f64d43ff0c18 955 static inline void clock_set_lolie0(bool enable)
mbed_official 146:f64d43ff0c18 956 {
mbed_official 146:f64d43ff0c18 957 BW_MCG_C6_LOLIE0(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 958 }
mbed_official 146:f64d43ff0c18 959
mbed_official 146:f64d43ff0c18 960 /*!
mbed_official 146:f64d43ff0c18 961 * @brief Gets the Loss of the Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 962 *
mbed_official 146:f64d43ff0c18 963 * This function gets the Loss of the Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 964 *
mbed_official 146:f64d43ff0c18 965 * @return enabled True if the Loss of Lock Interrupt is enabled.
mbed_official 146:f64d43ff0c18 966 */
mbed_official 146:f64d43ff0c18 967 static inline bool clock_get_lolie0(void)
mbed_official 146:f64d43ff0c18 968 {
mbed_official 146:f64d43ff0c18 969 return BR_MCG_C6_LOLIE0;
mbed_official 146:f64d43ff0c18 970 }
mbed_official 146:f64d43ff0c18 971
mbed_official 146:f64d43ff0c18 972 /*!
mbed_official 146:f64d43ff0c18 973 * @brief Sets the PLL Select Setting.
mbed_official 146:f64d43ff0c18 974 *
mbed_official 146:f64d43ff0c18 975 * This function controls whether the PLLCS or FLL output is selected as the
mbed_official 146:f64d43ff0c18 976 * MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and
mbed_official 146:f64d43ff0c18 977 * PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the
mbed_official 146:f64d43ff0c18 978 * PLLS is set, the FLL is disabled in all modes.
mbed_official 146:f64d43ff0c18 979 *
mbed_official 146:f64d43ff0c18 980 * @params setting PLL Select Setting
mbed_official 146:f64d43ff0c18 981 * - 0: FLL is selected.
mbed_official 146:f64d43ff0c18 982 * - 1: PLLCS output clock is selected (PRDIV0 bits of PLL in
mbed_official 146:f64d43ff0c18 983 * control need to be programmed to the correct divider to
mbed_official 146:f64d43ff0c18 984 * generate a PLL reference clock in the range of 1 - 32 MHz
mbed_official 146:f64d43ff0c18 985 * prior to setting the PLLS bit).
mbed_official 146:f64d43ff0c18 986 */
mbed_official 146:f64d43ff0c18 987 static inline void clock_set_plls(mcg_pll_select_t setting)
mbed_official 146:f64d43ff0c18 988 {
mbed_official 146:f64d43ff0c18 989 BW_MCG_C6_PLLS(setting);
mbed_official 146:f64d43ff0c18 990 }
mbed_official 146:f64d43ff0c18 991
mbed_official 146:f64d43ff0c18 992 /*!
mbed_official 146:f64d43ff0c18 993 * @brief Gets the PLL Select Setting.
mbed_official 146:f64d43ff0c18 994 *
mbed_official 146:f64d43ff0c18 995 * This function gets the PLL Select Setting.
mbed_official 146:f64d43ff0c18 996 *
mbed_official 146:f64d43ff0c18 997 * @return setting PLL Select Setting
mbed_official 146:f64d43ff0c18 998 */
mbed_official 146:f64d43ff0c18 999 static inline mcg_pll_select_t clock_get_plls(void)
mbed_official 146:f64d43ff0c18 1000 {
mbed_official 146:f64d43ff0c18 1001 return (mcg_pll_select_t)BR_MCG_C6_PLLS;
mbed_official 146:f64d43ff0c18 1002 }
mbed_official 146:f64d43ff0c18 1003
mbed_official 146:f64d43ff0c18 1004 /*!
mbed_official 146:f64d43ff0c18 1005 * @brief Sets the Clock Monitor Enable Setting.
mbed_official 146:f64d43ff0c18 1006 *
mbed_official 146:f64d43ff0c18 1007 * This function enables/disables the loss of clock monitoring circuit for
mbed_official 146:f64d43ff0c18 1008 * the OSC0 external reference mux select. The LOCRE0 bit determines whether an
mbed_official 146:f64d43ff0c18 1009 * interrupt or a reset request is generated following a loss of the OSC0 indication.
mbed_official 146:f64d43ff0c18 1010 * The CME0 bit should only be set to a logic 1 when the MCG is in an operational
mbed_official 146:f64d43ff0c18 1011 * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the
mbed_official 146:f64d43ff0c18 1012 * CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register
mbed_official 146:f64d43ff0c18 1013 * should not be changed. CME0 bit should be set to a logic 0 before the MCG
mbed_official 146:f64d43ff0c18 1014 * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode.
mbed_official 146:f64d43ff0c18 1015 * CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes
mbed_official 146:f64d43ff0c18 1016 * if the MCG is in BLPE mode.
mbed_official 146:f64d43ff0c18 1017 *
mbed_official 146:f64d43ff0c18 1018 * @params enable Clock Monitor Enable Setting
mbed_official 146:f64d43ff0c18 1019 * - true: External clock monitor is enabled for OSC0.
mbed_official 146:f64d43ff0c18 1020 * - false: External clock monitor is disabled for OSC0.
mbed_official 146:f64d43ff0c18 1021 */
mbed_official 146:f64d43ff0c18 1022 static inline void clock_set_cme0(bool enable)
mbed_official 146:f64d43ff0c18 1023 {
mbed_official 146:f64d43ff0c18 1024 BW_MCG_C6_CME0(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1025 }
mbed_official 146:f64d43ff0c18 1026
mbed_official 146:f64d43ff0c18 1027 /*!
mbed_official 146:f64d43ff0c18 1028 * @brief Gets the Clock Monitor Enable Setting.
mbed_official 146:f64d43ff0c18 1029 *
mbed_official 146:f64d43ff0c18 1030 * This function gets the Clock Monitor Enable Setting.
mbed_official 146:f64d43ff0c18 1031 *
mbed_official 146:f64d43ff0c18 1032 * @return enabled True if Clock Monitor is enabled
mbed_official 146:f64d43ff0c18 1033 */
mbed_official 146:f64d43ff0c18 1034 static inline bool clock_get_cme0(void)
mbed_official 146:f64d43ff0c18 1035 {
mbed_official 146:f64d43ff0c18 1036 return BR_MCG_C6_CME0;
mbed_official 146:f64d43ff0c18 1037 }
mbed_official 146:f64d43ff0c18 1038
mbed_official 146:f64d43ff0c18 1039 /*!
mbed_official 146:f64d43ff0c18 1040 * @brief Sets the VCO0 Divider Setting.
mbed_official 146:f64d43ff0c18 1041 *
mbed_official 146:f64d43ff0c18 1042 * This function selects the amount to divide the VCO output of the PLL0.
mbed_official 146:f64d43ff0c18 1043 * The VDIV0 bits establish the multiplication factor (M) applied to the
mbed_official 146:f64d43ff0c18 1044 * reference clock frequency. After the PLL0 is enabled (by setting either
mbed_official 146:f64d43ff0c18 1045 * PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero.
mbed_official 146:f64d43ff0c18 1046 *
mbed_official 146:f64d43ff0c18 1047 * @params setting VCO0 Divider Setting
mbed_official 146:f64d43ff0c18 1048 */
mbed_official 146:f64d43ff0c18 1049 static inline void clock_set_vdiv0(uint8_t setting)
mbed_official 146:f64d43ff0c18 1050 {
mbed_official 146:f64d43ff0c18 1051 BW_MCG_C6_VDIV0(setting);
mbed_official 146:f64d43ff0c18 1052 }
mbed_official 146:f64d43ff0c18 1053
mbed_official 146:f64d43ff0c18 1054 /*!
mbed_official 146:f64d43ff0c18 1055 * @brief Gets the VCO0 Divider Setting.
mbed_official 146:f64d43ff0c18 1056 *
mbed_official 146:f64d43ff0c18 1057 * This function gets the VCO0 Divider Setting.
mbed_official 146:f64d43ff0c18 1058 *
mbed_official 146:f64d43ff0c18 1059 * @return setting VCO0 Divider Setting
mbed_official 146:f64d43ff0c18 1060 */
mbed_official 146:f64d43ff0c18 1061 static inline uint8_t clock_get_vdiv0(void)
mbed_official 146:f64d43ff0c18 1062 {
mbed_official 146:f64d43ff0c18 1063 return BR_MCG_C6_VDIV0;
mbed_official 146:f64d43ff0c18 1064 }
mbed_official 146:f64d43ff0c18 1065
mbed_official 146:f64d43ff0c18 1066 /*!
mbed_official 146:f64d43ff0c18 1067 * @brief Gets the Loss of the Lock Status.
mbed_official 146:f64d43ff0c18 1068 *
mbed_official 146:f64d43ff0c18 1069 * This function gets the Loss of Lock Status. This bit is a sticky bit indicating
mbed_official 146:f64d43ff0c18 1070 * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL
mbed_official 146:f64d43ff0c18 1071 * output frequency has fallen outside the lock exit frequency tolerance, D unl .
mbed_official 146:f64d43ff0c18 1072 * LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set.
mbed_official 146:f64d43ff0c18 1073 * This bit is cleared by reset or by writing a logic 1 to it when set. Writing a
mbed_official 146:f64d43ff0c18 1074 * logic 0 to this bit has no effect.
mbed_official 146:f64d43ff0c18 1075 *
mbed_official 146:f64d43ff0c18 1076 * @return status Loss of Lock Status
mbed_official 146:f64d43ff0c18 1077 * - 0: PLL has not lost lock since LOLS 0 was last cleared
mbed_official 146:f64d43ff0c18 1078 * - 1: PLL has lost lock since LOLS 0 was last cleared
mbed_official 146:f64d43ff0c18 1079 */
mbed_official 146:f64d43ff0c18 1080 static inline mcg_lols_status_t clock_get_lols0(void)
mbed_official 146:f64d43ff0c18 1081 {
mbed_official 146:f64d43ff0c18 1082 return (mcg_lols_status_t)BR_MCG_S_LOLS0;
mbed_official 146:f64d43ff0c18 1083 }
mbed_official 146:f64d43ff0c18 1084
mbed_official 146:f64d43ff0c18 1085 /*!
mbed_official 146:f64d43ff0c18 1086 * @brief Gets the Lock Status.
mbed_official 146:f64d43ff0c18 1087 *
mbed_official 146:f64d43ff0c18 1088 * This function gets the Lock Status. This bit indicates whether the PLL0 has
mbed_official 146:f64d43ff0c18 1089 * acquired the lock. Lock detection is disabled when not operating in either the PBE or the
mbed_official 146:f64d43ff0c18 1090 * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode.
mbed_official 146:f64d43ff0c18 1091 * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and
mbed_official 146:f64d43ff0c18 1092 * MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock
mbed_official 146:f64d43ff0c18 1093 * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register
mbed_official 146:f64d43ff0c18 1094 * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear
mbed_official 146:f64d43ff0c18 1095 * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference
mbed_official 146:f64d43ff0c18 1096 * clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS,
mbed_official 146:f64d43ff0c18 1097 * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear
mbed_official 146:f64d43ff0c18 1098 * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock.
mbed_official 146:f64d43ff0c18 1099 * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and
mbed_official 146:f64d43ff0c18 1100 * MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted.
mbed_official 146:f64d43ff0c18 1101 *
mbed_official 146:f64d43ff0c18 1102 * @return status Lock Status
mbed_official 146:f64d43ff0c18 1103 * - 0: PLL is currently unlocked
mbed_official 146:f64d43ff0c18 1104 * - 1: PLL is currently locked
mbed_official 146:f64d43ff0c18 1105 */
mbed_official 146:f64d43ff0c18 1106 static inline mcg_lock_status_t clock_get_lock0(void)
mbed_official 146:f64d43ff0c18 1107 {
mbed_official 146:f64d43ff0c18 1108 return (mcg_lock_status_t)BR_MCG_S_LOCK0;
mbed_official 146:f64d43ff0c18 1109 }
mbed_official 146:f64d43ff0c18 1110
mbed_official 146:f64d43ff0c18 1111 /*!
mbed_official 146:f64d43ff0c18 1112 * @brief Gets the PLL Select Status.
mbed_official 146:f64d43ff0c18 1113 *
mbed_official 146:f64d43ff0c18 1114 * This function gets the PLL Select Status. This bit indicates the clock source
mbed_official 146:f64d43ff0c18 1115 * selected by PLLS . The PLLST bit does not update immediately after a write to
mbed_official 146:f64d43ff0c18 1116 * the PLLS bit due to the internal synchronization between the clock domains.
mbed_official 146:f64d43ff0c18 1117 *
mbed_official 146:f64d43ff0c18 1118 * @return status PLL Select Status
mbed_official 146:f64d43ff0c18 1119 * - 0: Source of PLLS clock is FLL clock.
mbed_official 146:f64d43ff0c18 1120 * - 1: Source of PLLS clock is PLLCS output clock.
mbed_official 146:f64d43ff0c18 1121 */
mbed_official 146:f64d43ff0c18 1122 static inline mcg_pllst_status_t clock_get_pllst(void)
mbed_official 146:f64d43ff0c18 1123 {
mbed_official 146:f64d43ff0c18 1124 return (mcg_pllst_status_t)BR_MCG_S_PLLST;
mbed_official 146:f64d43ff0c18 1125 }
mbed_official 146:f64d43ff0c18 1126
mbed_official 146:f64d43ff0c18 1127 /*!
mbed_official 146:f64d43ff0c18 1128 * @brief Gets the Internal Reference Status.
mbed_official 146:f64d43ff0c18 1129 *
mbed_official 146:f64d43ff0c18 1130 * This function gets the Internal Reference Status. This bit indicates the current
mbed_official 146:f64d43ff0c18 1131 * source for the FLL reference clock. The IREFST bit does not update immediately
mbed_official 146:f64d43ff0c18 1132 * after a write to the IREFS bit due to internal synchronization between the clock
mbed_official 146:f64d43ff0c18 1133 * domains.
mbed_official 146:f64d43ff0c18 1134 *
mbed_official 146:f64d43ff0c18 1135 * @return status Internal Reference Status
mbed_official 146:f64d43ff0c18 1136 * - 0: Source of FLL reference clock is the external reference clock.
mbed_official 146:f64d43ff0c18 1137 * - 1: Source of FLL reference clock is the internal reference clock.
mbed_official 146:f64d43ff0c18 1138 */
mbed_official 146:f64d43ff0c18 1139 static inline mcg_irefst_status_t clock_get_irefst(void)
mbed_official 146:f64d43ff0c18 1140 {
mbed_official 146:f64d43ff0c18 1141 return (mcg_irefst_status_t)BR_MCG_S_IREFST;
mbed_official 146:f64d43ff0c18 1142 }
mbed_official 146:f64d43ff0c18 1143
mbed_official 146:f64d43ff0c18 1144 /*!
mbed_official 146:f64d43ff0c18 1145 * @brief Gets the Clock Mode Status.
mbed_official 146:f64d43ff0c18 1146 *
mbed_official 146:f64d43ff0c18 1147 * This function gets the Clock Mode Status. These bits indicate the current clock mode.
mbed_official 146:f64d43ff0c18 1148 * The CLKST bits do not update immediately after a write to the CLKS bits due to
mbed_official 146:f64d43ff0c18 1149 * internal synchronization between clock domains.
mbed_official 146:f64d43ff0c18 1150 *
mbed_official 146:f64d43ff0c18 1151 * @return status Clock Mode Status
mbed_official 146:f64d43ff0c18 1152 * - 00: Output of the FLL is selected (reset default).
mbed_official 146:f64d43ff0c18 1153 * - 01: Internal reference clock is selected.
mbed_official 146:f64d43ff0c18 1154 * - 10: External reference clock is selected.
mbed_official 146:f64d43ff0c18 1155 * - 11: Output of the PLL is selected.
mbed_official 146:f64d43ff0c18 1156 */
mbed_official 146:f64d43ff0c18 1157 static inline mcg_clkst_status_t clock_get_clkst(void)
mbed_official 146:f64d43ff0c18 1158 {
mbed_official 146:f64d43ff0c18 1159 return (mcg_clkst_status_t)BR_MCG_S_CLKST;
mbed_official 146:f64d43ff0c18 1160 }
mbed_official 146:f64d43ff0c18 1161
mbed_official 146:f64d43ff0c18 1162 /*!
mbed_official 146:f64d43ff0c18 1163 * @brief Gets the OSC Initialization Status.
mbed_official 146:f64d43ff0c18 1164 *
mbed_official 146:f64d43ff0c18 1165 * This function gets the OSC Initialization Status. This bit, which resets to 0, is set
mbed_official 146:f64d43ff0c18 1166 * to 1 after the initialization cycles of the crystal oscillator clock have completed.
mbed_official 146:f64d43ff0c18 1167 * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the
mbed_official 146:f64d43ff0c18 1168 * OSC module's detailed description for more information.
mbed_official 146:f64d43ff0c18 1169 *
mbed_official 146:f64d43ff0c18 1170 * @return status OSC Initialization Status
mbed_official 146:f64d43ff0c18 1171 */
mbed_official 146:f64d43ff0c18 1172 static inline uint8_t clock_get_oscinit0(void)
mbed_official 146:f64d43ff0c18 1173 {
mbed_official 146:f64d43ff0c18 1174 return BR_MCG_S_OSCINIT0;
mbed_official 146:f64d43ff0c18 1175 }
mbed_official 146:f64d43ff0c18 1176
mbed_official 146:f64d43ff0c18 1177 /*!
mbed_official 146:f64d43ff0c18 1178 * @brief Gets the Internal Reference Clock Status.
mbed_official 146:f64d43ff0c18 1179 *
mbed_official 146:f64d43ff0c18 1180 * This function gets the Internal Reference Clock Status. The IRCST bit indicates the
mbed_official 146:f64d43ff0c18 1181 * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit
mbed_official 146:f64d43ff0c18 1182 * does not update immediately after a write to the IRCS bit due to the internal
mbed_official 146:f64d43ff0c18 1183 * synchronization between clock domains. The IRCST bit is only updated if the
mbed_official 146:f64d43ff0c18 1184 * internal reference clock is enabled, either by the MCG being in a mode that uses the
mbed_official 146:f64d43ff0c18 1185 * IRC or by setting the C1[IRCLKEN] bit.
mbed_official 146:f64d43ff0c18 1186 *
mbed_official 146:f64d43ff0c18 1187 * @return status Internal Reference Clock Status
mbed_official 146:f64d43ff0c18 1188 * - 0: Source of internal reference clock is the slow clock (32 kHz IRC).
mbed_official 146:f64d43ff0c18 1189 * - 1: Source of internal reference clock is the fast clock (2 MHz IRC).
mbed_official 146:f64d43ff0c18 1190 */
mbed_official 146:f64d43ff0c18 1191 static inline mcg_ircst_status_t clock_get_ircst(void)
mbed_official 146:f64d43ff0c18 1192 {
mbed_official 146:f64d43ff0c18 1193 return (mcg_ircst_status_t)BR_MCG_S_IRCST;
mbed_official 146:f64d43ff0c18 1194 }
mbed_official 146:f64d43ff0c18 1195
mbed_official 146:f64d43ff0c18 1196 /*!
mbed_official 146:f64d43ff0c18 1197 * @brief Gets the Automatic Trim machine Fail Flag.
mbed_official 146:f64d43ff0c18 1198 *
mbed_official 146:f64d43ff0c18 1199 * This function gets the Automatic Trim machine Fail Flag. This Fail flag for the
mbed_official 146:f64d43ff0c18 1200 * Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is
mbed_official 146:f64d43ff0c18 1201 * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG
mbed_official 146:f64d43ff0c18 1202 * enters into any Stop mode. A write to ATMF clears the flag.
mbed_official 146:f64d43ff0c18 1203 *
mbed_official 146:f64d43ff0c18 1204 * @return flag Automatic Trim machine Fail Flag
mbed_official 146:f64d43ff0c18 1205 * - 0: Automatic Trim Machine completed normally.
mbed_official 146:f64d43ff0c18 1206 * - 1: Automatic Trim Machine failed.
mbed_official 146:f64d43ff0c18 1207 */
mbed_official 146:f64d43ff0c18 1208 static inline mcg_atmf_status_t clock_get_atmf(void)
mbed_official 146:f64d43ff0c18 1209 {
mbed_official 146:f64d43ff0c18 1210 return (mcg_atmf_status_t)BR_MCG_SC_ATMF;
mbed_official 146:f64d43ff0c18 1211 }
mbed_official 146:f64d43ff0c18 1212
mbed_official 146:f64d43ff0c18 1213 /*!
mbed_official 146:f64d43ff0c18 1214 * @brief Sets the Automatic Trim machine Fail Flag.
mbed_official 146:f64d43ff0c18 1215 *
mbed_official 146:f64d43ff0c18 1216 * This function clears the ATMF flag.
mbed_official 146:f64d43ff0c18 1217 */
mbed_official 146:f64d43ff0c18 1218 static inline void clock_set_atmf(void)
mbed_official 146:f64d43ff0c18 1219 {
mbed_official 146:f64d43ff0c18 1220 BW_MCG_SC_ATMF(1);
mbed_official 146:f64d43ff0c18 1221 }
mbed_official 146:f64d43ff0c18 1222
mbed_official 146:f64d43ff0c18 1223 /*!
mbed_official 146:f64d43ff0c18 1224 * @brief Gets the OSC0 Loss of Clock Status.
mbed_official 146:f64d43ff0c18 1225 *
mbed_official 146:f64d43ff0c18 1226 * This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of
mbed_official 146:f64d43ff0c18 1227 * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set.
mbed_official 146:f64d43ff0c18 1228 * This bit is cleared by writing a logic 1 to it when set.
mbed_official 146:f64d43ff0c18 1229 *
mbed_official 146:f64d43ff0c18 1230 * @return status OSC0 Loss of Clock Status
mbed_official 146:f64d43ff0c18 1231 * - 0: Loss of OSC0 has not occurred.
mbed_official 146:f64d43ff0c18 1232 * - 1: Loss of OSC0 has occurred.
mbed_official 146:f64d43ff0c18 1233 */
mbed_official 146:f64d43ff0c18 1234 static inline mcg_locs0_status_t clock_get_locs0(void)
mbed_official 146:f64d43ff0c18 1235 {
mbed_official 146:f64d43ff0c18 1236 return (mcg_locs0_status_t)BR_MCG_SC_LOCS0;
mbed_official 146:f64d43ff0c18 1237 }
mbed_official 146:f64d43ff0c18 1238
mbed_official 146:f64d43ff0c18 1239 /*!
mbed_official 146:f64d43ff0c18 1240 * @brief Sets the Automatic Trim Machine Enable Setting.
mbed_official 146:f64d43ff0c18 1241 *
mbed_official 146:f64d43ff0c18 1242 * This function enables/disables the Auto Trim Machine to start automatically
mbed_official 146:f64d43ff0c18 1243 * trimming the selected Internal Reference Clock.
mbed_official 146:f64d43ff0c18 1244 * ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits
mbed_official 146:f64d43ff0c18 1245 * of the IRCS clock selected by the ATMS bit.
mbed_official 146:f64d43ff0c18 1246 * Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto
mbed_official 146:f64d43ff0c18 1247 * trim operation and clears this bit.
mbed_official 146:f64d43ff0c18 1248 *
mbed_official 146:f64d43ff0c18 1249 * @params enable Automatic Trim Machine Enable Setting
mbed_official 146:f64d43ff0c18 1250 * - true: Auto Trim Machine enabled
mbed_official 146:f64d43ff0c18 1251 * - false: Auto Trim Machine disabled
mbed_official 146:f64d43ff0c18 1252 */
mbed_official 146:f64d43ff0c18 1253 static inline void clock_set_atme(bool enable)
mbed_official 146:f64d43ff0c18 1254 {
mbed_official 146:f64d43ff0c18 1255 BW_MCG_SC_ATME(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1256 }
mbed_official 146:f64d43ff0c18 1257
mbed_official 146:f64d43ff0c18 1258 /*!
mbed_official 146:f64d43ff0c18 1259 * @brief Gets the Automatic Trim Machine Enable Setting.
mbed_official 146:f64d43ff0c18 1260 *
mbed_official 146:f64d43ff0c18 1261 * This function gets the Automatic Trim Machine Enable Setting.
mbed_official 146:f64d43ff0c18 1262 *
mbed_official 146:f64d43ff0c18 1263 * @return enabled True if Automatic Trim Machine is enabled
mbed_official 146:f64d43ff0c18 1264 */
mbed_official 146:f64d43ff0c18 1265 static inline bool clock_get_atme(void)
mbed_official 146:f64d43ff0c18 1266 {
mbed_official 146:f64d43ff0c18 1267 return BR_MCG_SC_ATME;
mbed_official 146:f64d43ff0c18 1268 }
mbed_official 146:f64d43ff0c18 1269
mbed_official 146:f64d43ff0c18 1270 /*!
mbed_official 146:f64d43ff0c18 1271 * @brief Sets the Automatic Trim Machine Select Setting.
mbed_official 146:f64d43ff0c18 1272 *
mbed_official 146:f64d43ff0c18 1273 * This function selects the IRCS clock for Auto Trim Test.
mbed_official 146:f64d43ff0c18 1274 *
mbed_official 146:f64d43ff0c18 1275 * @params setting Automatic Trim Machine Select Setting
mbed_official 146:f64d43ff0c18 1276 * - 0: 32 kHz Internal Reference Clock selected
mbed_official 146:f64d43ff0c18 1277 * - 1: 4 MHz Internal Reference Clock selected
mbed_official 146:f64d43ff0c18 1278 */
mbed_official 146:f64d43ff0c18 1279 static inline void clock_set_atms(mcg_atms_select_t setting)
mbed_official 146:f64d43ff0c18 1280 {
mbed_official 146:f64d43ff0c18 1281 BW_MCG_SC_ATMS(setting);
mbed_official 146:f64d43ff0c18 1282 }
mbed_official 146:f64d43ff0c18 1283
mbed_official 146:f64d43ff0c18 1284 /*!
mbed_official 146:f64d43ff0c18 1285 * @brief Gets the Automatic Trim Machine Select Setting.
mbed_official 146:f64d43ff0c18 1286 *
mbed_official 146:f64d43ff0c18 1287 * This function gets the Automatic Trim Machine Select Setting.
mbed_official 146:f64d43ff0c18 1288 *
mbed_official 146:f64d43ff0c18 1289 * @return setting Automatic Trim Machine Select Setting
mbed_official 146:f64d43ff0c18 1290 */
mbed_official 146:f64d43ff0c18 1291 static inline mcg_atms_select_t clock_get_atms(void)
mbed_official 146:f64d43ff0c18 1292 {
mbed_official 146:f64d43ff0c18 1293 return (mcg_atms_select_t)BR_MCG_SC_ATMS;
mbed_official 146:f64d43ff0c18 1294 }
mbed_official 146:f64d43ff0c18 1295
mbed_official 146:f64d43ff0c18 1296 /*!
mbed_official 146:f64d43ff0c18 1297 * @brief Sets the FLL Filter Preserve Enable Setting.
mbed_official 146:f64d43ff0c18 1298 *
mbed_official 146:f64d43ff0c18 1299 * This function sets the FLL Filter Preserve Enable. This bit prevents the
mbed_official 146:f64d43ff0c18 1300 * FLL filter values from resetting allowing the FLL output frequency to remain the
mbed_official 146:f64d43ff0c18 1301 * same during the clock mode changes where the FLL/DCO output is still valid.
mbed_official 146:f64d43ff0c18 1302 * (Note: This requires that the FLL reference frequency remain the same as
mbed_official 146:f64d43ff0c18 1303 * the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency
mbed_official 146:f64d43ff0c18 1304 * values change.)
mbed_official 146:f64d43ff0c18 1305 *
mbed_official 146:f64d43ff0c18 1306 * @params enable FLL Filter Preserve Enable Setting
mbed_official 146:f64d43ff0c18 1307 * - true: FLL filter and FLL frequency retain their previous values
mbed_official 146:f64d43ff0c18 1308 * during new clock mode change
mbed_official 146:f64d43ff0c18 1309 * - false: FLL filter and FLL frequency will reset on changes to correct
mbed_official 146:f64d43ff0c18 1310 * clock mode
mbed_official 146:f64d43ff0c18 1311 */
mbed_official 146:f64d43ff0c18 1312 static inline void clock_set_fltprsrv(bool enable)
mbed_official 146:f64d43ff0c18 1313 {
mbed_official 146:f64d43ff0c18 1314 BW_MCG_SC_FLTPRSRV(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1315 }
mbed_official 146:f64d43ff0c18 1316
mbed_official 146:f64d43ff0c18 1317 /*!
mbed_official 146:f64d43ff0c18 1318 * @brief Gets the FLL Filter Preserve Enable Setting.
mbed_official 146:f64d43ff0c18 1319 *
mbed_official 146:f64d43ff0c18 1320 * This function gets the FLL Filter Preserve Enable Setting.
mbed_official 146:f64d43ff0c18 1321 *
mbed_official 146:f64d43ff0c18 1322 * @return enabled True if FLL Filter Preserve is enabled.
mbed_official 146:f64d43ff0c18 1323 */
mbed_official 146:f64d43ff0c18 1324 static inline bool clock_get_fltprsrv(void)
mbed_official 146:f64d43ff0c18 1325 {
mbed_official 146:f64d43ff0c18 1326 return BR_MCG_SC_FLTPRSRV;
mbed_official 146:f64d43ff0c18 1327 }
mbed_official 146:f64d43ff0c18 1328
mbed_official 146:f64d43ff0c18 1329 /*!
mbed_official 146:f64d43ff0c18 1330 * @brief Sets the Fast Clock Internal Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1331 *
mbed_official 146:f64d43ff0c18 1332 * This function selects the amount to divide down the fast internal reference
mbed_official 146:f64d43ff0c18 1333 * clock. The resulting frequency is in the range 31.25 kHz to 4 MHz.
mbed_official 146:f64d43ff0c18 1334 * (Note: Changing the divider when the Fast IRC is enabled is not supported).
mbed_official 146:f64d43ff0c18 1335 *
mbed_official 146:f64d43ff0c18 1336 * @params setting Fast Clock Internal Reference Divider Setting
mbed_official 146:f64d43ff0c18 1337 */
mbed_official 146:f64d43ff0c18 1338 static inline void clock_set_fcrdiv(uint8_t setting)
mbed_official 146:f64d43ff0c18 1339 {
mbed_official 146:f64d43ff0c18 1340 BW_MCG_SC_FCRDIV(setting);
mbed_official 146:f64d43ff0c18 1341 }
mbed_official 146:f64d43ff0c18 1342
mbed_official 146:f64d43ff0c18 1343 /*!
mbed_official 146:f64d43ff0c18 1344 * @brief Gets the Fast Clock Internal Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1345 *
mbed_official 146:f64d43ff0c18 1346 * This function gets the Fast Clock Internal Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1347 *
mbed_official 146:f64d43ff0c18 1348 * @return setting Fast Clock Internal Reference Divider Setting
mbed_official 146:f64d43ff0c18 1349 */
mbed_official 146:f64d43ff0c18 1350 static inline uint8_t clock_get_fcrdiv(void)
mbed_official 146:f64d43ff0c18 1351 {
mbed_official 146:f64d43ff0c18 1352 return BR_MCG_SC_FCRDIV;
mbed_official 146:f64d43ff0c18 1353 }
mbed_official 146:f64d43ff0c18 1354
mbed_official 146:f64d43ff0c18 1355 /*!
mbed_official 146:f64d43ff0c18 1356 * @brief Sets the ATM Compare Value High Setting.
mbed_official 146:f64d43ff0c18 1357 *
mbed_official 146:f64d43ff0c18 1358 * This function sets the ATM compare value high setting. The values are used by the
mbed_official 146:f64d43ff0c18 1359 * Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM
mbed_official 146:f64d43ff0c18 1360 * SAR conversion.
mbed_official 146:f64d43ff0c18 1361 *
mbed_official 146:f64d43ff0c18 1362 * @params setting ATM Compare Value High Setting
mbed_official 146:f64d43ff0c18 1363 */
mbed_official 146:f64d43ff0c18 1364 static inline void clock_set_atcvh(uint8_t setting)
mbed_official 146:f64d43ff0c18 1365 {
mbed_official 146:f64d43ff0c18 1366 BW_MCG_ATCVH_ATCVH(setting);
mbed_official 146:f64d43ff0c18 1367 }
mbed_official 146:f64d43ff0c18 1368
mbed_official 146:f64d43ff0c18 1369 /*!
mbed_official 146:f64d43ff0c18 1370 * @brief Gets the ATM Compare Value High Setting.
mbed_official 146:f64d43ff0c18 1371 *
mbed_official 146:f64d43ff0c18 1372 * This function gets the ATM Compare Value High Setting.
mbed_official 146:f64d43ff0c18 1373 *
mbed_official 146:f64d43ff0c18 1374 * @return setting ATM Compare Value High Setting
mbed_official 146:f64d43ff0c18 1375 */
mbed_official 146:f64d43ff0c18 1376 static inline uint8_t clock_get_atcvh(void)
mbed_official 146:f64d43ff0c18 1377 {
mbed_official 146:f64d43ff0c18 1378 return BR_MCG_ATCVH_ATCVH;
mbed_official 146:f64d43ff0c18 1379 }
mbed_official 146:f64d43ff0c18 1380
mbed_official 146:f64d43ff0c18 1381 /*!
mbed_official 146:f64d43ff0c18 1382 * @brief Sets the ATM Compare Value Low Setting.
mbed_official 146:f64d43ff0c18 1383 *
mbed_official 146:f64d43ff0c18 1384 * This function sets the ATM compare value low setting. The values are used by the
mbed_official 146:f64d43ff0c18 1385 * Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM
mbed_official 146:f64d43ff0c18 1386 * SAR conversion.
mbed_official 146:f64d43ff0c18 1387 *
mbed_official 146:f64d43ff0c18 1388 * @params setting ATM Compare Value Low Setting
mbed_official 146:f64d43ff0c18 1389 */
mbed_official 146:f64d43ff0c18 1390 static inline void clock_set_atcvl(uint8_t setting)
mbed_official 146:f64d43ff0c18 1391 {
mbed_official 146:f64d43ff0c18 1392 BW_MCG_ATCVL_ATCVL(setting);
mbed_official 146:f64d43ff0c18 1393 }
mbed_official 146:f64d43ff0c18 1394
mbed_official 146:f64d43ff0c18 1395 /*!
mbed_official 146:f64d43ff0c18 1396 * @brief Gets the ATM Compare Value Low Setting.
mbed_official 146:f64d43ff0c18 1397 *
mbed_official 146:f64d43ff0c18 1398 * This function gets the ATM Compare Value Low Setting.
mbed_official 146:f64d43ff0c18 1399 *
mbed_official 146:f64d43ff0c18 1400 * @return setting ATM Compare Value Low Setting
mbed_official 146:f64d43ff0c18 1401 */
mbed_official 146:f64d43ff0c18 1402 static inline uint8_t clock_get_atcvl(void)
mbed_official 146:f64d43ff0c18 1403 {
mbed_official 146:f64d43ff0c18 1404 return BR_MCG_ATCVL_ATCVL;
mbed_official 146:f64d43ff0c18 1405 }
mbed_official 146:f64d43ff0c18 1406
mbed_official 146:f64d43ff0c18 1407 #if FSL_FEATURE_MCG_USE_OSCSEL
mbed_official 146:f64d43ff0c18 1408 /*!
mbed_official 146:f64d43ff0c18 1409 * @brief Sets the MCG OSC Clock Select Setting.
mbed_official 146:f64d43ff0c18 1410 *
mbed_official 146:f64d43ff0c18 1411 * This function selects the MCG FLL external reference clock.
mbed_official 146:f64d43ff0c18 1412 *
mbed_official 146:f64d43ff0c18 1413 * @params setting MCG OSC Clock Select Setting
mbed_official 146:f64d43ff0c18 1414 * - 0: Selects System Oscillator (OSCCLK).
mbed_official 146:f64d43ff0c18 1415 * - 1: Selects 32 kHz RTC Oscillator.
mbed_official 146:f64d43ff0c18 1416 */
mbed_official 146:f64d43ff0c18 1417 static inline void clock_set_oscsel(mcg_oscsel_select_t setting)
mbed_official 146:f64d43ff0c18 1418 {
mbed_official 146:f64d43ff0c18 1419 BW_MCG_C7_OSCSEL(setting);
mbed_official 146:f64d43ff0c18 1420 }
mbed_official 146:f64d43ff0c18 1421
mbed_official 146:f64d43ff0c18 1422 /*!
mbed_official 146:f64d43ff0c18 1423 * @brief Gets the MCG OSC Clock Select Setting.
mbed_official 146:f64d43ff0c18 1424 *
mbed_official 146:f64d43ff0c18 1425 * This function gets the MCG OSC Clock Select Setting.
mbed_official 146:f64d43ff0c18 1426 *
mbed_official 146:f64d43ff0c18 1427 * @return setting MCG OSC Clock Select Setting
mbed_official 146:f64d43ff0c18 1428 */
mbed_official 146:f64d43ff0c18 1429 static inline mcg_oscsel_select_t clock_get_oscsel(void)
mbed_official 146:f64d43ff0c18 1430 {
mbed_official 146:f64d43ff0c18 1431 return (mcg_oscsel_select_t)BR_MCG_C7_OSCSEL;
mbed_official 146:f64d43ff0c18 1432 }
mbed_official 146:f64d43ff0c18 1433 #endif /* FSL_FEATURE_MCG_USE_OSCSEL */
mbed_official 146:f64d43ff0c18 1434
mbed_official 146:f64d43ff0c18 1435 #if FSL_FEATURE_MCG_HAS_LOLRE
mbed_official 146:f64d43ff0c18 1436 /*!
mbed_official 146:f64d43ff0c18 1437 * @brief Sets the PLL Loss of Lock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1438 *
mbed_official 146:f64d43ff0c18 1439 * This function determines whether an interrupt or a reset request is made
mbed_official 146:f64d43ff0c18 1440 * following a PLL loss of lock.
mbed_official 146:f64d43ff0c18 1441 *
mbed_official 146:f64d43ff0c18 1442 * @params enable PLL Loss of Lock Reset Enable Setting
mbed_official 146:f64d43ff0c18 1443 * - true: Generate a reset request on a PLL loss of lock indication.
mbed_official 146:f64d43ff0c18 1444 * - false: Interrupt request is generated on a PLL loss of lock
mbed_official 146:f64d43ff0c18 1445 * indication. The PLL loss of lock interrupt enable bit
mbed_official 146:f64d43ff0c18 1446 * must also be set to generate the interrupt request.
mbed_official 146:f64d43ff0c18 1447 */
mbed_official 146:f64d43ff0c18 1448 static inline void clock_set_lolre(bool enable)
mbed_official 146:f64d43ff0c18 1449 {
mbed_official 146:f64d43ff0c18 1450 BW_MCG_C8_LOLRE(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1451 }
mbed_official 146:f64d43ff0c18 1452
mbed_official 146:f64d43ff0c18 1453 /*!
mbed_official 146:f64d43ff0c18 1454 * @brief Gets the PLL Loss of Lock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1455 *
mbed_official 146:f64d43ff0c18 1456 * This function gets the PLL Loss of Lock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1457 *
mbed_official 146:f64d43ff0c18 1458 * @return enabled True if the PLL Loss of Lock Reset is enabled.
mbed_official 146:f64d43ff0c18 1459 */
mbed_official 146:f64d43ff0c18 1460 static inline bool clock_get_lolre(void)
mbed_official 146:f64d43ff0c18 1461 {
mbed_official 146:f64d43ff0c18 1462 return BR_MCG_C8_LOLRE;
mbed_official 146:f64d43ff0c18 1463 }
mbed_official 146:f64d43ff0c18 1464 #endif /* FSL_FEATURE_MCG_HAS_LOLRE */
mbed_official 146:f64d43ff0c18 1465
mbed_official 146:f64d43ff0c18 1466
mbed_official 146:f64d43ff0c18 1467 #if FSL_FEATURE_MCG_HAS_RTC_32K
mbed_official 146:f64d43ff0c18 1468 /*!
mbed_official 146:f64d43ff0c18 1469 * @brief Sets the Loss of Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1470 *
mbed_official 146:f64d43ff0c18 1471 * This function determines whether an interrupt or a reset request is made following
mbed_official 146:f64d43ff0c18 1472 * a loss of the RTC external reference clock. The LOCRE1 only has an affect when CME1
mbed_official 146:f64d43ff0c18 1473 * is set.
mbed_official 146:f64d43ff0c18 1474 *
mbed_official 146:f64d43ff0c18 1475 * @params enable Loss of Clock Reset Enable Setting
mbed_official 146:f64d43ff0c18 1476 * - true: Generate a reset request on a loss of RTC external reference clock.
mbed_official 146:f64d43ff0c18 1477 * - false: Interrupt request is generated on a loss of RTC external
mbed_official 146:f64d43ff0c18 1478 * reference clock.
mbed_official 146:f64d43ff0c18 1479 */
mbed_official 146:f64d43ff0c18 1480 static inline void clock_set_locre1(bool enable)
mbed_official 146:f64d43ff0c18 1481 {
mbed_official 146:f64d43ff0c18 1482 BW_MCG_C8_LOCRE1(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1483 }
mbed_official 146:f64d43ff0c18 1484
mbed_official 146:f64d43ff0c18 1485 /*!
mbed_official 146:f64d43ff0c18 1486 * @brief Gets the Loss of Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1487 *
mbed_official 146:f64d43ff0c18 1488 * This function gets the Loss of Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1489 *
mbed_official 146:f64d43ff0c18 1490 * @return enabled True if Loss of Clock Reset is enabled.
mbed_official 146:f64d43ff0c18 1491 */
mbed_official 146:f64d43ff0c18 1492 static inline bool clock_get_locre1(void)
mbed_official 146:f64d43ff0c18 1493 {
mbed_official 146:f64d43ff0c18 1494 return BR_MCG_C8_LOCRE1;
mbed_official 146:f64d43ff0c18 1495 }
mbed_official 146:f64d43ff0c18 1496
mbed_official 146:f64d43ff0c18 1497 /*!
mbed_official 146:f64d43ff0c18 1498 * @brief Sets the Clock Monitor Enable1 Setting.
mbed_official 146:f64d43ff0c18 1499 *
mbed_official 146:f64d43ff0c18 1500 * This function enables/disables the loss of the clock monitoring circuit for the
mbed_official 146:f64d43ff0c18 1501 * output of the RTC external reference clock. The LOCRE1 bit determines whether an
mbed_official 146:f64d43ff0c18 1502 * interrupt or a reset request is generated following a loss of the RTC clock indication.
mbed_official 146:f64d43ff0c18 1503 * The CME1 bit should only be set to a logic 1 when the MCG is in an operational mode
mbed_official 146:f64d43ff0c18 1504 * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). CME1 bit must be set to
mbed_official 146:f64d43ff0c18 1505 * a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur
mbed_official 146:f64d43ff0c18 1506 * while in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or
mbed_official 146:f64d43ff0c18 1507 * VLPW power modes if the MCG is in BLPE mode.
mbed_official 146:f64d43ff0c18 1508 *
mbed_official 146:f64d43ff0c18 1509 * @params enable Clock Monitor Enable1 Setting
mbed_official 146:f64d43ff0c18 1510 * - true: External clock monitor is enabled for RTC clock.
mbed_official 146:f64d43ff0c18 1511 * - false: External clock monitor is disabled for RTC clock.
mbed_official 146:f64d43ff0c18 1512 */
mbed_official 146:f64d43ff0c18 1513 static inline void clock_set_cme1(bool enable)
mbed_official 146:f64d43ff0c18 1514 {
mbed_official 146:f64d43ff0c18 1515 BW_MCG_C8_CME1(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1516 }
mbed_official 146:f64d43ff0c18 1517
mbed_official 146:f64d43ff0c18 1518 /*!
mbed_official 146:f64d43ff0c18 1519 * @brief Gets the Clock Monitor Enable1 Setting.
mbed_official 146:f64d43ff0c18 1520 *
mbed_official 146:f64d43ff0c18 1521 * This function gets the Clock Monitor Enable1 Setting.
mbed_official 146:f64d43ff0c18 1522 *
mbed_official 146:f64d43ff0c18 1523 * @return enabled True if Clock Monitor Enable1 is enabled
mbed_official 146:f64d43ff0c18 1524 */
mbed_official 146:f64d43ff0c18 1525 static inline bool clock_get_cme1(void)
mbed_official 146:f64d43ff0c18 1526 {
mbed_official 146:f64d43ff0c18 1527 return BR_MCG_C8_CME1;
mbed_official 146:f64d43ff0c18 1528 }
mbed_official 146:f64d43ff0c18 1529
mbed_official 146:f64d43ff0c18 1530 /*!
mbed_official 146:f64d43ff0c18 1531 * @brief Gets the RTC Loss of Clock Status.
mbed_official 146:f64d43ff0c18 1532 *
mbed_official 146:f64d43ff0c18 1533 * This function gets the RTC Loss of Clock Status. This bit indicates when a loss
mbed_official 146:f64d43ff0c18 1534 * of clock has occurred. This bit is cleared by writing a logic 1 to it when set.
mbed_official 146:f64d43ff0c18 1535 *
mbed_official 146:f64d43ff0c18 1536 * @return status RTC Loss of Clock Status
mbed_official 146:f64d43ff0c18 1537 * - 0: Loss of RTC has not occurred
mbed_official 146:f64d43ff0c18 1538 * - 1: Loss of RTC has occurred
mbed_official 146:f64d43ff0c18 1539 */
mbed_official 146:f64d43ff0c18 1540 static inline mcg_locs1_status_t clock_get_locs1(void)
mbed_official 146:f64d43ff0c18 1541 {
mbed_official 146:f64d43ff0c18 1542 return (mcg_locs1_status_t)BR_MCG_C8_LOCS1;
mbed_official 146:f64d43ff0c18 1543 }
mbed_official 146:f64d43ff0c18 1544 #endif /* FSL_FEATURE_MCG_HAS_RTC_32K */
mbed_official 146:f64d43ff0c18 1545
mbed_official 146:f64d43ff0c18 1546 #if FSL_FEATURE_MCG_USE_PLLREFSEL
mbed_official 146:f64d43ff0c18 1547 /*!
mbed_official 146:f64d43ff0c18 1548 * @brief Sets the OSC1 Loss of Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1549 *
mbed_official 146:f64d43ff0c18 1550 * This function determines whether an interrupt or reset request is made following
mbed_official 146:f64d43ff0c18 1551 * a loss of OSC1 external reference clock. The LOCRE2 only has an affect when
mbed_official 146:f64d43ff0c18 1552 * LOCS2 is set.
mbed_official 146:f64d43ff0c18 1553 *
mbed_official 146:f64d43ff0c18 1554 * @params enable OSC1 Loss of Clock Reset Enable Setting
mbed_official 146:f64d43ff0c18 1555 * - true: Reset request is generated on a loss of OSC1 external
mbed_official 146:f64d43ff0c18 1556 * reference clock..
mbed_official 146:f64d43ff0c18 1557 * - false: Interrupt request is generated on a loss of OSC1 external
mbed_official 146:f64d43ff0c18 1558 * reference clock.
mbed_official 146:f64d43ff0c18 1559 */
mbed_official 146:f64d43ff0c18 1560 static inline void clock_set_locre2(bool enable)
mbed_official 146:f64d43ff0c18 1561 {
mbed_official 146:f64d43ff0c18 1562 BW_MCG_C10_LOCRE2(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1563 }
mbed_official 146:f64d43ff0c18 1564
mbed_official 146:f64d43ff0c18 1565 /*!
mbed_official 146:f64d43ff0c18 1566 * @brief Gets the OSC1 Loss of the Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1567 *
mbed_official 146:f64d43ff0c18 1568 * This function gets the OSC1 Loss of Clock Reset Enable Setting.
mbed_official 146:f64d43ff0c18 1569 *
mbed_official 146:f64d43ff0c18 1570 * @return enabled True if OSC1 Loss of Clock Reset is enabled.
mbed_official 146:f64d43ff0c18 1571 */
mbed_official 146:f64d43ff0c18 1572 static inline bool clock_get_locre2(void)
mbed_official 146:f64d43ff0c18 1573 {
mbed_official 146:f64d43ff0c18 1574 return BR_MCG_C10_LOCRE2;
mbed_official 146:f64d43ff0c18 1575 }
mbed_official 146:f64d43ff0c18 1576
mbed_official 146:f64d43ff0c18 1577 /*!
mbed_official 146:f64d43ff0c18 1578 * @brief Sets the Frequency Range1 Select Setting.
mbed_official 146:f64d43ff0c18 1579 *
mbed_official 146:f64d43ff0c18 1580 * This function selects the frequency range for the OSC1 crystal oscillator
mbed_official 146:f64d43ff0c18 1581 * or an external clock source. See the Oscillator chapter for more details and
mbed_official 146:f64d43ff0c18 1582 * the device data sheet for the frequency ranges used.
mbed_official 146:f64d43ff0c18 1583 *
mbed_official 146:f64d43ff0c18 1584 * @params setting Frequency Range1 Select Setting
mbed_official 146:f64d43ff0c18 1585 * - 00: Low frequency range selected for the crystal oscillator.
mbed_official 146:f64d43ff0c18 1586 * - 01: High frequency range selected for the crystal oscillator.
mbed_official 146:f64d43ff0c18 1587 * - 1X: Very high frequency range selected for the crystal oscillator.
mbed_official 146:f64d43ff0c18 1588 */
mbed_official 146:f64d43ff0c18 1589 static inline void clock_set_range1(mcg_freq_range_select_t setting)
mbed_official 146:f64d43ff0c18 1590 {
mbed_official 146:f64d43ff0c18 1591 BW_MCG_C10_RANGE1(setting);
mbed_official 146:f64d43ff0c18 1592 }
mbed_official 146:f64d43ff0c18 1593
mbed_official 146:f64d43ff0c18 1594 /*!
mbed_official 146:f64d43ff0c18 1595 * @brief Gets the Frequency Range1 Select Setting.
mbed_official 146:f64d43ff0c18 1596 *
mbed_official 146:f64d43ff0c18 1597 * This function gets the Frequency Range1 Select Setting.
mbed_official 146:f64d43ff0c18 1598 *
mbed_official 146:f64d43ff0c18 1599 * @return setting Frequency Range1 Select Setting
mbed_official 146:f64d43ff0c18 1600 */
mbed_official 146:f64d43ff0c18 1601 static inline mcg_freq_range_select_t clock_get_range1(void)
mbed_official 146:f64d43ff0c18 1602 {
mbed_official 146:f64d43ff0c18 1603 return (mcg_freq_range_select_t)BR_MCG_C10_RANGE1;
mbed_official 146:f64d43ff0c18 1604 }
mbed_official 146:f64d43ff0c18 1605
mbed_official 146:f64d43ff0c18 1606 /*!
mbed_official 146:f64d43ff0c18 1607 * @brief Sets the High Gain Oscillator1 Select Setting.
mbed_official 146:f64d43ff0c18 1608 *
mbed_official 146:f64d43ff0c18 1609 * This function controls the OSC1 crystal oscillator mode of operation.
mbed_official 146:f64d43ff0c18 1610 * See the Oscillator chapter for more details.
mbed_official 146:f64d43ff0c18 1611 *
mbed_official 146:f64d43ff0c18 1612 * @params setting High Gain Oscillator1 Select Setting
mbed_official 146:f64d43ff0c18 1613 * - 0: Configure crystal oscillator for low-power operation.
mbed_official 146:f64d43ff0c18 1614 * - 1: Configure crystal oscillator for high-gain operation.
mbed_official 146:f64d43ff0c18 1615 */
mbed_official 146:f64d43ff0c18 1616 static inline void clock_set_hgo1(mcg_hgo_select_t setting)
mbed_official 146:f64d43ff0c18 1617 {
mbed_official 146:f64d43ff0c18 1618 BW_MCG_C10_HGO1(setting);
mbed_official 146:f64d43ff0c18 1619 }
mbed_official 146:f64d43ff0c18 1620
mbed_official 146:f64d43ff0c18 1621 /*!
mbed_official 146:f64d43ff0c18 1622 * @brief Gets the High Gain Oscillator1 Select Setting.
mbed_official 146:f64d43ff0c18 1623 *
mbed_official 146:f64d43ff0c18 1624 * This function gets the High Gain Oscillator1 Select Setting.
mbed_official 146:f64d43ff0c18 1625 *
mbed_official 146:f64d43ff0c18 1626 * @return setting High Gain Oscillator1 Select Setting
mbed_official 146:f64d43ff0c18 1627 */
mbed_official 146:f64d43ff0c18 1628 static inline mcg_hgo_select_t clock_get_hgo1(void)
mbed_official 146:f64d43ff0c18 1629 {
mbed_official 146:f64d43ff0c18 1630 return (mcg_hgo_select_t)BR_MCG_C10_HGO1;
mbed_official 146:f64d43ff0c18 1631 }
mbed_official 146:f64d43ff0c18 1632
mbed_official 146:f64d43ff0c18 1633 /*!
mbed_official 146:f64d43ff0c18 1634 * @brief Sets the External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1635 *
mbed_official 146:f64d43ff0c18 1636 * This function selects the source for the OSC1 external reference clock.
mbed_official 146:f64d43ff0c18 1637 * See the Oscillator chapter for more details.
mbed_official 146:f64d43ff0c18 1638 *
mbed_official 146:f64d43ff0c18 1639 * @params setting External Reference Select Setting
mbed_official 146:f64d43ff0c18 1640 * - 0: External reference clock requested.
mbed_official 146:f64d43ff0c18 1641 * - 1: Oscillator requested.
mbed_official 146:f64d43ff0c18 1642 */
mbed_official 146:f64d43ff0c18 1643 static inline void clock_set_erefs1(mcg_eref_clock_select_t setting)
mbed_official 146:f64d43ff0c18 1644 {
mbed_official 146:f64d43ff0c18 1645 BW_MCG_C10_EREFS1(setting);
mbed_official 146:f64d43ff0c18 1646 }
mbed_official 146:f64d43ff0c18 1647
mbed_official 146:f64d43ff0c18 1648 /*!
mbed_official 146:f64d43ff0c18 1649 * @brief Gets the External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1650 *
mbed_official 146:f64d43ff0c18 1651 * This function gets the External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1652 *
mbed_official 146:f64d43ff0c18 1653 * @return setting External Reference Select Setting
mbed_official 146:f64d43ff0c18 1654 */
mbed_official 146:f64d43ff0c18 1655 static inline mcg_eref_clock_select_t clock_get_erefs1(void)
mbed_official 146:f64d43ff0c18 1656 {
mbed_official 146:f64d43ff0c18 1657 return (mcg_eref_clock_select_t)BR_MCG_C10_EREFS1;
mbed_official 146:f64d43ff0c18 1658 }
mbed_official 146:f64d43ff0c18 1659
mbed_official 146:f64d43ff0c18 1660 /*!
mbed_official 146:f64d43ff0c18 1661 * @brief Sets the PLL1 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1662 *
mbed_official 146:f64d43ff0c18 1663 * This function selects the PLL1 external reference clock source.
mbed_official 146:f64d43ff0c18 1664 *
mbed_official 146:f64d43ff0c18 1665 * @params setting PLL1 External Reference Select Setting
mbed_official 146:f64d43ff0c18 1666 * - 0: Selects OSC0 clock source as its external reference clock.
mbed_official 146:f64d43ff0c18 1667 * - 1: Selects OSC1 clock source as its external reference clock.
mbed_official 146:f64d43ff0c18 1668 */
mbed_official 146:f64d43ff0c18 1669 static inline void clock_set_pllrefsel1(mcg_pll_eref_clock_select_t setting)
mbed_official 146:f64d43ff0c18 1670 {
mbed_official 146:f64d43ff0c18 1671 BW_MCG_C11_PLLREFSEL1(setting);
mbed_official 146:f64d43ff0c18 1672 }
mbed_official 146:f64d43ff0c18 1673
mbed_official 146:f64d43ff0c18 1674 /*!
mbed_official 146:f64d43ff0c18 1675 * @brief Gets the PLL1 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1676 *
mbed_official 146:f64d43ff0c18 1677 * This function gets the PLL1 External Reference Select Setting.
mbed_official 146:f64d43ff0c18 1678 *
mbed_official 146:f64d43ff0c18 1679 * @return setting PLL1 External Reference Select Setting
mbed_official 146:f64d43ff0c18 1680 */
mbed_official 146:f64d43ff0c18 1681 static inline mcg_pll_eref_clock_select_t clock_get_pllrefsel1(void)
mbed_official 146:f64d43ff0c18 1682 {
mbed_official 146:f64d43ff0c18 1683 return (mcg_pll_eref_clock_select_t)BR_MCG_C11_PLLREFSEL1;
mbed_official 146:f64d43ff0c18 1684 }
mbed_official 146:f64d43ff0c18 1685
mbed_official 146:f64d43ff0c18 1686 /*!
mbed_official 146:f64d43ff0c18 1687 * @brief Sets the PLL1 Clock Enable Setting.
mbed_official 146:f64d43ff0c18 1688 *
mbed_official 146:f64d43ff0c18 1689 * This function enables/disables the PLL1 independent of PLLS and enables the
mbed_official 146:f64d43ff0c18 1690 * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs
mbed_official 146:f64d43ff0c18 1691 * to be programmed to the correct divider to generate a PLL1 reference clock in a
mbed_official 146:f64d43ff0c18 1692 * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1
mbed_official 146:f64d43ff0c18 1693 * enables the PLL1 selected external oscillator if not already enabled.
mbed_official 146:f64d43ff0c18 1694 * Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the
mbed_official 146:f64d43ff0c18 1695 * external oscillator is used as the reference clock, the OSCINIT1 bit should
mbed_official 146:f64d43ff0c18 1696 * be checked to make sure it is set.
mbed_official 146:f64d43ff0c18 1697 *
mbed_official 146:f64d43ff0c18 1698 * @params enable PLL1 Clock Enable Setting
mbed_official 146:f64d43ff0c18 1699 * - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless
mbed_official 146:f64d43ff0c18 1700 * MCG is in a bypass mode with LP=1 (BLPI or BLPE).
mbed_official 146:f64d43ff0c18 1701 * - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive.
mbed_official 146:f64d43ff0c18 1702 */
mbed_official 146:f64d43ff0c18 1703 static inline void clock_set_pllclken1(bool enable)
mbed_official 146:f64d43ff0c18 1704 {
mbed_official 146:f64d43ff0c18 1705 BW_MCG_C11_PLLCLKEN1(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1706 }
mbed_official 146:f64d43ff0c18 1707
mbed_official 146:f64d43ff0c18 1708 /*!
mbed_official 146:f64d43ff0c18 1709 * @brief Gets the PLL1 Clock Enable Setting.
mbed_official 146:f64d43ff0c18 1710 *
mbed_official 146:f64d43ff0c18 1711 * This function gets the PLL1 Clock Enable Setting.
mbed_official 146:f64d43ff0c18 1712 *
mbed_official 146:f64d43ff0c18 1713 * @return enabled True if the PLL1 Clock is enabled.
mbed_official 146:f64d43ff0c18 1714 */
mbed_official 146:f64d43ff0c18 1715 static inline bool clock_get_pllclken1(void)
mbed_official 146:f64d43ff0c18 1716 {
mbed_official 146:f64d43ff0c18 1717 return BR_MCG_C11_PLLCLKEN1;
mbed_official 146:f64d43ff0c18 1718 }
mbed_official 146:f64d43ff0c18 1719
mbed_official 146:f64d43ff0c18 1720 /*!
mbed_official 146:f64d43ff0c18 1721 * @brief Sets the PLL1 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 1722 *
mbed_official 146:f64d43ff0c18 1723 * This function enables/disables the PLL1 Clock during the Normal Stop (In Low
mbed_official 146:f64d43ff0c18 1724 * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other
mbed_official 146:f64d43ff0c18 1725 * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to
mbed_official 146:f64d43ff0c18 1726 * run if it is written to 1.
mbed_official 146:f64d43ff0c18 1727 *
mbed_official 146:f64d43ff0c18 1728 * @params enable PLL1 Stop Enable Setting
mbed_official 146:f64d43ff0c18 1729 * - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and
mbed_official 146:f64d43ff0c18 1730 * MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
mbed_official 146:f64d43ff0c18 1731 * - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X)
mbed_official 146:f64d43ff0c18 1732 * are disabled in any of the Stop modes.
mbed_official 146:f64d43ff0c18 1733 */
mbed_official 146:f64d43ff0c18 1734 static inline void clock_set_pllsten1(bool enable)
mbed_official 146:f64d43ff0c18 1735 {
mbed_official 146:f64d43ff0c18 1736 BW_MCG_C11_PLLSTEN1(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1737 }
mbed_official 146:f64d43ff0c18 1738
mbed_official 146:f64d43ff0c18 1739 /*!
mbed_official 146:f64d43ff0c18 1740 * @brief Gets the PLL1 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 1741 *
mbed_official 146:f64d43ff0c18 1742 * This function gets the PLL1 Stop Enable Setting.
mbed_official 146:f64d43ff0c18 1743 *
mbed_official 146:f64d43ff0c18 1744 * @return enabled True if PLL1 Stop is enabled.
mbed_official 146:f64d43ff0c18 1745 */
mbed_official 146:f64d43ff0c18 1746 static inline bool clock_get_pllsten1(void)
mbed_official 146:f64d43ff0c18 1747 {
mbed_official 146:f64d43ff0c18 1748 return BR_MCG_C11_PLLSTEN1;
mbed_official 146:f64d43ff0c18 1749 }
mbed_official 146:f64d43ff0c18 1750
mbed_official 146:f64d43ff0c18 1751 /*!
mbed_official 146:f64d43ff0c18 1752 * @brief Sets the PLL Clock Select Setting.
mbed_official 146:f64d43ff0c18 1753 *
mbed_official 146:f64d43ff0c18 1754 * This function controls whether the PLL0 or PLL1 output is selected as the
mbed_official 146:f64d43ff0c18 1755 * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode
mbed_official 146:f64d43ff0c18 1756 * (CLKS[1:0]=00 and IREFS=0 and PLLS=1).
mbed_official 146:f64d43ff0c18 1757 *
mbed_official 146:f64d43ff0c18 1758 * @params setting PLL Clock Select Setting
mbed_official 146:f64d43ff0c18 1759 * - 0: PLL0 output clock is selected.
mbed_official 146:f64d43ff0c18 1760 * - 1: PLL1 output clock is selected.
mbed_official 146:f64d43ff0c18 1761 */
mbed_official 146:f64d43ff0c18 1762 static inline void clock_set_pllcs(mcg_pllcs_select_t setting)
mbed_official 146:f64d43ff0c18 1763 {
mbed_official 146:f64d43ff0c18 1764 BW_MCG_C11_PLLCS(setting);
mbed_official 146:f64d43ff0c18 1765 }
mbed_official 146:f64d43ff0c18 1766
mbed_official 146:f64d43ff0c18 1767 /*!
mbed_official 146:f64d43ff0c18 1768 * @brief Gets the PLL Clock Select Setting.
mbed_official 146:f64d43ff0c18 1769 *
mbed_official 146:f64d43ff0c18 1770 * This function gets the PLL Clock Select Setting.
mbed_official 146:f64d43ff0c18 1771 *
mbed_official 146:f64d43ff0c18 1772 * @return setting PLL Clock Select Setting
mbed_official 146:f64d43ff0c18 1773 */
mbed_official 146:f64d43ff0c18 1774 static inline mcg_pllcs_select_t clock_get_pllcs(void)
mbed_official 146:f64d43ff0c18 1775 {
mbed_official 146:f64d43ff0c18 1776 return (mcg_pllcs_select_t)BR_MCG_C11_PLLCS;
mbed_official 146:f64d43ff0c18 1777 }
mbed_official 146:f64d43ff0c18 1778
mbed_official 146:f64d43ff0c18 1779 /*!
mbed_official 146:f64d43ff0c18 1780 * @brief Sets the PLL1 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1781 *
mbed_official 146:f64d43ff0c18 1782 * This function selects the amount to divide down the external reference
mbed_official 146:f64d43ff0c18 1783 * clock selected by REFSEL2 for PLL1. The resulting frequency must be in a valid
mbed_official 146:f64d43ff0c18 1784 * reference range. After the PLL1 is enabled (by setting either PLLCLKEN1 or PLLS),
mbed_official 146:f64d43ff0c18 1785 * the PRDIV1 value must not be changed when LOCK1 is zero.
mbed_official 146:f64d43ff0c18 1786 *
mbed_official 146:f64d43ff0c18 1787 * @params setting PLL1 External Reference Divider Setting
mbed_official 146:f64d43ff0c18 1788 */
mbed_official 146:f64d43ff0c18 1789 static inline void clock_set_prdiv1(uint8_t setting)
mbed_official 146:f64d43ff0c18 1790 {
mbed_official 146:f64d43ff0c18 1791 BW_MCG_C11_PRDIV1(setting);
mbed_official 146:f64d43ff0c18 1792 }
mbed_official 146:f64d43ff0c18 1793
mbed_official 146:f64d43ff0c18 1794 /*!
mbed_official 146:f64d43ff0c18 1795 * @brief Gets the PLL1 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1796 *
mbed_official 146:f64d43ff0c18 1797 * This function gets the PLL1 External Reference Divider Setting.
mbed_official 146:f64d43ff0c18 1798 *
mbed_official 146:f64d43ff0c18 1799 * @return setting PLL1 External Reference Divider Setting
mbed_official 146:f64d43ff0c18 1800 */
mbed_official 146:f64d43ff0c18 1801 static inline uint8_t clock_get_prdiv1(void)
mbed_official 146:f64d43ff0c18 1802 {
mbed_official 146:f64d43ff0c18 1803 return BR_MCG_C11_PRDIV1;
mbed_official 146:f64d43ff0c18 1804 }
mbed_official 146:f64d43ff0c18 1805
mbed_official 146:f64d43ff0c18 1806 /*!
mbed_official 146:f64d43ff0c18 1807 * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 1808 *
mbed_official 146:f64d43ff0c18 1809 * This function determines whether an interrupt request is made following a
mbed_official 146:f64d43ff0c18 1810 * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set.
mbed_official 146:f64d43ff0c18 1811 *
mbed_official 146:f64d43ff0c18 1812 * @params enable PLL1 Loss of Lock Interrupt Enable Setting
mbed_official 146:f64d43ff0c18 1813 * - true: Generate an interrupt request on loss of lock on PLL1.
mbed_official 146:f64d43ff0c18 1814 * - false: No interrupt request is generated on loss of lock on PLL1.
mbed_official 146:f64d43ff0c18 1815 */
mbed_official 146:f64d43ff0c18 1816 static inline void clock_set_lolie1(bool enable)
mbed_official 146:f64d43ff0c18 1817 {
mbed_official 146:f64d43ff0c18 1818 BW_MCG_C12_LOLIE1(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1819 }
mbed_official 146:f64d43ff0c18 1820
mbed_official 146:f64d43ff0c18 1821 /*!
mbed_official 146:f64d43ff0c18 1822 * @brief Gets the PLL1 Loss of Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 1823 *
mbed_official 146:f64d43ff0c18 1824 * This function gets the PLL1 Loss of Lock Interrupt Enable Setting.
mbed_official 146:f64d43ff0c18 1825 *
mbed_official 146:f64d43ff0c18 1826 * @return enabled true if PLL1 Loss of Lock Interrupt is enabled.
mbed_official 146:f64d43ff0c18 1827 */
mbed_official 146:f64d43ff0c18 1828 static inline bool clock_get_lolie1(void)
mbed_official 146:f64d43ff0c18 1829 {
mbed_official 146:f64d43ff0c18 1830 return BR_MCG_C12_LOLIE1;
mbed_official 146:f64d43ff0c18 1831 }
mbed_official 146:f64d43ff0c18 1832
mbed_official 146:f64d43ff0c18 1833 /*!
mbed_official 146:f64d43ff0c18 1834 * @brief Sets the Clock Monitor Enable2 Setting
mbed_official 146:f64d43ff0c18 1835 *
mbed_official 146:f64d43ff0c18 1836 * This function enables/disables the loss of the clock monitor for the OSC1 external
mbed_official 146:f64d43ff0c18 1837 * reference clock. LOCRE2 determines whether a reset or interrupt request is generated
mbed_official 146:f64d43ff0c18 1838 * following a loss of OSC1 external reference clock. The CME2 bit should only be set
mbed_official 146:f64d43ff0c18 1839 * to a logic 1 when the MCG is in an operational mode that uses the external clock
mbed_official 146:f64d43ff0c18 1840 * (PEE or PBE) . Whenever the CME2 bit is set to a logic 1, the value of the RANGE1
mbed_official 146:f64d43ff0c18 1841 * bits in the C10 register should not be changed. CME2 bit should be set to a logic 0
mbed_official 146:f64d43ff0c18 1842 * before the MCG enters any Stop mode. Otherwise, a reset request may occur while in
mbed_official 146:f64d43ff0c18 1843 * Stop mode.
mbed_official 146:f64d43ff0c18 1844 *
mbed_official 146:f64d43ff0c18 1845 * @params enable Clock Monitor Enable2 Setting
mbed_official 146:f64d43ff0c18 1846 * - true: Generate a reset request on loss of external clock on OSC1.
mbed_official 146:f64d43ff0c18 1847 * - false: External clock monitor for OSC1 is disabled.
mbed_official 146:f64d43ff0c18 1848 */
mbed_official 146:f64d43ff0c18 1849 static inline void clock_set_cme2(bool enable)
mbed_official 146:f64d43ff0c18 1850 {
mbed_official 146:f64d43ff0c18 1851 BW_MCG_C12_CME2(enable ? 1 : 0);
mbed_official 146:f64d43ff0c18 1852 }
mbed_official 146:f64d43ff0c18 1853
mbed_official 146:f64d43ff0c18 1854 /*!
mbed_official 146:f64d43ff0c18 1855 * @brief Gets the Clock Monitor Enable2 Setting.
mbed_official 146:f64d43ff0c18 1856 *
mbed_official 146:f64d43ff0c18 1857 * This function gets the Clock Monitor Enable2 Setting.
mbed_official 146:f64d43ff0c18 1858 *
mbed_official 146:f64d43ff0c18 1859 * @return enabled True if Clock Monitor Enable2 is enabled.
mbed_official 146:f64d43ff0c18 1860 */
mbed_official 146:f64d43ff0c18 1861 static inline bool clock_get_cme2(void)
mbed_official 146:f64d43ff0c18 1862 {
mbed_official 146:f64d43ff0c18 1863 return BR_MCG_C12_CME2;
mbed_official 146:f64d43ff0c18 1864 }
mbed_official 146:f64d43ff0c18 1865
mbed_official 146:f64d43ff0c18 1866 /*!
mbed_official 146:f64d43ff0c18 1867 * @brief Sets the VCO1 Divider Setting.
mbed_official 146:f64d43ff0c18 1868 *
mbed_official 146:f64d43ff0c18 1869 * This function selects the amount to divide the VCO output of the PLL1.
mbed_official 146:f64d43ff0c18 1870 * The VDIV1 bits establishes the multiplication factor (M) applied to the reference
mbed_official 146:f64d43ff0c18 1871 * clock frequency. After the PLL1 is enabled (by setting either PLLCLKEN1 or
mbed_official 146:f64d43ff0c18 1872 * PLLS), the VDIV1 value must not be changed when LOCK1 is zero.
mbed_official 146:f64d43ff0c18 1873 *
mbed_official 146:f64d43ff0c18 1874 * @params setting VCO1 Divider Setting
mbed_official 146:f64d43ff0c18 1875 */
mbed_official 146:f64d43ff0c18 1876 static inline void clock_set_vdiv1(uint8_t setting)
mbed_official 146:f64d43ff0c18 1877 {
mbed_official 146:f64d43ff0c18 1878 BW_MCG_C12_VDIV1(setting);
mbed_official 146:f64d43ff0c18 1879 }
mbed_official 146:f64d43ff0c18 1880
mbed_official 146:f64d43ff0c18 1881 /*!
mbed_official 146:f64d43ff0c18 1882 * @brief Gets the VCO1 Divider Setting.
mbed_official 146:f64d43ff0c18 1883 *
mbed_official 146:f64d43ff0c18 1884 * This function gets the VCO1 Divider Setting.
mbed_official 146:f64d43ff0c18 1885 *
mbed_official 146:f64d43ff0c18 1886 * @return setting VCO1 Divider Setting
mbed_official 146:f64d43ff0c18 1887 */
mbed_official 146:f64d43ff0c18 1888 static inline uint8_t clock_get_vdiv1(void)
mbed_official 146:f64d43ff0c18 1889 {
mbed_official 146:f64d43ff0c18 1890 return BR_MCG_C12_VDIV1;
mbed_official 146:f64d43ff0c18 1891 }
mbed_official 146:f64d43ff0c18 1892
mbed_official 146:f64d43ff0c18 1893 /*!
mbed_official 146:f64d43ff0c18 1894 * @brief Gets the Loss of the Lock2 Status.
mbed_official 146:f64d43ff0c18 1895 *
mbed_official 146:f64d43ff0c18 1896 * This function gets the Loss of the Lock2 Status. This bit is a sticky bit indicating
mbed_official 146:f64d43ff0c18 1897 * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1
mbed_official 146:f64d43ff0c18 1898 * output frequency has fallen outside the lock exit frequency tolerance, D unl.
mbed_official 146:f64d43ff0c18 1899 * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This
mbed_official 146:f64d43ff0c18 1900 * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0
mbed_official 146:f64d43ff0c18 1901 * to this bit has no effect.
mbed_official 146:f64d43ff0c18 1902 *
mbed_official 146:f64d43ff0c18 1903 * @return status Loss of Lock2 Status
mbed_official 146:f64d43ff0c18 1904 * - 0: PLL1 has not lost lock since LOLS1 was last cleared.
mbed_official 146:f64d43ff0c18 1905 * - 1: PLL1 has lost lock since LOLS1 was last cleared.
mbed_official 146:f64d43ff0c18 1906 */
mbed_official 146:f64d43ff0c18 1907 static inline mcg_lols_status_t clock_get_lols1(void)
mbed_official 146:f64d43ff0c18 1908 {
mbed_official 146:f64d43ff0c18 1909 return (mcg_lols_status_t)BR_MCG_S2_LOLS1;
mbed_official 146:f64d43ff0c18 1910 }
mbed_official 146:f64d43ff0c18 1911
mbed_official 146:f64d43ff0c18 1912 /*!
mbed_official 146:f64d43ff0c18 1913 * @brief Gets the Lock1 Status.
mbed_official 146:f64d43ff0c18 1914 *
mbed_official 146:f64d43ff0c18 1915 * This function gets the Lock1 Status. This bit indicates whether PLL1 has
mbed_official 146:f64d43ff0c18 1916 * acquired the lock. PLL1 Lock detection is disabled when not operating in either
mbed_official 146:f64d43ff0c18 1917 * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the
mbed_official 146:f64d43ff0c18 1918 * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK,
mbed_official 146:f64d43ff0c18 1919 * MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets
mbed_official 146:f64d43ff0c18 1920 * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0]
mbed_official 146:f64d43ff0c18 1921 * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the
mbed_official 146:f64d43ff0c18 1922 * lock status bit to clear and stay cleared until the PLL1 has reacquired lock.
mbed_official 146:f64d43ff0c18 1923 * Loss of PLL1 reference clock will also causes the LOCK1 bit to clear until the PLL1
mbed_official 146:f64d43ff0c18 1924 * has reacquired lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also
mbed_official 146:f64d43ff0c18 1925 * causes the lock status bit to clear and stay cleared until the Stop mode is exited
mbed_official 146:f64d43ff0c18 1926 * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit
mbed_official 146:f64d43ff0c18 1927 * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off
mbed_official 146:f64d43ff0c18 1928 * until the LOCK1 bit is asserted again.
mbed_official 146:f64d43ff0c18 1929 *
mbed_official 146:f64d43ff0c18 1930 * @return status Lock1 Status
mbed_official 146:f64d43ff0c18 1931 * - 0: PLL1 is currently unlocked.
mbed_official 146:f64d43ff0c18 1932 * - 1: PLL1 is currently locked.
mbed_official 146:f64d43ff0c18 1933 */
mbed_official 146:f64d43ff0c18 1934 static inline mcg_lock_status_t clock_get_lock1(void)
mbed_official 146:f64d43ff0c18 1935 {
mbed_official 146:f64d43ff0c18 1936 return (mcg_lock_status_t)BR_MCG_S2_LOCK1;
mbed_official 146:f64d43ff0c18 1937 }
mbed_official 146:f64d43ff0c18 1938
mbed_official 146:f64d43ff0c18 1939 /*!
mbed_official 146:f64d43ff0c18 1940 * @brief Gets the PLL Clock Select Status.
mbed_official 146:f64d43ff0c18 1941 *
mbed_official 146:f64d43ff0c18 1942 * This function gets the PLL Clock Select Status. The PLLCST indicates the PLL
mbed_official 146:f64d43ff0c18 1943 * clock selected by PLLCS. The PLLCST bit is not updated immediately after a
mbed_official 146:f64d43ff0c18 1944 * write to the PLLCS bit due internal synchronization between clock domains.
mbed_official 146:f64d43ff0c18 1945 *
mbed_official 146:f64d43ff0c18 1946 * @return status PLL Clock Select Status
mbed_official 146:f64d43ff0c18 1947 * - 0: Source of PLLCS is PLL0 clock.
mbed_official 146:f64d43ff0c18 1948 * - 1: Source of PLLCS is PLL1 clock.
mbed_official 146:f64d43ff0c18 1949 */
mbed_official 146:f64d43ff0c18 1950 static inline mcg_pllcs_select_t clock_get_pllcst(void)
mbed_official 146:f64d43ff0c18 1951 {
mbed_official 146:f64d43ff0c18 1952 return (mcg_pllcs_select_t)BR_MCG_S2_PLLCST;
mbed_official 146:f64d43ff0c18 1953 }
mbed_official 146:f64d43ff0c18 1954
mbed_official 146:f64d43ff0c18 1955 /*!
mbed_official 146:f64d43ff0c18 1956 * @brief Gets the OSC1 Initialization Status.
mbed_official 146:f64d43ff0c18 1957 *
mbed_official 146:f64d43ff0c18 1958 * This function gets the OSC1 Initialization Status. This bit is set after the
mbed_official 146:f64d43ff0c18 1959 * initialization cycles of the 2nd crystal oscillator clock have completed. See
mbed_official 146:f64d43ff0c18 1960 * the Oscillator block guide for more details.
mbed_official 146:f64d43ff0c18 1961 *
mbed_official 146:f64d43ff0c18 1962 * @return status OSC1 Initialization Status
mbed_official 146:f64d43ff0c18 1963 */
mbed_official 146:f64d43ff0c18 1964 static inline uint8_t clock_get_oscinit1(void)
mbed_official 146:f64d43ff0c18 1965 {
mbed_official 146:f64d43ff0c18 1966 return BR_MCG_S2_OSCINIT1;
mbed_official 146:f64d43ff0c18 1967 }
mbed_official 146:f64d43ff0c18 1968
mbed_official 146:f64d43ff0c18 1969 /*!
mbed_official 146:f64d43ff0c18 1970 * @brief Gets the OSC1 Loss of Clock Status.
mbed_official 146:f64d43ff0c18 1971 *
mbed_official 146:f64d43ff0c18 1972 * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss
mbed_official 146:f64d43ff0c18 1973 * of the OSC1 external reference clock has occurred. LOCRE2 determines if a reset or
mbed_official 146:f64d43ff0c18 1974 * interrupt is generated when LOCS2 is set. This bit is cleared by writing a
mbed_official 146:f64d43ff0c18 1975 * logic 1 to it when set.
mbed_official 146:f64d43ff0c18 1976 *
mbed_official 146:f64d43ff0c18 1977 * @return status OSC1 Loss of Clock Status
mbed_official 146:f64d43ff0c18 1978 * - 0: No loss of OSC1 external reference clock has occurred.
mbed_official 146:f64d43ff0c18 1979 * - 1: Loss of OSC1 external reference clock has occurred.
mbed_official 146:f64d43ff0c18 1980 */
mbed_official 146:f64d43ff0c18 1981 static inline mcg_locs2_status_t clock_get_locs2(void)
mbed_official 146:f64d43ff0c18 1982 {
mbed_official 146:f64d43ff0c18 1983 return (mcg_locs2_status_t)BR_MCG_S2_LOCS2;
mbed_official 146:f64d43ff0c18 1984 }
mbed_official 146:f64d43ff0c18 1985 #endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
mbed_official 146:f64d43ff0c18 1986
mbed_official 146:f64d43ff0c18 1987 /*@}*/
mbed_official 146:f64d43ff0c18 1988
mbed_official 146:f64d43ff0c18 1989 #if defined(__cplusplus)
mbed_official 146:f64d43ff0c18 1990 }
mbed_official 146:f64d43ff0c18 1991 #endif /* __cplusplus*/
mbed_official 146:f64d43ff0c18 1992
mbed_official 146:f64d43ff0c18 1993 /*! @}*/
mbed_official 146:f64d43ff0c18 1994
mbed_official 146:f64d43ff0c18 1995 #endif /* __FSL_MCG_HAL_H__*/
mbed_official 146:f64d43ff0c18 1996 /*******************************************************************************
mbed_official 146:f64d43ff0c18 1997 * EOF
mbed_official 146:f64d43ff0c18 1998 ******************************************************************************/
mbed_official 146:f64d43ff0c18 1999