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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.c@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/mcg/fsl_mcg_hal.c@146:f64d43ff0c18
Child:
324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30
mbed_official 146:f64d43ff0c18 31 #include "fsl_mcg_hal.h"
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 /*******************************************************************************
mbed_official 146:f64d43ff0c18 34 * Definitions
mbed_official 146:f64d43ff0c18 35 ******************************************************************************/
mbed_official 146:f64d43ff0c18 36
mbed_official 146:f64d43ff0c18 37
mbed_official 146:f64d43ff0c18 38 /*******************************************************************************
mbed_official 146:f64d43ff0c18 39 * Code
mbed_official 146:f64d43ff0c18 40 ******************************************************************************/
mbed_official 146:f64d43ff0c18 41
mbed_official 146:f64d43ff0c18 42 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 43 *
mbed_official 146:f64d43ff0c18 44 * Function Name : get_mcgffclk
mbed_official 146:f64d43ff0c18 45 * Description : Internal function to find the fll reference clock
mbed_official 146:f64d43ff0c18 46 * This is an internal function to get the fll reference clock. The returned
mbed_official 146:f64d43ff0c18 47 * value will be used for other APIs to calculate teh fll and other clock value.
mbed_official 146:f64d43ff0c18 48 *
mbed_official 146:f64d43ff0c18 49 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 50 uint32_t get_mcgffclk(void)
mbed_official 146:f64d43ff0c18 51 {
mbed_official 146:f64d43ff0c18 52 uint32_t mcgffclk;
mbed_official 146:f64d43ff0c18 53 uint8_t divider;
mbed_official 146:f64d43ff0c18 54
mbed_official 146:f64d43ff0c18 55 if (clock_get_irefs() == kMcgIrefClockSourceExt)
mbed_official 146:f64d43ff0c18 56 {
mbed_official 146:f64d43ff0c18 57 /* External reference clock is selected */
mbed_official 146:f64d43ff0c18 58 #if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for ffclk */
mbed_official 146:f64d43ff0c18 59
mbed_official 146:f64d43ff0c18 60 int32_t oscsel = clock_get_oscsel();
mbed_official 146:f64d43ff0c18 61 if (oscsel == kMcgOscselOsc)
mbed_official 146:f64d43ff0c18 62 {
mbed_official 146:f64d43ff0c18 63 #if FSL_FEATURE_MCG_HAS_OSC1
mbed_official 146:f64d43ff0c18 64 /* System oscillator 0 drives MCG clock */
mbed_official 146:f64d43ff0c18 65 mcgffclk = CPU_XTAL0_CLK_HZ;
mbed_official 146:f64d43ff0c18 66 #else
mbed_official 146:f64d43ff0c18 67 /* System oscillator 0 drives MCG clock */
mbed_official 146:f64d43ff0c18 68 mcgffclk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 69 #endif
mbed_official 146:f64d43ff0c18 70 }
mbed_official 146:f64d43ff0c18 71 else if (oscsel == kMcgOscselRtc)
mbed_official 146:f64d43ff0c18 72 {
mbed_official 146:f64d43ff0c18 73 /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 146:f64d43ff0c18 74 mcgffclk = CPU_XTAL32k_CLK_HZ;
mbed_official 146:f64d43ff0c18 75 }
mbed_official 146:f64d43ff0c18 76 #if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: if IRC 48M exists*/
mbed_official 146:f64d43ff0c18 77 else if (oscsel == kMcgOscselIrc)
mbed_official 146:f64d43ff0c18 78 {
mbed_official 146:f64d43ff0c18 79 /* IRC 48Mhz oscillator drives MCG clock */
mbed_official 146:f64d43ff0c18 80 mcgffclk = CPU_INT_IRC_CLK_HZ;
mbed_official 146:f64d43ff0c18 81 }
mbed_official 146:f64d43ff0c18 82 #endif
mbed_official 146:f64d43ff0c18 83 else
mbed_official 146:f64d43ff0c18 84 {
mbed_official 146:f64d43ff0c18 85 mcgffclk = 0;
mbed_official 146:f64d43ff0c18 86 }
mbed_official 146:f64d43ff0c18 87
mbed_official 146:f64d43ff0c18 88 #else /* case 2: use default osc0*/
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 /* System oscillator 0 drives MCG clock */
mbed_official 146:f64d43ff0c18 91 mcgffclk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 92
mbed_official 146:f64d43ff0c18 93 #endif
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 divider = (uint8_t)(1u << clock_get_frdiv());
mbed_official 146:f64d43ff0c18 96
mbed_official 146:f64d43ff0c18 97 /* Calculate the divided FLL reference clock*/
mbed_official 146:f64d43ff0c18 98 mcgffclk = (mcgffclk / divider);
mbed_official 146:f64d43ff0c18 99
mbed_official 146:f64d43ff0c18 100 if (clock_get_range0() != kMcgFreqRangeSelectLow)
mbed_official 146:f64d43ff0c18 101 {
mbed_official 146:f64d43ff0c18 102 /* If high range is enabled, additional 32 divider is active*/
mbed_official 146:f64d43ff0c18 103 mcgffclk = (mcgffclk >> kMcgConstant5);
mbed_official 146:f64d43ff0c18 104 }
mbed_official 146:f64d43ff0c18 105 }
mbed_official 146:f64d43ff0c18 106 else
mbed_official 146:f64d43ff0c18 107 {
mbed_official 146:f64d43ff0c18 108 /* The slow internal reference clock is selected */
mbed_official 146:f64d43ff0c18 109 mcgffclk = CPU_INT_SLOW_CLK_HZ;
mbed_official 146:f64d43ff0c18 110 }
mbed_official 146:f64d43ff0c18 111 return mcgffclk;
mbed_official 146:f64d43ff0c18 112 }
mbed_official 146:f64d43ff0c18 113
mbed_official 146:f64d43ff0c18 114 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 115 *
mbed_official 146:f64d43ff0c18 116 * Function Name : clock_hal_get_fllclk
mbed_official 146:f64d43ff0c18 117 * Description : Get the current mcg fll clock
mbed_official 146:f64d43ff0c18 118 * This function will return the mcgfllclk value in frequency(hz) based on
mbed_official 146:f64d43ff0c18 119 * current mcg configurations and settings. Fll should be properly configured
mbed_official 146:f64d43ff0c18 120 * in order to get the valid value.
mbed_official 146:f64d43ff0c18 121 *
mbed_official 146:f64d43ff0c18 122 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 123 uint32_t clock_hal_get_fllclk(void)
mbed_official 146:f64d43ff0c18 124 {
mbed_official 146:f64d43ff0c18 125 uint32_t mcgfllclk;
mbed_official 146:f64d43ff0c18 126 mcg_dmx32_select_t dmx32;
mbed_official 146:f64d43ff0c18 127 mcg_dco_range_select_t drstDrs;
mbed_official 146:f64d43ff0c18 128
mbed_official 146:f64d43ff0c18 129 mcgfllclk = get_mcgffclk();
mbed_official 146:f64d43ff0c18 130
mbed_official 146:f64d43ff0c18 131 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 146:f64d43ff0c18 132 dmx32 = clock_get_dmx32();
mbed_official 146:f64d43ff0c18 133 drstDrs = clock_get_drst_drs();
mbed_official 146:f64d43ff0c18 134
mbed_official 146:f64d43ff0c18 135 switch (drstDrs)
mbed_official 146:f64d43ff0c18 136 {
mbed_official 146:f64d43ff0c18 137 case kMcgDcoRangeSelectLow: /* Low frequency range */
mbed_official 146:f64d43ff0c18 138 switch (dmx32)
mbed_official 146:f64d43ff0c18 139 {
mbed_official 146:f64d43ff0c18 140 case kMcgDmx32Default: /* DCO has a default range of 25% */
mbed_official 146:f64d43ff0c18 141 mcgfllclk *= kMcgConstant640;
mbed_official 146:f64d43ff0c18 142 break;
mbed_official 146:f64d43ff0c18 143 case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
mbed_official 146:f64d43ff0c18 144 mcgfllclk *= kMcgConstant732;
mbed_official 146:f64d43ff0c18 145 break;
mbed_official 146:f64d43ff0c18 146 default:
mbed_official 146:f64d43ff0c18 147 break;
mbed_official 146:f64d43ff0c18 148 }
mbed_official 146:f64d43ff0c18 149 break;
mbed_official 146:f64d43ff0c18 150 case kMcgDcoRangeSelectMid: /* Mid frequency range*/
mbed_official 146:f64d43ff0c18 151 switch (dmx32)
mbed_official 146:f64d43ff0c18 152 {
mbed_official 146:f64d43ff0c18 153 case kMcgDmx32Default: /* DCO has a default range of 25% */
mbed_official 146:f64d43ff0c18 154 mcgfllclk *= kMcgConstant1280;
mbed_official 146:f64d43ff0c18 155 break;
mbed_official 146:f64d43ff0c18 156 case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
mbed_official 146:f64d43ff0c18 157 mcgfllclk *= kMcgConstant1464;
mbed_official 146:f64d43ff0c18 158 break;
mbed_official 146:f64d43ff0c18 159 default:
mbed_official 146:f64d43ff0c18 160 break;
mbed_official 146:f64d43ff0c18 161 }
mbed_official 146:f64d43ff0c18 162 break;
mbed_official 146:f64d43ff0c18 163 case kMcgDcoRangeSelectMidHigh: /* Mid-High frequency range */
mbed_official 146:f64d43ff0c18 164 switch (dmx32)
mbed_official 146:f64d43ff0c18 165 {
mbed_official 146:f64d43ff0c18 166 case kMcgDmx32Default: /* DCO has a default range of 25% */
mbed_official 146:f64d43ff0c18 167 mcgfllclk *= kMcgConstant1920;
mbed_official 146:f64d43ff0c18 168 break;
mbed_official 146:f64d43ff0c18 169 case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
mbed_official 146:f64d43ff0c18 170 mcgfllclk *= kMcgConstant2197;
mbed_official 146:f64d43ff0c18 171 break;
mbed_official 146:f64d43ff0c18 172 default:
mbed_official 146:f64d43ff0c18 173 break;
mbed_official 146:f64d43ff0c18 174 }
mbed_official 146:f64d43ff0c18 175 break;
mbed_official 146:f64d43ff0c18 176 case kMcgDcoRangeSelectHigh: /* High frequency range */
mbed_official 146:f64d43ff0c18 177 switch (dmx32)
mbed_official 146:f64d43ff0c18 178 {
mbed_official 146:f64d43ff0c18 179 case kMcgDmx32Default: /* DCO has a default range of 25% */
mbed_official 146:f64d43ff0c18 180 mcgfllclk *= kMcgConstant2560;
mbed_official 146:f64d43ff0c18 181 break;
mbed_official 146:f64d43ff0c18 182 case kMcgDmx32Fine: /* DCO is fine-tuned for max freq 32.768 kHz */
mbed_official 146:f64d43ff0c18 183 mcgfllclk *= kMcgConstant2929;
mbed_official 146:f64d43ff0c18 184 break;
mbed_official 146:f64d43ff0c18 185 default:
mbed_official 146:f64d43ff0c18 186 break;
mbed_official 146:f64d43ff0c18 187 }
mbed_official 146:f64d43ff0c18 188 break;
mbed_official 146:f64d43ff0c18 189 default:
mbed_official 146:f64d43ff0c18 190 break;
mbed_official 146:f64d43ff0c18 191 }
mbed_official 146:f64d43ff0c18 192
mbed_official 146:f64d43ff0c18 193 return mcgfllclk;
mbed_official 146:f64d43ff0c18 194 }
mbed_official 146:f64d43ff0c18 195
mbed_official 146:f64d43ff0c18 196 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 197 *
mbed_official 146:f64d43ff0c18 198 * Function Name : clock_hal_get_pll0clk
mbed_official 146:f64d43ff0c18 199 * Description : Get the current mcg pll/pll0 clock
mbed_official 146:f64d43ff0c18 200 * This function will return the mcgpllclk/mcgpll0 value in frequency(hz) based
mbed_official 146:f64d43ff0c18 201 * on current mcg configurations and settings. PLL/PLL0 should be properly
mbed_official 146:f64d43ff0c18 202 * configured in order to get the valid value.
mbed_official 146:f64d43ff0c18 203 *
mbed_official 146:f64d43ff0c18 204 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 205 uint32_t clock_hal_get_pll0clk(void)
mbed_official 146:f64d43ff0c18 206 {
mbed_official 146:f64d43ff0c18 207 uint32_t mcgpll0clk;
mbed_official 146:f64d43ff0c18 208 uint8_t divider;
mbed_official 146:f64d43ff0c18 209
mbed_official 146:f64d43ff0c18 210 /* PLL(0) output is selected*/
mbed_official 146:f64d43ff0c18 211 #if FSL_FEATURE_MCG_USE_PLLREFSEL /* case 1 use pllrefsel to select pll*/
mbed_official 146:f64d43ff0c18 212
mbed_official 146:f64d43ff0c18 213 if (clock_get_pllrefsel0() != kMcgPllErefClockSelectOsc0)
mbed_official 146:f64d43ff0c18 214 {
mbed_official 146:f64d43ff0c18 215 /* OSC1 clock source used as an external reference clock */
mbed_official 146:f64d43ff0c18 216 mcgpll0clk = CPU_XTAL1_CLK_HZ;
mbed_official 146:f64d43ff0c18 217 }
mbed_official 146:f64d43ff0c18 218 else
mbed_official 146:f64d43ff0c18 219 {
mbed_official 146:f64d43ff0c18 220 /* OSC0 clock source used as an external reference clock*/
mbed_official 146:f64d43ff0c18 221 mcgpll0clk = CPU_XTAL0_CLK_HZ;
mbed_official 146:f64d43ff0c18 222 }
mbed_official 146:f64d43ff0c18 223 #else
mbed_official 146:f64d43ff0c18 224 #if FSL_FEATURE_MCG_USE_OSCSEL /* case 2: use oscsel for pll */
mbed_official 146:f64d43ff0c18 225 uint32_t oscsel = clock_get_oscsel();
mbed_official 146:f64d43ff0c18 226 if (oscsel == kMcgOscselOsc) /* case 2.1: OSC0 */
mbed_official 146:f64d43ff0c18 227 {
mbed_official 146:f64d43ff0c18 228 /* System oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 229 mcgpll0clk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 230 }
mbed_official 146:f64d43ff0c18 231 else if (oscsel == kMcgOscselRtc) /* case 2.2: RTC */
mbed_official 146:f64d43ff0c18 232 {
mbed_official 146:f64d43ff0c18 233 /* RTC 32 kHz oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 234 mcgpll0clk = CPU_XTAL32k_CLK_HZ;
mbed_official 146:f64d43ff0c18 235 }
mbed_official 146:f64d43ff0c18 236 #if FSL_FEATURE_MCG_HAS_IRC_48M
mbed_official 146:f64d43ff0c18 237 else if (oscsel == kMcgOscselIrc) /* case 2.3: IRC 48M */
mbed_official 146:f64d43ff0c18 238 {
mbed_official 146:f64d43ff0c18 239 /* IRC 48Mhz oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 240 mcgpll0clk = CPU_INT_IRC_CLK_HZ;
mbed_official 146:f64d43ff0c18 241 }
mbed_official 146:f64d43ff0c18 242 else
mbed_official 146:f64d43ff0c18 243 {
mbed_official 146:f64d43ff0c18 244 mcgpll0clk = 0;
mbed_official 146:f64d43ff0c18 245 }
mbed_official 146:f64d43ff0c18 246 #endif
mbed_official 146:f64d43ff0c18 247 #else /* case 3: use default osc0*/
mbed_official 146:f64d43ff0c18 248 /* System oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 249 mcgpll0clk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 250 #endif
mbed_official 146:f64d43ff0c18 251 #endif
mbed_official 146:f64d43ff0c18 252
mbed_official 146:f64d43ff0c18 253 divider = (kMcgConstant1 + clock_get_prdiv0());
mbed_official 146:f64d43ff0c18 254
mbed_official 146:f64d43ff0c18 255 /* Calculate the PLL reference clock*/
mbed_official 146:f64d43ff0c18 256 mcgpll0clk /= divider;
mbed_official 146:f64d43ff0c18 257 divider = (clock_get_vdiv0() + FSL_FEATURE_MCG_PLL_VDIV_BASE);
mbed_official 146:f64d43ff0c18 258
mbed_official 146:f64d43ff0c18 259 /* Calculate the MCG output clock*/
mbed_official 146:f64d43ff0c18 260 mcgpll0clk = (mcgpll0clk * divider);
mbed_official 146:f64d43ff0c18 261
mbed_official 146:f64d43ff0c18 262 #if FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV
mbed_official 146:f64d43ff0c18 263 mcgpll0clk = (mcgpll0clk >> kMcgConstant1); /* divided by 2*/
mbed_official 146:f64d43ff0c18 264 #endif
mbed_official 146:f64d43ff0c18 265
mbed_official 146:f64d43ff0c18 266 return mcgpll0clk;
mbed_official 146:f64d43ff0c18 267 }
mbed_official 146:f64d43ff0c18 268
mbed_official 146:f64d43ff0c18 269 #if FSL_FEATURE_MCG_HAS_PLL1
mbed_official 146:f64d43ff0c18 270 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 271 *
mbed_official 146:f64d43ff0c18 272 * Function Name : clock_hal_get_pll1clk
mbed_official 146:f64d43ff0c18 273 * Description : Get the current mcg pll1 clock
mbed_official 146:f64d43ff0c18 274 * This function will return the mcgpll1clk value in frequency(hz) based
mbed_official 146:f64d43ff0c18 275 * on current mcg configurations and settings. PLL1 should be properly configured
mbed_official 146:f64d43ff0c18 276 * in order to get the valid value.
mbed_official 146:f64d43ff0c18 277 *
mbed_official 146:f64d43ff0c18 278 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 279 uint32_t clock_hal_get_pll1clk(void)
mbed_official 146:f64d43ff0c18 280 {
mbed_official 146:f64d43ff0c18 281 uint32_t mcgpll1clk;
mbed_official 146:f64d43ff0c18 282 uint8_t divider;
mbed_official 146:f64d43ff0c18 283
mbed_official 146:f64d43ff0c18 284 if (clock_get_pllrefsel1() != kMcgPllErefClockSelectOsc0)
mbed_official 146:f64d43ff0c18 285 {
mbed_official 146:f64d43ff0c18 286 /* OSC1 clock source used as an external reference clock*/
mbed_official 146:f64d43ff0c18 287 mcgpll1clk = CPU_XTAL1_CLK_HZ;
mbed_official 146:f64d43ff0c18 288 }
mbed_official 146:f64d43ff0c18 289 else
mbed_official 146:f64d43ff0c18 290 {
mbed_official 146:f64d43ff0c18 291 /* OSC0 clock source used as an external reference clock*/
mbed_official 146:f64d43ff0c18 292 mcgpll1clk = CPU_XTAL0_CLK_HZ;
mbed_official 146:f64d43ff0c18 293 }
mbed_official 146:f64d43ff0c18 294
mbed_official 146:f64d43ff0c18 295 divider = (kMcgConstant1 + clock_get_prdiv1());
mbed_official 146:f64d43ff0c18 296
mbed_official 146:f64d43ff0c18 297 /* Calculate the PLL reference clock*/
mbed_official 146:f64d43ff0c18 298 mcgpll1clk /= divider;
mbed_official 146:f64d43ff0c18 299 divider = (clock_get_vdiv1() + FSL_FEATURE_MCG_PLL_VDIV_BASE);
mbed_official 146:f64d43ff0c18 300
mbed_official 146:f64d43ff0c18 301 /* Calculate the MCG output clock*/
mbed_official 146:f64d43ff0c18 302 mcgpll1clk = ((mcgpll1clk * divider) >> kMcgConstant1); /* divided by 2*/
mbed_official 146:f64d43ff0c18 303 return mcgpll1clk;
mbed_official 146:f64d43ff0c18 304 }
mbed_official 146:f64d43ff0c18 305 #endif
mbed_official 146:f64d43ff0c18 306
mbed_official 146:f64d43ff0c18 307 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 308 *
mbed_official 146:f64d43ff0c18 309 * Function Name : clock_hal_get_irclk
mbed_official 146:f64d43ff0c18 310 * Description : Get the current mcg ir clock
mbed_official 146:f64d43ff0c18 311 * This function will return the mcgirclk value in frequency(hz) based
mbed_official 146:f64d43ff0c18 312 * on current mcg configurations and settings. It will not check if the
mbed_official 146:f64d43ff0c18 313 * mcgirclk is enabled or not, just calculate and return the value.
mbed_official 146:f64d43ff0c18 314 *
mbed_official 146:f64d43ff0c18 315 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 316 uint32_t clock_hal_get_irclk(void)
mbed_official 146:f64d43ff0c18 317 {
mbed_official 146:f64d43ff0c18 318 int32_t mcgirclk;
mbed_official 146:f64d43ff0c18 319 if (clock_get_ircs() == kMcgIrefClockSelectSlow)
mbed_official 146:f64d43ff0c18 320 {
mbed_official 146:f64d43ff0c18 321 /* Slow internal reference clock selected*/
mbed_official 146:f64d43ff0c18 322 mcgirclk = CPU_INT_SLOW_CLK_HZ;
mbed_official 146:f64d43ff0c18 323 }
mbed_official 146:f64d43ff0c18 324 else
mbed_official 146:f64d43ff0c18 325 {
mbed_official 146:f64d43ff0c18 326 mcgirclk = CPU_INT_FAST_CLK_HZ / (1 << clock_get_fcrdiv());
mbed_official 146:f64d43ff0c18 327 }
mbed_official 146:f64d43ff0c18 328 return mcgirclk;
mbed_official 146:f64d43ff0c18 329 }
mbed_official 146:f64d43ff0c18 330
mbed_official 146:f64d43ff0c18 331 /*FUNCTION**********************************************************************
mbed_official 146:f64d43ff0c18 332 *
mbed_official 146:f64d43ff0c18 333 * Function Name : clock_hal_get_outclk
mbed_official 146:f64d43ff0c18 334 * Description : Get the current mcg out clock
mbed_official 146:f64d43ff0c18 335 * This function will return the mcgoutclk value in frequency(hz) based on
mbed_official 146:f64d43ff0c18 336 * current mcg configurations and settings. The configuration should be
mbed_official 146:f64d43ff0c18 337 * properly done in order to get the valid value.
mbed_official 146:f64d43ff0c18 338 *
mbed_official 146:f64d43ff0c18 339 *END**************************************************************************/
mbed_official 146:f64d43ff0c18 340 uint32_t clock_hal_get_outclk(void)
mbed_official 146:f64d43ff0c18 341 {
mbed_official 146:f64d43ff0c18 342 /* Variable to store output clock frequency of the MCG module*/
mbed_official 146:f64d43ff0c18 343 uint32_t mcgoutclk = 0;
mbed_official 146:f64d43ff0c18 344
mbed_official 146:f64d43ff0c18 345 if (clock_get_clks() == kMcgClockSelectOut)
mbed_official 146:f64d43ff0c18 346 {
mbed_official 146:f64d43ff0c18 347 /* Output of FLL or PLL is selected*/
mbed_official 146:f64d43ff0c18 348 if (clock_get_plls() == kMcgPllSelectFll)
mbed_official 146:f64d43ff0c18 349 {
mbed_official 146:f64d43ff0c18 350 /* FLL is selected*/
mbed_official 146:f64d43ff0c18 351 mcgoutclk = clock_hal_get_fllclk();
mbed_official 146:f64d43ff0c18 352 }
mbed_official 146:f64d43ff0c18 353 else
mbed_official 146:f64d43ff0c18 354 {
mbed_official 146:f64d43ff0c18 355 /* PLL is selected*/
mbed_official 146:f64d43ff0c18 356 #if FSL_FEATURE_MCG_HAS_PLL1
mbed_official 146:f64d43ff0c18 357 if (clock_get_pllcs() != kMcgPllcsSelectPll0)
mbed_official 146:f64d43ff0c18 358 {
mbed_official 146:f64d43ff0c18 359 /* PLL1 output is selected*/
mbed_official 146:f64d43ff0c18 360 mcgoutclk = clock_hal_get_pll1clk();
mbed_official 146:f64d43ff0c18 361 }
mbed_official 146:f64d43ff0c18 362 else
mbed_official 146:f64d43ff0c18 363 {
mbed_official 146:f64d43ff0c18 364 mcgoutclk = clock_hal_get_pll0clk();
mbed_official 146:f64d43ff0c18 365 }
mbed_official 146:f64d43ff0c18 366 #else
mbed_official 146:f64d43ff0c18 367 mcgoutclk = clock_hal_get_pll0clk();
mbed_official 146:f64d43ff0c18 368 #endif
mbed_official 146:f64d43ff0c18 369 }
mbed_official 146:f64d43ff0c18 370 }
mbed_official 146:f64d43ff0c18 371 else if (clock_get_clks() == kMcgClockSelectIn)
mbed_official 146:f64d43ff0c18 372 {
mbed_official 146:f64d43ff0c18 373 /* Internal reference clock is selected*/
mbed_official 146:f64d43ff0c18 374 mcgoutclk = clock_hal_get_irclk();
mbed_official 146:f64d43ff0c18 375 }
mbed_official 146:f64d43ff0c18 376 else if (clock_get_clks() == kMcgClockSelectExt)
mbed_official 146:f64d43ff0c18 377 {
mbed_official 146:f64d43ff0c18 378 /* External reference clock is selected*/
mbed_official 146:f64d43ff0c18 379
mbed_official 146:f64d43ff0c18 380 #if FSL_FEATURE_MCG_USE_OSCSEL /* case 1: use oscsel for outclock */
mbed_official 146:f64d43ff0c18 381
mbed_official 146:f64d43ff0c18 382 uint32_t oscsel = clock_get_oscsel();
mbed_official 146:f64d43ff0c18 383 if (oscsel == kMcgOscselOsc)
mbed_official 146:f64d43ff0c18 384 {
mbed_official 146:f64d43ff0c18 385 #if FSL_FEATURE_MCG_HAS_OSC1
mbed_official 146:f64d43ff0c18 386 /* System oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 387 mcgoutclk = CPU_XTAL0_CLK_HZ;
mbed_official 146:f64d43ff0c18 388 #else
mbed_official 146:f64d43ff0c18 389 /* System oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 390 mcgoutclk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 391 #endif
mbed_official 146:f64d43ff0c18 392 }
mbed_official 146:f64d43ff0c18 393 else if (oscsel == kMcgOscselRtc)
mbed_official 146:f64d43ff0c18 394 {
mbed_official 146:f64d43ff0c18 395 /* RTC 32 kHz oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 396 mcgoutclk = CPU_XTAL32k_CLK_HZ;
mbed_official 146:f64d43ff0c18 397 }
mbed_official 146:f64d43ff0c18 398 #if FSL_FEATURE_MCG_HAS_IRC_48M /* case 1.1: IRC 48M exists*/
mbed_official 146:f64d43ff0c18 399 else if (oscsel == kMcgOscselIrc)
mbed_official 146:f64d43ff0c18 400 {
mbed_official 146:f64d43ff0c18 401 /* IRC 48Mhz oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 402 mcgoutclk = CPU_INT_IRC_CLK_HZ;
mbed_official 146:f64d43ff0c18 403 }
mbed_official 146:f64d43ff0c18 404 else
mbed_official 146:f64d43ff0c18 405 {
mbed_official 146:f64d43ff0c18 406 mcgoutclk = 0;
mbed_official 146:f64d43ff0c18 407 }
mbed_official 146:f64d43ff0c18 408 #endif
mbed_official 146:f64d43ff0c18 409
mbed_official 146:f64d43ff0c18 410 #else /* case 2: use default osc0*/
mbed_official 146:f64d43ff0c18 411 /* System oscillator drives MCG clock*/
mbed_official 146:f64d43ff0c18 412 mcgoutclk = CPU_XTAL_CLK_HZ;
mbed_official 146:f64d43ff0c18 413 #endif
mbed_official 146:f64d43ff0c18 414 }
mbed_official 146:f64d43ff0c18 415 else
mbed_official 146:f64d43ff0c18 416 {
mbed_official 146:f64d43ff0c18 417 /* Reserved value*/
mbed_official 146:f64d43ff0c18 418 return mcgoutclk;
mbed_official 146:f64d43ff0c18 419 }
mbed_official 146:f64d43ff0c18 420 return mcgoutclk;
mbed_official 146:f64d43ff0c18 421 }
mbed_official 146:f64d43ff0c18 422
mbed_official 146:f64d43ff0c18 423 /*******************************************************************************
mbed_official 146:f64d43ff0c18 424 * EOF
mbed_official 146:f64d43ff0c18 425 ******************************************************************************/
mbed_official 146:f64d43ff0c18 426