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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)

Committer:
mbed_official
Date:
Thu Apr 03 11:45:06 2014 +0100
Revision:
149:1fb5f62b92bd
Parent:
targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/i2c/fsl_i2c_features.h@146:f64d43ff0c18
Child:
324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42



Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
mbed_official 146:f64d43ff0c18 3 * All rights reserved.
mbed_official 146:f64d43ff0c18 4 *
mbed_official 146:f64d43ff0c18 5 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 146:f64d43ff0c18 6 * are permitted provided that the following conditions are met:
mbed_official 146:f64d43ff0c18 7 *
mbed_official 146:f64d43ff0c18 8 * o Redistributions of source code must retain the above copyright notice, this list
mbed_official 146:f64d43ff0c18 9 * of conditions and the following disclaimer.
mbed_official 146:f64d43ff0c18 10 *
mbed_official 146:f64d43ff0c18 11 * o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 146:f64d43ff0c18 12 * list of conditions and the following disclaimer in the documentation and/or
mbed_official 146:f64d43ff0c18 13 * other materials provided with the distribution.
mbed_official 146:f64d43ff0c18 14 *
mbed_official 146:f64d43ff0c18 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 146:f64d43ff0c18 16 * contributors may be used to endorse or promote products derived from this
mbed_official 146:f64d43ff0c18 17 * software without specific prior written permission.
mbed_official 146:f64d43ff0c18 18 *
mbed_official 146:f64d43ff0c18 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 146:f64d43ff0c18 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 146:f64d43ff0c18 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 146:f64d43ff0c18 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 146:f64d43ff0c18 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 146:f64d43ff0c18 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 146:f64d43ff0c18 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 146:f64d43ff0c18 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 146:f64d43ff0c18 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 146:f64d43ff0c18 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 29 */
mbed_official 146:f64d43ff0c18 30 #if !defined(__FSL_I2C_FEATURES_H__)
mbed_official 146:f64d43ff0c18 31 #define __FSL_I2C_FEATURES_H__
mbed_official 146:f64d43ff0c18 32
mbed_official 146:f64d43ff0c18 33 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
mbed_official 146:f64d43ff0c18 34 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
mbed_official 146:f64d43ff0c18 35 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
mbed_official 146:f64d43ff0c18 36 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
mbed_official 146:f64d43ff0c18 37 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
mbed_official 146:f64d43ff0c18 38 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
mbed_official 146:f64d43ff0c18 39 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
mbed_official 146:f64d43ff0c18 40 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || \
mbed_official 146:f64d43ff0c18 41 defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || \
mbed_official 146:f64d43ff0c18 42 defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 146:f64d43ff0c18 43 /* @brief Has I2C bus stop detection (register bit FLT[STOPF]).*/
mbed_official 146:f64d43ff0c18 44 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
mbed_official 146:f64d43ff0c18 45 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH).*/
mbed_official 146:f64d43ff0c18 46 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
mbed_official 146:f64d43ff0c18 47 /* @brief Maximum supported baud rate in kilobit per second.*/
mbed_official 146:f64d43ff0c18 48 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
mbed_official 146:f64d43ff0c18 49 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value).*/
mbed_official 146:f64d43ff0c18 50 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
mbed_official 146:f64d43ff0c18 51 /* @brief Has DMA support (register bit C1[DMAEN]).*/
mbed_official 146:f64d43ff0c18 52 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 53 /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]).*/
mbed_official 146:f64d43ff0c18 54 #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
mbed_official 146:f64d43ff0c18 55 /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]).*/
mbed_official 146:f64d43ff0c18 56 #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
mbed_official 146:f64d43ff0c18 57 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]).*/
mbed_official 146:f64d43ff0c18 58 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (0)
mbed_official 146:f64d43ff0c18 59 /* @brief Maximum width of the glitch filter in number of bus clocks.*/
mbed_official 146:f64d43ff0c18 60 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
mbed_official 146:f64d43ff0c18 61 /* @brief Has control of the drive capability of the I2C pins.*/
mbed_official 146:f64d43ff0c18 62 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
mbed_official 146:f64d43ff0c18 63 #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
mbed_official 146:f64d43ff0c18 64 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MK24FN1M0VDC12) || \
mbed_official 146:f64d43ff0c18 65 defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FN1M0VDC12) || \
mbed_official 146:f64d43ff0c18 66 defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VMD12) || \
mbed_official 146:f64d43ff0c18 67 defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || \
mbed_official 146:f64d43ff0c18 68 defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || \
mbed_official 146:f64d43ff0c18 69 defined(CPU_MK66FX1M0VMD18) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || \
mbed_official 146:f64d43ff0c18 70 defined(CPU_MKV31F512VLL12)
mbed_official 146:f64d43ff0c18 71 /* @brief Has I2C bus stop detection (register bit FLT[STOPF]).*/
mbed_official 146:f64d43ff0c18 72 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
mbed_official 146:f64d43ff0c18 73 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH).*/
mbed_official 146:f64d43ff0c18 74 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
mbed_official 146:f64d43ff0c18 75 /* @brief Maximum supported baud rate in kilobit per second.*/
mbed_official 146:f64d43ff0c18 76 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
mbed_official 146:f64d43ff0c18 77 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value).*/
mbed_official 146:f64d43ff0c18 78 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
mbed_official 146:f64d43ff0c18 79 /* @brief Has DMA support (register bit C1[DMAEN]).*/
mbed_official 146:f64d43ff0c18 80 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 81 /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]).*/
mbed_official 146:f64d43ff0c18 82 #define FSL_FEATURE_I2C_HAS_START_DETECT (1)
mbed_official 146:f64d43ff0c18 83 /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]).*/
mbed_official 146:f64d43ff0c18 84 #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (0)
mbed_official 146:f64d43ff0c18 85 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]).*/
mbed_official 146:f64d43ff0c18 86 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
mbed_official 146:f64d43ff0c18 87 /* @brief Maximum width of the glitch filter in number of bus clocks.*/
mbed_official 146:f64d43ff0c18 88 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
mbed_official 146:f64d43ff0c18 89 /* @brief Has control of the drive capability of the I2C pins.*/
mbed_official 146:f64d43ff0c18 90 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
mbed_official 146:f64d43ff0c18 91 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
mbed_official 146:f64d43ff0c18 92 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
mbed_official 146:f64d43ff0c18 93 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
mbed_official 146:f64d43ff0c18 94 defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
mbed_official 146:f64d43ff0c18 95 defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
mbed_official 146:f64d43ff0c18 96 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4)
mbed_official 146:f64d43ff0c18 97 /* @brief Has I2C bus stop detection (register bit FLT[STOPF]).*/
mbed_official 146:f64d43ff0c18 98 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
mbed_official 146:f64d43ff0c18 99 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH).*/
mbed_official 146:f64d43ff0c18 100 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
mbed_official 146:f64d43ff0c18 101 /* @brief Maximum supported baud rate in kilobit per second.*/
mbed_official 146:f64d43ff0c18 102 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
mbed_official 146:f64d43ff0c18 103 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value).*/
mbed_official 146:f64d43ff0c18 104 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
mbed_official 146:f64d43ff0c18 105 /* @brief Has DMA support (register bit C1[DMAEN]).*/
mbed_official 146:f64d43ff0c18 106 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 107 /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]).*/
mbed_official 146:f64d43ff0c18 108 #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
mbed_official 146:f64d43ff0c18 109 /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]).*/
mbed_official 146:f64d43ff0c18 110 #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1)
mbed_official 146:f64d43ff0c18 111 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]).*/
mbed_official 146:f64d43ff0c18 112 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
mbed_official 146:f64d43ff0c18 113 /* @brief Maximum width of the glitch filter in number of bus clocks.*/
mbed_official 146:f64d43ff0c18 114 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
mbed_official 146:f64d43ff0c18 115 /* @brief Has control of the drive capability of the I2C pins.*/
mbed_official 146:f64d43ff0c18 116 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
mbed_official 146:f64d43ff0c18 117 #elif defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \
mbed_official 146:f64d43ff0c18 118 defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
mbed_official 146:f64d43ff0c18 119 /* @brief Has I2C bus stop detection (register bit FLT[STOPF]).*/
mbed_official 146:f64d43ff0c18 120 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (1)
mbed_official 146:f64d43ff0c18 121 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH).*/
mbed_official 146:f64d43ff0c18 122 #define FSL_FEATURE_I2C_HAS_SMBUS (1)
mbed_official 146:f64d43ff0c18 123 /* @brief Maximum supported baud rate in kilobit per second.*/
mbed_official 146:f64d43ff0c18 124 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (100)
mbed_official 146:f64d43ff0c18 125 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value).*/
mbed_official 146:f64d43ff0c18 126 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (1)
mbed_official 146:f64d43ff0c18 127 /* @brief Has DMA support (register bit C1[DMAEN]).*/
mbed_official 146:f64d43ff0c18 128 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
mbed_official 146:f64d43ff0c18 129 /* @brief Has I2C bus start detection (register bits FLT[STARTF] and FLT[SSIE]).*/
mbed_official 146:f64d43ff0c18 130 #define FSL_FEATURE_I2C_HAS_START_DETECT (0)
mbed_official 146:f64d43ff0c18 131 /* @brief Has I2C bus stop detection interrupt (register bit FLT[STOPIE]).*/
mbed_official 146:f64d43ff0c18 132 #define FSL_FEATURE_I2C_HAS_STOP_DETECT_INTERRUPT (1)
mbed_official 146:f64d43ff0c18 133 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]).*/
mbed_official 146:f64d43ff0c18 134 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
mbed_official 146:f64d43ff0c18 135 /* @brief Maximum width of the glitch filter in number of bus clocks.*/
mbed_official 146:f64d43ff0c18 136 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (31)
mbed_official 146:f64d43ff0c18 137 /* @brief Has control of the drive capability of the I2C pins.*/
mbed_official 146:f64d43ff0c18 138 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
mbed_official 146:f64d43ff0c18 139 #else
mbed_official 146:f64d43ff0c18 140 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 141 #endif
mbed_official 146:f64d43ff0c18 142
mbed_official 146:f64d43ff0c18 143 #endif /* __FSL_I2C_FEATURES_H__*/
mbed_official 146:f64d43ff0c18 144 /*******************************************************************************
mbed_official 146:f64d43ff0c18 145 * EOF
mbed_official 146:f64d43ff0c18 146 ******************************************************************************/
mbed_official 146:f64d43ff0c18 147