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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/edma/fsl_edma_features.h@146:f64d43ff0c18
- Child:
- 324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
| mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
| mbed_official | 146:f64d43ff0c18 | 4 | * |
| mbed_official | 146:f64d43ff0c18 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 146:f64d43ff0c18 | 6 | * are permitted provided that the following conditions are met: |
| mbed_official | 146:f64d43ff0c18 | 7 | * |
| mbed_official | 146:f64d43ff0c18 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 146:f64d43ff0c18 | 9 | * of conditions and the following disclaimer. |
| mbed_official | 146:f64d43ff0c18 | 10 | * |
| mbed_official | 146:f64d43ff0c18 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 146:f64d43ff0c18 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 146:f64d43ff0c18 | 13 | * other materials provided with the distribution. |
| mbed_official | 146:f64d43ff0c18 | 14 | * |
| mbed_official | 146:f64d43ff0c18 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 146:f64d43ff0c18 | 16 | * contributors may be used to endorse or promote products derived from this |
| mbed_official | 146:f64d43ff0c18 | 17 | * software without specific prior written permission. |
| mbed_official | 146:f64d43ff0c18 | 18 | * |
| mbed_official | 146:f64d43ff0c18 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 146:f64d43ff0c18 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 146:f64d43ff0c18 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 146:f64d43ff0c18 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 146:f64d43ff0c18 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 146:f64d43ff0c18 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 146:f64d43ff0c18 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 146:f64d43ff0c18 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 146:f64d43ff0c18 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 146:f64d43ff0c18 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 146:f64d43ff0c18 | 29 | */ |
| mbed_official | 146:f64d43ff0c18 | 30 | #if !defined(__FSL_DMA_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 31 | #define __FSL_DMA_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 32 | |
| mbed_official | 146:f64d43ff0c18 | 33 | #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \ |
| mbed_official | 146:f64d43ff0c18 | 34 | defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 35 | defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \ |
| mbed_official | 146:f64d43ff0c18 | 36 | defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \ |
| mbed_official | 146:f64d43ff0c18 | 37 | defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 38 | defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \ |
| mbed_official | 146:f64d43ff0c18 | 39 | defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \ |
| mbed_official | 146:f64d43ff0c18 | 40 | defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) |
| mbed_official | 146:f64d43ff0c18 | 41 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 42 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) |
| mbed_official | 146:f64d43ff0c18 | 43 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 44 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) |
| mbed_official | 146:f64d43ff0c18 | 45 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 46 | #define FSL_FEATURE_DMA_IS_EDMA (1) |
| mbed_official | 146:f64d43ff0c18 | 47 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 48 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1) |
| mbed_official | 146:f64d43ff0c18 | 49 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 50 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) |
| mbed_official | 146:f64d43ff0c18 | 51 | #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \ |
| mbed_official | 146:f64d43ff0c18 | 52 | defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \ |
| mbed_official | 146:f64d43ff0c18 | 53 | defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12) |
| mbed_official | 146:f64d43ff0c18 | 54 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 55 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (16) |
| mbed_official | 146:f64d43ff0c18 | 56 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 57 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) |
| mbed_official | 146:f64d43ff0c18 | 58 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 59 | #define FSL_FEATURE_DMA_IS_EDMA (1) |
| mbed_official | 146:f64d43ff0c18 | 60 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 61 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1) |
| mbed_official | 146:f64d43ff0c18 | 62 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 63 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) |
| mbed_official | 146:f64d43ff0c18 | 64 | #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 65 | defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 66 | defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) |
| mbed_official | 146:f64d43ff0c18 | 67 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 68 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (16) |
| mbed_official | 146:f64d43ff0c18 | 69 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 70 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16) |
| mbed_official | 146:f64d43ff0c18 | 71 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 72 | #define FSL_FEATURE_DMA_IS_EDMA (1) |
| mbed_official | 146:f64d43ff0c18 | 73 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 74 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1) |
| mbed_official | 146:f64d43ff0c18 | 75 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 76 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) |
| mbed_official | 146:f64d43ff0c18 | 77 | #elif defined(CPU_MK65FN2M0VMF18) || defined(CPU_MK65FX1M0VMF18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) |
| mbed_official | 146:f64d43ff0c18 | 78 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 79 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (32) |
| mbed_official | 146:f64d43ff0c18 | 80 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 81 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) |
| mbed_official | 146:f64d43ff0c18 | 82 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 83 | #define FSL_FEATURE_DMA_IS_EDMA (1) |
| mbed_official | 146:f64d43ff0c18 | 84 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 85 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2) |
| mbed_official | 146:f64d43ff0c18 | 86 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 87 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) |
| mbed_official | 146:f64d43ff0c18 | 88 | #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 146:f64d43ff0c18 | 89 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 146:f64d43ff0c18 | 90 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 91 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (32) |
| mbed_official | 146:f64d43ff0c18 | 92 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 93 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32) |
| mbed_official | 146:f64d43ff0c18 | 94 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 95 | #define FSL_FEATURE_DMA_IS_EDMA (1) |
| mbed_official | 146:f64d43ff0c18 | 96 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 97 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2) |
| mbed_official | 146:f64d43ff0c18 | 98 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 99 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) |
| mbed_official | 146:f64d43ff0c18 | 100 | #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \ |
| mbed_official | 146:f64d43ff0c18 | 101 | defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \ |
| mbed_official | 146:f64d43ff0c18 | 102 | defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \ |
| mbed_official | 146:f64d43ff0c18 | 103 | defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \ |
| mbed_official | 146:f64d43ff0c18 | 104 | defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 105 | defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \ |
| mbed_official | 146:f64d43ff0c18 | 106 | defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \ |
| mbed_official | 146:f64d43ff0c18 | 107 | defined(CPU_MKL46Z256VMC4) |
| mbed_official | 146:f64d43ff0c18 | 108 | /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 109 | #define FSL_FEATURE_DMA_MODULE_CHANNEL (4) |
| mbed_official | 146:f64d43ff0c18 | 110 | /* @brief Total number of DMA channels on all modules.*/ |
| mbed_official | 146:f64d43ff0c18 | 111 | #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4) |
| mbed_official | 146:f64d43ff0c18 | 112 | /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/ |
| mbed_official | 146:f64d43ff0c18 | 113 | #define FSL_FEATURE_DMA_IS_EDMA (0) |
| mbed_official | 146:f64d43ff0c18 | 114 | /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 115 | #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (0) |
| mbed_official | 146:f64d43ff0c18 | 116 | /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/ |
| mbed_official | 146:f64d43ff0c18 | 117 | #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) |
| mbed_official | 146:f64d43ff0c18 | 118 | #else |
| mbed_official | 146:f64d43ff0c18 | 119 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 120 | #endif |
| mbed_official | 146:f64d43ff0c18 | 121 | |
| mbed_official | 146:f64d43ff0c18 | 122 | #endif /* __FSL_DMA_FEATURES_H__*/ |
| mbed_official | 146:f64d43ff0c18 | 123 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 124 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 125 | ******************************************************************************/ |
| mbed_official | 146:f64d43ff0c18 | 126 |
