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Last commit 20 Feb 2019 by 
mbed official
targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/can/fsl_flexcan_features.h@149:1fb5f62b92bd, 2014-04-03 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Apr 03 11:45:06 2014 +0100
- Revision:
- 149:1fb5f62b92bd
- Parent:
- targets/hal/TARGET_Freescale/TARGET_KSDK_MCUS/TARGET_KSDK_CODE/hal/can/fsl_flexcan_features.h@146:f64d43ff0c18
- Child:
- 324:406fd2029f23
Synchronized with git revision 220c0bb39ceee40016e1e86350c058963d01ed42
Full URL: https://github.com/mbedmicro/mbed/commit/220c0bb39ceee40016e1e86350c058963d01ed42/
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 146:f64d43ff0c18 | 1 | /* |
| mbed_official | 146:f64d43ff0c18 | 2 | * Copyright (c) 2014, Freescale Semiconductor, Inc. |
| mbed_official | 146:f64d43ff0c18 | 3 | * All rights reserved. |
| mbed_official | 146:f64d43ff0c18 | 4 | * |
| mbed_official | 146:f64d43ff0c18 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 146:f64d43ff0c18 | 6 | * are permitted provided that the following conditions are met: |
| mbed_official | 146:f64d43ff0c18 | 7 | * |
| mbed_official | 146:f64d43ff0c18 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
| mbed_official | 146:f64d43ff0c18 | 9 | * of conditions and the following disclaimer. |
| mbed_official | 146:f64d43ff0c18 | 10 | * |
| mbed_official | 146:f64d43ff0c18 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
| mbed_official | 146:f64d43ff0c18 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
| mbed_official | 146:f64d43ff0c18 | 13 | * other materials provided with the distribution. |
| mbed_official | 146:f64d43ff0c18 | 14 | * |
| mbed_official | 146:f64d43ff0c18 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
| mbed_official | 146:f64d43ff0c18 | 16 | * contributors may be used to endorse or promote products derived from this |
| mbed_official | 146:f64d43ff0c18 | 17 | * software without specific prior written permission. |
| mbed_official | 146:f64d43ff0c18 | 18 | * |
| mbed_official | 146:f64d43ff0c18 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| mbed_official | 146:f64d43ff0c18 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| mbed_official | 146:f64d43ff0c18 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 146:f64d43ff0c18 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| mbed_official | 146:f64d43ff0c18 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| mbed_official | 146:f64d43ff0c18 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| mbed_official | 146:f64d43ff0c18 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| mbed_official | 146:f64d43ff0c18 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| mbed_official | 146:f64d43ff0c18 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| mbed_official | 146:f64d43ff0c18 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 146:f64d43ff0c18 | 29 | */ |
| mbed_official | 146:f64d43ff0c18 | 30 | #if !defined(__FSL_CAN_FEATURES_H__) |
| mbed_official | 146:f64d43ff0c18 | 31 | #define __FSL_CAN_FEATURES_H__ |
| mbed_official | 146:f64d43ff0c18 | 32 | |
| mbed_official | 146:f64d43ff0c18 | 33 | #if defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \ |
| mbed_official | 146:f64d43ff0c18 | 34 | defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \ |
| mbed_official | 146:f64d43ff0c18 | 35 | defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || \ |
| mbed_official | 146:f64d43ff0c18 | 36 | defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || \ |
| mbed_official | 146:f64d43ff0c18 | 37 | defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18) |
| mbed_official | 146:f64d43ff0c18 | 38 | /* @brief Message buffer size*/ |
| mbed_official | 146:f64d43ff0c18 | 39 | #define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) |
| mbed_official | 146:f64d43ff0c18 | 40 | /* @brief Has doze mode support (register bit field MCR[DOZE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 41 | #define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 42 | /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/ |
| mbed_official | 146:f64d43ff0c18 | 43 | #define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (1) |
| mbed_official | 146:f64d43ff0c18 | 44 | /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/ |
| mbed_official | 146:f64d43ff0c18 | 45 | #define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (0) |
| mbed_official | 146:f64d43ff0c18 | 46 | /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/ |
| mbed_official | 146:f64d43ff0c18 | 47 | #define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (1) |
| mbed_official | 146:f64d43ff0c18 | 48 | #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
| mbed_official | 146:f64d43ff0c18 | 49 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) |
| mbed_official | 146:f64d43ff0c18 | 50 | /* @brief Message buffer size*/ |
| mbed_official | 146:f64d43ff0c18 | 51 | #define FSL_FEATURE_CAN_HAS_MESSAGE_BUFFER_MAX_NUMBER (16) |
| mbed_official | 146:f64d43ff0c18 | 52 | /* @brief Has doze mode support (register bit field MCR[DOZE]).*/ |
| mbed_official | 146:f64d43ff0c18 | 53 | #define FSL_FEATURE_CAN_HAS_DOZE_MODE_SUPPORT (0) |
| mbed_official | 146:f64d43ff0c18 | 54 | /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]).*/ |
| mbed_official | 146:f64d43ff0c18 | 55 | #define FSL_FEATURE_CAN_HAS_GLITCH_FILTER (0) |
| mbed_official | 146:f64d43ff0c18 | 56 | /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2).*/ |
| mbed_official | 146:f64d43ff0c18 | 57 | #define FSL_FEATURE_CAN_HAS_EXTENDED_FLAG_REGISTER (1) |
| mbed_official | 146:f64d43ff0c18 | 58 | /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]).*/ |
| mbed_official | 146:f64d43ff0c18 | 59 | #define FSL_FEATURE_CAN_HAS_SEPARATE_BUFFER_0_FLAG (0) |
| mbed_official | 146:f64d43ff0c18 | 60 | #else |
| mbed_official | 146:f64d43ff0c18 | 61 | #error "No valid CPU defined!" |
| mbed_official | 146:f64d43ff0c18 | 62 | #endif |
| mbed_official | 146:f64d43ff0c18 | 63 | |
| mbed_official | 146:f64d43ff0c18 | 64 | #endif /* __FSL_CAN_FEATURES_H__*/ |
| mbed_official | 146:f64d43ff0c18 | 65 | /******************************************************************************* |
| mbed_official | 146:f64d43ff0c18 | 66 | * EOF |
| mbed_official | 146:f64d43ff0c18 | 67 | ******************************************************************************/ |
| mbed_official | 146:f64d43ff0c18 | 68 |
